National Instruments AT-MIO-16D Owners Manual

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AT-MIO-16D

User Manual

Multifunction I/O Board for the PC AT

March 1995 Edition

Part Number 320489-01

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National Instruments Corporate Headquarters

6504 Bridge Point Parkway Austin, TX 78730-5039 (512) 794-0100 Technical support fax: (800) 328-2203

(512) 794-5678

Branch Offices:

Australia (03) 879 9422, Austria (0662) 435986, Belgium 02/757.00.20, Canada (Ontario) (519) 622-9310, Canada (Québec) (514) 694-8521, Denmark 45 76 26 00, Finland (90) 527 2321, France (1) 48 14 24 24, Germany 089/741 31 30, Italy 02/48301892, Japan (03) 3788-1921, Mexico 95 800 010 0793, Netherlands 03480-33466, Norway 32-84 84 00, Singapore 2265886, Spain (91) 640 0085, Sweden 08-730 49 70, Switzerland 056/20 51 51, Taiwan 02 377 1200, U.K. 0635 523545

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Limited Warranty

The AT-MIO-16D is warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.

The media on which you receive National Instruments software are warranted not to fail to execute programming instructions, due to defects in materials and workmanship, for a period of 90 days from date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period. National Instruments does not warrant that the operation of the software shall be uninterrupted or error free.

A Return Material Authorization (RMA) number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work. National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty.

National Instruments believes that the information in this manual is accurate. The document has been carefully reviewed for technical accuracy. In the event that technical or typographical errors exist, National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition. The reader should consult National Instruments if errors are suspected. In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it.

EXCEPT AS SPECIFIED HEREIN, NATIONAL INSTRUMENTS MAKES NO WARRANTIES, EXPRESS OR IMPLIED,

AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OF

NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA, PROFITS,

USE OF PRODUCTS, OR INCIDENTAL OR CONSEQUENTIAL DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY THEREOF

whether in contract or tort, including negligence. Any action against National Instruments must be brought within one year after the cause of action accrues. National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control. The warranty provided herein does not cover damages, defects, malfunctions, or service failures caused by owner's failure to follow the National Instruments installation, operation, or maintenance instructions; owner's modification of the product; owner's abuse, misuse, or negligent acts; and power failure or surges, fire, flood, accident, actions of third parties, or other events outside reasonable control.

. CUSTOMER'S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART

NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER.

. This limitation of the liability of National Instruments will apply regardless of the form of action,

Copyright

Under the copyright laws, this publication may not be reproduced or transmitted in any form, electronic or mechanical, including photocopying, recording, storing in an information retrieval system, or translating, in whole or in part, without the prior written consent of National Instruments Corporation.

Trademarks

LabVIEW®, NI-DAQ®, and RTSI® are trademarks of National Instruments Corporation.

Product and company names listed are trademarks or trade names of their respective companies.

Page 4

WARNING REGARDING MEDICAL AND CLINICAL USE

OF NATIONAL INSTRUMENTS PRODUCTS

National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans. Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure, or by errors on the part of the user or application designer. Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel, and all traditional medical safeguards, equipment, and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used. National Instruments products are NOT intended to be a substitute for any form of established process, procedure, or equipment used to monitor or safeguard human health and safety in medical or clinical treatment.

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Preface

This manual describes the electrical and mechanical aspects of the AT-MIO-16D and contains information concerning its operation and programming. The AT-MIO-16D, a member of the National Instruments AT Series of expansion boards for the IBM PC AT and compatible computers, combines the functionality of two popular National Instruments boards, the AT-MIO-16 and the PC-DIO-24. The AT-MIO-16D contains two logical sections–the MIO-16 circuitry and the DIO-24 circuitry. The MIO-16 circuitry contains a 12-bit ADC with up to 16 analog inputs, two 12-bit DACs with voltage outputs, eight lines of transistor-transistor logic (TTL) compatible digital I/O, and three 16-bit counter/timer channels for timing I/O. The DIO24 circuitry is a 24-bit parallel, digital I/O interface based on an 82C55A programmable peripheral interface (PPI). If you require signal conditioning or additional analog inputs, you can use the SCXI signal conditioning modules, the SCXI multiplexer products, or the AMUX-64T multiplexer board.

Organization of This Manual

The AT-MIO-16D User Manual is organized as follows:

• Chapter 1, Introduction, describes the AT-MIO-16D; lists the contents of your AT-MIO-16D kit, the optional software, and optional equipment; and explains how to unpack the AT-MIO-16D.

• Chapter 2, Configuration and Installation, describes the AT-MIO-16D jumper configuration, installation of the AT-MIO-16D board into the PC, signal connections to the AT-MIO-16D board, cable wiring, and handshake timing diagrams for the DIO-24 circuitry of the AT-MIO-16D.

• Chapter 3, Theory of Operation, contains a functional overview of the AT-MIO-16D and explains the operation of each functional unit making up the AT-MIO-16D.

• Chapter 4, Programming, discusses the programming of the AT-MIO-16D. Included in this chapter are the AT-MIO-16D register address map, a detailed register description, and a functional programming description.

• Chapter 5, Calibration Procedures, discusses the calibration procedures for the AT-MIO-16D analog input and analog output circuitry.

• Appendix A, Specifications, lists the specifications for the AT-MIO-16D.

• Appendix B, MIO-16 I/O Connector, describes the pinout and signal names for the MIO-16 50-pin I/O connector of the AT-MIO-16D.

• Appendix C, DIO-24 I/O Connector, describes the pinout and signal names for the DIO-24 50-pin I/O connector of the AT-MIO-16D.

• Appendix D, AT-MIO-16D I/O Connector, describes the pinout and signal names for the AT-MIO-16D 100-pin I/O connector.

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Preface

• Appendix E, AMD Am9513A Data Sheet, contains the manufacturer data sheet for the Am9513A System Controller integrated circuit (Advanced Micro Devices, Inc.). This device is used on the AT-MIO-16D.

• Appendix F, Oki MSM82C55A Data Sheet, contains the manufacturer data sheet for the MSM82C55A CMOS Programmable Peripheral Interface (Oki Semiconductor). This device is used on the AT-MIO-16D.

• Appendix G, Customer Communication, contains forms for you to complete to facilitate communication with National Instruments concerning our products.

• The Index alphabetically lists topics covered in this manual, including the page where the topic can be found.

Conventions Used in This Manual

The following conventions are used to distinguish elements of text throughout this manual:

italic Italic text denotes emphasis, a cross reference, or an introduction to a key

concept.

PC PC refers to the IBM PC AT and compatible computers.

Abbreviations

The following metric system prefixes are used with abbreviations for units of measure in this manual:

Prefix Meaning Value

p- pico- 10 n- nano- 10

µ- micro- 10

m- milli- 10 k- kilo- 10 M- mega- 10 G- giga- 10

The following abbreviations are used in this manual:

A amperes dB decibels ft feet hex hexadecimal Hz hertz kbytes 1,000 bytes ksamples 1,000 samples M megabytes of memory

-12

-9

-6

-3

AT-MIO-16D User Manual vi © National Instruments Corporation

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Abbreviations (continued)

m meters

Ω ohms

ppm parts per million sec seconds V volts Vrms volts, root mean square

Acronyms

The following acronyms are used in this manual:

AC alternating current A/D analog-to-digital ADC A/D converter D/A digital-to-analog DAC D/A converter DIP dual inline package DMA direct memory access FIFO first-in-first-out I/O input/output LS low-power Schottky LSB least significant bit MSB most significant bit PPI programmable peripheral interface RTSI Real-Time System Integration SSR solid-state relays TTL transistor-transistor logic VDC volts direct current

Preface

Customer Communication

National Instruments wants to receive your comments on our products and manuals. We are interested in the applications you develop with our products, and we want to help if you have problems with them. To make it easy for you to contact us, this manual contains comment and configuration forms for you to complete. These forms are in Appendix G, Customer

Communication, at the end of this manual.

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Chapter 1 Introduction

What Your Kit Should Contain......................................................................................1-3

Optional Software ..........................................................................................................1-4

Optional Equipment.......................................................................................................1-5

Unpacking......................................................................................................................1-7

Chapter 2 Configuration and Installation

Board Configuration ......................................................................................................2-1

AT Bus Interface............................................................................................................2-1

Base I/O Address Selection............................................................................................2-3

DMA Channel Selection................................................................................................2-5

Interrupt Selection..........................................................................................................2-7

Analog I/O Jumper Settings...........................................................................................2-8

Analog Input Configuration...........................................................................................2-10

Analog Output Configuration ........................................................................................2-15

RTSI Bus Clock Selection .............................................................................................2-18

Hardware Installation.....................................................................................................2-20

Signal Connections ........................................................................................................2-20

..........................................................................................................................1-1

Custom Cables ...................................................................................................1-6

.......................................................................................2-1

DIO-24 Circuitry Interrupt Enable Settings....................................................... 2-8

Input Mode.........................................................................................................2-10

DIFF Analog Input (Eight Channels, Factory Setting)..........................2-10

RSE Analog Input (16 Channels)...........................................................2-11

NRSE Analog Input (16 Channels)........................................................2-12

Analog Input Polarity and Range.......................................................................2-12

Considerations for Selecting Analog Input Ranges ...............................2-14

Analog Output Reference Selection...................................................................2-15

External Reference Selection................................................................. 2-15

Internal Reference Selection (Factory Setting)......................................2-15

Analog Output Polarity Selection ......................................................................2-16

Bipolar Output Selection (Factory Setting) ...........................................2-16

Straight Binary Mode.................................................................2-17

Two's Complement Mode (Factory Setting).............................. 2-17

Unipolar Output Selection .....................................................................2-18

AT-MIO-16D I/O Connector Pin Description...................................................2-21

MIO-16 I/O Connector Pin Description.............................................................2-22

MIO-16 Signal Connection Descriptions...........................................................2-23

Analog Input Signal Connections ......................................................................2-25

Types of Signal Sources.....................................................................................2-26

Floating Signal Sources .........................................................................2-26

Ground-Referenced Signal Sources....................................................... 2-27

Input Configurations ..........................................................................................2-27

Differential Connection Considerations (DIFF Configuration)............. 2-27

Differential Connections for Grounded Signal Sources ........................2-28

Differential Connections for Floating Signal Sources ...........................2-29

Single-Ended Connection Considerations .............................................2-30

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Contents

Single-Ended Connections for Floating Signal Sources (RSE

Configuration)........................................................................................2-30

Single-Ended Connections for Grounded Signal Sources (NRSE

Configuration)........................................................................................2-31

Common-Mode Signal Rejection Considerations..................................2-32

Analog Output Signal Connections....................................................................2-33

Digital I/O Signal Connections..........................................................................2-34

Power Connections ............................................................................................2-36

Timing Connections...........................................................................................2-36

Data Acquisition Timing Connections...................................................2-36

General-Purpose Timing Signal Connections........................................ 2-38

DIO-24 I/O Connector Pin Description .............................................................2-43

DIO-24 Signal Connection Descriptions ...........................................................2-44

Power Connections ................................................................................2-44

Port C Pin Assignments .........................................................................2-44

Timing Specifications ........................................................................................2-45

DIO-24 Mode 1 Input Timing................................................................2-47

DIO-24 Mode 1 Output Timing.............................................................2-48

DIO-24 Mode 2 Bidirectional Timing ...................................................2-49

Cabling and Field Wiring...............................................................................................2-50

Field Wiring Considerations..............................................................................2-50

MIO-16 Cabling Considerations........................................................................2-50

DIO-24 Cabling Considerations.........................................................................2-51

Chapter 3 Theory of Operation

MIO-16 Functional Overview........................................................................................3-1

PC AT I/O Channel Interface Circuitry .........................................................................3-2

Analog Input and Data Acquisition Circuitry................................................................ 3-4

Analog Input Circuitry.......................................................................................3-6

Analog Input Multiplexers.....................................................................3-6

Analog Input Mode Selection ................................................................3-6

The Instrumentation Amplifier ..............................................................3-6

Channel Selection Circuitry...................................................................3-6

A/D Converter........................................................................................3-7

ADC FIFO Buffer.................................................................................. 3-7

Data Acquisition Timing Circuitry ....................................................................3-7

Single Conversions ................................................................................ 3-8

Sample-Interval Timer ...........................................................................3-8

Sample Counter......................................................................................3-8

Single-Channel Data Acquisition...........................................................3-9

Multiple-Channel (Scanned) Data Acquisition...................................... 3-9

Data Acquisition Rates...........................................................................3-9

Analog Output Circuitry ................................................................................................3-10

Analog Output Range.........................................................................................3-11

Analog Output Data Coding ..............................................................................3-11

MIO-16 Digital I/O Circuitry.........................................................................................3-11

Timing I/O Circuitry......................................................................................................3-13

RTSI Bus Interface Circuitry .........................................................................................3-15

DIO-24 Functional Overview ........................................................................................3-17

DIO-24 Interrupt Control Circuitry................................................................................3-17

DIO-24 Circuitry I/O Connector.................................................................................... 3-18

..........................................................................................................3-1

AT-MIO-16D User Manual x © National Instruments Corporation

Page 10

82C55A Programmable Peripheral Interface.................................................................3-18

82C55A Modes of Operation.............................................................................3-18

Chapter 4 Programming

Register Map..................................................................................................................4-1

Configuration and Status Register Group..........................................................4-3

The Event Strobe Register Group ......................................................................4-11

Analog Output Register Group ..........................................................................4-16

Analog Input Register Group.............................................................................4-20

Am9513A Counter/Timer Register Group ........................................................4-26

MIO-16 Digital I/O Register Group...................................................................4-30

The RTSI Switch Register Group......................................................................4-33

DIO-24 Register Group......................................................................................4-36

MIO-16 Programming Considerations...........................................................................4-41

Initializing the MIO-16 Circuitry of the AT-MIO-16D Board.......................... 4-41

Contents

Mode 0 ...................................................................................................3-18

Mode 1 ...................................................................................................3-19

Mode 2 ...................................................................................................3-19

Single Bit Set/Reset Feature ..................................................................3-19

........................................................................................................................4-1

Command Register 1..............................................................................4-4

Status Register........................................................................................4-6

Command Register 2..............................................................................4-9

Start Convert Register............................................................................4-12

Start DAQ Register................................................................................4-13

A/D Clear Register.................................................................................4-14

External Strobe Register ........................................................................4-15

DAC0 Register.......................................................................................4-17

DAC1 Register.......................................................................................4-18

INT2CLR Register.................................................................................4-19

Mux-Counter Register............................................................................4-21

Mux-Gain Register.................................................................................4-22

A/D FIFO Register.................................................................................4-24

DMA TC INT Clear Register.................................................................4-25

Am9513A Data Register........................................................................4-27

Am9513A Command Register...............................................................4-28

Am9513A Status Register......................................................................4-29

MIO-16 Digital Input Register...............................................................4-31

MIO-16 Digital Output Register............................................................4-32

RTSI Switch Shift Register....................................................................4-34

RTSI Switch Strobe Register.................................................................4-35

DIO-24 PORTA Register.......................................................................4-37

DIO-24 PORTB Register.......................................................................4-38

DIO-24 PORTC Register.......................................................................4-39

DIO-24 CNFG Register .........................................................................4-40

Initializing the Am9513A ......................................................................4-42

Initializing the Analog Output Circuitry................................................4-43

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Contents

Programming the Analog Input Circuitry ..........................................................4-43

A/D FIFO Output Binary Formats.........................................................4-44

Clearing the Analog Input Circuitry ......................................................4-45

Programming Multiple A/D Conversions on a Single Input Channel ...............4-46

External Timing Considerations for Multiple A/D Conversions.......................4-51

Pretriggering with the STOP TRIG Signal ............................................4-51

Controlling Multiple A/D Conversions with the EXTCONV* Signal ..4-55

Programming Multiple A/D Conversions with Channel Scanning....................4-57

Multiple A/D Conversions with Continuous Channel Scanning

(Round Robin)........................................................................................4-57

Multiple A/D Conversions with Interval Channel Scanning

(Pseudo-Simultaneous) ..........................................................................4-62

External Timing Considerations for Scanned Data Acquisition............4-68

Resetting the Hardware after a Data Acquisition Operation..............................4-68

Resetting Counter 2................................................................................4-69

Resetting Counter 3................................................................................4-69

Resetting Counter 4................................................................................4-70

Resetting Counter 5................................................................................4-70

Programming the Analog Output Circuitry .......................................................4-71

Programming the MIO-16 Digital I/O Circuitry................................................ 4-72

Programming the Am9513A Counter/Timer .....................................................4-73

RTSI Bus Trigger Line Programming Considerations ......................................4-73

AT-MIO-16D RTSI Signal Connection Considerations........................4-74

Programming the RTSI Switch..............................................................4-75

Programming DMA Operations.........................................................................4-76

Interrupt Programming.......................................................................................4-77

DIO-24 Circuitry Programming Considerations............................................................4-78

DIO-24 Circuitry Register Descriptions ............................................................4-78

82C55A Modes of Operation.............................................................................4-80

Mode 0–Basic I/O..................................................................................4-80

Mode 0 Programming Example.................................................4-81

Mode 1–Strobed Input ...........................................................................4-82

Mode 1 Input Programming Example........................................4-84

Mode 1–Strobed Output.........................................................................4-84

Mode 1 Output Programming Example.....................................4-86

Mode 2–Bidirectional Bus .....................................................................4-87

Mode 2 Programming Example.................................................4-88

Single Bit Set/Reset Feature ..................................................................4-89

Interrupt Programming Examples......................................................................4-89

DIO-24 Interrupt Handling ............................................................................................4-90

Chapter 5 Calibration Procedures

Calibration Equipment Requirements............................................................................5-1

Calibration Trimpots......................................................................................................5-2

Analog Input Calibration ...............................................................................................5-3

Board Configuration ..........................................................................................5-4

Bipolar Input Calibration Procedure.................................................................. 5-4

Unipolar Input Calibration Procedure................................................................ 5-5

Analog Output Calibration.............................................................................................5-6

Board Configuration ..........................................................................................5-7

Bipolar Output Calibration Procedure ...............................................................5-7

Unipolar Output Calibration Procedure .............................................................5-8

AT-MIO-16D User Manual xii © National Instruments Corporation

.....................................................................................................5-1

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Appendix A Specifications

MIO-16 Circuitry Specifications ...................................................................................A-1

Analog Input ......................................................................................................A-1

Analog Data Acquisition Rates..........................................................................A-3

Analog Output....................................................................................................A-4

Digital I/O (MIO-16 I/O Connector only) .........................................................A-5

Timing I/O..........................................................................................................A-5

DIO-24 Circuitry Specifications ....................................................................................A-5

I/O Signals Rating..............................................................................................A-5

Input Signal Specifications ................................................................................A-5

Output Signal Specifications..............................................................................A-6

Transfer Rates ................................................................................................................A-6

Power Requirement (from PC AT I/O Channel) ...........................................................A-6

Physical.......................................................................................................................... A-6

Operating Environment..................................................................................................A-6

Storage Environment......................................................................................................A-6

Contents

........................................................................................................................A-1

Explanation of Analog Input Specifications ..........................................A-2

Single-Channel Acquisition Rates .........................................................A-3

Multiple-Channel Scanning Acquisition Rates......................................A-3

Explanation of Analog Output Specifications .......................................A-4

Appendix B MIO-16 I/O Connector

MIO-16 Signal Connection Descriptions.......................................................................B-2

......................................................................................................B-1

Appendix C DIO-24 I/O Connector

DIO-24 Signal Connection Descriptions .......................................................................C-2

.......................................................................................................C-1

Appendix D AT-MIO-16D I/O Connector

..........................................................................................D-1

Appendix E AMD Am9513A Data Sheet

.............................................................................................E-1

Appendix F Oki MSM82C55A Data Sheet

.........................................................................................F-1

Appendix G Customer Communication

...............................................................................................G-1

Index ..................................................................................................................................Index-1

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Contents

Figures

Figure 1-1. AT-MIO-16D Interface Board..........................................................................1-2

Figure 1-2. AT-MIO-16D Cable Assembly ........................................................................1-6

Figure 2-1. Parts Locator Diagram......................................................................................2-2

Figure 2-2. Example Base I/O Address Switch Settings.....................................................2-4

Figure 2-3. DMA Jumper Settings for DMA Channels 6 and 7 (Factory Setting)..............2-6

Figure 2-4. DMA Jumper Settings for DMA Channel 6 Only............................................2-6

Figure 2-5. DMA Jumper Settings for Disabling DMA Transfers......................................2-7

Figure 2-6. Factory Interrupt Jumper Settings IRQ5 (DIO-24) and IRQ10 (MIO-16)....... 2-7

Figure 2-7. Interrupt Jumper Setting for Disabling Interrupts ............................................2-8

Figure 2-8. Jumper Settings–PC6, PC4, PC2, and N/C.......................................................2-8

Figure 2-9. DIFF Analog Input Configuration (Factory Setting)........................................2-11

Figure 2-10. RSE Analog Input Configuration .....................................................................2-11

Figure 2-11. NRSE Analog Input Configuration ..................................................................2-12

Figure 2-12. 0 to +10 V Input Configuration ........................................................................2-13

Figure 2-13. -5 to +5 V Input Configuration......................................................................... 2-13

Figure 2-14. Factory -10 to +10 V Analog Input Configuration........................................... 2-13

Figure 2-15. External Reference Configuration ....................................................................2-15

Figure 2-16. Factory Internal Reference Configuration........................................................ 2-16

Figure 2-17. Factory Bipolar Output Configuration..............................................................2-16

Figure 2-18. Straight Binary Mode .......................................................................................2-17

Figure 2-19. Two's Complement Mode (Factory Setting).....................................................2-17

Figure 2-20. Unipolar Output Configuration.........................................................................2-18

Figure 2-21. Disconnect from RTSI Bus Clock; Use Onboard Oscillator

(Factory Setting)...............................................................................................2-19

Figure 2-22. Receive RTSI Bus Clock Signal.......................................................................2-19

Figure 2-23. Drive RTSI Bus Clock Signal with Onboard Oscillator...................................2-20

Figure 2-24. AT-MIO-16D I/O Connector Pin Assignments................................................2-21

Figure 2-25. MIO-16 I/O Connector Pin Assignments .........................................................2-22

Figure 2-26. AT-MIO-16D Instrumentation Amplifier.........................................................2-26

Figure 2-27. Differential Input Connections for Grounded Signal Sources..........................2-28

Figure 2-28. Differential Input Connections for Floating Sources........................................2-29

Figure 2-29. Single-Ended Input Connections for Floating Signal Sources .........................2-31

Figure 2-30. Single-Ended Input Connections for Grounded Signal Sources.......................2-32

Figure 2-31. Analog Output Connections .............................................................................2-34

Figure 2-32. Digital I/O Connections....................................................................................2-35

Figure 2-33. EXTSTROBE* Signal Timing .........................................................................2-36

Figure 2-34. EXTCONV* Signal Timing .............................................................................2-37

Figure 2-35. START TRIG* Signal Timing .........................................................................2-38

Figure 2-36. STOP TRIG Signal Timing ..............................................................................2-38

Figure 2-37. Event-Counting Application with External Switch Gating ..............................2-39

Figure 2-38. Frequency Measurement Application............................................................... 2-40

Figure 2-39. General-Purpose Timing Signals......................................................................2-41

Figure 2-40. DIO-24 I/O Connector Pin Assignments..........................................................2-43

Figure 3-1. AT-MIO-16D MIO-16 Circuitry Block Diagram.............................................3-1

Figure 3-2. PC AT I/O Channel Interface Circuitry Block Diagram ..................................3-3

Figure 3-3. Analog Input and Data Acquisition Circuitry Block Diagram .........................3-5

Figure 3-4. Analog Output Circuitry Block Diagram .........................................................3-10

Figure 3-5. Digital I/O Circuitry Block Diagram................................................................3-12

Figure 3-6. Timing I/O Circuitry Block Diagram ...............................................................3-13

AT-MIO-16D User Manual xiv © National Instruments Corporation

Page 14

Contents

Figure 3-7. Counter Block Diagram....................................................................................3-14

Figure 3-8. RTSI Bus Interface Circuitry Block Diagram ..................................................3-16

Figure 3-9. AT-MIO-16D DIO-24 Block Diagram.............................................................3-17

Figure 4-1. RTSI Switch Control Pattern............................................................................4-75

Figure 4-2. Control-Word Formats......................................................................................4-79

Figure 5-1. Calibration Trimpot Location Diagram............................................................ 5-2

Figure B-1. AT-MIO-16D MIO-16 I/O Connector..............................................................B-1

Figure C-1. AT-MIO-16D DIO-24 I/O Connector ..............................................................C-1

Figure D-1. AT-MIO-16D I/O Connector............................................................................D-1

Tables

Table 2-1. AT Bus Interface Factory Settings ...................................................................2-1

Table 2-2. Default Settings of Other National Instruments Products for the PC............... 2-3

Table 2-3. Switch Settings with Corresponding Base I/O Address and Base I/O

Address Space...................................................................................................2-5

Table 2-4. DMA Channels for the AT-MIO-16D..............................................................2-6

Table 2-5. Analog I/O Jumper Settings..............................................................................2-9

Table 2-6. Input Configurations Available for the AT-MIO-16D..................................... 2-10

Table 2-7. Configurations for Input Range and Input Polarity..........................................2-13

Table 2-8. Actual Range and Measurement Precision Versus Input Range Selection

and Gain............................................................................................................2-14

Table 2-9. Configurations for RTSI Bus Clock Selection .................................................2-19

Table 2-10. Recommended Input Configurations for Ground-Referenced and

Floating Signal Sources.................................................................................... 2-27

Table 2-11. Port C Signal Assignments...............................................................................2-45

Table 3-1. AT-MIO-16D Maximum Recommended Data Acquisition Rates................... 3-10

Table 4-1. AT-MIO-16D Register Map.............................................................................4-1

Table 4-2. Straight Binary Mode A/D Conversion Values................................................4-45

Table 4-3. Two's Complement Mode A/D Conversion Values .........................................4-45

Table 4-4. Multiple-Channel Data Acquisition Rates........................................................4-68

Table 4-5. Analog Output Voltage Versus Digital Code (Unipolar Mode)....................... 4-71

Table 4-6. Analog Output Voltage Versus Digital Code (Bipolar Mode).........................4-72

Table 4-7. RTSI Switch Signal Connections .....................................................................4-74

Table 4-8. Port C Set/Reset Control Words....................................................................... 4-80

Table 4-9. Mode 0 I/O Configurations...............................................................................4-81

Table 4-10. DIO-24 Interrupt Enable Signals for All Mode Combinations ........................4-91

Page 15

Chapter 1 Introduction

This chapter describes the AT-MIO-16D; lists the contents of your AT-MIO-16D kit, the optional software, and optional equipment; and explains how to unpack the AT-MIO-16D.

The AT-MIO-16D combines the functionality of two popular National Instruments boards, the AT-MIO-16 and the PC-DIO-24. The AT-MIO-16D contains two logical sections–the MIO-16 circuitry and the DIO-24 circuitry. Henceforth, we will refer to the entire board as the AT-MIO-16D, and to a particular logical part of the board as either the MIO-16 or DIO-24 circuitry. The MIO-16 circuitry contains a 12-bit ADC with up to 16 analog inputs, two 12-bit DACs with voltage outputs, eight lines of transistor-transistor logic (TTL) compatible digital I/O, and three 16-bit counter/timer channels for timing I/O. The DIO-24 circuitry is a 24-bit parallel, digital I/O interface based on an 82C55A programmable peripheral interface (PPI).

The MIO-16 circuitry of the AT-MIO-16D is a high-performance multifunction analog, digital, and timing I/O circuit for the PC. The AT-MIO-16D has a fast 12-bit ADC, 16 single-ended or eight differential channels (expandable with SCXI and the AMUX-64T), and programmable

gains of 1, 10, 100, and 500 or 1, 2, 4, and 8. The AT-MIO-16D has a 9-µsec converter,

guaranteed transfer rates of up to 100 ksamples/sec, and a 512-word A/D FIFO buffer to obtain the highest possible data acquisition rate. The AT-MIO-16D has internal or external A/D timing, two double-buffered multiplying 12-bit DACs, unipolar or bipolar voltage output, and an onboard DAC reference voltage of 10 V. The AT-MIO-16D also has onboard timers for waveform generation, eight digital I/O lines that can sink up to 24 mA of current, and three independent 16-bit counter/timers for frequency counting, event counting, and pulse output applications. The AT-MIO-16D has timer-generated interrupts, a high-performance RTSI bus interface with four triggers for system-level timing, and full PC AT I/O channel DMA capability.

The DIO-24 circuitry of the AT-MIO-16D is a 24-bit parallel, digital I/O interface for the PC. An 82C55A PPI controls the 24 bits of digital I/O. The 82C55A is very flexible and powerful when interfacing with peripheral equipment, can operate in either a unidirectional or bidirectional mode, and can generate interrupt request outputs. You can program the 82C55A for almost any 8-bit or 16-bit digital I/O application. The 100-pin connector of the AT-MIO16D breaks out into two standard 50-pin female connectors via a cable assembly. The pin assignments for these connectors are compatible with standard 24-channel digital I/O applications.

Figure 1-1 shows the AT-MIO-16D interface board.

Page 16

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Chapter 1 Introduction

With the AT-MIO-16D, the PC can serve as a digital I/O system controller for laboratory testing, production testing, and industrial process monitoring and control.

The AT-MIO-16D is interfaced to the National Instruments RTSI bus. With this bus, National Instruments AT Series boards can send timing signals to each other. The AT-MIO-16D can send signals from the onboard counter/timer to another board, or another board can control single and multiple A/D conversions on the AT-MIO-16D.

The AT-MIO-16D is available in two gain ranges. The AT-MIO-16DL-9 has software-programmable gain settings of 1, 10, 100, and 500 for low-level analog input signals. The AT-MIO-16DH-9 has software-programmable gain settings of 1, 2, 4, and 8 for high-level

analog input signals. The AT-MIO-16D contains an ADC with a 9-µsec conversion time, and is

capable of data acquisition rates of up to 100 kbytes/sec.

Detailed specifications for the AT-MIO-16D are listed in Appendix A, Specifications.

What Your Kit Should Contain

Each version of the AT-MIO-16D board has a different part number and kit part number, listed as follows.

Kit Name Kit Part Number Kit Component Board Part

Number

AT-MIO-16DL-9 776646-01 AT-MIO-16DL-9 board 181965-01

AT-MIO-16DH-9 776646-11 AT-MIO-16DH-9 board 181965-11

The board part number is printed on your board along the top edge on the component side. You can identify which version of the AT-MIO-16D board you have by looking up the part number in the preceding table.

In addition to the board, each version of the AT-MIO-16D kit contains the following components.

Kit Component Part Number

AT-MIO-16D User Manual

NI-DAQ software for DOS/Windows/LabWindows, with manuals

NI-DAQ Software Reference Manual for DOS/Windows/LabWindows NI-DAQ Function Reference Manual for DOS/Windows/LabWindows

320489-01 776250-01 320498-01 320499-01

If your kit is missing any of the components or if you received the wrong version, contact National Instruments.

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Introduction Chapter 1

Your AT-MIO-16D is shipped with the NI-DAQ software for DOS/Windows/LabWindows. NI-DAQ has a library of functions that can be called from your application programming environment. These functions include routines for analog input (A/D conversion), buffered data acquisition (high-speed A/D conversion), analog output (D/A conversion), waveform generation, digital I/O, counter/timer, SCXI, RTSI, and self-calibration. NI-DAQ maintains a consistent software interface among its different versions so you can switch between platforms with minimal modifications to your code. NI-DAQ comes with language interfaces for Professional BASIC, Turbo Pascal, Turbo C, Turbo C++, Borland C++, and Microsoft C for DOS; and Visual Basic, Turbo Pascal, Microsoft C with SDK, and Borland C++ for Windows. NI-DAQ software is on high-density 5.25 in. and 3.5 in. diskettes.

Optional Software

This manual contains complete instructions for directly programming the AT-MIO-16D. Normally, however, you should not need to read the low-level programming details in the user manual because the NI-DAQ software package for controlling the AT-MIO-16D is included with the board. Using NI-DAQ is quicker and easier than and as flexible as using the low-level programming described in Chapter 4, Programming.

You can use the AT-MIO-16D with LabVIEW for Windows or LabWindows for DOS. LabVIEW and LabWindows are innovative program development software packages for data acquisistion and control applications. LabVIEW uses graphical programming, whereas LabWindows enhances Microsoft C and QuickBASIC. Both packages include extensive libraries for data acquisition, instrument control, data analysis, and graphical data presentation.

Part numbers for these software packages are listed in the following table.

Software Part Number

LabVIEW for Windows LabWindows

Standard package Advanced Analysis Library Standard package with the Advanced Analysis Library

776670-01

776473-01 776474-01 776475-01

AT-MIO-16D User Manual 1-4 © National Instruments Corporation

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Chapter 1 Introduction

Optional Equipment

Equipment Part Number

CB-100 I/O connector block

0.5-m cable

1.0-m cable

Type NB5 100-conductor ribbon cable

0.5-m cable

1.0-m cable

SCXI signal conditioning modules

SCXI-1100 32-channel differential multiplexer/amplifier SCXI-1120 8-channel isolated analog input SCXI-1121 4-channel isolated transducer amplifier with excitation SCXI-1140 8-channel simultaneously sampling differential amplifier SCXI-1180 feedthrough panel SCXI-1181 breadboard

AMUX-64T analog multiplexer board without cable

with 0.2-m ribbon cable with 0.5-m ribbon cable with 1.0-m ribbon cable with 2.0-m ribbon cable

AT Series RTSI bus cables for

2 boards 3 boards 4 boards 5 boards

Cable adapter board for signal conditioning

SC-2050 without cable SC-2051 without cable

SC-2060 optically isolated digital input board with conductor cable 0.2 m

0.4 m

SC-2061 optically isolated digital output board

with 26-conductor cable 0.2 m

0.4 m

SC-2062 electromechanical relay digital control board

with 26-conductor cable 0.2 m

0.4 m

General-purpose termination breadboard

SC-2070 without cable SC-2072 without cable

SC-2072D without cable BNC-2080 BNC adapter board without cable Digital signal conditioning modules

SSR Series mounting rack and 1.0 m cable

24-channel without cable

16-channel without cable

8-channel without cable

8-channel with SC-205X cable

776455-01 776455-02

181304-05 181304-10

776572-00 776572-20 776572-21 776572-40 776572-80 776572-81

776366-90 776366-02 776366-05 776366-10 776366-20

776249-02 776249-03 776249-04 776249-05

776335-90 776335-91

776336-00 776336-10

776336-01 776336-11

776336-02 776336-12

776358-90 776358-92 776358-192

776579-90

776290-924 776290-916 776290-908 776290-18

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Introduction Chapter 1

Custom Cables

The AT-MIO-16D I/O connector is a 100-pin male ribbon cable header. The manufacturer part number National Instruments uses for this header is as follows:

• Robinson Nugent (part number P50E-100P1-SR1-TG)

The mating connector for the board is a 100-position, polarized, ribbon socket connector. This connector breaks out into two 50-pin female connectors with 50-conductor ribbon cables via a cable assembly. National Instruments uses a keyed connector to prevent inadvertent upsidedown connection to the board. The recommended manufacturer part number for this mating connector is as follows:

• Robinson Nugent (part number P50E-100S-TG)

Figure 1-2 shows the AT-MIO-16D cable assembly.

MIO-16 50-pin I/O

Connector

AT-MIO-16D Board

AT-MIO-16D 100-pin

I/O Connector

DIO-24 50-pin I/O

Connector

Figure 1-2. AT-MIO-16D Cable Assembly

Recommended manufacturer part numbers for standard ribbon cable (50-conductor, 28 AWG, stranded) that can be used with the mating connector are as follows:

• Electronic Products Division/3M (part number 3365/50)

• T&B/Ansley Corporation (part number 171-50)

Recommended manufacturer part numbers for the 50-pin edge connector for connecting to a module rack with an edge connector are as follows:

• Electronic Products Division/3M (part number 3415-0001)

• T&B Ansley Corporation (part number 609-5015M)

AT-MIO-16D User Manual 1-6 © National Instruments Corporation

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Chapter 1 Introduction

You can plug a polarizing key into these edge connectors to prevent inadvertent upside-down connection to the I/O module rack. The location of this key varies from rack to rack. Consult the specification for the rack you intend to use for the location of any polarizing key. The recommended manufacturer part numbers for this polarizing key are as follows:

• Electronic Products Division/3M (part number 3439-2)

• T&B Ansley Corporation (part number 609-0005)

Unpacking

Your AT-MIO-16D board is shipped in an antistatic plastic bag to prevent electrostatic damage to the board. Several components on the board can be damaged by electrostatic discharge. To avoid such damage in handling the board, take the following precautions:

• Touch the plastic bag to a metal part of your PC chassis before removing the board from the bag.

• Remove the board from the bag and inspect the board for loose components or any other sign of damage. Notify National Instruments if the board appears damaged in any way. Do not install a damaged board into your computer.

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Chapter 2 Configuration and Installation

This chapter describes the AT-MIO-16D jumper configuration, installation of the AT-MIO-16D board into the PC, signal connections to the AT-MIO-16D board, cable wiring, and handshake timing diagrams for the DIO-24 circuitry of the AT-MIO-16D.

Board Configuration

The AT-MIO-16D contains 14 jumpers and one dual inline package (DIP) switch to configure the AT bus interface and analog input/output (I/O) settings. The DIP switch is used to set the base I/O address. Three jumpers are used as interrupt and direct memory access (DMA) selectors. The remaining 11 jumpers are used to change the analog input and analog output circuitry. The jumpers are shown in the parts locator diagram in Figure 2-1. Jumpers W1, W4, W6, and W9 configure the analog input circuitry. Jumpers W2, W3, W7, W8, W10, and W11 configure the analog output circuitry. Jumper W5 selects the clock signal used by the Am9513A Counter/Timer and the clock pin on the Real-Time System Integration (RTSI) bus. Jumpers W12 and W13 select the DMA channel and the interrupt level, respectively. Jumper W14 selects the DIO-24 circuitry interrupt enable line.

AT Bus Interface

The AT-MIO-16D is configured at the factory to a base I/O address of hex 220, to use DMA channels 6 and 7, to use interrupt level 10 for the MIO-16 circuitry, and to use interrupt enable line PC4 with interrupt level 5 for the DIO-24 circuitry. These settings, as shown in Table 2-1, are suitable for most systems. However, if your system has other hardware at this base I/O address, DMA channel, or interrupt level, you will need to change these settings on the other hardware or on the AT-MIO-16D as described in the following pages.

Table 2-1. AT Bus Interface Factory Settings

Base I/O Address Hex 220

DMA Channel DMA 1 = DMA Channel 6

DMA 2 = DMA Channel 7

Interrupt Level Interrupt levels 5 and 10

selected

(The shaded portion indicates the side of the base address switch that is pressed down.)

W12: R6: A-B A6: A-B W12: R7: B-C A7: B-C

W13: IRQ 10 (MIO-16)

A9A8A7A6A5

12 345

U61

IRQ 5 (DIO-24)

DIO Interrupt Enable Line

PC4 W14: Row PC4

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Chapter 2 Configuration and Installation

Base I/O Address Selection

The base I/O address for the AT-MIO-16D is determined by the switches at position U61 as shown in Figure 2-1. The switches are set at the factory for the base I/O address hex 220. This factory setting is used as the default base I/O address value by National Instruments software packages for use with the AT-MIO-16D. The AT-MIO-16D uses the base I/O address space hex 220 through 23F with the factory setting.

Note: Verify that this space is not already used by other equipment installed in your computer.

If any equipment in your computer uses this base I/O address space, you must change the base I/O address of the AT-MIO-16D or of the other device. If you change the AT-MIO-16D base I/O address, you must make a corresponding change to any software packages you use with the AT-MIO-16D. Table 2-2 lists the default settings of other National Instruments products for the PC AT. For more information about the I/O address of your PC AT, refer to the technical reference manual for your computer.

Table 2-2. Default Settings of Other National Instruments Products for the PC

Board DMA Channel Interrupt Level Base I/O Address

AT-A2150 None* None* 120 hex AT-AO-6/10 Channel 5 Lines 11, 12 1C0 hex AT-DIO-32F Channels 5, 6 Lines 11, 12 240 hex AT-DSP2200 None* None* 120 hex AT-GPIB Channel 5 Line 11 2C0 hex AT-MIO-16 Channels 6, 7 Line 10 220 hex AT-MIO-16D Channels 6, 7 Line 5, 10 220 hex AT-MIO-16F-5 Channels 6, 7 Line 10 220 hex AT-MIO-16X None* None* 220 hex AT-MIO-64F-5 None* None* 220 hex GPIB-PCII Channel 1 Line 7 2B8 hex GPIB-PCIIA Channel 1 Line 7 02E1 hex GPIB-PCIII Channel 1 Line 7 280 hex Lab-PC Channel 3 Line 5 260 hex PC-DIO-24 None Line 5 210 hex PC-DIO-96 None Line 5 180 hex PC-LPM-16 None Line 5 260 hex PC-TIO-10 None Line 5 1A0 hex

*These settings are software configurable and are set to default at startup time.

Each switch in U61 corresponds to one of the address lines A9 through A5. Press the side marked OFF to select a binary value of 1 for the corresponding address bit. Press the other side of the switch to select a binary value of 0 for the corresponding address bit. Figure 2-2 shows two possible switch settings. The shaded portion indicates the side of the switch that is pressed down.

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Configuration and Installation Chapter 2

12 3 4 5

This side down for

This side down for 1

A. Switches Set to Base I/O Address of Hex 00

This side down for

This side down for 1

B. Switches Set to Base I/O Address of Hex 220 (Factory Settin

O N

O F F

12 3 4 5

1234 O

O F F

U61

Figure 2-2. Example Base I/O Address Switch Settings

The five least significant bits (LSBs) of the address (A4 through A0) are decoded by the AT-MIO-16D to select the appropriate AT-MIO-16D register. To change the base I/O address, remove the plastic cover on U61; press each switch to the desired position; check each switch to make sure the switch is pressed down all the way; and replace the plastic cover. Make a note of the new AT-MIO-16D base I/O address for use when configuring the AT-MIO-16D software (a form is provided for you in Appendix G, Customer Communication). Table 2-3 lists the possible switch settings, the corresponding base I/O address, and the base I/O address space used for that setting.

AT-MIO-16D User Manual 2-4 © National Instruments Corporation

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Chapter 2 Configuration and Installation

Table 2-3. Switch Settings with Corresponding Base I/O Address and Base I/O Address Space

Switch Setting Base I/O Address Base I/O Address

A9 A8 A7 A6 A5 (hex) Space Used (hex)

00XXX 000-0E0 Reserved 0 1000 100 100 - 11F 0 1001 120 120 - 13F 0 1010 140 140 - 15F 0 1011 160 160 - 17F 0 1100 180 180 - 19F 0 1101 1A0 1A0 - 1BF 0 1110 1C0 1C0 - 1DF 0 1111 1E0 1E0 - 1FF 1 0000 200 200 - 21F

1 0 0 0 1* 220* 220 - 23F* 1 0010 240 240 - 25F

1 0011 260 260 - 27F 1 0100 280 280 - 29F 1 0101 2A0 2A0 - 2BF 1 0110 2C0 2C0 - 2DF 1 0111 2E0 2E0 - 2FF 1 1000 300 300 - 31F 1 1001 320 320 - 33F 1 1010 340 340 - 35F 1 1011 360 360 - 37F 1 1100 380 380 - 39F 1 1101 3A0 3A0 - 3BF 1 1110 3C0 3C0 - 3DF 1 1111 3E0 3E0 - 3FF

*This setting is the factory default setting.

DMA Channel Selection

The DMA channel used by the AT-MIO-16D is selected by jumpers on W12 as shown in Figure 2-1. The AT-MIO-16D is set at the factory to use DMA channels 6 and 7 for dual DMA mode. These are the default DMA channels used by the AT-MIO-16D software handler. Verify that these DMA channels are not also used by equipment already installed in your computer. If any device uses DMA channel 6 and/or channel 7, change the DMA channel used by either the AT-MIO-16D or the other device. The DMA channels supported by the AT-MIO-16D hardware are channels 5, 6, and 7. Notice that these are the three 16-bit channels on the PC AT I/O channel. The AT-MIO-16D does not use and cannot be configured to use the 8-bit DMA channels on the PC AT I/O channel.

Each DMA channel consists of two signal lines as shown in Table 2-4.

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Configuration and Installation Chapter 2

Table 2-4. DMA Channels for the AT-MIO-16D

DMA DMA DMA

Channel Acknowledge Request

5 DACK5 (A5) DRQ5 (R5) 6 DACK6 (A6) DRQ6 (R6) 7 DACK7 (A7) DRQ7 (R7)

Two jumpers must be installed to select a DMA channel. The DMA Acknowledge and DMA Request lines selected must have the same number suffix for proper operation. When you use dual DMA mode, the left two rows of W12 are used for DMA 1 and the right two rows of W12 are used for DMA 2. Figure 2-3 displays the jumper positions for selecting DMA channels 6 and

7. In this setting, DMA 1 uses DMA channel 6 and DMA 2 uses DMA channel 7.

••

• •

•••

W12

Figure 2-3. DMA Jumper Settings for DMA Channels 6 and 7 (Factory Setting)

If you want to use only one DMA channel, then place the configuration jumpers on W12 in the position shown in Figure 2-4.

•

•••

•

W12

•

• •

Figure 2-4. DMA Jumper Settings for DMA Channel 6 Only

AT-MIO-16D User Manual 2-6 © National Instruments Corporation

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Chapter 2 Configuration and Installation

If you do not want to use DMA for AT-MIO-16D transfers, then place the configuration jumpers on W12 in the position shown in Figure 2-5.

•••

••

•

W12

• •

•

Figure 2-5. DMA Jumper Settings for Disabling DMA Transfers

Interrupt Selection

The AT-MIO-16D board can connect to any of the 11 interrupt lines of the PC AT I/O channel. The interrupt lines for the MIO-16 and DIO-24 circuitry are selected by jumpers on one of the rows of pins located above the I/O slot edge connector on the AT-MIO-16D (refer to Figure 2-1). To use the interrupt capability of the AT-MIO-16D, you must select an interrupt line and place the jumper in the appropriate position to enable that particular interrupt line.

The AT-MIO-16D can share interrupt lines with other devices by using a tristate driver to drive its selected interrupt line. The interrupt lines supported by the AT-MIO-16D hardware for the MIO16 circuitry are IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, IRQ9, IRQ10, IRQ11, IRQ12, IRQ14, and IRQ15. The interrupt lines supported by the AT-MIO-16D hardware for the DIO-24 circuitry are IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, IRQ9.

Note: Do not use interrupt line 6 or interrupt line 14. Interrupt line 6 is used by the diskette drive

controller, and interrupt line 14 is used by the hard disk controller on most IBM PC ATs and compatibles.

Once you have selected an interrupt level, place the interrupt jumper on the appropriate pins to enable the interrupt line.

The interrupt jumper set is W13. The default interrupt lines are IRQ10 for the MIO-16 circuitry and IRQ5 for the DIO-24 circuitry, which are selected by placing the jumpers on the pins in rows 5 and 10. Figure 2-6 shows the default interrupt jumper settings IRQ5 and IRQ10. To change to another line, remove the jumper from IRQ5 or IRQ10 and place it on the new pins.

MIO IRQ

3456791011121415

•••

• •••••••

W13

•

•••

DIO IRQ

•

Figure 2-6. Factory Interrupt Jumper Settings IRQ5 (DIO-24) and IRQ10 (MIO-16)

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Configuration and Installation Chapter 2

If you do not want to use interrupts, place the jumpers on W13 in the position shown in Figure 2-7. This setting disables the AT-MIO-16D from asserting an interrupt line on the PC AT I/O channel.

MIO IRQ

3456791011121415

W13

••

•

•••

DIO IRQ

•

••

•••••••

•

Figure 2-7. Interrupt Jumper Setting for Disabling Interrupts

DIO-24 Circuitry Interrupt Enable Settings

To enable interrupt requests from the DIO-24 circuitry, you must set jumper W14 to select PC2, PC4, or PC6 as the active low interrupt enable line. When the interrupt enable line is logic low, interrupts are enabled from the DIO-24 circuitry of the AT-MIO-16D board. Refer to Chapter 4, Programming, for the suggested interrupt enable line setting for each digital I/O mode of operation. If W14 is set to N/C, all interrupt requests from the DIO-24 circuitry are disabled. Figure 2-8 shows the possible jumper settings for W14. The board is shipped with this jumper set to PC4; therefore, interrupt requests from the board are enabled and controlled by PC4.

W14

• •

DIO INT

W14

PC6

PC4

PC2

N/C

(Default Factory Setting)

• •

DIO INT

PC6

PC4

PC2

N/C

W14

• •

DIO INT

PC6

PC4

PC2

N/C

W14

• •

DIO INT

Figure 2-8. Jumper Settings–PC6, PC4, PC2, and N/C

Analog I/O Jumper Settings

The AT-MIO-16D is shipped from the factory with the following configuration:

• Differential analog input (eight channels)

• Bipolar analog input

• ±10 V input range

PC6

PC4

PC2

N/C

AT-MIO-16D User Manual 2-8 © National Instruments Corporation

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Chapter 2 Configuration and Installation

• ±10 V output range with internal reference selected

• Two's complement digital-to-analog converter (DAC) input modes

• AT-MIO-16D clock signal set to 10 MHz

Table 2-5 lists all the available analog I/O jumper configurations for the AT-MIO-16D with the factory settings noted.

Table 2-5. Analog I/O Jumper Settings

Configuration Jumper Settings

ADC Input Unipolar 0 V to +10 V W1: B-C W4: A-B

Range Bipolar ±5 V W1: B-C W4: B-C

Bipolar ±10 V (factory setting) W1: A-B W4: B-C

ADC Input Differential (DIFF) (factory setting) W6: A-C, B-D, E-F W9: A-B Mode Nonreferenced single-ended (NRSE) W6: A-B, C-E, G-H W9: B-C

Referenced single-ended (RSE) W6: A-B, C-D, G-H W9: B-C

Am9513A & AT-MIO-16D clock signal = W5: C-D, E-F RTSI Bus 10 MHz (factory setting) Clock Select AT-MIO-16D clock signal = W5: A-B, E-F

RTSI clock signal

AT-MIO-16D & RTSI clock W5: A-B, C-D

signals both = 10 MHz

DAC0 Internal (factory setting) W3: B-C Reference External W3: A-B

DAC1 Internal (factory setting) W2: B-C Reference External W2: A-B

DAC0 Output Unipolar – Straight binary mode W8: B-C W10: B-C Polarity – Bipolar – Two's complement mode W8: A-B W10: A-B Digital Format (factory setting)

DAC1 Output Unipolar – Straight binary mode W7: B-C W11: B-C Polarity – Bipolar – Two's complement mode W7: A-B W11: A-B Digital Format (factory setting)

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Configuration and Installation Chapter 2

Analog Input Configuration

You can select different analog input configurations by using the jumper settings shown in Table 2-5. The following paragraphs describe in detail each of the analog input categories. In the configuration illustrations throughout this chapter, the black bars show where to place jumpers.

Input Mode

The AT-MIO-16D offers three different analog input modes–nonreferenced single-ended (NRSE) input, referenced single-ended (RSE) input, and differential (DIFF) input. The single-ended input configurations use 16 channels. The DIFF input configuration uses eight channels. These configurations are described in Table 2-6.

Table 2-6. Input Configurations Available for the AT-MIO-16D

Configuration Description

DIFF Differential configuration

Provides eight differential inputs with the negative (-) input of the instrumentation amplifier tied to the multiplexer output of channels 8 through 15

RSE Referenced Single-Ended configuration

Provides 16 single-ended inputs with the negative (-) input of the instrumentation amplifier referenced to analog ground

NRSE Nonreferenced Single-Ended configuration

Provides 16 single-ended inputs with the negative (-) input of the instrumentation amplifier tied to AI SENSE and not connected to ground

While reading the following paragraphs, you may find it helpful to refer to the Analog Input Signal Connections section later in this chapter, which contains diagrams showing the signal paths for the three configurations.

DIFF Analog Input (Eight Channels, Factory Setting)

DIFF input means that each input signal has its own reference, and the difference between each signal and its reference is measured. The signal and its reference are each assigned an input channel. With this input configuration, the AT-MIO-16D can monitor eight different analog input signals. You select the DIFF analog input configuration by setting jumpers W6 and W9 as follows:

W6 :

A - C Jumper is placed in standby position. Jumper can be discarded.

B - D AI SENSE is tied to the instrumentation amplifier output ground point.

E - F Channels 0 through 7 are tied to the positive (+) input of the

instrumentation amplifier. Channels 8 through 15 are tied to the negative (-) input of the instrumentation amplifier.

AT-MIO-16D User Manual 2-10 © National Instruments Corporation

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Chapter 2 Configuration and Installation

W9 :

A - B Multiplexer is configured to control eight input channels.

This configuration is shown in Figure 2-9.

•

DIFF

•

ABC

Input Mode

Figure 2-9. DIFF Analog Input Configuration (Factory Setting)

Considerations in using the DIFF analog input configuration are discussed in the Signal Connections section later in this chapter. Figure 2-26 shows a schematic diagram of this configuration.

RSE Analog Input (16 Channels)

RSE input means that all input signals are referenced to a common ground point that is also tied to the analog input ground of the AT-MIO-16D board. The negative (-) input of the differential input amplifier is tied to the analog ground. This configuration is useful when measuring floating signal sources. See the Types of Signal Sources section later in this chapter for more information. With this input configuration, the AT-MIO-16D can monitor 16 different analog input signals. You select the RSE analog input configuration by setting jumpers W6 and W9 as follows:

W6 :

A - B AI SENSE is tied to the negative (-) input of the instrumentation

amplifier.

C - D The negative (-) input of the instrumentation amplifier is tied to the

instrumentation amplifier signal ground.

G - H Multiplexer outputs are tied together into the positive (+) input of the

instrumentation amplifier.

W9 :

B - C Multiplexer control is configured to control 16 input channels.

This configuration is shown in Figure 2-10.

•

ABC

DIFF

•

Figure 2-10. RSE Analog Input Configuration

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Configuration and Installation Chapter 2

Considerations in using the ground-referenced single-ended analog configuration are discussed in the Signal Connections section later in this chapter. Figure 2-28 shows a schematic diagram of this configuration.

NRSE Analog Input (16 Channels)

NRSE analog input means that all input signals are referenced to the same common mode voltage, but that this common mode voltage is allowed to float with respect to the analog ground of the AT-MIO-16D board. This common mode voltage is subsequently subtracted by the input instrumentation amplifier. This configuration is useful when measuring ground-referenced signal sources. See the Types of Signal Sources section later in this chapter for more information. With this input configuration, the AT-MIO-16D can measure 16 different analog input signals. You select the NRSE analog input configuration by setting jumpers W6 and W9 as follows:

W6 :

A - B AI SENSE is tied into the negative (-) input of the instrumentation

amplifier.

C - E Jumper is placed in standby position. Jumper can be discarded.

G - H Multiplexer outputs are tied together into the positive (+) input of the

instrumentation amplifier.

W9:

B - C Multiplexer control is configured for 16 input channels.

This configuration is shown in Figure 2-11.

•

ABC

DIFF

•

Figure 2-11. NRSE Analog Input Configuration

Considerations in using the NRSE configuration are discussed under the Signal Connections section later in this chapter. Figure 2-29 shows a schematic diagram of this configuration.

Analog Input Polarity and Range

The AT-MIO-16D offers two analog input polarities–unipolar input and bipolar input. Unipolar input means that the analog input voltage range is between 0 and V reference voltage. Bipolar input means that the analog input voltage range is between -V +V

. The AT-MIO-16D also has two input ranges–10 V input range and a 20 V input range.

ref

The selection of input polarity and range are combined into three possible configurations as shown in Table 2-7.

where V

ref

is some positive

ref

and

ref

AT-MIO-16D User Manual 2-12 © National Instruments Corporation

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Chapter 2 Configuration and Installation

Table 2-7. Configurations for Input Range and Input Polarity

Input Range Input Polarity Jumper Settings

W1 W4

0 to +10 V (10 V range) Unipolar B-C A-B

-5 to +5 V (10 V range) Bipolar B-C B-C

-10 to +10 V (20 V range) Bipolar A-B B-C (factory setting)

Figures 2-12, 2-13, and 2-14 show the jumper positions for the 0 to +10 V, -5 to +5 V, and

-10 to +10 V input polarity/range configurations, respectively.

•

A B C

ADC Mode

ADC Range

20 V 10 V

•

A B C

Figure 2-12. 0 to +10 V Input Configuration

ADC Range

20 V 10 V

•

A B C

•

A B C

ADC Mode

Figure 2-13. -5 to +5 V Input Configuration

ADC Range

20 V 10 V

•

A B C

•

A B C

ADC Mode

Figure 2-14. Factory -10 to +10 V Analog Input Configuration

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Configuration and Installation Chapter 2

Considerations for Selecting Analog Input Ranges

Analog input polarity/range selection depends on the expected input range of the incoming signal. A large input range can accommodate a large signal variation but sacrifices voltage resolution. Choosing a smaller input range increases voltage resolution but may result in the input signal going out of range. For best results, the input range should be matched as closely as possible to the expected range of the input signal. For example, if the input signal is guaranteed to never go negative (below 0 V), a unipolar input is best. However, if the signal does go negative, inaccurate readings will occur.

Software-programmable gain on the AT-MIO-16D increases overall flexibility by matching input signal ranges to those accommodated by the AT-MIO-16D analog-to-digital converter (ADC). The AT-MIO-16DH board has gains of 1, 2, 4, and 8 and is suited for high-level signals near the range of the ADC. The AT-MIO-16DL board is designed to measure low-level signals and has gains of 1, 10, 100, and 500. With the proper gain setting, the full resolution of the ADC can be used to measure the input signal. Table 2-8 shows the overall input range and precision according to the input range configuration and gain used.

Table 2-8. Actual Range and Measurement Precision Versus Input Range Selection and Gain

Range Configuration Gain Actual Input Range Precision*

0 to +10 V 1 0 to +10 V 2.44 mV

2 0 to +5 V 1.22 mV

4 0 to +2.5 V 610 µV 8 0 to +1.25 V 305 µV

10 0 to +1 V 244 µV 100 0 to +0.1 V 24.4 µV 500 0 mV to +20 mV 4.88 µV

-5 to +5 V 1 -5 to +5 V 2.44 mV 2 -2.5 to +2.5 V 1.22 mV

4 -1.25 to +1.25 V 610 µV 8 -0.625 to +0.625 V 305 µV

10 -0.5 to +0.5 V 244 µV 100 -50 mV to +50 mV 24.4 µV 500 -10 mV to +10 mV 4.88 µV

-10 to +10 V 1 -10 to +10 V 4.88 mV 2 -5 to +5 V 2.44 mV 4 -2.5 to +2.5 V 1.22 mV

8 -1.25 to +1.25 V 610 µV

10 -1 to +1 V 488 µV 100 -0.1 to +0.1 V 48.8 µV 500 -20 mV to +20 mV 9.76 µV

* The value of 1 LSB of the 12-bit ADC, that is, the voltage increment corresponding to a

change of 1 count in the ADC 12-bit count.

AT-MIO-16D User Manual 2-14 © National Instruments Corporation

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Chapter 2 Configuration and Installation

Analog Output Configuration

You can select different analog output configurations by using the jumper settings shown in Table 2-5. The following paragraphs describe in detail each of the analog output configurations.

Analog Output Reference Selection

Each DAC can be connected to the AT-MIO-16D internal reference of 10 V or to the external reference signal connected to the EXTREF pin on the I/O connector. This signal applied to EXTREF must be between -10 V and +10 V. Both channels need not be configured the same way.

External Reference Selection

You select the external reference signal for each analog output channel by setting the following jumpers:

Analog Output Channel 0: W3 A - B External reference signal connected to DAC 0

reference input.

Analog Output Channel 1: W2 A - B External reference signal connected to DAC 1

reference input.

This configuration is shown in Figure 2-15.

Channel 0 Channel 1

EXT

INT

•

DAC DAC

•

EXT

INT

Figure 2-15. External Reference Configuration

Internal Reference Selection (Factory Setting)

You select the onboard 10 V reference for each analog output channel by setting the following jumpers:

Analog Output Channel 0: W3 B - C 10 V onboard reference connected to DAC 0

reference input.

Analog Output Channel 1: W2 B - C 10 V onboard reference connected to DAC 1

reference input.

This configuration is shown in Figure 2-16.

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Configuration and Installation Chapter 2

Channel 0 Channel 1

EXT

•

INT

DAC DAC

•

EXT

INT

Figure 2-16. Factory Internal Reference Configuration

Analog Output Polarity Selection

Each analog output channel can be configured for either unipolar or bipolar output. A unipolar configuration has a range of 0 to V

-V

ref

to +V

at the analog output. V

ref

output circuitry and can either be the 10 V onboard reference or an externally supplied reference between -10 V and +10 V. Both channels need not be configured the same way; however, at the factory both channels are configured for bipolar output.

at the analog output. A bipolar configuration has a range of

ref

is the voltage reference used by the DACs in the analog

ref

Bipolar Output Selection (Factory Setting)

You select the bipolar output configuration for each analog output channel by setting the following jumpers:

Analog Output Channel 0: W8 A - B

Analog Output Channel 1: W7 A - B

This configuration is shown in Figure 2-17.

A B C

Channel 0 Channel 1

UBU

•

DAC 0 DAC 1

A B C

•

Figure 2-17. Factory Bipolar Output Configuration

AT-MIO-16D User Manual 2-16 © National Instruments Corporation

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Chapter 2 Configuration and Installation

When you use the bipolar configuration, you need to select whether to write straight binary or two's complement to the DAC. In straight binary mode, data values written to the analog output channel range from 0 to 4,095 decimal (0 to 0FFF hex). In two's complement mode, data values written to the the analog output channel range from -2,048 to +2,047 decimal (F800 to 07FF hex).

Straight Binary Mode

The data value written to each analog output channel is interpreted as a straight binary number when the following jumpers are set:

Analog Output Straight Binary for Channel 0: W10 B - C

Analog Output Straight Binary for Channel 1: W11 B - C

This configuration is shown in Figure 2-18.

2SC

W10

•

A B C

Channel 0 Channel 1

BIN

DAC 0

W11

2SC

•

A B C

BIN

DAC 1

Figure 2-18. Straight Binary Mode

Two's Complement Mode (Factory Setting)

The data value written to each analog output channel is interpreted as a two's complement number when the following jumpers are set:

Analog Output Two's Complement for Channel 0: W10 A - B

Analog Output Two's Complement for Channel 1: W11 A - B

This configuration is shown in Figure 2-19.

2SC

W10

A B C

BIN

•

DAC 0

W11

2SC

A B C

BIN

•

DAC 1

Channel 0 Channel 1

Figure 2-19. Two's Complement Mode (Factory Setting)

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Configuration and Installation Chapter 2

Unipolar Output Selection

You select the unipolar output configuration for each analog output channel by setting the following jumpers:

Analog Output Channel 0: W8 B - C

Analog Output Straight Binary for Channel 0: W10 B - C

Analog Output Channel 1: W7 B - C

Analog Output Straight Binary for Channel 1: W11 B - C

Notice that the straight binary format must be used when in unipolar output mode.

This configuration is shown in Figure 2-20.

•

A B C

•

A B C

DAC 0 DAC 1

Channel 0 Channel 1

2SC

W10

•

A B C

Channel 0 Channel 1

BIN

DAC 0

W11

2SC

•

A B C

BIN

DAC 1

Figure 2-20. Unipolar Output Configuration

Note: If you are using a software package such as LabWindows or NI-DAQ, you may need to

reconfigure your software to reflect any changes in jumper or switch settings.

RTSI Bus Clock Selection

When multiple AT Series boards are connected via the RTSI bus, you may want to have all the boards use the same 10-MHz clock. This arrangement is useful for applications that require counter/timer synchronization between boards. Each AT Series board with a RTSI bus interface has an onboard 10-MHz oscillator. Thus, one board can drive the RTSI bus clock signal, and the other boards can receive this signal or disconnect from it.

AT-MIO-16D User Manual 2-18 © National Instruments Corporation

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Chapter 2 Configuration and Installation

The configuration for jumper W5 specifies whether a board is to drive the onboard 10-MHz oscillator onto the RTSI bus, receive the RTSI bus clock, or disconnect from the RTSI bus clock. This clock source, whether local or RTSI signal, is then divided by 10 and used as the Am9513A frequency source.

The jumper selections are listed in Table 2-9.

Table 2-9. Configurations for RTSI Bus Clock Selection

Configuration W5

Disconnect board from RTSI bus clock; use local

C - D, E - F (factory setting)

oscillator

Receive RTSI bus clock signal A - B, E - F

Drive RTSI bus clock signal with local oscillator A - B, C - D

Figures 2-21, 2-22, and 2-23 show the jumper positions for each of the configurations described above.

BRD

•

RTSI

10 MHZ

Figure 2-21. Disconnect from RTSI Bus Clock; Use Onboard Oscillator (Factory Setting)

BRD

•

RTSI

10 MHZ

Figure 2-22. Receive RTSI Bus Clock Signal

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Configuration and Installation Chapter 2

BRD

•

RTSI

10 MHZ

Figure 2-23. Drive RTSI Bus Clock Signal with Onboard Oscillator

Hardware Installation

The AT-MIO-16D can be installed in any available 16-bit expansion slot (AT style) in your computer. The AT-MIO-16D does not work if installed in an eight-bit expansion slot (PC style). After you have changed (if needed), verified, and recorded the switches and jumper settings, you are ready to install the AT-MIO-16D. The following are general installation instructions, but consult the user manual or technical reference manual of your PC AT for specific instructions and warnings.

1. Turn off your computer.

2. Remove the top cover or access port to the I/O channel.

3. Remove the expansion slot cover on the back panel of the computer.

4. Insert the AT-MIO-16D into a 16-bit slot. It may be a tight fit, but do not force the board into place.

5. Screw the mounting bracket of the AT-MIO-16D to the back panel rail of the computer.

6. Check the installation.

7. Replace the cover.

The AT-MIO-16D board is installed and ready for operation.

Signal Connections

This section describes input and output signal connections to the AT-MIO-16D board via the AT-MIO-16D I/O connector. This section includes specifications and connection instructions for the signals given on the AT-MIO-16D I/O connector. The I/O connector contains 100 pins that can be split into two standard 50-pin connectors via a cable assembly such as a Type NB5 ribbon cable (see Figure 1-2). One 50-pin connector contains signals associated with the MIO-16 circuitry, while the other 50-pin connector contains signals for the DIO-24 circuitry.

AT-MIO-16D User Manual 2-20 © National Instruments Corporation

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Chapter 2 Configuration and Installation

Warning: Connections that exceed any of the maximum ratings of input or output signals on

the AT-MIO-16D can result in damage to the AT-MIO-16D board and to the PC AT. Maximum input ratings for each signal are given in this chapter under the discussion of that signal. National Instruments is not liable for any damages resulting from any such signal connections.

AT-MIO-16D I/O Connector Pin Description

Figure 2-24 shows the pin assignments for the AT-MIO-16D I/O connector. Refer to MIO-16 Signal Connection Descriptions and DIO-24 Signal Connection Descriptions later in this chapter

for descriptions of the AT-MIO-16D signal connections.

AI GND AI GND

ACH0 ACH8 ACH1 ACH9 ACH2

ACH10

ACH3

ACH11

ACH4

ACH12

ACH5

ACH13

ACH6

ACH14

ACH7

ACH15

AI SENSE DAC0 OUT DAC1 OUT

EXTREF

AO GND

DIG GND

ADIO0 BDIO0 ADIO1 BDIO1 ADIO2 BDIO2 ADIO3 BDIO3

DIG GND

+5 V +5 V

SCANCLK

EXTSTROBE*

START TRIG*

STOP TRIG

EXTCONV*

SOURCE1

GATE1

OUT1

SOURCE2

GATE2

OUT2

SOURCE5

GATE5

OUT5 FOUT

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

100

PC7 GND PC6 GND PC5 GND PC4 GND PC3 GND PC2 GND PC1 GND PC0 GND PB7 GND PB6 GND PB5 GND PB4 GND PB3 GND PB2 GND PB1 GND PB0 GND PA 7 GND PA 6 GND PA 5 GND PA 4 GND PA 3 GND PA 2 GND PA 1 GND PA 0 GND +5 V GND

Figure 2-24. AT-MIO-16D I/O Connector Pin Assignments

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Configuration and Installation Chapter 2

MIO-16 I/O Connector Pin Description

Figure 2-25 shows the pin assignments for the MIO-16 I/O connector of the AT-MIO-16D.

AI GND

ACH0 ACH1

ACH2 ACH3 ACH4 ACH5 ACH6 ACH7

AI SENSE

DAC1 OUT

AO GND

ADIO0

ADIO1 ADIO2

ADIO3

DIG GND

+5 V

EXTSTROBE*

STOP TRIG

SOURCE1

OUT1

GATE2

SOURCE5

OUT5

2 43 65

87 109 1211 1413 1615 1817

2019 2221 2423 2625 2827 3029 3231 3433 3635 3837 4039 4241 4443

4645 4847 50

AI GND ACH8 ACH9

ACH10

ACH11

ACH12

ACH13

ACH14 ACH15 DAC0 OUT

EXTREF

DIG GND

BDIO0

BDIO1 BDIO2

BDIO3

+5 V SCANCLK START TRIG*

EXTCONV*

GATE1 SOURCE2

OUT2

GATE5 FOUT

Figure 2-25. MIO-16 I/O Connector Pin Assignments

AT-MIO-16D User Manual 2-22 © National Instruments Corporation

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Chapter 2 Configuration and Installation

MIO-16 Signal Connection Descriptions

Pin Signal Name Reference Description

1-2 AI GND N/A Analog Input Ground – These pins are the reference

point for single-ended measurements and the bias current return point for differential measurements.

3-18 ACH<0..15> AIGND Analog Input Channels 0 through 15 – In differential

mode, the input is configured for up to eight channels. In single-ended mode, the input is configured for up to 16 channels.

19 AI SENSE AIGND Analog Input Sense – This pin serves as the

reference node when the board is in NRSE configuration. If desired, this signal can be programmed to be driven by the board analog input ground.

20 DAC0 OUT AOGND Analog Channel 0 Output – This pin supplies the

voltage output of analog output channel 0.

21 DAC1 OUT AOGND Analog Channel 1 Output – This pin supplies the

voltage output of analog output channel 1.

22 EXTREF AOGND External Reference – This is the external reference

input for the analog output circuitry.

23 AO GND N/A Analog Output Ground – The analog output voltages

are referenced to this node.

24,33 DIG GND N/A Digital Ground – This pin supplies the reference for

the digital signals at the I/O connector as well as the +5 VDC supply.

25, 27, ADIO<0..3> DIGGND Digital I/O port A signals. 29, 31

26, 28, BDIO<0..3> DIGGND Digital I/O port B signals. 30, 32

34-35 +5 V DIGGND +5 VDC Source – This pin is fused for up to 1 A of

+5 V supply.

36 SCANCLK DIGGND Scan Clock – This pin pulses once for each A/D

conversion in the scanning modes. The low-to-high edge indicates when the input signal can be removed from the input or switched to another signal.

37 EXTSTROBE* DIGGND External Strobe – Writing to the EXTSTROBE*

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Configuration and Installation Chapter 2

Pin Signal Name Reference Description (continued)

38 START TRIG* DIGGND External Trigger – In posttrigger data acquisition

sequences, a low-to-high edge on START TRIG* initiates the sequence. In pretrigger applications, the low-to-high edge of START TRIG* initiates pretrigger conversions while the STOP TRIG signal initiates the posttrigger sequence.

39 STOP TRIG DIGGND Stop Trigger – In pretrigger data acquisition, the

high-to-low edge of STOP TRIG initiates the posttrigger sequence.

40 EXTCONV* DIGGND External Convert – A high-to-low edge on

EXTCONV* causes an A/D conversion to occur. If EXTGATE* or EXTCONV* is low, conversions are inhibited.

41 SOURCE1 DIGGND SOURCE1 – This pin is from the Am9513A

Counter 1 signal.

42 GATE1 DIGGND GATE1 – This pin is from the Am9513A Counter 1

signal.

43 OUT1 DIGGND OUTPUT1 – This pin is from the Am9513A

Counter 1 signal.

44 SOURCE2 DIGGND SOURCE2 – SOURCE5 – This pin is from the

Am9513A Counter 2 signal.

45 GATE2 DIGGND GATE2 – This pin is from the Am9513A Counter 2

signal.

46 OUT2 DIGGND OUTPUT2 – This pin is from the Am9513A

Counter 2 signal.

47 SOURCE5 DIGGND SOURCE5 – This pin is from the Am9513A

Counter 5 signal.

48 GATE5 DIGGND GATE5 – This pin is from the Am9513A Counter 5

signal.

49 OUT5 DIGGND OUT5 – This pin is from the Am9513A Counter 5

signal.

50 FOUT DIGGND Frequency Output – This pin is from the Am9513A

FOUT signal.

The signals on the connector can be classified as analog input signals, analog output signals, digital I/O signals, digital power connections, or timing I/O signals. Signal connection guidelines for each of these groups are given as follows.

AT-MIO-16D User Manual 2-24 © National Instruments Corporation

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Chapter 2 Configuration and Installation

Analog Input Signal Connections

Pins 1 through 19 of the MIO-16 I/O connector are analog input signal pins. Pins 1 and 2 are AI GND signal pins. AI GND is an analog input common signal that is routed directly to the ground tie point on the AT-MIO-16D. These pins can be used for a general analog power ground tie point to the AT-MIO-16D if necessary. Pin 19 is the AI SENSE pin. In single-ended mode, this pin is connected internally to the negative (-) input of the AT-MIO-16D instrumentation amplifier. In DIFF mode, this signal is connected to the reference ground at the output of the instrumentation amplifier.

Pins 3 through 18 are ACH<15..0> signal pins. These pins are tied to the 16 analog input channels of the AT-MIO-16D. In single-ended mode, signals connected to ACH<15..0> are routed to the positive (+) input of the AT-MIO-16D instrumentation amplifier. In DIFF mode, signals connected to ACH<7..0> are routed to the positive (+) input of the AT-MIO-16D instrumentation amplifier, and signals connected to ACH<15..8> are routed to the negative (-) input of the AT-MIO-16D instrumentation amplifier.

The following input ranges and maximum ratings apply to inputs ACH<15..0>:

Differential input range ±10 V Common-mode input range ±7 V with respect to AT-MIO-16D AGND Input range ±12 V with respect to AT-MIO-16D AGND Maximum input voltage rating ±20 V for AT-MIO-16D board powered off

±35 V for AT-MIO-16D board powered on

Warning: Exceeding the differential and common-mode input ranges will result in distorted

input signals. Exceeding the maximum input voltage rating may result in damage to the AT-MIO-16D board and to the PC AT. National Instruments is not liable for any damages resulting from any such signal connections.

Connection of analog input signals to the AT-MIO-16D depends on the configuration of the AT-MIO-16D analog input circuitry and the type of input signal source. The different AT-MIO-16D configurations allow the AT-MIO-16D instrumentation amplifier to be used in different ways. Figure 2-26 shows a diagram of the AT-MIO-16D instrumentation amplifier.

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Configuration and Installation Chapter 2

Instrumentation

Amplifier

Measured Voltage

Vm = [ V

Figure 2-26. AT-MIO-16D Instrumentation Amplifier

The AT-MIO-16D instrumentation amplifier applies gain, common-mode voltage rejection, and high-input impedance to the analog input signals connected to the AT-MIO-16D board. Signals are routed to the positive (+) and negative (-) inputs of the instrumentation amplifier through input multiplexers on the AT-MIO-16D. The instrumentation amplifier converts two input signals to a signal that is the difference between the two input signals multiplied by the gain setting of the amplifier. The amplifier output voltage is referenced to the AT-MIO-16D ground. The AT-MIO-16D ADC measures this output voltage when it performs A/D conversions.

All signals must be referenced to ground somewhere, either at the source device or at the AT-MIO-16D. If you have a floating source, you must use a ground-referenced input connection at the AT-MIO-16D. If you have a grounded source, you must use a nonreferenced input connection at the AT-MIO-16D.

- ] * GAIN

Types of Signal Sources

When configuring the input mode of the AT-MIO-16D and making signal connections, you must first determine whether the signal source is floating or ground-referenced. These two types of signals are described in the following sections.

Floating Signal Sources

A floating signal source is one that is not connected in any way to the building ground system but rather has an isolated ground reference point. Some examples of floating signal sources are outputs of transformers, thermocouples, battery-powered devices, optical isolator outputs, and isolation amplifiers. The ground reference of a floating signal must be tied to the AT-MIO-16D analog input ground in order to establish a local or onboard reference for the signal. Otherwise, the measured input signal varies or appears to float. An instrument or device that provides an isolated output falls into the floating signal source category.

AT-MIO-16D User Manual 2-26 © National Instruments Corporation

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Chapter 2 Configuration and Installation

Ground-Referenced Signal Sources

A ground-referenced signal source is one that is connected in some way to the building system ground and is therefore already connected to a common ground point with respect to the AT-MIO-16D board, assuming that the PC AT is plugged into the same power system. Nonisolated outputs of instruments and devices that plug into the building power system fall into this category.

The difference in ground potential between two instruments connected to the same building power system is typically between 1 mV and 100 mV but can be much higher if power distribution circuits are not properly connected. If the grounded signal source is measured improperly, this difference may show up as an error in the measurement. The connection instructions for grounded signal sources below are designed to eliminate this ground potential difference from the measured signal.

Input Configurations

The AT-MIO-16D can be configured for one of three input modes–NRSE, RSE, or DIFF. The following sections discuss the use of single-ended and differential measurements, and considerations for measuring both floating and ground-referenced signal sources. Table 2-10 summarizes the recommended input configuration for both types of signal sources.

Table 2-10. Recommended Input Configurations for Ground-Referenced

and Floating Signal Sources

Type of Signal Recommended Input Configuration

Ground-Referenced

(nonisolated outputs,

DIFF NRSE

plug-in instruments)

Floating

(batteries, thermocouples,

DIFF with bias resistors RSE

isolated outputs)

Differential Connection Considerations (DIFF Configuration)

Differential connections are those in which each AT-MIO-16D analog input signal has its own reference signal or signal return path. These connections are available when the AT-MIO-16D is configured in the DIFF mode. Each input signal is tied to the positive (+) input of the instrumentation amplifier; and its reference signal, or return, is tied to the negative (-) input of the instrumentation amplifier.

When the AT-MIO-16D is configured for DIFF input, each signal uses two of the multiplexer inputs–one for the signal and one for its reference signal. Therefore, only eight analog input channels are available when using the DIFF configuration. The DIFF input configuration should be used when any of the following conditions are present:

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Configuration and Installation Chapter 2

1. Input signals are low level (less than 1 V).

2. Leads connecting the signals to the AT-MIO-16D are greater than 15 ft.

3. Any of the input signals requires a separate ground reference point or return signal.

4. The signal leads travel through noisy environments.

Differential signal connections reduce picked-up noise and increase common-mode signal and noise rejection. They also allow input signals to float within the common-mode limits of the input instrumentation amplifier.

Differential Connections for Grounded Signal Sources

Figure 2-27 shows how to connect a ground-referenced signal source to an AT-MIO-16D board configured for DIFF input. Configuration instructions are included under the Analog Input Configuration section earlier in this chapter.



ACH<0..7>

GroundReferenced Signal Source

Common Mode Noise, Ground Potential, Etc.

MIO-16 I/O Connector

ACH<8..15>

Input Multiplexers

AI SENSE

1-2

AI GND

Instrumentation

Amplifier

Measured Voltage

AT-MIO-16D Board in DIFF Configuratio

Figure 2-27. Differential Input Connections for Grounded Signal Sources

AT-MIO-16D User Manual 2-28 © National Instruments Corporation

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Chapter 2 Configuration and Installation

With this type of connection, the instrumentation amplifier rejects both the common-mode noise in the signal and the ground potential difference between the signal source and the AT-MIO-16D ground (shown as V

in Figure 2-27).

Differential Connections for Floating Signal Sources

Figure 2-28 shows how to connect a floating signal source to an AT-MIO-16D board configured for DIFF input. Configuration instructions are included under the Analog Input Configuration section earlier in this chapter.

Floating Signal Source

Bias Current Return Paths

100 kΩ

1-2

AI GND

AI SENSE

ACH<0..7>

ACH<8..15>

Input Multiplexers

Instrumentation

Amplifier

Measured Voltage

I/O Connector

AT-MIO-16 Board in DIFF Configuratio

Figure 2-28. Differential Input Connections for Floating Sources

The 100-kΩ resistors shown in Figure 2-28 create a return path to ground for the bias currents of

the instrumentation amplifier. If a return path is not provided, the instrumentation amplifier bias currents charge up stray capacitances, resulting in uncontrollable drift and possible saturation in the

amplifier. Typically, values from 10 kΩ to 100 kΩ are used.

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Configuration and Installation Chapter 2

A resistor from each input to ground, as shown in Figure 2-28, provides bias current return paths for an AC-coupled input signal. This solution, although necessary for AC-coupled signals, lowers the input impedance of the analog input channel. In addition, the input offset current of the instrumentation amplifier contributes a DC offset voltage at the input. The amplifier has a

maximum input offset current of ±15 nA and a typical offset current drift of ±20 pA/°C. Multiplied by the 100-kΩ resistor, this current contributes a maximum offset voltage of 1.5 mV and a typical offset voltage drift of 2 µV/°C at the input. Keep this in mind when you observe DC

offsets with AC-coupled inputs.

If the input signal is DC-coupled, then you only need the resistor connecting the negative (-) signal input to ground. This connection does not lower the input impedance of the analog input channel.

Single-Ended Connection Considerations

Single-ended connections are those in which all AT-MIO-16D analog input signals are referenced to one common ground. The input signals are tied to the positive (+) input of the instrumentation amplifier, and their common ground point is tied to the negative (-) input of the instrumentation amplifier.

When the AT-MIO-16D is configured for single-ended input (NRSE or RSE), 16 analog input channels are available. You can use single-ended input connections when the following criteria are met by all input signals:

1. Input signals are high-level (greater than 1 V).

2. Leads connecting the signals to the AT-MIO-16D are less than 15 ft.

3. All input signals share a common reference signal (at the source).

If any of the above criteria is not met, using DIFF input configuration is recommended.

You can jumper configure the AT-MIO-16D for two different types of single-ended connections– RSE configuration and NRSE configuration. Use the RSE configuration for floating signal sources; in this case, the AT-MIO-16D provides the reference ground point for the external signal. Use the NRSE configuration for ground-referenced signal sources; in this case, the external signal supplies its own reference ground point and the AT-MIO-16D should not supply one.

Single-Ended Connections for Floating Signal Sources (RSE Configuration)

Figure 2-29 shows how to connect a floating signal source to an AT-MIO-16D board configured for single-ended input. You must configure the AT-MIO-16D analog input circuitry for RSE input to make these types of connections. Configuration instructions are included under the

Analog Input Configuration section earlier in this chapter.

AT-MIO-16D User Manual 2-30 © National Instruments Corporation

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Chapter 2 Configuration and Installation

ACH<0..15>

Instrumentation

Input Multiplexer

AI GND

AT-MIO-16D Board in RSE Configuratio

Amplifier

Measured Voltage

Floating

Signal

Sourc

MIO-16 I/O Connector

1-2

AI SENSE

Figure 2-29. Single-Ended Input Connections for Floating Signal Sources

Single-Ended Connections for Grounded Signal Sources (NRSE Configuration)

If a grounded signal source is to be measured with a single-ended configuration, then you must configure the AT-MIO-16D in the NRSE input configuration. Connect the signal to the positive (+) input of the AT-MIO-16D instrumentation amplifier and connect the signal local ground reference to the negative (-) input of the AT-MIO-16D instrumentation amplifier. The ground point of the signal should therefore be connected to the AI SENSE pin. Any potential difference between the AT-MIO-16D ground and the signal ground appears as a common-mode signal at both the positive (+) and negative (-) inputs of the instrumentation amplifier and this difference is rejected by the amplifier. On the other hand, if the input circuitry of the AT-MIO-16D is referenced to ground, such as in the RSE configuration, this difference in ground potentials appears as an error in the measured voltage.

Figure 2-30 shows how to connect a grounded signal source to an AT-MIO-16D board configured in the NRSE configuration. Configuration instructions are included under the Analog Input

Configuration section earlier in this chapter.

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Configuration and Installation Chapter 2

ACH<0..15>

Input Multiplexer

AI SENSE

AI GND

Ground-

Reference

Signal

Sourc

Common-

Mode Nois

and So O

MIO-16 I/O Connector AT-MIO-16D Board in NRSE Input Configuration

1-2

Figure 2-30. Single-Ended Input Connections for Grounded Signal Sources

Common-Mode Signal Rejection Considerations

Instrumentation

- V

Amplifier

Measured Voltage

Figures 2-27 and 2-30, located earlier in this chapter, show connections for signal sources that are already referenced to some ground point with respect to the AT-MIO-16D. In these cases, the instrumentation amplifier can reject any voltage due to ground potential differences between the signal source and the AT-MIO-16D. In addition, with differential input connections, the instrumentation amplifier can reject common-mode noise pickup in the leads connecting the signal sources to the AT-MIO-16D.

The common-mode input range of the AT-MIO-16D instrumentation amplifier is defined as the magnitude of the greatest common-mode signal that can be rejected.

The common-mode input range for the AT-MIO-16D depends on the size of the differential input signal (V

diff

= V

- V

) and the gain setting of the instrumentation amplifier. The exact

formula for the allowed common-mode input range is as follows:

cm-max

where the maximum value for V

±10 V range V

0 to +10 V range V

±5 V range V

= ± (12 V -

is as follows:

diff

diff-max diff-max diff-max

= ±10 V

= 10 V

= ±5 V

diff * Gain

)

AT-MIO-16D User Manual 2-32 © National Instruments Corporation

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Chapter 2 Configuration and Installation

For example, for a differential voltage as large as 20 mV and a gain of 500, the largest common

mode voltage that can be rejected is ±7 V. However, if the differential signal is 10 mV with a gain of 500, ±9.5-V common-mode voltage can be rejected.

The common-mode voltage is measured with respect to the AT-MIO-16D ground and can be calculated by the following formula:

where V

cm-actual

is the signal at the positive (+) input of the instrumentation amplifier and V

+ V

is the

signal at the negative (-) input of the instrumentation amplifier.

If the input signal common-mode range exceeds ±7 V with respect to the AT-MIO-16D ground,

you need to limit the amount of floating that occurs between the signal ground and the AT-MIO-16D ground.

Analog Output Signal Connections

Pins 20 through 23 of the MIO-16 I/O connector are analog output signal pins.

Pins 20 and 21 are the DAC0 OUT and DAC1 OUT signal pins. DAC0 OUT is the voltage output signal for analog output channel 0. DAC1 OUT is the voltage output signal for analog output channel 1.

Pin 22, EXTREF, is the external reference input for both analog output channels. You must configure each analog output channel individually for external reference selection in order for the signal applied at the external reference input to be used by that channel. Analog output configuration instructions are included under the Analog Output Configuration section earlier in this chapter.

The following ranges and ratings apply to the EXTREF input:

Useful input voltage range: ±10 V peak with respect to AO GND Absolute maximum ratings: ±25 V peak with respect to AO GND

Pin 23, AO GND, is the ground reference point for both analog output channels and for the external reference signal.

Figure 2-31 shows how to make analog output connections and the external reference input connection to the AT-MIO-16D board. If neither channel is configured to use an external reference signal, do not connect anything to the EXTREF pin.

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Configuration and Installation Chapter 2

EXTREF

DAC0 OUT

External Reference Signal (Optional)

ref

Loa

VOUT 0

AO GND

Channel 0

VOUT 1

Loa

MIO-16 I/O Connector

DAC1 OUT

Channel 1

Analog Output Channels

AT-MIO-16D Boar

Figure 2-31. Analog Output Connections

The external reference signal can be either a DC or an AC signal. This reference signal is multiplied by the DAC code to generate the output voltage. The DACs in the analog output channels are rated for -82 dB total harmonic distortion with a 1 kHz, 6-Vrms sine wave reference signal and with the DACs set at their maximum (full-scale) digital value.

Digital I/O Signal Connections

Pins 24 through 32 of the MIO-16 I/O connector are digital I/O signal pins associated with the MIO-16 circuitry of the AT-MIO-16D board.

Pins 25, 27, 29, and 31 are connected to the digital lines ADIO<3..0> for digital I/O port A. Pins 26, 28, 30, and 32 are connected to the digital lines BDIO<3..0> for digital I/O port B. Pin 24, DIG GND, is the digital ground pin for both digital I/O ports. Ports A and B can be programmed individually to be inputs or outputs.

The following specifications and ratings apply to the MIO-16 digital I/O lines.

Absolute maximum voltage input rating 5.5 V with respect to DIG GND

Digital input specifications (referenced to DIG GND):

input logic high voltage 2 V minimum

input logic low voltage 0.8 V maximum

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Chapter 2 Configuration and Installation

IIH input current load,

logic high input voltage 40 µA maximum

input current load,

logic low input voltage -120 µA maximum

Digital output specifications (referenced to DIG GND):

output logic high voltage 2.4 V minimum

output logic low voltage 0.5 V maximum

IOH output source current, logic high 2.6 mA maximum

IOH output sink current, logic low 24 mA maximum

With these specifications, each digital output line can drive 11 standard TTL loads and over 50 LS

TTL loads. The MIO-16 circuitry digital I/O lines are pulled up through 100-kΩ resistors to +5 V.

Figure 2-32 depicts signal connections for three typical digital I/O applications.

+5 V

LED

+5 V

Switch

TTL Signal

MIO-16 I/O Connector

Port A

ADIO<3..0>

Port B

BDIO<3..0>

DIG GND

AT-MIO-16D Boar

Figure 2-32. Digital I/O Connections

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Configuration and Installation Chapter 2

In Figure 2-32, port A is configured for digital output, and port B is configured for digital input. Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch in Figure 2-32. Digital output applications include sending TTL signals and driving external devices such as the LED shown in Figure 2-32.

Power Connections

Pins 34 and 35 of the MIO-16 I/O connector provide +5 V from the PC AT power supply. These pins are referenced to DIG GND and can be used to power external digital circuitry.

Power rating: 1 A at +5 V ± 10%

Warning: These +5 V power pins should not be directly connected to analog or digital ground

or to any other voltage source on the AT-MIO-16D or any other device. Doing so can damage the AT-MIO-16D and the PC AT. National Instruments is not liable for damages resulting from such a connection. A spare MIO-16 fuse is provided in case the power rating is inadvertently exceeded. You should use this fuse only after the cause of the initial problem is known, so as not to blow the spare fuse as well.

Timing Connections

Pins 36 through 50 of the MIO-16 I/O connector are connections for timing I/O signals. Pins 36 through 40 carry signals used for data acquisition timing. These signals are explained under the Data Acquisition Timing Connections section later in this chapter. Pins 41 through 50 carry general-purpose timing signals provided by the onboard Am9513A Counter/Timer. These signals are explained under the General-Purpose Timing Signal Connections section later in this chapter.

Data Acquisition Timing Connections

The data acquisition timing signals are SCANCLK, EXTSTROBE*, START TRIG*, STOP TRIG, and EXTCONV*.

SCANCLK is an output signal that generates a high-to-low edge whenever an A/D conversion begins. SCANCLK pulses only when scanning is enabled on the AT-MIO-16D. SCANCLK is

normally high and pulses low for approximately 1 µsec after the A/D conversion begins. The low-

to-high edge signals that the input signal has been acquired. This signal can be used to clock external analog input multiplexers. The SCANCLK signal is driven by one LS TTL gate.

A low pulse is generated on the EXTSTROBE* pin when the External Strobe Register is loaded (see the External Strobe Register section in Chapter 4, Programming). Figure 2-33 shows the timing for the EXTSTROBE* signal.

t w

t w approx. 200 nsec

Figure 2-33. EXTSTROBE* Signal Timing

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Chapter 2 Configuration and Installation

The pulse is typically 200 nsec in width. The EXTSTROBE* signal can be used by an external device to latch signals or trigger events. The EXTSTROBE* signal is an LS TTL signal.

A/D conversions can be externally triggered with the EXTCONV* pin. Applying an active low pulse to the EXTCONV* signal initiates an A/D conversion. The A/D conversion is initiated by the low-to-high edge of the applied pulse. Figure 2-34 shows the timing requirements for the EXTCONV* signal.

t w

A/D conversion starts within 250 nsec from this point

t w

50 nsec minimum

Figure 2-34. EXTCONV* Signal Timing

The minimum allowed pulse width is 50 nsec. An A/D conversion starts within 250 nsec of the low-to-high edge. There is no maximum pulse width limitation. EXTCONV* should be high for at least 50 nsec before going low. The EXTCONV* signal is one LS TTL load and is pulled up to

+5 V through a 4.7-kΩ resistor.

Note: EXTCONV* is also driven by the output of Counter 3 of the Am9513A Counter/Timer.

This counter is also referred to as the sample-interval counter. The output of Counter 3 must be disabled to a high-impedance state if A/D conversions are to be controlled by pulses applied to the EXTCONV* pin. If Counter 3 is used to control A/D conversions, its output signal can be monitored at the EXTCONV* pin.

You can initiate any data acquisition sequence controlled by the onboard sample-interval and sample counters by an external trigger applied to the START TRIG* pin. If conversions are generated by the EXTCONV* signal, START TRIG* does not affect the acquisition timing. Once the two counters are initialized and armed, applying a falling edge to the START TRIG* pin starts the counters, thereby initiating a data acquisition sequence.

The data acquisition operation is initiated by the high-to-low edge of the applied pulse. Figure 2-35 shows the timing requirements for the START TRIG* signal.

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Configuration and Installation Chapter 2

w 50 nsec minimum

First A/D conversion starts within one sample interval from this point

Figure 2-35. START TRIG* Signal Timing

The minimum allowed pulse width is 50 nsec. The first A/D conversion starts within one sample interval from the high-to-low edge. The sample interval is controlled by Counter 3.

There is no maximum pulse width limitation; however, START TRIG* should be high for at least 50 nsec before going low. The START TRIG* signal is one LS TTL load and is pulled up to +5

V through a 4.7-kΩ resistor.

The STOP TRIG pin is used during AT-MIO-16D pretriggered data acquisition operations. In pretriggered mode, data is acquired but no sample counting occurs until a rising edge is applied to the STOP TRIG pin. This causes the sample counter to then start counting conversions. The acquisition then completes when the sample counter decrements to zero. This mode acquires data both before and after a hardware trigger is received. Figure 2-36 shows the timing requirements for the STOP TRIG signal.

STOP TRIG

w 50 nsec minimum

First sample counting occurs within one sample interval from this point

Figure 2-36. STOP TRIG Signal Timing

The STOP TRIG signal is one LS TTL load and is pulled up to +5 V through a 4.7-kΩ resistor.

General-Purpose Timing Signal Connections

The general-purpose timing signals include the GATE, SOURCE, and OUT signals for the Am9513A Counters 1, 2, and 5, and the FOUT signal generated by the Am9513A. Counters 1, 2,

AT-MIO-16D User Manual 2-38 © National Instruments Corporation

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Chapter 2 Configuration and Installation

and 5 of the Am9513A Counter/Timer can be used for general-purpose applications, such as pulse and square wave generation, event counting, and pulse-width, time-lapse, and frequency measurements. For these applications, SOURCE and GATE signals can be directly applied to the counters from the I/O connector, and the counters are programmed for various operations.

The Am9513A Counter/Timer is described briefly in Chapter 3, Theory of Operation. For detailed programming information, consult Appendix E, Am9513A Data Sheet. For detailed applications information, consult the Am9513A/Am9513 System Timing Controller technical manual published by Advanced Micro Devices, Inc.

You can produce pulses and square waves by programming Counter 1, 2, or 5 to generate a pulse signal at its OUT output pin or to toggle the OUT signal each time the counter reaches the terminal count.

For event counting, program one of the counters to count rising or falling edges applied to any of the Am9513A SOURCE inputs. The counter value can then be read to determine the number of edges that have occurred. You can gate counter operation on and off during event counting.

Figure 2-37 shows connections for a typical event-counting operation where a switch is used to gate the counter on and off.

+5 V

4.7 kΩ

SOURCE

OUT

GATE

Switch

Signal Source

MIO-16 I/O Connector

DIG GND

AT-MIO-16D Boar

Counter

Figure 2-37. Event-Counting Application with External Switch Gating

To perform pulse-width measurement, program a counter to be level gated. The pulse to be measured is applied to the counter GATE input. Program the counter to count while the signal at the GATE input is either high or low. If the counter is programmed to count an internal timebase, then the pulse width is equal to the counter value multiplied by the timebase period.

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Configuration and Installation Chapter 2

For time-lapse measurement, program a counter to be edge gated. Apply an edge to the counter GATE input to start the counter. You can program the counter to start counting after receiving either a high-to-low edge or a low-to-high edge. If the counter is programmed to count an internal timebase, then the time lapse since receiving the edge is equal to the counter value multiplied by the timebase period.

To measure frequency, program a counter to be level gated and the rising or falling edges are counted in a signal applied to a SOURCE input. The gate signal applied to the counter GATE input is of some known duration. In this case, program the counter to count either rising or falling edges at the SOURCE input while the gate is applied. The frequency of the input signal is then the count value divided by the known gate period. Figure 2-38 shows the connections for a frequency measurement application. You could use a second counter to generate the gate signal in this application.

+5 V

4.7 kΩ

SOURCE

OUT

GATE

Signal

Source

MIO-16 I/O Connector

Gate

Source

Counter

DIG GND

AT-MIO-16D Boar

Figure 2-38. Frequency Measurement Application

Two or more counters can be concatenated by tying the OUT signal from one counter to the SOURCE signal of another counter. You can then treat the counters as one 32-bit or 48-bit counter for most counting applications.

The GATE, SOURCE, and OUT signals for Counters 1, 2, and 5, and the FOUT output signal are tied directly from the Am9513A input and output pins to the I/O connector. In addition, the

GATE, SOURCE, and OUT1 pins are pulled up to +5 V through a 4.7-kΩ resistor. The input

and output ratings and timing specifications for the Am9513A signals are given below.

AT-MIO-16D User Manual 2-40 © National Instruments Corporation

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Chapter 2 Configuration and Installation

The following specifications and ratings apply to the Am9513A I/O signals:

Absolute maximum voltage input rating -0.5 V to +7.0 V with respect to DIG GND

Am9513A digital input specifications (referenced to DIG GND):

input logic high voltage 2.2 V minimum

input logic low voltage 0.8 V maximum

Input load current ±10 µA maximum

Am9513A digital output specifications (referenced to DIG GND):

output logic high voltage 2.4 V minimum

output logic low voltage 0.4 V maximum

output source current at V

output sink current at V

200 µA maximum

3.2 mA maximum

Output current, high-impedance state ±25 µA maximum

Figure 2-39 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the OUT output signals of the Am9513A.

SOURCE

GATE

OUT

gsu

out

gsu 100 nsec minimu

gh 10 nsec minimu

gw 145 nsec minimu

out 300 nsec maximu

145 nsec minimu

70 nsec minimu

Figure 2-39. General-Purpose Timing Signals

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Configuration and Installation Chapter 2

The GATE and OUT signal transitions in Figure 2-39 are referenced to the rising edge of the SOURCE signal. This timing diagram assumes that the counters are programmed to count rising edges. The same timing diagram, with the source signal inverted and referenced to the falling edge of the source signal, applies to the case in which the counter is programmed to count falling edges.

The signal applied at a SOURCE input can be used as a clock source by any of the Am9513A counter/timers and by the Am9513A frequency division output FOUT. The signal applied to a SOURCE input must not exceed a frequency of 6 MHz for proper operation of the Am9513A. The Am9513A counters can be individually programmed to count rising or falling edges of signals applied at any of the Am9513A SOURCE or GATE input pins.

In addition to the signals applied to the SOURCE and GATE inputs, the Am9513A generates five internal timebase clocks from the clock signal supplied by the AT-MIO-16D. This clock signal is selected by the W5 jumper and then divided by 10. The factory default value is 1 MHz into the Am9513A (10-MHz clock signal on the AT-MIO-16D). The five internal timebase clocks can be used as counting sources, and these clocks have a maximum skew of 75 nsec between them. The SOURCE signal shown in Figure 2-38 represents any of the signals applied at the SOURCE inputs, GATE inputs, or internal timebase clocks. See Appendix E, Am9513A Data Sheet, for further details.

Specifications for signals at the GATE input are referenced to the signal at the SOURCE input or one of the Am9513A internally generated signals. Figure 2-39 shows the GATE signal referenced to the rising edge of a source signal. The gate must be valid (either high or low) at least 100 nsec before the rising or falling edge of a source signal for the gate to take effect at that source edge (as shown by t

and tgh in Figure 2-39). Similarly, the gate signal must be held for at least 10 nsec

gsu after the rising or falling edge of a source signal for the gate to take effect at that source edge. The gate high or low period must be at least 145 nsec in duration. If an internal timebase clock is used, the gate signal cannot be synchronized with the clock. In this case, gates applied close to a source edge take effect either on that source edge or on the next one. This arrangement provides an uncertainty of one source clock period with respect to unsynchronized gating sources.

Signals generated at the OUT output are referenced to the signal at the SOURCE input or to one of the Am9513A internally generated clock signals. Figure 2-39 shows the OUT signal referenced to the rising edge of a source signal. Any OUT signal state changes occur within 300 nsec after the source signal rising or falling edge.

AT-MIO-16D User Manual 2-42 © National Instruments Corporation

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Chapter 2 Configuration and Installation

DIO-24 I/O Connector Pin Description

The I/O connector contains 100 pins that can be split into two standard 50-pin connectors via a cable assembly such as a Type NB5 ribbon cable (see Figure 1-2). One 50-pin connector contains signals associated with the MIO-16 circuitry, while the other 50-pin connector contains signals for the DIO-24 circuitry.

Figure 2-40 shows the pin assignments for the DIO-24 circuitry I/O connector.

Warning: Connections that exceed any of the maximum ratings of input or output signals on the

AT-MIO-16D may result in damage to the AT-MIO-16D board and to the PC. Maximum ratings for each signal are given in this chapter under the discussion of that signal. National Instruments is not liable for any damages resulting from any such signal connections.

PC7 PC6 PC5

PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5 PB4 PB3

PB2 PB1

PB0 PA7 PA6

PA5 PA4 PA3 PA2 PA1

PA0

+5 V

109 1211 1413 1615 1817

4847 50

GND

65 87

GND GND GND GND GND GND GND

2019

GND

2221

GND

2423

GND

2625 2827

GND GND

3029 3231

GND

3433

GND

3635

GND

3837 4039

GND GND

4241

GND

4443

GND

4645

GND

Figure 2-40. DIO-24 I/O Connector Pin Assignments

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Configuration and Installation Chapter 2

DIO-24 Signal Connection Descriptions

Pin Signal Name Reference Description

1, 3, 5, PC7 through PC0 DIGGND Bidirectional data lines for Port C. 7, 9, 11, PC7 is the MSB, PC0 the LSB. 13, 15

17, 19, 21, PB7 through PB0 DIGGND Bidirectional data lines for Port B. 23, 25, 27, PB7 is the MSB, PB0 the LSB. 29, 31

33, 35, 37, PA7 through PA0 DIGGND Bidirectional data lines for Port A. 39, 41, 43, PA7 is the MSB, PA0 the LSB. 45, 47

49 +5 V DIGGND This pin provides +5 VDC.

All even- DIGGND These signals are connected to the PC ground numbered signal. pins

The absolute maximum voltage input rating is -0.5 to +7.0 V with respect to GND.

Power Connections

Pin 49 of the DIO-24 I/O connector provides +5 V from the PC AT power supply. This pin is referenced to DIG GND and can be used to power external digital circuitry.

Power rating: 1 A at +5 V ± 10%

Warning: This +5-V power pin should not be directly connected to analog or digital ground or

to any other voltage source on the AT-MIO-16D or any other device. Doing so can damage the AT-MIO-16D and the PC AT. National Instruments is not liable for damages resulting from such a connection. A spare DIO-24 fuse is provided in case the power rating is inadvertently exceeded. You should use this fuse only after the cause of the initial problem is known, so as not to blow the spare fuse as well.

Port C Pin Assignments

The signals assigned to Port C depend on the mode in which the 82C55A is programmed. In Mode 0, Port C is considered two 4-bit I/O ports. In Modes 1 and 2, Port C is used for status and handshaking signals with two or three I/O bits mixed in. Table 2-11 summarizes the signal assignments of Port C for each programmable mode. See Chapter 4, Programming, for programming information.

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Chapter 2 Configuration and Installation

Table 2-11. Port C Signal Assignments

Programming

Group A Group B

Mode

PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

Mode 0

Mode 1 Input

Mode 1 Output

Mode 2

I/O I/O I/O I/O I/O I/O I/O I/O

I/O I/O IBF

OBFA* ACKA* I/O I/O INTR

OBFA* ACKA* IBF

STBA* INTR

STBB* IBFB

ACKB* OBFB* INTR

I/O I/O I/O

INTR

* Indicates that the signal is active low.

Timing Specifications

This section lists the timing specifications for handshaking with the DIO-24 circuitry. The handshaking lines STB* and IBF synchronize input transfers. The handshaking lines OBF* and ACK* synchronize output transfers.

The following signals are used in the timing diagrams that follow.

Name Type Description

STB* input Strobe Input

A low signal on this handshaking line loads data into the input latch.

IBF output Input Buffer Full

A high signal on this handshaking line indicates that data has been loaded into the input latch. This is an input acknowledge signal.

ACK* input Acknowledge Input

A low signal on this handshaking line indicates that the data written from the selected port has been accepted. This signal is a response from the external device that it has received the data from the ATMIO-16D.

OBF* output Output Buffer Full

A low signal on this handshaking line indicates that data has been written from the selected port.

INTR output Interrupt Request

This signal becomes high when the 82C55A is requesting service during a data transfer. The appropriate DIO interrupt enable bits must be set to generate this signal.

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Configuration and Installation Chapter 2

Name Type Description (continued)

RD* internal Read Signal

This signal is the read signal generated from the control lines of the PC.

WR* internal Write Signal

This signal is the write signal generated from the control lines of the PC.

DATA bidirectional Data Lines at the Selected Port

This signal indicates when the data on the data lines at a selected port is or should be available.

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Chapter 2 Configuration and Installation

DIO-24 Mode 1 Input Timing

The following are the timing specifications for an input transfer in Mode 1:

T2 T4

STB *

IBF

INTR

RD *

T3 T5

DATA

Name Description Minimum Maximum

T1 STB* Pulse Width 500 – T2 STB* = 0 to IBF = 1 – 300 T3 Data before STB*= 1 0 – T4 STB* = 1 to INTR = 1 – 300 T5 Data after STB* = 1 180 – T6 RD* = 0 to INTR = 0 – 400 T7 RD* = 1 to IBF = 0 – 300

All timing values are in nanoseconds.

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Configuration and Installation Chapter 2

DIO-24 Mode 1 Output Timing

The following are the timing specifications for an output transfer in Mode 1:

WR*

OBF*

INTR

ACK*

DATA

Name Description Minimum Maximum

T1 WR* = 0 to INTR = 0 – 450 T2 WR* = 1 to Output – 350 T3 WR* = 1 to OBF* = 0 – 650 T4 ACK* = 0 to OBF* = 1 – 350 T5 ACK* Pulse Width 300 – T6 ACK* = 1 to INTR = 1 – 350

All timing values are in nanoseconds.

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Chapter 2 Configuration and Installation

DIO-24 Mode 2 Bidirectional Timing

The following are the timing specifications for bidirectional transfers in Mode 2:

WR *

OBF *

INTR

ACK *

STB *

IBF

RD *

DATA

T2 T5 T8 T9

Name Description Minimum Maximum

T1 WR* = 1 to OBF* = 0 – 650 T2 Data before STB*= 1 0 – T3 STB* Pulse Width 500 – T4 STB* = 0 to IBF = 1 – 300 T5 Data after STB* = 1 180 – T6 ACK* = 0 to OBF = 1 – 350 T7 ACK* Pulse Width 300 – T8 ACK* = 0 to Output – 300 T9 ACK* = 1 to Output Float 20 250 T10 RD* = 1 to IBF = 0 – 300

T10

All timing values are in nanoseconds.

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Configuration and Installation Chapter 2

Cabling and Field Wiring

This section discusses cabling and field wiring guidelines for the AT-MIO-16D board.

Field Wiring Considerations

Accuracy of measurements made with the AT-MIO-16D can be seriously affected by environmental noise if proper considerations are not taken into account when running signal wires between signal sources and the AT-MIO-16D board. The following recommendations mainly apply to analog input signal routing to the AT-MIO-16D board, though they are applicable for signal routing in general.

You can minimize noise pickup and maximize measurement accuracy by doing the following:

• Use individually shielded, twisted-pair wires to connect analog input signals to the AT-MIO-16D. With this type of wire, the signals attached to the CH+ and CH- inputs are twisted together and then covered with a shield. This shield is then connected only at one point to the signal source ground. This kind of connection is required for signals traveling through areas with large magnetic fields or high electromagnetic interference.

• Use differential analog input connections to reject common-mode noise.

The following recommendations apply for all signal connections to the AT-MIO-16D:

• Physically separate AT-MIO-16D signal lines from high-current or high-voltage lines. These lines are capable of inducing currents in or voltages on the AT-MIO-16D signal lines if they run in parallel paths at a close distance. Reduce the magnetic coupling between lines by separating them by a reasonable distance if they run in parallel, or by running the lines at right angles to each other.

• Do not run AT-MIO-16D signal lines through conduits that also contain power lines.

• Protect AT-MIO-16D signal lines from magnetic fields caused by electric motors, welding equipment, breakers, or transformers by running the AT-MIO-16D signal lines through special metal conduits.

MIO-16 Cabling Considerations

National Instruments has a cable termination accessory–the CB-100–for use with the AT-MIO16D board. This kit includes two terminated 50-conductor flat ribbon cables and two 50-pin CB50 connector blocks. You can attach signal I/O leads to screw terminals on the connector block and thereby be connected to the AT-MIO-16D I/O connector.

The CB-100 is useful for prototyping an application or in situations where AT-MIO-16D interconnections are frequently changed. Once you develop a final field wiring scheme, however, you may want to develop your own cable. This section contains information and guidelines for design of such a cable.

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The MIO-16 circuitry I/O connector is a 50-pin female ribbon-cable header. The manufacturer part numbers for this header are as follows:

Electronic Products Division/3M part number 3596-5002 T&B/Ansley Corporation part number 609-5007

The mating connector for the MIO-16 circuitry is a 50-position ribbon socket connector, polarized, with strain relief. National Instruments uses a polarized (keyed) connector to prevent inadvertent upside-down connection to the AT-MIO-16D. Recommended manufacturer part numbers for this mating connector are as follows:

Electronic Products Division/3M part number 3425-7650 T&B/Ansley Corporation part number 609-5041CE

The following is the standard ribbon cable (50-conductor, 28 AWG, stranded) that can be used with these connectors:

Electronic Products Division/3M part number 3365/50 T&B/Ansley Corporation part number 171-50

In making your own cabling, you may decide to shield your cables. The following guidelines may help:

• For the analog input signals, shielded twisted-pair wires for each analog input pair yield the best results, assuming that differential inputs are used. Tie the shield for each signal pair to the ground reference at the source.

• The analog lines, pins 1 through 23, should be routed separately from the digital lines, pins 24 through 50.

• When using a cable shield, use separate shields for the analog and digital halves of the cable. Failure to do so will result in noise from switching digital signals coupling into the analog signals.

DIO-24 Cabling Considerations

The DIO-24 circuitry of the AT-MIO-16D can be interfaced to a wide range of printers, plotters, test instruments, I/O racks and modules, screw terminal panels, and almost any device with a parallel interface. The DIO-24 circuitry I/O connector is a standard 50-pin header connector. The pin assignments are compatible with the standard 24-channel I/O module mounting racks (such as those manufactured by Opto 22 and Gordos).

The CB-100 cable termination accessory is available from National Instruments for use with the DIO-24 circuitry of the AT-MIO-16D. This kit includes two 50-conductor flat ribbon cables and two 50-pin CB-50 connector blocks. Signal input and output wires can be attached to screw terminals on the connector block and are therefore connected to the DIO-section I/O connector.

The CB-100 is useful for initial prototyping of an application or in situations where DIO-section interconnections are frequently changed. Once you develop a final field wiring scheme, however, you may want to develop your own cable. This section contains information and guidelines for the design of custom cables.

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Configuration and Installation Chapter 2

The DIO-24 circuitry I/O connector is a 50-pin female ribbon-cable header. The manufacturers and the appropriate part numbers for this connector are as follows:

Electronic Products Division/3M part number 3596-5002 T&B/Ansley Corporation part number 609-5007

The mating connector for the DIO section is a 50-position, polarized, ribbon socket connector with strain relief. National Instruments uses a polarized (keyed) connector to prevent inadvertent upside-down connection to the DIO section . Recommended manufacturers and the appropriate part numbers for this mating connector are as follows:

Electronic Products Division/3M part number 3425-7650 T&B/Ansley Corporation part number 609-5041CE

The standard ribbon cable (50-conductor, 28 AWG, stranded) that can be used with these connectors is as follows:

Electronic Products Division/3M part number 3365/50 T&B/Ansley Corporation part number 171-50

If you plan to use the DIO section of the AT-MIO-16D for a communications application, you may need shielded cables to meet FCC requirements. The DIO-section I/O bracket has been designed so that the shield of the I/O cable can be grounded through the computer chassis when a mating connector such as the following is used:

AMP Special Industries part number 2-746483-2

Many varieties of shielded ribbon cable are available to work with the mating connector listed previously. One type of shielded cable encloses a standard ribbon cable with a shielded jacket. Recommended manufacturers and the appropriate part numbers for this type of cable are as follows:

Belden Electronic Wire and Cable part number 9L28350 T&B/Ansley Corporation part number 187-50

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This chapter contains a functional overview of the AT-MIO-16D and explains the operation of each functional unit making up the AT-MIO-16D.

MIO-16 Functional Overview

The block diagram in Figure 3-1 is a functional overview of the MIO-16 circuitry of the AT-MIO-16D board.

RTSI Bus

RTSI Bus Interface

PC AT I/O Channel

Timing

Internal

Data Bus

Internal

Control Bus

PC AT I/O Channel Interface

Data

Acquisition

Timing

I/O

Analog

Input

Analog

Output

Digital

I/O

Figure 3-1. AT-MIO-16D MIO-16 Circuitry Block Diagram

I/O Connector

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The following are the major components making up the MIO-16 section of the AT-MIO-16D board:

¥ PC AT I/O channel interface circuitry

¥ Analog input and data acquisition circuitry

¥ Analog output circuitry

¥ Digital I/O circuitry

¥ Timing I/O circuitry

¥ RTSI bus interface circuitry

The internal data and control buses interconnect the components. The theory of operation of each of these components is explained in the remainder of this chapter.

PC AT I/O Channel Interface Circuitry

The AT-MIO-16D board is a full-size 16-bit PC AT I/O channel adapter. The PC AT I/O channel consists of a 24-bit address bus, a 16-bit data bus, a direct memory access (DMA) arbitration bus, interrupt lines, and several control and support signals. The components making up the AT-MIO-16D PC AT I/O channel interface circuitry are shown in Figure 3-2.

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Address

Bus

I/O Channel

Control Lines

Data

Bus

PC AT I/O Channel

DMA Request

Acknowledge

IRQ

DMA

Address Latches

PC AT I/O

Channel

Timing

Interface

Data

Buffers

DMA

Control

Circuitry

Interrupt

Control

Circuitry

Address Decoder

Read & Write Signals

Internal Data Bus

AT-MIO-16D DMA Request

AT-MIO-16D DMA Acknowledge & Terminal Count

AT-MIO-16D Interrupt Request

Figure 3-2. PC AT I/O Channel Interface Circuitry Block Diagram

The PC AT I/O channel interface circuitry consists of address latches, address decoder circuitry, data buffers, PC AT I/O channel interface timing signals, interrupt circuitry, and DMA arbitration circuitry. The PC AT I/O channel interface circuitry generates the signals necessary to control and monitor the operation of the AT-MIO-16D multiple function circuitry.

The PC AT I/O channel has 24 address lines; the AT-MIO-16D uses 10 of these lines to decode the board address. Therefore, the board address range is hex 000 to 3FF. SA5 through SA9 are used to generate the board enable signal. SA0 through SA4 are used to select onboard registers. These address lines are latched by the address latches at the beginning of an I/O transfer. The latched address lines send the same address to the address-decoding circuitry during the entire I/O transfer cycle. The address-decoding circuitry generates the register select signals that specify which AT-MIO-16D register is being accessed. The data buffers control the direction of data transfer on the bidirectional data lines based on whether the transfer is a read or a write.

The PC AT I/O channel interface timing signals are used to generate read-and-write signals and to define the transfer cycle. A transfer cycle can be either an 8-bit or a 16-bit data I/O operation. The AT-MIO-16D returns signals to the PC AT I/O channel to indicate when the board has been

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accessed, when the board is ready for another transfer, and the data bit size of the current I/O transfer.

The interrupt control circuitry routes any enabled interrupt requests to the selected interrupt request line. The interrupt requests are tristate output signals allowing the AT-MIO-16D board to share the interrupt lines with other devices. Eleven interrupt request lines are available for use by the AT-MIO-16D: IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, IRQ9, IRQ10, IRQ11, IRQ12, IRQ14, and IRQ15. Five different interrupts can be generated by the MIO-16 circuitry of the AT-MIO-16D:

¥ When an A/D conversion is available to be read from the A/D FIFO memory

¥ When a data acquisition operation completes

¥ When a DMA terminal count pulse is received

¥ When a rising edge signal is detected on the OUT2 pin of the Am9513A Counter/Timer

¥ When either an OVERFLOW or an OVERRUN error occurs

Each one of these interrupts is individually enabled and cleared. See Chapter 4, Programming, for more information about programming with interrupts.

The DMA control circuitry generates DMA requests whenever an A/D measurement is available from the A/D FIFO, if the DMA transfer is enabled. The DMA circuitry supports full PC AT I/O channel 16-bit DMA transfers. DMA channels 5, 6, and 7 of the PC AT I/O channel are available for such transfers. With the DMA circuitry, either single-channel transfer mode or dual-channel transfer mode can be selected for DMA transfer.

Analog Input and Data Acquisition Circuitry

The AT-MIO-16D handles 16 channels of analog input with software-programmable gain and 12bit A/D conversion. In addition, the AT-MIO-16D contains data acquisition circuitry for automatic timing of multiple A/D conversions and includes advanced options such as external triggering, gating, and clocking. Figure 3-3 shows a block diagram of the analog input and data acquisition circuitry.

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Figure 3-3. Analog Input and Data Acquisition Circuitry Block Diagram

ACH0 ACH1 ACH2 ACH3 ACH4 ACH5 ACH6 ACH7

AI SENSE

ACH8

ACH9 ACH10 ACH11 ACH12 ACH13 ACH14 ACH15

SCAN CLK

START TRIG

EXT CONV

STOP TRIG

MUX

I/O Connector

Start Trigger

External Convert Stop Trigger

MUX0OUT

MUX0EN

MUX1OUT MUX1EN

SCAN CLK

Mux Mode

Selection

(W6 & W9)

Programmable Gain Amplifier

GAIN1 GAIN0

MA3 MA2 MA1 MA0

Acquisition

S/H Amplifier

Unipolar/Bipolar

Selection (W4)

10 V/20 V

Selection

LASTONE

CONVERT

Data

Timing

Converter

(W1)

Multi-

Plexer/

Gain

Memory

MUX CTR CLK

Counter/Timer Signals

Analog

Digital

Sign

Exten-

sion

A/D

Data

A/D

FIFO

MUXGAIN WR

Mux

Counter

Data

A/D RD

Data

CONV AVAIL

Data

MUXCTR WR

A/D RD

PC AT I/O Channel

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Theory of Operation Chapter 3

Analog Input Circuitry

The analog input circuitry consists of an input multiplexer, multiplexer-mode selection jumpers, a software-programmable gain instrumentation amplifier, a sample-and-hold amplifier, a 12-bit analog-to-digital converter (ADC), and a 12-bit FIFO with a 16-bit sign extension option.

Analog Input Multiplexers

The input multiplexer consists of two CMOS analog input multiplexers and has 16 analog input channels. Multiplexer MUX0 is connected to analog input channels 0 through 7. Multiplexer MUX1 is connected to analog input channels 8 through 15. The input multiplexers provide input overvoltage protection of ±35 V powered on and ±20 V powered off.

Analog Input Mode Selection

The multiplexer-mode selection jumpers configure the analog input channels as 16 single-ended inputs or 8 differential inputs. When single-ended mode is selected, the outputs of the two multiplexers are tied together and routed to the positive (+) input of the instrumentation amplifier. The negative (-) input of the instrumentation amplifier is tied to the AT-MIO-16D ground for RSE input or to the analog return of the input signals via the AI SENSE input on the I/O connector for NRSE input. When DIFF mode is selected, the output of MUX0 is routed to the positive (+) input of the instrumentation amplifier, and the output of MUX1 is routed to the negative (-) input of the instrumentation amplifier.

The Instrumentation Amplifier

The instrumentation amplifier fulfills two purposes on the AT-MIO-16D board. It converts a differential input signal into a single-ended signal with respect to the AT-MIO-16D ground for a minimum input common-mode rejection ratio of 85 dB. This conversion allows the input analog signal to be extracted from any common-mode voltage or noise before being sampled and converted. The instrumentation amplifier also applies gain to the input signal, allowing an input analog signal to be amplified before being sampled and converted, and thus increasing measurement resolution and accuracy. The gain of the instrumentation amplifier is selected under software control. The AT-MIO-16DL (L stands for low-level signals) provides gains of 1, 10, 100, and 500. The AT-MIO-16DH (H stands for high-level signals) provides gains of 1, 2, 4, andÊ8.

Channel Selection Circuitry

Selection of the analog input channel and the gain settings is controlled by the mux-gain memory. The mux-gain memory provides two gain control bits to the instrumentation amplifier and four multiplexer address bits to the input multiplexers and multiplexer-mode selection circuitry that select the analog input channels. Operation of the mux-gain memory is explained in more detail in the Data Acquisition Timing Circuitry section later in this chapter.

The sample-and-hold amplifier aids the ADC in performing A/D conversions. At the beginning of an A/D conversion, the sample-and-hold amplifier is put in hold mode, which means that it holds its output voltage at a steady value (the value when the hold period started) regardless of voltage changes at its input. This sample-and-hold amplifier provides the ADC with a steady voltage while

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it is performing an A/D conversion. Without the sample-and-hold amplifier, the analog input signal could change during a conversion, thereby causing errors during A/D conversion. By isolating the ADC from the analog input signals during conversion, you can change the input multiplexer and allow the instrumentation amplifier to settle to a new value while the ADC is converting the old value. This isolation creates a two-stage pipeline and increases and optimizes the performance of the analog input circuitry during high-speed, multiple A/D conversions.

A/D Converter

The ADC is a 12-bit, successive-approximation ADC with a maximum conversion time of 9 msec. The 12-bit resolution allows the converter to resolve its input range into 4,096 different steps. This resolution also provides a 12-bit digital word that represents the value of the input voltage level with respect to the converter input range. The ADC supports three input ranges that are jumper-selectable on the AT-MIO-16D board, -10ÊtoÊ+10 V, -5 to +5 V, or 0 to +10 V.

ADC FIFO Buffer

When an A/D conversion is complete, the ADC clocks the result into the A/D FIFO. The A/D FIFO is 12 bits wide and 512 words deep. This FIFO serves as a buffer to the ADC and provides two benefits. Any time an A/D conversion is complete, the value is saved in the A/D FIFO for later reading, and the ADC is free to start a new conversion. Secondly, the A/D FIFO can collect up to 512 A/D conversion values before any information is lost; thus software or DMA has extra time (512 times the sample interval) to catch up with the hardware. If more than 512 values are stored in the A/D FIFO without the A/D FIFO being read from, an error condition called A/D FIFO overflow occurs and A/D conversion information is lost.

The A/D FIFO generates a signal that indicates when it contains A/D conversion data. You can read the state of this signal from the AT-MIO-16D Status Register. You can use this signal to generate a DMA request signal or to generate an interrupt. Sign-extension circuitry at the A/D FIFO output adds four most significant bits (MSBs), bits 15 through 12, to the 12-bit FIFO output (bits 11 through 0) to produce a 16-bit result.

The sign-extension circuitry is software programmable to generate either straight binary numbers or two's complement numbers. In straight binary mode, bits 15 through 12 are always zero and provide a range of 0 to 4,095. In two's complement mode, the MSB of the 12-bit ADC result, bit 11, is inverted and extended to bits 15 through 12, providing a range of -2,048 to +2,047.

Data Acquisition Timing Circuitry

A data acquisition operation refers to the process of taking a sequence of A/D conversions with the sample interval (the time between successive A/D conversions) carefully timed. The data acquisition timing circuitry consists of various clocks and timing signals. Three types of data acquisition are supported by the AT-MIO-16D boardÐsingle-channel data acquisition, multiplechannel data acquisition with continuous scanning, and multiple-channel data acquisition with interval scanning.

Scanned data acquisition uses the multiplexer counter and the mux-gain memory to automatically switch between analog input channels during data acquisition. Continuous scanning cycles through the mux-gain memory without any delays between cycles. Interval scanning assigns a

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time interval called the scan interval to each cycle through the mux-gain memory. The scan interval is basically the time between starts for each cycle through the mux-gain memory.

Data acquisition timing consists of signals that initiate a data acquisition operation, initiate individual A/D conversions, gate the data acquisition operation, and generate scanning clocks. The sources for these signals can be supplied by timers on the AT-MIO-16D board, by signals connected to the AT-MIO-16D I/O connector, or by signals from other AT Series boards connected to the RTSI bus.

Single Conversions

You can initiate single A/D conversions by applying an active low pulse to the EXTCONV* input on the I/O connector or by writing to the Start Convert Register on the AT-MIO-16D board. During data acquisition, the onboard sample-interval counter (Counter 3 of the Am9513A Counter/Timer) generates pulses that initiate A/D conversions. External control of the sample interval is possible by applying a stream of pulses at the EXTCONV* input. In this case, you have complete external control over the sample interval and the number of A/D conversions performed.

Sample-Interval Timer

The sample-interval timer is a 16-bit down counter that can be used with the five internal timebases of the Am9513A to generate sample intervals from 2 msec to 6 sec (see the Timing I/O Circuitry section later in this chapter). The sample-interval timer can also use any of the external clock inputs to the Am9513A as a timebase. During data acquisition, the sample interval counts down at the rate given by the internal timebase or external clock. Each time the sample-interval timer reaches zero, it generates a pulse and reloads with the programmed sample-interval count. This operation continues until data acquisition halts.

Sample Counter

The onboard sample counter can control data acquisition. Load this counter with the number of samples to be taken during a data acquisition operation. The sample counter can be 16-bit for

counts up to 65,535 or 32-bit for counts up to (232 - 1). If a 16-bit counter is needed, Counter 4 of the Am9513A Counter/Timer is used. If more than 16 bits are needed, Counter 4 is concatenated with Counter 5 of the Am9513A to form a 32-bit counter. The sample counter decrements its count each time the sample-interval counter generates an A/D conversion pulse, and the sample counter stops the data acquisition process when it counts down to zero.

You can trigger the sample counter externally with the STOP TRIG input on the AT-MIO-16D I/O connector. The counter does not begin counting the A/D conversion pulses until a rising edge signal occurs on STOP TRIG. With this method, A/D conversion samples can be collected both before and after a hardware trigger is received.

You can initiate the data acquisition process by writing to the Start DAQ Register on the AT-MIO-16D board or by applying an active low pulse to the START TRIG* input on the AT-MIO-16D I/O connector. These triggers start the sample-interval and sample counters. The sample-interval counter then manages the data acquisition process until the sample counter reaches zero.

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Single-Channel Data Acquisition

During single-channel data acquisition, the mux-gain memory is set up to select the gain and analog input channel before data acquisition is initiated. These gain and multiplexer settings remain constant during the entire data acquisition process; therefore, all A/D conversion data is read from a single channel.

Multiple-Channel (Scanned) Data Acquisition

You perform multiple-channel data acquisition by enabling scanning during data acquisition. You control multiple-channel scanning with the multiplexer counter and the mux-gain memory.

The mux-gain memory consists of 16 words of memory. Each word of memory contains a multiplexer address (4 bits) for input analog channel selection, a gain setting (2 bits), and a bit indicating if the entry is the last in the scan sequence. The mux-gain memory address is controlled by the multiplexer counter. Whenever a mux-gain memory address location is selected, the multiplexer and gain control bits contained in that memory location are applied to the analog input circuitry. For scanning operations, the multiplexer counter steps through successive locations in the mux-gain memory at a rate determined by the scan clock. With the mux-gain memory, therefore, an arbitrary sequence of channels (16 maximum) with a separate gain setting for each channel can be clocked through during a scanning operation.

Both the multiplexer counter and the mux-gain memory can be directly written to through AT-MIO-16D registers. For writing purposes, the multiplexer counter serves as a pointer to the mux-gain memory. The counter can be loaded with any 4-bit value to point to any mux-gain memory location. With this counter, scanning can start at any location in the mux-gain memory.

The SCAN CLK signal is generated from the sample-interval counter. This signal pulses once at the beginning of each A/D conversion and is supplied at the I/O connector. During multiplechannel scanning, the multiplexer counter is incremented repeatedly, thereby sequencing through the mux-gain memory and automatically selecting new channel and gain settings during data acquisition. The MUX CTR CLK signal is generated from the SCAN CLK and provides the pulses that increment the multiplexer counter. MUX CTR CLK can be identical to SCAN CLK, incrementing the multiplexer counter once after every A/D conversion. MUX CTR CLK can also be generated by dividing SCAN CLK by Counter 1 of the Am9513A Counter/Timer. With this method, the multiplexer counter can be incremented once every N A/D conversions such that N conversions can be performed on a single channel and gain selection before switching to the next channel and gain selection.

Data Acquisition Rates

Data acquisition rates (number of samples per second) are determined by the conversion period of the ADC plus the sample-and-hold acquisition time. During multiple-channel scanning, the data acquisition rates are further limited by the settling time of the input multiplexers and instrumentation amplifier. After the input multiplexers are switched, the instrumentation amplifier should be allowed to settle to the new input signal value before an A/D conversion is performed or else high accuracy will not be achieved. The settling time is determined by the gain selected.

Table 3-1 shows the maximum recommended data acquisition rates for both single-channel and multiple-channel data acquisition. The rates in Table 3-1 refer to typical settling accuracies of 0.5 LSBs of the final value.

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Theory of Operation Chapter 3

Table 3-1. AT-MIO-16D Maximum Recommended Data Acquisition Rates

Data Acquisition Type Gain Data Acquisition Rate

Single-channel data acquisition Any gain setting 100 ksamples/sec

Multiple-channel data acquisition Gain = 1, 2, 4, 8 100 ksamples/sec

Gain = 10 100 ksamples/sec Gain = 100 70 ksamples/sec Gain = 500 20 ksamples/sec

Analog Output Circuitry

The AT-MIO-16D provides two channels of 12-bit digital-to-analog (D/A) output. Each analog output channel provides options such as unipolar or bipolar output and internal or external reference voltage selection. Figure 3-4 shows a block diagram of the analog output circuitry.

Bipolar/Unipolar

Selection

DAC0WR

DATA / 12

DAC1WR

PC AT I/O Channel

+10 V (From

A/D

REF)

REF

DAC1 + op-amps

Bipolar/Unipolar

Selection

Internal REF

(W8)

(W7)

DAC1 OUTDAC0 + op-amps

AO GND

DAC0 OUT

EXTREF

I/O Connector

(W2)

(W3)

REF Selection

Figure 3-4. Analog Output Circuitry Block Diagram

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Chapter 3 Theory of Operation

Each analog output channel contains a 12-bit digital-to-analog converter (DAC), output operational amplifiers (op-amps), reference selection jumpers, and unipolar/bipolar output selection jumpers.

The DAC in each analog output channel generates a current proportional to the input voltage reference (V

) multiplied by the digital code loaded into the DAC. Each DAC can be loaded with

ref

a 12-bit digital code by writing to registers on the AT-MIO-16D board. The output op-amps convert the DAC current output to a voltage output provided at the AT-MIO-16D I/O connector DAC0 OUT and DAC1 OUT pins. The analog output of the DACs is updated to reflect the loaded 12-bit digital code in one of two ways: immediately when the 12-bit code is written to the DACs, or when an active low pulse occurs on the Am9513A OUT2 pin. The update method used is selected by the LDAC bit in Command Register 2.

Analog Output Range

The DAC output op-amps can be jumper configured to provide either a unipolar voltage output or a bipolar voltage output range. A unipolar output has an output voltage range of 0 to +V

A bipolar output provides an output voltage range of -V

ref

to +V

-1 LSB V. For unipolar output,

ref

- 1 LSB V.

ref

0 V output corresponds to a digital code word of zero. For bipolar output, the form of the digital code input is jumper selectable. If straight binary form is selected, 0 V output corresponds to a digital code word of 2,048. If two's complement form is selected, 0 V output corresponds to a digital code word of zero. One LSB is the voltage increment corresponding to an LSB change in the digital code word. For unipolar output, 1 LSB = (V

1 LSB = (V

)/2,048.

ref

)/4,096. For bipolar output,

ref

Analog Output Data Coding

The voltage reference source for each DAC is jumper selectable and can be supplied either externally at the EXTREF input or internally. The external reference can be either a DC or an AC signal. If an AC reference is applied, the analog output channel acts as a signal attenuator, and the AC signal appears at the output attenuated by the digital code divided by 4,096 for unipolar output.

Bipolar output with an AC reference provides four-quadrant multiplication, which means that the signal is inverted for digital codes 0 to 2,047 and not inverted for digital codes 2,049 to 4,095. In straight binary mode, a digital code word of 2,048 attenuates the input signal to 0 V. This attenuation is equivalent to multiplying the signal by (digital code word - 2,048)/+2,048. In two's complement mode, a digital code word of zero attenuates the input signal to 0 V.

The internal voltage reference is a buffered version of the 10 V reference supplied by the ADC. Using the internal reference supplies an output voltage range of 0 to 9.9976 V in steps of 2.44 mV for unipolar output and an output voltage range of -10 V to +9.9951 V in steps of 4.88 mV for bipolar output.

MIO-16 Digital I/O Circuitry

The MIO-16 circuitry of the AT-MIO-16D provides eight digital I/O lines, while the DIO-24 circuitry provides 24 lines of digital I/O (discussed later in this chapter). The eight lines of digital I/O from the MIO-16 circuitry are divided into two ports of four lines each and are located at pins ADIO<3..0> and BDIO<3..0> on the I/O connector. Figure 3-5 shows a block diagram of the digital I/O circuitry.

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Theory of Operation Chapter 3

DATA <3..0

DOUT0 ENABLE

DO REG WR

DATA <7..4

DOUT1 ENABLE

ADIO <3..0

BDIO <3..0>

DOUT0

Digital Output

DOUT1

Digital Output

I/O Connector

EXT STROBE WR*EXTSTROBE*

Digital

Input

DATA <7..0

DIREG RD

PC AT I/O Channel

Figure 3-5. Digital I/O Circuitry Block Diagram

The digital I/O lines are controlled by the Digital Output Register and monitored by the Digital Input Register. The Digital Output Register is an 8-bit register that contains the digital output values for both ports 0 and 1. When port 0 is enabled, bits <3..0> in the Digital Output Register are driven onto digital output lines ADIO<3..0>. When port 1 is enabled, bits <7..4> in the Digital Output Register are driven onto digital output lines BDIO<3..0>.

Reading the Digital Input Register returns the state of the digital I/O lines. Digital I/O lines ADIO<3..0> are connected to bits <3..0> of the Digital Input Register. Digital I/O lines BDIO<3..0> are connected to bits <7..4> of the Digital Input Register. When a port is enabled, the Digital Input Register serves as a read-back register, returning the digital output value of the port. When a port is not enabled, reading the Digital Input Register returns the state of the digital I/O lines as driven by an external device.

Both the digital input and output registers are TTL-compatible. The digital output ports, when enabled, are capable of sinking 24 mA of current and sourcing 2.6 mA of current on each digital I/O line. When the ports are not enabled, the digital I/O lines act as high-impedance inputs.

The external strobe signal EXTSTROBE*, shown in Figure 3-5, is a general-purpose strobe signal. Writing to an address location on the AT-MIO-16D board generates an active-low 200-nsec

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Chapter 3 Theory of Operation

pulse on this output pin. EXTSTROBE* is not necessarily part of the digital I/O circuitry but is shown here because it can be used to latch digital output from the AT-MIO-16D into an external device.

Timing I/O Circuitry

The AT-MIO-16D uses an Am9513A Counter/Timer for data acquisition timing and for generalpurpose timing I/O functions. An onboard oscillator is used to generate the 10-MHz clock. FigureÊ3-6 shows a block diagram of the timing I/O circuitry.

FOUT

GATE2

SOURCE

OUT2

GATE1

SOURCE1

OUT1

GATE5

SOURCE5

OUT5

STOP TRI

I/O Connector

Flip

Flop

Figure 3-6. Timing I/O Circuitry Block Diagram

Am9513

Channel

Counter/

Timer

GATE4

SOURCE SOURCE3

OUT1 OUT3 OUT4 OUT5

GATE3

1-MHz CLK

Data

Acquisition

Timing

/ 16

/ 2

MYCLK

(10 MHz)

DATA<15..0>

Am9513 RD/WR

RTSI Bus

PC AT I/O Channel

CONVERT

SCANCLK

MUX CTR CLK

The Am9513A contains five independent 16-bit counter/timers, a 4-bit frequency output channel, and five internally generated timebases. The five counter/timers can be programmed to operate in several useful timing modes. The programming and operation of the Am9513A is presented in detail in Appendix E, Am9513A Data Sheet.

The Am9513A clock input is one-tenth the MYCLK frequency selected by the W5 jumpers. The factory default for MYCLK is 10 MHz, which generates a 1-MHz clock input to the Am9513A. The Am9513A uses this clock input to generate five internal timebases. These timebases can be used as clocks by the counter/timers and by the frequency output channel. When MYCLK is 10 MHz, the five internal timebases normally used for AT-MIO-16D timing functions are 1 MHz, 100ÊkHz, 10 kHz, 1 kHz, and 100 Hz.

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The 16-bit counters in the Am9513A can be diagrammed as shown in Figure 3-7.

SOURCE

COUNTER

OUT

GATE

Figure 3-7. Counter Block Diagram

Each counter has a SOURCE input pin, a GATE input pin, and an output pin labeled OUT. The Am9513A counters are numbered 1 through 5, and their GATE, SOURCE, and OUT pins are labeled GATE N, SOURCE N, and OUT N, where N is the counter number.

For counting operations, the counters can be programmed to use any of the five internal timebases, any of the five GATE and five SOURCE inputs to the Am9513A, and the output of the previous counter (Counter 4 uses Counter 3 output, and so on). A counter can be configured to count either falling or rising edges of the selected input.

The counter GATE input allows counter operation to be gated. Once a counter is configured for an operation through software, a signal at the GATE input can be used to start and stop counter operation. There are five gating modes supported by the Am9513A: no gating, level gating active high, level gating active low, low-to-high edge gating, and high-to-low edge gating. A counter can also be active high level gated by a signal at GATE N+1 and GATE N-1, where N is the counter number.

The counter generates timing signals at its OUT output pin. The OUT output pin can also be set to a high-impedance state or a grounded-output state. The counters generate two types of output signals during counter operation: terminal count pulse output and terminal count toggle output. Terminal count is often referred to as TC. A counter reaches TC when it counts up or down and rolls over. In many counter applications, the counter reloads from an internal register when it reaches TC. In TC pulse output mode, the counter generates a pulse during the cycle that it reaches TC and reloads. In TC toggle output mode, the counter output changes state after it reaches TC and reloads. In addition, the counters can be configured for positive logic output or negative (inverted) logic output for a total of four possible output signals generated for one timing mode.

The SOURCE, GATE, and OUT pins for Counters 1, 2, and 5 of the onboard Am9513A are located on the AT-MIO-16D I/O connector. A rising edge signal on the STOP TRIG pin of the I/O connector sets the flip-flop output signal connected to the GATE4 input of the Am9513A and can be used as an additional gate input. The flip-flop output connected to GATE4 is cleared when the sample counter reaches TC, when an overflow or overrun occurs, or when the A/D Clear Register is written to.

The Am9513A SOURCE5 pin is connected to the AT-MIO-16D RTSI switch, which means that a signal from the RTSI trigger bus can be used as a counting source for the Am9513A counters.

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The Am9513A OUT2 pin can be used in several different ways. If the LDAC bit is set in Command Register 2, an active low pulse on OUT2 updates the analog output on the two DACs. OUT2 can also be used to trigger interrupt requests. If INT2EN bit is set, an interrupt occurs when a rising edge signal is detected on OUT2. This interrupt can be used to update the DACs or to interrupt on an external signal connected to OUT2 through the I/O connector.

Counters 3 and 4 of the Am9513A are dedicated to data acquisition timing and therefore are not made available for general-purpose timing applications. Signals generated at OUT3 and OUT4 are provided to the data acquisition timing circuitry. GATE3 is controlled by the data acquisition timing circuitry.

Counter 5 is sometimes used by the data acquisition timing circuitry and concatenated with Counter 4 to form a 32-bit sample counter. The SCAN CLK signal is connected to the SOURCE3 input of the Am9513A, and OUT1 is provided to the data acquisition timing circuitry. This allows Counter 1 to be used to divide the SCAN CLK signal for generating the MUX CTR CLK signal (see the Data Acquisition Timing Circuitry section earlier in this chapter).

Counter 2 is sometimes used by the data acquisition timing circuitry to assign a time interval to each cycle through the scan sequence programmed in the mux-gain memory. This mode is called interval channel scanning. See the Multiple-Channel (Scanned) Data Acquisition section earlier in this chapter.

The Am9513A 3-bit programmable frequency output channel is provided at the I/O connector FOUT pin. Any of the five internal timebases and any of the counter SOURCE or GATE inputs can be selected as the frequency output source. The frequency output channel divides the selected source by its 4-bit programmed value and provides the divided down signal at the FOUT pin.

RTSI Bus Interface Circuitry

The AT-MIO-16D is interfaced to the National Instrument RTSI bus. The RTSI bus has seven trigger lines and a system clock line. All National Instruments AT Series boards with RTSI bus connectors can be wired together inside the PC AT and share these signals. A block diagram of the RTSI bus interface circuitry is shown in Figure 3-8.

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Theory of Operation Chapter 3

DRVA2RCV

MYCLK

10-MHz Oscillator

RTSICLK

OUT2

GATE1

OUT5

STOP TRIG

Drivers

DRVA4RCV

EXTCONV

FOUT

SOURCE5

OUT1

START TRIG

RTSI SEL

Internal

Data Bus

A0 A1 A2 A3 A4 A5 A6

/SEL DATA

RTSI

Switch

B0 B1 B2 B3 B4 B5 B6

Figure 3-8. RTSI Bus Interface Circuitry Block Diagram

Trigger

RTSI Bus Connector

The RTSI CLK line can be used to source a 10-MHz signal across the RTSI bus or to receive another clock signal from another AT board connected to the RTSI bus. MYCLK is the system clock used by the AT-MIO-16D. The W5 jumpers select how these clock signals are routed.

The RTSI switch is a National Instruments custom integrated circuit that acts as a 7x7 crossbar switch. Pins B<6..0> are connected to the seven RTSI bus trigger lines. Pins A<6..0> are connected to seven signals on the board. The RTSI switch can drive any of the signals at pins A<6..0> onto any one or more of the seven RTSI bus trigger lines and can drive any of the seven trigger line signals onto any one or more of the pins A<6..0>. This capability provides a completely flexible signal interconnection scheme for any AT Series board sharing the RTSI bus. The RTSI switch is programmed via its select and data inputs.

On the AT-MIO-16D board, nine signals are connected to pins A<6..0> of the RTSI switch with the aid of additional drivers. The signals GATE1, OUT1, OUT2, OUT5, FOUT, and STOP TRIG are shared with the AT-MIO-16D I/O connector and Am9513A Counter/Timer. The signal SOURCE5 is connected to the Am9513A SOURCE5 pin. The EXTCONV* and START TRIG* signals are shared with the I/O connector and the data acquisition timing circuitry. These onboard interconnections allow AT-MIO-16D general-purpose and data acquisition timing to be controlled over the RTSI bus as well as externally and allow the AT-MIO-16D and the I/O connector to provide timing signals to other AT boards connected to the RTSI bus.

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Chapter 3 Theory of Operation

DIO-24 Functional Overview

The block diagram in Figure 3-9 illustrates the key functional components of the AT-MIO-16D DIO-24 circuitry.

Address Decoder

Bus

Transceivers

82C55A

PPI

I/O Connector

PC3

PC0

PC AT I/O Channel

+5 V

PC AT I/O

Channel

Control

Circuitry

Interrupt

Control

Circuitry

1A Fuse

Figure 3-9. AT-MIO-16D DIO-24 Block Diagram

DIO-24 Interrupt Control Circuitry

The interrupt level used by the DIO-24 circuitry of the AT-MIO-16D is selected by the onboard jumper W13. Another onboard jumper, W14, is used to enable interrupts from the DIO-24 circuitry. The setting for W14 selects PC2, PC4, or PC6 as the active low interrupt enable signal. Selecting N/C for W14 disables interrupts from the DIO-24 circuitry. When the onboard jumpers are set to enable interrupts, the 82C55A can be programmed to generate an interrupt request by setting INTRA for Group A or INTRB for Group B. When interrupts are enabled for Group A, an active high signal on the PC3 line generates an interrupt request. When interrupts are enabled for Group B, an active high signal on the PC0 line generates an interrupt request.

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DIO-24 Circuitry I/O Connector

All digital I/O is transmitted through a 100-pin male connector. This 100-pin connector is physically divided into two standard 50-pin female connectors using a cable assembly. The pin assignments for the 50-pin DIO-24 I/O connector are compatible with standard 24-channel digital I/O applications. All even pins on the 50-pin DIO-24 connector are attached to logic ground, and pin 49 is connected to +5 V through a protection fuse (F4), which is often required to operate I/O module mounting racks. See Chapter 2, Configuration and Installation, for additional information.

82C55A Programmable Peripheral Interface

The 82C55A PPI is the heart of the AT-MIO-16D DIO-24 circuitry. This chip has 24 programmable I/O pins that represent three 8-bit ports: PA, PB, and PC. Each port can be programmed as an input or an output port. The 82C55A has three modes of operation: simple I/O (Mode 0), strobed I/O (Mode 1), and bidirectional I/O (Mode 2). In Modes 1 and 2, the three 8-bit ports are divided into two groups: Group A and Group B (two groups of twelve signals). One 8-bit configuration (or control) word determines the mode of operation for each group. The Group A control bits configure Port A (A0 through A7) and the upper 4 bits (nibble) of Port C (C4 through C7). The Group B control bits configure Port B (B0 through B7) and the lower nibble of Port C (C0 through C3). Modes 1 and 2 use handshaking signals from Port C to synchronize data transfers. Refer to Chapter 4, Programming, or to Appendix F, Oki MSM82C55A Data Sheet, for more detailed information.

82C55A Modes of Operation

The three basic modes of operation for the 82C55A are as follows:

¥ Mode 0 Ð Basic I/O

¥ Mode 1 Ð Strobed I/O

¥ Mode 2 Ð Bidirectional bus

The 82C55A also has a single bit set/reset feature for Port C. The 8-bit control word also programs this function. For additional information, refer to Appendix F, Oki MSM82C55A Data Sheet.

Mode 0

This mode can be used for simple input and output operations for each of the ports. No handshaking is required; data is simply written to or read from a selected port.

Mode 0 has the following features:

¥ Two 8-bit ports (A and B) and two 4-bit ports (upper and lower nibble of Port C)

¥ Any port can be input or output

¥ Outputs are latched, but inputs are not latched

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Mode 1

This mode transfers data that is synchronized by handshaking signals. Ports A and B use the eight lines of Port C to generate or receive the handshake signals. This mode divides the ports into two groups (Group A and Group B) and has the following features:

¥ Each group contains one 8-bit data port (Port A or Port B) and one 4-bit control/data port

(upper or lower nibble of Port C).

¥ The 8-bit data ports can be either input or output, both of which are latched.

¥ The 4-bit ports are used for control and status of the 8-bit data ports.

¥ Interrupt generation and enable and/or disable functions are available.

Mode 2

This mode can be used for communication over a bidirectional 8-bit bus. Handshaking signals are used in a manner similar to Mode 1. Interrupt generation and enable and/or disable functions are also available. Other features of this mode include the following:

¥ Used in Group A only (Port A and upper nibble of Port C)

¥ One 8-bit bidirectional port (Port A) and a 5-bit control status port (Port C)

¥ Latched inputs and outputs

Single Bit Set/Reset Feature

Any of the eight bits of Port C can be set or reset with one control word. This feature generates status and control for Port A and Port B when operating in Mode 1 or Mode 2.

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Chapter 4 Programming

This chapter discusses the programming of the AT-MIO-16D. Included in this chapter are the AT-MIO-16D register address map, a detailed register description, and a functional programming description.

Note: If you plan to use a programming software package such as NI-DAQ for DOS/Windows

or LabWindows with your AT-MIO-16D board, you need not read this chapter. However, you will gain added insight into your AT-MIO-16D board by reading this chapter.

Register Map

The register map for the AT-MIO-16D is shown in Table 4-1. This table gives the register name, the register offset address, the size of the register in bits, and the type of the register (read-only, write-only, or read-and-write). The actual register address is computed by adding the individual offset address to the board base address.

Table 4-1. AT-MIO-16D Register Map

(Hex) Type Size

Configuration and Status Register Group:

Command Register 1 0 Write-only 16-bit Status Register 0 Read-only 16-bit Command Register 2 2 Write-only 16-bit

Event Strobe Register Group:

Start Convert Register 8 Write-only 16-bit Start DAQ Register A Write-only 16-bit A/D Clear Register C Write-only 16-bit External Strobe Register E Write-only 16-bit

Analog Output Register Group:

DAC0 Register 10 Write-only 16-bit DAC1 Register 12 Write-only 16-bit INT2CLR Register 14 Write-only 16-bit

(continues)

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Programming Chapter 4

Table 4-1. AT-MIO-16D Register Map (continued)

(Hex) Type Size

Analog Input Register Group:

Mux-Counter Register 4 Write-only 16-bit Mux-Gain Register 6 Write-only 16-bit A/D FIFO Register 16 Read-only 16-bit DMA TC INT Clear Register 16 Write-only 16-bit

Am9513A Counter/Timer Register Group:

Am9513A Data Register 18 Read-and-write 16-bit Am9513A Command Register 1A Write-only 16-bit Am9513A Status Register 1A Read-only 16-bit

MIO-16 Digital I/O Register Group:

MIO-16 Digital Input Register 1C Read-only 16-bit MIO-16 Digital Output Register 1C Write-only 16-bit

RTSI Switch Register Group:

RTSI Switch Shift Register 1E Write-only 8-bit RTSI Switch Strobe Register 1F Write-only 8-bit

DIO-24 Register Group:

DIO-24 PORTA Register 0x00 Read-and-write 8-bit DIO-24 PORTB Register 0x01 Read-and-write 8-bit DIO-24 PORTC Register 0x02 Read-and-write 8-bit DIO-24 CNFG Register 0x03 Write-only 8-bit

Register Sizes

The IBM PC AT and compatibles support two different transfer sizes for read-and-write operations: byte (8-bit) and word (16-bit). Table 4-1 shows the size of each AT-MIO-16D register. For example, reading the A/D FIFO Register requires a 16-bit (word) read operation at the specified address, whereas writing to the RTSI Strobe Register requires an 8-bit (byte) write operation at the specified address.

Register Description

Table 4-1 divides the AT-MIO-16D registers into eight different register groups. A bit description of each of the registers making up these groups is included later in this chapter.

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Chapter 4 Programming

The Configuration and Status Register Group controls the overall operation of the AT-MIO-16D hardware. The Event Strobe Group is a group of registers that, when written to, generate some event on the AT-MIO-16D board. The registers in the Analog Output Group access the AT-MIO-16D DACs. The Analog Input Group allows ADC output to be read. The Counter/Timer Group consists of the three registers of the onboard Am9513A Counter/Timer chip. The registers in the Digital I/O Group access the onboard digital input and output lines. The registers in the RTSI Switch Group control the onboard RTSI switch. The DIO-24 Register Group controls all operations and modes of the DIO-24 circuitry on the AT-MIO-16D board.

You may notice that the DIO-24 registers have the same offset as Command Register 1 and Command Register 2. Access to the DIO-24 registers are distinguished by means of performing an 8-bit bus transfer versus a 16-bit bus transfer.

The remainder of this register description chapter discusses each of the AT-MIO-16D registers in the order shown in Table 4-1. Each register group is introduced, followed by a detailed bit description of each register. The individual register description gives the address, type, word size, and bit map of the register, followed by a description of each bit.

The register bit map shows a diagram of the register with the MSB (bit 15 for a 16-bit register, bit 7 for an 8-bit register) shown on the left, and the LSB (bit 0) shown on the right. A square is used to represent each bit. Each bit is labeled with a name inside its square. An asterisk (*) after the bit name indicates that the bit is inverted (negative logic).

In many of the registers, several bits are labeled with an X, indicating don't care bits. When a register is read, these bits may appear set or cleared but should be ignored because they have no significance. When a register is written to, setting or clearing these bit locations has no effect on the AT-MIO-16D hardware.

The bit map field for some write-only registers states not applicable, no bits used. Writing to these registers generates a strobe in the AT-MIO-16D. These strobes are used to cause some onboard event to occur. For example, they can be used to clear the analog input circuitry or to start a data acquisition operation. The data is ignored when writing to these registers; therefore, any bit pattern will suffice.

Configuration and Status Register Group

The three registers making up the Configuration and Status Register Group allow general control and monitoring of the AT-MIO-16D hardware. Command Registers 1 and 2 contain bits that control operation of several different pieces of the AT-MIO-16D hardware. The Status Register can be used to read the state of different pieces of the AT-MIO-16D hardware.

Bit descriptions of the three registers making up the Configuration and Status Group are given on the following pages.

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Programming Chapter 4

Command Register 1

Command Register 1 contains ten bits that control AT-MIO-16D interrupts, direct memory access (DMA), and some analog input and output modes.

Address: Base address + 0 (hex)

Type: Write-only

Word Size: 16-bit

Bit Map:

15 14 13 12 11 10 9 8

XXXXXXDAQSTOPINTEN TCINTEN

7 6543 2 1 0

CONVINTEN DBDMA DMAEN DAQEN SCANEN SCANDIV 16*/32CNT 2SCADC*

Bit Name Description

15-10 X Don't care bits.

9 DAQSTOPINTEN This bit enables and disables the generation of an interrupt when a

data acquisition operation is terminated. This termination can be caused by either the normal completion of a data acquisition operation or by an error condition. If an error condition occurs, either OVERFLOW or OVERRUN is set in the Status Register. The interrupt is serviced by writing to the A/D Clear Register. If DAQSTOPINTEN is cleared, no data acquisition termination interrupts are generated.

8 TCINTEN This bit enables and disables generation of an interrupt when a

DMA terminal count pulse is received from the DMA controller in the PC AT. If TCINTEN is set, an interrupt request is generated when the DMA controller transfer count register decrements from 0 to FFFF (hex). The interrupt request is serviced by writing to the DMA TC INT Clear Register. When TCINTEN is cleared, no DMA terminal count interrupts are generated.

7 CONVINTEN This bit enables and disables the generation of an interrupt when

A/D conversion results are available. If CONVINTEN is set, an interrupt is generated whenever an A/D conversion is available to be read from the A/D FIFO. If CONVINTEN is cleared, no interrupt is generated.

6 DBDMA This bit selects the DMA mode. If DBDMA is cleared and

DMAEN is set, a single-channel, single-buffered DMA mode is selected. If DBDMA is set and DMAEN is set, a double-channel, double-buffered DMA mode is selected.

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Bit Name Description (continued)

5 DMAEN This bit enables and disables the generation of DMA requests. If

DMAEN is set, a DMA request is generated whenever an A/D conversion result is available to be read from the A/D FIFO. If DMAEN is cleared, no DMA request is generated.

4 DAQEN This bit enables and disables a data acquisition operation that is

controlled by the onboard sample-interval and sample counters. If DAQEN is set, a software or start trigger starts the counters (assuming that the counters are programmed and enabled), thereby initiating a data acquisition operation. If DAQEN is cleared, software and start triggers are ignored.

3 SCANEN This bit enables and disables multiple-channel scanning during

data acquisition. If SCANEN is set, alternate analog input channels are sampled during data acquisition under control of the mux-gain memory. If SCANEN is cleared, a single analog input channel is sampled during the entire data acquisition operation.

2 SCANDIV This bit enables and disables division of the mux-counter clock

during data acquisition. The mux-counter clock controls sequencing of the mux-gain memory. If SCANDIV is set, the mux-counter clock is controlled by Counter 1 of the Am9513A Counter/Timer. If SCANDIV is cleared, the mux-counter clock generates one pulse per conversion.

1 16*/32CNT This bit selects the count resolution for the number of A/D

conversions to be performed in a data acquisition operation. If 16*/32CNT is cleared, a 16-bit count mode is selected and Counter 4 of the Am9513A Counter/Timer controls conversion counting. If 16*/32CNT is set, a 32-bit count mode is selected and Counter 4 is concatenated with Counter 5 to control conversion counting. A 16-bit count mode can be used if the number of A/D sample conversions to be performed is less than 65,537. A 32-bit count mode should be used if the number of A/D sample conversions to be performed is greater than or equal to 65,537.

0 2SCADC* This bit selects the binary format for the 16-bit data word read

from the A/D FIFO. If 2SCADC* is set, a straight binary format is used and the data read from the A/D FIFO ranges from 0 to +4,095 decimal (0 to 0FFF hex). This mode is useful if a unipolar input range is used. If 2SCADC* is cleared, a 16-bit two's complement mode is used and the data read from the ADC ranges from -2,048 to +2,047 decimal (F800 to 07FF hex). This mode is useful if a bipolar input range is used.

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Programming Chapter 4

Status Register

The Status Register contains 16 bits of AT-MIO-16D hardware status information, including interrupt and analog input status.

Address: Base address + 0 (hex)

Type: Read-only

Word Size: 16-bit

Bit Map:

15 14 13 12 11 10 9 8

GINT DAQSTOPINT CONVAVAIL OUT2INT DAQPROG DMATCINT OVERFLOW OVERRUN

7654321 0

GAIN1 GAIN0 DMACH MUX1EN MUX0EN MA2 MA1 MA0

Bit Name Description

15 GINT This bit reflects the overall state of interrupts generated by the

MIO-16 circuitry on the AT-MIO-16D board. If GINT is set, the AT-MIO-16D is asserting an interrupt request on the MIO-16 interrupt that has not yet been serviced. If GINT is cleared, no MIO-16 interrupt is pending. This bit is normally cleared.

14 DAQSTOPINT This bit reflects the status of the data acquisition termination

interrupt. If DAQSTOPINT is set and either OVERFLOW or OVERRUN is set, the current interrupt is due to an error condition. If DAQSTOPINT is set and neither OVERFLOW nor OVERRUN is set, the current interrupt is due to the completion of the data acquisition operation. DAQSTOPINT is cleared by writing to the A/D Clear Register.

13 CONVAVAIL This bit reflects the state of the A/D FIFO. If CONVAVAIL is set,

one or more A/D conversion results are available to be read from the A/D FIFO. If conversion interrupts are enabled (CONVINTEN is set) and CONVAVAIL is set, the current interrupt indicates that A/D conversion data is available in the A/D FIFO. If CONVAVAIL is cleared, the A/D FIFO is empty and no conversion interrupt request is asserted.

12 OUT2INT This bit reflects the status of the OUT2INT interrupt. OUT2INT is

cleared by writing to the INT2CLR Register. OUT2INT is set whenever a rising edge on OUT2 is detected; this condition generates an interrupt request only if the INT2EN bit in Command Register 2 is set.

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Bit Name Description (continued)

11 DAQPROG This bit indicates whether a data acquisition operation is in

progress. If DAQPROG is set, a data acquisition operation is in progress. If DAQPROG is cleared, a data acquisition operation is not in progress.

10 DMATCINT This bit reflects the status of the DMA terminal count interrupt. If

DMATCINT is set, and if TCINTEN is set in Command Register 1, then the current interrupt is due to the detection of a DMA terminal count pulse. DMATCINT is cleared by writing to the DMA TC Clear Register.

9 OVERFLOW This bit indicates whether the A/D FIFO has overflowed during a

sample run. OVERFLOW is an error condition that occurs if the FIFO fills up with A/D conversion data and A/D conversions continue. If OVERFLOW is set, A/D conversion data has been lost because of FIFO overflow. If OVERFLOW is cleared, no overflow has occurred. If OVERFLOW occurs during a data acquisition operation, the data acquisition is terminated immediately. This bit can be reset by writing to the A/D Clear Register.

8 OVERRUN This bit indicates whether an A/D conversion was initiated before

the previous A/D conversion was complete. OVERRUN is an error condition that may occur if the data acquisition sample interval is too small (sample rate is too high). If OVERRUN is set, one or more conversions were skipped. If OVERRUN is cleared, no overrun condition has occurred. If OVERRUN occurs during a data acquisition operation, the data acquisition is terminated immediately. This bit can be reset by writing to the A/D Clear Register.

7-6 GAIN<1..0> These two bits show the current gain setting for the programmable

gain amplifier (see Mux-Gain Register later in this chapter).

5 DMACH This bit indicates the current DMA channel. If DBDMA in

Command Register 1 is set, dual DMA mode is selected. In this mode, DMA transfers switch between two DMA channels. DMACH indicates which DMA channel is currently in use for DMA operation. If DMACH is cleared, then DMA 1 is in use. If DMACH is set, then DMA 2 is in use. In single DMA mode, only DMA 1 is used.

4 MUX1EN This bit indicates the state of multiplexer 1. Multiplexer 1 controls

analog input channels 8 through 15. If this bit is set, multiplexer 1 is currently enabled. If this bit is cleared, multiplexer 1 is currently disabled. In single-ended mode, multiplexer 1 is enabled only when one of the input channels 8 through 15 is selected. In this mode, the output of multiplexer 1 is connected to the positive (+) input of the instrumentation amplifier. In DIFF mode, multiplexer 1 is always enabled. In this mode, the output of multiplexer 1 is connected to the negative (-) input of the instrumentation amplifier.

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Bit Name Description (continued)

3 MUX0EN This bit indicates the state of multiplexer 0. Multiplexer 0 controls

analog input channels 0 through 7. If this bit is set, multiplexer 0 is currently enabled. If this bit is cleared, multiplexer 0 is currently disabled. In single-ended mode, multiplexer 0 is enabled only when one of the input channels 0 through 7 is selected. In DIFF mode, multiplexer 0 is always enabled. The output of multiplexer 0 is always connected to the positive (+) input of the instrumentation amplifier.

2-0 MA<2..0> MA<2..0> give the low-order three bits of the analog input channel

address. MA stands for multiplexer address. These three bits, in conjunction with the MUX1EN and MUX0EN bits, indicate which analog input channel is currently selected. In single-ended mode, the analog input channel selected is determined by the value of MA<2..0> if MUX0EN is set and by the value of MA<2..0> + 8 if MUX1EN is set. In DIFF mode, two analog input channels are selected simultaneously. The two channels are MA<2..0> and MA<2..0> + 8.

National Instruments AT-MIO-16D Owners Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Limited Warranty

Copyright

Trademarks

WARNING REGARDING MEDICAL AND CLINICAL USE

Preface

Organization of This Manual

Conventions Used in This Manual

Abbreviations

Acronyms

Related Documentation

Customer Communication

Contents

Figures

Tables

Chapter 1 Introduction

What Your Kit Should Contain

Optional Software

Optional Equipment

Custom Cables

Figure 1-2. AT-MIO-16D Cable Assembly

Unpacking

Chapter 2 Configuration and Installation

Board Configuration

AT Bus Interface

Table 2-1. AT Bus Interface Factory Settings

Base I/O Address Selection

Table 2-2. Default Settings of Other National Instruments Products for the PC

Figure 2-2. Example Base I/O Address Switch Settings

Table 2-3. Switch Settings with Corresponding Base I/O Address and Base I/O Address Space

DMA Channel Selection

Table 2-4. DMA Channels for the AT-MIO-16D

Figure 2-3. DMA Jumper Settings for DMA Channels 6 and 7 (Factory Setting)

Figure 2-4. DMA Jumper Settings for DMA Channel 6 Only

Figure 2-5. DMA Jumper Settings for Disabling DMA Transfers

Interrupt Selection

Figure 2-6. Factory Interrupt Jumper Settings IRQ5 (DIO-24) and IRQ10 (MIO-16)

Figure 2-7. Interrupt Jumper Setting for Disabling Interrupts

DIO-24 Circuitry Interrupt Enable Settings

Figure 2-8. Jumper Settings–PC6, PC4, PC2, and N/C

Analog I/O Jumper Settings

Table 2-5. Analog I/O Jumper Settings

Analog Input Configuration

Input Mode

Table 2-6. Input Configurations Available for the AT-MIO-16D

Figure 2-9. DIFF Analog Input Configuration (Factory Setting)

Figure 2-10. RSE Analog Input Configuration

Figure 2-11. NRSE Analog Input Configuration

Analog Input Polarity and Range

Table 2-7. Configurations for Input Range and Input Polarity

Figure 2-12. 0 to +10 V Input Configuration

Figure 2-13. -5 to +5 V Input Configuration

Figure 2-14. Factory -10 to +10 V Analog Input Configuration

Table 2-8. Actual Range and Measurement Precision Versus Input Range Selection and Gain

Analog Output Configuration

Analog Output Reference Selection

Figure 2-15. External Reference Configuration

Figure 2-16. Factory Internal Reference Configuration

Analog Output Polarity Selection

Figure 2-17. Factory Bipolar Output Configuration

Figure 2-18. Straight Binary Mode

Figure 2-19. Two's Complement Mode (Factory Setting)

Figure 2-20. Unipolar Output Configuration

RTSI Bus Clock Selection

Table 2-9. Configurations for RTSI Bus Clock Selection

Figure 2-21. Disconnect from RTSI Bus Clock; Use Onboard Oscillator (Factory Setting)

Figure 2-22. Receive RTSI Bus Clock Signal

Figure 2-23. Drive RTSI Bus Clock Signal with Onboard Oscillator

Hardware Installation

Signal Connections

AT-MIO-16D I/O Connector Pin Description

Figure 2-24. AT-MIO-16D I/O Connector Pin Assignments

MIO-16 I/O Connector Pin Description

Figure 2-25. MIO-16 I/O Connector Pin Assignments

MIO-16 Signal Connection Descriptions

Analog Input Signal Connections

Figure 2-26. AT-MIO-16D Instrumentation Amplifier