Datasheet NT5DS32M8AT-6, NT5DS32M8AT-66, NT5DS64M4AT-66, NT5DS64M4AW-6, NT5DS64M4AW-66 Datasheet (NANYA)

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb DDR333/300 SDRAM

Features

CAS Latency and Frequency

CAS Latency

2 133 133

2.5 166 150

• Double data rate architecture: two data transfers per
clock cycle

• Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver

• DQS is edge-aligned with data for reads and is center­aligned with data for writes

• Differential clock inputs (CK and CK)

• Four internal banks for concurrent operation

Maximum Operating Frequency (MHz)*

DDR333 (-6) DDR300 (-66)

Description

• Data mask (DM) for write data

• DLL aligns DQ and DQS transitions with CK transitions.

• Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS

• Burst lengths: 2, 4, or 8

• CAS Latency: 2, 2.5

• Auto Precharge option for each burst access

• Auto Refresh and Self Refresh Modes

• 7.8µs Maximum Average Periodic Refresh Interval

• 2.5V (SSTL_2 compatible) I/O

• V

• VDD = 2.5V ± 0.2V

• Package : 66pin TSOP-II / 60 balls 0.8mmx1.0mm pitch

= 2.5V ± 0.2V

DDQ

CSP.

The 256Mb DDR SDRAM is a high-speed CMOS, dynamic
random-access memory containing 268,435,456 bits. It is
internally configured as a quad-bank DRAM.

The 256Mb DDR SDRAM uses a double-data-rate architec­ture to achieve high-speed operation. The double data rate
architecture is essentially a 2n prefetch architecture with an
interface designed to transfer two data words per clock cycle
at the I/O pins. A single read or write access for the 256Mb
DDR SDRAM effectively consists of a single 2n-bit wide, one
clock cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.

A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads
and by the memory controller during Writes. DQS is edge­aligned with data for Reads and center-aligned with data for
Writes.

The 256Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well
as to both edges of CK.

Read and write accesses to the DDR SDRAM are burst ori­ented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write com­mand. The address bits registered coincident with the Active
command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.

The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4 or 8 locations. An Auto Precharge func­tion may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst access.

As with standard SDRAMs, the pipelined, multibank architec­ture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row pre­charge and activation time.

An auto refresh mode is provided along with a power-saving
power-down mode. All inputs are compatible with the JEDEC
Standard for SSTL_2. All outputs are SSTL_2, Class II com­patible.

Preliminary

10/01

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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb DDR333/300 SDRAM

Pin Configuration - 400mil TSOP II

V

NC

V

DDQ

NC

DQ0

V

SSQ

NC
NC

V

DDQ

NC

DQ1

V

SSQ

NC
NC

V

DDQ

NC
NC

V

NU
NC

WE

CAS
RAS

CS
NC

BA0
BA1

A10/AP

A0
A1
A2
A3

V

DD

DD

DD

V

DD

DQ0

V

DDQ

NC

DQ1

V

SSQ

NC

DQ2

V

DDQ

NC

DQ3

V

SSQ

NC
NC

V

DDQ

NC
NC

V

NU
NC

WE

CAS
RAS

CS

NC

BA0

BA1

A10/AP

A0
A1
A2
A3

V

DD

DD

1
2

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

33

39
38

37
36

35
34

66-pin Plastic TSOP-II 400mil

66
65

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

40

V

SS

DQ7
V

SSQ

NC
DQ6
V

DDQ

NC
DQ5
V

SSQ

NC
DQ4
V

DDQ

NC
NC
V

SSQ

DQS
NC
V

REF

V

SS

DM*
CK

CK
CKE
NC

A12
A11

A9
A8

A7
A6

A5
A4

V

SS

V

SS

NC
V

SSQ

NC
DQ3
V

DDQ

NC
NC
V

SSQ

NC
DQ2
V

DDQ

NC
NC
V

SSQ

DQS
NC
V

REF

V

SS

DM*
CK

CK
CKE
NC

A12
A11

A9
A8

A7
A6

A5
A4

V

SS

Preliminary

10/01

32Mb x 8

NT5DS32M8AT

64Mb x 4

NT5DS64M4AT

Column Address Table

Organization Column Address

64Mb x 4 A0-A9, A11
32Mb x 8 A0-A9

*DM is internally loaded to match DQ and DQS identically.

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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb DDR333/300 SDRAM

Pin Configuration - 60 balls 0.8mmx1.0mm Pitch CSP Package

<Top View >

See the balls through the package.

64 X 4

1

VSSQ

NC

2

VSS

3

A

7

VDD

8

NC

9

VDDQ

NC

NC

NC

NC

VREF

1

VSSQ

NC

VDDQ

VSSQ

VDDQ

VSSQ

VSS

CLK

A12

A11

A8

A6

A4

2

DQ7

VDDQ

DQ3

NC

DQ2

DQS

DQM

CLK

CKE

A9

A7

A5

VSS

3

VSS

DQ6

B

C

D

E

F

G

H

J

K

L

M

32 X 8

A

B

DQ0

NC

DQ1

QFC

NC

WE

RAS

BA1

A0

A2

VDD

7

VDD

DQ1

VSSQ

VDDQ

VSSQ

VDDQ

VDD

CAS

CS

BA0

A10/AP

A1

A3

8

DQ0

VSSQ

NC

NC

NC

NC

NC

9

VDDQ

NC

Preliminary

10/01

NC

NC

NC

VREF

VSSQ

VDDQ

VSSQ

VSS

CLK

A12

A11

A8

A6

A4

DQ5

DQ4

DQS

DQM

CLK

CKE

A9

A7

A5

VSS

C

D

E

F

G

H

J

K

L

M

DQ2

DQ3

QFC

NC

WE

RAS

BA1

A0

A2

VDD

VDDQ

VSSQ

VDDQ

VDD

CAS

CS

BA0

A10/AP

A1

A3

NC

NC

NC

NC

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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb DDR333/300 SDRAM

Input/Output Functional Description

Symbol Type Function

CK, CK Input

CKE, CKE0, CKE1 Input

CS, CS0, CS1 Input

RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.

DM Input

BA0, BA1 Input

A0 - A12 Input

DQ Input/Output Data Input/Output: Data bus.

DQS Input/Output

NC No Connect: No internal electrical connection is present.

NU Electrical connection is present. Should not be connected at second level of assembly.
V
V

V
V
V

DDQ
SSQ

DD

SS

REF

Supply DQ Power Supply: 2.5V ± 0.2V.
Supply DQ Ground
Supply Power Supply: 2.5V ± 0.2V.
Supply Ground
Supply SSTL_2 reference voltage: (V

Clock: CK and CK are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer­enced to the crossings of CK and CK (both directions of crossing).

Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self
Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is syn­chronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self
refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK, CK and CKE are disabled during power-down. Input buffers, excluding CKE, are
disabled during self refresh. The standard pinout includes one CKE pin. Optional pinouts might
include CKE1 on a different pin, in addition to CKE0, to facilitate independent power down control
of stacked devices.

Chip Select: All commands are masked when CS is registered high. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code. The
standard pinout includes one CS pin. Optional pinouts might include CS1 on a different pin, in
addition to CS0, to allow upper or lower deck selection on stacked devices.

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled high coincident with that input data during a Write access. DM is sampled on both edges
of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Dur­ing a Read, DM can be driven high, low, or floated.

Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge
command is being applied. BA0 and BA1 also determines if the mode register or extended mode
register is to be accessed during a MRS or EMRS cycle.

Address Inputs: Provide the row address for Active commands, and the column address and
Auto Precharge bit for Read/Write commands, to select one location out of the memory array in
the respective bank. A10 is sampled during a Precharge command to determine whether the Pre­charge applies to one bank (A10 low) or all banks (A10 high). If only one bank is to be precharged,
the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode
Register Set command.

Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered
in write data. Used to capture write data.

/ 2) ± 1%.

DDQ

Preliminary

10/01

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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb DDR333/300 SDRAM

Ordering Information

Part Number Org.

NT5DS64M4AT-6 x 4

NT5DS32M8AT-6 x 8
NT5DS64M4AT-66 x 4
NT5DS32M8AT-66 x 8
NT5DS64M4AW-6 x 4
NT5DS32M8AW-6 x 8

NT5DS64M4AW-66 x 4
NT5DS32M8AW-66 x 8

CAS

Latency

2.5 166 2 133 DDR333

2.5 150 2 133 DDR300

2.5 166 2 133 DDR333

2.5 150 2 133 DDR300

Clock

(MHz)

CAS

Latency

Clock

(MHz)

Speed Package

66 pin TSOP-II

60 balls CSP

Preliminary

10/01

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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb DDR333/300 SDRAM

Block Diagram (64Mb x 4)

CKE
CK
CK
CS
WE
CAS
RAS

A0-A12,

BA0, BA1

Command

Mode

Registers

15

15

Decode

Control Logic

13

13

Row-Address MUX
13

2

Refresh Counter

2

Address Register

Column-Address

11

Counter/Latch

Bank1

8192

Bank0

& Decoder

Row-Address Latch

Bank Control Logic

10

1

Bank0

Memory

Array

(8192 x 1024 x 8)
Sense Amplifiers

8192

I/O Gating

DM Mask Logic

1024

(x8)

Column

Decoder

COL0

8

8

4
4

Read Latch

COL0

Mask

Write

FIFO

&

8

Drivers

clk

clk

in

out

Data

CK,
CK

MUX

2

8

4

DQS

Generator

Input

Register

1
1

4
4

COL0

Data

1
1

4
4

CK, CK

DLL

Drivers

1

DQS

1

4

Receivers

1

DQ0-DQ3,
DM

DQS

Bank3

Bank2

Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.

Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi­rectional DQ and DQS signals.

Preliminary

10/01

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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb DDR333/300 SDRAM

Block Diagram (32Mb x 8)

CKE
CK
CK
CS
WE
CAS
RAS

A0-A12,
BA0, BA1

Command

Mode

Registers

15

15

Decode

Control Logic

13

13

Row-Address MUX
13

2

Refresh Counter

2

Address Register

Column-Address

10

Counter/Latch

Bank Control Logic

Bank1

8192

Bank0

& Decoder

Row-Address Latch

9

1

Bank0

Memory

Array

(8192 x 512 x 16)

Sense Amplifiers

8192

I/O Gating

DM Mask Logic

512

(x16)

Column

Decoder

COL0

16

16

8
8

Read Latch

COL0

Mask

Write

FIFO

&

16

Drivers

clk

clk

in

out

Data

CK,
CK

MUX

2

16

8

DQS

Generator

Input

Register

1
1
8

8

COL0

Data

1
1
8

8

CK, CK

DLL

Drivers

1

DQS

1

8

Receivers

1

DQ0-DQ7,
DM

DQS

Bank3

Bank2

Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.

Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi­rectional DQ and DQS signals.

Preliminary

10/01

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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb DDR333/300 SDRAM

Mode Register Operation

BA1 BA0 A11 A10 A9

0* 0*

A12 - A9

0 0 0 Valid

0 1 0 Valid

0 0 1 VS**

A12

Operating Mode

A8 A7 A6 - A0 Operating Mode

Normal operation
Do not reset DLL

Normal operation

in DLL Reset

Vendor-Specific

Test Mode

− − − Reserved

CAS Latency

A6 A5 A4 Latency

0 0 0 Reserved
0 0 1 Reserved
0 1 0 2
0 1 1 Reserved
1 0 0 Reserved
1 0 1 Reserved
1 1 0 2.5
1 1 1 Reserved

A8 A7 A6 A5 A4

CAS Latency

A3

0 Sequential
1 Interleave

A2 A1 A0 Burst Length

0 0 0 Reserved
0 0 1 2
0 1 0 4
0 1 1 8
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved

A3 A2 A1 A0

Burst LengthBT

Burst
Type

Burst Length

Address Bus

Mode Register

VS** Vendor Specific

* BA0 and BA1 must be 0, 0 to select the Mode Register

(vs. the Extended Mode Register).

Preliminary

10/01

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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb DDR333/300 SDRAM

Burst Definition

Burst Length

2

4

8

Starting Column Address Order of Accesses Within a Burst

A2 A1 A0 Type = Sequential Type = Interleaved

0 0-1 0-1

1 1-0 1-0
0 0 0-1-2-3 0-1-2-3
0 1 1-2-3-0 1-0-3-2
1 0 2-3-0-1 2-3-0-1
1 1 3-0-1-2 3-2-1-0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Notes:

1. For a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the block.

2. For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access within the block.

3. For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access within the block.

4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.

Burst Type

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type
and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the start­ing column address, as shown in Burst Definition on page 9.

Read Latency

The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability
of the first burst of output data. The latency can be programmed 2 or 2.5 clocks.

If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with
clock edge n + m.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Preliminary

10/01

9

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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb DDR333/300 SDRAM

Extended Mode Register Definition

BA1 BA0

0* 1*

A12 - A3 A2 - A0 Operating Mode

* BA0 and BA1 must be 1, 0 to select the Extended Mode Register

(vs. the base Mode Register)

A

A11A10A

12

0 Valid Normal Operation

− −

All other states

A8A

9

Reserved

A

2

0 Disable

A6A5A

7

Operating Mode

QFC

A

4

A

3

2

0**

Drive Strength

A

0 Normal
1 Reserved

Drive Strength

1

A

0

0 Enable
1 Disable

DLL

A1A

DS DLL

0

Address Bus
Extended

Mode Register

Preliminary

10/01

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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb DDR333/300 SDRAM

Commands

Truth Tables 1a and 1b provide a reference of the commands supported by DDR SDRAM devices. A verbal description of each
commands follows.

Truth Table 1a: Commands

Name (Function) CS RAS CAS WE Address MNE Notes
Deselect (Nop) H X X X X NOP 1, 9
No Operation (Nop) L H H H X NOP 1, 9
Active (Select Bank And Activate Row) L L H H Bank/Row ACT 1, 3
Read (Select Bank And Column, And Start Read Burst) L H L H Bank/Col Read 1, 4
Write (Select Bank And Column, And Start Write Burst) L H L L Bank/Col Write 1, 4
Burst Terminate L H H L X BST 1, 8
Precharge (Deactivate Row In Bank Or Banks) L L H L Code PRE 1, 5
Auto Refresh Or Self Refresh (Enter Self Refresh Mode) L L L H X AR / SR 1, 6, 7
Mode Register Set L L L L Op-Code MRS 1, 2

1. CKE is high for all commands shown except Self Refresh.

2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects
Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode
Register.)

3. BA0-BA1 provide bank address and A0-A12 provide row address.

4. BA0, BA1 provide bank address; A0-Ai provide column address (where i = 9 for x8 and 9, 11 for x4); A10 high enables the Auto Pre­charge feature (nonpersistent), A10 low disables the Auto Precharge feature.

5. A10 LOW: BA0, BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care.”

6. This command is auto refreshif CKE is high; Self Refresh if CKE is low.

7. Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto
Precharge enabled or for write bursts

9. Deselect and NOP are functionally interchangeable.

Truth Table 1b: DM Operation

Name (Function) DM DQs Notes

Write Enable L Valid 1

Write Inhibit H X 1

1. Used to mask write data; provided coincident with the corresponding data.

Preliminary

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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb DDR333/300 SDRAM

Truth Table 2: Clock Enable (CKE)

1. CKE n is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.

2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.

3. Command n is the command registered at clock edge n, and action n is a result of command n.

4. All states and sequences not shown are illegal or reserved.

CKE n-1 CKEn

Current State

Self Refresh L L X Maintain Self-Refresh

Self Refresh L H Deselect or NOP Exit Self-Refresh 1
Power Down L L X Maintain Power-Down
Power Down L H Deselect or NOP Exit Power-Down

All Banks Idle H L Deselect or NOP Precharge Power-Down Entry
All Banks Idle H L Auto Refresh Self Refresh Entry

Bank(s) Active H L Deselect or NOP Active Power-Down Entry

Previous

Cycle

H H

Current

Cycle

See “Truth Table 3: Current State

Bank n - Command to Bank n (Same

Command n Action n Notes

Bank)” on page 13

1. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (t
200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.

) period. A minimum of

XSNR

Preliminary

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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb DDR333/300 SDRAM

Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)

Current State CS RAS CAS WE Command Action Notes

Any

Idle

Row Active

Read

(Auto Precharge

Disabled)

Write

(Auto Precharge

Disabled)

H X X X Deselect NOP. Continue previous operation 1-6

L H H H No Operation NOP. Continue previous operation 1-6
L L H H Active Select and activate row
L L L H Auto Refresh
L L L L Mode Register Set
L H L H Read Select column and start Read burst
L H L L Write Select column and start Write burst
L L H L Precharge Deactivate row in bank(s)
L H L H Read Select column and start new Read burst
L L H L Precharge Truncate Read burst, start Precharge
L H H L Burst Terminate Burst Terminate
L H L H Read Select column and start Read burst
L H L L Write Select column and start Write burst
L L H L Precharge Truncate Write burst, start Precharge

1-6, 10, 11

1-6
1-7

1-7
1-6, 10
1-6, 10

1-6, 8

1-6, 10

1-6, 8
1-6, 9

1-6, 10

1-6, 8, 11

1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t
met (if the previous state was self refresh).

2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed
to be issued to that bank when in that state. Exceptions are covered in the notes below.

3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and t

progress.
Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

4. The following states must not be interrupted by a command issued to the same bank.
Precharging: Starts with registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank is in the idle

state.

Row Activating: Starts with registration of an Active command and ends when t

active” state.

Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when tRP has been

met. Once tRP is met, the bank is in the idle state.

Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when tRP has been

met. Once tRP is met, the bank is in the idle state.

Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these

states. Allowable commands to the other bank are determined by its current state and according to Truth Table 4.

5. The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive
clock edge during these states.
Refreshing: Starts with registration of an Auto Refresh command and ends when t

in the “all banks idle” state.

Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when t

met, the DDR SDRAM is in the “all banks idle” state.

Precharging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in the idle

state.

6. All states and sequences not shown are illegal or reserved.

7. Not bank-specific; requires that all banks are idle.

8. May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.

9. Not bank-specific; Burst terminate affects the most recent Read burst, regardless of bank.

10. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.

11. Requires appropriate DM masking.

has been met. No data bursts/accesses and no register accesses are in

RCD

is met. Once t

RCD

RFC

is met. Once t

is met, the bank is in the “row

RCD

MRD

XSNR / tXSRD

is met, the DDR SDRAM is

RFC

has been met. Once t

has been

is

MRD

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Truth Table 4: Current State Bank n - Command to Bank m (Different bank)

(Part 1 of 2)

Current State CS RAS CAS WE Command Action Notes

Any

Idle X X X X

Row Activating,

Active, or

Precharging

Read

(Auto Precharge

Disabled)

Write

(Auto Precharge

Disabled)

H X X X Deselect NOP/continue previous operation 1-6

L H H H No Operation NOP/continue previous operation 1-6

Any Command Otherwise

Allowed to Bank m
L L H H Active Select and activate row 1-6
L H L H Read Select column and start Read burst 1-7
L H L L Write Select column and start Write burst 1-7
L L H L Precharge 1-6
L L H H Active Select and activate row 1-6
L H L H Read Select column and start new Read burst 1-7
L L H L Precharge 1-6
L L H H Active Select and activate row 1-6
L H L H Read Select column and start Read burst 1-8
L H L L Write Select column and start new Write burst 1-7
L L H L Precharge 1-6

1-6

1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t
met (if the previous state was self refresh).

2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are
those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are cov­ered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and t

Row Active: A row in the bank has been activated, and t

in progress.
Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Read with Auto Precharge Enabled: See note 10.
Write with Auto Precharge Enabled: See note 10.

4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle.

5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only.

6. All states and sequences not shown are illegal or reserved.

7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.

8. Requires appropriate DM masking.

9. A Write command may be applied after the completion of data output.

10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the access
period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with
Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses all of the data in the burst.
For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The

access period starts with registration of the command and ends where the precharge period (or tRP) begins. During the precharge period
of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, Active, Precharge, Read, and Write commands

to the other bank may be applied; during the access period, only Active and Precharge commands to the other bank may be applied. In
either case, all other related limitations apply (e.g. contention between Read data and Write data must be avoided).

has been met.

RP

RCD

has been met. No data bursts/accesses and no register accesses are

XSNR / tXSRD

has been

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Truth Table 4: Current State Bank n - Command to Bank m (Different bank)

(Part 2 of 2)

Current State CS RAS CAS WE Command Action Notes

L L H H Active Select and activate row 1-6

Read (With

Auto Precharge)

Write (With

Auto Precharge)

L H L H Read Select column and start new Read burst 1-7,10
L H L L Write Select column and start Write burst 1-7,9,10
L L H L Precharge 1-6
L L H H Active Select and activate row 1-6
L H L H Read Select column and start Read burst 1-7,10
L H L L Write Select column and start new Write burst 1-7,10
L L H L Precharge 1-6

1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t
met (if the previous state was self refresh).

2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are
those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are cov­ered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and t

Row Active: A row in the bank has been activated, and t

in progress.
Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Read with Auto Precharge Enabled: See note 10.
Write with Auto Precharge Enabled: See note 10.

4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle.

5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only.

6. All states and sequences not shown are illegal or reserved.

7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.

8. Requires appropriate DM masking.

9. A Write command may be applied after the completion of data output.

10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the access
period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with
Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses all of the data in the burst.
For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The

access period starts with registration of the command and ends where the precharge period (or tRP) begins. During the precharge period
of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, Active, Precharge, Read, and Write commands

to the other bank may be applied; during the access period, only Active and Precharge commands to the other bank may be applied. In
either case, all other related limitations apply (e.g. contention between Read data and Write data must be avoided).

has been met.

RP

RCD

has been met. No data bursts/accesses and no register accesses are

XSNR / tXSRD

has been

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Absolute Maximum Ratings

Symbol Parameter Rating Units

VIN, V

V

V

V

DDQ

T

T

STG

P

I

OUT

Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rat­ing only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci­fication is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Voltage on I/O pins relative to V

OUT

Voltage on Inputs relative to V

IN

Voltage on VDD supply relative to V

DD

Voltage on V
Operating Temperature (Ambient) 0 to +70 °C

A

Storage Temperature (Plastic) −55 to +150 °C
Power Dissipation 1.0 W

D

Short Circuit Output Current 50 mA

supply relative to V

DDQ

SS

SS

SS

SS

−0.5 to V

+ 0.5 V

DDQ

−0.5 to +3.6 V

−0.5 to +3.6 V

−0.5 to +3.6 V

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Capacitance

Parameter Symbol Min. Max. Units Notes

Input Capacitance: CK, CK CI

1

Delta Input Capacitance: CK, CK delta CI
Input Capacitance: All other input-only pins (except DM) CI

2

Delta Input Capacitance: All other input-only pins (except DM) delta CI
Input/Output Capacitance: DQ, DQS, DM C
Delta Input/Output Capacitance: DQ, DQS, DM delta C

1. V

= VDD = 2.5V ± 0.2V (minimum range to maximum range), f = 100MHz, TA = 25°C, VODC = V

DDQ

2. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is

IO

IO

2.0 3.0 pF 1

1

0.25 pF 1

2.0 3.0 pF 1

2

0.5 pF 1

4.0 5.0 pF 1, 2

0.5 pF 1

DDQ/2

, VO

Peak -Peak

=0.2V.

required to match input propagation times of DQ, DQS and DM in the system.

DC Electrical Characteristics and Operating Conditions

(0°C ≤ T

≤ 70°C; V

A

= 2.5V ± 0.2V, V

DDQ

= + 2.5V ± 0.2V, see AC Characteristics)

DD

Symbol Parameter Min Max Units Notes

V

V

DDQ

VSS, V

V

REF

V

V

IH(DC)

V

IL(DC)

V

IN(DC)

V

ID(DC)

VI

Ratio

I

OZ

I

OH

I

OL

1. Inputs are not recognized as valid until V

2. V
noise on V

3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to V
must track variations in tHalf-he DC level of V

4. VID is the magnitude of the difference between the input level on CK and the input level on CK.

Supply Voltage 2.3 2.7 V 1

DD

I/O Supply Voltage 2.3 2.7 V 1
Supply Voltage

SSQ

I/O Supply Voltage
I/O Reference Voltage 0.49 x V
I/O Termination Voltage (System) V

TT

Input High (Logic1) Voltage V
Input Low (Logic0) Voltage − 0.3 V
Input Voltage Level, CK and CK Inputs − 0.3 V
Input Differential Voltage, CK and CK Inputs 0.30 V

0 0 V

DDQ

− 0.04 V

REF

+ 0.15 V

REF

0.51 x V

DDQ

+ 0.04 V 1, 3

REF

+ 0.3 V 1

DDQ

− 0.15 V 1

REF

+ 0.3 V 1

DDQ

+ 0.6 V 1, 4

DDQ

V-I Matching Pullup Current to Pulldown Current Ratio 0.71 1.4 5
Input Leakage Current

I

I

Any input 0V ≤ VIN ≤ VDD; (All other pins not under test = 0V)
Output Leakage Current

(DQs are disabled; 0V ≤ V

out

≤ V

DDQ

Output Current: Nominal Strength Driver
High current (V
Low current (V

is expected to be equal to 0.5 V

REF

may not exceed ± 2% of the DC value.

REF

= V

OUT

DDQ

= 0.373V, max V

OUT

-0.373V, min V

REF

of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak

DDQ

REF

, max VTT)

REF

stabilizes.

.

REF

, min VTT)

− 5 5 µA 1

− 5 5 µA 1

− 16.8

16.8

V 1, 2

mA 1

REF

, and

5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire tempera-ture and
voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum difference
between pullup and pulldown drivers due to process variation.

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DC Electrical Characteristics and Operating Conditions

(0°C ≤ T

≤ 70°C; V

A

= 2.5V ± 0.2V, V

DDQ

= + 2.5V ± 0.2V, see AC Characteristics)

DD

Symbol Parameter Min Max Units Notes

I

OHW

I

OLW

Output Current: Half- Strength Driver
High current (V
Low current (V

= V

OUT

DDQ

= 0.763V, max V

OUT

-0.763V, min V
, max VTT)

REF

, min VTT)

REF

− 9.0
mA 1

9.0

1. Inputs are not recognized as valid until V

2. V

is expected to be equal to 0.5 V

REF

noise on V

may not exceed ± 2% of the DC value.

REF

3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to V
must track variations in tHalf-he DC level of V

stabilizes.

REF

of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak

DDQ

.

REF

REF

, and

4. VID is the magnitude of the difference between the input level on CK and the input level on CK.

5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire tempera-ture and
voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum difference
between pullup and pulldown drivers due to process variation.

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AC Characteristics

(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, IDD
Specifications and Conditions, and Electrical Characteristics and AC Timing.)

1. All voltages referenced to VSS.

2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage
levels, but the related specifications and device operation are guaranteed for the full voltage range specified.

3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.

4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced
to V

(or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels

REF

under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between V
V

.

IH(AC)

IL(AC)

and

5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a
result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above
(below) the DC input low (high) level.

AC Output Load Circuit Diagrams

V

TT

Output
(V

OUT

50Ω

)

Timing Reference Point

30pF

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DQS/DQ/DM Slew Rate

DDR333

Parameterl Symbol

Min Max

DCS/DQ/DM

input slew rate

1. Measured between V IH (DC), V IL (DC), and V IL (DC), V IH (DC).

2. DQS, DQ, and DM input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal tran-sition
through the DC region must be monotonic..

DC

SLEW

TBD TBD

(-6)

Unit Notes

V/ns

1,2

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AC Input Operating Conditions (0 °C ≤ T

≤ 70 °C; V

A

= 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC

DDQ

Characteristics)

Symbol Parameter/Condition Min Max Unit Notes

V

IH(AC)

V

IL(AC)

V

ID(AC)

V

IX(AC)

Input High (Logic 1) Voltage, DQ, DQS, and DM Signals V

+ 0.31 V 1, 2

REF

Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals V
Input Differential Voltage, CK and CK Inputs 0.62 V
Input Crossing Point Voltage, CK and CK Inputs 0.5*V

− 0.2 0.5*V

DDQ

− 0.31 V 1, 2

REF

+ 0.6 V 1, 2, 3

DDQ

+ 0.2 V 1, 2, 4

DDQ

1. Input slew rate = 1V/ns.

2. Inputs are not recognized as valid until V

stabilizes.

REF

3. VID is the magnitude of the difference between the input level on CK and the input level on CK.

4. The value of VIX is expected to equal 0.5*V

IDD Specifications and Conditions (0 °C ≤ T

of the transmitting device and must track variations in the DC level of the same.

DDQ

≤ 70 °C; V

A

= 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC

DDQ

Characteristics)

Symbol Parameter/Condition

Operating Current: one bank; active / precharge; tRC = tRC (min); DQ, DM, and

I

DD0

DQS inputs changing twice per clock cycle; address and control inputs changing
once per clock cycle

Operating Current: one bank; active / read / precharge; Burst = 2; tRC = tRC

I

DD1

I

DD2P

I

DD2N

I

DD3P

(min); CL = 2.5; I
cycle

= 0mA; address and control inputs changing once per clock

OUT

Precharge Power-Down Standby Current: all banks idle; power-down mode;
CKE ≤ V

IL

(max)

Idle Standby Current: CS ≥ VIH (min); all banks idle; CKE ≥ VIH (min);
address and control inputs changing once per clock cycle

Active Power-Down Standby Current: one bank active; power-down mode;
CKE ≤ V

IL

(max)

Active Standby Current: one bank; active / precharge; CS ≥ VIH (min);

I

DD3N

CKE ≥ VIH (min); tRC = t
clock cycle; address and control inputs changing once per clock cycle

(max); DQ, DM, and DQS inputs changing twice per

RAS

Operating Current: one bank; Burst = 2; reads; continuous burst; address and

I

DD4R

control inputs changing once per clock cycle; DQ and DQS outputs changing
twice per clock cycle; CL = 2.5; I

OUT

= 0mA

Operating Current: one bank; Burst = 2; writes; continuous burst; address and

I

DD4W

I

DD5

I

DD6

control inputs changing once per clock cycle; DQ and DQS inputs changing twice
per clock cycle; CL = 2.5

Auto-Refresh Current: tRC = t

(min) 170 mA 1

RFC

Self-Refresh Current: CKE ≤ 0.2V 3 mA 1, 2
Operating current: four bank; four bank interleaving with BL = 4, address and

I

DD7

control inputs randomly changing; 50% of data changing at every transfer;
t RC = t RC (min); I OUT = 0mA.

DDR333

tCK=6ns

DDR333

tCK=6.6ns

Unit Notes

85 mA 1

110 mA 1

15 mA 1

35 mA 1

15 mA 1

60 mA 1

165 mA 1

150 mA 1

150 mA 1

1. IDD specifications are tested after the device is properly initialized.

2. Enables on-chip refresh and address counters.

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Electrical Characteristics & AC Timing - Absolute Specifications

(0 °C ≤ TA ≤ 70 °C; V

= 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 1 of 2)

DDQ

Symbol Parameter

t

DQ output access time from CK/CK − 0.7 + 0.7 − 0.75 + 0.75 ns 1-4

AC

t

DQSCK

t

DIPW

t

DQSQ

t

t

DQSS

t

DQSL,H

t
t

t

MRD

t

WPRES

t

WPST

t

WPRE

t

t

RPRE

t

RPST

t

DQS output access time from CK/CK − 0.7 + 0.7 − 0.75 + 0.75 ns 1-4

t

CK high-level width 0.45 0.55 0.45 0.55 t

CH

t

CK low-level width 0.45 0.55 0.45 0.55 t

CL

t

Clock cycle time

CK

t

DQ and DM input hold time 0.45 0.5 ns

DH

t

DQ and DM input setup time 0.45 0.5 ns

DS

DQ and DM input pulse width (each input) 1.75 1.75 ns 1-4

t

Data-out high-impedance time from CK/CK − 0.7 + 0.7 − 0.75 + 0.57 ns 1-4, 5

HZ

t

Data-out low-impedance time from CK/CK − 0.7 + 0.7 − 0.75 + 0.75 ns 1-4, 5

LZ

DQS-DQ skew (DQS & associated DQ signals) + 0.4 + 0.5 ns 1-4
minimum half clk period for any given cycle;

t

HP

defined by clk high (tCH) or clk low (tCL) time
Data output hold time from DQS t

QH

Write command to 1st DQS latching
transition

DQS input low (high) pulse width (write cycle) 0.35 0.35 t
DQS falling edge to CK setup time (write cycle) 0.2 0.2 t

DSS

DQS falling edge hold time from CK (write cycle) 0.2 0.2 t

DSH

Mode register set command cycle time 2 x t
Write preamble setup time 0 0 ns 1-4, 7
Write postamble 0.40 0.60 0.40 0.60 t
Write preamble 0.25 0.25 t
Address and control input hold time

t

IH

(fast slew rate)
Address and control input setup time

t

IS

(fast slew rate)
Address and control input hold time

t

IH

(slow slew rate)
Address and control input setup time

t

IS

(slow slew rate)
Input pulse width 2.2 2.2 ns 2-4, 12

IPW

Read preamble 0.9 1.1 0.9 1.1 t
Read postamble 0.40 0.60 0.40 0.60 t
Active to Precharge command 42 120,000 45 120,000 ns 1-4

RAS

DDR333

(-6)

DDR300

(-66)

Min Max Min Max

CL = 2.5 6 12 6.6 12
CL = 2.0 7.5 12 7.5 12

min

(t

CH,tCL)

- t

HP

QHS

t

(t

HP

min

CH,tCL)

- t

QHS

0.75 1.25 0.75 1.25 t

CK

2 x t

CK

0.75 0.9 ns

0.75 0.9 ns

0.8 1.0 ns

0.8 1.0 ns

Unit Notes

CK

CK

1-4
1-4

ns 1-4

1-4,

15,16

1-4,

15,16

t

CK

t

CK

CK

CK

CK

CK

1-4

1-4

1-4

1-4
1-4
1-4

ns 1-4

1-4, 6

CK

CK

1-4

2-4,

9,11,12

2-4,

9,11,12

2-4, 10,

11,12,14

2-4, 10,

11,12,14

CK

CK

1-4
1-4

Preliminary

10/01

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© NANYA TECHNOLOGY CORP. All rights reserved.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb DDR333/300 SDRAM

Electrical Characteristics & AC Timing - Absolute Specifications

(0 °C ≤ TA ≤ 70 °C; V

= 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 2 of 2)

DDQ

Symbol Parameter

t

Active to Active/Auto-refresh command period 60 65 ns 1-4

RC

t

t

RCD

t

t

RRD

t

t

t

WTR

t

XSNR

t

XSRD

t

REFI

Auto-refresh to Active/Auto-refresh

RFC

command period
Active to Read or Write delay 18 20 ns 1-4
Active to Read Command with Autoprecharge 18 20 ns 1-4

RAP

t

Precharge command period 18 20 ns 1-4

RP

Active bank A to Active bank B command 12 15 ns 1-4
Write recovery time 15 15 ns 1-4

WR

Auto precharge write recovery

DAL

+ precharge time

Internal write to read command delay 1 1 t
Exit self-refresh to non-read command 75 75 ns 1-4
Exit self-refresh to read command 200 200 t
Average Periodic Refresh Interval 7.8 7.8 µs 1-4, 8

DDR333

(-6)

DDR300

(-66)

Unit Notes

Min Max Min Max

72 75 ns 1-4

(tWR/t

(tRP/t

CK)

+

CK)

(tWR/t

(tRP/t

CK)

+

CK)

t

CK

CK

CK

1-4,13

1-4

1-4

Preliminary

10/01

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© NANYA TECHNOLOGY CORP. All rights reserved.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb DDR333/300 SDRAM

Electrical Characteristics & AC Timing - Absolute Specifications
Notes

1. Input slew rate = 1V/ns.

2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross:
the input reference level for signals other than CK/CK, is VREF.

3. Inputs are not recognized as valid until VREF stabilizes.

4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT .

5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred

to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).

6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.

7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A
valid
transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were prev­ iously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS
could be HIGH, LOW, or transitioning from high to low at this time, depending on t DQSS .

8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.

9. For command/address input slew rate ≥ 1.0V/ns. Slew rate is measured between V OH (AC) and V OL (AC).

10. For command/address input slew rate ≥ 0.5V/ns and < 1.0V/ns. Slew rate is measured between VOH (AC) and V OL (AC).

11. CK/CK slew rates are ≥ 1.0V/ns.

12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guara­ nteed by design or tester characterization.

13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. tCK is equal to the actual
system clock cycle time.

Preliminary

10/01

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© NANYA TECHNOLOGY CORP. All rights reserved.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb DDR333/300 SDRAM

14. An input setup and hold time derating table is used to increase t IS and t IH in the case where the input slew
rate is below 0.5 V/ns.

Input Slew Rate

0.5 V/ns

0.4 V/ns

0.3 V/ns

1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly for rising
transitions.

2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on eachdevice.

delta ( t IS) delta ( t IH)

0 0 ps 1,2

+50 0 ps 1,2

+100 0 ps 1,2

Unit Notes

15. An input setup and hold time derating table is used to increase t DS and t DH in the case where the I/O slew rate is below

0.5 V/ns.

Input Slew Rate

0.5 V/ns

0.4 V/ns

0.3 V/ns

1. I/O slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly for rising
transitions.

2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on eachdevice.

delta ( t DS) delta ( t DH)

0 0 ps 1,2

+75 +75 ps 1,2

+150 +150 ps 1,2

Unit Notes

16. An I/O Delta Rise, Fall Derating table is used to increase t DS and t DH) in the case where DQ, DM, and DQS slew rates
differ.

Input Slew Rate

0.0 V/ns

0.25 V/ns

0.5 V/ns

1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly for rising
transitions.

2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate.

3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)]
For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns
Delta rise, fall = (1/0.5) - (1/0.4) [ns/V]

= -0.5 ns/V
Using the table above, this would result in an increase in t DS and t DH of 100 ps.

4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.

delta ( t DS) delta ( t DH)

0 0 ps 1,2,3,4

+50 +50 ps 1,2,3,4

+100 +100 ps 1,2,3,4

Unit Notes

Preliminary

10/01

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© NANYA TECHNOLOGY CORP. All rights reserved.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb DDR333/300 SDRAM

Package Dimensions (400mil; 66 lead; Thin Small Outline Package)

22.22 ± 0.10

Detail A

10.16 ±. 0.13

11.76 ± 0.20

Lead #1

0.65 Basic 0.30

+ 0.03

- 0.08

1.20 Max

0.05 Min

0.71REF

Detail A

0.10

0.25 Basic

0.5 ± 0.1

Seating Plane

Gage Plane

Preliminary

10/01

26

© NANYA TECHNOLOGY CORP. All rights reserved.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW

256Mb DDR333/300 SDRAM

Package Dimensions ( 60 balls ; 0.8mmx1.0mm Pitch ; CSP Package)

8.5

1.05 0.80

1.000.50

15.50

Dia.

0.45

2.25

0.80

Note : All dimensions are typical unless otherwise stated.
Unit : Millimeters

0.35

1.15

Preliminary

10/01

27

© NANYA TECHNOLOGY CORP. All rights reserved.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.