Page 1
5
VIDEO IN
CONNECTOR
D D
SHT 20
MEMORY CHANNEL A
Rank 1
Rank 0
DDRI (16X16 TSOP)
SHT 13,14
4
3
2
1
MEMORY CHANNEL B
Rank 1
Rank 0
DDRI (16X16 TSOP)
SHT 13,14
MEMORY TERMINATIONS A
SHT 12
MAA[14..0]
QSA[7..0]
CASA#
QSA#[7..0]
RASA#
CLKA01
DQMA[0..7]
WEA#
CLKA01#
RESET
CSA#01MDA[63..0]
CKEA/B
MAB[14..0]
QSB[7..0]
CASB#
MAB[14..0]
RASB#
MEM A MEM B
STRAPS
SHT 15
C C
B B
POWER
REGULATION
SHT 5, 6, 7, 8, 9,10
From +12v
SINGLE PHASE SWITCHING:
VDDC, MVDDC, MVDDQ,+VTT
From +12V DIRECT:
FAN
From +12V LINEAR:
+5V, RAGE THEATER
From +3.3 V LINEAR:
AVDD, VDD15, VDDRH
TPVDD, TXVDDR, PVDD,
AVDDDI, A2VDD, A2VDDDI,
A2VDDQ, PCIE_VDDR,
PCIE_PVDD_18, VDDC_CT
VDDR4, VDDR5
From +3.3 V DIRECT:
VDDR3
Speed control
& temperature
SHT 17
sense
POWER DELIVERY
BIOS
SHT 4
FAN
SHT 15
ROMCS#
GPIO
ROM
SHEET 3, 4, 5, 6, 11
RV410
DAC1
VIP
TVO
DAC2
CRT
TMDS
MEMORY TERMINATIONS B
DQMB[0..7]
WEB#
QSB#[7..0] RESET
CLKB01#
CSB#01
CKEBCLKB01
SHT 12
DVP
R G B HSY VSY DDC1DATA DDC1CLK
TMDS_TX[C,2..0]N TMDS_TX[C,2..0]P HPD, DDC2CLK DDC2DATA
External TMDS
PRIMARY CRT
FILTERS
SHEET 16
Rage Theater 1
SHT 19
TVOUT
FILTERS
SHT 20
SECONDARY
CRT FILTERS
SHT 16, 17
IMPEDANCE
MATCHING
SHT 4
DVI-I
CONN
SHT 19
TVout/
VIVO
CONN
SHT 21
DVI-I
CONN
SHT 19
PCI-Express
PCI-Express Bus
SHT 2
RV410 Trinity Board
REV 0.3
A A
Size Document Number Rev
C
5
4
3
2
Date: Sheet
MS-V016 ATI RV410
Monday, June 13, 2005
1
124
0A
of
www.vinafix.vn
Page 2
5
+12V_BUS +3.3V_BUS
C10
100uF_16V
4260110700
D D
C3
100uF_16V
4260110700
4
PCI-EXPRESS BUS
3
2
1
SYMBOL LEGEND
DO NOT
DNI
INSTALL
ACTIVE
#
LOW
DIGITAL
GROUND
ANALOG
GROUND
+12V_BUS
+3.3V_BUS
MPCIE1
B1
+12V#B1
B2
+12V#B2
B3
RSVD#B3
B4
GND#B4
B5
SMCLK
B6
SMDAT
B7
GND#B7
DNI
3230000000
JTAG_TRST#
PRESENCE
HSYNC_DAC1(4,15,16)
PETp0_GFXRp0(3) PCIE_REFCLKN (3)
PETn0_GFXRn0(3)
PETp1_GFXRp1(3)
C C
B B
PETn1_GFXRn1(3)
PETp2_GFXRp2(3)
PETn2_GFXRn2(3)
PETp3_GFXRp3(3)
PETn3_GFXRn3(3)
PETp4_GFXRp4(3)
PETn4_GFXRn4(3)
PETp5_GFXRp5(3)
PETn5_GFXRn5(3)
PETp6_GFXRp6(3)
PETn6_GFXRn6(3)
PETp7_GFXRp7(3)
PETn7_GFXRn7(3)
PETp8_GFXRp8(3)
PETn8_GFXRn8(3)
PETp9_GFXRp9(3)
PETn9_GFXRn9(3)
PETp10_GFXRp10(3)
PETn10_GFXRn10(3)
PETp11_GFXRp11(3)
PETn11_GFXRn11(3)
PETp12_GFXRp12(3)
PETn12_GFXRn12(3)
PETp13_GFXRp13(3)
PETn13_GFXRn13(3)
PETp14_GFXRp14(3)
PETn14_GFXRn14(3)
PETp15_GFXRp15(3)
PETn15_GFXRn15(3)
R1008 0R
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
+3.3V#B8
JTAG1
3.3Vaux
WAKE#
RSVD#B12
GND#B13
PETp0
PETn0
GND#B16
PRSNT2#B17
GND#B18
PETp1
PETn1
GND#B21
GND#B22
PETp2
PETn2
GND#B25
GND#B26
PETp3
PETn3
GND#B29
RSVD#B30
PRSNT2#B31
GND#B32
PETp4
PETn4
GND#B35
GND#B36
PETp5
PETn5
GND#B39
GND#B40
PETp6
PETn6
GND#B43
GND#B44
PETp7
PETn7
GND#B47
PRSNT2#B48
GND#B49
PETp8
PETn8
GND#B52
GND#B53
PETp9
PETn9
GND#B56
GND#B57
PETp10
PETn10
GND#B60
GND#B61
PETp11
PETn11
GND#B64
GND#B65
PETp12
PETn12
GND#B68
GND#B69
PETp13
PETn13
GND#B72
GND#B73
PETp14
PETn14
GND#B76
GND#B77
PETp15
PETn15
GND#B80
PRSNT2#B81
RSVD#B82
x16 PCIe
614NOPN084
Mechanical Key
PRSNT1#A1
+12V#A2
+12V#A3
GND#A4
JTAG2
JTAG3
JTAG4
JTAG5
+3.3V#A9
+3.3V#A10
PERST#
GND#A12
REFCLK+
REFCLKGND#A15
PERp0
PERn0
GND#A18
RSVD#A19
GND#A20
PERp1
PERn1
GND#A23
GND#A24
PERp2
PERn2
GND#A27
GND#A28
PERp3
PERn3
GND#A31
RSVD#A32
RSVD#A33
GND#A34
PERp4
PERn4
GND#A37
GND#A38
PERp5
PERn5
GND#A41
GND#A42
PERp6
PERn6
GND#A45
GND#A46
PERp7
PERn7
GND#A49
RSVD#A50
GND#A51
PERp8
PERn8
GND#A54
GND#A55
PERp9
PERn9
GND#A58
GND#A59
PERp10
PERn10
GND#A62
GND#A63
PERp11
PERn11
GND#A66
GND#A67
PERp12
PERn12
GND#A70
GND#A71
PERp13
PERn13
GND#A74
GND#A75
PERp14
PERn14
GND#A78
GND#A79
PERp15
PERn15
GND#A82
+12V_BUS
+3.3V_BUS
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
PRESENCE
R1835 0R
C300
100nF
C302
100nF
C304
100nF
C306
100nF
C308
100nF
C310
100nF
C312
100nF
C314
100nF
C316
100nF
C318
100nF
C320
100nF
C322
100nF
C324
100nF
C326
100nF
C328
100nF
C330
100nF
3270002800
RP1D 0R
RP1C 0R
RP1B 0R
RP1A 0R
C301
100nF
C303
100nF
C305
100nF
C307
100nF
C309
100nF
C311
100nF
C313
100nF
C315
100nF
C317
100nF
C319
100nF
C321
100nF
C323
100nF
C325
100nF
C327
100nF
C329
100nF
C331
100nF
54
63
72
81
DNI
DNI
DNI
DNI
PCIE_REFCLKP (3)
GFXTp0_PERp0 (3)
GFXTn0_PERn0 (3)
GFXTp1_PERp1 (3)
GFXTn1_PERn1 (3)
GFXTp2_PERp2 (3)
GFXTn2_PERn2 (3)
GFXTp3_PERp3 (3)
GFXTn3_PERn3 (3)
GFXTp4_PERp4 (3)
GFXTn4_PERn4 (3)
GFXTp5_PERp5 (3)
GFXTn5_PERn5 (3)
GFXTp6_PERp6 (3)
GFXTn6_PERn6 (3)
GFXTp7_PERp7 (3)
GFXTn7_PERn7 (3)
GFXTp8_PERp8 (3)
GFXTn8_PERn8 (3)
GFXTp9_PERp9 (3)
GFXTn9_PERn9 (3)
GFXTp10_PERp10 (3)
GFXTn10_PERn10 (3)
GFXTp11_PERp11 (3)
GFXTn11_PERn11 (3)
GFXTp12_PERp12 (3)
GFXTn12_PERn12 (3)
GFXTp13_PERp13 (3)
GFXTn13_PERn13 (3)
GFXTp14_PERp14 (3)
GFXTn14_PERn14 (3)
GFXTp15_PERp15 (3)
GFXTn15_PERn15 (3)
VSYNC_DAC1 (4,15,16)
CRT1DDCDATA (4,16)
SCL (4,17,18)
CRT1DDCCLK (4,16)
PERST#
+5V
74ACT08MTC
5
4
R3 100R
6
U2B
1
2
R4
180R
402
+5V
14
+-U2A
74ACT08MTC
7
PERST#_buf (3,18,20)
3
C1
100nF
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
PERp0
PERn0
PERp1
PERn1
PERp2
PERn2
PERp3
PERn3
PERp4
PERn4
PERp5
PERn5
PERp6
PERn6
PERp7
PERn7
PERp8
PERn8
PERp9
PERn9
PERp10
PERn10
PERp11
PERn11
PERp12
PERn12
PERp13
PERn13
PERp14
PERn14
PERp15
PERn15
A A
Size Document Number Rev
C
Monday, June 13, 2005
5
4
3
2
Date: Sheet
Spare gate
MS-V016 ATI RV410
1
224
0A
of
www.vinafix.vn
Page 3
5
NOTE: some of the PCIE testpoints will
be available trought via on traces.
D D
4
3
2
1
AH31
AH30
AG30
AG32
AF32
AF31
AE31
AE30
AD30
AD32
AC32
AC31
AB31
AB30
AA30
AA32
AK28
AG24
AA24
AF24
AJ31
Y32
Y31
W31
W30
V30
V32
U32
U31
T31
T30
R30
R32
P32
P31
N31
AL28
U1A
PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N
PCIE_RX13P
PCIE_RX13N
PCIE_RX14P
PCIE_RX14N
PCIE_RX15P
PCIE_RX15N
PCIE_REFCLKP
PCIE_REFCLKN
PERSTB
PCIE_TEST
MCL_0
RV410
TP34
TP35
TP38
TP39
TP46
TP47
TP50
TP51
TP58
TP59
TP28
TP29
TP32
TP33
TP40
TP41
TP44
TP45
TP52
TP53
TP56
TP57
PETp0_GFXRp0(2)
PETn0_GFXRn0(2)
PETp1_GFXRp1(2)
PETn1_GFXRn1(2)
PETp2_GFXRp2(2)
PETn2_GFXRn2(2)
PETp3_GFXRp3(2)
PETn3_GFXRn3(2)
PETp4_GFXRp4(2)
PETn4_GFXRn4(2)
PETp5_GFXRp5(2)
PETn5_GFXRn5(2)
PETp6_GFXRp6(2)
C C
B B
PETn6_GFXRn6(2)
PETp7_GFXRp7(2)
PETn7_GFXRn7(2)
PETp8_GFXRp8(2)
PETp9_GFXRp9(2)
PETn9_GFXRn9(2)
PETp10_GFXRp10(2)
PETn10_GFXRn10(2)
PETp11_GFXRp11(2)
PETn11_GFXRn11(2)
PETp12_GFXRp12(2)
PETn12_GFXRn12(2)
PETp13_GFXRp13(2)
PETn13_GFXRn13(2)
PETp14_GFXRp14(2)
PETn14_GFXRn14(2)
PETp15_GFXRp15(2)
PETn15_GFXRn15(2)
PCIE_REFCLKP(2)
PCIE_REFCLKN(2)
PERST#_buf(2,18,20)
+3.3V_BUS
R1007
4.7K
NI
Clock
PART 1 OF 7
P
C
I
E
X
P
R
E
S
S
I
N
T
E
R
F
A
C
E
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13P
PCIE_TX13N
PCIE_TX14P
PCIE_TX14N
PCIE_TX15P
PCIE_TX15N
Calibration
PCIE_CALRN
PCIE_CALRP
PCIE_CALI
AK27
AJ27
AJ25
AH25
AH28
AG28
AG27
AF27
AF25
AE25
AE28
AD28
AD27
AC27
AC25
AB25
AB28
AA28
AA27
Y27
Y25
W25
W28
V28
V27
U27
U25
T25
T28
R28
R27
P27
AE24
AD24
AB24
R1010 100R
R1009 150R
R1011 10K
+PCIE_VDDR
GFXTp0_PERp0 (2)
GFXTn0_PERn0 (2)
GFXTp1_PERp1 (2)
GFXTn1_PERn1 (2)
GFXTp2_PERp2 (2)
GFXTn2_PERn2 (2)
GFXTp3_PERp3 (2)
GFXTn3_PERn3 (2)
GFXTp4_PERp4 (2)
GFXTn4_PERn4 (2)
GFXTp5_PERp5 (2)
GFXTn5_PERn5 (2)
GFXTp6_PERp6 (2)
GFXTn6_PERn6 (2)
GFXTp7_PERp7 (2)
GFXTn7_PERn7 (2)
GFXTp8_PERp8 (2)
GFXTn8_PERn8 (2)PETn8_GFXRn8(2)
GFXTp9_PERp9 (2)
GFXTn9_PERn9 (2)
GFXTp10_PERp10 (2)
GFXTn10_PERn10 (2)
GFXTp11_PERp11 (2)
GFXTn11_PERn11 (2)
GFXTp12_PERp12 (2)
GFXTn12_PERn12 (2)
GFXTp13_PERp13 (2)
GFXTn13_PERn13 (2)
GFXTp14_PERp14 (2)
GFXTn14_PERn14 (2)
GFXTp15_PERp15 (2)
GFXTn15_PERn15 (2)
R1006
4.7K
A A
Size Document Number Rev
C
5
4
3
2
Date: Sheet
MS-V016 ATI RV410
Monday, June 13, 2005
1
324
0A
of
www.vinafix.vn
Page 4
5
VID[7..0]
VID[7..0](20)
CLK_VIDCLK(20)
DVALID(15)
VID/DVO_R[11..0](18)
27MHZ
2 1
PSYNC(15)
VHAD0(20)
VHAD1(20)
VPHCTL(20)
CLK_VIPCLK(20)
DVOMODE_0(15)
DVOMODE_1(15)
LCDCNTL_R[3..0](18)
DC_Strap2(15)
DC_Strap3(15,21)
DC_Strap4(15)
PAL/NTSC(15)
DEMUX_SEL(15)
GPIO[6..0](15)
GPIO[13..8](15)
HPD_ExtTMDS(18)
ThermINT(17)
GPU_DPLUS(17)
GPU_DMINUS(17)
Y3
27_MHZ
R30
1.0M
LCDCNTL_R[3..0]
VID/DVO_R[11..0]
+VDD_1.8V
+MPVDD
Install close to ASIC to provide
return path for EMI
B33
200R
GND_PVSS
B26
200R
GND_MPVSS
XTALIN
R65
NI
150R
D D
C C
B B
C71
22pF
C79
22pF
R586499R
C46
22uF_16V
4170082000
C27
22uF_16V
+3.3V_BUS
C52582pF
C45
100nF
4170010400
+3.3V_BUS +3.3V_BUS
R51
4.7K
TP12
TP13
R587499R
C26
100nF
4170010400
1.0uF
C44
R64 0R
Overlap pads
R58
4.7K
+3.3V_BUS
C41
1.0uF
1.0uF
C43
1.0uF
C42
PVDD
PVSS
4
R60
4.7K
DVOMODE_0
DVOMODE_1
MPVDD
MPVSS
R62
221R
LCDCNTL_R0
LCDCNTL_R1
LCDCNTL_R2
LCDCNTL_R3
VID/DVO_R0
VID/DVO_R1
VID/DVO_R2
VID/DVO_R3
VID/DVO_R4
VID/DVO_R5
VID/DVO_R6
VID/DVO_R7
VID/DVO_R8
VID/DVO_R9
VID/DVO_R10
VID/DVO_R11
TP14
R43 1K
ROMCS#
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
TP60
TP61
TP62
TP63
TP64
TP65
TP66
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
TP67
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
HPD_ExtTMDS
TP68
TP69
XTALIN
XTALOUT
R66
150R
U1B
AF10
VID_0
AG10
VID_1
AH9
VID_2
AJ8
VID_3
AH8
VID_4
AG9
VID_5
AH7
VID_6
AG8
VID_7
AF7
VPCLK0
AH6
DVALID
AF8
PSYNC
AE10
VHAD_0
AE9
VHAD_1
AG7
VPHCTL
AF9
VIPCLK
AE13
SDA
AF13
SCL
AK4
DVOVMODE_0
AL4
DVOVMODE_1
AF2
DVPCNTL_0
AF1
DVPCNTL_1
AF3
DVPCNTL_2
AG1
DVPCLK
AG2
DVPDATA_0
AG3
DVPDATA_1
AH2
DVPDATA_2
AH3
DVPDATA_3
AJ2
DVPDATA_4
AJ1
DVPDATA_5
AK2
DVPDATA_6
AK1
DVPDATA_7
AK3
DVPDATA_8
AL2
DVPDATA_9
AL3
DVPDATA_10
AM3
DVPDATA_11
AE6
DVPDATA_12
AF4
DVPDATA_13
AF5
DVPDATA_14
AG4
DVPDATA_15
AJ3
DVPDATA_16
AH4
DVPDATA_17
AJ4
DVPDATA_18
AG5
DVPDATA_19
AH5
DVPDATA_20
AF6
DVPDATA_21
AE7
DVPDATA_22
AG6
DVPDATA_23
AD4
GPIO_0
AD2
GPIO_1
AD1
GPIO_2
AD3
GPIO_3
AC1
GPIO_4
AC2
GPIO_5
AC3
GPIO_6
AB2
GPIO_7
AC6
GPIO_8
AC5
GPIO_9
AC4
GPIO_10
AB3
GPIO_11
AB4
GPIO_12
AB5
GPIO_13
AD5
GPIO_14
AB8
GPIO_15
AA8
GPIO_16
AB7
GPIO_17
AB6
NC_22
AC8
VREFG
AG12
DPLUS
AH12
DMINUS
AJ14
PVDD
AH14
PVSS
A6
MPVDD
A5
MPVSS
AL26
XTALIN
AM26
XTALOUT
AG14
TESTEN
PLLTEST
AG22
TESTEN
AC7
ROMCSb
AK17
VSS_166
AJ19
VSS_167
AF18
VSS_168
AH17
VSS_169
AG17
VSS_170
AG19
VSS_171
AH19 AF21
VSS_172 VSS_173
RV410
VIP
Capture
VIP
Host
MMI2C
General
Purpose
I/O
Thermal
Diode
PLL &
XTAL
Test
ROM
PART 2 OF 7
V
I
D
E
O
&
M
U
L
T
I
M
E
D
I
A
Zoom Video Port/ VIP
Host/External TMDS
3
Integrated
TMDS
TXVDDR_1
TXVDDR_2
TXVDDR_3
TXVDDR_4
TXVSSR_1
TXVSSR_2
TXVSSR_3
TXVSSR_4
TXVSSR_5
DAC / CRT
GENERICA
GENERICB
AVDD_1
AVDD_2
AVSSN_1
AVSSN_2
DAC2 (TV/CRT2)
H2SYNC
V2SYNC
A2VDD_1
A2VDD_2
A2VSSN_1
A2VSSN_2
A2VDDQ
A2VSSQ
Monitor
Interface
DDC1DATA
DDC1CLK
DDC2DATA
DDC2CLK
DDC3DATA
DDC3CLK
GENERICC
VSS_175
VSS_174
TXCM
TXCP
TX0M
TX0P
TX1M
TX1P
TX2M
TX2P
TX3M
TX3P
TX4M
TX4P
TX5M
TX5P
TPVDD
TPVSS
HSYNC
VSYNC
RSET
AVSSQ
VDD1DI
VSS1DI
COMP
R2SET
VDD2DI
VSS2DI
HPD1
MCL_1
R2
G2
B2
R
G
B
Y
C
AL9
AM9
AK10
AL10
AL11
AM11
AL12
AM12
AK9
AJ9
AK11
AJ11
AK12
AJ12
AM8
AL8
AJ6
AK6
AL6
AM6
AJ7
AK7
AL7
AM7
AK8
AK24
AM24
AL24
AJ23
AJ22
AK22
AF23
AL22
AL25
AM25
AK23
AK25
AJ24
AM23
AL23
AK15
AM15
AL15
AF15
AG15
AJ15
AJ13
AH15
AK14
AM16
AL16
AM17
AL17
AL14
AK13
AJ16
AJ17
AF11
AH22
AH23
AH13
AG13
AE12
AF12
AE23
AE18
AF22
AF17
R33 1K
R52 499R
AVDD
GND_AVSSQ
R55 715R
GND_R2SET
1.0uF
C35
R34 1K
GND_RSET
+VDD2DI
C36
100nF
4170010400
C7
1.0uF
DNI
B8 Bead
22uF_16V
C34
C40
100nF
4170010400
2
R797 330R
R796 330R
R795 330R
R794 330R
INSTALL TERMINATION RESISTORS
CLOSE TO ASIC
C17
1.0uF
82pF
C15
4170082000
TXVDDR
C9
C8
22uF_16V
82pF
4170082000
+VDD_1.8V
Ba3
B5
+AVDD
Bead
C23
22uF_16V
GND_AVSSN
1.0uF
DNI
C33
C31
100nF
4170010400
GND_A2VSSN
+VDD_1.8V
1.0uF
C37
C13
100nF
4170010400
C32
22uF_16V
B15
200R
C16
22uF_16V
GND_TPVSS
+A2VDD
B40
200R
C38
100nF
4170010400
+TPVDD
C21
100nF
4170010400
1.0uF
C29
+A2VDDQ
C39
22uF_16V
GND_A2VSSQ
R44
Rk
0R
DNI
Ba2
B4
Bead
GND_TXVSSR
+VDDDI
C30
100nF
4170010400
Ba5
C28
22uF_16V
B9
Bead
+VDD_1.8V
B7
Bead
+3.3V_BUS
R53
4.7K
+3.3V_BUS
+VDD_1.8V
+VDD_1.8V
+3.3V_BUS
R54
4.7K
TXCM (19)
TXCP (19)
TX0M (19)
TX0P (19)
TX1M (19)
TX1P (19)
TX2M (19)
TX2P (19)
R50
4.7K
R_DAC1 (16)
G_DAC1 (16)
B_DAC1 (16)
HSYNC_DAC1 (2,15,16)
VSYNC_DAC1 (2,15,16)
STEREOSYNC (21)
R_DAC2 (16)
G_DAC2 (16)
B_DAC2 (16)
HSYNC_DAC2 (16)
VSYNC_DAC2 (16)
Y_DAC2 (21)
C_DAC2 (21)
COMP_DAC2 (21)
HPD1 (19)
CRT1DDCDATA (2,16)
CRT1DDCCLK (2,16)
CRT2DDCDATA (16)
CRT2DDCCLK (16)
SDA (17,18)
SCL (2,17,18)
1
+3.3V_BUS
R91
10K
A A
CLK_RT(20)
GPIO8
GPIO9
GPIO10
ROMCS#
7 2
5 4
6 3
8 1
RP193B33R
RP193C33R
RP193A33R
SERIAL EEPROM 512K/1M
5
4
3
ROM_SO
RP193D33R
SI/A16
SCK/WEb
CSb
HOLD1
U11
5
D
6
C
1
S
7
HOLD
+3.3V_BUS
3
W
8
VCC
M25P05-VMN6T
C80
100nF
4170010400
ALTERNAT IVE PART : M25P05(512Kbit)
2
Q
4
VSS
Size Document Number Rev
C
2
Date: Sheet
MS-V016 ATI RV410
Monday, June 13, 2005
1
424
0A
of
www.vinafix.vn
Page 5
5
D D
C C
+MVDDQ
C616
1uF
+3.3V_BUS
+VDD_1.8V
+VDD_1.8V
+3.3V_BUS
+MVDDQ
C68
47uF_6.3V
C600
1uF
C64
C70
10uf
10uf
C65
10uf
C617
C618
1uF
1uF
C67
22uF_16V
DNI
DNI
B29 220R
C602
C603
C613
1uF
C620
1uF
C609
1uF
C625
1uF
C604
1uF
1uF
C611
C610
1uF
1uF
C615
C614
1uF
1uF
C622
C621
1uF
1uF
C627
C626
1uF
1uF
1.0uF
C74
C709
100nF
C75
1.0uF
C667
C669
1uF
1uF
C601
1uF
1uF
C608
1uF
C612
C73
1uF
10uf
C619
1uF
C66
C624
1.0uF
1uF
R700R
R690R
R680R
R670R
B12
220R
B14
220R
B30 220R
C668
1uF
C605
1uF
+VDDR4
4170010400
+VDDR5
C710
100nF
4170010400
C670
1uF
C623
1uF
C707
4
U1E
C1
VDDR1_1
J1
VDDR1_2
M1
VDDR1_3
R1
VDDR1_4
V1
VDDR1_5
AA1
VDDR1_6
A3
VDDR1_7
P9
VDDR1_8
J10
VDDR1_9
N9
VDDR1_10
P10
VDDR1_11
A9
VDDR1_12
Y10
VDDR1_13
P8
VDDR1_14
R9
VDDR1_15
Y9
VDDR1_16
J11
AB10
AC19
AD18
AC20
AD19
AD20
VDDR1_17
A21
VDDR1_18
M10
VDDR1_20
N10
VDDR1_21
Y8
VDDR1_22
J18
VDDR1_23
J19
VDDR1_24
K21
VDDR1_25
A12
VDDR1_26
H13
VDDR1_27
A15
VDDR1_28
J20
VDDR1_29
J13
VDDR1_30
K11
VDDR1_31
K19
VDDR1_32
A18
VDDR1_33
L23
VDDR1_34
K20
VDDR1_35
K24
VDDR1_36
L24
VDDR1_37
H19
VDDR1_38
A24
VDDR1_39
K13
VDDR1_40
J32
VDDR1_41
A30
VDDR1_42
C32
VDDR1_43
F32
VDDR1_45
L32
VDDR1_46
AB9
VDDR3_1
VDDR3_2
AA9
VDDR3_3
VDDR3_4
VDDR3_5
VDDR3_6
VDDR3_7
VDDR3_8
AJ5
VDDR4_1
AM5
VDDR4_2
AL5
VDDR4_3
AK5
VDDR4_4
AE2
VDDR5_1
AE3
VDDR5_2
AE4
VDDR5_3
AE5
VDDR5_4
A27
VDDRH0
F1
VDDRH1
A28
VSSRH0
E1
VSSRH1
RV410
C607
C606
1uF
1uF
C69
1uF
C708
1uF
1uF
C676
1uF
Clock
I/O
PART 5 OF 7
Memory I/O
I/0
Memory
3
+VDD_1.8V
+PCIE_VDDR_12
C981
1uF
R714.7K
+A2VDD
C970
1uF
C982
1uF
C632
1uF
C637
1uF
C61
10uf
1uF
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDD15_1
VDD15_2
VDD15_3
VDDCI_1
VDDCI_2
VDDCI_3
VDDCI_4
VDDCI_5
VDDCI_6
VDDCI_7
VDDCI_8
VDDL0
VDDL0_1
VDDL0_2
VDDL0_3
VDDL1_1
VDDL1_2
VDDL1_3
VDDL2_1
VDDL2_2
VDDL2_3
V23
N23
P23
U23
N29
N28
N27
N26
N25
AL31
AM31
AM30
AL32
AL30
AM28
AL29
AM29
AM27
AC11
AC12
P14
U15
W14
W15
R17
R15
V15
V16
T16
U16
T17
U17
V14
R18
T18
V18
P18
P19
R19
W19
AD11
AC13
AC16
AC18
W10
T14
W17
P16
AC15
T23
K14
U19
AE19
AF20
AE20
AF19
AC21
AC22
AD22
AE21
AD21
AE22
PCIE_PVDD_12_1
PCIE_PVDD_12_2
PCIE_PVDD_12_3
PCIE_PVDD_12_4
PCIE_PVDD_18_1
PCIE_PVDD_18_2
PCIE_PVDD_18_3
PCIE_PVDD_18_4
PCIE_PVDD_18_5
PCIE_VDDR_12_1
PCIE_VDDR_12_2
PCIE_VDDR_12_3
PCIE_VDDR_12_4
PCIE_VDDR_12_5
PCIE_VDDR_12_6
PCIE_VDDR_12_7
PCI-Express
PCIE_VDDR_12_8
PCIE_VDDR_12_9
P
O
W
E
R
I/O Internal Core
2
+VDDC
ALT: 0R
L7 1.8uH
B27 200R
C978
C633
1uF
C638
1uF
C62
10uf
C979
1uF
1uF
C971
C976
1uF
1uF
C972
C973
1uF
1uF
C634
1uF
C639
1uF
C59
10uF_10V
C49
C50
1uF
1uF
C646
C648
1uF
1uF
C977
1uF
C974
1uF
C983
1uF
C48
C1675
10uF_6.3V
C1668
10uF_6.3V
C635
1uF
C640
1uF
C968
1uF
+VDDC_CT
C53
22uF_16V
C60
10uf
C1703
10uF_6.3V
C1704
10uF_6.3V
C1702
10uF_6.3V
C636
1uF
C641
1uF
C63
10uF_10V
+VDDC+3.3V_BUS
+PCIE_PVDD_18
+VDDC
C642
1uF
L6 1.8uH
B23 60R
C644
1uF
+PCIE_VDDR
ALT: 0R
+PCIE_VDDR
1
+VDDC
B B
A A
5
GND_VSSRH0
GND_VSSRH1
U1G
Forward
Compatibility
Y23
BBN_4
K15
BBN_3
R10
BBN_2
AC17
BBN_1
AC14
BBP_4
M23
BBP_3
V10
BBP_2
K18
BBP_1
L10
VDD25B_1
K22
VDD25B_2
AA10
VDD25A
RV410
4
PART 7 OF 7
No Connect
AD12
NC_0
AE11
NC_1
AD23
GENERICD
AJ21
NC_2
AK21
NC_3
AH21
NC_4
AG21
NC_5
AG20
NC_6
AH20
NC_7
AK20
NC_8
AJ20
NC_9
AG18
NC_10
AH18
NC_11
AK19
NC_12
AL19
NC_13
AL20
NC_14
AM20
NC_15
AL21
NC_16
AM21
NC_17
AK18
NC_18
AJ18
NC_19
AL18
NC_20
AM18
NC_21
3
TP11
Size Document Number Rev
C
2
Date: Sheet
MS-V016 ATI RV410
Monday, June 13, 2005
1
524
0A
of
www.vinafix.vn
Page 6
5
GND_TPVSS
GND_MPVSS GND_A2VSSN
GND_PVSS
GND_AVSSN
NOTE: THIS IS A DRAWING. THESE
GROUNDS MUST BE MANUALLY
CONNECTED TO THE GROUND PLANE
D D
C C
B B
A A
GND_TXVSSR
5
GND_A2VSSQ
GND_AVSSQ
GND_RSET
GND_R2SET
GND_VSSRH0
GND_VSSRH1
GND_TVVSSN
4
U1F
AH27
PCIE_VSS_1
AC23
PCIE_VSS_2
AL27
PCIE_VSS_3
R23
PCIE_VSS_4
P25
PCIE_VSS_5
R25
PCIE_VSS_6
T26
PCIE_VSS_7
U26
PCIE_VSS_8
W26
PCIE_VSS_9
Y26
PCIE_VSS_10
AB26
PCIE_VSS_11
AC26
PCIE_VSS_12
AD25
PCIE_VSS_13
AE26
PCIE_VSS_14
AF26
PCIE_VSS_15
AD26
PCIE_VSS_16
AG25
PCIE_VSS_17
AH26
PCIE_VSS_18
AC28
PCIE_VSS_19
Y28
PCIE_VSS_20
U28
PCIE_VSS_21
P28
PCIE_VSS_22
AH29
PCIE_VSS_23
AF28
PCIE_VSS_24
V29
PCIE_VSS_25
AC29
PCIE_VSS_26
W27
PCIE_VSS_27
AB27
PCIE_VSS_28
V26
PCIE_VSS_29
AJ26
PCIE_VSS_30
AJ32
PCIE_VSS_31
AK29
PCIE_VSS_32
P26
PCIE_VSS_33
P29
PCIE_VSS_34
R29
PCIE_VSS_35
T29
PCIE_VSS_36
U29
PCIE_VSS_37
W29
PCIE_VSS_38
Y29
PCIE_VSS_39
AA29
PCIE_VSS_40
AB29
PCIE_VSS_41
AD29
PCIE_VSS_42
AE29
PCIE_VSS_43
AF29
PCIE_VSS_44
AG29
PCIE_VSS_45
AJ29
PCIE_VSS_46
AK26
PCIE_VSS_47
AK30
PCIE_VSS_48
AG26
PCIE_VSS_49
N30
PCIE_VSS_50
R31
PCIE_VSS_51
AF30
PCIE_VSS_52
AC30
PCIE_VSS_53
V31
PCIE_VSS_54
P30
PCIE_VSS_55
AA31
PCIE_VSS_56
U30
PCIE_VSS_57
AD31
PCIE_VSS_58
AK32
PCIE_VSS_59
AJ28
PCIE_VSS_60
Y30
PCIE_VSS_61
AJ30
PCIE_VSS_62
AK31
PCIE_VSS_63
AA23
PCIE_VSS_64
AG31
PCIE_VSS_65
N24
PCIE_VSS_66
W23
PCIE_VSS_67
AB23
PCIE_VSS_69
P24
PCIE_VSS_70
R24
PCIE_VSS_71
T24
PCIE_VSS_72
U24
PCIE_VSS_73
V24
PCIE_VSS_74
W24
PCIE_VSS_75
Y24
PCIE_VSS_76
AC24
PCIE_VSS_77
AH24
PCIE_VSS_78
V25
PCIE_VSS_79
AA25
PCIE_VSS_80
R26
PCIE_VSS_81
AA26
PCIE_VSS_82
T27
PCIE_VSS_83
AE27
PCIE_VSS_84
B1
VSS_1
H1
VSS_2
L1
VSS_3
P1
VSS_4
U1
VSS_5
Y1
VSS_6
AD7
VSS_7
AE8
VSS_8
AL1
VSS_9
A2
VSS_10
AM2
VSS_11
AD10
VSS_12
E8
VSS_13
H5
VSS_14
K10
VSS_15
M8
VSS_16
T10
VSS_17
E12
VSS_18
AC9
VSS_19
AF14
VSS_20
AD8
VSS_21
C5
VSS_22
F10
VSS_23
J3
VSS_24
L6
VSS_25
M6
VSS_26
P6
VSS_27
AA4
VSS_28
AG11
VSS_29
V3
VSS_30
AG16
VSS_31
R3
VSS_32
C6
VSS_33
C9
VSS_34
F6
VSS_35
H7
VSS_36
J6
VSS_37
RV410
4
Part 6 of 7
PCI-Express GND
CORE GND
3
AD16
VSS_45
AA6
VSS_44
P7
VSS_43
P5
VSS_42
M3
VSS_41
M9
VSS_40
L7
VSS_39
M7
VSS_38
AD17
VSS_47
AH11
VSS_48
A8
VSS_49
U7
VSS_50
C10
VSS_51
E9
VSS_52
F3
VSS_53
J9
VSS_54
N7
VSS_55
N3
VSS_56
Y5
VSS_57
AM13
VSS_58
AC10
VSS_59
Y6
VSS_60
U6
VSS_61
E5
VSS_62
AL13
VSS_63
A11
VSS_64
U8
VSS_65
U9
VSS_66
U10
VSS_67
R6
VSS_68
AD6
VSS_69
V6
VSS_70
AD14
VSS_71
AD13
VSS_72
D11
VSS_73
J12
VSS_74
K12
VSS_75
A13
VSS_77
F13
VSS_78
E13
VSS_79
F15
VSS_80
K16
VSS_81
J21
VSS_82
H16
VSS_83
T15
VSS_84
V17
VSS_85
C15
VSS_86
C4
VSS_87
U14
VSS_88
P15
VSS_89
A16
VSS_90
E16
VSS_91
G13
VSS_92
G16
VSS_93
P17
VSS_94
R16
VSS_95
R14
VSS_97
W16
VSS_98
C18
VSS_99
F16
VSS_100
W18
VSS_101
U18
VSS_102
AE16
VSS_103
AE17
VSS_104
A19
VSS_105
H32
VSS_106
F19
VSS_107
G19
VSS_108
N8
VSS_109
Y7
VSS_110
T19
VSS_112
V19
VSS_113
G21
VSS_114
C21
VSS_115
F21
VSS_116
AE14
VSS_117
AK16
VSS_118
U5
VSS_119
F22
VSS_120
F18
VSS_121
K30
VSS_122
C24
VSS_124
F24
VSS_125
M24
VSS_126
A25
VSS_127
D30
VSS_128
E25
VSS_129
G25
VSS_130
G20
VSS_131
G22
VSS_132
F27
VSS_133
E28
VSS_134
H21
VSS_135
C27
VSS_136
E32
VSS_137
H28
VSS_138
J30
VSS_139
K17
VSS_140
K27
VSS_141
M32
VSS_142
A22
VSS_143
C20
VSS_144
E19
VSS_145
H20
VSS_146
J24
VSS_147
M28
VSS_148
J28
VSS_149
J16
VSS_150
F30
VSS_151
K23
VSS_152
L29
VSS_153
A31
VSS_154
B32
VSS_155
E30
VSS_156
AE15
VSS_157
AG23
VSS_158
AD9
VSS_159
AF16
VSS_160
AH10
VSS_161
AJ10
VSS_163
AD15
VSS_164
AH16
VSS_165
3
2
Size Document Number Rev
C
Monday, June 13, 2005
2
Date: Sheet
1
MS-V016 ATI RV410
1
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CORE REGULATOR VDDC
D D
Rc1
R1592
1.87K
1%
Rc2
R1597
1.33K
1%
+3.3V_BUS
C1705
470UF
R1581
5.1K
R1582
2.4K
+12V_BUS
1
Q7
CMPT3904
B1
Chock 1.2u
C1152
820uF_6.3V
+12V_BUS
2 3
R1583
20K
1
Q8
CMPT3904
+VDDC
2 3
C1153
820uF_6.3V
SS_VDDC3
+PCIE_VDDR
B60
60R
C1155
C805
220uF_6.3V
820uF_6.3V
Dual footprint
DESIGN NOTES:
Compensation Circuit
COMP_VDDC3
C1163
Cc3
Rc5
C1161
10nF
33pF
R1580
15K
Fb_VDDC3
Cc2
FOR ALTERNATE #2
Change C157 for 10 uF and C121 for 1 uF
Replace C764 by 0 Ohm resistor
Replace R314 with a bead
Remove R954, R370, R305-R308, C159,
R112, C160 and MU32
+12V_BUS
+PW_VDDC3
1
D28
BAT54SLT1
3
2
C C
C1692
1uF
+PW_VDDC3
SS_VDDC3
COMP_VDDC3
C1157
22nf
B B
BOOT_VDDC3
R1598 51K
R1602 3K
R1686 10K
MU43
2
OCSET
3
SS
LGATE
4
COMP
5
FB
6
EN
UGATE
7
PHASE
GND
ISL6522CB
ISL6522CB : SOIC
ISL6522CV : TSSOP
PVCC
PGND
BOOT
VCCRT
C1688 100nF
R1619
2R2
R1591
2R2
+12V_BUS
141
13
12
11
10
9
8
C1690
1uF
BOOT_VDDC3Fb_VDDC3
R1618
2.2R
DS
Q28
G
N-APM3023N TO-252
DS
Q29
G
N-APM3023N TO-252
C1159
1nF
Lower MOSFET should be surrounded by
a lot of copper for heat dissipation
G
G
DS
Q30
N-APM3023N
DS
Q31
N-APM3023N
C1532
1.0uF
C1149
10uF
L63
Dip 1.6u
C1146
10uF
Fb_VDDC3
C1148
C1147
10uF
10uF
C1158
1nf
DNI
Cc1
R1617
1.5K
DNI
Rc4
POWER SEQUENCING CIRCUIT:
FOR ALTERNATE #1
Remove R374, R375, R371, C168 and U32
Install R370, R112, R954, R305-R308, C160
C159 and MU32
Install R374, R375, R371, C168 and U32
Compensation circuit
A A
Rc1 = 10K, Rc2 = 8.06K
R313 = 93.1K, C171 = 3.9 nF, C170 = 10 pF
Size Document Number Rev
C
8
7
6
5
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3
Date: Sheet
2
MS-V016 ATI RV410
Monday, June 13, 2005
of
724
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+12V_BUS
1
D4
BAT54SLT1
3
D D
C C
B B
C141
22nf
+12V_BUS
2
C142
1uF
+PW_VDDC1
SS_VDDC1
COMP_VDDC1
Fb_VDDC1
1
D5
BAT54SLT1
3
2
C157
1uF
+PW_VDDC2
SS_VDDC2
COMP_VDDC2
C169
22nf
MVDDQ Switching Regulator for
Memory Core for 256M
configuration
BOOT_VDDC1
R257 10K
R258 51K
R259 3K
MU31
2
3
4
5
6
7
ISL6522CB
OCSET
SS
COMP
FB
EN
GND
PVCC
LGATE
PGND
BOOT
UGATE
PHASE
141
VCCRT
13
12
11
10
9
8
ISL6522CB : SOIC
MVDDC Switching Regulator for
Memory Core for 256M
configuration
BOOT_VDDC2
R307 10K
R305 51K
R306 3K
MU32
2
OCSET
3
SS
LGATE
4
COMP
5
FB
6
EN
UGATE
7
GND
PHASE
ISL6522CB
ISL6522CB : SOIC
ISL6522CV : TSSOP
PVCC
PGND
BOOT
VCCRT
141
13
12
11
10
9
8
C122 100nF
+12V_BUS
BOOT_VDDC1
BOOT_VDDC2Fb_VDDC2
R251
2R2
R373
2R2
C113
1uF
C121 100nF
R314
2R2
R371
2R2
+12V_BUS
C159
1uF
TO-252
換
R255
2.2R
TO-252
換
R308
2.2R
DS
G
DS
G
Fb_VDDC1
G
G
Fb_VDDC2
Q34
N-APM3023N TO-252
Q35
N-APM3023N TO-252
C116
1nF
DS
Q36
N-APM3023N TO-252
DS
Q37
N-APM3023N TO-252
C160
1nF
+PW_VDDC1
L65
Dip 2.2uH
+MVDDQ= 2.1V
+PW_VDDC2
L66
Dip 2.2uH
Lower MOSFET should be surrounded by
a lot of copper for heat dissipation
+12V_BUS
B21
Chock 1.2u
C137
C138
10uF
10uF
+MVDDQ
C110
1nf
DNI
R254
1.5K
DNI
Rc1
Cc1 Rc5
R253
1.8K
1%
Rc4
Rc2
R256
1.1K
1%
C106
22uF
Cout1
C105
22uF
DNIDNI
C104
22uF
Dual footprintDual footprintDual footprint
POWER SEQUENCING CIRCUIT:
R250
2K
R249
2.4K
1
Q9
CMPT3904
+12V_BUS
R248
20K
CMPT3904
2 3
1
C107
470uF_10V
+MVDDC
FOR ALTERNATE #1
Install R372, D4, R376, C113, R257,
R258, R259, MU31, R255 and C116
Remove R373, R377, R378, C122,
C140 and U31
SS_VDDC1
2 3
Q10
Cc2
FOR ALTERNATE #2
Change C142 for 10uF
Install R377, R378, R373, C122, C140
and U31
Remove R255, C116, R372, R376, D4,
MU31, R257, R258, R259 and C113
Compensation circuit
Rc1 = 10K, Rc2 = 8.06K
R264 = 41.2K, C111 = 27 pF
+12V_BUS
B28
Chock 1.2u
C172
C163
10uF
10uF
+MVDDC
C161
1nf
DNI
R309
1.5K
DNI
Cc1
Rc4
Rc1
R310
2.37K
1%
Rc2
R311
1.1K
1%
+MVDDC= 2.5V
C164
22uF
Cout1
C165
22uF
DNIDNI DNI
C166
22uF
Dual footprintDual footprintDual footprint
***
C1706
470uF_10V
***
Dual footprint
FOR ALTERNATE #1
Remove R374, R375, R371, C168 and U32
Install R370, R112, R954, R305-R308, C160
C159 and MU32
Cc2
FOR ALTERNATE #2
Change C157 for 10 uF and C121 for 1 uF
Replace C764 by 0 Ohm resistor
Replace R314 with a bead
Remove R954, R370, R305-R308, C159,
R112, C160 and MU32
Install R374, R375, R371, C168 and U32
Compensation circuit
Rc1 = 10K, Rc2 = 8.06K
R313 = 93.1K, C171 = 3.9 nF, C170 = 10 pF
DESIGN NOTES:
Compensation Circuit
COMP_VDDC1
C111
33pF
C112
10nF
R264
15K
DESIGN NOTES:
Compensation Circuit
COMP_VDDC2
C170
33pF
C171
10nF
R313
15K
Rc5
Cc3
Fb_VDDC1
Cc3
Fb_VDDC2
A A
Size Document Number Rev
C
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3
Date: Sheet
2
MS-V016 ATI RV410
Monday, June 13, 2005
of
824
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Page 9
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REGULATOR FOR +VDD_1.8V/ PVDD / TPVDD / MPVDD (+1.8V)
+1.8V Regulator +1.5V Regulator for VDDC _ C T ( V D D15)
C134
22uF_16V
C139
22uF_16V
+3.3V_BUS
B10
60R
C135
100nF
B11
60R
C143
100nF
REG2
LT1117CST
3 2
IN OUT
ADJ
1
REG10
LT1117CST
3 2
IN OUT
ADJ
1
D D
REG2 SPEC :
ANPEC/APL1117VC-TR,SOT223,REGULATOR(ADJ)/1A, V in=15Vm ax
C C
CASE
CASE
+VDD_1.8V
4
+PCIE_PVDD_18
4
R129
1.50K
1%
R126
681R
1%
R130
1.50K
1%
R131
681R
1%
PVDD Max: 55 mA
TPVDD Max: 20 mA
MPVDD Max: 20 mA
+TPVDD +MPVDD+PVDD
C132
C131
100uF_16V
100nF
+VDD_1.8V+3.3V_BUS
B2
60R
+PCIE_PVDD_18
C957
10uf
C980
22uF
Max: 55 mA
+3.3V_BUS
B22 200R
3 2
C984
22uF
AS432S
MREG7
Current limit circuit MAX 125 mA
R128
+VDDC_CT
27R
R125
681R
1%
1
R127
1.50K
1%
REG7
4
SC431LC5SK-1
NC
1
NC
2
5 3
C127
100nF
C126
10uf
+5V
23
Q16
NI
R407
0R
+5VCON1(16,19,21)
1
MMBT3906
+5VCON1
R405
4.7K
1
Q18
CMPT3904
Q17
2N7002E
1
2 3
32
+5V
+12V_BUS
C400
1uF
R406
1.0M
23
R1447
220R
R404
5.6R
Q19
MMBT3906
1
REG29
TL431CDBVR
R1448
220R
+12V_BUS
5 3
R1449
220R
R1042
14R
NC
NC
+VTT Linear Regulator
Vin = +MVDDQ
Vout = 1.25V
Iout = 2000mA MAX
Iout = 750mA Est. MAX
R273
1.4V
1K
R275
1K
+MVDDQ
***
C133
470uF_6.3V
***
R1450
220R
R1043
14R
4
1
2
REG20
1 5
IN VOUT
R1836
1.00K
4 2
REFEN GND
RT9173ACL5
R1838
C2190
1.00K
10uF
R1
R2
Regulator for +5V
Vout = 5V
Iout = 125mA MAX
+5V
R1040
75.0R
1%
402
C917
2.2uF
R1041
75.0R
1%
402
+3.3V_BUS
C130
47uF_6.3V
3
6
TAB
VCNTL
R1837
1K
C129
220uF_6.3V
+VTT
***
C2189
22uF_16V
***
Regulator for PCIE_VDDR & +A2VDD
+3.3V_BUS
B B
A A
5
+3.3V_BUS
R820
110R
U900APL431BAC_SOT23
2
3 1
+12V_BUS
411
U801A
3
+
1
2
-
LM324M
4
5
6
R821
1K
C180
0603_0.1uF
+
-
U801B
LM324M
R819 10R
7
R101
0R
B
3
C181
100uF/6.3V
CE
Q802
N-MMBT2222A_SOT23
C182
DIP_220uF_6.3V
+A2VDD
Size Document Number Rev
C
2
Date: Sheet
MS-V016 ATI RV410
Monday, June 13, 2005
1
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Page 10
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RV410 MEMORY CHANNELS A and B
D D
M_MDA[63..0]
M_MDA[63..0](11,12) M_MDB[63..0](11,13)
C C
+MVDDQ
R137
150R
B B
R138
C149
100nF
150R
4170010400
+MVDDQ
R148
150R
R149
C148
100nF
150R
4170010400
M_MDA0
M_MDA1
M_MDA2
M_MDA3
M_MDA4
M_MDA5
M_MDA6
M_MDA7
M_MDA8
M_MDA9
M_MDA10
M_MDA11
M_MDA12
M_MDA13
M_MDA14
M_MDA15
M_MDA16
M_MDA17
M_MDA18
M_MDA19
M_MDA20
M_MDA21
M_MDA22
M_MDA23
M_MDA24
M_MDA25
M_MDA26
M_MDA27
M_MDA28
M_MDA29
M_MDA30
M_MDA31
M_MDA32
M_MDA33
M_MDA34
M_MDA35
M_MDA36
M_MDA37
M_MDA38
M_MDA39
M_MDA40
M_MDA41
M_MDA42
M_MDA43
M_MDA44
M_MDA45
M_MDA46
M_MDA47
M_MDA48
M_MDA49
M_MDA50
M_MDA51
M_MDA52
M_MDA53
M_MDA54
M_MDA55
M_MDA56
M_MDA57
M_MDA58
M_MDA59
M_MDA60
M_MDA61
M_MDA62
M_MDA63
U1C
M31
DQA_0
M30
DQA_1
L31
DQA_2
L30
DQA_3
H30
DQA_4
G31
DQA_5
G30
DQA_6
F31
DQA_7
M27
DQA_8
M29
DQA_9
L28
DQA_10
L27
DQA_11
J27
DQA_12
H29
DQA_13
G29
DQA_14
G27
DQA_15
M26
DQA_16
L26
DQA_17
M25
DQA_18
L25
DQA_19
J25
DQA_20
G28
DQA_21
H27
DQA_22
H26
DQA_23
F26
DQA_24
G26
DQA_25
H25
DQA_26
H24
DQA_27
H23
DQA_28
H22
DQA_29
J23
DQA_30
J22
DQA_31
E23
DQA_32
D22
DQA_33
D23
DQA_34
E22
DQA_35
E20
DQA_36
F20
DQA_37
D19
DQA_38
D18
DQA_39
B19
DQA_40
B18
DQA_41
C17
DQA_42
B17
DQA_43
C14
DQA_44
B14
DQA_45
C13
DQA_46
B13
DQA_47
D17
DQA_48
E18
DQA_49
E17
DQA_50
F17
DQA_51
E15
DQA_52
E14
DQA_53
F14
DQA_54
D13
DQA_55
H18
DQA_56
H17
DQA_57
G18
DQA_58
G17
DQA_59
G15
DQA_60
G14
DQA_61
H14
DQA_62
J14
DQA_63
C31
MVREFD_0
C30
MVREFS_0
RV410
Channel A
Part 3 of 7
DDR1 DDR2 DDR3
Not used bidir. strobe
MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13
MAA_14
MAA_15
DQMAb_0
DQMAb_1
DQMAb_2
DQMAb_3
MEMORY INTERFACE
A
DQMAb_4
DQMAb_5
DQMAb_6
DQMAb_7
QSA_0
QSA_1
QSA_2
QSA_3
QSA_4
QSA_5
QSA_6
QSA_7
QSA_0B
QSA_1B
QSA_2B
QSA_3B
QSA_4B
QSA_5B
bidir. differential strobe
QSA_6B
QSA_7B
write strobe read strobe
For DDR2
ODTA
ODTA1
CLKA0
CLKA0b
CKEA0
RASA0b
CASA0b
WEA0b
CSA0b_0
CSA0b_1
CLKA1
CLKA1b
CKEA1
RASA1b
CASA1b
WEA1b
CSA1b_0
CSA1b_1
U1D
M_MAA0
D26
M_MAA1
F28
M_MAA2
D28
M_MAA3
D25
M_MAA4
E24
M_MAA5
E26
M_MAA6
D27
M_MAA7
F25
M_MAA8
C26
M_MAA9
B26
M_MAA10
D29
M_MAA11
B27
M_MAA12
B25
M_MAA13
C25
M_CSA#1
E27
E29
M_DQMA#0
H31
M_DQMA#1
J29
M_DQMA#2
J26
M_DQMA#3
G23
M_DQMA#4
E21
M_DQMA#5
B15
M_DQMA#6
D14
M_DQMA#7
J17
M_QSA0
J31
M_QSA1
K29
M_QSA2
K25
M_QSA3
F23
M_QSA4
D20
M_QSA5
B16
M_QSA6
D16
M_QSA7
H15
K31
K28
K26
G24
D21
C16
D15
J15
F29
D24
D31
E31
B30
M_RASA#
B28
M_CASA#
C29
M_WEA#
B31
M_CSA#0
B29
C28
B20
C19
C22
B24
B22
B21
B23
C23
M_MAA[13..0] (11,14)
M_CSA#1 (11,14)
M_DQMA#[7..0] (11,14)
M_QSA[7..0] (11,14)
CLKA0 (11,14)
CLKA#0 (11,14)
M_CKEA (11,14)
M_RASA# (11,14)
M_CASA# (11,14)
M_WEA# (11,14)
M_CSA#0 (11,14)
CLKA1 (11,14)
CLKA#1 (11,14)
+MVDDQ
+MVDDQ
R158
150R
R159
150R
R150
150R
R151
150R
C151
100nF
4170010400
C150
100nF
4170010400
M_MDB0
B12
R166243R
C12
B11
C11
C8
C7
F12
D12
E11
F11
D8
D7
G12
G11
H12
H11
H9
G8
G6
G7
H8
N5
N6
R4
R2
W3
W2
R5
W5
W6
R8
R7
W7
W8
W9
C3
AA3
AA5
AA2
AA7
B7
B6
F9
F7
E7
F8
J8
K8
L8
K9
L9
K5
L4
K4
L5
P4
P2
T3
T2
Y3
Y2
T4
T5
T6
V5
Y4
T8
T7
V7
B3
DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31
DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63
MVREFD_1
MVREFS_1
DRAM_RST
TEST_MCLK
TEST_YCLK
MEMTEST
RV410
M_MDB1
M_MDB2
M_MDB3
M_MDB4
M_MDB5
M_MDB6
M_MDB7
M_MDB8
M_MDB9
M_MDB10
M_MDB11
M_MDB12
M_MDB13
M_MDB14
M_MDB15
M_MDB16
M_MDB17
M_MDB18
M_MDB19
M_MDB20
M_MDB21
M_MDB22
M_MDB23
M_MDB24
M_MDB25
M_MDB26
M_MDB27
M_MDB28
M_MDB29
M_MDB30
M_MDB31
M_MDB32
M_MDB33
M_MDB34
M_MDB35
M_MDB36
M_MDB37
M_MDB38
M_MDB39
M_MDB40
M_MDB41
M_MDB42
M_MDB43
M_MDB44
M_MDB45
M_MDB46
M_MDB47
M_MDB48
M_MDB49
M_MDB50
M_MDB51
M_MDB52
M_MDB53
M_MDB54
M_MDB55
M_MDB56
M_MDB57
M_MDB58
M_MDB59
M_MDB60
M_MDB61
M_MDB62
M_MDB63
TEST_MCLK
TEST_YCLK
R1634.7K
R1564.7K
R1574.7K
NI
Channel B
Part 4 of 7
DDR1 DDR2 DDR3
Not used bidir. strobe
MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8
MAB_9
MAB_10
MAB_11
MAB_12
MAB_13
MAB_14
MAB_15
DQMBb_0
DQMBb_1
DQMBb_2
DQMBb_3
DQMBb_4
MEMORY INTERFACE
B
DQMBb_5
DQMBb_6
DQMBb_7
QSB_0
QSB_1
QSB_2
QSB_3
QSB_4
QSB_5
QSB_6
QSB_7
read strobe
QSB_0B
QSB_1B
QSB_2B
QSB_3B
QSB_4B
QSB_5B
QSB_6B
bidir. differential strobe
QSB_7B
write strobe
For DDR2
ODTB
ODTB1
CLKB0
CLKB0b
CKEB0
RASB0b
CASB0b
WEB0b
CSB0b_0
CSB0b_1
CLKB1
CLKB1b
CKEB1
RASB1b
CASB1b
WEB1b
CSB1b_0
CSB1b_1
M_MAB0
G4
M_MAB1
E6
M_MAB2
E4
M_MAB3
H4
M_MAB4
J5
M_MAB5
G5
M_MAB6
F4
M_MAB7
H6
M_MAB8
G3
M_MAB9
G2
M_MAB10
D4
M_MAB11
F2
M_MAB12
H2
M_MAB13
H3
M_CSB#1
F5
D5
M_DQMB#0
B8
M_DQMB#1
D9
M_DQMB#2
G9
M_DQMB#3
K7
M_DQMB#4
M5
M_DQMB#5
V2
M_DQMB#6
W4
M_DQMB#7
T9
M_QSB0
B9
M_QSB1
D10
M_QSB2
H10
M_QSB3
K6
M_QSB4
N4
M_QSB5
U2
M_QSB6
U4
M_QSB7
V8
B10
E10
G10
J7
M4
U3
V4
V9
D6
J4
B4
B5
C2
M_RASB#
E2
M_CASB#
D3
M_WEB#
B2
M_CSB#0
D2
E3
N2
P3
L3
J2
L2
M2
K2
K3
M_MAB[13..0] (11,14)
M_CSB#1 (11,14)
M_DQMB#[7..0] (11,14)
M_QSB[7..0] (11,14)
CLKB0 (11,14)
CLKB#0 (11,14)
M_CKEB (11,14)
M_RASB# (11,14)
M_CASB# (11,14)
M_WEB# (11,14)
M_CSB#0 (11,14)
CLKB1 (11,14)
CLKB#1 (11,14)
A A
Size Document Number Rev
C
5
4
3
2
Date: Sheet
MS-V016 ATI RV410
Monday, June 13, 2005
1
10 24
0A
of
www.vinafix.vn
Page 11
8
RP601D 56R
RP601C 56R
RP601B 56R
RP601A 56R
C2163
RP2D 56R
RP2C 56R
RP2B 56R
RP2A 56R
RP3A 56R
RP3B 56R
RP3C 56R
RP3D 56R
C2165
RP4A 56R
RP4B 56R
RP4C 56R
RP4D 56R
RP5D 56R
RP5C 56R
RP5B 56R
RP5A 56R
RP6D 56R
C2167
RP6C 56R
RP6B 56R
RP6A 56R
RP7D 56R
RP7C 56R
RP7B 56R
RP7A 56R
RP8D 56R
RP8C 56R
RP8B 56R
RP8A 56R
RP9A 56R
RP9B 56R
RP9C 56R
RP9D 56R
C2171
RP10A 56R
RP10B 56R
RP10C 56R
RP10D 56R
RP11A 56R
RP11B 56R
RP11C 56R
C2172
RP11D 56R
RP12A 56R
RP12B 56R
RP12C 56R
RP12D 56R
RP13A 56R
RP13B 56R
RP13C 56R
RP13D 56R
RP14A 56R
RP14B 56R
RP14C 56R
RP14D 56R
RP15D 56R
RP15C 56R
RP15B 56R
RP15A 56R
RP16D 56R
RP16C 56R
RP16B 56R
RP16A 56R
RP23A 56R
RP20B 56R
RP20A 56R
RP20D 56R
C2178
RP20C 56R
RP17A 56R
RP23B 56R
RP18D 56R
RP18A 56R
RP23C 56R
RP23D 56R
C2180
RP19A 56R
RP17C 56R
RP17D 56R
R189 56R
R190 56R
R192 56R
R194 56R
R196 56R
R198 56R
R200 56R
R202 56R
C2183
RP17B 56R
RP18B 56R
RP18C 56R
C2185
RP19B 56R
RP19D 56R
RP19C 56R
R718 56R
R719 56R
R720 56R
R721 56R
R722 56R
R723 56R
R724 56R
R725 56R
+VTT
8
5 4
6 3
7 2
8 1
5 4
6 3
7 2
8 1
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
5 4
6 3
7 2
8 1
5 4
6 3
7 2
8 1
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
8 1
5 4
6 3
8 1
7 2
5 4
8 1
6 3
5 4
8 1
6 3
5 4
7 2
7 2
6 3
7 2
5 4
6 3
+MVDDQ
100nF
D D
100nF
+MVDDQ
100nF
C2168
100nF
+MVDDQ
100nF
C C
100nF
+MVDDQ
C2174
100nF
C2176
100nF
+MVDDQ
100nF
B B
100nF
+MVDDQ
100nF
100nF
A A
+MVDDQ
C2187
100nF
C179
22uF
M_MDA3
M_MDA2
M_MDA1
M_MDA0
M_MDA7
M_MDA6
M_MDA5
M_MDA4
M_MDA11
M_MDA10
M_MDA9
M_MDA8
M_MDA15
M_MDA14
M_MDA13
M_MDA12
M_MDA17
M_MDA16
M_MDA19
M_MDA18
M_MDA21
M_MDA20
M_MDA23
M_MDA22
M_MDA27
54
M_MDA26
63
M_MDA25
72
M_MDA24
81
M_MDA31
54
M_MDA30
63
M_MDA29
72
M_MDA28
81
M_MDA32
81
M_MDA33
72
M_MDA34
63
M_MDA35
54
M_MDA36
81
M_MDA37
72
M_MDA38
63
M_MDA39
54
M_MDA40
M_MDA41
M_MDA42
M_MDA43
M_MDA44
M_MDA45
M_MDA46
M_MDA47
M_MDA48
81
M_MDA49
72
M_MDA50
63
M_MDA51
54
M_MDA52
81
M_MDA53
72
M_MDA54
63
M_MDA55
54
M_MDA56
54
M_MDA57
63
M_MDA58
72
M_MDA59
81
M_MDA60
54
M_MDA61
63
M_MDA62
72
M_MDA63
81
M_MAA10
M_MAA7
M_MAA4
M_MAA3
M_MAA5
M_MAA0
M_MAA1
M_MAA13
M_MAA9
M_CKEA
M_WEA#
M_CASA#
M_CSA#1
M_MAA2
M_DQMA#0
M_DQMA#1
M_DQMA#2
M_DQMA#3
M_DQMA#4
M_DQMA#5
M_DQMA#6
M_DQMA#7
M_MAA6
M_MAA8
M_MAA12
M_CSA#0
M_MAA11
M_RASA#
M_QSA0
M_QSA1
M_QSA2
M_QSA3
M_QSA4
M_QSA5
M_QSA6
M_QSA7
7
+MVDDQ +MVDDQ
C2195
10nF
+MVDDQ +MVDDQ
C2197
10nF
M_CKEA (10,14)
M_WEA# (10,14) M_WEB# (10,14)
M_CASA# (10,14)
M_CSA#1 (10,14)
M_DQMA#[7..0] (10,14)
M_MAA6 (10,14)
M_MAA8 (10,14)
M_MAA12 (10,14)
M_CSA#0 (10,14)
M_MAA11 (10,14)
M_RASA# (10,14)
M_QSA[7..0] (10,14)
7
6
M_MDA[63..0]
M_MAA[13..0]
Vtt
TERMINATION
for DDR
C2196
10nF
C2198
10nF
6
M_MDA[63..0] (10,12)
M_MAA[13..0] (10,14)
+MVDDQ
100nF
C2166
100nF
+MVDDQ
100nF
C2169
100nF
+MVDDQ
100nF
C2173
100nF
+MVDDQ
100nF
100nF
+MVDDQ
100nF
C2181
100nF
+MVDDQ
100nF
C2184
100nF
+MVDDQ
100nF
5
+VTT
RP46D 56R
RP46C 56R
RP46B 56R
RP46A 56R
RP47D 56R
C2164
RP47C 56R
RP47B 56R
RP47A 56R
RP48D 56R
RP48C 56R
RP48B 56R
RP48A 56R
RP49D 56R
RP49C 56R
RP49B 56R
RP49A 56R
RP50D 56R
RP50C 56R
RP50B 56R
RP50A 56R
C2188
RP51D 56R
RP51C 56R
RP51B 56R
RP51A 56R
RP52A 56R
RP52B 56R
RP52C 56R
RP52D 56R
RP53A 56R
RP53B 56R
RP53C 56R
RP53D 56R
RP54A 56R
RP54B 56R
RP54C 56R
RP54D 56R
C2170
RP55A 56R
RP55B 56R
RP55C 56R
RP55D 56R
RP56D 56R
RP56C 56R
RP56B 56R
RP56A 56R
RP57D 56R
RP57C 56R
RP57B 56R
RP57A 56R
RP58D 56R
RP58C 56R
RP58B 56R
RP58A 56R
RP59D 56R
C2175
RP59C 56R
RP59B 56R
RP59A 56R
RP60D 56R
RP60C 56R
RP60B 56R
RP60A 56R
C2177
RP61D 56R
RP61C 56R
RP61B 56R
RP61A 56R
RP65A 56R
RP66B 56R
RP66A 56R
RP66D 56R
RP66C 56R
C2179
RP64A 56R
RP65B 56R
RP62D 56R
RP62A 56R
RP65C 56R
RP65D 56R
RP63A 56R
RP64C 56R
RP64D 56R
R191 56R
R193 56R
R195 56R
R197 56R
R199 56R
R201 56R
R203 56R
R204 56R
C2182
RP64B 56R
RP62B 56R
RP62C 56R
RP63B 56R
RP63D 56R
RP63C 56R
R726 56R
R727 56R
R728 56R
R729 56R
R730 56R
R731 56R
C2186
R732 56R
R733 56R
5
5 4
6 3
7 2
8 1
5 4
6 3
7 2
8 1
5 4
6 3
7 2
8 1
5 4
6 3
7 2
8 1
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
5 4
6 3
7 2
8 1
5 4
6 3
7 2
8 1
8 1
7 2
8 1
5 4
6 3
8 1
7 2
5 4
8 1
6 3
5 4
8 1
6 3
5 4
7 2
7 2
6 3
7 2
5 4
6 3
C178
22uF
4
M_MDB3
M_MDB2
M_MDB1
M_MDB0
M_MDB7
M_MDB6
M_MDB5
M_MDB4
M_MDB11
54
M_MDB10
63
M_MDB9
72
M_MDB8
81
M_MDB15
54
M_MDB14
63
M_MDB13
72
M_MDB12
81
M_MDB19
M_MDB18
M_MDB17
M_MDB16
M_MDB23
M_MDB22
M_MDB21
M_MDB20
M_MDB27
M_MDB26
M_MDB25
M_MDB24
M_MDB31
M_MDB30
M_MDB29
M_MDB28
M_MDB35
81
M_MDB34
72
M_MDB33
63
M_MDB32
54
M_MDB39
81
M_MDB38
72
M_MDB37
63
M_MDB36
54
M_MDB43
M_MDB42
M_MDB41
M_MDB40
M_MDB47
M_MDB46
M_MDB45
M_MDB44
M_MDB51
54
M_MDB50
63
M_MDB49
72
M_MDB48
81
M_MDB55
54
M_MDB54
63
M_MDB53
72
M_MDB52
81
M_MDB59
54
M_MDB58
63
M_MDB57
72
M_MDB56
81
M_MDB63
54
M_MDB62
63
M_MDB61
72
M_MDB60
81
M_MAB6
M_MAB2
M_CSB#1
M_CSB#1 (10,14)
M_CSB#0
M_CSB#0 (10,14)
M_MAB1
M_CKEB
M_CKEB (10,14)
M_MAB10
M_MAB3
M_RASB#
M_RASB# (10,14)
M_MAB0
M_WEB#
M_MAB4
M_MAB12
M_MAB13
M_DQMB#0
M_DQMB#1
M_DQMB#2
M_DQMB#3
M_DQMB#4
M_DQMB#5
M_DQMB#6
M_DQMB#7
M_MAB9
M_MAB7
M_MAB5
M_MAB8
M_CASB#
M_MAB11
M_QSB0
M_QSB1
M_QSB2
M_QSB3
M_QSB4
M_QSB5
M_QSB6
M_QSB7
M_DQMB#[7..0] (10,14)
M_MAB9 (10,14)
M_MAB7 (10,14)
M_MAB5 (10,14)
M_MAB8 (10,14)
M_CASB# (10,14)
M_MAB11 (10,14)
M_QSB[7..0] (10,14)
4
3
CLKA#1(10,14)
M_CLKA0(10,14)
M_CLKA#0(10,14)
CLKB#1(10,14)
M_CLKB0(10,14)
M_CLKB#0(10,14)
3
M_MDB[63..0]
M_MAB[13..0]
Differential CLOCK termination A
M_CLKA1
CLKA1(10,14) M_CLKA1 (10,14)
Differential CLOCK termination B
CLKB1(10,14)
M_CLKB#1
M_CLKB0
M_CLKB#0
M_CLKA#1
M_CLKA0
M_CLKA#0
M_CLKB1
R826
56R
C711 10nF
R169
56R
CLKA0 (10,14)
R827
56R
C712 10nF
R170
56R
CLKA#0 (10,14)
M_CLKB1 (10,14)
R828
56R
C713 10nF
R172
56R
M_CLKB#1 (10,14)
CLKB0 (10,14)
R829
56R
C714 10nF
R171
56R
CLKB#0 (10,14)
Size Document Number Rev
B
Date: Sheet
2
M_MDB[63..0] (10,13)
M_MAB[13..0] (10,14)
M_CLKA#1 (10,14)
MS-V016 ATI RV410
Monday, June 13, 2005
2
1
of
11 24
1
0A
www.vinafix.vn
Page 12
5
4
3
2
1
MDA[63..0]
TERMINATION FOR
MEMORY
CHANNEL A
D D
C C
Proper Termination of QSA?
MDA[63..0](14) M_MDA[63..0] (10,11)
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
RP117D 56R
54
RP117C 56R
63
RP117B 56R
72
RP117A 56R
81
RP118D 56R
54
RP118C 56R
63
RP118B 56R
72
RP118A 56R
81
RP119D 56R
5 4
RP119C 56R
6 3
RP119B 56R
7 2
RP119A 56R
8 1
RP120A 56R
81
RP120B 56R
72
RP120C 56R
63
RP120D 56R
54
RP121D 56R
54
RP121C 56R
63
RP121B 56R
72
RP121A 56R
81
RP122D 56R
54
RP122C 56R
63
RP122B 56R
72
RP122A 56R
81
RP123A 56R
81
RP123B 56R
72
RP123C 56R
63
RP123D 56R
54
RP124D 56R
5 4
RP124C 56R
6 3
RP124B 56R
7 2
RP124A 56R
8 1
RP127A 56R
8 1
RP127B 56R
7 2
RP127C 56R
6 3
RP127D 56R
5 4
RP128A 56R
8 1
RP128B 56R
7 2
RP128C 56R
6 3
RP128D 56R
5 4
RP125D 56R
5 4
RP125C 56R
6 3
RP125B 56R
7 2
RP125A 56R
8 1
RP126D 56R
5 4
RP126C 56R
6 3
RP126B 56R
7 2
RP126A 56R
8 1
RP129A 56R
8 1
RP129B 56R
7 2
RP129C 56R
6 3
RP129D 56R
5 4
RP130A 56R
8 1
RP130B 56R
7 2
RP130C 56R
6 3
RP130D 56R
5 4
RP131A 56R
81
RP131B 56R
72
RP131C 56R
63
RP131D 56R
54
RP132D 56R
5 4
RP132C 56R
6 3
RP132B 56R
7 2
RP132A 56R
8 1
M_MDA3
M_MDA2
M_MDA1
M_MDA0
M_MDA7
M_MDA6
M_MDA5
M_MDA4
M_MDA11
M_MDA10
M_MDA9
M_MDA8
M_MDA15
M_MDA14
M_MDA13
M_MDA12
M_MDA17
M_MDA16
M_MDA19
M_MDA18
M_MDA21
M_MDA20
M_MDA23
M_MDA22
M_MDA27
M_MDA26
M_MDA25
M_MDA24
M_MDA31
M_MDA30
M_MDA29
M_MDA28
M_MDA32
M_MDA33
M_MDA34
M_MDA35
M_MDA36
M_MDA37
M_MDA38
M_MDA39
M_MDA40
M_MDA41
M_MDA42
M_MDA43
M_MDA44
M_MDA45
M_MDA46
M_MDA47
M_MDA48
M_MDA49
M_MDA50
M_MDA51
M_MDA52
M_MDA53
M_MDA54
M_MDA55
M_MDA56
M_MDA57
M_MDA58
M_MDA59
M_MDA60
M_MDA61
M_MDA62
M_MDA63
M_MDA[63..0]
SERIES Resistors
For Bi-Directional signals,
Series resistors should be
placed close to the
memory
B B
A A
Size Document Number Rev
C
5
4
3
2
Date: Sheet
MS-V016 ATI RV410
Monday, June 13, 2005
1
12 24
0A
of
www.vinafix.vn
Page 13
5
D D
TERMINATION FOR
MEMORY
CHANNEL B
C C
4
MDB[63..0]
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63
3
RP167A 56R
8 1
RP167B 56R
7 2
RP167C 56R
6 3
RP167D 56R
5 4
RP168A 56R
8 1
RP168B 56R
7 2
RP168C 56R
6 3
RP168D 56R
5 4
RP169D 56R
5 4
RP169C 56R
6 3
RP169B 56R
7 2
RP169A 56R
8 1
RP170A 56R
81
RP170B 56R
72
RP170C 56R
63
RP170D 56R
54
RP171A 56R
8 1
RP171B 56R
7 2
RP171C 56R
6 3
RP171D 56R
5 4
RP172A 56R
8 1
RP172B 56R
7 2
RP172C 56R
6 3
RP172D 56R
5 4
RP173A 56R
81
RP173B 56R
72
RP173C 56R
63
RP173D 56R
54
RP174D 56R
5 4
RP174C 56R
6 3
RP174B 56R
7 2
RP174A 56R
8 1
RP175D 56R
54
RP175C 56R
63
RP175B 56R
72
RP175A 56R
81
RP176D 56R
54
RP176C 56R
63
RP176B 56R
72
RP176A 56R
81
RP177A 56R
8 1
RP177B 56R
7 2
RP177C 56R
6 3
RP177D 56R
5 4
RP178D 56R
54
RP178C 56R
63
RP178B 56R
72
RP178A 56R
81
RP179D 56R
5 4
RP179C 56R
6 3
RP179B 56R
7 2
RP179A 56R
8 1
RP180D 56R
5 4
RP180C 56R
6 3
RP180B 56R
7 2
RP180A 56R
8 1
RP181D 56R
5 4
RP181C 56R
6 3
RP181B 56R
7 2
RP181A 56R
8 1
RP182A 56R
81
RP182B 56R
72
RP182C 56R
63
RP182D 56R
54
M_MDB3
M_MDB2
M_MDB1
M_MDB0
M_MDB7
M_MDB6
M_MDB5
M_MDB4
M_MDB11
M_MDB10
M_MDB9
M_MDB8
M_MDB15
M_MDB14
M_MDB13
M_MDB12
M_MDB19
M_MDB18
M_MDB17
M_MDB16
M_MDB23
M_MDB22
M_MDB21
M_MDB20
M_MDB27
M_MDB26
M_MDB25
M_MDB24
M_MDB31
M_MDB30
M_MDB29
M_MDB28
M_MDB35
M_MDB34
M_MDB33
M_MDB32
M_MDB39
M_MDB38
M_MDB37
M_MDB36
M_MDB43
M_MDB42
M_MDB41
M_MDB40
M_MDB47
M_MDB46
M_MDB45
M_MDB44
M_MDB51
M_MDB50
M_MDB49
M_MDB48
M_MDB55
M_MDB54
M_MDB53
M_MDB52
M_MDB59
M_MDB58
M_MDB57
M_MDB56
M_MDB63
M_MDB62
M_MDB61
M_MDB60
M_MDB[63..0]
M_MDB[63..0] (10,11)MDB[63..0](14)
SERIES Resistors
For Bi-Directional signals,
Series resistors should be
placed close to the
memory
2
1
B B
Proper Termination of QSB?
A A
Size Document Number Rev
C
5
4
3
2
Date: Sheet
MS-V016 ATI RV410
Monday, June 13, 2005
1
13 24
0A
of
www.vinafix.vn
Page 14
5
4
3
2
1
M_DQMA#[7..0](10,11)
M_DQMB#[7..0](10,11)
D D
M_QSA[7..0](10,11)
M_QSB[7..0](10,11)
C C
M_MAA[13..0](10,11)
M_MAB[13..0](10,11)
B B
M_DQMA#[7..0]
M_DQMB#[7..0]
M_QSA[7..0]
M_QSB[7..0]
M_CLKA#0(10,11)
M_CLKA#1(10,11)
M_CLKB#0(10,11)
M_CLKB#1(10,11)
M_CLKA0(10,11)
M_CLKA1(10,11)
M_CLKB0(10,11)
M_CLKB1(10,11)
M_CKEA(10,11)
M_WEA#(10,11)
M_CASA#(10,11)
M_RASA#(10,11)
M_CSA#0(10,11)
M_CSA#1(10,11)
M_CKEB(10,11)
M_WEB#(10,11)
M_CASB#(10,11)
M_RASB#(10,11)
M_CSB#0(10,11)
M_CSB#1(10,11)
M_MAA[13..0]
M_MAB[13..0]
+MVDDQ
+VREF_U55
C211
100nF
M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_CLKA0
M_CLKA#0
M_CKEA
M_CSA#0
M_RASA#0
M_CASA#0
M_WEA#
M_QSA3
M_QSA1
M_DQMA#3
M_DQMA#1
M_MAA13
M_MAA12
C210
100nF
+VREF_U54
M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_CLKA0
M_CLKA0#
M_CKEA
M_CSA#0
M_RASA#0
M_CASA#0
M_WEA#
M_QSA0
M_QSA2
M_DQMA#0
M_DQMA#2
M_MAA13
M_MAA12
M_DQMA#0
M_DQMA#1
M_DQMA#2
M_DQMA#3
M_DQMA#4
M_DQMA#5
M_DQMA#6
M_DQMA#7
M_DQMB#0
M_DQMB#1
M_DQMB#2
M_DQMB#3
M_DQMB#4
M_DQMB#5
M_DQMB#6
M_DQMB#7
M_QSA0
M_QSA1
M_QSA2
M_QSA3
M_QSA4
M_QSA5
M_QSA6
M_QSA7
M_QSB0
M_QSB1
M_QSB2
M_QSB3
M_QSB4
M_QSB5
M_QSB6
M_QSB7
M_CLKA0#
M_CLKA1#
M_CLKB0#
M_CLKB1#
M_CLKA0
M_CLKA1
M_CLKB0
M_CLKB1
M_CKEA
M_WEA#
M_CASA#0
M_RASA#0
M_CSA#0
M_CSA#1
M_CKEB
M_WEB#
M_CASB#0
M_RASB#0
M_CSB#0
M_CSB#1
M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_MAA12
M_MAA13
M_MAB0
M_MAB1
M_MAB2
M_MAB3
M_MAB4
M_MAB5
M_MAB6
M_MAB7
M_MAB8
M_MAB9
M_MAB10
M_MAB11
M_MAB12
M_MAB13
MDA[63..0](12)
MDB[63..0](13)
Channel A UP Channel A Down
U55
49
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
A10/AP
41
A11
45
CK
46
CK
44
CKE
24
CS
23
RAS
22
CAS
21
WE
16
LDQS
51
UDQS
20
LDM
47
UDM
26
BA0
27
BA1
1MX16X4
64MB
U54
49
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
A10/AP
41
A11
45
CK
46
CK
44
CKE
24
CS
23
RAS
22
CAS
21
WE
16
LDQS
51
UDQS
20
LDM
47
UDM
26
BA0
27
BA1
1MX16X4
64MB
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
NC#17
NC#19
NC#25
NC#42
NC#43
NC#50
NC#53
VDD#18
VDD#33
VDDQ
VDDQ#9
VDDQ#15
VDDQ#55
VDDQ#61
VSS#48
VSS#66
VSSQ#6
VSSQ#12
VSSQ
VSSQ#58
VSSQ#64
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
NC#17
NC#19
NC#25
NC#42
NC#43
NC#50
NC#53
VDD#18
VDD#33
VDDQ
VDDQ#9
VDDQ#15
VDDQ#55
VDDQ#61
VSS#48
VSS#66
VSSQ#6
VSSQ#12
VSSQ
VSSQ#58
VSSQ#64
MDA28
2
DQ0
MDA29
4
DQ1
MDA30
5
DQ2
MDA31
7
DQ3
MDA24
8
DQ4
MDA25
10
DQ5
MDA26
11
DQ6
MDA27
13
DQ7
MDA12
54
DQ8
MDA13
56
DQ9
MDA14
57
MDA15
59
MDA8
60
MDA9
62
MDA10
63
MDA11
65
14
NC
17
19
25
M_CSA#1
42
43
+MVDDC
50
53
1
VDD
18
33
3
9
15
55
61
34
VSS
48
66
6
12
52
58
64
MDA3
2
DQ0
MDA2
4
DQ1
MDA1
5
DQ2
MDA0
7
DQ3
MDA7
8
DQ4
MDA6
10
DQ5
MDA5
11
DQ6
MDA4
13
DQ7
MDA19
54
DQ8
MDA18
56
DQ9
MDA17
57
MDA16
59
MDA23
60
MDA22
62
MDA21
63
MDA20
65
14
NC
17
19
25
M_CSA#1
42
43
+MVDDC
50
53
1
VDD
18
33
3
9
15
55
61
34
VSS
48
66
6
12
52
58
64
+MVDDQ
+MVDDQ
+MVDDQ
+VREF_U53
C209
100nF
M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_CLKA1
M_CLKA1#
M_CKEA
M_CSA#0
M_RASA#0
M_CASA#0
M_WEA#
M_QSA7
M_QSA5
M_DQMA#7
M_DQMA#5
M_MAA13
M_MAA12
C208
100nF
+VREF_U52
M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_CLKA1
M_CLKA1#
M_CKEA
M_CSA#0
M_RASA#0
M_CASA#0
M_WEA#
M_QSA6
M_QSA4
M_DQMA#6
M_DQMA#4
M_MAA13
M_MAA12
U53
49
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
A10/AP
41
A11
CK
CK
CKE
CS
RAS
CAS
WE
LDQS
UDQS
LDM
UDM
BA0
BA1
1MX16X4
64MB
U52
VREF
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
CK
CK
CKE
CS
RAS
CAS
WE
LDQS
UDQS
LDM
UDM
BA0
BA1
1MX16X4
64MB
NC#17
NC#19
NC#25
NC#42
NC#43
NC#50
NC#53
VDD#18
VDD#33
VDDQ
VDDQ#9
VDDQ#15
VDDQ#55
VDDQ#61
VSS#48
VSS#66
VSSQ#6
VSSQ#12
VSSQ#58
VSSQ#64
NC#17
NC#19
NC#25
NC#42
NC#43
NC#50
NC#53
VDD#18
VDD#33
VDDQ
VDDQ#9
VDDQ#15
VDDQ#55
VDDQ#61
VSS#48
VSS#66
VSSQ#6
VSSQ#12
VSSQ#58
VSSQ#64
45
46
44
24
23
22
21
16
51
20
47
26
27
49
29
30
31
32
35
36
37
38
39
40
28
41
45
46
44
24
23
22
21
16
51
20
47
26
27
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
VSSQ
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
VSSQ
Channel B UP
U50
49
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
A10/AP
41
A11
45
CK
46
CK
44
CKE
24
CS
23
RAS
22
CAS
21
WE
16
LDQS
51
UDQS
VDDQ#15
VDDQ#55
VDDQ#61
20
LDM
47
UDM
26
BA0
27
BA1
VSSQ#12
VSSQ#58
VSSQ#64
1MX16X4
64MB
U51
49
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
A10/AP
41
A11
45
CK
46
CK
44
CKE
24
CS
23
RAS
22
CAS
21
WE
16
LDQS
51
UDQS
VDDQ#15
VDDQ#55
VDDQ#61
20
LDM
47
UDM
26
BA0
27
BA1
VSSQ#12
VSSQ#58
VSSQ#64
1MX16X4
64MB
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
NC#17
NC#19
NC#25
NC#42
NC#43
NC#50
NC#53
VDD#18
VDD#33
VDDQ
VDDQ#9
VSS#48
VSS#66
VSSQ#6
VSSQ
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
NC#17
NC#19
NC#25
NC#42
NC#43
NC#50
NC#53
VDD#18
VDD#33
VDDQ
VDDQ#9
VSS#48
VSS#66
VSSQ#6
VSSQ
2
DQ0
4
DQ1
5
DQ2
7
DQ3
8
DQ4
10
DQ5
11
DQ6
13
DQ7
54
DQ8
56
DQ9
57
59
60
62
63
65
14
NC
17
19
25
42
43
50
53
1
VDD
18
33
3
9
15
55
61
34
VSS
48
66
6
12
52
58
64
2
DQ0
4
DQ1
5
DQ2
7
DQ3
8
DQ4
10
DQ5
11
DQ6
13
DQ7
54
DQ8
56
DQ9
57
59
60
62
63
65
14
NC
17
19
25
42
43
50
53
1
VDD
18
33
3
9
15
55
61
34
VSS
48
66
6
12
52
58
64
M_CLKB1
M_CLKB1#
M_CKEB
+MVDDQ
M_CLKB1
M_CLKB1#
M_CKEB
+VREF_U49
M_MAB0
M_MAB1
M_MAB2
M_MAB3
M_MAB4
M_MAB5
M_MAB6
M_MAB7
M_MAB8
M_MAB9
M_MAB10
M_MAB11
M_CSB#0
M_RASB#0
M_CASB#0
M_WEB#
M_QSB7
M_QSB6
M_DQMB#7
M_DQMB#6
M_MAB13
M_MAB12
C256
100nF
+VREF_U47
M_MAB0
M_MAB1
M_MAB2
M_MAB3
M_MAB4
M_MAB5
M_MAB6
M_MAB8
M_MAB9
M_MAB10
M_MAB11
M_CSB#0
M_RASB#0
M_CASB#0
M_WEB#
M_QSB4
M_QSB5
M_DQMB#4
M_DQMB#5
M_MAB13
M_MAB12
MDB3
MDB2
MDB1
MDB0
MDB7
MDB6
MDB5
MDB4
MDB19
MDB18
MDB17
MDB16
MDB23
MDB22
MDB21
MDB20
M_CSB#1
+MVDDC
+MVDDQ
MDB28
MDB29
MDB30
MDB31
MDB24
MDB25
MDB26
MDB27
MDB12
MDB13
MDB14 M_MAB7
MDB15
MDB8
MDB9
MDB10
MDB11
M_CSB#1
+MVDDC
+MVDDQ
+MVDDQ
+VREF_U50
C257
100nF
M_MAB0
M_MAB1
M_MAB2
M_MAB3
M_MAB4
M_MAB5
M_MAB6
M_MAB7
M_MAB8
M_MAB9
M_MAB10
M_MAB11
M_CLKB0
M_CLKB0#
M_CKEB
M_CSB#0
M_RASB#0
M_CASB#0
M_WEB#
M_QSB0
M_QSB2
M_DQMB#0
M_DQMB#2
M_MAB13
M_MAB12
C259
100nF
+VREF_U51
M_MAB0
M_MAB1
M_MAB2
M_MAB3
M_MAB4
M_MAB5
M_MAB6
M_MAB7
M_MAB8
M_MAB9
M_MAB10
M_MAB11
M_CLKB0
M_CLKB0#
M_CKEB
M_CSB#0
M_RASB#0
M_CASB#0
M_WEB#
M_QSB3
M_QSB1
M_DQMB#3
M_DQMB#1
M_MAB13
M_MAB12
MDA56
2
DQ0
MDA57
4
DQ1
MDA58
5
DQ2
MDA59
7
DQ3
MDA60
8
DQ4
MDA61
10
DQ5
MDA62
11
DQ6
MDA63
13
DQ7
MDA40
54
DQ8
MDA41
56
DQ9
MDA42
57
MDA43
59
60
MDA45
62
MDA46
63
MDA47
65
14
NC
17
19
25
M_CSA#1
42
43
+MVDDC
50
53
1
VDD
VSS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
VDD
VSS
+MVDDQ
18
33
3
9
15
55
61
34
48
66
6
12
52
58
64
MDA55
2
MDA54
4
MDA53
5
MDA52
7
MDA51
8
MDA50
10
MDA49
11
MDA48
13
MDA39
54
MDA38
56
MDA37
57
MDA36
59
MDA35
60
MDA34
62
MDA33
63
MDA32
65
14
NC
17
19
25
M_CSA#1
42
43
+MVDDC
50
53
1
+MVDDQ
18
33
3
9
15
55
61
34
48
66
6
12
52
58
64
C258
100nF
Channel B Down
U49
49
29
30
31
32
35
36
37
38
39
40
28
41
45
46
44
24
23
22
21
16
51
20
47
26
27
49
29
30
31
32
35
36
37
38
39
40
28
41
45
46
44
24
23
22
21
16
51
20
47
26
27
VREF
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
CK
CK
CKE
CS
RAS
CAS
WE
LDQS
UDQS
LDM
UDM
BA0
BA1
1MX16X4
64MB
U47
VREF
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
CK
CK
CKE
CS
RAS
CAS
WE
LDQS
UDQS
LDM
UDM
BA0
BA1
1MX16X4
64MB
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
NC#17
NC#19
NC#25
NC#42
NC#43
NC#50
NC#53
VDD#18
VDD#33
VDDQ
VDDQ#9
VDDQ#15
VDDQ#55
VDDQ#61
VSS#48
VSS#66
VSSQ#6
VSSQ#12
VSSQ
VSSQ#58
VSSQ#64
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
NC#17
NC#19
NC#25
NC#42
NC#43
NC#50
NC#53
VDD#18
VDD#33
VDDQ
VDDQ#9
VDDQ#15
VDDQ#55
VDDQ#61
VSS#48
VSS#66
VSSQ#6
VSSQ#12
VSSQ
VSSQ#58
VSSQ#64
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
VDD
VSS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
VDD
VSS
MDB60
2
MDB61
4
MDB62
5
MDB63
7
MDB56
8
MDB57
10
MDB58
11
MDB59
13
MDB52
54
MDB53
56
MDB54MDA44
57
MDB55
59
MDB48
60
MDB49
62
MDB50
63
MDB51
65
14
NC
17
19
25
M_CSB#1
42
43
+MVDDC
50
53
1
+MVDDQ
18
33
3
9
15
55
61
34
48
66
6
12
52
58
64
MDB35
2
MDB34
4
MDB33
5
MDB32
7
MDB39
8
MDB38
10
MDB37
11
MDB36
13
MDB43
54
MDB42
56
MDB41
57
MDB40
59
MDB47
60
MDB46
62
MDB45
63
MDB44
65
14
NC
17
19
25
M_CSB#1
42
43
+MVDDC
50
53
1
+MVDDQ
18
33
3
9
15
55
61
34
48
66
6
12
52
58
64
DDR SDRAM 64Mbit 1Mx16x4
DDR SDRAM 128Mbit 2Mx16x4
R280
5.1K
+VREF_U55
R284
5.1K
R288
5.1K
+VREF_U50
R291
5.1K
R279
5.1K
+VREF_U54
R283
5.1K
R287
5.1K
+VREF_U51
R292
5.1K
+MVDDQ
+MVDDQ
+MVDDQ
+MVDDQ
R278
5.1K
+VREF_U53
R282
5.1K
R286
5.1K
+VREF_U49
R290
5.1K
R277
5.1K
+VREF_U52
R281
5.1K
R285
5.1K
+VREF_U47
R289
5.1K
+MVDDQ
+MVDDQ
+MVDDQ
+MVDDQ
C222
100nF
C242
100nF
C270
100nF
C290
100nF
C223
100nF
C243
100nF
C271
100nF
C291
100nF
+MVDDC+MVDDQ +MVDDQ
+MVDDC
C224
100nF
C244
100nF
C272
100nF
C292
100nF
C227
100nF
C247
100nF
C275
100nF
C228
100nF
C248
100nF
C276
100nF
C229
100nF
C249
100nF
C226
C225
100nF
100nF
+MVDDQ +MVDDQ
C246
C245
100nF
100nF
C273
C274
100nF
100nF
C293
100nF
4
C230
100nF
C250
100nF
+MVDDQ
+MVDDQ
C231
100nF
C251
100nF
C279
100nF
C299
100nF
C232
100nF
C252
100nF
C280
100nF
C2191
100nF
C233
100nF
C253
100nF
3
C235
C234
100nF
100nF
+MVDDC+MVDDC
C255
C254
100nF
100nF
+MVDDC+MVDDQ+MVDDQ
C283
100nF
+MVDDC+MVDDC
C2194
100nF
Size Document Number Rev
C
2
Date: Sheet
MS-V016 ATI RV410
Monday, June 13, 2005
1
14 24
0A
of
+MVDDC +MVDDQ +MVDDC +MVDDC
C216
C217
C218
100nF
100nF
+MVDDQ +MVDDC+MVDDC
C236
C237
100nF
100nF
A A
+MVDDQ
C264
100nF
C284
100nF
C265
100nF
C285
100nF
C219
100nF
100nF
C239
100nF
C266
C267
100nF
100nF
+MVDDC
C287
C286
100nF
100nF
5
C220
100nF
C240
100nF
C268
100nF
C288
100nF
+MVDDQ
+MVDDQ+MVDDC
+MVDDQ+MVDDQ
C221
100nF
C241
100nF
C269
100nF
C289
100nF
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Page 15
1
2
3
4
5
6
7
8
OPTION STRAPS
GPIO[6..0]
GPIO[6..0](4)
R570 10K
R571 10K
+VDD_1.8V
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO8
GPIO9
GPIO11
GPIO12
GPIO13
+VDD_1.8V
DNI
DNI
R57210K
R57310K
A A
Overlap pads to save space
and to prevent assembly of
both resistors.
Layout
High logic voltageGround
Signal
GPIO[13..8](4)
B B
VSYNC_DAC1(2,4,16)
HSYNC_DAC1(2,4,16)
DVALID(4)
C C
D D
PSYNC(4)
DVOMODE_0(4)
R331 10K
R332 10K
R333 10K
R334 10K
R205 10K DNI
R206 10K
R335 10K DNI
R336 10K
R347 10K DNI
R348 10K
R349 10K DNI
R350 10K
R351 10K DNI
R352 10K
R345 10K DNI
R346 10K
R343 10K
R344 10K DNI
R337 10K
R338 10K
R339 10K
R340 10K
R341 10K
R342 10K
R359 10K
R360 10K
R357 10K
R358 10K
R361 10K DNI
R362 10K
R363 10K DNI
R364 10K
DVOMODE_1 (4)
DNI
DNI
DNI
DNI
DNI
DNI
DNI
RV410 Shared Straps
STRAPS
+3.3V_BUS
TRANSMIT_DE-EMPHASIS
PCIE_MODE
(ATI Internal)
TX_IEXT
FORCE _COMPLIANCE GPIO(5)
PLL_BW
(ATI Internal)
RV410 Dedicated Straps
ZV_VOLTAGE_SEL0 DVOVMODE_0
Board Straps
STRAPS VALUEDESCRIPTIONPIN
MEMTYPE(1:0)
DC_Strap1
DC_Strap2
DC_Strap3 HDTV out detect
DC_Strap4,
DEMUX_SEL
PAL/NTSC
PIN
GPIO(0)PCIE_SWING
GPIO(1)
GPIO(3:2)
GPIO(4)
GPIO(6)
GPIO(8)DEBUG_ACCESS
VSYNC
HSYNC 0RFU RFU
DVALID, PSYNC.
GPIO(10)
LCDDATA(13)
LCDDATA(14)
LCDDATA(15,19)
LCDDATA(18)
DESCRIPTION
Transmitter Swing Control
0: 50% Tx output swing mode
1: full Tx output swing
Transmitter De-emphasis Enable
0: Tx de-emphasis disabled for mobile mode
1: Tx de-emphasis enabled
PCIE mode:
00: PCI Express 1.0A mode
01: Kyrene-compatible mode
10: PCI Express 1.0 mode
11: RESERVED
Transmitter Extra Current
0: normal mode
1: extra current in Tx output stage
Force chip to get to compliance state quickly for Tester purposes
0: Normal operation
1: Force to compliance state
1: Reduced PLL bandwidth
0: Disable debug access
1: Enable debug access
If no ROM attached, controls chip IDis. If rom attached identifies ROM type.
GPIO[9,13,12,11]
000x - No ROM,CHG_ID=00
001x - No ROM, CHG_ID=01
010x - No ROM, CHG_ID=10
011x - No ROM, CHG_ID=11
1001 - 1M Serial AT25F1024 ROM (Atmel)
1010 - 1M Serial AT45DB011 ROM (Atmel)
1011 - 1M Serial M25P10 ROM (ST)
1100 - 512K Serial M25P05 ROM (ST)
1101 - 1M Serial SST45LF010 ROM (SST)
1M Serial W45B512 ROM (WinBond)
512K Serial W45B012 ROM (WinBond)
1110 - 1M Serial SST25VF010 ROM (SST)
512K Serial SST25VF512 ROM (SST)
1111 - 1M NX25F011B ROM (NexFlash)
Chip IDs:
Chip ID is based on substrate fuses and CHG_ID strap (which comes from ROM if used,
or pin straps if no ROM is connected): CHG_ID = ROMIDCFG[2:1] = GPIO[13:12]
Indicates if any slave VIP host devices drove this in low during reset.VIP_DEVICE
0 - Slave VIP host port devi ces pr esent
1 - No slave VIP host port devices reportin g presence during reset
0 - Normal
1 - Not used
DVOVMODE_0 is for ZV_LCDCNTL and ZV_LCDDATA(11:0}.
0 - 3.3 V signaling
1 - 1.8 V signaling
DVOVMODE_1 is for ZV_LCDDATA(23:12)ZV_VOLTAGE_SEL1 DVOVMODE_1
0 - 3.3 V signaling
1 - 1.8 V signaling
Memory connected to R420 identification for BIOS
00 - Samsung GDDR 3 memory 144 Ball BGA package
01 - TBD
10 - TBD
11 - TBD
Internal TMDS Enabled
0 - Disabled
1 - Enabled
Video Capture Enabled
0 - Disabled
1 - Not detected
0 - Detected
1 - Enabled
Video capture enable
00 - DAC2 Off
01 - DAC2 On as CRT
10 - DAC2 On as TVOUT
11 - DAC2 On as TVOUT and CRT
TVO Standard Default (Resistor pull-up and switch short to GND)
0 - PAL (on boar d resistor pull-down and switch closed)
1 -NTSC (on board resistor pull-up)
REV. 0.5
VALUE
1
1
00
0
0
00: Full PLL Bandwidth
0Strap to set the debug muxes to bring out DEBUG signals even if registers are inaccessible
1100GPIO(9,13:11)ROMIDCFG(3:0)
1
REV. 0.2
0
0
REV. 0.3
000
1
0
1
01
1
+3.3V_BUS
R584 10K
R580 10K
DNI
R576 10K
PAL/NTSC (4)
+3.3V_BUS
DEMUX_SEL(4)
DC_Strap3(4,21)
GPIO10(4)
DC_Strap4 (4)
DC_Strap2 (4)
R577 10K
R581 10K
R585 10K DNI
R582 10K
R578 10K
R574 10K
DC_Strap1GPIO[13..8]
R575 10K
R579 10K
R583 10K DNI
DNI
DNI
DNI
WARNING
Some of those straps must be connected to +VDD_1.8V
if ZV_LCDATA bus is set to 1.8 V.
Size Document Number Rev
C
1
2
3
4
5
6
Date: Sheet
7
MS-V016 ATI RV410
Monday, June 13, 2005
15 24
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Page 16
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4
3
2
1
PRIMARY DISPLAY
VSYNC_DAC1_R(19)
HSYNC_DAC1_R(19)
DDCCLK_DAC1_5V(19)
DDCDATA_DAC1_5V(19)
B_DAC1_F(19)
G_DAC1_F(19)
R_DAC1_F(19)
D D
R_DAC1(4)
G_DAC1(4)
B_DAC1(4)
+3.3V_BUS
R467
+3.3V_BUS
4.7K
R468
4.7K
+3.3V_BUS
CRT1DDCDATA(2,4)
CRT1DDCCLK(2,4)
C C
HSYNC_DAC1(2,4,15)
VSYNC_DAC1(2,4,15)
+3.3V_BUS
1
1
BSN20
Q13
BSN20
Q12
32
+5V
32
U3B
4
5
9
10
SN74ACT86PW
R464
6.8K
+5V
R463
6.8K
6
SN74ACT86PW
U3C
8
R403
75.0R
R859 33R
R860 33R
PRIMARY CRT INTERFACE
L51 47nH
L52 47nH
L53 47nH
R401
R402
75.0R
75.0R
C401
C402
C403
6.8pF
6.8pF
6.8pF
PLACE CLOSE TO ASIC
L54 47nH
L55 47nH
L56 47nH
C404
C405
8pF
8pF
C406
8pF
NI NI NI
C408
C407
5pF
5pF
C409
5pF
R_DAC1_F
G_DAC1_F
B_DAC1_F
DDCDATA_DAC1_5V
DDCCLK_DAC1_5V
HSYNC_DAC1_R
VSYNC_DAC1_R
OPTIONAL ESD/HOTPLUG PROTECTION DIODES
+3.3V_BUS +3.3V_BUS
BAT54SLT1
3
PLACE CLOSE TO
CONNECTOR
+3.3V_BUS
+12V_BUS+12V_BUS+12V_BUS+12V_BUS
D11
BAT54SLT1
3
2
D12
BAT54SLT1
1
2
3
1
2
2
D10
3
1
1
DNI DNI DNI DNI DNI DNI DNI
R465 33R
R466 33R
NI NI
D13
BAT54SLT1
3
C751
22pF
2
D14
BAT54SLT1
1
2
3
1
D15
BAT54SLT1
3
C752
22pF
2
D16
BAT54SLT1
1
C562
100nF
PRIMARY VGA
CONNECTOR
F1
750mA
+5VCON1
B39
Bead
1
2
3
11
12
4
15
9
13
14
5
6
7
8
10
16
17
+5V
+5VCON1 (9,19,21)
+5V_DIN2 (19)
J5
R
G
B
MS0
MS1
MS2
MS3
NC
HS
VS
VSS
VSS#6
VSS#7
VSS#8
VSS#10
CASE
CASE#17
SLIM VGA HT 6.27MM
SECONDARY DISPLAY
OPTIONAL ESD/HOTPLUG PROTECTION DIODES
+3.3V_BUS+3.3V_BUS +3.3V_BUS
2
2
D17
D18
1
3
BAT54SLT1
1
3
BAT54SLT1
PLACE CLOSE TO ASIC
C451
6.8pF
1
BSN20
1
BSN20
Q15
74ACT08MTC
U2C
U2D
74ACT08MTC
L71 47nH
L72 47nH
L73 47nH
C452
C453
6.8pF
6.8pF
+5V
32
Q14
+5V
32
8
11
6.8K
R480
6.8K
R482
R31 33R
R32 33R
R_DAC2(4)
G_DAC2(4)
B_DAC2(4)
B B
CRT2DDCDATA(4)
CRT2DDCCLK(4)
A A
HSYNC_DAC2(4)
VSYNC_DAC2(4)
5
R451 75.0R
R452 75.0R
R453 75.0R
+3.3V_BUS
R479
4.7K
+3.3V_BUS
R481
4.7K
+5V
10
9
13
12
C454
C455
8pF
8pF
R825 33R
R824 33R
L74 47nH
L75 47nH
L76 47nH
C456
8pF
4
NI NI NI
C573
C574
5pF
5pF
DDCDATA_DAC2_R (19)
DDCCLK_DAC2_R (19)
HSYNC_DAC2_R (19)
VSYNC_DAC2_R (19)
C575
5pF
R_DAC2_F
G_DAC2_F
B_DAC2_F
3
R_DAC2_F (19)
G_DAC2_F (19)
B_DAC2_F (19)
3
+12V_BUS+12V_BUS+12V_BUS+12V_BUS
2
1
D19
3
BAT54SLT1
C749
22pF
DNI DNI
2
DNIDNIDNIDNI
C750
22pF
2
1
2
2
D22
D21
D20
3
BAT54SLT1
3
3
BAT54SLT1
BAT54SLT1
1
1
PLACE CLOSE TO
CONNECTOR
2
D23
BAT54SLT1
1
DNIDNIDNI
Size Document Number Rev
C
Monday, June 13, 2005
Date: Sheet
+5V_DIN1
1
2
3
11
12
4
15
9
13
14
5
6
7
8
10
16
17
DNI
MJ4
R
G
B
DDC2_MONID0
MS0
DDC2_MONID1(SDA)
MS1
DDC2_MONID2
MS2
DDC2_MONID3(SCL)
MS3
NC
HS
VS
VSS
VSS#6
VSS#7
VSS#8
VSS#10
CASE
CASE#17
SLIM VGA HT 6.27MM
+5V_DIN1 (19)
MS-V016 ATI RV410
1
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Page 17
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1
TEMPERATURE SENSE AND SPEED CONTROLLED FAN
D D
+12V_BUS
B59
Bead
R1573
C1134
0R
100nF
DNI
+3.3V_BUS
C1517
C1516
R1610
C C
SCL(2,4,18)
SDA(4,18)
ThermINT(4)
R1620 100R
R1621
R1624 0R
100R
SCL_R
SDA_R
10K
TACH GPU_DMINUS
C1524
56pF
C1525
56pF
U106
8
SMBCLK
7
SMBDAT
6
ALERT
5 4
GND PWM
LM63CIMAX
Do not install
This resistor will
be shorted in layout.
It is present to control
where the signal will be
connected to digital
ground.
B B
R1684 0R
DNI
C1518
0.1uF
10uF
VDD
D+
D-
100pF
1
2
3
PWM
R1683 10R
R1609
4.7K
C1519
2.2nF
DNI
R1682 0R
GPU_DPLUS
+12V_BUS
1
R1681
1K
Q213
MMBT2222ALT1
2 3
DNI
TACH
R1629
10K
GPU_DPLUS (4)
GPU_DMINUS (4)
C1577
1uF
DNI
R16280R
C1520 10nF
+12V_BUS
DNI
R1631
10K
32
Q209
1
ZXM61N03FTA
DNI
R1611
0R
DNI
JU1
1
2
JUl2
DUAL FOOTPRINT
MJU1
1
2
JUl1
3
Header_1X3
Not installed
A A
Size Document Number Rev
C
5
4
3
2
Date: Sheet
MS-V016 ATI RV410
Monday, June 13, 2005
1
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0A
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Page 18
5
D D
4
LCDCNTL_R[3..0]
MUST BE INSTALLED IF NO
TMDS IS INSTALLED
+3.3V_BUS
3
2
1
LCDCNTL_R0
LCDCNTL_R1
LCDCNTL_R2
LCDCNTL_R3
RP600A 10K
RP600B 10K
RP600C 10K
RP600D 10K
81
72
63
54
Place close to TMDS
TXCP_EXT (19)
TXCM_EXT (19)
TX2P_EXT (19)
C481 100nF
C482 100nF
C483 100nF
C484 100nF
C465
100nF
C471
22uF_10V
+3.3V_BUS
C476
100pF
TX2M_EXT (19)
TX1P_EXT (19)
TX1M_EXT (19)
TX0P_EXT (19)
TX0M_EXT (19)
B31
C466
47uF_6.3V
C477
2.2nF
150R
+3.3V_BUS+AVCC_TMDS
Max 25 mA
+3.3V_BUS
B32
200R
22uF_10V
C1236
REG9
TL431CDBVR
+12V_BUS
R301
360R
R304
680R
4
NC
1
NC
R491
2
2K
5 3
VID/DVO_R[11..0](4)
C C
LCDCNTL_R[3..0](4)
B B
PERST#_buf(2,3,20)
VID/DVO_R[11..0]
LCDCNTL_R[3..0]
+3.3V_BUS
INSTALL FOR Si164
HI = I2C SELECT,LO = I2C CTRL RESET
+3.3V_BUS
+3.3V_BUS
R483 5.1K
R1103
R1104 0R
R484 0R
R492 0R
R625 1K
R620 1K
33K
Do not install
VID/DVO_R0
VID/DVO_R1
VID/DVO_R2 TX0M_EXT
VID/DVO_R3
VID/DVO_R4
VID/DVO_R5
VID/DVO_R6
VID/DVO_R7
VID/DVO_R8
VID/DVO_R9
VID/DVO_R10
VID/DVO_R11
I2C_ADDR
LCDCNTL_R1
LCDCNTL_R0
LCDCNTL_R2
LCDCNTL_R3
+VREF_TMDS
MSEN_TMDS
HPD_ExtTMDS
I2C_RST
SDA(4,17)
SCL(2,4,17)
18
17
16
15
14
13
10
9
8
7
6
5
24
20
21
19
12
11
48
44
25
26
27
1
31
47
U37
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
CTL3/A2
HDYNC
VSYNC
DE
IDICK+
IDCK-
MSEN
EDGE/HTPLG
ISEL/RST#
SDA
SCL
RSVD
RSVD#31
RSVD#47
SiI1162
TX0+
TX1+
TX2+
TXC-
TXC+
AVCC
AVCC#40
AGND
AGND#43
VREF
EXT_SWING
PVCC1
PVCC2
PGND
PGND#45
VCC#22
GND#23
TH_GND
35
TX0-
36
38
TX1-
39
41
TX2-
42
32
33
34
40
37
43
+VREF_TMDS
2
30
28
46
29
45
22
3
VCC
4
GND
23
49
TX0P_EXT
TX1M_EXT
TX1P_EXT
TX2M_EXT
TX2P_EXT
TXCM_EXT
TXCP_EXT
100pF
C460
C461
2.2nF
EXT_SWING
C469
100pF
C472
100pF
C470
100nF
C473
100nF
C462
100nF
R1240 330R
R1241 330R
R1242 330R
R1243 330R
C463
100pF
C479
100pF
C474
2.2nF
C464
2.2nF
R485 680R
+PVCC_TMDS
C480
100nF
C475
100nF
SELECT VREF ACCORDING
TO SWING ON D[23:0]
+VDDR4
+3.3V_BUS
R486
R487
20K
20K
CMPT3904
Q32
402 402
1
Q33
2 3
CMPT3904
1
2 3
A A
5
HPD_ExtTMDS
D35
MMBZ5222BLT1
R490
100K
1 3
4
R488 20K
R489 20K
402
402
3
HPD_ExtTMDS_DVI (19)HPD_ExtTMDS(4)
SELECT VREF ACCORDING
TO SWING ON D[23:0]
C478
100nF
X7R
C467
100nF
X7R
R302
1.0K
R303
1.0K
2
+VREF_TMDS
Size Document Number Rev
C
Date: Sheet
MS-V016 ATI RV410
Monday, June 13, 2005
of
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Page 19
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PRIMARY DVI-I CONNECTOR (DVI-I1)
B38 Bead
+5V_DIN1
+5V_DIN2
Place close to
the connector
C558
100nF
J4
25
CASE
1
TMDS Data2-
2
TMDS Data2+
3
TMDS Data2/4 Shield
4
TMDS Data4-
5
TMDS Data4+
6
DDC Clock
7
DDC Data
8
Analog VSYNC
9
TMDS Data1-
10
TMDS Data1+
11
TMDS Data1/3 Shield
12
TMDS Data3-
13
TMDS Data3+
14
+5V Power
15
GND (for +5V)
16
Hot Plug Detect
17
TMDS Data0-
18
TMDS Data0+
19
TMDS Data0/5 Shield
20
TMDS Data5-
21
TMDS Data5+
22
TMDS Clock Shield
23
TMDS Clock+
24
TMDS Clock-
C1
Analog Red
C2
Analog Green
C3
Analog Blue
C4
Analog HYNC
C5
Analog GND
C6
Analog GND#C6
26
CASE#26
27
CASE#27
28
CASE#28
29
CASE#29
30
CASE#30
DVICONNECTOR
J6
25
CASE
1
TMDS Data2-
2
TMDS Data2+
3
TMDS Data2/4 Shield
4
TMDS Data4-
5
TMDS Data4+
6
DDC Clock
7
DDC Data
8
Analog VSYNC
9
TMDS Data1-
10
TMDS Data1+
11
TMDS Data1/3 Shield
12
TMDS Data3-
13
TMDS Data3+
14
+5V Power
15
GND (for +5V)
16
Hot Plug Detect
17
TMDS Data0-
18
TMDS Data0+
19
TMDS Data0/5 Shield
20
TMDS Data5-
21
TMDS Data5+
22
TMDS Clock Shield
23
TMDS Clock+
24
TMDS Clock-
C1
Analog Red
C2
Analog Green
C3
Analog Blue
C4
Analog HYNC
C5
Analog GND
C6
Analog GND#C6
26
CASE#26
27
CASE#27
28
CASE#28
29
CASE#29
30
CASE#30
DVICONNECTOR
DVI-I1
DVI-I2
+5V_DIN1(16)
D D
TX2M(4)
TX2P(4)
DDCCLK_DAC2_R(16)
DDCDATA_DAC2_R(16)
VSYNC_DAC2_R(16)
TX1M(4)
TX1P(4)
+5VCON1(9,16,21)
TX0M(4)
TX0P(4)
TXCP(4)
TXCM(4)
R_DAC2_F(16)
G_DAC2_F(16)
B_DAC2_F(16)
HSYNC_DAC2_R(16)
C C
B B
A A
HPD1(4)
2 1
TX2M_EXT(18)
TX2P_EXT(18)
DDCCLK_DAC1_5V(16)
DDCDATA_DAC1_5V(16)
VSYNC_DAC1_R(16)
TX1M_EXT(18)
TX1P_EXT(18)
+5V_DIN2(16)
HPD_ExtTMDS_DVI(18)
TX0M_EXT(18)
TX0P_EXT(18)
TXCP_EXT(18)
TXCM_EXT(18)
R_DAC1_F(16)
G_DAC1_F(16)
B_DAC1_F(16)
HSYNC_DAC1_R(16)
R456
D9
100K
2.5V
CMPT3904
+3.3V_BUS
Q25
R454
20K
402 402
1
Q26
2 3
CMPT3904
R455
20K
1
2 3
R457 20K
R458 20K
402
402
Size Document Number Rev
C
5
4
3
2
Date: Sheet
MS-V016 ATI RV410
Monday, June 13, 2005
1
19 24
0A
of
www.vinafix.vn
Page 20
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C1590
1uF
GND_RT
12
22uF_16V
R1691
10R
C1610
0.068uF
C1612 2.2uF
Add copper area
for heat dissipation
Max 290 mA
REG8
3.3V
3 2
IN OUT
CASE
GND
1
GND_RT GND_RT GND_RT
12
R1689
L67
10R
3.3uH
C1603
C1604
1.0uF
GND_RT
C1606
1.0uF
C1611
+VADCD
22nf
+VADCA
R1703
4.7K
4
C1589
22uF_16V
47
VAGCVDD
49
VAGCVSS#49
48
VAGCVSS
66
VDACVDD
60
VDACBVSS
61
VDACJVSS
33
VIND0
34
VIND1
35
VIND2
36
VIND3
37
VIND4
38
VIND5
39
VIND6
40
VIND7
27
VINGATEA
28
VINGATEB
58
CF
59
CR
57
VAGCCAP
56
VIDEOGNDSENSE
55
VCLAMPCAP
43
VADCDVDD
45
VADCAVDD
44
VADCDVSS
46
VADCAVSS
50
COMP0
51
COMP1
52
COMP2
53
YF_COMP3
54
YR_COMP4
69
XTALIN
70
XTALOUT
73
TESTEN
74
RESETB
67
PLLVDD
68
PLLVSS
+RTAVDD
C1591
1.0uF
18
VSSC#26
VSSC
26
1
VSSC#77
VSSC#83
100
83
29
VDDR
VDDR#71
VDDR#29
VSSR#2
VSSC#100
2
81
VDDR#81
VSSR#12
VSSR#30
12
30
C1595
10nF
25
767771
VDDC
VSSR#72
82
72
99
VDDC#99
VDDC#76
VSSR
VSSR#90
90
GND_RT
C1596
1.0uF
41
31
VDDR#31
VDDC#41
DS_VIPCLK
AS_HCTL
SRDY_IRQB
C_GREEN
COMP_BLUE
CLKOUT0_GPIO0
CLKOUT1_GPIO1
CLKOUT2_GPIO2
VSSC#42
VSSR#32
42
32
RAGE_THEATER
+RTVDDC
C1597
1.0uF
U111
SAD0
SAD1
SAD2
SAD3
SAD4
SAD5
SAD6
SAD7
HAD0
HAD1
SDA
SCL
ADO
ADIO
WS
BITCLK
SPDIF
BYTCLK
SYNC
Y_RED
RSET
GPIO3
GPIO4
GPIO5
GPIO6
PDATA0
PDATA1
PDATA2
PDATA3
PDATA4
PDATA5
PDATA6
PDATA7
PCLK
91
92
93
94
95
96
97
98
88
87
86
84
85
15
16
22
24
23
21
19
89
75
62
63
64
65
78
79
20
13
14
17
80
4
5
6
7
8
9
10
11
3
C1598
1.0uF
+3.3V_BUS
C1592
C1599
22uF_16V
1.0uF
GND_RT
RP196A 33R
RP196B 33R
R1692 47K
RP196D 33R
RP196C 33R
RP194D 33R
5 4
RP194C 33R
6 3
RP194B 33R
7 2
RP194A 33R
8 1
RP195D 33R
5 4
RP195C 33R
6 3
RP195B 33R
7 2
RP195A 33R
8 1
Place close to the Rage
Theater
R1704
12
R1687
L79
3.3uH
10R
C1593
22uF_16V
GND_RT GND_RT
81
72
54
63
R1697 10K
R1695 10K
33R
+VADCA +VADCD
C1600
1.0uF
GND_RT
GND_RT
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VID[7..0]
L80
3.3uH
C1594
22uF_16V
+3.3V_BUS
GND_RT
R1696
4.7K
12
R1688
10R
C1601
1.0uF
CLK_VIPCLK (4)
VPHCTL (4)
VHAD0 (4)
VHAD1 (4)
SPDIFOut (21)
CLK_RT (4)
VID[7..0] (4)
CLK_VIDCLK (4)
Must spread resistors
Do not place under
D D
+12V_BUS
regulator
R1680 47R
R1679 47R
R1678 47R
R1677 47R
PD = 1W
3.3uH
L68
1 2
CompR(21)
3.3uH
L70
LumaR(21)
C C
ChromaR(21)
1 2
L77
1 2
3.3uH
27MHZ
C1616
22pF
PERST#_buf(2,3,18)
B B
3.3uH
C1614
22uF_16V
Ca1 Ca2
L78
C1617
22pF
+RTAVDD
Y2
27_MHZ
2 1
12
R1701
10R
C1615
1.0uF
C1602
330pF
C1607
330pF
C1609
330pF
R1603 330R
R1604
1.0M
R1690
75.0R
R1693
75.0R
R1694
75.0R
C1613 2.2uF
GND_VIN
L69
3.3uH
C1605
22uF_16V
GND_RT
C1608 0.1uF
GND_RT
IMPORTANT
Layout Guide line of THEATER
#1 : Ca1 and Ca2 have to be placed as close as poss i bl e t o t h e r e sp e c t i ve p i n s o f R a g e THEATER
#2 : GND_VIN should be seperated from Di g i t al o r Ch a s s i s G r ound and have no loops
A A
5
#3 : GND_VIN should be connected to Digital GND plane at one point as close as possible to
pin 56 of THEATER
4
Put 2D line as close as possible to pin 56 of Rage Theater
GND_VIN
GND_RT
3
Size Document Number Rev
C
2
Date: Sheet
MS-V016 ATI RV410
Monday, June 13, 2005
1
20 24
0A
of
www.vinafix.vn
Page 21
5
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TV Out (SVHS) MiniDIN 7-pin
SCART
PIN1
PIN2
Jm1
J7
6
+12V
3
Y-OUT
4
C-OUT
7
Comp_out
5
SYNC
1
GND
2
GND#2
8
CASE
9
CASE#9
10
CASE#10
Conn_DIN_Mini_Circular_7_Pin_with_O_Ring
DC_Strap3(4,15)
TBLuma
R606 220R
TBChroma
D D
R608 220R
R504 220R
Connector Jm1 uses the
same footprint as Jm2
and Jm3
R878 0R
Rm22
Rm23
Rm24
C527
82pF
Rm1
B51
TBLuma_R
TBChroma_R
COMPTBComp
CompR_F
B52
R1578
0R
SPDIF - OUT
C C
SPDIFOut(20)
12
13
Not Installed
SN74ACT86PW
U3D
11
+5V
1
2
D2
BAT54SLT1
3
C1144
100nF
R1575 390R
R1577
100R
BLM21A121SPT
B55
C1145
100pF
PIN1
ViVO connector (Installed only if Rage Theater is installed)
TBLuma_R
TBChroma_R
COMP
C1142
220pF
B54
CompR(20)
LumaR(20)
ChromaR(20)
CompR
LumaR
ChromaR
Connector Jm2 uses the
same footprint as Jm1
and Jm3
B53
B56
C1141
220pF
Not Installed
STEREOSCOPIC DISPLAY
CONNECTOR
STEREOSYNC(4)
Not Installed
Rm21
R763 0R
DNI
C753
100nF
1
2
+5V
147
SN74ACT86PW
U3A
+5VCON1(9,16,19)
Rm3
R517 0R
3
Connector Jm3 uses the
same footprint as Jm1
and Jm2
SCART
GND_VIN
DNI
B50 Bead
Bm4
COMP
DNI
Jm2
MJ8
6
+12V
3
Y-OUT
4
C-OUT
7
Comp-out
CompR_F
5
Comp-in
PIN1
1
GND
PIN2
2
GND#2
11
Luma-in
12
Chroma-in
8
CASE
9
CASE#9
10
CASE#10
9 PIN MINIDIN
C1143
120pF
B20
DNI
Jm3
MJ7
PIN1
1
1
2
2
7
7
8
CASE
9
CASE
10
CASE
MiniDIN_3_Pin
TV-OUT
Y_DAC2 TBLuma
Y_DAC2(4)
B B
C_DAC2(4)
COMP_DAC2(4)
A A
COMP_DAC2
C_DAC2
GND_TVVSSN
GND_TVVSSN
GND_TVVSSN
R912
75.0R
R913
75.0R
R914
75.0R
Not Installed
5
L20 470nH
C583
47pF
L21 470nH
C585
47pF
L22 470nH
C588
47pF
C584
47pF
TBChroma
C586
47pF
TBComp
C587
47pF
Size Document Number Rev
C
4
3
2
Date: Sheet
MS-V016 ATI RV410
Monday, June 13, 2005
1
21 24
0A
of
www.vinafix.vn
Page 22
5
CRT
SCREWS
ASSY1
SCREW
JACKSCREW
D D
ASSY4
ASSY
SCREW
JACKSCREW
ASSY
DVI SCREWS
ASSY2
SCREW
JACKSCREW
ASSY
ASSY5
SCREW
JACKSCREW
ASSY
Bracket
6_X_11
ASSY
MT1
MT_Hole_0.136_in.
620NOPN004
ANTISTATIC
BAG
4
REF2
PCB
109-A38700-00A
REF3
ATI LOGO
LABEL
ATI_LOGO_LABEL
3
2
1
RUBBER
Ru1
C C
B B
2 mm
Ru4
2 mm
FM1
SW_FB
1
FM2
SW_FB
1
FM3
SW_FB
1
FM4
SW_FB
1
Ru2
2 mm
Ru3
2 mm
FM5
SW_FB
1
FM6
SW_FB
1
FM7
SW_FB
1
H103
HEATSINK
H104
NA
A A
Size Document Number Rev
C
5
4
3
2
Date: Sheet
MS-V016 ATI RV410
Monday, June 13, 2005
1
22 24
0A
of
www.vinafix.vn
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