MSI MS-V009 Schematic 10

8

<Variant Name>

Title

7

6

5

4

Schematic No.

3

2

1

Date:

AGP R480+Rialto 256MB BGA DVII DVII VIVO

REVISION HISTORY

D D

Sch

PCB

Rev

Rev

0 00A 07/07/04 Initial revision of the schematic based on 105-A474xx-00

C C

Date

REVISION DESCRIPTION

105-A49000-00A

Friday, January 28, 2005

Rev

0

B B

A A

8

7

6

5

4

3

2

1

www.vinafix.vn

5

4

3

2

1

D D

+12V EXT.
+5V EXT.

EXTERNAL
POWER
CONNECTOR

POWER

REGULATION

SHT 14,15,16,17

From +12V_Bus

SWITCHING

+MVDDQ, +MVDDC, +VTT,
+VDDC, +PCIE_VDDRC

From +12V_Bus

C C

B B

Linear

+5V

From +3.3V_Bus

Linear

+VDD_1.8V, +VDDC_CT
+VPCIE_VDDR, +A2VDD,
+PVDD, +TPVDD, +MPVDD

PCIE_PVDD_18, VDDCI

From +3.3V DIRECT:

VDDR3

From +3.3V direct Or drivitive

VDDR4,5

From on board +5V

+RTAVDD

From +12V DIRECT:

FAN

From +3.3V_Bus

Linear

+B_VDDC

MEMORY CHANNEL A B

GDDR3 8M X 32 (BGA)

Speed control
& temperature
sense

SHT 12

Channel A-B memory Address, Data nad Control signals

SHT 19

POWER DELIVERY

BIOS

SHT 4

STRAPS

SHT 7

FAN

SHT 19

ROMCS#

Channel C-D memory Add re ss , Da ta nad Control signals

MEM A B MEM C D

GPIO

R480

SHEET 3, 4, 5, 6, 8, 9

DAC1

VIP

TVO

DAC2

CRT

TMDS

PCIE

TMDS_TX[C,2..0]N TMDS_TX[C,2..0]P HPD, DDC2CLK DDC2DATA

MEMORY CHANNEL C D

GDDR3 8M X 32 (BGA)

R G B HSY VSY DDC1DATA DDC1CLK

SHT 13

CRT1

FILTERS

SHT 20, 22

TVOUT
FILTERS

SHT 23

CRT2 FILTERS

SHT 21

IMPEDANCE
MATCHING

Slim_VGA

slim
CONN

SHT 20

TVout

CONN

SHT 24

DVI-I

CONN

SHT 21

PCI-Express

ROM

Rialto

GPIO

STRAPS

SHT 14

POWER DELIVERY

AGP

AGP R480+Rialto

BLOCK DIAGRAM REFLECTING DELL U HM G A11
CONFIGURATION.
COMPONENTS THAT ARE NOT POPULATED FOR DELL

AGP Bus

SHT 2

A A

5

4

3

UHMGA11 SKU ARE MARKED AS "DNI"

2

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP R480+Rialto 256MB BGA DVII DVII VIVO

Size Document Number Rev

C

Date: Sheet

105-A49000-00A

1

of

128Friday, January 28, 2005

0

www.vinafix.vn

8

LAYOUT NOTE: SOME OF THE CAPS BELOW MAY BE
REMOVED IF SPACE IS AN ISSUE, ASK BEFORE REMOVING

+12V_BUS

C12
10uF_20V

D D

C C

B B

+5V_BUS +3.3V_BUS

C5
47uF_6.3V

AGP_INTR#(23)

AGP_GNT#(23)

AGP_MB_8X_DET#(23)

AGP_DBI_HI(23)

AGP_WBF#(23)

AGP_SBSTB#(23)

AGP_ADSTB1#(23)

AGP_FRAME#(23)

AGP_TRDY#(23)

AGP_STOP#(23)

AGP_PAR(23)

AGP_ADSTB0#(23)

C10
47uF_6.3V

7

+VDDQ_BUS

C4
330uF_2.5V

AGP_CON_RESET#

6

Use 47uF Tant. 16V 20% D size (P/N 4230047600),
800mR Max. ESR and Max. ripple 430mA @ 100kHz

or
100uF, Alum. 6.3V 20% 6.3mm dia (P/N 4261010700),
440mR Max. ESR and Max. ripple 230mA @ 100kHz
or
47uF, Alum. 6.3V 20% 5mm dia (P/N 4262047600),
760mR Max. ESR and Max. ripple 150mA @ 100kHz

Place C2 on left side of AGP connector

+3.3V_BUS

+VDDQ_BUS

AGP_TYPEDET#
AGP_GC_8X_DET#

R7 0R
R9 0R

R1 0R

R5 0R

R12 0R

AGP_VREFGC

402
402

402

402

402

AGP_ST1
AGP_MB_8X_DET#_R
AGP_DBI_HI_R

AGP_SBA1
AGP_SBA3

AGP_SBA5
AGP_SBA7

AGP_AD30
AGP_AD28

AGP_AD26
AGP_AD24

AGP_C/BE#3
AGP_AD22

AGP_AD20
AGP_AD18

AGP_AD16

AGP_PAR_R
AGP_AD15
AGP_AD13

AGP_AD11
AGP_AD9

AGP_C/BE#0

AGP_AD6
AGP_AD4

AGP_AD2

4X/8X AGP BUS

+12V_BUS

MAGP1

A1

12V

A2

TYPEDET#

A3

GC_DET#/RESERVED

A4

USB-

A5

GND

A6

INTA#

A7

RST#

A8

GNT#

A9

VCC3.3

A10

ST1

A11

MB_DET#/RESERVED

A12

DBI_HI/PIPE#

A13

GND#A13

A14

WBF#

A15

SBA1

A16

VCC3.3#A16

A17

SBA3

A18

SB_STB#

A19

GND#A19

A20

SBA5

A21

SBA7

A22

RESERVED

A23

GND#A23

A24

RESERVED#A24

A25

VCC3.3#A25

A26

AD30

A27

AD28

A28

VCC3.3#A28

A29

AD26

A30

AD24

A31

GND#A31

A32

AD_STB1#

A33

C/BE3#

A34

VDDQ1.5

A35

AD22

A36

AD20

A37

GND#A37

A38

AD18

A39

AD16

A40

VDDQ1.5#A40

A41

FRAME#

A42

KEY

A43

KEY#A43

A44

KEY#A44

A45

KEY#A45

A46

TRDY#

A47

STOP#

A48

PME#

A49

GND#A49

A50

PAR

A51

AD15

A52

VDDQ1.5#A52

A53

AD13

A54

AD11

A55

GND#A55

A56

AD9

A57

C/BE0#

A58

VDDQ1.5#A58

A59

AD_STB0#

A60

AD6

A61

GND#A61

A62

AD4

A63

AD2

A64

VDDQ1.5#A64

A65

AD0

A66

VREFGC

1.5V_AGP_BUS

5

OVRCNT#

5.0V#B3
USB+

GND#B5

INTB#
REQ#

VCC3.3#B9

RBF#

GND#B13

DBI_LO/RESERVED

SBA0

VCC3.3#B16

SBA2

SB_STB

GND#B19

SBA4
SBA6

RESERVED#B22

GND#B23

3.3VAUX

VCC3.3#B25

AD31
AD29

VCC3.3#B28

AD27

AD25
GND#B31
AD_STB1

AD23

VDDQ1.5#B34

AD21

AD19
GND#B37

AD17

C/BE2#

VDDQ1.5#B40

IRDY#
KEY#B42
KEY#B43
KEY#B44
KEY#B45

DEVSEL#

VDDQ1.5#B47

PERR#

GND#B49

SERR#
C/BE1#

VDDQ1.5#B52

AD14
AD12

GND#B55

AD10

VDDQ1.5#B58

AD_STB0
GND#B61

VDDQ1.5#B64

VREFCG

4

AGP_C/BE#[3..0]
AGP_AD[31..0]
AGP_SBA[7..0]
AGP_ST[2..0]

+3.3V_BUS

+5V_BUS

+VDDQ_BUS
B1
B2

5.0V

B3
B4
B5
B6
B7

CLK

B8
B9
B10

ST0

B11

ST2

B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57

AD8

B58
B59
B60

AD7

B61
B62

AD5

B63

AD3

B64
B65

AD1

B66

AGP_ST0
AGP_ST2

AGP_SBA0
AGP_SBA2

AGP_SBA4
AGP_SBA6

AGP_AD31
AGP_AD29

AGP_AD27
AGP_AD25

AGP_AD23
AGP_AD21

AGP_AD19
AGP_AD17

AGP_C/BE#2

AGP_C/BE#1
AGP_AD14

AGP_AD12
AGP_AD10

AGP_AD8

AGP_AD7
AGP_AD5

AGP_AD3
AGP_AD1AGP_AD0

AGP_DBI_LO_R

AGP_SBSTB_R

AGP_ADSTB1_R

AGP_ADSTB0_R

AGP_AGPREF

R8 0R

R2 0R

R10 0R

R13 0R

3

VDDC_PGOOD(7)

AGP_C/BE#[3..0] (23)
AGP_AD[31..0] (23)
AGP_SBA[7..0] (23)
AGP_ST[2..0] (23)

402

402

402

402

AGP_AGPCLK (23)
AGP_REQ# (23)

AGP_RBF# (23)
AGP_DBI_LO (23)

AGP_SBSTB (23)

AGP_ADSTB1 (23)

AGP_IRDY# (23)

AGP_DEVSEL# (23)

AGP_ADSTB0 (23)

R1833 0R

DNI

AGP_CON_RESET#

74ACT08MTC

R1834
10K

2

+5V_BUS

1
2

14

+-U2A

7

C972
100nF

R1837 100R

3

+12V_BUS

C22
100nF

402

R1838
180R

+3.3V_BUS+5V_BUS

C25
100nF

402 402

1

SYMBOL LEGEND

DNI

#

AGP_RESET# (19,20,23)

C24
100nF

DO NOT
INSTALL

ACTIVE
LOW

DIGITAL
GROUND

ANALOG
GROUND

Caps for EMI - install close to AGP connector

UNIVERSAL VREFGC CIRCUIT (4X, 8X)

TEST

+VDDQ_BUS

1

32

Q1

R20
324R

2N7002E

R21
147R

R24
100R

402

3

AGP_VREFGC

C6
10nF

402

Close to ASIC

+3.3V_BUS

1

Q20

BSN20

+5V_BUS

53

+

1
2

-U4TC7SZ08FU

32

+12V_BUS

C3
100nF

4

R6
20K

402402

402

R23
1K

402

4

AGP_TYPEDET#

AGP_GC_8X_DET#

A A

R19

5.1R

R64
0R

402

+12V, TYPEDET#
short protection
for OEM (5.1R)

8

R17

AGP_MB_8X_DET#(23)

AGP_MB_8X_DET#

47K

May be placed far from connector -- place C3 FAR from connector, on left side!!

7

6

5

AGP_AGPREF

TEST

UNIVERSAL VREFCG CIRCUIT (4X, 8X)

+VDDQ_BUS

32

1

Q77

2N7002E

R72
147R

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title
Size Document Number Rev

C

Date: Sheet

2

DNI

R75

R73

324R

0R

402 402402

AGP_AGPREFCG

R74

C11

100R

10nF

402402

Close to ASIC

*

AGP R480+Rialto 256MB BGA DVII DVII VIVO

105-A49000-00A

AGP_AGPREFCG (23)

of

228Friday, January 28, 2005

1

0

www.vinafix.vn

8

D D

PETp0_GFXRp0(22) GFXTp0_PERp0 (22)
PETn0_GFXRn0(22)

PETp1_GFXRp1(22)
PETn1_GFXRn1(22)

PETp2_GFXRp2(22)
PETn2_GFXRn2(22)

PETp3_GFXRp3(22)
PETn3_GFXRn3(22)

PETp4_GFXRp4(22)
PETn4_GFXRn4(22)

PETp5_GFXRp5(22)
PETn5_GFXRn5(22)

PETp6_GFXRp6(22)
PETn6_GFXRn6(22)

PETp7_GFXRp7(22)
PETn7_GFXRn7(22)

PETp8_GFXRp8(22)
PETn8_GFXRn8(22)

PETp9_GFXRp9(22)
PETn9_GFXRn9(22)

PETp10_GFXRp10(22)

C C

PETn10_GFXRn10(22)
PETp11_GFXRp11(22)

PETn11_GFXRn11(22)
PETp12_GFXRp12(22)

PETn12_GFXRn12(22)
PETp13_GFXRp13(22)

PETn13_GFXRn13(22)
PETp14_GFXRp14(22)

PETn14_GFXRn14(22)
PETp15_GFXRp15(22)

PETn15_GFXRn15(22)

PCIE_REFCLKP(22)
PCIE_REFCLKN(22)

PERST#(22)

7

Place the Test Points
close to U1

TP28

TP29

TP42

TP43

TP58

TP59

ATI PN# 215RBKAGA11F

U1A

PCIE_RX0P
PCIE_RX0N

PCIE_RX1P
PCIE_RX1N

PCIE_RX2P
PCIE_RX2N

PCIE_RX3P
PCIE_RX3N

PCIE_RX4P
PCIE_RX4N

PCIE_RX5P
PCIE_RX5N

PCIE_RX6P
PCIE_RX6N

PCIE_RX7P
PCIE_RX7N

PCIE_RX8P
PCIE_RX8N

PCIE_RX9P
PCIE_RX9N

PCIE_RX10P
PCIE_RX10N

PCIE_RX11P
PCIE_RX11N

PCIE_RX12P
PCIE_RX12N

PCIE_RX13P
PCIE_RX13N

PCIE_RX14P
PCIE_RX14N

PCIE_RX15P
PCIE_RX15N

PCIE_REFCLKP
PCIE_REFCLKN

PERSTB

215RBKAGA11F

PART 1 OF 10

AU38
AU39

AT38
AR38

AR39
AP39

AP38
AN38

AM38
AM39

AL39
AL38

AK38

AJ38
AJ39

AH39
AH38

AG38
AG37

AF37
AF38

AF39
AE39

AE38
AD38

AC38
AC39

AB39
AB38

AA38

AH31
AG31

AM34

Y38
Y39

PCI
Express
Interface

6

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

PCIE_TX8P
PCIE_TX8N

PCIE_TX9P
PCIE_TX9N

PCIE_TX10P
PCIE_TX10N

PCIE_TX11P
PCIE_TX11N

PCIE_TX12P
PCIE_TX12N

PCIE_TX13P
PCIE_TX13N

PCIE_TX14P
PCIE_TX14N

PCIE_TX15P
PCIE_TX15N

PERSTb_MASK

CALRP
CALRN

5

TP32

AN36
AM36

TP33

AK34
AJ34

AK36
AJ36

AK35
AJ35

AH33
AG33

AE32
AE33

AG34
AF34

TP46

AG35
AF35

TP47

AD34
AC34

AD36
AC36

AD35
AC35

AE31
AD31

AB32
AA32

AB33
AA33

AA36
Y36

TP56

AA35
AA34

TP57

AL34

AV38

CALI

AN35
AM35

R101110K
R1009150R
R1010100R

GFXTn0_PERn0 (22)
GFXTp1_PERp1 (22)

GFXTn1_PERn1 (22)
GFXTp2_PERp2 (22)

GFXTn2_PERn2 (22)
GFXTp3_PERp3 (22)

GFXTn3_PERn3 (22)
GFXTp4_PERp4 (22)

GFXTn4_PERn4 (22)
GFXTp5_PERp5 (22)

GFXTn5_PERn5 (22)
GFXTp6_PERp6 (22)

GFXTn6_PERn6 (22)
GFXTp7_PERp7 (22)

GFXTn7_PERn7 (22)
GFXTp8_PERp8 (22)

GFXTn8_PERn8 (22)
GFXTp9_PERp9 (22)

GFXTn9_PERn9 (22)
GFXTp10_PERp10 (22)

GFXTn10_PERn10 (22)
GFXTp11_PERp11 (22)

GFXTn11_PERn11 (22)
GFXTp12_PERp12 (22)

GFXTn12_PERn12 (22)
GFXTp13_PERp13 (22)

GFXTn13_PERn13 (22)
GFXTp14_PERp14 (22)

GFXTn14_PERn14 (22)
GFXTp15_PERp15 (22)

GFXTn15_PERn15 (22)

+PCIE_VDDR_12

4

3

2

1

B B

A A

<Variant Name>

8

7

6

5

4

3

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP R480+Rialto 256MB BGA DVII DVII VIVO

Size Document Number Rev

C

Date: Sheet

2

105-A49000-00A

of

328Friday, January 28, 2005

1

0

www.vinafix.vn

8

VID[7..0]

VID[7..0](20)

D D

CLK_VIDCLK(20)

DVALID(14)
PSYNC(14)
VHAD1(20)

VHAD0(20)

VPHCTL(20)

CLK_VIPCLK(20)

DVOMODE_0(14)
DVOMODE_1(14)

DVO[11..0](19)

Install close to ASIC to provide
return path for EMI

C C

DC_Strap2(14)
DC_Strap3(14,21)
DC_Strap4(14)

PAL/NTSC(14)

DEMUX_SEL(14)

GPIO[6..0](14)
GPIO[13..8](8,14)

GPIO15(8)
ThermINT(15)

GPU_DPLUS(15)
GPU_DMINUS(15)

B B

+3.3V_BUS

B3
220R

C1522

R1625
1K

1.0uF

A A

C1523
100nF

Oscillator Circuit

4
2

8

Y3

VCC
GND

27.000MHz

3

OUT

1

E/D

DVO[11..0]

R1623 22R

DNI

R57
221R

7

C52582pF

+PVDD

GND_PVSS

+MPVDD

GND_MPVSS

R63

7

R586499R

C46

22uF_16V

221R

R66
150R

C27
22uF_16V

+3.3V_BUS

C45
100nF

+3.3V_BUS +3.3V_BUS

R51

R58

4.7K

4.7K

TP12
TP13

DVO_VSYNC(19)
DVO_HSYNC(19)
DVO_DE(19)
CLK_DVOCLK0(19)

DVO0
DVO1
DVO2
DVO3
DVO4
DVO5
DVO6
DVO7
DVO8
DVO9
DVO10
DVO11

+3.3V_BUS

R587499R

C41

C26

1.0uF

100nF

1.0uF

1.0uF

C44

C43

To Rage Theater

XTALIN

R65
0R

XTALOUT

1.0uF
C42

PVDD
PVSS

6

6

R60

4.7K

DVOMODE_0
DVOMODE_1

MPVDD
MPVSS

VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO8

GPIO9

GPIO10

GPIO11

GPIO12

GPIO13

GPIO15

XTALIN
XTALOUT

CLK_RT_XTALIN (20)

AK26
AJ26
AL24
AN25
AM23
AL23
AK23
AJ23

AM27
AL26
AK28
AJ20

AK20
AK19
AK18
AL20
AK22

AW20

AP23
AU13

AV14

AW14

AU14

AW15

AV15
AU15
AV16
AU16
AV17

AW17

AU17

AW18

AV18
AV19
AV20
AP17
AR17
AT17

AM18

AP19

AN19
AM19
AM21

AP20
AM22

AP22

AN22

AV13

AU12

AV12
AW12

AU11
AW11

AV11

AU10

AV10

AT13

AR14

AT14

AN15

AT15

AT16

AN16

AP16

AK15

AJ16

AJ17
AW36

AV36

AV37
AW37

AV9

A10
A11

5

U1B

VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
VID_6

Video Capture/

VID_7

VIP

VPCLK0
DVALID
PSYNC
VHAD_1

VHAD_0
VPHCTL
VIPCLK
SDA
SCL
DVOVMODE_0

DVOVMODE_1
ZV_LCDCNTL_0

ZV_LCDCNTL_1
ZV_LCDCNTL_2

215RBKAGA11F

ZV_LCDCNTL_3
ZV_LCDDATA_0
ZV_LCDDATA_1
ZV_LCDDATA_2
ZV_LCDDATA_3
ZV_LCDDATA_4
ZV_LCDDATA_5
ZV_LCDDATA_6
ZV_LCDDATA_7
ZV_LCDDATA_8
ZV_LCDDATA_9
ZV_LCDDATA_10
ZV_LCDDATA_11
ZV_LCDDATA_12
ZV_LCDDATA_13
ZV_LCDDATA_14
ZV_LCDDATA_15
ZV_LCDDATA_16
ZV_LCDDATA_17
ZV_LCDDATA_18
ZV_LCDDATA_19
ZV_LCDDATA_20
ZV_LCDDATA_21
ZV_LCDDATA_22
ZV_LCDDATA_23

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17

VREFG
DPLUS
DMINUS
PVDD
PVSS
MPVDD

MPVSS
XTALIN

XTALOUT

GPIO8
GPIO9
GPIO10
ROMCS#

5

PART 2 OF 10

DVO

GPIO

Thermal
Diode

Mem PLL

XTAL

TMDS

I2C

DAC1

DAC2

Hot Plug

DDC

PLL

TEST
ROM

TXCM
TXCP

TX0M

TX0P

TX1M

TX1P

TX2M

TX2P

TPVDD
TPVSS

TXVDDR_1
TXVDDR_2

TXVSSR_1
TXVSSR_2
TXVSSR_3

VSYNC
HSYNC

STEREOSYNC

AUXWIN

RSET

AVDD_1
AVDD_2

AVSSQ
AVSSN_1
AVSSN_2

VDD1DI
VSS1DI

H2SYNC

V2SYNC

COMP

R2SET

A2VDD_1
A2VDD_2

A2VSSN_1
A2VSSN_2

A2VDDQ

A2VSSQ

VDD2DI
VSS2DI

HPD1

DDC1DATA

DDC1CLK

DDC2DATA

DDC2CLK

DDC3DATA

DDC3CLK

TESTEN

ROMCSb

Test

RP193A33R

81

RP193D33R

54

RP193C33R

63

RP193B33R

72

AW23
AW24

AV24
AV25

AW26
AW27

AV27
AV28

AW21
AV22
AW29

AV30
AV29

AV26
AV23

AV33

R

AW33

G

AW32

B

AU36
AU35
AR36

AR35
AW35
AV34

AV35
AT34

AU34
AU33

AP35
AP36
AV31

R2

AU31

G2

AW30

B2

AN31
AP31

AR32

C

AT32

Y

AT31
AV32
AP28

AN28
AP29

AN29
AM28
AM29
AL29
AK29

AL16
AT36

AT35
AL17

AM16
AN32

AP32
AN33
AK13

+3.3V_BUS

R91
10K

SERIAL EEPROM 512K/1M

4

R52 499R

AVDD

GND_AVSSQ

R55 715R

1.0uF
C35

TESTEN

ROM_SO
SI/A16
SCK/WEb
CSb
HOLD1

4

GND_RSET

C7

1.0uF

DNI

GND_R2SET

B8 Bead

C34

C36

22uF_16V

100nF

R431K

+3.3V_BUS

C80
100nF

ALTERNAT IVE PART : M25P05(512Kbit)

INSTALL TERMINATION RESISTORS
CLOSE TO ASIC

R797 330R

R796 330R

R795 330R

R794 330R

1.0uF
C15

C9
22uF_16V

+AVDD

C40
100nF

C23
22uF_16V

GND_AVSSN

1.0uF

DNI

C31

+VDD_1.8V+VDD2DI

ROM_SO (23)

SI/A16 (23)
SCK/WEb (23)
CSb (23)

U11

D
C
S
HOLD
W
VCC

VSS

M25P05-AVMN6T

2

Q

4

5
6
1
7
3
8

3

C17
82pF

TXVDDR

Ba3

B5

Bead

C33
100nF

GND_A2VSSN

MU11

BIOS

113-A31901-001

3

C13
100nF

C8
82pF

+A2VDD

ROMCS#

+TPVDD

GND_TPVSS

+VDD_1.8V

C32

22uF_16V

1.0uF
C37

C16
22uF_16V

C21
100nF

1.0uF
C29

+A2VDDQ

C38
100nF

GND_A2VSSQ

<Variant Name>

R44

Rk

0R

DNI

Ba2

B4

Bead

GND_TXVSSR

+VDDDI

C30
100nF

Ba5

C39

22uF_16V

2

TXCM (18)
TXCP (18)

TX0M (18)
TX0P (18)

TX1M (18)
TX1P (18)

TX2M (18)
TX2P (18)

+VDD_1.8V

+3.3V_BUS

R50

4.7K

R_DAC1 (16)
G_DAC1 (16)
B_DAC1 (16)

VSYNC_DAC1 (14,16)
HSYNC_DAC1 (14,16)
STEREOSYNC (21)

+VDD_1.8V

B7

Bead

C28
22uF_16V

R_DAC2 (17)
G_DAC2 (17)
B_DAC2 (17)

HSYNC_DAC2 (14,17)
VSYNC_DAC2 (14,17)

C_DAC2 (21)
Y_DAC2 (21)
COMP_DAC2 (21)

+VDD_1.8V

B9

Bead

+3.3V_BUS +3.3V_BUS

R53

R54

4.7K

4.7K

HPD1 (18)

SDA (15,19)
SCL (15,19)

CRT1DDCDATA (16)
CRT1DDCCLK (16)

CRT2DDCDATA (17)
CRT2DDCCLK (17)

+3.3V_BUS

R1836
10R

JU_LED

JU2

SDA

R25 33R

SCL

R26 33R

Title
Size Document Number Rev

C

Date: Sheet

2

1
2
3
4

4x2mm

JU_LED connector in
the vicinity of Top Left
corner

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

AGP R480+Rialto 256MB BGA DVII DVII VIVO

105-A49000-00A

1

0

of

428Friday, January 28, 2005

1

www.vinafix.vn

5

4

3

2

1

U1G

A7

VDDR1_1

E1

VDDR1_2

T36

VDDR1_3

A17

VDDR1_4

A19

VDDR1_5

A22

VDDR1_6

A26

D D

+MVDDQ

C600
10nF

C70
10uf

C72
10uf

C617

C616

10nF

10nF

C C

B B

+MVDDQ

B29 220R

B30 220R

C668

1.0uF

C669

100nF

C71
10uf

C618
10nF

C73
10uf

C667

1.0uF

C601
10nF

C602
10nF

C608
10nF

C612
10nF

C619
10nF

B31 220R

C670

100nF

C613
10nF

C620
10nF

C609
10nF

C603
10nF

C666

1.0uF

C604
10nF

C610
10nF

C615

C614

10nF

10nF

C621

C622

10nF

10nF

B32 220R

C671

100nF

C611
10nF

C605
10nF

GND_VSSRH0GND_VSSRH1GND_VSSRH2GND_VSSRH3

C623
10nF

C665

1.0uF

C707

C69
1uF

100nF

C606
10nF

C708
100nF

C676
100nF

C672

100nF

C607
10nF

AM15

AM14
AH10
AH12

AG14
AG13

AE13

AW9

AW6

AL15
AL10

AF13

A29
A32

N14
K39

F8
J11
M14

AR1

AK1

AM7

AL8

G8
L14

U1
U11
AL7

H9

AK9

AG7

AK4
N13
AF8
N27

W7

L10

H8

G9
AF7
V13

W13

AA1

AD1

AF1

Y8
K11
V11

U6
T33
U33
U34
M13
L13
G20
G19
L22
L23
N29
P29
L31

M1
M12
H20
M23
N25
N26
M30
M31
N16
N17
N18
N21
N22
N23
N39

R1

Y7
U27
T27
N28
U13
U12

C38
A13

H1

AM1

D36
A14

J1

AN1

VDDR1_7
VDDR1_8
VDDR1_9
VDDR1_10
VDDR1_11
VDDR1_12
VDDR1_13
VDDR1_14
VDDR1_15
VDDR1_16
VDDR1_17
VDDR1_18
VDDR1_19
VDDR1_20
VDDR1_21
VDDR1_22
VDDR1_23
VDDR1_24
VDDR1_25
VDDR1_26
VDDR1_27
VDDR1_28
VDDR1_29
VDDR1_30
VDDR1_31
VDDR1_32

215RBKAGA11F

VDDR1_33
VDDR1_34
VDDR1_35
VDDR1_36
VDDR1_37
VDDR1_38
VDDR1_39
VDDR1_40
VDDR1_41
VDDR1_42
VDDR1_43
VDDR1_44
VDDR1_45
VDDR1_46
VDDR1_47
VDDR1_48
VDDR1_49
VDDR1_50
VDDR1_51
VDDR1_52
VDDR1_53
VDDR1_54
VDDR1_55
VDDR1_56
VDDR1_57
VDDR1_58
VDDR1_59
VDDR1_60
VDDR1_61
VDDR1_62
VDDR1_63
VDDR1_64
VDDR1_65
VDDR1_66
VDDR1_67
VDDR1_68
VDDR1_69
VDDR1_70
VDDR1_71
VDDR1_72
VDDR1_73
VDDR1_74
VDDR1_75
VDDR1_76
VDDR1_77
VDDR1_78
VDDR1_79
VDDR1_80
VDDR1_81
VDDR1_82
VDDR1_83
VDDR1_84
VDDR1_85
VDDR1_86
VDDR1_87
VDDR1_88
VDDR1_89
VDDR1_90

VDDRH_0
VDDRH_1
VDDRH_2
VDDRH_3

VSSRH_0
VSSRH_1
VSSRH_2
VSSRH_3

Memory I/O

Memory I/O
Clock Generator

PART 7 OF 10

POWER

I/O

PCIE

CORE

I/O (INTERNAL)

PCIE_VDDR_12_10

PCIE_VDDR_12_9
PCIE_VDDR_12_1
PCIE_VDDR_12_2
PCIE_VDDR_12_3
PCIE_VDDR_12_4
PCIE_VDDR_12_5
PCIE_VDDR_12_6
PCIE_VDDR_12_7
PCIE_VDDR_12_8

PCIE_PVDD_12_1
PCIE_PVDD_12_2
PCIE_PVDD_12_3
PCIE_PVDD_12_4
PCIE_PVDD_12_5

PCIE_PVDD_18_1
PCIE_PVDD_18_2
PCIE_PVDD_18_3
PCIE_PVDD_18_4
PCIE_PVDD_18_5
PCIE_PVDD_18_6
PCIE_PVDD_18_7

VDDR3_1
VDDR3_2
VDDR3_3
VDDR3_4
VDDR3_5
VDDR3_6
VDDR3_7
VDDR3_8

VDDR4_1
VDDR4_2
VDDR4_3
VDDR4_4
VDDR4_5
VDDR4_6

VDDR5_1
VDDR5_2
VDDR5_3
VDDR5_4

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32
VDDC_33
VDDC_34
VDDC_35
VDDC_36
VDDC_37

VDDCI_8
VDDCI_7
VDDCI_6
VDDCI_5
VDDCI_4
VDDCI_3
VDDCI_2
VDDCI_1

VDD15_6
VDD15_5
VDD15_4
VDD15_3

AH16
AH28
AH27
AG16
AJ28
AJ29
AH15
AJ27

AH21
AJ22
AH22
AK21
AL21
AL22

AH18
AH19
AL18
AL19

AE28
AF28
AG29
AG28
AK31
AK30
AJ30
AJ31
AF30
AF29

AD28
AC27
AC29
AD27
AC28

AB30
AA30
AA29
AB29
AB28
AA28
AB27

AC21
U19
U21
AC19
V18
V19
V20
V21
V22
W18
W19
W20
W21
W22
Y19
Y20
Y21
AA18
AA19
AA20
AA21
AA22
AB18
AB19
AB20
AB21
AB22
W17
Y18
AA17
AA23
Y22
W23
U18
U22
AC18
AC22

Y27
Y13
N20
AG20
AC20
Y23
Y17
U20

AG22
AG21
AG18
AG17

+VDDC_CT

+VDDR4

+VDDR5

change to 4210010600

C1668
10uF_6.3V

PCIE_PVDD_12

C1675
10uF_6.3V

C48

100nF

+3.3V_BUS

C49

100nF

C74

1.0uF

C75

1.0uF

C1702
10uF_6.3V

C1703
10uF_6.3V

C1704
10uF_6.3V

C632
10nF

C637
10nF

C61
10uf

C67
22uF_16V

B12 220R

B14 220R

C633
10nF

C638
10nF

C62
10uf

C50

100nF

C709

100nF

C710

100nF

+PCIE_VDDR_12

C1669
100nF

+PCIE_PVDD_12

C1673
1nF

C1676
1nF

C53
22uF_16V

C66

1.0uF

C634
10nF

C639
10nF

C1670
1nF

C1674
100nF

C624
10nF

C1677
100nF

C59
10uF_10V

C625
10nF

DNI

R69 0R

R70 0R

DNI

R67 0R

R68 0R

+PCIE_PVDD_18

C635
10nF

C640
10nF

C646
10nF

L81
60R

C636

1.0uF

C641
10nF

C63
10uF_10V

C648
10nF

C626
10nF

+3.3V_BUS

+VDD_1.8V

+3.3V_BUS

+VDD_1.8V

C56

1.0uF

C642
10nF

+VDDC

C60
10uf

C627
10nF

+PCIE_VDDR

L82
42r@100MHz

C57

1.0uF

C643
10nF

C1952
10nF

+VDDC

C673

1.0uF

C644
10nF

C1953
10nF

C1954
10nF

C1955
10nF

A A

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP R480+Rialto 256MB BGA DVII D VII VIVO

Size Document Number Rev

C

5

4

3

2

Date: Sheet

105-A49000-00A

1

0

of

528Friday, January 28, 2005

www.vinafix.vn

5

4

3

2

1

U1H

AB31
AD33
AD32
AD37
AG36
AE35
AE36
AH35
AG30
AF32

Y34

D D

C C

B B

A A

AH37
AH36
AE29
AN37
AH30
AC32
AK37
AD29
AF33

AL35

AM37

AJ33
AL37

AL32
AE34
AF36
AC30
AF27

AG32

AJ37
AC33
AH32
AH34
AF31
AD30
AB34
AC31
AB37
AC37

AL33
AB35
AB36
AE37
AA37
AE30
AA31

AE27
AR37

AT37
AP37
AN34

AL36
AK33
AK32

AJ32

AL11

AJ15

Y37

Y35

Y33

J10

R33

A16
A20
A23
A25
A28
A31

G37

D10
D13
D19
D28
D34
D35

E10
E12
E13
E18
E19
E27
E28
E33
E34
E38

H10

F13
F19

F28
H34
C34

H11
G11
G13
G14
G16
G17
G23
G33
G34
G35

V31

F25
G10

F11
H14
H17
M29
H33
H39

F10

F16

J15

PCIE_VSS_1
PCIE_VSS_2
PCIE_VSS_3
PCIE_VSS_4
PCIE_VSS_5
PCIE_VSS_6
PCIE_VSS_7
PCIE_VSS_8
PCIE_VSS_9
PCIE_VSS_10
PCIE_VSS_11
PCIE_VSS_12
PCIE_VSS_13
PCIE_VSS_14
PCIE_VSS_15
PCIE_VSS_16
PCIE_VSS_17
PCIE_VSS_18
PCIE_VSS_19
PCIE_VSS_20
PCIE_VSS_21
PCIE_VSS_22
PCIE_VSS_23
PCIE_VSS_24
PCIE_VSS_25
PCIE_VSS_26
PCIE_VSS_27
PCIE_VSS_28
PCIE_VSS_29
PCIE_VSS_30
PCIE_VSS_31
PCIE_VSS_32
PCIE_VSS_33
PCIE_VSS_34
PCIE_VSS_35
PCIE_VSS_36
PCIE_VSS_37
PCIE_VSS_38
PCIE_VSS_39
PCIE_VSS_40
PCIE_VSS_41
PCIE_VSS_42
PCIE_VSS_43
PCIE_VSS_44
PCIE_VSS_45
PCIE_VSS_46
PCIE_VSS_47
PCIE_VSS_48

PCIE_VSS_50
PCIE_VSS_51
PCIE_VSS_52
PCIE_VSS_53
PCIE_VSS_54
PCIE_VSS_55
PCIE_VSS_56
PCIE_VSS_57
PCIE_VSS_58
PCIE_VSS_59
PCIE_VSS_60

A8

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9

B3

VSS_10
VSS_11

Y6

VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20

F1

VSS_21

E4

VSS_22

E9

VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33

F4

VSS_34

F5

VSS_35

G6

VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42

G5

VSS_43

G7

VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57

H7

VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64

J5

VSS_65

K5

VSS_66

F9

VSS_67
VSS_68
VSS_69
VSS_70

215RBKAGA11F

5

PART 8 OF 10

GND

VSS_280
VSS_279
VSS_278
VSS_277
VSS_276
VSS_275
VSS_274
VSS_273
VSS_272
VSS_271
VSS_270
VSS_269
VSS_268
VSS_267
VSS_266
VSS_265
VSS_264
VSS_263
VSS_262
VSS_261
VSS_260
VSS_259
VSS_258
VSS_257
VSS_256
VSS_255
VSS_254
VSS_253
VSS_252
VSS_251
VSS_250
VSS_249
VSS_248
VSS_247
VSS_246
VSS_245
VSS_244
VSS_243
VSS_242
VSS_241
VSS_240
VSS_239
VSS_238
VSS_237
VSS_236
VSS_235
VSS_234
VSS_233
VSS_232
VSS_231
VSS_230
VSS_229
VSS_228
VSS_227
VSS_226
VSS_225
VSS_224
VSS_223
VSS_222
VSS_221
VSS_220
VSS_219
VSS_218
VSS_217
VSS_216
VSS_215
VSS_214
VSS_213
VSS_212
VSS_211
VSS_210
VSS_209
VSS_208
VSS_207
VSS_206
VSS_205
VSS_204
VSS_203
VSS_202
VSS_201
VSS_200
VSS_199
VSS_198
VSS_197
VSS_196
VSS_195
VSS_194
VSS_193
VSS_192
VSS_191
VSS_190
VSS_189
VSS_188
VSS_187
VSS_186
VSS_185
VSS_184
VSS_183
VSS_182
VSS_181
VSS_180
VSS_179
VSS_178
VSS_177
VSS_176
VSS_175
VSS_174
VSS_173
VSS_172
VSS_171
VSS_170
VSS_169
VSS_168
VSS_167
VSS_166
VSS_165
VSS_164
VSS_163
VSS_162

AL27
AH20
AK25
R35
T34
AK16
L20
AL5
AV21
AN7
AL6
AH5
AK27
AH26
AK6
AN26
AK17
AL12
U30
AM6
AK8
AG6
AG5
AG4
AR34
AJ18
AL25
AJ14
AK14
AP8
AJ8
AJ7
AJ1
AH17
AH14
AG19
AG23
AG15
AG1
AR33
AT33
AP33
J6
AU18
AP34
AE9
AE5
T35
F30
E30
K31
H31
F31
H32
AD13
AD11
AD10
AD9
AD7
AC6
AD5
AD6
E21
D22
G32
G36
AC13
AC12
AC11
AC8
AC7
AC1
E22
F22
M25
J7
AU37
AT12
H4
V23
AB23
AB13
AB9
AB5
AU32
W11
AF4
AA13
AA11
AA10
AA9
U7
W6
Y5
AA5
AJ9
AR19
Y28
AG25
AU9
Y12
Y11
U8
V7
Y1
AJ19
Y32
Y30
Y29
W35
W30
W34
W27
V35
W32
V27
AB17
V17
V1

AU27

AH23

AM33

AC17
AC23

4

J16
J24
J25
L29

N36
N35

J35

F7
K16
K25

K33
K34
K35
K36

L1

L7

L9
L11
E16
L16
L17
L25
L26
J34
L33
L39

P4

N5
M8
M7

M9
M10
M11

E15
M17
M26
M35

P5

N9

L12

J4
D16
N15
N19

J30
N24
H23
G22
U28
U29
N30
N31
N33
N34

AJ25

P1
P8

P7
P11
P12
P13
P27
P28
T29
L30

M33

P39

R4
R5
R6
R7

R9
R10
R11
R13
R27

T5
T9

T13

U17

Y31

U23

K30

H29

J29

K29
G28
H28

J28
G26
H26
D25

E25
G25

E24

J22

K22

J21

J19

K19

J18

J14

J13

K13

D7

E7
E6

U5

U1I

VSS_71

PART 9 OF 10

VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_156
VSS_158
VSS_159
VSS_160
VSS_371
VSS_372
VSS_373
VSS_374
VSS_375
VSS_376
VSS_377
VSS_378
VSS_379
VSS_380
VSS_381
VSS_382
VSS_383
VSS_384
VSS_385
VSS_386
VSS_387
VSS_388
VSS_389
VSS_390
VSS_391
VSS_392
VSS_393
VSS_394
VSS_395
VSS_396

215RBKAGA11F

VSS_363
VSS_362
VSS_361
VSS_360
VSS_359
VSS_358
VSS_357
VSS_356
VSS_355
VSS_354
VSS_353
VSS_352
VSS_351
VSS_350
VSS_349
VSS_348
VSS_347
VSS_346
VSS_345
VSS_344
VSS_343
VSS_342
VSS_341
VSS_340
VSS_339
VSS_338
VSS_337
VSS_336
VSS_335
VSS_334
VSS_333
VSS_332
VSS_331
VSS_330
VSS_329
VSS_328
VSS_327
VSS_326
VSS_325
VSS_324
VSS_323
VSS_322
VSS_321
VSS_320
VSS_319
VSS_318
VSS_317
VSS_316
VSS_315
VSS_314
VSS_313
VSS_312
VSS_311
VSS_310
VSS_309
VSS_308
VSS_307
VSS_306
VSS_305
VSS_304
VSS_303
VSS_302
VSS_301
VSS_300
VSS_299
VSS_298
VSS_297
VSS_296
VSS_295
VSS_294
VSS_293
VSS_292
VSS_291
VSS_290
VSS_289
VSS_288
VSS_287
VSS_286
VSS_285
VSS_284
VSS_283
VSS_282
VSS_281
VSS_411
VSS_410
VSS_409
VSS_408
VSS_407
VSS_406
VSS_405
VSS_404
VSS_403
VSS_402
VSS_401
VSS_400
VSS_399
VSS_398
VSS_397

AA27
W36
W37
W39
R32
D12
E36
AK24
AW8
AW5
AT6
AT1
R28
AT27
AT24
D26
AT21
F17
M20
AT11
AT7
AR8
AN5
AL4
AR31
AM26
AR28
AU24
AR25
AU21
AR22
AJ24
AR18
AR16
AR15
AP14
AR12
AR9
AT8
AR7
AP10
AP30
AP27
AN24
AP21
AP18
AP15
AN11
AP9
AR5
AR13
AN30
AH25
AN27
AN23
AM24
AU30
AN21
AN20
AN18
AN17
AJ21
AN14
AN10
AM10
AM8
AT3
AN8
AT30
AH29
AM31
AT18
AM30
AM25
AP24
AM20
AM17
L19
AM11
AN9
AP7
AL31
AL28
AK5
AK11
AJ12
AJ11
AH9
AG11
AG10
AG9
AF11
AF12
W9
V10
V9
V5
V4

+A2VDD

+VDD_1.8V

R71

4.7K

U1J

AM32

PART 10 OF 10

SSIN

AL30

NC_1

AL13

NC_2

AL14

NC_3

AP25

LPVDD

AP26

LPVSS

AH24

LVDDR_18/VDDL0_1

AG24

LVDDR_18/VDDL0_2

AG27

LVDDR_25/VDDL1_1

AG26

LVDDR_25/VDDL1_2

AR27

LVSSR_1

AR26

LVSSR_2

AR21

LVSSR_3

AR20

LVSSR_4

215RBKAGA11F

GND_MPVSS GND_TPVSS GND_RSETGND_AVSSQ

3

AR29

NC_4

AR30

NC_5

AU28

NC_6

AU29

NC_7

AT28

NC_8

AT29

NC_9

AU25

NC_10

AU26

NC_11

AT25

NC_12

AT26

NC_13

AR23

NC_14

AR24

NC_15

AU22

NC_16

AU23

NC_17

AT22

NC_18

AT23

NC_19

AU19

NC_20

AU20

NC_21

AT19

NC_22

AT20

NC_23

GND_A2VSSN

GND_A2VSSQ

NOTE: THIS IS A DRAWING. THESE GROUNDS MUST
BE MANUALLY CONNECTED TO THE GROUND PLANE

<Variant Name>

2

GND_VSSRH0

GND_TVVSSNGND_AVSSN GND_R2SET

GND_VSSRH2

GND_VSSRH1

Title
Size Document Number Rev

C

Date: Sheet

GND_P

GND_VSSRH3GND_TXVSSRGND_PVSS

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

AGP R480+Rialto 256MB BGA DVII DVII VIVO

GND_RT

GND_A GND_VIN

105-A49000-00A

1

628Friday, January 28, 2005

0

of

www.vinafix.vn

8

7

6

5

4

3

2

1

D D

OPTIONAL

CORE REGULATOR VDDC

Trace as short as possible for 2A current

*

C1151 100nF

BAT54SLT1

+5V_BUS

D28

*

ISNS1

VID4

R18581K

DNI

R1591

SW1

ISNS2

R1603

R1589

0R

HDRV1

BOOT1

HDRV2

SW2

1.00K

C1161 100nF

+5V_BUS

PGND1

BOOT2

R1590

0R

LDRV1

PGND2

12345678910111213

C C

R1632

DNI

432R

C1173

1uF

C1157

1.00K

22nf

16171819202122232425262728

DELAY

ILIM

R18521K

R18531K

DNI

7

VCORE-

FPWM

R18541K

DNI

VCORE+

VID0

R18551K

SS

PGOOD

FAN5240MTCX

VID2

VID1

R18561K

R18571K

VIN

VID3

R1860
15K

1

R1861
2K

R1593 432R

+5V_BUS

Q37
CMPT3904

2 3

R1619
0R

R1840
2K

R1602

C1160

4.7K
1nf

+5V_BUS

VID
4 3 2 1 0 +VDDC

--------------------------------­1 0 0 1 1 1.200
1 0 0 1 0 1.225
1 0 0 0 1 1.250
1 0 0 0 0 1.275
0 1 1 1 0 1.300
0 1 1 0 1 1.350
0 1 1 0 0 1.400

C1156
220nF

U43

EN AGND

14 15

R1596

41.2K

+12V_BUS

Do not install

This resistor will
be shorted in layout.

+3.3V_BUS +12V_BUS

B B

A A

R1595
243R

Q225
CMPT3904

1

R1598
221R

2 3

8

R1594

VCC

LDRV2

*

*

D29

BAT54SLT1

6

4 5
3
2
1

4 5
3
2
1

R1597

1.50K

R873 0R

10K

C1158
10uf

Q27

Thermal

Pad

FDS7096N3

Q28

Thermal

Pad

FDS7064N

DNI

+5V_BUS

C1159

0.22uF

FDS7064N

1
2
3
4 5

Pad

Thermal

Q210

FDS7096N3

1
2
3
4 5

Pad

Thermal

Q31

9

6
7
8

9

6
7
8

*

8
7
6

9

8
7
6

9

FDS7096N3

4 5
3
2
1

Q29

4 5
3
2
1

FDS7064N

R1592432R

1
2
3
4 5

1
2
3
4 5

Q232

Thermal

Pad

9

6
7
8

Q231

Thermal

Pad

9

6
7
8

***

VDDC_PGOOD (2)

FDS7064N

Pad

Thermal

Q224

Pad

Thermal

FDS7096N3

OPTIONAL

5

8
7
6

9

8
7
6

9

VIN

C1692

C1688

100nF

10uF

L63 1.71uH

1 2

R1851

2.2R

C1706
1nF

R1617
0R

DNI

PADS SHORTED IN
LAYOUT

R1618
0R

DNI

PADS SHORTED IN
LAYOUT

L64

1 2

R1859

2.2R

CHANGE TO 1.5uH 23A
VISHAY IHLP5050EZRZ1R5M01

C1707
1nF

VIN

CHANGE TO 1.5uH 23A
VISHAY IHLP5050EZRZ1R5M01

1.71uH

C1689
10uF

C1532
33uF_16V

4

C1690
10uF

C1152
1500uF

C1691
10uF

C1153
1500uF

+12VEXT

B79
60R

B78

60R

C1154
1500uF

+VDDC

C167

180uF_16V

C1155
1500uF

3

C1951
1500uF

C1948
330uF_2.5V

OPTIONAL

<Variant Name>

C1949
330uF_2.5V

C1950
330uF_2.5V

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP R480+Rialto 256MB BGA DVII DVII VIVO

Size Document Number Rev

C

Date: Sheet

2

105-A49000-00A

of

728Friday, January 28, 2005

1

0

www.vinafix.vn

8

7

6

5

4

3

2

1

+12V_BUS

+5V_BUS

DNI

R372

R373

0R

2R2

D4

BAT54SLT1

C142
1uF

DNI

DNI

C136

0.22uF

C141
22nf

D D

Alternative 1

+PW_VDDC1
SS_VDDC1
COMP_VDDC1
Fb_VDDC1

C C

+12V_BUS

+5V_BUS

DNI

R371

R370

2R2

0R

D5

BAT54SLT1

R112

DNI

0R

R314 0R

C158

0.22uF

DNI

C157
1uF

C169
22nf

B B

Alternative 1

R305 51K

+PW_VDDC2

R306 3K

SS_VDDC2
COMP_VDDC2
Fb_VDDC2

A A

8

MVDDQ Switching Regulator for
Memory Core for 256M
configuration

BST1

R376
0R

R251 0R

SS_VDDC1

Fb_VDDC1
COMP_VDDC1

UVIN1
SWN1

Alternative 2

R258 51K
R259 3K

MVDDC Switching Regulator for
Memory Core for 256M
configuration

BST2

SS_VDDC2

Fb_VDDC2
COMP_VDDC2

UVIN2
SWN2

Alternative 2

U31

DNI

7

SS

4

Vfb

5

COMP

6

UVIN

8

SWN

SP6132

SIPEX SP6132

R257 10K

MU31

2

OCSET

3

SS

4

COMP

5

FB

6

EN

7

GND

ISL6522CB

ISL6522CB : SOIC
ISL6522CV : TSSOP

BOOT_VDDC2

U32

DNI

7

BST

SS

GH

4

Vfb

5

GND

COMP

6

GL

UVIN

8

Vcc

SWN

SP6132

SIPEX SP6132

R307 10K

MU32

2

OCSET

3

SS

4

COMP

5

FB

6

EN

7

GND

ISL6522CB

ISL6522CB : SOIC
ISL6522CV : TSSOP

BOOT_VDDC1

BST

GH

GND

GL

Vcc

LGATE

UGATE
PHASE

10
9
3
2
1

VCCRT

PVCC

LGATE

PGND

BOOT
UGATE
PHASE

10
9
3
2
1

VCCRT

PVCC
PGND

BOOT

BST2

MVDDC_UGATE

MVDDC_LGATE

MVDDC_VCC

141
13
12
11
10
9
8

7

BST1
MVDDQ_UGATE

M<VDDQ_LGATE
MVDDQ_VCC

141
13
12
11

BOOT_VDDC1

10
9
8

BOOT_VDDC2

C122 100nF

+12V_BUS

C121 100nF

+12V_BUS

SWN1

4 5
3
2
1

4 5
3
2
1

IRF7413ATR (2020005600)

C113
1uF

SWN2

R255

2.2R

Q23

4 5
3
2
1

IRF7413A

Q24

4 5
3
2
1

IRF7413A

Fb_VDDC2

IRF7413ATR (2020005600)

R308

C160

2.2R
C159
1uF

1nF

EXTERNAL POWER DETECT

GPIO8(4,14)

PCIETEST(22)

GPIO15(4)

R910 0R

DNI

R909 0R

Q21

IRF7413A

Q22

IRF7413A

Fb_VDDC1

C116
1nF

R874 0R

DNI

6

6
7
8

6
7
8

6
7
8

6
7
8

MMBT3906

C1678

C1679

10uF

100nF

L65

1.5uH

C110
1nf

R254

1.5K

C1683

100nF

L66

1.5uH

C161
1nf

Cc1 Cout1

R309

1.5K

Rc4

+5V_BUS

Q233

10uF

***

Rc1

Cc1

R253

***

1.87K

1%

Rc4

Rc2

R256

1.24K

1%

+PW_VDDC2 UVIN2

C1681

C1682

10uF

10uF

***

Rc1

R310

***

1.87K

1%

+MVDDC = REF * (1+Rc1/Rc2)

Rc2

R311

1.24K

1%

23

1

R1567
0R

C1132

1nf
R917
562R

R918

1.0K

5

+PW_VDDC1

C1680

+5VEXT

+5V_BUS

B21

B76
60R

60R

DNI

***

C106
330uF_2.5V

C105
330uF_2.5V

Cout1

***

+MVDDQ = REF * (1+Rc1/Rc2)

+5VEXT

+5V_BUS

B28
60R

DNI

330uF_2.5V

***

C164

C165
330uF_2.5V

***

+5VEXT

R1565
1K

+MVDDQ

B77
60R

+MVDDC

Connector_4_Pin

J1

R377

DNI

63.4K

C104
330uF_2.5V

C163

180uF_16V

R374

DNI

220K

R375
100K

DNI

C166
330uF_2.5V

+12VEXT +12V_BUS

4
3
2
1

C1167

J1

10uF

UVIN1

R378
100K

DNI

+5VEXT +5V_BUS

C1169

2.2uF

ONLY THROUGH
JU1 PINS 2 AND 3.

4

C1170
10uF

D41

S3AB

D38

S3AB

+5VEXT

F

21

21

C1171

10uF_25V

R1685 0R
R1686 0R

External Power

R250
2K

R249

2.4K

1

Q9

CMPT3904

+12V_BUS

R248
20K

CMPT3904

2 3

SS_VDDC1

1

2 3

Q10

+MVDDC

POWER SEQUENCING CIRCUIT:

R1849
1K

R1850

2.4K

+12VEXT

C1168
10uF_25V

1

Q228

CMPT3904

+12V_BUS

R1848
20K

CMPT3904

2 3

<Variant Name>

SS_VDDC2

1

2 3

Q227

+VDDC

3

DESIGN NOTES:POWER SEQUENCING CIRCUIT:

Add this Capacitor for SP6132

COMP_VDDC1

C140

DNI

2.2nF

Compensation Circuit

COMP_VDDC1

C111

Cc3

Rc5

C112
10nF

33pF

R264
15K

Fb_VDDC1

Cc2

FOR ALTERNATE #2

Change C142 for 10uF
Change C122 for 1uF
Replace R251 with a bead
Swap Rc4 with Cc1

DESIGN NOTES:

Add this Capacitor for SP6132

Compensation Circuit

Cc2

Cc4

COMP_VDDC2

C171
10nF

Rc5

COMP_VDDC2

C168
100pF

C170
33pF

R313
15K

DNI

Cc3

Fb_VDDC2

FOR ALTERNATE #2

Change C157 for 10 uF
Change C121 for 1 uF
Replace C764 by 0 Ohm resistor
Remove R954
Replace R314 with a bead
Swap Rc4 with Cc1

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP R480+Rialto 256MB BGA DVII DVII VIVO

Size Document Number Rev

C

Date: Sheet

2

105-A49000-00A

of

828Friday, January 28, 2005

1

0

www.vinafix.vn

8

7

6

5

4

3

2

1

+1.8V Regulator for analog power supplies

C134
22uF_16V

+3.3V_BUS

B23
60R

C135
100nF

REG2
LT1117CST

3 2

IN OUT

CASE

ADJ

1

+VDD_1.8V

C132

R129

1.50K

1%

R126
681R

1%

C131
100nF

22uF_16V

4

D D

+1.5V Regulator for VDDC_ C T (VDD15)

+3.3V_BUS

C129
22uF_16V

B47
60R

3 2

C130
100nF

REG7
LT1117CST

IN OUT

ADJ

1

CASE

+VDDC_CT

4

R171

1.0K

1%

R170
200R

1%

C127
100nF

C128
22uF_16V

Max 400 mA if all 1.8 V analog power supplies are connected

REGULATOR
FOR
MPVDD(+1.8V)

75R

+MPVDD+TPVDD

REG5

4

SC431LC5SK-1

NC

1

NC

2

5 3

GND_MPVSSGND_TPVSS

+3.3V_BUS

C1619
47uF

C185
22uF_6.3V

+B_VDDC

3

6

MREG34

1 5

IN VOUT

TAB

VCNTL

4 2

REFEN GND

RT9173ACL5

C991

1.0uF

RT9173ACL5, TO-252-5, 3A, (2480025000)
Alt. SS6383BCE5, TO-252-5, 3A

R1872
1K

402

C186
68uF_6.3V

LOW ESR

Note: Put copper under MREG33 for heat dissipation.

GND

VOUT

BYPASS

BLM21A121SPT

1

REGULATOR
FOR
A2VDD(+2.5V)

5

4

C147
470pF

DNI

+PVDD

B66

R1781

1.0K

R1783
2K

32

Q215

2N7002LT1

B25 200R

+A2VDD

1uF
C146

+3.3V_BUS

C1618
47uF

REG12

1 5

IN VOUT

4 2

REFEN GND

RT9173ACL5

C975

1.0uF

Place 250 sq. mm (2cmx1.25cm) Copper Area under REG12,

Note:

Use Vias to Direct Heat into the Large Copper Area on the Bottom Layer.
The Heat Sink Copper Area should be Solder-Painted without Masked.

R139

R140

AS432S

681R

1%

1

MREG4

R141

DNI DNI DNI

1.50K

3 2

1%

3

6

TAB

VCNTL

RT9173ACL5, TO-252-5, 3A, (2480025000)
Alt. SS6383BCE5, TO-252-5, 3A

+3.3V_BUS

B24

C C

B B

200R

REG3

1

VIN

1uF

3

SHDN

C145

2.5V

2

GND_A2VSSN GND_A2VSSN

Regulator for PCIE_VDDR
Vout = 1.2V
Iout = 2400mA

R1797

1.5K

R1799

2.4K

CMPT3904

+3.3V_BUS

Q216

1

R1795
20K

R1798 100R

2 3

+PCIE_PVDD_18

REGULATOR
FOR PVDD
(+1.8V)

+PVDD

33R

REG4

4

SC431LC5SK-1

NC

1

NC

2

5 3

GND_PVSS

+PCIE_VDDR

R1843
1K

402

C1705
330uF_2.5V

+3.3V_BUS+3.3V_BUS +3.3V_BUS

B27 200R

R143

R145

AS432S

681R

1%

1

MREG6

R147

1.50K

3 2

1%

C1700
22uF_6.3V

REGULATOR
FOR TPVDD
(+1.8V)

33R

REG6

4

SC431LC5SK-1

NC

1

NC

2

5 3

Regulator for B_VDDC
Vout = 1.2V
Iout = 1000mA MAX

+PCIE_VDDR_12

R509

1.5K

Rq5

Rq6

R508

2.4K

DNI

CMPT3904

Q163

1

+3.3V_BUS

2 3

R507
20K

402

B26 200R

R142

R144

AS432S

681R

1%

1

R146

MREG5

1.50K

3 2

1%

+PCIE_PVDD_18

B67
220R

R1871

1.0K

Rc1

R1873
2K

Rc2

1

Q164

2 3

CMPT3904

+B_VDDC Rc1 Rc2

1.2V

1.3V

1.4V

Regulator for PCIE_PVDD_18
Vout = 1.8V
Iout = 800mA MAX

+3.3V_BUS

B70
42r@100MHz

A A

C1665
22uF_6.3V

Put copper under REG10 for heat dissipation.

Use SPX2810AM3, ADJ, 1A, SOT223, DO<1.2V (2480041400 ) $0.11

Alt. LX8117B-00CST, ADJ, 1.2A, SOT-223, DO<1.3V (2480041100)

Alt. FAN1117AS, ADJ, 1A, SOT-223, DO<1.2V (2480041000, PL9)

Alt. FAN1117AS-1.8V, 1A, SOT-223, DO<1.2V (2480020000, PL4), $0.13
Alt. LX8117A-00CST, ADJ, 1A, SOT-223, DO<1.3V (2480002100, PL1), $0.25
Alt. AP1117, ADJ, 1A, SOT-223, DO<1.4V, Use +5V_BUS Input Only, $0.10

8

REG11
LT1117CST

3 2

IN OUT

ADJ

C1666
100nF

1

7

CASE

C1714
10uF_6.3V

+PCIE_PVDD_18

4

R1792
121R

1%

R1793

53.6R

1%

* R1792, 3160121000, 121R, 1%, 402
R1793, 316053R600, 53.6R, 1%, 402

C997
22uF_6.3V

+VDD_1.8V

C996
47uF

6.3v
ESR 0.25ohm

L83
120R

DNI

6

C996 can use 4231068600,
CAP TANT 68UF 6.3V 20%
LOW ESR B CASE

<Variant Name>

5

4

3

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP R480+Rialto 256MB BGA DVII DVII VIVO

Size Document Number Rev

C

Date: Sheet

2

105-A49000-00A

of

928Friday, January 28, 2005

1

0

www.vinafix.vn

5

4

3

2

1

R423 MEMORY CHANNELS A and B

D D

MAA[13..0]

MAA[13..0](12)

MDA[63..0]

MDA[63..0](12)

C C

+MVDDQ

B B

R137

40.2R

R138
100R

C149
100nF

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

W38

V37
V38
U37
T39
T38
R37
R38

W33

V34
V36
V32
U36
T32
R36
R34
P37
P38
N37
N38
L38
K37
K38
J37
P34
P35
P36

M34

L35

J36
H35
H36
P30
P31
P32
P33

J33
K32

J32

J31
V28
V29

W31

T30
R31
R30
R29

T28

F36

F35
E35
D33
E32
D32
G31
D31
M28

L28
K28
M27

J27

J26
K26
H25

W29
W28

U1C

DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31

215RBKAGA11F

DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63

MVREFD_0
MVREFS_0

Part 3 of 10

Memory
Channel A

MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8

MAA_9
MAA_10
MAA_11
MAA_12
MAA_13
MAA_14

DQMAb_0
DQMAb_1
DQMAb_2
DQMAb_3
DQMAb_4
DQMAb_5
DQMAb_6
DQMAb_7

QSA_0B
QSA_1B
QSA_2B
QSA_3B
QSA_4B
QSA_5B
QSA_6B
QSA_7B

QSA_0
QSA_1
QSA_2
QSA_3
QSA_4
QSA_5
QSA_6
QSA_7

RASAb

CASAb

WEAb

CSAb_0
CSAb_1

CKEA

CLKA0

CLKA0b

CLKA1

CLKA1b

MAA0

B34

MAA1

B35

MAA2

A34

MAA3

B33

MAA4

J38

MAA5

H38

MAA6

G39

MAA7

H37

MAA8

F38

MAA9

G38

MAA10

A35

MAA11

B36

MAA12

A37

MAA13

E39
D38

DQMA#0

T37

DQMA#1

U35

DQMA#2

M37

DQMA#3

L34

DQMA#4

N32

DQMA#5

V30

DQMA#6

F32

DQMA#7

H27

QSA#0

U39

QSA#1

U32

QSA#2

M38

QSA#3

L36

QSA#4

M32

QSA#5

U31

QSA#6

F33

QSA#7

L27

QSA0

U38

QSA1

V33

QSA2

L37

QSA3

M36

QSA4

L32

QSA5

T31

QSA6

F34

QSA7

K27

RASA#

B37

CASA#

C37

WEA#

C39

CSA#0

D39
F37

CKEA

B38

D37
E37

C35
C36

DQMA#[7..0] (12)

QSA#[7..0] (12)

QSA[7..0] (12)

RASA# (12)
CASA# (12)
WEA# (12)
CSA#0 (12)

CKEA (12)

CLKA0 (12)
CLKA#0 (12)

CLKA1 (12)
CLKA#1 (12)

+MVDDQ

R158

40.2R

R159
100R

MAB[13..0](12)

MDB[63..0](12)

C151
100nF

MAB[13..0]

MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41

C33

B32

C32

B31
B29

C29

B28
C28
G30
H30
G29

F29

F27

E26
D27

F26

B27
C27

B26
C26
C24

B23
C23

B22
M24

L24

K24
M22

L21
M21

J20

K20
H24

F24
D24
G24

F21

F23
G21
H22
H21
H19

F20

E20
G18
H18

E17
D17
M19

K18

L18
M18

L15
M16
M15

K14

F15
G15
H16
H15

F12
G12
H13
H12

D30

E31

U1D

DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31

215RBKAGA11F

DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63

MVREFD_1
MVREFS_1

Part 4 of 10

Memory
Channel B

MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8

MAB_9
MAB_10
MAB_11
MAB_12
MAB_13
MAB_14

DQMBb_0
DQMBb_1
DQMBb_2
DQMBb_3
DQMBb_4
DQMBb_5
DQMBb_6
DQMBb_7

QSB_0B
QSB_1B
QSB_2B
QSB_3B
QSB_4B
QSB_5B
QSB_6B
QSB_7B

QSB_0

QSB_1

QSB_2

QSB_3

QSB_4

QSB_5

QSB_6

QSB_7

RASBb

CASBb

WEBb

CSBb_0
CSBb_1

CKEB

CLKB0
CLKB0b

CLKB1
CLKB1b

MAB0

B12

MAB1

B13

MAB2

C13

MAB3

C12

MAB4

C22

MAB5

C21

MAB6

B20

MAB7

B21

MAB8

B19

MAB9

C20

MAB10

C14

MAB11

B14

MAB12

B15

MAB13

B18
C17

DQMB#0

C30

DQMB#1

G27

DQMB#2

B25

DQMB#3

K21

DQMB#4

E23

DQMB#5

D20

DQMB#6

K15

DQMB#7

D9

QSB#0

C31

QSB#1

D29

QSB#2

B24

QSB#3

K23

QSB#4

D21

QSB#5

F18

QSB#6

J17

QSB#7

D11

QSB0

B30

QSB1

E29

QSB2

C25

QSB3

J23

QSB4

D23

QSB5

D18

QSB6

K17

QSB7

E11

RASB#

C15

CASB#

C16

WEB#

B17

CSB#0

C18
C19

CKEB

B16

D15
D14

F14
E14

DQMB#[7..0] (12)

QSB#[7..0] (12)

QSB[7..0] (12)

RASB# (12)
CASB# (12)
WEB# (12)
CSB#0 (12)

CKEB (12)

CLKB0 (12)
CLKB#0 (12)

CLKB1 (12)
CLKB#1 (12)

+MVDDQ

R148

40.2R

R149

C148
100nF

100R

A A

5

4

3

+MVDDQ

R150

40.2R

R151
100R

C150
100nF

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP R480+Rialto 256MB BGA DVII DVII VIVO

Size Document Number Rev

C

2

Date: Sheet

105-A49000-00A

1

0

of

10 28Friday, January 28, 2005

www.vinafix.vn

5

4

3

2

1

R-420 MEMORY CHANNELS C and D

D D

C156
100nF

MAD[13..0]

MDD0
MDD1
MDD2
MDD3
MDD4
MDD5
MDD6
MDD7
MDD8
MDD9
MDD10
MDD11
MDD12
MDD13
MDD14
MDD15
MDD16
MDD17
MDD18
MDD19
MDD20
MDD21
MDD22
MDD23
MDD24
MDD25
MDD26
MDD27
MDD28
MDD29
MDD30
MDD31
MDD32
MDD33
MDD34
MDD35
MDD36
MDD37
MDD38
MDD39
MDD40
MDD41
MDD42
MDD43
MDD44
MDD45
MDD46
MDD47
MDD48
MDD49
MDD50
MDD51
MDD52
MDD53
MDD54
MDD55
MDD56
MDD57
MDD58
MDD59
MDD60
MDD61
MDD62
MDD63

AA12
AB10

AB11
AD12
AE12
AE11
AE10

AF10
AG12
AH11
AK10

AJ10

AK12

AJ13

AM12
AM13
AN13
AN12
AP11
AT10
AR10

AA2
AA3
AB2
AB3
AD3
AE2
AE3
AF2
AB8
AB6
AB7
AD8
AE6
AE7
AE4
AE8

AF3
AG2
AG3
AH2
AK2
AK3

AL2

AL3
AG8
AF6
AF5
AH8

AJ6

AJ5

AJ4
AK7

Y9

AF9

AN6
AP6
AP5
AR6
AU4
AU5
AU6
AU7

AT9

Y10
W10

U1F

DQD_0
DQD_1
DQD_2
DQD_3
DQD_4
DQD_5
DQD_6
DQD_7
DQD_8
DQD_9
DQD_10
DQD_11
DQD_12
DQD_13
DQD_14
DQD_15
DQD_16
DQD_17
DQD_18
DQD_19
DQD_20
DQD_21
DQD_22
DQD_23
DQD_24
DQD_25
DQD_26
DQD_27
DQD_28
DQD_29
DQD_30
DQD_31

215RBKAGA11F

DQD_32
DQD_33
DQD_34
DQD_35
DQD_36
DQD_37
DQD_38
DQD_39
DQD_40
DQD_41
DQD_42
DQD_43
DQD_44
DQD_45
DQD_46
DQD_47
DQD_48
DQD_49
DQD_50
DQD_51
DQD_52
DQD_53
DQD_54
DQD_55
DQD_56
DQD_57
DQD_58
DQD_59
DQD_60
DQD_61
DQD_62
DQD_63

MVREFD_3
MVREFS_3

Part 6 of 10

Memory
Channel D

MAD_0
MAD_1
MAD_2
MAD_3
MAD_4
MAD_5
MAD_6
MAD_7
MAD_8

MAD_9
MAD_10
MAD_11
MAD_12
MAD_13
MAD_14

DQMDb_0
DQMDb_1
DQMDb_2
DQMDb_3
DQMDb_4
DQMDb_5
DQMDb_6
DQMDb_7

QSD_0B
QSD_1B
QSD_2B
QSD_3B
QSD_4B
QSD_5B
QSD_6B
QSD_7B

QSD_0

QSD_1

QSD_2

QSD_3

QSD_4

QSD_5

QSD_6

QSD_7

RASDb

CASDb

WEDb

CSDb_0
CSDb_1

CKED

CLKD0

CLKD0b

CLKD1

CLKD1b

DRAM_RST
TEST_MCLK
TEST_YCLK

MEMTEST

AU8
AV6
AV7
AV8
AM2
AN2
AN3
AM3
AP3
AP2
AV5
AV4
AV3
AR3
AU2

AD2
AD4
AH3
AH4
AB12
AH13
AT5
AP13

AC2
AC5
AJ3
AH7
AC10
AL9
AT4
AP12

AC3
AC4
AJ2
AH6
AC9
AM9
AR4
AR11

AW3
AV2
AU1
AT2

AR2
AU3

AM4
AM5

AP4
AN4

B11
J12
K12
C11

MAD0
MAD1
MAD2
MAD3
MAD4
MAD5
MAD6
MAD7
MAD8
MAD9
MAD10
MAD11
MAD12
MAD13

DQMD#0
DQMD#1
DQMD#2
DQMD#3
DQMD#4
DQMD#5
DQMD#6
DQMD#7

QSD#0
QSD#1
QSD#2
QSD#3
QSD#4
QSD#5
QSD#6
QSD#7

QSD0
QSD1
QSD2
QSD3
QSD4
QSD5
QSD6
QSD7

RASD#
CASD#
WED#
CSD#0

CKED

RESET
TEST_MCLK
TEST_YCLK

R166
243R

R156

4.7K

DQMD#[7..0] (13)

QSD#[7..0] (13)

QSD[7..0] (13)

CLKD0 (13)
CLKD#0 (13)

CLKD1 (13)
CLKD#1 (13)

R157

4.7K

RASD# (13)
CASD# (13)
WED# (13)
CSD#0 (13)

CKED (13)

RESET (12,13)

R163

4.7K

DNI

+MVDDQ

+MVDDQ

R161

40.2R

R162
100R

R154

40.2R

R155
100R

MAD[13..0](13)

MDD[63..0](13)

C155
100nF

C154
100nF

C153
100nF

MAC[13..0]

MDC0
MDC1
MDC2
MDC3
MDC4
MDC5
MDC6
MDC7
MDC8
MDC9
MDC10
MDC11
MDC12
MDC13
MDC14
MDC15
MDC16
MDC17
MDC18
MDC19
MDC20
MDC21
MDC22
MDC23
MDC24
MDC25
MDC26
MDC27
MDC28
MDC29
MDC30
MDC31
MDC32
MDC33
MDC34
MDC35
MDC36
MDC37
MDC38
MDC39
MDC40
MDC41
MDC42
MDC43
MDC44
MDC45
MDC46
MDC47
MDC48
MDC49
MDC50
MDC51
MDC52
MDC53
MDC54
MDC55
MDC56
MDC57
MDC58
MDC59
MDC60
MDC61
MDC62
MDC63

B10
C10

B9
C9
C7

B6
C6

B5
D8

E8
D6

F6

E5
D4
C4
G4

A5
C5

A4

B4
C2
C3
D2
D3

K10

J9

J8

K9

K6

L6
M6

L5
N8
N7
M5
N6

T4

T8

T6
U4

N10
P10

P9

R12
U10

U9

V12

W12

R3

T2

T3
U2
W2
W3

Y2

Y3

V6

V8
W8
W4

AA4
AB4
AA7
AA8

N11
N12

U1E

DQC_0
DQC_1
DQC_2
DQC_3
DQC_4
DQC_5
DQC_6
DQC_7
DQC_8
DQC_9
DQC_10
DQC_11
DQC_12
DQC_13
DQC_14
DQC_15
DQC_16
DQC_17
DQC_18
DQC_19
DQC_20
DQC_21
DQC_22
DQC_23
DQC_24
DQC_25
DQC_26
DQC_27
DQC_28
DQC_29
DQC_30
DQC_31

215RBKAGA11F

DQC_32
DQC_33
DQC_34
DQC_35
DQC_36
DQC_37
DQC_38
DQC_39
DQC_40
DQC_41
DQC_42
DQC_43
DQC_44
DQC_45
DQC_46
DQC_47
DQC_48
DQC_49
DQC_50
DQC_51
DQC_52
DQC_53
DQC_54
DQC_55
DQC_56
DQC_57
DQC_58
DQC_59
DQC_60
DQC_61
DQC_62
DQC_63

MVREFD_2
MVREFS_2

Part 5 of 10

Memory
Channel C

MAC_0
MAC_1
MAC_2
MAC_3
MAC_4
MAC_5
MAC_6
MAC_7
MAC_8

MAC_9
MAC_10
MAC_11
MAC_12
MAC_13
MAC_14

DQMCb_0
DQMCb_1
DQMCb_2
DQMCb_3
DQMCb_4
DQMCb_5
DQMCb_6
DQMCb_7

QSC_0B
QSC_1B
QSC_2B
QSC_3B
QSC_4B
QSC_5B
QSC_6B
QSC_7B

QSC_0

QSC_1

QSC_2

QSC_3

QSC_4

QSC_5

QSC_6

QSC_7

RASCb

CASCb

WECb

CSCb_0
CSCb_1

CKEC

CLKC0
CLKC0b

CLKC1
CLKC1b

MAC0

P3

MAC1

N3

MAC2

P2

MAC3

R2

MAC4

E2

MAC5

F2

MAC6

F3

MAC7

E3

MAC8

G3

MAC9

G2

MAC10

N2

MAC11

M3

MAC12

L3

MAC13

H3
K2

DQMC#0

B7

DQMC#1

D5

DQMC#2

A3

DQMC#3

L8

DQMC#4

P6

DQMC#5

T12

DQMC#6

V3

DQMC#7

AA6

QSC#0

B8

QSC#1

H5

QSC#2

C1

QSC#3

K7

QSC#4

R8

QSC#5

T11

QSC#6

V2

QSC#7

Y4

QSC0

C8

QSC1

H6

QSC2

B2

QSC3

K8

QSC4

T7

QSC5

T10

QSC6

U3

QSC7

W5

RASC#

M2

CASC#

L2

WEC#

J3

CSC#0

J2
H2

CKEC

K3

L4
K4

N4
M4

DQMC#[7..0] (13)

QSC#[7..0] (13)

QSC[7..0] (13)

RASC# (13)
CASC# (13)
WEC# (13)
CSC#0 (13)

CKEC (13)

CLKC0 (13)
CLKC#0 (13)

CLKC1 (13)
CLKC#1 (13)

MAC[13..0](13)

MDC[63..0](13)

C C

+MVDDQ

R160

+MVDDQ

40.2R

R133
100R

R153

40.2R

R152
100R

B B

A A

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP R480+Rialto 256MB BGA DVII DVII VIVO

Size Document Number Rev

C

5

4

3

2

Date: Sheet

105-A49000-00A

1

0

of

11 28Friday, January 28, 2005

www.vinafix.vn

5

256 Mbit GDDRIII Channels A and B

MDA[63..0](10)

MAA[13..0](10)

D D

WEA#(10)
CASA#(10)
RASA#(10)

RESET(11,13)

CSA#0(10)

CKEA(10)
CLKA0(10)

CLKA1(10)
CLKA#0(10)
CLKA#1(10)

DQMA#[7..0](10)

C C

B B

+MVDDQ

+MVDDC

A A

QSA[7..0](10)

CLKA0(10)

CLKA#0(10)

CLKA1(10)

CLKA#1(10)

C1845

C1844

100nF

100nF

C1876

C1877

1nF

1nF

C1909

C1908

100nF

100nF

C1933

C1932

1nF

1nF

C1846
100nF

C1878
1nF

C1910
100nF

C1934
1nF

R315

2.37K

R316

5.49K

R27460.4R

R27560.4R

R27660.4R

R27860.4R

+MVDDQ

C1847
100nF

C1879
1nF

C1911
100nF

C1935
1nF

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

CASA#
RASA#
RESET
CSA#0

CKEA
CLKA0
CLKA1
CLKA#0
CLKA#1

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

MDA[63..0]

+MVDDQ

+MVDDQ

R277

2.37K

R281

5.49K

C199
100nF

C1848
100nF

C1880
1nF

+MVDDQ

C1849
100nF

C1881
1nF

MAA13
MAA12

MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

RESET RESET RESET RESETWEA#

CLKA#0
CLKA0

CKEA

CSA#0

WEA#
RASA#
CASA#

DQMA#0
DQMA#2
DQMA#3
DQMA#1

QSA#0
QSA#2
QSA#3
QSA#1

QSA0
QSA2
QSA3
QSA1

R938 243R

C208
100nF

C1850
100nF

C1882
1nF

C1924
10uf

C1851
100nF

C1883
1nF

+MVDDQ+MVDDC

U52

M9
M4

M3

L3

L10
M10
M12
M11

L11

K11

K2

L2
M2
M1

L5

M7
M6

L6

L9
M8

L4
M5

B11

H2

H11

B2

A12

G1

G12

A1

A11

G2

G11

A2

E5

E6

E7

E8

F5

F6

F7

F8
G5
G6
G7
G8
H5
H6
H7
H8

K8

K5
D2

D11

L7

L8

L1

L12

HYB18T256321F-2.0

C1925
10uf

BA1
BA0

A11
A10
A9
A8/AP
A7
A6
A5
A4
A3
A2
A1
A0

RESET

CK
CK

CKE

CS
WE
RAS
CAS

DM3
DM2
DM1
DM0

WDQS3
WDQS2
WDQS1
WDQS0

RDQS3
RDQS2
RDQS1
RDQS0

NC/VSS
NC/VSS#E6
NC/VSS#E7
NC/VSS#E8
NC/VSS#F5
NC/VSS#F6
NC/VSS#F7
NC/VSS#F8
NC/VSS#G5
NC/VSS#G6
NC/VSS#G7
NC/VSS#G8
NC/VSS#H5
NC/VSS#H6
NC/VSS#H7
NC/VSS#H8

RFU1
RFU2
RFU3
RFU4
RFU5

ZQ

VREF

VREF#L12

VDDQ#B4
VDDQ#B6
VDDQ#B7
VDDQ#B9

VDDQ#B10

VDDQ#G3

VDDQ#G10

VDDQ#E3

VDDQ#E10

VDDQ#F3

VDDQ#F10

VDDQ#H3

VDDQ#H10

VDDQ#J3

VDDQ#J10

VDD#D10

VDD#K10

VSSQ#C3
VSSQ#C4
VSSQ#C5
VSSQ#C8
VSSQ#C9

VSSQ#C10

VSSQ#D5
VSSQ#D8
VSSQ#E9
VSSQ#F4
VSSQ#F9
VSSQ#G4
VSSQ#G9
VSSQ#H4
VSSQ#H9
VSSQ#J4
VSSQ#J9
VSSQ#A3

VSSQ#A10

+MVDDQ

+MVDDC

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ

VDD#C7
VDD#D3

VDD#K3
VDD#K6
VDD#K7

VSSQ

VSS#D6
VSS#D7
VSS#D9

VSS#J5
VSS#J6
VSS#J7

VSS#J8
VSS#K4
VSS#K9

A7
B8
A8
A9
B12
C11
C12
D12
K1
J2
J1
H1
F1
F2
E1
E2
E11
E12
F11
F12
H12
J12
J11

DQ9

K12

DQ8

D1

DQ7

C1

DQ6

C2

DQ5

B1

DQ4

A4

DQ3

A5

DQ2

B5

DQ1

A6

DQ0

B3
B4
B6
B7
B9
B10
G3
G10
E3
E10
F3
F10
H3
H10
J3
J10
C6

VDD

C7
D3
D10
K3
K6
K7
K10

E4
C3
C4
C5
C8
C9
C10
D5
D8
E9
F4
F9
G4
G9
H4
H9
J4
J9
A3
A10
D4

VSS

D6
D7
D9
J5
J6
J7
J8
K4
K9

C1852
100nF

C1884
1nF

C1912
100nF

C1936
1nF

4

Channel A Channel B

CLKA#1
CLKA1

CKEA

CSA#0

WEA#
RASA#
CASA#

C1858
100nF

C1890
1nF

C1926
10uf

U53

M9

BA1

M4

BA0

M3

A11

L3

A10

L10

A9

M10

A8/AP

M12

A7

M11

A6

L11

A5

K11

A4

K2

A3

L2

A2

M2

A1

M1

A0

L5

RESET

M7

CK

M6

CK

L6

CKE

L9

CS

M8

WE

L4

RAS

M5

CAS

B11

DM3

H2

DM2

H11

DM1

B2

DM0

A12

WDQS3

G1

WDQS2

G12

WDQS1

A1

WDQS0

A11

RDQS3

G2

RDQS2

G11

RDQS1

A2

RDQS0

E5

NC/VSS

E6

NC/VSS#E6

E7

NC/VSS#E7

E8

NC/VSS#E8

F5

NC/VSS#F5

F6

NC/VSS#F6

F7

NC/VSS#F7

F8

NC/VSS#F8

G5

NC/VSS#G5

G6

NC/VSS#G6

G7

NC/VSS#G7

G8

NC/VSS#G8

H5

NC/VSS#H5

H6

NC/VSS#H6

H7

NC/VSS#H7

H8

NC/VSS#H8

K8

RFU1

K5

RFU2

D2

RFU3

D11

RFU4

L7

RFU5

L8

ZQ

L1

VREF

L12

VREF#L12

HYB18T256321F-2.0

C1859
100nF

C1891
1nF

+MVDDQ+MVDDC

C1927
10uf

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ
VDDQ#B4
VDDQ#B6
VDDQ#B7
VDDQ#B9

VDDQ#B10

VDDQ#G3

VDDQ#G10

VDDQ#E3

VDDQ#E10

VDDQ#F3

VDDQ#F10

VDDQ#H3

VDDQ#H10

VDDQ#J3

VDDQ#J10

VDD#C7
VDD#D3

VDD#D10

VDD#K3
VDD#K6
VDD#K7

VDD#K10

VSSQ
VSSQ#C3
VSSQ#C4
VSSQ#C5
VSSQ#C8
VSSQ#C9

VSSQ#C10

VSSQ#D5
VSSQ#D8
VSSQ#E9
VSSQ#F4
VSSQ#F9

VSSQ#G4
VSSQ#G9

VSSQ#H4
VSSQ#H9
VSSQ#J4
VSSQ#J9
VSSQ#A3

VSSQ#A10

VSS#D6
VSS#D7
VSS#D9

VSS#J5
VSS#J6
VSS#J7

VSS#J8
VSS#K4
VSS#K9

A7
B8
A8
A9
B12
C11
C12
D12
K1
J2
J1
H1
F1
F2
E1
E2
E11
E12
F11
F12
H12
J12
J11

DQ9

K12

DQ8

D1

DQ7

C1

DQ6

C2

DQ5

B1

DQ4

A4

DQ3

A5

DQ2

B5

DQ1

A6

DQ0

B3
B4
B6
B7
B9
B10
G3
G10
E3
E10
F3
F10
H3
H10
J3
J10
C6

VDD

C7
D3
D10
K3
K6
K7
K10

E4
C3
C4
C5
C8
C9
C10
D5
D8
E9
F4
F9
G4
G9
H4
H9
J4
J9
A3
A10
D4

VSS

D6
D7
D9
J5
J6
J7
J8
K4
K9

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA23 MDA48
MDA22
MDA21
MDA20
MDA17
MDA19
MDA16
MDA18
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA15
MDA14
MDA13
MDA12
MDA11
MDA10
MDA9
MDA8

+MVDDQ

+MVDDC

R270

2.37K

R271

5.49K

+MVDDQ

R317

2.37K

R318

5.49K

C1854
100nF

C1886
1nF

C1914
100nF

C1938
1nF

C1855
100nF

C1887
1nF

C1915
100nF

C1939
1nF

C1853
100nF

C1885
1nF

C1913
100nF

C1937
1nF

MAA13
MAA12

MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

DQMA#4
DQMA#6
DQMA#5
DQMA#7

QSA#4
QSA#6
QSA#5
QSA#7

QSA4
QSA6
QSA5
QSA7

+MVDDQ +MVDDQ

R939 243R

C200
100nF

C198
100nF

C1856

C1857

100nF

100nF

C1888

C1889

1nF

1nF

MDA39
MDA38
MDA37
MDA36
MDA35
MDA34
MDA33
MDA32

MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA47
MDA46
MDA45
MDA44
MDA43
MDA42
MDA41
MDA40
MDA56
MDA57
MDA58
MDA59
MDA61
MDA60
MDA63
MDA62

+MVDDQ

+MVDDC

3

R319

2.37K

R320

5.49K

R26060.4R

R26160.4R

R26260.4R

R26360.4R

+MVDDQ

C1861
100nF

C1893
1nF

C1917
100nF

C1941
1nF

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7

+MVDDQ

+MVDDQ

C1862
100nF

C1894
1nF

C1918
100nF

C1942
1nF

MDB[63..0]

WEB#
CASB#
RASB#
CSB#0

CKEB
CLKB0
CLKB1
CLKB#0
CLKB#1

C197
100nF

R279

2.37K

R283

5.49K

C1863
100nF

C1895
1nF

C1919
100nF

C1943
1nF

+MVDDQ

C1864
100nF

C1896
1nF

C210
100nF

MAB13
MAB12

MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0

CLKB#0
CLKB0

CKEB

CSB#0

WEB#
RASB#
CASB#

DQMB#0
DQMB#2
DQMB#3
DQMB#1

QSB#0
QSB#2
QSB#3
QSB#1

QSB0
QSB2
QSB3
QSB1

R940 243R

C1865
100nF

C1897
1nF

MDB[63..0](10)

MAB[13..0](10)

WEB#(10)
CASB#(10)
RASB#(10)

CSB#0(10)

CKEB(10)
CLKB0(10)

CLKB1(10)
CLKB#0(10)
CLKB#1(10)

DQMB#[7..0](10)

QSB#[7..0](10)QSA#[7..0](10)

QSB[7..0](10)

CLKB0(10)

CLKB#0(10)

CLKB1(10)

CLKB#1(10)

+MVDDQ

C1860
100nF

C1892
1nF

+MVDDC

C1916
100nF

C1940
1nF

C1866
100nF

C1898
1nF

C1928
10uf

M9
M4

M3

L3
L10
M10
M12
M11
L11
K11

K2

L2

M2
M1

L5

M7
M6

L6

L9

M8

L4

M5

B11

H2

H11

B2

A12

G1

G12

A1

A11

G2

G11

A2

E5

E6

E7

E8

F5

F6

F7

F8

G5
G6
G7
G8
H5
H6
H7
H8

K8

K5

D2

D11

L7

L8

L1

L12

2

U54

BA1
BA0

A11
A10
A9
A8/AP
A7
A6
A5
A4
A3
A2
A1
A0

RESET

CK
CK

CKE

CS
WE
RAS
CAS

DM3
DM2
DM1
DM0

WDQS3
WDQS2
WDQS1
WDQS0

RDQS3
RDQS2
RDQS1
RDQS0

NC/VSS
NC/VSS#E6
NC/VSS#E7
NC/VSS#E8
NC/VSS#F5
NC/VSS#F6
NC/VSS#F7
NC/VSS#F8
NC/VSS#G5
NC/VSS#G6
NC/VSS#G7
NC/VSS#G8
NC/VSS#H5
NC/VSS#H6
NC/VSS#H7
NC/VSS#H8

RFU1
RFU2
RFU3
RFU4
RFU5

ZQ

VREF

VREF#L12

HYB18T256321F-2.0

C1867
100nF

C1899
1nF

+MVDDQ+MVDDC

C1929
10uf

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ
VDDQ#B4
VDDQ#B6
VDDQ#B7
VDDQ#B9

VDDQ#B10

VDDQ#G3

VDDQ#G10

VDDQ#E3

VDDQ#E10

VDDQ#F3

VDDQ#F10

VDDQ#H3

VDDQ#H10

VDDQ#J3

VDDQ#J10

VDD#C7
VDD#D3

VDD#D10

VDD#K3
VDD#K6
VDD#K7

VDD#K10

VSSQ
VSSQ#C3
VSSQ#C4
VSSQ#C5
VSSQ#C8
VSSQ#C9

VSSQ#C10

VSSQ#D5
VSSQ#D8
VSSQ#E9
VSSQ#F4
VSSQ#F9
VSSQ#G4
VSSQ#G9
VSSQ#H4
VSSQ#H9

VSSQ#J4
VSSQ#J9

VSSQ#A3

VSSQ#A10

VSS#D6
VSS#D7
VSS#D9

VSS#J5
VSS#J6
VSS#J7

VSS#J8
VSS#K4
VSS#K9

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDD

VSS

+MVDDQ

+MVDDC

MDB0

A7

MDB1

B8

MDB2

A8

MDB3

A9

MDB4

B12

MDB5

C11

MDB6

C12

MDB7

D12

MDB20

K1

MDB21

J2

MDB23

J1

MDB22

H1

MDB18

F1

MDB19

F2

MDB16

E1

MDB17

E2

MDB24

E11

MDB25

E12

MDB26

F11

MDB27

F12

MDB28

H12

MDB29

J12

MDB31

J11

MDB30

K12

MDB15

D1

MDB13

C1

MDB14

C2

MDB12

B1

MDB11

A4

MDB10

A5

MDB8

B5

MDB9

A6
B3

B4
B6
B7
B9

+MVDDQ

B10
G3
G10
E3
E10
F3
F10
H3
H10
J3
J10
C6

+MVDDC

C7
D3
D10
K3
K6
K7
K10

E4
C3
C4
C5
C8
C9
C10
D5
D8
E9
F4
F9
G4
G9
H4
H9
J4
J9
A3
A10
D4
D6
D7
D9
J5
J6
J7
J8
K4
K9

+MVDDQ

R321

2.37K

R322

5.49K

C1868
100nF

C1900
1nF

C1920
100nF

C1944
1nF

C1869
100nF

C1901
1nF

C1921
100nF

C1945
1nF

R272

2.37K

R273

5.49K

C196
100nF

C1870
100nF

C1902
1nF

C1922
100nF

C1946
1nF

C201
100nF

C1871
100nF

C1903
1nF

C1923
100nF

C1947
1nF

MAB13
MAB12

MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0

CLKB#1
CLKB1

CKEB

CSB#0

WEB#
RASB#
CASB#

DQMB#5
DQMB#4
DQMB#7
DQMB#6

QSB#5
QSB#4
QSB#7
QSB#6

QSB5
QSB4
QSB7
QSB6

R941 243R

C1872
100nF

C1904
1nF

U55

M9
M4

M3

L3

L10
M10
M12
M11

L11
K11

K2

L2
M2
M1

L5

M7
M6

L6

L9
M8

L4
M5

B11

H2

H11

B2

A12

G1

G12

A1

A11

G2

G11

A2

E5

E6

E7

E8

F5

F6

F7

F8
G5
G6
G7
G8
H5
H6
H7
H8

K8

K5
D2

D11

L7

L8

L1

L12

HYB18T256321F-2.0

C1873
100nF

C1905
1nF

1

BA1
BA0

A11
A10
A9
A8/AP
A7
A6
A5
A4
A3
A2
A1
A0

RESET

CK
CK

CKE

CS
WE
RAS
CAS

DM3
DM2
DM1
DM0

WDQS3
WDQS2
WDQS1
WDQS0

RDQS3
RDQS2
RDQS1
RDQS0

NC/VSS
NC/VSS#E6
NC/VSS#E7
NC/VSS#E8
NC/VSS#F5
NC/VSS#F6
NC/VSS#F7
NC/VSS#F8
NC/VSS#G5
NC/VSS#G6
NC/VSS#G7
NC/VSS#G8
NC/VSS#H5
NC/VSS#H6
NC/VSS#H7
NC/VSS#H8

RFU1
RFU2
RFU3
RFU4
RFU5

ZQ

VREF

VREF#L12

C1874
100nF

C1906
1nF

C1930
10uf

VDDQ#B4
VDDQ#B6
VDDQ#B7
VDDQ#B9

VDDQ#B10

VDDQ#G3

VDDQ#G10

VDDQ#E3

VDDQ#E10

VDDQ#F3

VDDQ#F10

VDDQ#H3

VDDQ#H10

VDDQ#J3

VDDQ#J10

VDD#D10

VDD#K10

VSSQ#C3
VSSQ#C4
VSSQ#C5
VSSQ#C8
VSSQ#C9

VSSQ#C10

VSSQ#D5
VSSQ#D8

VSSQ#E9
VSSQ#F4

VSSQ#F9
VSSQ#G4
VSSQ#G9
VSSQ#H4
VSSQ#H9

VSSQ#J4

VSSQ#J9

VSSQ#A3

VSSQ#A10

C1875
100nF

C1907
1nF

+MVDDQ+MVDDC

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ

VDD#C7
VDD#D3

VDD#K3
VDD#K6
VDD#K7

VSSQ

VSS#D6
VSS#D7
VSS#D9

VSS#J5
VSS#J6
VSS#J7

VSS#J8
VSS#K4
VSS#K9

C1931
10uf

MDB45

A7

MDB46

B8

MDB44

A8

MDB47

A9

MDB42

B12

MDB41

C11

MDB40

C12

MDB43

D12

MDB32

K1

MDB35

J2

MDB33

J1

MDB34

H1

MDB36

F1

MDB37

F2

MDB39

E1

MDB38

E2

MDB61

E11

MDB63

E12

MDB62

F11

MDB60

F12

MDB59

H12

MDB56

J12

MDB57

J11

DQ9

MDB58

K12

DQ8

MDB55

D1

DQ7

MDB54

C1

DQ6

MDB53

C2

DQ5

MDB52

B1

DQ4

MDB51

A4

DQ3

MDB50

A5

DQ2

MDB49

B5

DQ1

MDB48

A6

DQ0

B3
B4
B6
B7
B9

+MVDDQ

B10
G3
G10
E3
E10
F3
F10
H3
H10
J3
J10
C6

VDD

VSS

+MVDDC

C7
D3
D10
K3
K6
K7
K10

E4
C3
C4
C5
C8
C9
C10
D5
D8
E9
F4
F9
G4
G9
H4
H9
J4
J9
A3
A10
D4
D6
D7
D9
J5
J6
J7
J8
K4
K9

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP R480+Rialto 256MB BGA DVII DVII VIVO

Size Document Number Rev

C

5

4

3

2

Date: Sheet

105-A49000-00A

1

0

of

12 28Friday, January 28, 2005

www.vinafix.vn

5

256 Mbit GDDRIII Channels A and B Channel C Channel D

MDC[63..0](11)
MAC[13..0](11)

D D

WEC#(11)
CASC#(11)
RASC#(11) RASD#(11)

RESET(11,12)

CSC#0(11)

CKEC(11)
CLKC0(11)

CLKC1(11)
CLKC#0(11)
CLKC#1(11)

DQMC#[7..0](11)

QSC#[7..0](11)

C C

B B

+MVDDQ

+MVDDC

A A

QSC[7..0](11)

CLKC0(11)

CLKC#0(11)

CLKC1(11)

CLKC#1(11)

C1725

C1724

100nF

100nF

C1756

C1757

1nF

1nF

C1788

C1789

100nF

100nF

C1813

C1812

1nF

1nF

C1726
100nF

C1758
1nF

C1790
100nF

C1814
1nF

R323

2.37K

R324

5.49K

R29660.4R

R29760.4R

R29860.4R

R29960.4R

+MVDDQ

C1727
100nF

C1759
1nF

C1791
100nF

C1815
1nF

5

MAC0
MAC1
MAC2
MAC3
MAC4
MAC5
MAC6
MAC7
MAC8
MAC9
MAC10
MAC11
MAC12
MAC13

WEC#
CASC#
RASC#
RESET
CSC#0

CKEC
CLKC0
CLKC1
CLKC#0

DQMC#0
DQMC#1
DQMC#2
DQMC#3
DQMC#4
DQMC#5
DQMC#6
DQMC#7

QSC#0
QSC#1
QSC#2
QSC#3
QSC#4
QSC#5
QSC#6
QSC#7

QSC0
QSC1
QSC2
QSC3
QSC4
QSC5
QSC6
QSC7

+MVDDQ

+MVDDQ

MDC[63..0]

R285

2.37K

R289

5.49K

C195
100nF

C1728
100nF

C1760
1nF

+MVDDQ

C1729
100nF

C1761
1nF

MAC13
MAC12

MAC11
MAC10
MAC9
MAC8
MAC7
MAC6
MAC5
MAC4
MAC3
MAC2
MAC1
MAC0

RESET

CLKC#0
CLKC0

CKEC

CSC#0

WEC#
RASC#
CASC#

DQMC#0
DQMC#3
DQMC#1
DQMC#2

QSC#0
QSC#3
QSC#1
QSC#2

QSC0
QSC3
QSC1
QSC2

R934 243R

C256
100nF

C1730
100nF

C1762
1nF

C1804
10uf

C1731
100nF

C1763
1nF

+MVDDQ+MVDDC

U56

M9
M4

M3

L3

L10
M10
M12
M11

L11

K11

K2

L2
M2
M1

L5

M7
M6

L6

L9
M8

L4
M5

B11

H2

H11

B2

A12

G1

G12

A1

A11

G2

G11

A2

E5

E6

E7

E8

F5

F6

F7

F8
G5
G6
G7
G8
H5
H6
H7
H8

K8

K5
D2

D11

L7

L8

L1

L12

HYB18T256321F-2.0

C1805
10uf

BA1
BA0

A11
A10
A9
A8/AP
A7
A6
A5
A4
A3
A2
A1
A0

RESET

CK
CK

CKE

CS
WE
RAS
CAS

DM3
DM2
DM1
DM0

WDQS3
WDQS2
WDQS1
WDQS0

RDQS3
RDQS2
RDQS1
RDQS0

NC/VSS
NC/VSS#E6
NC/VSS#E7
NC/VSS#E8
NC/VSS#F5
NC/VSS#F6
NC/VSS#F7
NC/VSS#F8
NC/VSS#G5
NC/VSS#G6
NC/VSS#G7
NC/VSS#G8
NC/VSS#H5
NC/VSS#H6
NC/VSS#H7
NC/VSS#H8

RFU1
RFU2
RFU3
RFU4
RFU5

ZQ

VREF

VREF#L12

VDDQ#B4
VDDQ#B6
VDDQ#B7
VDDQ#B9

VDDQ#B10

VDDQ#G3

VDDQ#G10

VDDQ#E3

VDDQ#E10

VDDQ#F3

VDDQ#F10

VDDQ#H3

VDDQ#H10

VDDQ#J3

VDDQ#J10

VDD#D10

VDD#K10

VSSQ#C3
VSSQ#C4
VSSQ#C5
VSSQ#C8
VSSQ#C9

VSSQ#C10

VSSQ#D5
VSSQ#D8

VSSQ#E9
VSSQ#F4

VSSQ#F9
VSSQ#G4
VSSQ#G9
VSSQ#H4
VSSQ#H9

VSSQ#J4

VSSQ#J9

VSSQ#A3

VSSQ#A10

+MVDDQ

+MVDDC

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ

VDD#C7
VDD#D3

VDD#K3
VDD#K6
VDD#K7

VSSQ

VSS#D6
VSS#D7
VSS#D9
VSS#J5
VSS#J6
VSS#J7
VSS#J8
VSS#K4
VSS#K9

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDD

VSS

C1732
100nF

C1764
1nF

C1792
100nF

C1816
1nF

4

RESET

CLKC#1
CLKC1

CKEC

CSC#0

WEC#
RASC#
CASC#

C1738
100nF

C1770
1nF

C1806
10uf

U57

M9

BA1

M4

BA0

M3

A11

L3

A10

L10

A9

M10

A8/AP

M12

A7

M11

A6

L11

A5

K11

A4

K2

A3

L2

A2

M2

A1

M1

A0

L5

RESET

M7

CK

M6

CK

L6

CKE

L9

CS

M8

WE

L4

RAS

M5

CAS

B11

DM3

H2

DM2

H11

DM1

B2

DM0

A12

WDQS3

G1

WDQS2

G12

WDQS1

A1

WDQS0

A11

RDQS3

G2

RDQS2

G11

RDQS1

A2

RDQS0

E5

NC/VSS

E6

NC/VSS#E6

E7

NC/VSS#E7

E8

NC/VSS#E8

F5

NC/VSS#F5

F6

NC/VSS#F6

F7

NC/VSS#F7

F8

NC/VSS#F8

G5

NC/VSS#G5

G6

NC/VSS#G6

G7

NC/VSS#G7

G8

NC/VSS#G8

H5

NC/VSS#H5

H6

NC/VSS#H6

H7

NC/VSS#H7

H8

NC/VSS#H8

K8

RFU1

K5

RFU2

D2

RFU3

D11

RFU4

L7

RFU5

L8

ZQ

L1

VREF

L12

VREF#L12

HYB18T256321F-2.0

C1739
100nF

C1771
1nF

+MVDDQ+MVDDC

C1807
10uf

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ
VDDQ#B4
VDDQ#B6
VDDQ#B7
VDDQ#B9

VDDQ#B10

VDDQ#G3

VDDQ#G10

VDDQ#E3

VDDQ#E10

VDDQ#F3

VDDQ#F10

VDDQ#H3

VDDQ#H10

VDDQ#J3

VDDQ#J10

VDD#C7
VDD#D3

VDD#D10

VDD#K3
VDD#K6
VDD#K7

VDD#K10

VSSQ
VSSQ#C3
VSSQ#C4
VSSQ#C5
VSSQ#C8
VSSQ#C9

VSSQ#C10

VSSQ#D5
VSSQ#D8
VSSQ#E9
VSSQ#F4
VSSQ#F9

VSSQ#G4
VSSQ#G9

VSSQ#H4
VSSQ#H9
VSSQ#J4
VSSQ#J9
VSSQ#A3

VSSQ#A10

VSS#D6
VSS#D7
VSS#D9

VSS#J5
VSS#J6
VSS#J7

VSS#J8
VSS#K4
VSS#K9

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDD

VSS

MDC0

A7

MDC1

B8

MDC2

A8

MDC3

A9

MDC4

B12

MDC5

C11

MDC6

C12

MDC7

D12

MDC31

K1

MDC30

J2

MDC29

J1

MDC28

H1

MDC27

F1

MDC26

F2

MDC24

E1

MDC25

E2

MDC8

E11

MDC9

E12

MDC10

F11

MDC11

F12

MDC14

H12

MDC13

J12

MDC12

J11

MDC15

K12

MDC22

D1

MDC23

C1

MDC20

C2

MDC21

B1

MDC19

A4

MDC17

A5

MDC18

B5

MDC16

A6
B3

B4
B6
B7
B9
B10
G3
G10
E3
E10
F3
F10
H3
H10
J3
J10
C6
C7
D3
D10
K3
K6
K7
K10

E4
C3
C4
C5
C8
C9
C10
D5
D8
E9
F4
F9
G4
G9
H4
H9
J4
J9
A3
A10
D4
D6
D7
D9
J5
J6
J7
J8
K4
K9

C1733
100nF

C1765
1nF

C1793
100nF

C1817
1nF

R325

2.37K

R326

5.49K

+MVDDQ

C1734
100nF

C1766
1nF

C1794
100nF

C1818
1nF

4

R292

2.37K

R293

5.49K

+MVDDQ

C194
100nF

C1735
100nF

C1767
1nF

C1795
100nF

C1819
1nF

R300

C1736
100nF

C1768
1nF

C308
100nF

MAC13
MAC12

MAC11
MAC10
MAC9
MAC8
MAC7
MAC6
MAC5
MAC4
MAC3
MAC2
MAC1
MAC0

DQMC#7
DQMC#5
DQMC#6
DQMC#4

QSC#7
QSC#5
QSC#6
QSC#4

QSC7
QSC5
QSC6
QSC4

R935 243R

C1737
100nF

C1769
1nF

3

60.4R

R327

2.37K

R328

5.49K

+MVDDQ

C1740
100nF

C1772
1nF

C1796
100nF

C1820
1nF

MAD0
MAD1
MAD2
MAD3
MAD4
MAD5
MAD6
MAD7
MAD8
MAD9
MAD10
MAD11
MAD12
MAD13

DQMD#0
DQMD#1
DQMD#2
DQMD#3
DQMD#4
DQMD#5
DQMD#6
DQMD#7

QSD#0
QSD#1
QSD#2
QSD#3
QSD#4
QSD#5
QSD#6
QSD#7

QSD0
QSD1
QSD2
QSD3
QSD4
QSD5
QSD6
QSD7

C1741
100nF

C1773
1nF

C1797
100nF

C1821
1nF

MDD[63..0]

WED#
CASD#
RASD#
CSD#0

CKED
CLKD0
CLKD1
CLKD#0
CLKD#1

R30160.4R

R30260.4R

R30360.4R

C193
100nF

C1742
100nF

C1774
1nF

C1798
100nF

C1822
1nF

+MVDDQ

+MVDDQ

+MVDDQ

R291

5.49K

R288

2.37K

C1743
100nF

C1775
1nF

C1799
100nF

C1823
1nF

C257
100nF

MAD13
MAD12

MAD11
MAD10
MAD9
MAD8
MAD7
MAD6
MAD5
MAD4
MAD3

MAD1
MAD0

C1744
100nF

C1776
1nF

RESET

CLKD#0
CLKD0

CKED

CSD#0

WED#
RASD#
CASD#

DQMD#0
DQMD#3
DQMD#2
DQMD#1

QSD#0
QSD#3
QSD#2
QSD#1

QSD0
QSD3
QSD2
QSD1

R936 243R

MDD[63..0](11)

+MVDDQ

+MVDDC+MVDDC

3

MAD[13..0](11)

WED#(11)
CASD#(11)

CSD#0(11)

CKED(11)
CLKD0(11)

CLKD1(11)
CLKD#0(11)
CLKD#1(11)

DQMD#[7..0](11)

QSD#[7..0](11)

QSD[7..0](11)

CLKD0(11)

CLKD#0(11)

CLKD1(11)

CLKD#1(11)

+MVDDQ

+MVDDC

MDC63

A7

MDC61

B8

MDC62

A8

MDC60

A9

MDC58

B12

MDC59

C11

MDC56

C12

MDC57

D12

MDC42

K1

MDC40

J2

MDC43

J1

MDC41

H1

MDC46

F1

MDC44

F2

MDC47

E1

MDC45

E2

MDC55

E11

MDC54

E12

MDC53

F11

MDC52

F12

MDC51

H12

MDC50

J12

MDC49

J11

MDC48

K12

MDC39

D1

MDC38

C1

MDC37

C2

MDC36

B1

MDC35

A4

MDC34

A5

MDC33

B5

MDC32

A6
B3

B4
B6
B7
B9
B10
G3
G10
E3
E10
F3
F10
H3
H10
J3
J10
C6
C7
D3
D10
K3
K6
K7
K10

E4
C3
C4
C5
C8
C9
C10
D5
D8
E9
F4
F9
G4
G9
H4
H9
J4
J9
A3
A10
D4
D6
D7
D9
J5
J6
J7
J8
K4
K9

C1745
100nF

C1777
1nF

U58

M9

BA1

M4

BA0

M3

A11

L3

A10

L10

A9

M10

A8/AP

M12

A7

M11

A6

L11

A5

K11

A4

K2

A3

L2

A2

M2

A1

M1

A0

L5

RESET

M7

CK

M6

CK

L6

CKE

L9

CS

M8

WE

L4

RAS

M5

CAS

B11

DM3

H2

DM2

H11

DM1

B2

DM0

A12

WDQS3

G1

WDQS2

G12

WDQS1

A1

WDQS0

A11

RDQS3

G2

RDQS2

G11

RDQS1

A2

RDQS0

E5

NC/VSS

E6

NC/VSS#E6

E7

NC/VSS#E7

E8

NC/VSS#E8

F5

NC/VSS#F5

F6

NC/VSS#F6

F7

NC/VSS#F7

F8

NC/VSS#F8

G5

NC/VSS#G5

G6

NC/VSS#G6

G7

NC/VSS#G7

G8

NC/VSS#G8

H5

NC/VSS#H5

H6

NC/VSS#H6

H7

NC/VSS#H7

H8

NC/VSS#H8

K8

RFU1

K5

RFU2

D2

RFU3

D11

RFU4

L7

RFU5

L8

ZQ

L1

VREF

L12

VREF#L12

HYB18T256321F-2.0

C1746
100nF

C1778
1nF

C1808
10uf

2

MDD0

A7

DQ31

MDD1

B8

DQ30

MDD2

A8

DQ29

MDD3

A9

DQ28

MDD4

B12

DQ27

MDD5

C11

DQ26

MDD6

C12

DQ25

MDD7

D12

DQ24

MDD29

K1

DQ23

MDD31

J2

DQ22

MDD28

J1

DQ21

MDD30

H1

DQ20

MDD27

F1

DQ19

MDD25

F2

DQ18

MDD24

E1

DQ17

MDD26

E2

DQ16

MDD16

E11

DQ15

MDD17

E12

DQ14

MDD18

F11

DQ13

MDD19

F12

DQ12

MDD20

H12

DQ11

MDD21

J12

DQ10

MDD23

J11

DQ9

MDD22

K12

DQ8

MDD15

D1

DQ7

MDD14

C1

DQ6

MDD13

C2

DQ5

MDD12

B1

DQ4

MDD10

A4

DQ3

MDD8

A5

DQ2

MDD11

B5

DQ1

MDD9

A6

DQ0

B3

VDDQ

B4

VDDQ#B4

B6

VDDQ#B6

B7

VDDQ#B7

B9

VDDQ#B9

VDDQ#B10

VDDQ#G3

VDDQ#G10

VDDQ#E3

VDDQ#E10

VDDQ#F3

VDDQ#F10

VDDQ#H3

VDDQ#H10

VDDQ#J3

VDDQ#J10

VDD
VDD#C7
VDD#D3

VDD#D10

VDD#K3
VDD#K6
VDD#K7

VDD#K10

VSSQ
VSSQ#C3
VSSQ#C4
VSSQ#C5
VSSQ#C8
VSSQ#C9

VSSQ#C10

VSSQ#D5
VSSQ#D8
VSSQ#E9
VSSQ#F4
VSSQ#F9
VSSQ#G4
VSSQ#G9
VSSQ#H4
VSSQ#H9

VSSQ#J4
VSSQ#J9

VSSQ#A3

VSSQ#A10

VSS
VSS#D6
VSS#D7
VSS#D9

VSS#J5
VSS#J6
VSS#J7

VSS#J8
VSS#K4
VSS#K9

C1747
100nF

C1779
1nF

+MVDDQ+MVDDC

C1809
10uf

2

B10
G3
G10
E3
E10
F3
F10
H3
H10
J3
J10
C6
C7
D3
D10
K3
K6
K7
K10

E4
C3
C4
C5
C8
C9
C10
D5
D8
E9
F4
F9
G4
G9
H4
H9
J4
J9
A3
A10
D4
D6
D7
D9
J5
J6
J7
J8
K4
K9

+MVDDQ

+MVDDC

<Variant Name>

R329

2.37K

R330

5.49K

+MVDDQ

+MVDDC

+MVDDQ

C1748
100nF

C1780
1nF

C1800
100nF

C1824
1nF

R294

2.37K

R295

5.49K

MAD13
MAD12

MAD11
MAD10
MAD9
MAD8
MAD7
MAD6
MAD5
MAD4
MAD3
MAD2
MAD1
MAD0

RESET

CLKD#1
CLKD1

CKED

CSD#0

WED#
RASD#
CASD#

DQMD#4
DQMD#7
DQMD#5
DQMD#6

QSD#4
QSD#7
QSD#5
QSD#6

QSD4
QSD7
QSD5
QSD6

+MVDDQ

C1749
100nF

C1781
1nF

C1801
100nF

C1825
1nF

R937 243R

C309
100nF

C192
100nF

C1751

C1750
100nF

C1782
1nF

C1802
100nF

C1826
1nF

C1752

100nF

100nF

C1784

C1783

1nF

1nF

C1803
100nF

C1827
1nF

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP R480+Rialto 256MB BGA DVII DVII VIVO

Size Document Number Rev

C

Date: Sheet

U59

M9

BA1

M4

BA0

M3

A11

L3

A10

L10

A9

M10

A8/AP

M12

A7

M11

A6

L11

A5

K11

A4

K2

A3

L2

A2

M2

A1

M1

A0

L5

RESET

M7

CK

M6

CK

L6

CKE

L9

CS

M8

WE

L4

RAS

M5

CAS

B11

DM3

H2

DM2

H11

DM1

B2

DM0

A12

WDQS3

G1

WDQS2

G12

WDQS1

A1

WDQS0

A11

RDQS3

G2

RDQS2

G11

RDQS1

A2

RDQS0

E5

NC/VSS

E6

NC/VSS#E6

E7

NC/VSS#E7

E8

NC/VSS#E8

F5

NC/VSS#F5

F6

NC/VSS#F6

F7

NC/VSS#F7

F8

NC/VSS#F8

G5

NC/VSS#G5

G6

NC/VSS#G6

G7

NC/VSS#G7

G8

NC/VSS#G8

H5

NC/VSS#H5

H6

NC/VSS#H6

H7

NC/VSS#H7

H8

NC/VSS#H8

K8

RFU1

K5

RFU2

D2

RFU3

D11

RFU4

L7

RFU5

L8

ZQ

L1

VREF

L12

VREF#L12

HYB18T256321F-2.0

C1753
100nF

C1785
1nF

105-A49000-00A

1

C1754
100nF

C1786
1nF

C1810
10uf

1

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ
VDDQ#B4
VDDQ#B6
VDDQ#B7
VDDQ#B9

VDDQ#B10

VDDQ#G3

VDDQ#G10

VDDQ#E3

VDDQ#E10

VDDQ#F3

VDDQ#F10

VDDQ#H3

VDDQ#H10

VDDQ#J3

VDDQ#J10

VDD#C7
VDD#D3

VDD#D10

VDD#K3
VDD#K6
VDD#K7

VDD#K10

VSSQ
VSSQ#C3
VSSQ#C4
VSSQ#C5
VSSQ#C8
VSSQ#C9

VSSQ#C10

VSSQ#D5
VSSQ#D8

VSSQ#E9
VSSQ#F4

VSSQ#F9
VSSQ#G4
VSSQ#G9
VSSQ#H4
VSSQ#H9

VSSQ#J4

VSSQ#J9

VSSQ#A3

VSSQ#A10

VSS#D6
VSS#D7
VSS#D9

VSS#J5
VSS#J6
VSS#J7

VSS#J8
VSS#K4
VSS#K9

C1755
100nF

C1787
1nF

+MVDDQ+MVDDC

MDD39

A7

MDD38

B8

MDD37

A8

MDD36

A9

MDD35

B12

MDD34

C11

MDD33

C12

MDD32

D12

MDD62

K1

MDD63

J2

MDD60

J1

MDD61

H1

MDD58MAD2

F1

MDD59

F2

MDD56

E1

MDD57

E2

MDD46

E11

MDD47

E12

MDD44

F11

MDD45

F12

MDD43

H12

MDD42

J12

MDD41

J11

DQ9

MDD40

K12

DQ8

MDD55

D1

DQ7

MDD54

C1

DQ6

MDD53

C2

DQ5

MDD52CLKC#1

B1

DQ4

MDD51

A4

DQ3

MDD50

A5

DQ2

MDD49

B5

DQ1

MDD48

A6

DQ0

B3
B4
B6
B7
B9

+MVDDQ+MVDDQ

B10
G3
G10
E3
E10
F3
F10
H3
H10
J3
J10
C6

VDD

VSS

C1811
10uf

+MVDDC

C7
D3
D10
K3
K6
K7
K10

E4
C3
C4
C5
C8
C9
C10
D5
D8
E9
F4
F9
G4
G9
H4
H9
J4
J9
A3
A10
D4
D6
D7
D9
J5
J6
J7
J8
K4
K9

0

of

13 28Friday, January 28, 2005

www.vinafix.vn

1

GPIO[6..0]

GPIO[6..0](4)

Overlap pads to save space
and to prevent assembly of
both resistors.

A A

Layout

High logic voltageGround

Signal

GPIO[13..8]

GPIO[13..8](4,8)

B B

VSYNC_DAC2(4,17)

HSYNC_DAC2(4,17)

VSYNC_DAC1(4,16)

HSYNC_DAC1(4,16)

C C

DVALID(4)

PSYNC(4)

2

OPTION STRAPS

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO8

GPIO9

GPIO11

GPIO12

GPIO13

R331 10K
R332 10K
R333 10K
R334 10K

R205 10K DNI
R206 10K
R335 10K DNI
R336 10K

R347 10K
R348 10K
R349 10K DNI
R350 10K
R351 10K DNI
R352 10K

R345 10K DNI
R346 10K

R343 10K
R344 10K DNI

R337 10K
R338 10K
R339 10K
R340 10K
R341 10K
R342 10K

R353 10K
R354 10K
R355 10K
R356 10K DNI

R359 10K
R360 10K

R357 10K
R358 10K

R361 10K DNI
R362 10K
R363 10K DNI
R364 10K

3

+3.3V_BUS

R423 Shared Straps

STRAPS

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

MOBILE_FEATURE1

PCIE_MODE
(ATI Internal)

TX_IEXT

FORCE _COMPLIANCE GPIO(5)

PLL_BW
(ATI Internal)

MULTIFUNC(1:0)

R423 Dedicated Straps

ZV_VOLTAGE_SEL0 DVOVMODE_0

4

PIN

GPIO(0)MOBILE_FEATURE0

GPIO(1)

GPIO(3:2)

GPIO(4)

GPIO(6)

GPIO(8)DEBUG_ACCESS

H2SYNC, V2SYNC

VSYNC

HSYNC 0RFU RFU

DESCRIPTION
Transmitter Power Savings Enable

0: 50% Tx output swing for mobile mode
1: full Tx output swing
(Desktop must have an external pullup)

Transmitter De-emphasis Enable
0: Tx de-emphasis disabled for mobile mode
1: Tx de-emphasis enabled
(Desktop must have an external pullup)

PCIE mode:
00: PCI Express 1.0A mode
01: Kyrene-compatible mode
10: PCI Express 1.0 mode
11: Short-circuit internal loopback and PCI Express 1.0A mode

Transmitter Extra Current
0: normal mode
1: extra current in Tx output stage - potential power savings for mobile mode

Force chip to get to compliance state quickly for Tester purposes
0: Normal operation
1: Force to compliance state

1: Reduced PLL bandwidth

0: Disable debug access
1: Enable debug access

If no ROM attached, controls chip IDis. If rom attached identifies ROM type.
GPIO[9,13,12,11]

000x - No ROM,CHG_ID=00
001x - No ROM, CHG_ID=01
010x - No ROM, CHG_ID=10
011x - No ROM, CHG_ID=11

1001 - 1M Serial AT25F1024 ROM (Atmel)
1010 - 1M Serial AT45DB011 ROM (Atmel)
1011 - 1M Serial M25P10 ROM (ST)

1100 - 512K Serial M25P05 ROM (ST)

1101 - 1M Serial SST45LF010 ROM (SST)
1M Serial W45B512 ROM (WinBond)
512K Serial W45B012 ROM (WinBond)

1110 - 1M Serial SST25VF010 ROM (SST)
512K Serial SST25VF512 ROM (SST)

1111 - 1M NX25F011B ROM (NexFlash)

Chip IDs:

Chip ID is based on substrate fuses and CHG_ID strap (which comes from ROM if used,
or pin straps if no ROM is connected): CHG_ID = ROMIDCFG[2:1] = GPIO[13:12]

Multi-function device select
00 - single function device.
01 - two function device.

10 - two function device.

11 - two function device.

Indicates if any slave VIP host devices drove this in low during reset.VIP_DEVICE
0 - Slave VIP host port devices present

1 - No slave VIP host port devices reporting presence during reset

0 - Normal

1 - Not used

DVOVMODE_0 is for ZV_LCDCNTL and ZV_LCDDATA(11:0}.

0 - 3.3 V signaling

1 - 1.8 V signaling
DVOVMODE_1 is for ZV_LCDDATA(23:12)ZV_VOLTAGE_SEL1 DVOVMODE_1

0 - 3.3 V signaling

1 - 1.8 V signaling

5

6

REV. 0.0

DEFAULT

0

0

00

0

0

00: Full PLL Bandwidth

0Strap to set the debug muxes to bring out DEBUG signals even if registers are inaccessible

1100GPIO(9,13:11)ROMIDCFG(3:0)

+3.3V_BUS

DEMUX_SEL(4)
DC_Strap3(4,21)
GPIO10(4)

7

R584 10K
R580 10K
R576 10K

DC_Strap4 (4)
DC_Strap2 (4)

R577 10K
R581 10K DNI
R585 10K DNI

R582 10K
R578 10K
R574 10K

DC_Strap1

R575 10K
R579 10K
R583 10K DNI

+3.3V_BUS

DNI(STINGRAY)

DNI
DNI

41

SW1A
DIP_SWX2

8

PAL/NTSC (4)

WARNING

Some of those straps must be connected to +VDD_1.8V
if ZV_LCDATA bus is set to 1.8 V.

10

1

+VDD_1.8V

REV. 0.0

0

0

R570 10K

R571 10K

DNI

DVOMODE_1 (4)

Board Straps

STRAPS DEFAULTDESCRIPTIONPIN

MEMTYPE(1:0)

DC_Strap1

DC_Strap2

DC_Strap3 Not defined

D D

1

2

3

DC_Strap4,
DEMUX_SEL

PAL/NTSC

EXT_PWR

DVALID, PSYNC.

GPIO(10)

LCDDATA(13)

LCDDATA(14)

LCDDATA(15,19)

LCDDATA(18)

GPIO15

Memory connected to R420 identification for BIOS

00 - Samsung GDDR 3 memory 144 Ball BGA package

01 - TBD
10 - TBD
11 - TBD

Internal TMDS Enabled
0 - Disabled

1 - Enabled

Video Capture Enabled

0 - Disabled

1 - Enabled

Video capture enable
00 - DAC2 Off

01 - DAC2 On as CRT

10 - DAC2 On as TVOUT
11 - DAC2 On as TVOUT and CRT

TVO Standard Default (Resistor pull-up and switch short to GND)

0 - PAL (on board resistor pull-down and switch closed)

1 -NTSC (on board resistor pull-up)

External power cable detect

0 - Cable is properly connected

1 - Cable is not properly connected. Software should pr event the board from booting, should display
a warning at screen and should decrease engine and memory clock speed.

4

5

REV. 0.0

000

1

0

0

01

1

NA

6

<Variant Name>

+VDD_1.8V

R572 10K

R573 10K

DNI

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP R480+Rialto 256MB BGA DVII DVII VIVO

Size Document Number Rev

C

Date: Sheet

7

DVOMODE_0 (4)

105-A49000-00A

14 28Friday, January 28, 2005

8

0

of

www.vinafix.vn

8

D D

7

6

5

4

3

2

1

TEMPERATURE SENSE AND SPEED CONTROLLED FAN

H1

+12V_BUS

R1863
0R

DNI

B59

Bead

23

Si2301DS

1

Q229

DNI

D40
LL4148

DNI

2 1

R1864
0R

DNI

32

1

DNI

R1611
0R

2 1

D39
LL4148

DNI

R1862
0R

R1573
0R

DNI

C1134
1uF

DUAL FOOTPRINT

JU1

1
2

MJU1

1
2
3

Header_1X3

DNI

JUl2

JUl1

HEATSINK_FAN

C C

+3.3V_BUS

C1516

C1517

C1518

10uF

0.1uF

R1610
10K

R1620 100R

SCL(4,19)

R1621

SDA(4,19)

ThermINT(4)

R1624 0R

100R

SCL_R
SDA_R

C1524
56pF

C1525
56pF

TACH GPU_DMINUS

U106

8

SMBCLK

7

SMBDAT

6

ALERT

5 4

GND PWM

LM63CIMAX

100pF

1

VDD

2

D+

3

D-

Do not install

This resistor will
be shorted in layout.

+3.3V_BUS

R1613
10K

DNI

R1614
10K

DNI

It is present to control
where the signal will be
connected to digital
ground.

DNI

R1615 0R

DNI

R1616 0R

B B

PWM
GPU_DMINUS
SCL_R

R1684 0R

DNI

U107

4

NC#4

1

PWM

5

GND

9

D-

13

ADD

16

SCL

7

THERM

8

FAULT

ADM1030ARQ

DNI

TACHNC#3

NC#11

R1683
10R

TACH

23

R1612 0R

14

INT

NC

D+
VCC
SDA

12
11
10
6
15

GPU_DPLUS

SDA_R

DNI

DNI DNI DNI

C1578

10uF

C1519

2.2nF

+3.3V_BUS

C1579

0.1uF

R1609

4.7K

GPU_DPLUS

DNI

R1682

R1866

C1580

100pF

0R

0R

DNI

GPU_DPLUS (4)

GPU_DMINUS (4)

R1628
0R

DNI

R1629
10K

+12V_BUS

R1631
10K

DNI

1

+3.3V_BUS

2 3

R1865
1K

DNI

1

Q230
MMBT2222ALT1

DNI

+12V_BUS

2 3

+3.3V_BUS

R1681
1K

Q213
MMBT2222ALT1

DNI

R1769
1K

R1844 10K

C1577
1uF

C1520 10nF

TACHPWM

Q209
ZXM61N03FTA

A A

<Variant Name>

8

7

6

5

4

3

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP R480+Rialto 256MB BGA DVII DVII VIVO

Size Document Number Rev

C

Date: Sheet

2

105-A49000-00A

of

15 28Friday, January 28, 2005

1

0

www.vinafix.vn

Change to Maxim part

8

7

6

5

4

OPTIONAL ESD/HOTPLUG PROTECTION DIODES

+3.3V_BUS +12V_BUS

BAT54SLT1

D10

D11

D13

D12

D14

3

D15

D16

2

1

D D

R_DAC1(4)
G_DAC1(4)

B_DAC1(4)

+3.3V_BUS

R467

CRT1DDCDATA(4)

C C

B B

CRT1DDCCLK(4)

HSYNC_DAC1(4,14)

VSYNC_DAC1(4,14)

+3.3V_BUS

4.7K

R468

4.7K

+3.3V_BUS

+3.3V_BUS

1

BSN20

1

Q12

BSN20
Q13

32

SN74ACT86PW

+5V_BUS

32

+5V_BUS

4
5

9

10

SN74ACT86PW

R463

6.8k

R464

6.8k

U3B

6

U3C

8

DAC1 CRT INTERFACE

R402

R403

R401

75.0R

75.0R

75.0R
C401

6.8pF

PLACE CLOSE TO ASIC

R859 33R

R860 33R

C402

6.8pF

C403

6.8pF

L51 47nH
L52 47nH
L53 47nH

C404

C405

8pF

8pF

L54 47nH
L55 47nH
L56 47nH

C406

8pF

DNI DNI DNI DNI DNI DNI DNI

R465 33R
R466 33R

DNI DNI DNI

C408

C409

C407

5pF

5pF

5pF

DNI DNI DNI

L8

L7

82nH

82nH

82nH

L9

DNI DNI

C751
22pF

C752
22pF

PLACE CLOSE TO
CONNECTOR

R_DAC1_F
G_DAC1_F
B_DAC1_F

DDCDATA_DAC1_R

DDCCLK_DAC1_R

HSYNC_DAC1_R
VSYNC_DAC1_R

+5V_DIN1(18)

R_DAC1_F (18)
G_DAC1_F (18)
B_DAC1_F (18)

DDCDATA_DAC1_R (18)
DDCCLK_DAC1_R (18)
HSYNC_DAC1_R (18)

VSYNC_DAC1_R (18)

R_DAC1_F
G_DAC1_F
B_DAC1_F

DDCDATA_DAC1_R
DDCCLK_DAC1_R
HSYNC_DAC1_R

VSYNC_DAC1_R

F1

750mA

+5VCON1 (17)

B39
Bead

J2 and MJ2 share the
same area - they are
mutually exclusive.

+5V_BUS

MJ2

DNI

1

R

2

G

3

B

11

MS0

12

MS1

4

MS2

15

MS3

9

NC

13

HS

14

VS

5

VSS

6

VSS#6

7

VSS#7

8

VSS#8

10

VSS#10

16

CASE

17

CASE#17

SLIM VGA HT 6.27MM

A A

<Variant Name>

8

7

6

5

4

3

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP R480+Rialto 256MB BGA DVII DVII VIVO

Size Document Number Rev

C

Date: Sheet

2

105-A49000-00A

of

16 28Friday, January 28, 2005

1

0

www.vinafix.vn

8

D D

7

6

5

OPTIONAL ESD/HOTPLUG PROTECTION DIODES

+3.3V_BUS

D17

D18

D19

+12V_BUS

D20 D22

4

D21

D23

3

2

1

BAT54SLT1

DNIDNIDNIDNI DNIDNIDNI

C C

B B

R_DAC2(4)
G_DAC2(4)

B_DAC2(4)

+3.3V_BUS

R479

+3.3V_BUS

+5V_BUS

R481

4.7K

4.7K

1

10

9

13
12

7

CRT2DDCDATA(4)

CRT2DDCCLK(4)

A A

HSYNC_DAC2(4,14)

VSYNC_DAC2(4,14)

8

1

BSN20

Q14

BSN20

32

Q15

74ACT08MTC

U2C

U2D

74ACT08MTC

+5V_BUS

6.8k
R480

32

+5V_BUS

6.8k
R482

8

11

R825 33R

R824 33R

R31 47R
R32 47R

6

R_DAC2_F
G_DAC2_F

B_DAC2_F
DDCDATA_DAC2_R
DDCCLK_DAC2_R
HSYNC_DAC2_R

VSYNC_DAC2_R

R451 75.0R
R452 75.0R
R453 75.0R

PLACE CLOSE TO ASIC

C451

C452

6.8pF

6.8pF

DDCDATA_DAC2_R (18)

DDCCLK_DAC2_R (18)

HSYNC_DAC2_R (18)
VSYNC_DAC2_R (18)

DNI DNI DNI DNI DNI

C574

C573

C575

5pF

5pF

5pF

DNI DNI DNI

L17

L18

L16

82nH

82nH

82nH

L71 47nH
L72 47nH
L73 47nH

C453

6.8pF

SECONDARY CRT LOGIC
CRT2

5

5
4

A_R_DAC2_F1
A_G_DAC2_F1
A_B_DAC2_F1

C454
8pF

74ACT08MTC

U2B

C749
22pF

PLACE CLOSE TO
CONNECTOR

C455

C456

8pF

8pF

6

C750
22pF

L74 47nH
L75 47nH
L76 47nH

4

+5V_DIN2(18)

R_DAC2_F (18)
G_DAC2_F (18)
B_DAC2_F (18)

B63

+5VCON1 (16)

J4 and MJ4 share the
same area - they are
mutually exclusive.

3

DNI

MJ4

1

R

2

G

3

B

11

MS0

12

MS1

4

MS2

15

MS3

9

NC

13

HS

14

VS

5

VSS

6

VSS#6

7

VSS#7

8

VSS#8

10

VSS#10

16

CASE

17

CASE#17

DB15F_slim_RA

DDC2_MONID0
DDC2_MONID1(SDA)
DDC2_MONID2
DDC2_MONID3(SCL)

<Variant Name>

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP R480+Rialto 256MB BGA DVII D VII VIVO

Size Document Number Rev

C

Date: Sheet

2

105-A49000-00A

of

17 28Friday, January 28, 2005

1

0

www.vinafix.vn

8

D D

7

6

5

4

3

2

1

PRIMARY DVI-I CONNECTOR (DVI-I1)

DVI-I1

J4

25

DVI-I2

J2

CASE

1

TMDS Data2-

2

TMDS Data2+

3

TMDS Data2/4 Shield

4

TMDS Data4-

5

TMDS Data4+

6

DDC Clock

7

DDC Data

8

Analog VSYNC

9

TMDS Data1­TMDS Data1+
TMDS Data1/3 Shield
TMDS Data3­TMDS Data3+
+5V Power
GND (for +5V)
Hot Plug Detect
TMDS Data0­TMDS Data0+
TMDS Data0/5 Shield
TMDS Data5­TMDS Data5+
TMDS Clock Shield
TMDS Clock+
TMDS Clock-

Analog Red
Analog Green
Analog Blue
Analog HYNC
Analog GND
Analog GND#C6

CASE#26
CASE#27
CASE#28
CASE#29
CASE#30

DVICONNECTOR

CASE

1

TMDS Data2-

2

TMDS Data2+

3

TMDS Data2/4 Shield

4

TMDS Data4-

5

TMDS Data4+

6

DDC Clock

7

DDC Data

8

Analog VSYNC

9

TMDS Data1-

10

TMDS Data1+

11

TMDS Data1/3 Shield

12

TMDS Data3-

13

TMDS Data3+

14

+5V Power

15

GND (for +5V)

16

Hot Plug Detect

17

TMDS Data0-

18

TMDS Data0+

19

TMDS Data0/5 Shield

20

TMDS Data5-

21

TMDS Data5+

22

TMDS Clock Shield

23

TMDS Clock+

24

TMDS Clock-

C1

Analog Red

C2

Analog Green

C3

Analog Blue

C4

Analog HYNC

C5

Analog GND

C6

Analog GND#C6

26

CASE#26

27

CASE#27

28

CASE#28

29

CASE#29

30

CASE#30

DVICONNECTOR

J2 and MJ2 share the
same area - they are
mutually exclusive.

3

<Variant Name>

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP R480+Rialto 256MB BGA DVII DVII VIVO

Size Document Number Rev

C

Date: Sheet

2

105-A49000-00A

of

18 28Friday, January 28, 2005

1

0

TX2M(4)

C C

B B

A A

8

TX2P(4)

DDCCLK_DAC2_R(17)
DDCDATA_DAC2_R(17)

TX1M(4)
TX1P(4)

TX0M(4)
TX0P(4)

TXCP(4)
TXCM(4)

HPD1(4)

D9

2.5V

NOTE:
ALL ITEMS ARE DNI

HPD2(19)

2 1

7

6

D35

2.5V

R405 20K

R408
100K

R457 20K

R458
100K

2 1

DDCCLK_DAC1_R(16)

DDCDATA_DAC1_R(16)

VSYNC_DAC1_R(16)

HSYNC_DAC1_R(16)

5

VSYNC_DAC2_R(17)

Place close to

Place close to
the connector

C1701
100nF

the connector

TX2­TX2+

TX1­TX1+

TX0­TX0+

TXC+
TXC-

4

+5V_DIN2(17)

R_DAC2_F(17)
G_DAC2_F(17)
B_DAC2_F(17)

HSYNC_DAC2_R(17)

TX2-(19)
TX2+(19)

TX1-(19)
TX1+(19)

+5V_DIN1(16)

TX0-(19)
TX0+(19)

TXC+(19)
TXC-(19)

R_DAC1_F(16)
G_DAC1_F(16)
B_DAC1_F(16)

TX2M
TX2P

TX1M
TX1P

TX0M

TX0P

C558
100nF

TXCP

TXCM

SECONDARY DVI-I CONNECTOR

25

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

C1

C2

C3

C4

C5

C6

26
27
28
29
30

www.vinafix.vn

5

4

3

2

1

SILICON IMAGE TMDS TRANSMITTERNOTE:
ITEMS ON THIS
PAGE ARE ALL DNI

D D

DVO[11..0](4)

C C

DVO_HSYNC(4)
DVO_VSYNC(4)
DVO_DE(4)

CLK_DVOCLK0(4)

+3.3V_BUS

HPD2(18)

SDA(4,15)
SCL(4,15)

AGP_RESET#(2,20,23)

B B

+3.3V_BUS

RP213A 33R

DVO0
DVO1
DVO2
DVO3
DVO4
DVO5
DVO6
DVO7
DVO8
DVO9 DVOR9 DVOR9
DVO10
DVO11

R1773 0R

8 1

RP213B 33R

7 2

RP213C 33R

6 3

RP213D 33R

5 4

RP214A 33R

8 1

RP214B 33R

7 2

RP214C 33R

6 3

RP214D 33R

5 4

RP215A 33R

8 1

RP215B 33R

7 2

RP215C 33R

6 3

RP215D 33R

5 4

PLACE CLOSE TO THE ASIC

PLACE CLOSE TO THE ASIC

R385 33R
R388 33R
R390 33R

R394 33R

R397 5.1K

R400 33K
R1770 33R

R1771 33R

DVOR0 DVOR0
DVOR2 DVOR2

DVOR5 DVOR5
DVOR6 DVOR6

DVOR8 DVOR8

DVOR11 DVOR11

DVOR1DVOR1
DVOR3DVOR3

DVOR4DVOR4

DVOR7DVOR7

DVOR10DVOR10

SI_HS

SI_VS

SI_DE

IDCKP

TMDS_VREF

MSEN

HPD2

ISEL

DSEL

BSEL

U114

18
17
16
15
14
13
10

9
8
7
6
5

24
20

21
19

12
11

48
44

25
26

27

1
31
47

SiI1162

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11

CTL3/A2
HSYNC

VSYNC
DE

IDICK+
IDCK-

MSEN
EDGE/HTPLG

ISEL/RST#
SDA

SCL

GND#1
AGND#31
PD#

TX0-

TX0+

TX1-

TX1+

TX2-

TX2+
TXC-

TXC+

AVCC

AVCC#40

AGND

AGND#43

VREF

EXT_SWING

PVCC1
PVCC2

PGND

PGND#45

VCC#22

VCC

GND

GND#23

TH_GND

35
36

38
39

41
42

32
33

34
40

37
43

2
30

28
46

29
45
22
3

4
23

49

AVCC1
AVCC2

GND_A

TMDS_VREF
EXT_SWING

PVCC1
PVCC2

VCC1
VCC2

TX0­TX0+

TX1­TX1+

TX2­TX2+

TXC­TXC+

100nF

PLACE OPTIONAL TERMINATIONS CLOSE TO TRANSMITTER

R1785 330R

R1786 330R

R1787 330R

R1788 330R

C504

C503

R386 1K
R389 1K
C508 0.1uF

GND_P

C510

C511

2.2nF

C502

100pF

C509
100nF

C1583
100nF

+VDDR4

2.2nF

C1581

2.2nF

C1584

2.2nF

100nF

GND_A

C505
100pF

GND_P

GND_P

R392 390R

C500
10uF_6.3V

C1656 100nF

C1657 100nF

C1658 100nF

C1659 100nF

C507

2.2nF

GND_A

B64 Bead

C1582
10uF_6.3V

B65 Bead

C506
100nF

+3.3V_BUS

+PVCC1

C501
10uF_6.3V

LM431CCM/N1B

GND_A GND_P

REG9

TX0­TX0+

TX1­TX1+

TX2­TX2+

TXC­TXC+

B60 Bead

C499
10uF_16V

+5V_BUS

3 1

TX0- (18)

TX0+ (18)

TX1- (18)

TX1+ (18)

TX2- (18)

TX2+ (18)
TXC- (18)

TXC+ (18)

+3.3V_BUS

R380

27R

R381
137R

2

R382
432R

C512
100nF

A A

5

4

3

C513

2.2nF

<Variant Name>

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP R480+Rialto 256MB BGA DVII DVII VIVO

Size Document Number Rev

B

Date: Sheet

2

105-A49000-00A

19 28Friday, January 28, 2005

of

1

0

www.vinafix.vn

8

NOTE:
ITEMS ON THIS
PAGE ARE ALL DNI

7

6

5

4

3

2

1

D D

3.3uH

L68

1 2

CompR(21)

3.3uH

L70

LumaR(21)

C C

ChromaR(21)

CLK_RT_XTALIN(4)

AGP_RESET#(2,19,23)

B B

22uF_16V

1 2

L77

1 2

+RTAVDD

12

L78

3.3uH

C1614

Ca1 Ca2

10R

3.3uH

R1701

C1615

1.0uF

C1602
330pF

C1607
330pF

C1609
330pF

R1690

75.0R

R1693

75.0R

R1694

75.0R

GND_VIN

C1613 2.2uF

+5V_BUS

REG8

3.3V

3 2

IN OUT

C1590

1.0uF

GND_RT GND_RT GND_RT GND_RT

12

L67

3.3uH

12

C1603

22uF_16V

L69

3.3uH
R1691

10R

C1605

22uF_16V

GND_RT

C1608 0.1uF

GND_RT

C1606

1.0uF

C1610

0.068uF
C1611

C1612 2.2uF

22nf

GND

1

10R

R1689

+VADCD
+VADCA

CASE

C1604

1.0uF

R1703

4.7K

4

C1589

22uF_16V

47

VAGCVDD

49

VAGCVSS#49

48

VAGCVSS

66

VDACVDD

60

VDACBVSS

61

VDACJVSS

33

VIND0

34

VIND1

35

VIND2

36

VIND3

37

VIND4

38

VIND5

39

VIND6

40

VIND7

27

VINGATEA

28

VINGATEB

58

CF

59

CR

57

VAGCCAP

56

VIDEOGNDSENSE

55

VCLAMPCAP

43

VADCDVDD

45

VADCAVDD

44

VADCDVSS

46

VADCAVSS

50

COMP0

51

COMP1

52

COMP2

53

YF_COMP3

54

YR_COMP4

69

XTALIN

70

XTALOUT

73

TESTEN

74

RESETB

67

PLLVDD

68

PLLVSS

+RTAVDD

C1591

1.0uF

VSSC

18

VSSC#26

VSSC#77

26

1

VDDR

VSSC#100

VSSC#83

100

83

12

R1687

L79

+3.3V_BUS

3.3uH
10R

+RTVDDC +VADCD

C1596

99

VDDC#99

VDDC#76

VSSR

VSSR#90

90

GND_RT

1.0uF

41

31

VDDR#31

VDDC#41

DS_VIPCLK

SRDY_IRQB

C_GREEN

COMP_BLUE

CLKOUT0_GPIO0
CLKOUT1_GPIO1
CLKOUT2_GPIO2

VSSC#42

VSSR#32

42

32

RAGE_THEATER

C1597

1.0uF

U111

SAD0
SAD1
SAD2
SAD3
SAD4
SAD5
SAD6
SAD7

AS_HCTL

HAD0
HAD1

ADIO

BITCLK

SPDIF

BYTCLK

SYNC

Y_RED

RSET

GPIO3
GPIO4
GPIO5
GPIO6

PDATA0
PDATA1
PDATA2
PDATA3
PDATA4
PDATA5
PDATA6
PDATA7

PCLK

C1598

1.0uF

91
92
93
94
95
96
97
98

88
87
86
84
85

15

SDA

16

SCL

22

ADO

24
23

WS

21

19
89

75
62
63
64
65

78
79
20
13
14
17
80

4
5
6
7
8
9
10
11
3

C1595
10nF

25

767771

81

29

VDDC

VDDR#71

VDDR#29

VDDR#81

VSSR#2

VSSR#72

VSSR#12

VSSR#30

82

2

72

12

30

C1592

C1599

22uF_16V

1.0uF

GND_RT

RP196A 33R
RP196B 33R
R1692 47K
RP196D 33R
RP196C 33R

RP194D 33R
RP194C 33R
RP194B 33R
RP194A 33R
RP195D 33R
RP195C 33R
RP195B 33R
RP195A 33R

Place close to the Rage
Theater

R1704

C1593

22uF_16V

GND_RT GND_RT

81
72

54
63

R1697 10K

R1695 10K

54
63
72
81
54
63
72
81

33R

+VADCA

C1600

1.0uF

GND_RT

GND_RT

VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7

VID[7..0]

L80

3.3uH

C1594

22uF_16V

+3.3V_BUS

GND_RT

R1696

4.7K

12

R1688

10R

C1601

1.0uF

CLK_VIPCLK (4)
VPHCTL (4)

VHAD0 (4)
VHAD1 (4)

VID[7..0] (4)

CLK_VIDCLK (4)

GND_RT

IMPORTANT

Layout Guide line of THEATER

#1 : Ca1 and Ca2 have to be placed as close as poss i bl e t o t h e r e sp e c t i ve p i n s o f R a g e THEATER
#2 : GND_VIN should be seperated from Di g i t al o r Ch a s s i s G r ound and have no loops

A A

8

#3 : GND_VIN should be connected to Digital GND plane at one point as close as possible to
pin 56 of THEATER

7

6

Put 2D line as close as possible to pin 56 of Rage Theater

GND_VIN

GND_RT

5

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP R480+Rialto 256MB BGA DVII DVII VIVO

Size Document Number Rev

C

4

3

Date: Sheet

2

105-A49000-00A

0

of

20 28Friday, January 28, 2005

1

www.vinafix.vn

8

7

6

5

4

3

2

1

TV-OUT

D D

COMP_DAC2(4)

Y_DAC2 TBLuma

Y_DAC2(4)

G

C_DAC2(4)

COMP_DAC2

C_DAC2

GND_TVVSSN

GND_TVVSSN

GND_TVVSSN

R912

75.0R

R913

75.0R

R914

75.0R

C583
47pF

C585
47pF

C588
47pF

L20

470nH

C584
47pF

L21

470nH

L22

470nH

C586
47pF

C587
47pF

TBChroma

TBComp

Footprint - M1

TV Out (SVHS) MiniDIN 7-pin

C C

DC_Strap3(4,14)

TBLuma
TBChroma
TBComp

R606 0R
R608 0R
R504 0R

A

B B

STEREOSYNC(4)

R763 0R

R878 2500R

Connector Jm1 uses the
same footprint as Jm2
and Jm3

+5V_BUS

C753
100nF

147

1
2

SN74ACT86PW

12
13

SN74ACT86PW

Rm22
Rm23
Rm24

U3A

U3D

C527
82pF

3

11

Conn_DIN_Mini_Circular_7_Pin_with_O_Ring

HDTV_DET#

TBLuma_R
TBChroma_R
Comp_Out
CompR_F

DNI

PIN1

Jm1

J7

6

HDTV_OUT_DET#

3

Y-OUT

4

C-OUT

7

Comp_out

5

SYNC

1

GND

2

GND#2

8

CASE

9

CASE#9

10

CASE#10

TV-OUT 7-PIN MiniDIN

102-00302-00
102-00305-00

VIVO 9-PIN MiniDIN

102-00303-00
102-00306-00

No Options (Just DB15)

Install

ACB

C

NOTE:
ALL ITEMS ARE DNI

C

NOTE:
ALL ITEMS ARE DNI

ChromaR_MUX_FP
CompR_MUX_FP

LumaR_MUX_FP

DNI

E

AB

E

ABC

CompR_MUX_BR

LumaR_MUX_BR
ChromaR_MUX_BR

Connector Jm2 uses the
same footprint as Jm1
and Jm3

B16 120R
B17 120R

B18 120R

C7633pF

E

HDTV_DET#

TBLuma_R
TBChroma_R
Comp_Out

B54

B53

C7733pF

C7833pF

VI MUX

+5V_BUS +5V_BUS

32

SW1B
DIP_SWX2

R365
10K

DNI

B56

C1141
220pF

JP1

1

1

2

2

3

3

4

4

header_1x4_YELLOW

B19
120R

NOTE:
ALL ITEMS ARE DNI

CompR_MUX_BR
CompR_MUX_FP

ChromaR_MUX_BR
ChromaR_MUX_FP

C1142
220pF

VI MUX BYPASS

CompR
LumaR

NOTE:
ALL ITEMS ARE DNI

DNI

U96

1

SEL

2

1A0

3

1A1

5

1B0

6

1B1

11

1C0

10 14

1C1 1D0

15

E

PI5V330

Jm2

MJ8

6

HDTV_OUT_DET#

3

Y-OUT

4

C-OUT

7

Comp-out

CompR_F

5

Comp-in

PIN1

1

GND

2

GND#2

11

Luma-in

12

Chroma-in

8

CASE

9

CASE#9

10

CASE#10

9 PIN MINIDIN
C1143
120pF

B20

GND_VIN

ChromaR_MUX_BRChromaR

R9670R

CompR_MUX_BR

R9680R

LumaR_MUX_BR

R9690R

ChromaR_MUX_FP

R9700R

CompR_MUX_FP

R9710R

LumaR_MUX_FP

R9720R

B6

220R

16

VCC

4

YA

7

YB

9

YC

12

YD

13

1D1

8

GND

LumaR_MUX_FP

LumaR_MUX_BR

C735
100nF

CompR (20)
ChromaR (20)

LumaR (20)

share the same footprint

AC

A A

<Variant Name>

8

7

6

5

4

3

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP R480+Rialto 256MB BGA DVII DVII VIVO

Size Document Number Rev

C

Date: Sheet

2

105-A49000-00A

of

21 28Friday, January 28, 2005

1

0

www.vinafix.vn

5

D D

Place the Test Points
close to U112

4

3

2

1

Rialto ASIC p/n is: 218BAPAGA11F

PETp0_GFXRp0(3)
PETn0_GFXRn0(3)

PETp1_GFXRp1(3)
PETn1_GFXRn1(3)

PETp2_GFXRp2(3)
PETn2_GFXRn2(3)

PETp3_GFXRp3(3)
PETn3_GFXRn3(3)

PETp4_GFXRp4(3)
PETn4_GFXRn4(3)

PETp5_GFXRp5(3)

C C

B B

PETn5_GFXRn5(3)

PETp6_GFXRp6(3)
PETn6_GFXRn6(3)

PETp7_GFXRp7(3)
PETn7_GFXRn7(3)

PETp8_GFXRp8(3)
PETn8_GFXRn8(3)

PETp9_GFXRp9(3)
PETn9_GFXRn9(3)

PETp10_GFXRp10(3)
PETn10_GFXRn10(3)

PETp11_GFXRp11(3)
PETn11_GFXRn11(3)

PETp12_GFXRp12(3)
PETn12_GFXRn12(3)

PETp13_GFXRp13(3)
PETn13_GFXRn13(3)

PETp14_GFXRp14(3)
PETn14_GFXRn14(3)

PETp15_GFXRp15(3)
PETn15_GFXRn15(3)

PCIE_REFCLKP(3)
PCIE_REFCLKN(3)

PCIE_REFCLKP(3)
PCIE_REFCLKN(3)

R1774 49.9R
R1777 49.9R

TP30

TP31

TP45

TP54

TP55

R1775 33.2R
R1776 33.2R

Place the reisitors
close to ASIC

U112A

U13

PCIE_TX0P

T13

PCIE_TX0N

T14

PCIE_TX1P

R14

PCIE_TX1N

R12

PCIE_TX2P

P12

PCIE_TX2N

P13

PCIE_TX3P

N13

PCIE_TX3N

N14

PCIE_TX4P

M14

PCIE_TX4N

M12

PCIE_TX5P

L12

PCIE_TX5N

L13

PCIE_TX6P

K13

PCIE_TX6N

K14

PCIE_TX7P

J14

PCIE_TX7N

J12

PCIE_TX8P

H12

PCIE_TX8N

H13

PCIE_TX9P

G13

PCIE_TX9N

G14

PCIE_TX10P

F14

PCIE_TX10N

F12

PCIE_TX11P

E12

PCIE_TX11N

E13

PCIE_TX12P

D13

PCIE_TX12N

D14

PCIE_TX13P

C14

PCIE_TX13N

C12

PCIE_TX14P

B12

PCIE_TX14N

B13

PCIE_TX15P

A13

PCIE_TX15N

W16

PCIE_REFCLKP

V16

PCIE_REFCLKN

Y11

RefCLKP

W11

RefCLKN

R20

PERSTB

W19 Y8

PCIETEST R_EXT

Rialto

PART 1 OF 4

PCIE TX

Clock

R1772 750R

TP34

TP35

TP48TP44

TP49

TP52

TP53

+PCIE_VDDR_12

GFXTp0_PERp0 (3)
GFXTn0_PERn0 (3)

GFXTp1_PERp1 (3)
GFXTn1_PERn1 (3)

GFXTp2_PERp2 (3)
GFXTn2_PERn2 (3)

GFXTp3_PERp3 (3)
GFXTn3_PERn3 (3)

GFXTp4_PERp4 (3)
GFXTn4_PERn4 (3)

GFXTp5_PERp5 (3)
GFXTn5_PERn5 (3)

GFXTp6_PERp6 (3)
GFXTn6_PERn6 (3)

GFXTp7_PERp7 (3)
GFXTn7_PERn7 (3)

GFXTp8_PERp8 (3)
GFXTn8_PERn8 (3)

GFXTp9_PERp9 (3)
GFXTn9_PERn9 (3)

GFXTp10_PERp10 (3)
GFXTn10_PERn10 (3)

GFXTp11_PERp11 (3)
GFXTn11_PERn11 (3)

GFXTp12_PERp12 (3)
GFXTn12_PERn12 (3)

GFXTp13_PERp13 (3)
GFXTn13_PERn13 (3)

GFXTp14_PERp14 (3)
GFXTn14_PERn14 (3)

GFXTp15_PERp15 (3)
GFXTn15_PERn15 (3)

V17

PCIE_RX0P

U17

PCIE_RX0N

P
C
I

­E
X
P
R
E
S
S

I
N
T
E
R
F
A
C

PCIE RX

E

PCIE_RX1P
PCIE_RX1N

PCIE_RX2P
PCIE_RX2N

PCIE_RX3P
PCIE_RX3N

PCIE_RX4P
PCIE_RX4N

PCIE_RX5P
PCIE_RX5N

PCIE_RX6P
PCIE_RX6N

PCIE_RX7P
PCIE_RX7N

PCIE_RX8P
PCIE_RX8N

PCIE_RX9P
PCIE_RX9N

PCIE_RX10P
PCIE_RX10N

PCIE_RX11P
PCIE_RX11N

PCIE_RX12P
PCIE_RX12N

PCIE_RX13P
PCIE_RX13N

PCIE_RX14P
PCIE_RX14N

PCIE_RX15P
PCIE_RX15N

Calibration

PCIE_CALRN
PCIE_CALRP

PCIE_CALI

U19
T19

T16
R16

R17
P17

P19
N19

N16
M16

M17
L17

L19
K19

K16
J16

J17
H17

H19
G19

G16
F16

F17
E17

E19
D19

D16
C16

C17
B17

AA21
Y21

W21

R1014 100R
R1013 150R

R1012 10K

PERST#(3)

PCIETEST(8)

R877

DNI

0R

402

DNI

R36

4.7K

402

Share the adjacent
pads of R36 and R877

CLK R42 R36

1.2V

3.3V

3150000000 (0R)

4

3150018100 (180R)3150030100 (300R)

<Variant Name>

DNI

3

2

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP R480+Rialto 256MB BGA DVII DVII VIVO

Size Document Number Rev

C

Date: Sheet

105-A49000-00A

1

of

22 28Friday, January 28, 2005

0

A A

+3.3V_BUS

C54
100nF

402

Y6

4

VCC

2

VSS

25.000MHz

Use 100MHZ OSC

Place R36, R42 close to Y6,
Place Y6 close to the ASIC.

R42
300R

402

3

OUT

1

OE

+3.3V_BUS

100MHZ Bypass Clock

5

www.vinafix.vn

5

4

3

2

1

D D

C C

B B

+VDDQ_BUS

R37 47R

402

OPTION 1: Crystal Circuit

C82 18pF

Y4

25.000MHz

C81 18pF

Use 18pF, 1%, Cap

A A

+3.3V_BUS

C18
100nF

402

2 1

Y5

4

VCC

OUT

2

VSS

OE

25.000MHz

Place R27, R28 close to Y5

3
1

R27
220R

+3.3V_BUS

AGP_AD[31..0](2)

AGP_C/BE#[3..0](2)

AGP_SBA[7..0](2)

AGP_ST[2..0](2)

AGP_ADSTB0#(2)

AGP_ADSTB1#(2)

AGP_AGPREFCG(2)

AGP_MB_8X_DET#(2)

DNI

R35

1.0M

402

R28
130R

OPTION 2: Oscillator Circuit

Note: Overlap the footprints of Y4, Y5.

5

Place Y4, Y5 close to ASIC.

AGP_AGPCLK(2)

AGP_DEVSEL#(2)

AGP_FRAME#(2)

AGP_ADSTB0(2)

AGP_ADSTB1(2)

AGP_SBSTB#(2)

AGP_DBI_LO(2)
AGP_DBI_HI(2)

+3.3V_BUS

R29
0R

402

AGP_RESET#(2,19,20)

AGP_REQ#(2)
AGP_GNT#(2)

AGP_PAR(2)

AGP_STOP#(2)
AGP_TRDY#(2)

AGP_IRDY#(2)

AGP_INTR#(2)
AGP_WBF#(2)

AGP_RBF#(2)

AGP_SBSTB(2)

AGP_ST[2..0]

+VDDQ_BUS

AGP_AD[31..0]

AGP_C/BE#[3..0]

4

R46 1K
R48 1K

DNI

R49 1K

B_GPIO8
B_GPIO9
B_GPIO10

+3.3V_BUS

R589
499R

R588
499R

B_GPIO[7..0]

B_GPIO[24..11]

B_GPIO[7..0] (26)

B_GPIO[24..11] (26)

B_GPIO9

B_ROMCS#

2

R38 33R
R39 33R
R40 33R
R41 33R

ROM_SOB_GPIO8
SI/A16
SCK/WEbB_GPIO10
CSb

TO SERIAL EEPROM 512K/1M

<Variant Name>

Title
Size Document Number Rev

C

Date: Sheet

ROM_SO (4)

SI/A16 (4)
SCK/WEb (4)
CSb (4)

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

AGP R480+Rialto 256MB BGA DVII DVII VIVO

105-A49000-00A

1

of

23 28Friday, January 28, 2005

0

U112B

AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31

AGP_C/BE#0
AGP_C/BE#1
AGP_C/BE#2
AGP_C/BE#3

AGP_SBA0AGP_SBA[7..0]
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7

AGP_ST0
AGP_ST1
AGP_ST2

STP_AGPB(26)

A6
A5
B6
B5
C5
C4
C3
D4
E4
F4
F3
G4
G3
H3
H4

J3
F6
F5
G6
H7
H6

J6

J7
K7
L7

M7
M6
M5

N7
N6
P7
P6

E3

J4
G7

J5

AA2
AB3

U6
V5
E7
F7
L4
L3

M3
M4
W4

R7
T6

D2
K6
R3

U4
U3
T4
T3
P4
P3
N4
N3

W3

V4
V3

R4
C2
L6

D6
E6

R5
R6
T7

AA3
AA4

Y3

AA8
AB8

Rialto

AD_0
AD_1
AD_2
AD_3
AD_4
AD_5
AD_6
AD_7
AD_8
AD_9
AD_10
AD_11
AD_12
AD_13
AD_14
AD_15
AD_16
AD_17
AD_18
AD_19
AD_20
AD_21
AD_22
AD_23
AD_24
AD_25
AD_26
AD_27
AD_28
AD_29
AD_30
AD_31

C_BEB_0
C_BEB_1
C_BEB_2
C_BEB_3

PCICLK
RSTB
REQB
GNTB
PAR
STOPB
DEVSELB
TRDYB
IRDYB
FRAMEB
INTAB

WBFB
RBFB

AD_STBF_0
AD_STBF_1
SB_STBF

SBA_0
SBA_1
SBA_2
SBA_3
SBA_4
SBA_5
SBA_6
SBA_7

ST_0
ST_1
ST_2

SB_STBS
AD_STBS_0
AD_STBS_1

AGPVREF
AGPTEST

DBI_LO
DBI_HI
AGP8X_DETB

STP_AGPB
AGP_BUSYB
RSTB_MSK

XTO
XTI

PART 2 OF 4

PCI / AGPAGP2X

4X8X

AGP

Additional

AGP

CLK

GPIOMISC

NC

REFCLKBYP

3

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8

GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
GPIO_18
GPIO_19
GPIO_20
GPIO_21
GPIO_22
GPIO_23
GPIO_24

ROMCSB

VrefG1

PLLTEST

TESTEN

Y9
AB10
AA10
Y10
AA11
Y12
AA12
AB12
W18
Y20
AB20
AA13
AB13
AA14
AB14
AA15
AB15
AA16
AB16
AA17
AB17
AA18
AB18
Y18
AA19

Y19

W20

AB4

W6
Y4

TESTEN

B_GPIO0
B_GPIO1
B_GPIO2
B_GPIO3
B_GPIO4
B_GPIO5
B_GPIO6
B_GPIO7

B_GPIO11
B_GPIO12
B_GPIO13
B_GPIO14
B_GPIO15
B_GPIO16
B_GPIO17
B_GPIO18
B_GPIO19
B_GPIO20
B_GPIO21
B_GPIO22
B_GPIO23
B_GPIO24

B_ROMCS#

REFCLKBYP (26)

R47 1K
R45 1K

www.vinafix.vn

5

D D

4

3

2

1

U112C

+B_VDDC

C629
10nF

C100

1.0uF

C992
1uF

C651
10nF

C95
10uf

C628
10nF

C993
1uF

C654
10nF

C79
10uF_10V

C630
10nF

C994
1uF

C656
10nF

C631
10nF

C995
1uF

C652
10nF

C84
10uF_10V

C11

VDDC_1

F9

VDDC_2

K11

VDDC_3

B11

VDDC_4

K9

VDDC_5

F11

VDDC_6

G10

VDDC_7

G11

VDDC_8

P11

VDDC_9

P10

VDDC_10

L9

VDDC_11

L11

VDDC_12

B9

VDDC_13

F10

VDDC_14

G9

VDDC_15

L10

VDDC_16

P9

VDDC_17

C9

VDDC_18

B10

VDDC_19

C10

VDDC_20

K10

VDDC_21

AB9

VDDCI

U9

VDDR3_1

W8

VDDR3_2

U10

VDDR3_3

V9

VDDR3_4

W9

VDDR3_5

AB5

PVDD

AA5

PVSS

Rialto

3

C655

C658

C C

B B

NOTE: Place REG1 close to ASIC.

REGULATOR FOR B_1.8V
Vin=+3.3V
Vout=+1.8V(150mA)

+3.3V_BUS

B37
200R

R16 18R
R18 18R

A A

Use SP6201EM5-ADJ, 200mA, SOT23-5, DO<500mV (2480041200 ) $0.11
Alt. TI TPS76301, ADJ, 150mA, DO<300mV, SOT23 (2480040800)
Alt. TI TPS76318, 1.8V, 150MA, DO<300mV, SOT23 (2480003900)

SP6201EM5-ADJ
Vo=1.25 (1+R1/R2)

3240681000, 681R, 1%

R1
R2

C107

1.0uF

+VAA_DIO

+VAA_XTL

+B_PVDD

REG1

1.8V

1

IN

3

EN

NC/FB

OUT

GND

2

TPS76301, ADJ
Vo=1.186 (1+R1/R2)

3240787000, 787R, 1%

3240150100, 1.50K, 1%3240150100, 1.50K, 1%

5

B35 200R

B36 200R

B40 200R

4
5

R169
681R

R168

1.50K

+B_1.8V

R1

603

C108

R2

10uf

603

10nF

C657
10nF

+3.3V_BUS

+B_PVDD

GND_B_PVSS

10nF

C645
10nF

C86
22uF_16V

C187
22uF

C659

C649

10nF

10nF

C650

C653

10nF

10nF

C97
10uf

C87

1.0uF

C101
100nF

4

NC

Core

GPIO

PLL

PART 3 OF 4

AGP

PCIE_PVDD_18

VDDP_1
VDDP_2
VDDP_3
VDDP_4
VDDP_5
VDDP_6
VDDP_7
VDDP_8

VDDP_9
VDDP_10
VDDP_11
VDDP_12
VDDP_13
VDDP_14
VDDP_15
VDDP_16
VDDP_17
VDDP_18
VDDP_19
VDDP_20
VDDP_21
VDDP_22
VDDP_23
VDDP_24

VDD15_1
VDD15_2
VDD15_3
VDD15_4
VDD15_5

VAA_DIO

AGND_DIO_1
AGND_DIO_2

VAA_XTL

AGND_XTL_1
AGND_XTL_2

F21
A21
B21
E21

A15
A16
A17
A18
A19

W13
Y13
Y14
W12
W14
Y16
W15
Y15
Y17

A4
E2
G2
L2
U2
W2
AB2
G5
K4
B4
T5
W5
B2
N2
E5
D8
E8
C8
H8
J8
M8
N8
R8
A2

B8
U8
A8
T9
V8

AB6

AA6
Y6

AB7

C103

AA7
Y7

100nF

<Variant Name>

2

C989
10nF

C102

1.0uF

C986
10nF

C55
10nF

+VAA_XTL

GND_XTL

C982
10nF

C988
10nF

C65
10uF_6.3V

C188
22uF

C984
10nF

C64

100nF

C981
10nF

C990
1uF

C663
10nF

C979

C978

1uF

1uF

C980

C983

1uF

1uF

C985

C987

1uF

1uF

C662

C661

10nF

10nF

+VDDC_CT

1.5V

C52

C58

100nF

10uF_6.3V

C99
100nF

NOTE: THIS IS A DRAWING. THESE
GROUNDS MUST BE MANUALLY
CONNECTED TO THE GROUND PLANE

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP R480+Rialto 256MB BGA DVII DVII VIVO

Size Document Number Rev

C

Date: Sheet

PCIE_PVDD_12_1
PCIE_PVDD_12_2
PCIE_PVDD_12_3
PCIE_PVDD_12_4

PCIE_VDDR_18_2
PCIE_VDDR_18_3
PCIE_VDDR_18_4
PCIE_VDDR_18_1

PCIE_VDDR_12_1
PCIE_VDDR_12_2
PCIE_VDDR_12_3
PCIE_VDDR_12_4
PCIE_VDDR_12_5

PCI-Express

PCIE_VDDR_12_6
PCIE_VDDR_12_7
PCIE_VDDR_12_8
PCIE_VDDR_12_9

P
O
W

AGPDIFF

E
R

Volt COV

OSC

I/O

+PCIE_VDDR_12

L85
60R

C1708
10uF_6.3V

C1710
10uF_6.3V

C660
10nF

C98

1.0uF

+PCIE_PVDD_18

C1711
10uF_6.3V

+PCIE_VDDR_12

C1713

C1712

10uF_6.3V

10uF_6.3V

+VDDQ_BUS

C677

C675

100nF

100nF

+VAA_DIO

C189
22uF

GND_DIO

GND_B_PVSS GND_DIO GND_XTL

105-A49000-00A

1

0

of

24 28Friday, January 28, 2005

www.vinafix.vn

5

4

3

2

1

U112D

D D

C C

B B

T17

L21

W17

C21
B19
C19
D18
E18
G18
H18
K18

L18
M19
N18
P18
M18
R19
T18

L16
H16
E16
B16
T15
P16
F15

L15
G17
K17
F18
U18
U12
V15
B18
B15
C15
D15
E15
G15
H15

J15
K15
M15
N15
P15
R15
U15
V18
V14
R18
A14
C13
P14

L14
F13
B14

J13
E14
M13
V12
U16
H14
U14
V13

J21
R13
A20
G21
A12
K21
B20
C20
D20
E20
F20
G20
H20

L20
T20
F19

J19
C18

J18
D17
N17
D12
G12
N12
T12
K12

V10
V11

T11
U11

W10

W7

PCIE_VSS_1
PCIE_VSS_2
PCIE_VSS_3
PCIE_VSS_4
PCIE_VSS_5
PCIE_VSS_6
PCIE_VSS_7
PCIE_VSS_8
PCIE_VSS_9
PCIE_VSS_10
PCIE_VSS_11
PCIE_VSS_12
PCIE_VSS_13
PCIE_VSS_14
PCIE_VSS_15
PCIE_VSS_16
PCIE_VSS_17
PCIE_VSS_18
PCIE_VSS_19
PCIE_VSS_20
PCIE_VSS_21
PCIE_VSS_22
PCIE_VSS_23
PCIE_VSS_24
PCIE_VSS_25
PCIE_VSS_26
PCIE_VSS_27
PCIE_VSS_28
PCIE_VSS_29
PCIE_VSS_30
PCIE_VSS_31
PCIE_VSS_32
PCIE_VSS_33
PCIE_VSS_34
PCIE_VSS_35
PCIE_VSS_36
PCIE_VSS_37
PCIE_VSS_38
PCIE_VSS_39
PCIE_VSS_40
PCIE_VSS_41
PCIE_VSS_42
PCIE_VSS_43
PCIE_VSS_44
PCIE_VSS_45
PCIE_VSS_46
PCIE_VSS_47
PCIE_VSS_48
PCIE_VSS_49
PCIE_VSS_50
PCIE_VSS_51
PCIE_VSS_52
PCIE_VSS_53
PCIE_VSS_54
PCIE_VSS_55
PCIE_VSS_56
PCIE_VSS_57
PCIE_VSS_58
PCIE_VSS_59
PCIE_VSS_60
PCIE_VSS_61
PCIE_VSS_62
PCIE_VSS_63
PCIE_VSS_64
PCIE_VSS_65
PCIE_VSS_66
PCIE_VSS_67
PCIE_VSS_68
PCIE_VSS_69
PCIE_VSS_70
PCIE_VSS_71
PCIE_VSS_72
PCIE_VSS_73
PCIE_VSS_74
PCIE_VSS_75
PCIE_VSS_76
PCIE_VSS_77
PCIE_VSS_78
PCIE_VSS_79
PCIE_VSS_80
PCIE_VSS_81
PCIE_VSS_82
PCIE_VSS_83
PCIE_VSS_84
PCIE_VSS_85
PCIE_VSS_86
PCIE_VSS_87
PCIE_VSS_88
PCIE_VSS_89

VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34

Part 4 of 4

PCI-Express GND

GPIO GND

CORE GND

AGP GND

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28

VSSP_1
VSSP_2
VSSP_3
VSSP_4
VSSP_5
VSSP_6
VSSP_7
VSSP_8

VSSP_9
VSSP_10
VSSP_11
VSSP_12
VSSP_13
VSSP_14
VSSP_15
VSSP_16
VSSP_17
VSSP_18
VSSP_19
VSSP_20
VSSP_21
VSSP_22
VSSP_23
VSSP_24
VSSP_25
VSSP_26
VSSP_27
VSSP_28
VSSP_29

M9
A10
H11
N11
T8
E10
R9
A9
E11
N10
D10
J11
D11
J9
H9
H10
M10
M11
R10
A11
N9
D9
E9
T10
J10
R11
V7
AA9

L5
D3
H2
K2
P2
T2
C6
B3
D5
H5
K3
K5
N5
U5
Y2
P5
A7
B7
D7
U7
C7
F8
G8
K8
L8
P8
A3
V6
Y5

Rialto

A A

<Variant Name>

5

4

3

2

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP R480+Rialto 256MB BGA DVII DVII VIVO

Size Document Number Rev

C

Date: Sheet

105-A49000-00A

1

of

25 28Friday, January 28, 2005

0

www.vinafix.vn

5

4

3

2

1

B_GPIO[7..0]

B_GPIO[7..0](23)

Overlap pads to save space
and to prevent assembly of

D D

both resistors.

Layout

High logic voltageGround

Signal

C C

B_GPIO[24..11](23)

B B

REFCLKBYP(23)

A A

B_GPIO[24..11]

STP_AGPB(23)

5

OPTION STRAPS

B_GPIO0

B_GPIO1

B_GPIO2

B_GPIO3

B_GPIO4

B_GPIO5

B_GPIO6

B_GPIO7

B_GPIO11

B_GPIO12

B_GPIO13

B_GPIO14

B_GPIO15

B_GPIO16

B_GPIO17

B_GPIO18

B_GPIO19

B_GPIO20

B_GPIO21

B_GPIO22

B_GPIO23

B_GPIO24

REFCLKBYP

STP_AGPB

R398 10K
R412 10K
R399 10K
R411 10K
R208 10K
R207 10K
R439 10K DNI
R441 10K
R445 10K DNI
R446 10K
R368 10K DNI
R442 10K
R366 10K DNI
R410 10K
R396 10K
R409 10K

R384 10K DNI
R406 10K
R387 10K DNI
R395 10K
R210 10K
R209 10K
R440 10K DNI
R443 10K
R447 10K DNI
R448 10K
R369 10K DNI
R444 10K
R367 10K DNI
R393 10K
R383 10K DNI
R391 10K
R415 10K DNI
R449 10K
R379 10K DNI
R418 10K
R416 10K DNI
R417 10K
R414 10K DNI
R476 10K
R413 10K DNI
R475 10K
R438 10K DNI
R450 10K

R470 10K DNI
R474 10K

R493 10K
R494 10K

+3.3V_BUS

DNI

DNI

DNI

DNI

DNI

+VDDQ_BUS

R477

R478

0R

0R

DNI

DNI

4

3

PCIE_AGP_Bridge Shared Straps

STRAPS

GPIO(0)PCIE_PTX_PWRS_ENB

PCIE_PTX_DEEMPH_EN PCI Express transmitter de-emphasis enable

PCIE_ICP (1:0)

PCIE_PTX_IEXT GPIO(4)0PCI Express transmitter extra ouptput current

PCIE_PRX_IDLE_MODE GPIO(5)0Controls sensitivity of the electrical idle detectors

PCIE_PPLL_BW GPIO(6) PCI Express PLL bandwidth setting

PCIE_REVERSE_ALL GPIO(7)10 - Don't reverse physical PCIE lanes

PCI_RETRY_ENb GPIO(8)00 - Enable all PCI read/write retry, retry cycle 0x3

MULTIFUNC

PCIE_FORCE_
COMPLIANCE

PCIE_LINK_TIMEOUT
_OVERRIDE

MOBILE_EN REFCLKBYP

BUS_PCI_CFG_
RETRY_Enb

GPIO(1)

GPIO(3:2)

GPIO(9)

GPIO(10)DEBUG_ACCESS 1 - Set the debug bus muxes to bring out debug signals even if registers are inaccessable

GPIO(24, 14)VGA_MONO_MODE(1:0)

GPIO(15)MEM_AP_SIZE

GPIO(16)

GPIO(18:17)AGPFBSKEW(1:0)

GPIO(20:19)X1CLK_SKEW(1:0)

GPIO(21)BUSCFG Control BUS type, CLK PLL select

GPIO(22)AGP_ONLY 00 - normal operation, assume VPU is working

GPIO(23)

STP_AGPB

DESCRIPTIONPIN

PCI Express transmitter power-saving enable bar
0 - 50% Tx output swing for mobile applications

1 - Full output swing

0 - de-emphasis disenable
1 - de-emphasis enable

Charge pump current setting
00 - 5.0uA

01 - 10.0uA

10 - 15.0uA

11 - 20.0uA

0 - no extra current
1 - extra current in output stage

0 - normal idle detect
1 - improve idle detect

0 - Full PLL bandwidth
1 - Reduces PLL bandwidth

1 - Reverse physical PCIE lanes

1 - Disable PCI read/write retry

If no ROM attached, comtrols chip IDis. If rom attached identifies ROM type
000 - No ROM, CHG_ID=0
001 - 512Kb Serial AT25F512 ROM (Atmel)
010 - Reserved
011 - 1M Serial M25P10A ROM (ST)

100 - 512K Serial M25P05A ROM (ST)

101 - 1M Serial SST45LF010 ROM (SST)
1M Serial W45B012 ROM (WinBond)
512K Serial W45B512 ROM (WindBond)

110 - 1M Serial SST25VF010 ROM (SST)
512K Serial SST25VF512 ROM (SST)

111 - Reserved

00 - only VGA controller
01 - only MONO controller
10 - neither VGA/MONO controller
11 - both VGA/MONO controller

Used only there is no valid ROM
0 - 128Mb(2x64Mb)
1 - 256Mb(2x128Mb)

For MULTIFUNC, when TESTEN(pin)=0,
0 = 00 - Single function device
1 = 01 - Two function device. No AGP in either function

For PCIE_FORCE_COMPLIANCE, when TESTEN(pin)=1,
0 - Normal operation
1 - Force LC into compliance mode

AGP 1xclock feedback phase adjustment wrt refclk(cpuclk)
00 - refclk slightly earlier than feedback
01 - refclk 1 tap later than feedback
10 - refclk 1 tap earlier than feedback
11 - refclk 2 tap earlier than feedback clock

Clock phase adjustment between x1clk and x2clk
00 - 0 tap delay
01 - 1 tap delay
10 - 2 tap delay
11 - 3 tap delay

1 - for debugging, shut off VPU so the bridge is working in AGP only mode

1 - Timeout is disabled

when internal MOBILE_EN=0 STRAP_BUS_PCI_CFG_RETRY_Enb

<Variant Name>

2

DEFAULT

1

1

01

0

0

0

100GPIO(13:11)ROMIDCFG(2:0)

00

0

0

0

00
internal pulldown

00
internal pulldown

0
internal pulldown

00 - Timeout is active

0

1

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP R480+Rialto 256MB BGA DVII DVII VIVO

Size Document Number Rev

C

Date: Sheet

105-A49000-00A

1

of

26 28Friday, January 28, 2005

0

www.vinafix.vn

5

4

3

2

1

D D

C C

B B

DVI SCREWS

ASSY1

SCREW

JACKSCREW

ASSY

ASSY3

SCREW

JACKSCREW

ASSY

ASSY5

SCREW

PAN_HEAD

ASSY6

BRACKET

VGA, VID OUT, DVI

ASSY11

BRACKET

80200365A0

DVI SCREWS

ASSY2

SCREW

JACKSCREW

ASSY

ASSY4

SCREW

JACKSCREW

ASSY

ASSY10

BRACKET
DUAL

DUAL, VGA, DIN, DVI

MISC. BOARD PARTS

ASSY7

BLANK
LABEL

1.50W_X_0.50H

ASSY

ASSY8

ANTISTATIC
BAG

6_X_11

ASSY

MT1
MT_Hole_0.136_in.

REF2

PCB

109-A31900-00C

REF3

ATI LOGO
LABEL

ATI_LOGO_LABEL

<Variant Name>

A A

5

4

3

2

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP R480+Rialto 256MB BGA DVII DVII VIVO

Size Document Number Rev

B

Date: Sheet

105-A49000-00A

28 28Friday, January 28, 2005

of

1

0

www.vinafix.vn