5
Title
4
3
2
1
Date:Schematic No.
AGP RV410 DV VG VIVO 256MB DDR3
105-A41800-00
REVISION HISTORY
D D
Sch
Rev
PCB
Rev
0
00A Initial release, based on A379 RV410 Pipecleaner.
00B1 Unify Chassis and Digital Gnd.
Date
06/08/04
08/10/04
REVISION DESCRIPTION
Thursday, December 23, 2004
Rev
3
Update ASIC memory VREF divider to 70%. Change R138, R149, R151, R159 to 3160100000
Update ASIC memory voltages from 1.9V to 2.1V, change R256 and R311 to 3240124100, change R253 and R310 to 3240200100
Added option for new Capacitors to input of +VDDC Regulator C1705 and alternate MC1705.
Add option for different bulk capcitors on the ouptupt of +VDDC, +MVDDC, +MVDDQ regulators. These alternates are for Polymer Caps and Throughhole
LOW ESR electrolytic caps.
C C
00C2 Change +PCIE_VDDR Regulator REG7 to RT9194 with MTD3055.
25/10/04
Add Option three resistor packs (RP207, RP208, RP210) to give option to short +MVDDC and +MVDDQ. Power bufget must be verified before implementing.
003 Add B2 to share +B_VDDC with +PCIE_VDDR_12.
5/12/04
B B
A A
5
4
www.vinafix.vn
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MEMORY CHANNEL A
Rank 1
D D
VIDEO IN
CONNECTOR
SHT 20
+12V EXT.
EXTERNAL
POWER
CONNECTOR
POWER
REGULATION
SHT 5, 6, 7, 8, 9
C C
From +12v
SINGLE PHASE SWITCHING:
VDDC, MVDDC, MVDDQ
From +12V DIRECT:
FAN
From +12V LINEAR:
+5V, RAGE THEATER
From +3.3 V LINEAR:
AVDD, VDD15, VDDRH
TPVDD, TXVDDR, PVDD,
AVDDDI, A2VDD, A2VDDDI,
A2VDDQ, PCIE_VDDR,
PCIE_PVDD_18, VDDC_CT
VDDR4, VDDR5
From +3.3 V DIRECT:
VDDR3
Rank 0
GDDRIII (144 BALL BGA)
SHT 12
MAA[14..0]
QSA[7..0]
QSA#[7..0]
CASA#
RASA#
STRAPS
Speed control
& temperature
SHT 15
sense
POWER DELIVERY
BIOS
SHT 4
FAN
SHT 15
SHT 14
ROMCS#
CLKA01
DQMA[0..7]
WEA#
CLKA01#
CSA#01MDA[63..0]
RESET
CKEA/B
MEM A MEM B
GPIO
SHEET 3 , 4, 5, 6, 10, 11
ROM
RV410
PCI-Express
DAC1
DAC2
TMDS
VIP
TVO
CRT
MAB[14..0]
MAB[14..0]
QSB[7..0]
QSB#[7..0] RESET
RASB#
CASB#
DVP
R G B HSY VSY DDC1DATA DDC1CLK
TMDS_TX[C,2..0]N TMDS_TX[C,2..0]P HPD, DDC2CLK DDC2DATA
MEMORY CHANNEL B
Rank 1
Rank 0
GDDRIII (144 BALL BGA)
SHT 13
DQMB[0..7]
CSB#01
WEB#
CKEBCLKB01
CLKB01#
External TMDS
PRIMARY CRT
FILTERS
SHEET 16
Rage Theater 1
SHT 19
TVOUT
FILTERS
SHT 20
SECONDARY
CRT FILTERS
SHT 16, 17
IMPEDANCE
MATCHING
SHT 4
DVI-I
CONN
SHT 16
TVout/
VIVO
CONN
SHT 20
DVI-I
CONN
SHT 18
ROM
PCI-Express
Rialto
GPIO
STRAPS
SHT 14
B B
POWER DELIVERY
AGP
RV410 + Rialto Pipecleaner
AGP Bus
SHT 2
A A
5
4
www.vinafix.vn
3
REV 1
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV410 DV VG VIVO 256MB DDR3
Size Docum e n t N u mb er R e v
C
2
Date: Sheet
105-A41800-00
1
3
of
127Thursday, D e cember 23, 2004
5
LAYOUT NOTE: S OME OF TH E CAPS BELOW MAY BE
REMOVED IF SPACE IS AN ISSUE, ASK BEFORE REMOVING
+12V_BUS
C12
10uF_20V
+5V_BUS +3.3V_BUS
C5
47uF_6.3V
C10
47uF_6.3V
+VDDQ_BUS
Use 47uF Tant. 16V 20% D si ze (P/ N 4230047600),
800mR Max. ESR and Max. ripple 430mA @ 100kHz
or
100uF, Alum. 6.3V 20% 6.3mm dia (P/N 4261010700),
C4
100uF_6.3V
440mR Max. ESR and Max. ripple 230mA @ 100kHz
>= 6.3V
or
47uF, Alum. 6.3V 20% 5mm dia (P/N 4262047600),
760mR Max. ESR and Max. ripple 150mA @ 100kHz
Place C2 on left side of AGP connector
D D
AGP_TYPEDET#
AGP_GC_8X_DET#
AGP_INTR#(21)
AGP_GNT#(21)
AGP_MB_8X_DET#(21)
AGP_DBI_HI(21)
AGP_WBF#(21)
AGP_SBSTB#(21)
C C
AGP_ADSTB1#(21)
AGP_FRAME#(21)
AGP_TRDY#(21)
AGP_STOP#(21)
AGP_PAR(21)
AGP_ADSTB0#(21)
B B
AGP_CON_RESET#
R7 0R
R9 0R
R1 0R
R5 0R
R12 0R
AGP_VREFGC
402
402
402
402
402
4
+3.3V_BUS
+VDDQ_BUS
AGP_ST1
AGP_MB_8X_DET#_R
AGP_DBI_HI_R
AGP_SBA1
AGP_SBA3
AGP_SBA5
AGP_SBA7
AGP_AD30
AGP_AD28
AGP_AD26
AGP_AD24
AGP_C/BE#3
AGP_AD22
AGP_AD20
AGP_AD18
AGP_AD16
AGP_PAR_R
AGP_AD15
AGP_AD13
AGP_AD11
AGP_AD9
AGP_C/BE#0
AGP_AD6
AGP_AD4
AGP_AD2
4X/8X AGP BUS
+12V_BUS
MAGP1
A1
12V
A2
TYPEDET#
A3
GC_DET#/RESERVED
A4
USB-
A5
GND
A6
INTA#
A7
RST#
A8
GNT#
A9
VCC3.3
A10
ST1
A11
MB_DET#/RESERVED
A12
DBI_HI/PIPE#
A13
GND#A13
A14
WBF#
A15
SBA1
A16
VCC3.3#A16
A17
SBA3
A18
SB_STB#
A19
GND#A19
A20
SBA5
A21
SBA7
A22
RESERVED
A23
GND#A23
A24
RESERVED#A24
A25
VCC3.3#A25
A26
AD30
A27
AD28
A28
VCC3.3#A28
A29
AD26
A30
AD24
A31
GND#A31
A32
AD_STB1#
A33
C/BE3#
A34
VDDQ1.5
A35
AD22
A36
AD20
A37
GND#A37
A38
AD18
A39
AD16
A40
VDDQ1.5#A40
A41
FRAME#
A42
KEY
A43
KEY#A43
A44
KEY#A44
A45
KEY#A45
A46
TRDY#
A47
STOP#
A48
PME#
A49
GND#A49
A50
PAR
A51
AD15
A52
VDDQ1.5#A52
A53
AD13
A54
AD11
A55
GND#A55
A56
AD9
A57
C/BE0#
A58
VDDQ1.5#A58
A59
AD_STB0#
A60
AD6
A61
GND#A61
A62
AD4
A63
AD2
A64
VDDQ1.5#A64
A65
AD0
A66
VREFGC
1.5V_AGP_BUS
OVRCNT#
5.0V#B3
USB+
GND#B5
INTB#
REQ#
VCC3.3#B9
RBF#
GND#B13
DBI_LO/RESERVED
SBA0
VCC3.3#B16
SBA2
SB_STB
GND#B19
SBA4
SBA6
RESERVED#B22
GND#B23
3.3VAUX
VCC3.3#B25
AD31
AD29
VCC3.3#B28
AD27
AD25
GND#B31
AD_STB1
AD23
VDDQ1.5#B34
AD21
AD19
GND#B37
AD17
C/BE2#
VDDQ1.5#B40
IRDY#
KEY#B42
KEY#B43
KEY#B44
KEY#B45
DEVSEL#
VDDQ1.5#B47
PERR#
GND#B49
SERR#
C/BE1#
VDDQ1.5#B52
AD14
AD12
GND#B55
AD10
VDDQ1.5#B58
AD_STB0
GND#B61
VDDQ1.5#B64
VREFCG
3
AGP_C/BE#[3..0]
AGP_AD[31..0]
AGP_SBA[7..0]
AGP_ST[2..0]
+3.3V_BUS
+5V_BUS
+VDDQ_BUS
B1
B2
5.0V
B3
B4
B5
B6
B7
CLK
B8
B9
B10
ST0
B11
ST2
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
AD8
B58
B59
B60
AD7
B61
B62
AD5
B63
AD3
B64
B65
AD1
B66
AGP_ST0
AGP_ST2
AGP_SBA0
AGP_SBA2
AGP_SBA4
AGP_SBA6
AGP_AD31
AGP_AD29
AGP_AD27
AGP_AD25
AGP_AD23
AGP_AD21
AGP_AD19
AGP_AD17
AGP_C/BE#2
AGP_C/BE#1
AGP_AD14
AGP_AD12
AGP_AD10
AGP_AD8
AGP_AD7
AGP_AD5
AGP_AD3
AGP_AD1AGP_AD0
AGP_DBI_LO_R
AGP_SBSTB_R
AGP_ADSTB1_R
AGP_ADSTB0_R
AGP_AGPREF
R8 0R
R2 0R
R10 0R
R13 0R
AGP_C/BE#[3..0] (21)
AGP_AD[31..0] (21)
AGP_SBA[7..0] (21)
AGP_ST[2..0] (21)
2
+5V_BUS
AGP_CON_RESET#
AGP_AGPCLK (21)
AGP_REQ# (21)
AGP_RB F # (21)
402
AGP_DBI _LO (21)
402
AGP_SBSTB (21)
402
AGP_ADSTB1 (21)
AGP_IRDY# (21)
AGP_DEVSEL# (21)
5
4
74ACT08MTC
6
U2B
R3 100R
+5V_BUS
14
+-U2A
1
2
74ACT08MTC
7
1
SYMBOL LEGEND
DO NOT
DNI
INSTALL
#
ACTIVE
LOW
DIGITAL
GROUND
ANALOG
GROUND
AGP_RESET# (16,18,21)
R4
180R
402
3
C1
100nF
Spare gate
402
AGP_ADSTB0 (21)
+12V_BUS
C22
100nF
402
+5V_BUS
+3.3V_BUS
C25
100nF
402 402
C24
100nF
Caps for EMI - install close to AGP connector
UNIVERSAL VREFGC CIRCUIT (4X, 8X)
TEST
+VDDQ_BUS
1
32
Q1
R20
324R
2N7002E
R21
147R
R24
100R
402
AGP_VREFGC
C6
10nF
402
Close to ASIC
2
+3.3V_BUS
1
Q20
BSN20
+5V_BUS
53
+
1
2
-U4TC7SZ08FU
3
32
+12V_BUS
C3
100nF
4
R6
20K
402402
402
R23
1K
402
AGP_TYPEDET#
AGP_GC_8X_DET#
A A
R19
5.1R
R63
0R
402
+12V, TYPEDET#
short protection
for OEM (5.1R)
R17
AGP_MB_8X_DET#(21)
AGP_MB_8X_DET#
47K
May be placed far from connector -- place C3 FAR from connector, on left side!!
5
4
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AGP_AGPREF
TEST
UNIVERSAL VREFCG CIRCUIT (4X, 8X)
+VDDQ_BUS
32
1
Q77
2N7002E
R72
147R
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV410 DV VG VIVO 256MB DDR3
Size Docum e n t N u mb er R e v
C
Date: Sheet
R75
324R
402 402402
R74
100R
DNI
R73
0R
AGP_AGPREFCG
C11
10nF
402402
Close to ASIC
*
105-A41800-00
1
AGP_AGPREFCG (21)
of
227Thursday, January 27, 2005
3
5
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NOTE: some of the PCIE testpoints will
be available trought via on traces.
D D
U1A
PETp0_GFXRp0(20)
PETn0_GFXRn0(20)
PETp1_GFXRp1(20)
PETn1_GFXRn1(20)
PETp2_GFXRp2(20)
PETn2_GFXRn2(20)
PETp3_GFXRp3(20)
PETn3_GFXRn3(20)
PETp4_GFXRp4(20)
PETn4_GFXRn4(20)
PETp5_GFXRp5(20)
PETn5_GFXRn5(20)
PETp6_GFXRp6(20)
C C
B B
PETn6_GFXRn6(20)
PETp7_GFXRp7(20)
PETn7_GFXRn7(20)
PETp8_GFXRp8(20)
PETp9_GFXRp9(20)
PETn9_GFXRn9(20)
PETp10_GFXRp10(20)
PETn10_GFXRn10(20)
PETp11_GFXRp11(20)
PETn11_GFXRn11(20)
PETp12_GFXRp12(20)
PETn12_GFXRn12(20)
PETp13_GFXRp13(20)
PETn13_GFXRn13(20)
PETp14_GFXRp14(20)
PETn14_GFXRn14(20)
PETp15_GFXRp15(20)
PETn15_GFXRn15(20)
PCIE_REFCLKP(20)
PCIE_REFCLKN(20)
PERST#(20)
+3.3V_BUS
R1007
4.7K
NI
AH31
AH30
AG30
AG32
AF32
AF31
AE31
AE30
AD30
AD32
AC32
AC31
AB31
AB30
AA30
AA32
AK28
AG24
AA24
AF24
AJ31
W31
W30
AL28
Y32
Y31
V30
V32
U32
U31
T31
T30
R30
R32
P32
P31
N31
PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N
PCIE_RX13P
PCIE_RX13N
PCIE_RX14P
PCIE_RX14N
PCIE_RX15P
PCIE_RX15N
PCIE_REFCLKP
PCIE_REFCLKN
PERSTB
PCIE_TEST
MCL_0
RV410
Clock
PART 1 OF 7
P
C
I
ÂE
X
P
R
E
S
S
I
N
T
E
R
F
A
C
E
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13P
PCIE_TX13N
PCIE_TX14P
PCIE_TX14N
PCIE_TX15P
PCIE_TX15N
Calibration
PCIE_CALRN
PCIE_CALRP
PCIE_CALI
AK27
AJ27
AJ25
AH25
AH28
AG28
AG27
AF27
AF25
AE25
AE28
AD28
AD27
AC27
AC25
AB25
AB28
AA28
AA27
Y27
Y25
W25
W28
V28
V27
U27
U25
T25
T28
R28
R27
P27
AE24
AD24
AB24
R1010 100R
R1009 150R
R1011 10K
+PCIE_VDDR
GFXTp0_PERp0 (20)
GFXTn0_PERn0 (20)
GFXTp1_PERp1 (20)
GFXTn1_PERn1 (20)
GFXTp2_PERp2 (20)
GFXTn2_PERn2 (20)
GFXTp3_PERp3 (20)
GFXTn3_PERn3 (20)
GFXTp4_PERp4 (20)
GFXTn4_PERn4 (20)
GFXTp5_PERp5 (20)
GFXTn5_PERn5 (20)
GFXTp6_PERp6 (20)
GFXTn6_PERn6 (20)
GFXTp7_PERp7 (20)
GFXTn7_PERn7 (20)
GFXTp8_PERp8 (20)
GFXTn8_PERn8 (20)PETn8_GFXRn8(20)
GFXTp9_PERp9 (20)
GFXTn9_PERn9 (20)
GFXTp10_PERp10 (20)
GFXTn10_PERn10 (20)
GFXTp11_PERp11 (20)
GFXTn11_PERn11 (20)
GFXTp12_PERp12 (20)
GFXTn12_PERn12 (20)
GFXTp13_PERp13 (20)
GFXTn13_PERn13 (20)
GFXTp14_PERp14 (20)
GFXTn14_PERn14 (20)
GFXTp15_PERp15 (20)
GFXTn15_PERn15 (20)
R1006
4.7K
A A
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV410 DV VG VIVO 256MB DDR3
Size Docum e n t N u mb er R e v
C
5
4
www.vinafix.vn
3
2
Date: Sheet
105-A41800-00
1
3
of
327Thursday, January 27, 2005
5
VID[7..0]
VID[7..0](18)
CLK_VIDCLK(18)
DVALID(13)
D D
C C
B B
C71
22pF
C79
22pF
+3.3V_BUS
B3
220R
R16251KC1522
A A
C1523
100nF
1.0uF
4170010400
CLK_RT(18)
PSYNC(13)
VHAD0(18)
VHAD1(18)
VPHCTL(18)
CLK_VIPCLK(18)
DVOMODE_0(13)
DVOMODE_1(13)
LCDCNTL_R[3..0]( 16)
VID/DVO_R[11..0](16)
DC_Strap2(13)
DC_Strap3(13,19)
DC_Strap4(13)
PAL/NTSC(13)
DEMUX_SEL(13)
GPIO[6..0](13)
GPIO[13..8](13)
HPD_ExtTMDS(16)
GPIO7(25)
GPIO15(25)
GPIO16(25)
ThermINT(14)
GPU_DPLUS(14)
GPU_DMINUS(14)
27MHZ
Y3
27_MHZ
2 1
XTAL
Oscillator Circuit
Y1
4
VCC
2
GND
27.000MHz
5
R30
1.0M
OUT
E/D
LCDCNTL_R[3..0]
VID/DVO_R[11..0]
+3.3V_BUS
+VDD_1.8V
3
1
Install close to ASIC to provide
return path for EMI
B33
NI
Bead
GND_PVSS
+MPVDD
GND_MPVSS
XTALIN
R65
NI
150R
R587499R
R586499R
+PVDD
C46
22uF_16V
4170082000
C27
22uF_16V
+3.3V_BUS
C52582pF
C45
100nF
4170010400
+3.3V_BUS +3.3V_BUS
R51
4.7K
TP12
TP13
C26
100nF
4170010400
1.0uF
C44
R64 0R
Overlap pads
C41
1.0uF
1.0uF
C43
4
VID0
VID1
VID2
VID3
MPVDD
R62
221R
LCDCNTL_R0
LCDCNTL_R1
LCDCNTL_R2
LCDCNTL_R3
VID/DVO_R0
VID/DVO_R1
VID/DVO_R2
VID/DVO_R3
VID/DVO_R4
VID/DVO_R5
VID/DVO_R6
VID/DVO_R7
VID/DVO_R8
VID/DVO_R9
VID/DVO_R10
VID/DVO_R11
TP14
R43 1K
ROMCS#
VID4
VID5
VID6
VID7
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
HPD_ExtTMDS
GPIO15
GPIO16
XTALIN
XTALOUT
R66
150R
TESTEN
R58
R60
4.7K
4.7K
DVOMODE_0
DVOMODE_1
PVDD
PVSS
MPVSS
1.0uF
C42
R61
221R
4
U1B
AF10
VID_0
AG10
VID_1
AH9
VID_2
AJ8
VID_3
AH8
VID_4
AG9
VID_5
AH7
VID_6
AG8
VID_7
AF7
VPCLK0
AH6
DVALID
AF8
PSYNC
AE10
VHAD_0
AE9
VHAD_1
AG7
VPHCTL
AF9
VIPCLK
AE13
SDA
AF13
SCL
AK4
DVOVMODE_0
AL4
DVOVMODE_1
AF2
DVPCNTL_0
AF1
DVPCNTL_1
AF3
DVPCNTL_2
AG1
DVPCLK
AG2
DVPDATA_0
AG3
DVPDATA_1
AH2
DVPDATA_2
AH3
DVPDATA_3
AJ2
DVPDATA_4
AJ1
DVPDATA_5
AK2
DVPDATA_6
AK1
DVPDATA_7
AK3
DVPDATA_8
AL2
DVPDATA_9
AL3
DVPDATA_10
AM3
DVPDATA_11
AE6
DVPDATA_12
AF4
DVPDATA_13
AF5
DVPDATA_14
AG4
DVPDATA_15
AJ3
DVPDATA_16
AH4
DVPDATA_17
AJ4
DVPDATA_18
AG5
DVPDATA_19
AH5
DVPDATA_20
AF6
DVPDATA_21
AE7
DVPDATA_22
AG6
DVPDATA_23
AD4
GPIO_0
AD2
GPIO_1
AD1
GPIO_2
AD3
GPIO_3
AC1
GPIO_4
AC2
GPIO_5
AC3
GPIO_6
AB2
GPIO_7
AC6
GPIO_8
AC5
GPIO_9
AC4
GPIO_10
AB3
GPIO_11
AB4
GPIO_12
AB5
GPIO_13
AD5
GPIO_14
AB8
GPIO_15
AA8
GPIO_16
AB7
GPIO_17
AB6
NC_22
AC8
VREFG
AG12
DPLUS
AH12
DMINUS
AJ14
PVDD
AH14
PVSS
A6
MPVDD
A5
MPVSS
AL26
XTALIN
AM26
XTALOUT
AG14
PLLTEST
AG22
TESTEN
AC7
ROMCSb
AK17
VSS_166
AJ19
VSS_167
AF18
VSS_168
AH17
VSS_169
AG17
VSS_170
AG19
VSS_171
AH19
VSS_172
RV410
www.vinafix.vn
VIP
Capture
VIP
Host
MMI2C
General
Purpose
I/O
Thermal
Diode
PLL &
XTAL
Test
ROM
PART 2 OF 7
Zoom Video Port/ VIP Host/External TMDS
3
AL9
TXCM
V
I
D
E
O
&
M
U
L
T
I
M
E
D
I
A
Integrated
TMDS
DAC / CRT
DAC2 (TV/CRT2)
Monitor
Interfa ce
GPIO8
GPIO9
GPIO10
ROMCS#
TXCP
TX0M
TX1M
TX2M
TX3M
TX4M
TX5M
TPVDD
TPVSS
TXVDDR_1
TXVDDR_2
TXVDDR_3
TXVDDR_4
TXVSSR_1
TXVSSR_2
TXVSSR_3
TXVSSR_4
TXVSSR_5
HSYNC
VSYNC
GENERICA
GENERICB
RSET
AVDD_1
AVDD_2
AVSSQ
AVSSN_1
AVSSN_2
VDD1DI
VSS1DI
H2SYNC
V2SYNC
COMP
R2SET
A2VDD_1
A2VDD_2
A2VSSN_1
A2VSSN_2
A2VDDQ
A2VSSQ
VDD2DI
VSS2DI
HPD1
DDC1DATA
DDC1CLK
DDC2DATA
DDC2CLK
DDC3DATA
DDC3CLK
GENERICC
MCL_1
VSS_175
VSS_174
VSS_173
TX0P
TX1P
TX2P
TX3P
TX4P
TX5P
R
G
B
R2
G2
B2
Y
C
7 2
5 4
6 3
8 1
AM9
AK10
AL10
AL11
AM11
AL12
AM12
AK9
AJ9
AK11
AJ11
AK12
AJ12
AM8
AL8
AJ6
AK6
AL6
AM6
AJ7
AK7
AL7
AM7
AK8
AK24
AM24
AL24
AJ23
AJ22
AK22
AF23
AL22
AL25
AM25
AK23
AK25
AJ24
AM23
AL23
AK15
AM15
AL15
AF15
AG15
AJ15
AJ13
AH15
AK14
AM16
AL16
AM17
AL17
AL14
AK13
AJ16
AJ17
AF11
AH22
AH23
AH13
AG13
AE12
AF12
AE23
AE18
AF22
AF17
AF21
RP193B33R
RP193D33R
RP193C33R
RP193A33R
R33 1K
R52 499R
AVDD
GND_AVSSQ
R55 715R
1.0uF
C35
R34 1K
+3.3V_BUS
R91
10K
SERIAL EEPROM 512K/1M
3
GND_RSET
C7
C40
1.0uF
100nF
DNI
4170010400
GND_R2SET
+VDD2DI
B8 Bead
22uF_16V
C34
C36
100nF
4170010400
ROM_SO
SI/A16
SCK/WEb
CSb
HOLD1
USE ALTERNATIVE PART : M25P05(512Kbit) (2280002700)
2
R797 330R
R796 330R
R795 330R
R794 330R
INSTALL TERMINATION RESISTORS
CLOSE TO ASIC
1.0uF
C17
C15
82pF
4170082000
TXVDDR
C9
C8
22uF_16V
82pF
4170082000
+VDD_1.8V
Ba3
B5
+AVDD
Bead
C23
22uF_16V
GND_AVSSN
+A2VDD
+VDD_1.8V
+3.3V_BUS
C80
100nF
1.0uF
DNI
C31
GND_A2VSSN
5
6
1
7
3
8
C33
100nF
4170010400
ROM_SO (21)
SI/A16 (21)
SCK/WEb (21)
CSb (21)
U11
D
C
S
HOLD
W
VCC
M25P05-VMN6T
C32
1.0uF
C37
Q
VSS
2
+TPVDD
C13
100nF
4170010400
22uF_16V
2
4
C16
22uF_16V
GND_TPVSS
C21
100nF
4170010400
1.0uF
C29
+A2VDDQ
C38
100nF
4170010400
GND_A2VSSQ
C39
22uF_16V
R44
Rk
0R
DNI
Ba2
B4
Bead
GND_TXVSSR
+VDDDI
C30
100nF
4170010400
Ba5
1
TXCM (17 )
TXCP (17)
TX0M (1 7)
TX0P (17)
TX1M (1 7)
TX1P (17)
TX2M (1 7)
TX2P (17)
+VDD_1.8V
+3.3V_BUS
R50
4.7K
R_DAC1 (15)
G_DAC1 (15)
B_DAC1 (15)
HSYNC_DAC1 (13,15)
VSYNC_DAC1 (13,15)
STEREOSYNC (19)
+VDD_1.8V
B7
C28
Bead
22uF_16V
R_DAC2 (15)
G_DAC2 (15)
B_DAC2 (15)
HSYNC_DAC2 (15)
VSYNC_DAC2 (15)
Y_DAC2 (19)
C_DAC2 (19)
COMP_DAC2 (19)
+VDD_1.8V
B9
Bead
+3.3V_BUS
+3.3V_BUS
R54
R53
4.7K
4.7K
HPD1 (17)
CRT1DDCDATA (15)
CRT1DDCCLK (15)
CRT2DDCDATA (15)
CRT2DDCCLK (15)
SDA (14,16)
SCL (14,16)
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV410 DV VG VIVO 256MB DDR3
Size Docum e n t N u mb er R e v
C
Date: Sheet
105-A41800-00
1
3
of
427Thursday, January 27, 2005
5
D D
C C
+MVDDQ
C616
1uF
+3.3V_BUS
+VDD_1.8V
+VDD_1.8V
+3.3V_BUS
+MVDDQ
C68
47uF_6.3V
C600
1uF
C64
C70
10uf
10uf
C65
10uf
C617
C618
1uF
1uF
C67
22uF_16V
DNI
DNI
B29 220R
C602
C603
C613
1uF
C620
1uF
C609
1uF
C625
1uF
C604
1uF
1uF
C611
C610
1uF
1uF
C615
C614
1uF
1uF
C622
C621
1uF
1uF
C627
C626
1uF
1uF
1.0uF
C74
C709
100nF
C75
1.0uF
C667
C669
1uF
1uF
C601
1uF
1uF
C608
1uF
C612
C73
1uF
10uf
C619
1uF
C66
C624
1.0uF
1uF
R700R
R690R
R680R
R670R
B12
220R
B14
220R
B30 220R
C668
1uF
C605
1uF
+VDDR4
4170010400
+VDDR5
C710
100nF
4170010400
C670
1uF
C623
1uF
C707
4
U1E
C1
VDDR1_1
J1
VDDR1_2
M1
VDDR1_3
R1
VDDR1_4
V1
VDDR1_5
AA1
VDDR1_6
A3
VDDR1_7
P9
VDDR1_8
J10
VDDR1_9
N9
VDDR1_10
P10
VDDR1_11
A9
VDDR1_12
Y10
VDDR1_13
P8
VDDR1_14
R9
VDDR1_15
Y9
VDDR1_16
J11
AB10
AC19
AD18
AC20
AD19
AD20
VDDR1_17
A21
VDDR1_18
M10
VDDR1_20
N10
VDDR1_21
Y8
VDDR1_22
J18
VDDR1_23
J19
VDDR1_24
K21
VDDR1_25
A12
VDDR1_26
H13
VDDR1_27
A15
VDDR1_28
J20
VDDR1_29
J13
VDDR1_30
K11
VDDR1_31
K19
VDDR1_32
A18
VDDR1_33
L23
VDDR1_34
K20
VDDR1_35
K24
VDDR1_36
L24
VDDR1_37
H19
VDDR1_38
A24
VDDR1_39
K13
VDDR1_40
J32
VDDR1_41
A30
VDDR1_42
C32
VDDR1_43
F32
VDDR1_45
L32
VDDR1_46
AB9
VDDR3_1
VDDR3_2
AA9
VDDR3_3
VDDR3_4
VDDR3_5
VDDR3_6
VDDR3_7
VDDR3_8
AJ5
VDDR4_1
AM5
VDDR4_2
AL5
VDDR4_3
AK5
VDDR4_4
AE2
VDDR5_1
AE3
VDDR5_2
AE4
VDDR5_3
AE5
VDDR5_4
A27
VDDRH0
F1
VDDRH1
A28
VSSRH0
E1
VSSRH1
RV410
C607
C606
1uF
1uF
C69
1uF
C708
1uF
1uF
C676
1uF
Clock
Memory I/O
Memory
I/O
PART 5 OF 7
I/0
3
C981
1uF
R714.7K
+PCIE_PVDD_12
C970
1uF
C982
1uF
C632
1uF
C637
1uF
C61
10uf
+A2VDD
1uF
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDD15_1
VDD15_2
VDD15_3
VDDCI_1
VDDCI_2
VDDCI_3
VDDCI_4
VDDCI_5
VDDCI_6
VDDCI_7
VDDCI_8
VDDL0
VDDL0_1
VDDL0_2
VDDL0_3
VDDL1_1
VDDL1_2
VDDL1_3
VDDL2_1
VDDL2_2
VDDL2_3
V23
N23
P23
U23
N29
N28
N27
N26
N25
AL31
AM31
AM30
AL32
AL30
AM28
AL29
AM29
AM27
AC11
AC12
P14
U15
W14
W15
R17
R15
V15
V16
T16
U16
T17
U17
V14
R18
T18
V18
P18
P19
R19
W19
AD11
AC13
AC16
AC18
W10
T14
W17
P16
AC15
T23
K14
U19
AE19
AF20
AE20
AF19
AC21
AC22
AD22
AE21
AD21
AE22
+PCIE_VDD R_12
+VDD_1.8V
PCIE_PVDD_12_1
PCIE_PVDD_12_2
PCIE_PVDD_12_3
PCIE_PVDD_12_4
PCIE_PVDD_18_1
PCIE_PVDD_18_2
PCIE_PVDD_18_3
PCIE_PVDD_18_4
PCIE_PVDD_18_5
PCIE_VDDR_12_1
PCIE_VDDR_12_2
PCIE_VDDR_12_3
PCIE_VDDR_12_4
PCIE_VDDR_12_5
PCIE_VDDR_12_6
PCIE_VDDR_12_7
PCI-Express
PCIE_VDDR_12_8
PCIE_VDDR_12_9
P
O
W
E
R
I/O Internal Core
2
B27 200R
C978
C633
1uF
C638
1uF
C62
10uf
C979
1uF
1uF
C971
C976
1uF
1uF
C972
C973
1uF
1uF
C634
1uF
C639
1uF
C59
2.2uF
C49
C50
1uF
1uF
C646
C648
1uF
1uF
C977
1uF
C974
1uF
C983
1uF
C48
C1675
10uF_6.3V
C1668
10uF_6.3V
C635
1uF
C640
1uF
C968
1uF
+VDDC_CT
C60
10uf
C1703
10uF_6.3V
C1704
10uF_6.3V
C1702
10uF_6.3V
C636
1uF
C641
1uF
C63
10uF_10V
+VDDC+3.3V_BUS
+PCIE_PVDD_18
+VDDC
C642
1uF
B23 60R
C644
1uF
+PCIE_VDDR
+PCIE_VDDR
1
B B
A A
5
GND_VSSRH0 GND_VSSRH1
U1G
Forward
Compatibility
Y23
BBN_4
K15
BBN_3
R10
BBN_2
AC17
BBN_1
AC14
BBP_4
M23
BBP_3
V10
BBP_2
K18
BBP_1
L10
VDD25B_1
K22
VDD25B_2
AA10
VDD25A
RV410
4
www.vinafix.vn
PART 7 OF 7
No Connect
AD12
NC_0
AE11
NC_1
GENERICD
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
3
AD23
AJ21
AK21
AH21
AG21
AG20
AH20
AK20
AJ20
AG18
AH18
AK19
AL19
AL20
AM20
AL21
AM21
AK18
AJ18
AL18
AM18
TP11
35mil
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV410 DV VG VIVO 256MB DDR3
Size Docum e n t N u mb er R e v
C
2
Date: Sheet
105-A41800-00
1
3
of
527Thursday, January 27, 2005
5
GND_TPVSS
GND_MPVSS GND_A2VSSN
GND_PVSS
GND_AVSSN
NOTE: THIS IS A DRAWING. THESE
GROUNDS MUST BE MANUALLY
CONNECTED TO THE GROUND PLANE
D D
C C
B B
A A
GND_TXVSSR
5
GND_A2VSSQ
GND_AVSSQ
GND_RSET
GND_R2SET
GND_VSSRH1
GND_VSSRH0
GND_RT
GND_VIN
GND_TVVSSN
4
U1F
AH27
PCIE_VSS_1
AC23
PCIE_VSS_2
AL27
PCIE_VSS_3
R23
PCIE_VSS_4
P25
PCIE_VSS_5
R25
PCIE_VSS_6
T26
PCIE_VSS_7
U26
PCIE_VSS_8
W26
PCIE_VSS_9
Y26
PCIE_VSS_10
AB26
PCIE_VSS_11
AC26
PCIE_VSS_12
AD25
PCIE_VSS_13
AE26
PCIE_VSS_14
AF26
PCIE_VSS_15
AD26
PCIE_VSS_16
AG25
PCIE_VSS_17
AH26
PCIE_VSS_18
AC28
PCIE_VSS_19
Y28
PCIE_VSS_20
U28
PCIE_VSS_21
P28
PCIE_VSS_22
AH29
PCIE_VSS_23
AF28
PCIE_VSS_24
V29
PCIE_VSS_25
AC29
PCIE_VSS_26
W27
PCIE_VSS_27
AB27
PCIE_VSS_28
V26
PCIE_VSS_29
AJ26
PCIE_VSS_30
AJ32
PCIE_VSS_31
AK29
PCIE_VSS_32
P26
PCIE_VSS_33
P29
PCIE_VSS_34
R29
PCIE_VSS_35
T29
PCIE_VSS_36
U29
PCIE_VSS_37
W29
PCIE_VSS_38
Y29
PCIE_VSS_39
AA29
PCIE_VSS_40
AB29
PCIE_VSS_41
AD29
PCIE_VSS_42
AE29
PCIE_VSS_43
AF29
PCIE_VSS_44
AG29
PCIE_VSS_45
AJ29
PCIE_VSS_46
AK26
PCIE_VSS_47
AK30
PCIE_VSS_48
AG26
PCIE_VSS_49
N30
PCIE_VSS_50
R31
PCIE_VSS_51
AF30
PCIE_VSS_52
AC30
PCIE_VSS_53
V31
PCIE_VSS_54
P30
PCIE_VSS_55
AA31
PCIE_VSS_56
U30
PCIE_VSS_57
AD31
PCIE_VSS_58
AK32
PCIE_VSS_59
AJ28
PCIE_VSS_60
Y30
PCIE_VSS_61
AJ30
PCIE_VSS_62
AK31
PCIE_VSS_63
AA23
PCIE_VSS_64
AG31
PCIE_VSS_65
N24
PCIE_VSS_66
W23
PCIE_VSS_67
AB23
PCIE_VSS_69
P24
PCIE_VSS_70
R24
PCIE_VSS_71
T24
PCIE_VSS_72
U24
PCIE_VSS_73
V24
PCIE_VSS_74
W24
PCIE_VSS_75
Y24
PCIE_VSS_76
AC24
PCIE_VSS_77
AH24
PCIE_VSS_78
V25
PCIE_VSS_79
AA25
PCIE_VSS_80
R26
PCIE_VSS_81
AA26
PCIE_VSS_82
T27
PCIE_VSS_83
AE27
PCIE_VSS_84
B1
VSS_1
H1
VSS_2
L1
VSS_3
P1
VSS_4
U1
VSS_5
Y1
VSS_6
AD7
VSS_7
AE8
VSS_8
AL1
VSS_9
A2
VSS_10
AM2
VSS_11
AD10
VSS_12
E8
VSS_13
H5
VSS_14
K10
VSS_15
M8
VSS_16
T10
VSS_17
E12
VSS_18
AC9
VSS_19
AF14
VSS_20
AD8
VSS_21
C5
VSS_22
F10
VSS_23
J3
VSS_24
L6
VSS_25
M6
VSS_26
P6
VSS_27
AA4
VSS_28
AG11
VSS_29
V3
VSS_30
AG16
VSS_31
R3
VSS_32
C6
VSS_33
C9
VSS_34
F6
VSS_35
H7
VSS_36
J6
VSS_37
RV410
4
Part 6 of 7
PCI-Express GND
CORE GND
www.vinafix.vn
3
AD16
VSS_45
AA6
VSS_44
P7
VSS_43
P5
VSS_42
M3
VSS_41
M9
VSS_40
L7
VSS_39
M7
VSS_38
AD17
VSS_47
AH11
VSS_48
A8
VSS_49
U7
VSS_50
C10
VSS_51
E9
VSS_52
F3
VSS_53
J9
VSS_54
N7
VSS_55
N3
VSS_56
Y5
VSS_57
AM13
VSS_58
AC10
VSS_59
Y6
VSS_60
U6
VSS_61
E5
VSS_62
AL13
VSS_63
A11
VSS_64
U8
VSS_65
U9
VSS_66
U10
VSS_67
R6
VSS_68
AD6
VSS_69
V6
VSS_70
AD14
VSS_71
AD13
VSS_72
D11
VSS_73
J12
VSS_74
K12
VSS_75
A13
VSS_77
F13
VSS_78
E13
VSS_79
F15
VSS_80
K16
VSS_81
J21
VSS_82
H16
VSS_83
T15
VSS_84
V17
VSS_85
C15
VSS_86
C4
VSS_87
U14
VSS_88
P15
VSS_89
A16
VSS_90
E16
VSS_91
G13
VSS_92
G16
VSS_93
P17
VSS_94
R16
VSS_95
R14
VSS_97
W16
VSS_98
C18
VSS_99
F16
VSS_100
W18
VSS_101
U18
VSS_102
AE16
VSS_103
AE17
VSS_104
A19
VSS_105
H32
VSS_106
F19
VSS_107
G19
VSS_108
N8
VSS_109
Y7
VSS_110
T19
VSS_112
V19
VSS_113
G21
VSS_114
C21
VSS_115
F21
VSS_116
AE14
VSS_117
AK16
VSS_118
U5
VSS_119
F22
VSS_120
F18
VSS_121
K30
VSS_122
C24
VSS_124
F24
VSS_125
M24
VSS_126
A25
VSS_127
D30
VSS_128
E25
VSS_129
G25
VSS_130
G20
VSS_131
G22
VSS_132
F27
VSS_133
E28
VSS_134
H21
VSS_135
C27
VSS_136
E32
VSS_137
H28
VSS_138
J30
VSS_139
K17
VSS_140
K27
VSS_141
M32
VSS_142
A22
VSS_143
C20
VSS_144
E19
VSS_145
H20
VSS_146
J24
VSS_147
M28
VSS_148
J28
VSS_149
J16
VSS_150
F30
VSS_151
K23
VSS_152
L29
VSS_153
A31
VSS_154
B32
VSS_155
E30
VSS_156
AE15
VSS_157
AG23
VSS_158
AD9
VSS_159
AF16
VSS_160
AH10
VSS_161
AJ10
VSS_163
AD15
VSS_164
AH16
VSS_165
3
2
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV410 DV VG VIVO 256MB DDR3
Size Docum e n t N u mb er R e v
C
2
Date: Sheet
1
105-A41800-00
1
3
of
627Thursday, January 27, 2005
8
7
6
CORE REGULATOR VDDC
5
4
3
2
TP1
I_VDDC_LOOP
TP2
1
Current loop to measure
VDDC output current.
D D
+5V_BUS
+12V_BUS
R1589
R1591
0R
2R2
D28
BAT54SLT1
BST3
R1595
0R
BOOT_VDDC3
DNI
C1151
0.22uF
SS_VDDC3
Fb_VDDC3
COMP_VDDC3
C1157
C1692
1uF
22nf
UVIN3
SWN3
VCC3
Alternative 2
C C
Alternative 1
R1598 51K
+PW_VDDC3
R1602 3K
SS_VDDC3
COMP_VDDC3
B B
U43
7
BST
SS
GH
4
Vfb
5
GND
COMP
6
GL
UVIN
8
Vcc
SWN
SP6132
SIPEX SP6132
R1686 10K
MU43
1
RT
2
OCSET
3
SS
4
COMP
5
FB
6
EN
7
GND
ISL6522CB
ISL6522CB : SOIC
ISL6522CV : TSSOP
10
9
3
2
1
VCC
PVCC
LGATE
PGND
BOOT
UGATE
PHASE
UGATE3
LGATE3
BST3
VCC3
14
13
12
11
10
9
8
C1688 100nF
10nF
C1689
+12V_BUS
BOOT_VDDC3Fb_VDDC3
R1619
10R
C1690
1uF
SWN3
+3.3V_BUS
R873
10K
DNI
R1594
10K
DNI
R1618
2.2R
Q28
Thermal
Pad
FDS7096N3
Q29
Thermal
Pad
4 5
3
2
1
FDS7096N3
9
6
7
8
9
6
7
8
C1159
1nF
4 5
3
2
1
Lower MOSFET should be surrounded by
a lot of copper for heat dissipation
+PW_VDDC3
Q30
Thermal
Pad
4 5
3
2
1
FDS7096N3
Q31
Thermal
Pad
4 5
3
2
1
FDS7096N3
C1149
C1532
1.0uF
9
6
7
8
9
6
7
8
C1146
10uF
10uF
DNI DNI
L63
HC1213
Fb_VDDC3
C1148
C1147
10uF
10uF
This trace must be
manully shorted in layout.
It is present to
prevent feedback to
be taken at the wrong
place.
C1158
1nf
DNI
Cc1
R1617
1.5K
DNI
Rc4
POWER SEQUENCING CIRCUIT:
+3.3V_BUS
FOR ALTERNATE #1
Remove R374, R375, R371, C168 and U32
Install R370 , R112, R954, R305-R308, C160
C159 and MU32
Rv1
R1592
10K
1%
Rv2
R1597
16.5K 1%
R1581
5.1K
R1582
2.4K
Dual footprint Dual footprintDNI
C1705
180uF_16V
VR1
1K
DNI
1
Q7
CMPT3904
2
1 3
+12V_BUS
R1583
20K
CMPT3904
2 3
180uF_16V
DNI
1
Q8
MC1705
2 3
SS_VDDC3
C1709
MC1709
180uF_16V
470uF_10V
DNI
C1152
330uF_2.5V
+VDDC
1.28V
1.344V
DESIGN NOTES:
Add this Capacitor for SP6132
Compensation Circuit
Cc2
FOR ALTERNATE #2
Change C157 for 10 uF and C121 for 1 uF
Replace C764 by 0 Ohm resistor
Replace R314 with a bead
Remove R954, R370, R305-R308, C159,
R112, C160 and MU32
Install R374, R375, R371, C168 and U32
D40
21
S3AB
B1 60R
R1593
UVIN3
220K
R1632
100K
+VDDC
1.3V
C1153
330uF_2.5V
C1154
330uF_2.5V
C1155
470uF_10V
DNI
Dual footprint
Rv1
( R1592 )
3240100200, 10K, 1%, 603 3240147200, 14.7K, 1 %, 603
C1164
100pF
Cc4
COMP_VDDC3
C1163
33pF
C1161
10nF
R1580
15K
Rc5
3240165200, 16.5K, 1%, 6033240100200, 10K, 1%, 603
COMP_VDDC3
Cc3
Fb_VDDC3
Rv2
( R1597 )
+12V_BUS
+12VEXT
MC1155
470uF
Compensation circuit
A A
Rc1 = 10K, Rc2 = 8.06K
R313 = 93.1K, C171 = 3.9 nF, C170 = 10 pF
<Variant Name>
8
7
6
5
www.vinafix.vn
4
3
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV410 DV VG VIVO 256MB DDR3
Size Docum e n t N u mb er R e v
C
Date: Sheet
2
105-A41800-00
of
727Thursday, January 27, 2005
1
3
8
+5V_BUS
+12V_BUS
R373
R372
2R2
0R
DNI
BAT54SLT1
D D
C136
0.22uF
DNI
C141
22nf
C142
1uF
Alternative 1
+PW_VDDC1
SS_VDDC1
COMP_VDDC1
Fb_VDDC1
C C
MVDDQ Switching Regulator for
Memory Core for 256M
configuration
8A Max
D4
BST1
R376
0R
BOOT_VDDC1
SS_VDDC1
Fb_VDDC1
COMP_VDDC1
UVIN1
SWN1 VCC1
VCC1
Alternative 2
R258 51K
R259 3K
U31
7
SS
4
Vfb
5
COMP
6
UVIN
8
SWN
SP6132
SIPEX SP6132
MU31
1
RT
2
OCSET
3
SS
4
COMP
5
FB
6
EN
7
GND
ISL6522CB
ISL6522CB : SOIC
BST
GH
GND
GL
Vcc
R257 10K
LGATE
UGATE
PHASE
PVCC
PGND
BOOT
7
SWN1
C122 1.0uF
R251
+3.3V_BUS
14
13
12
11
10
9
8
10R
10nF
C765
+12V_BUS
BOOT_VDDC1
C113
1uF
R953
10K
DNI
R952
10K
DNI
BST1
10
UGATE1
9
3
LGATE1
2
1
VCC
6
+5VEXT
Dual footprint
C1708
180uF_16V
3000mA
Q24
4 5
3
2
1
Q22
4 5
3
2
1
IRF7413A
Fb_VDDC1
R255
2.2R
Lower MOSFET should be surrounded by
a lot of copper for heat dissipation
IRF7413A
C116
1nF
6
7
8
6
7
8
MC1708
470uF_10V
1230mA
DNI
+PW_VDDC1
L65
1.5uH
C110
1nf
DNI
R254
1.5K
DNI
C1683
100nF
B21 6 0R
Cc1
Rc4
C137
10uF
Rq1
R253
2K
1%
Rq2
R256
1.24K
1%
5
R377 220K
C138
10uF
VR2
C106
1K
13
22uF
DNI
2
TP3
I_MVDDC_LOOP
TP4
Current loop to measure
MVDDQ output current.
C105
22uF
R378
100K
C104
22uF
DNI
UVIN1
4
C1711
470uF_10V
Dual footprint
MC1711
470uF
DNI
+MVDDQ
( 2.1V )
C1707
470uF_10V
Dual footprint
3
POWER SEQUENCING CIRCUIT:
+MVDDC
MC1707
470uF
FOR ALTERNATE #1
DNI
Install R372, D4, R376, C113, R257,
R258, R259, MU31, R255 and C116
Remove R373, R377, R378, C122,
C140 and U31
2.09V
+12V_BUS
R250
2K
1
R249
Q9
2.4K
CMPT3904
Rq1
3240200100, 2K, 1% 3240124100, 1.24K, 1%
R248
20K
CMPT3904
2 3
2
1
DESIGN NOTES:
Add this Cap ac ito r for ALTERNATE #2
COMP_VDDC1
SS_VDDC1
1
2 3
Q10
C140
100pF
Compensation Circuit
COMP_VDDC1
C111
Rc5
C112
100nF
33pF
R264
15K
Cc2
Cc3
Fb_VDDC1
FOR ALTERNATE #2
Change C142 for 10uF
Install R377, R378, R373, C122, C140
and U31
Remove R255, C116, R372, R376, D4,
MU31, R257, R258, R259 and C113
Compensation circuit
Rc1 = 10K, Rc2 = 8.06K
R264 = 41.2K, C111 = 27 pF
Rq2+MVDDQ
+5V_BUS
+5V_BUS
+12V_BUS
R370
R371
0R
2R2
DNI
D5
BAT54SLT1
B B
DNI
C158
0.22uF
C169
22nf
C157
1uF
Alternative 1
+PW_VDDC2
SS_VDDC2
COMP_VDDC2
A A
8
MVDDC Switching Regulator for
Memory Core for 256M
configuration
BST2
R112
0R
BOOT_VDDC2
Fb_VDDC2
COMP_VDDC2
UVIN2
SWN2
VCC2
Alternative 2
R305 51K
R306 3K
7
4
5
6
8
U32
SP6132
10
BST
SS
9
GH
Vfb
3
GND
COMP
2
GL
UVIN
1
Vcc
SWN
SIPEX SP6132
R307 10K
MU32
1
2
3
4
5
6
7
VCC
RT
OCSET
PVCC
SS
LGATE
COMP
PGND
FB
BOOT
EN
UGATE
GND
PHASE
ISL6522CB
ISL6522CB : SOIC
ISL6522CV : TSSOP
UGATE2
LGATE2
7
BST2
VCC2
14
13
12
11
10
9
8
BOOT_VDDC2Fb_VDDC2
B46
60R
5
C163
10uF
Rc1
R310
2K
1%
Rc2
R311
1.24K
1%
Dual footprint
C1710
180uF_16V
DNI
VR3
13
1K
2
+PW_VDDC2
71
C121 100nF
10nF
C764
+12V_BUS
SWN2
R314
10R
+3.3V_BUS
R955
DNI
10K
R954
DNI
10K
C159
1uF
+MVDDQ +MVDDC +MVDDQ +M VDDC +MVDDQ +MVDDC
RP207A 0R
RP207B 0R
RP207C 0R
RP207D 0R
8
MQ23A
2
BSO4804
L66
3.3uH
53
6
MQ23B
4
BSO4804
Fb_VDDC2
C160
R308
1nF
2.2R
81
72
63
54
DNI DNI DNI
6
C172
C1684
10uF
100nF
C161
1nf
Cc1
DNI
R309
Rc4
1.5K
DNI
RP208A 0R
81
RP208B 0R
72
RP208C 0R
63
RP208D 0R
54
www.vinafix.vn
R374
C164
22uF
220K
81
72
63
54
MC1710
470UF
RP210A 0R
RP210B 0R
RP210C 0R
RP210D 0R
C165
22uF
UVIN2
R375
100K
C166
22uF
4
2.09V
+MVDDC
( 2.1V )
C1706
470uF_10V
Dual footprint
FOR ALTERNATE #1
Remove R374, R375, R371, C168 and U32
Install R370 , R112, R954, R305-R308, C160
C159 and MU32
Rc1
3240200100, 2K, 1% 3240124100, 1.24K, 1%
MC1706
470uF
DNI
3
Rc2+MVDDC
<Variant Name>
TP5
I_MVDDQ_LOOP
TP6
Current loop to measure
MVDDC output current.
DESIGN NOTES:
Add this Capacitor for SP6132
Compensation Circuit
Cc2
Rc5
C171
10nF
COMP_VDDC2
C168
100pF
Cc4
COMP_VDDC2SS_VDDC2
C170
Cc3
33pF
Fb_VDDC2
R313
15K
FOR ALTERNATE #2
Change C157 for 10 uF and C121 for 1 uF
Replace C764 by 0 Ohm resistor
Replace R314 with a bead
Remove R954, R370, R305-R308, C159,
R112, C160 and MU32
Install R374, R375, R371, C168 and U32
Compensation circuit
Rc1 = 10K, Rc2 = 8.06K
R313 = 93.1K, C171 = 3.9 nF, C170 = 10 pF
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV410 DV VG VIVO 256MB DDR3
Size Docum e n t N u mb er R e v
C
Date: Sheet
2
105-A41800-00
1
827Thursday, January 27, 2005
3
of
5
4
3
2
1
R1
R171
301R
R2
R170
1.50K
VDDC_CT
+VDDC_CT
C126
10uf
+1.5V Regulator for VDDC_CT (VDD15)
Vin=+3.3V
+1.8V Regulator
D D
C C
+3.3V_BUS
B10
42r@100MHz
REG2
LT1117CST
IN3OUT
C135
C134
100nF
22uF_16V
* R129, 3160121000, 121R, 1%, 402
R126, 316053R600, 53.6R, 1%, 402
+3.3V_BUS
B24
200R
1
1uF
3
C145
GND_A2VSSN GND_A2VSSN
REG3
VIN
SHDN
2.5V
CASE
ADJ
1
BYPASS
GND
2
VOUT
2
4
5
4
R129
1.50K
1%
R126
681R
1%
REGULATOR
FOR
A2VDD(+2.5V)
+A2VDD
1uF
C146
C147
470pF
DNI
C131
100nF
+VDD_1.8V
C132
100uF_16V
B25 200R
3 2
AS432S
MREG4
REGULATOR
FOR PVDD
(+1.8V)
Max: 55 mA Max: 20 mA Max: 20 mA
R139
27R
+PVDD
R140
681R
1%
1
R141
1.50K
1%
4
NC
1
NC
2
GND_PVSS
5 3
REG4
SC431LC5SK-1
+3.3V_BUS+3.3V_BUS +3.3V_BUS
B15 200R
R143
R145
681R
AS432S
1%
1
R147
MREG6
1.50K
3 2
1%
REGULATOR
FOR TPVDD
(+1.8V)
75R
REG6
4
SC431LC5SK-1
NC
1
NC
2
5 3
B26 2 00R
AS432S
1
MREG5
3 2
R142
R144
681R
1%
R146
1.50K
1%
REGULATOR
FOR
MPVDD(+1.8V)
75R
+MPVDD+TPVDD
4
NC
1
NC
2
5 3
GND_MPVSSGND_TPVSS
Vout=+1.5V( 100m A)
+3.3V_BUS
C114
1.0uF
REG14
1.8V
1
IN
3
EN
TPS76301, ADJ
Vo=1.186 (1+R1/R2)
3240402000, 402R, 1%
3240150100, 1.50K, 1%3240150100, 1.50K, 1%
B45
200R
R11 20R
R14 20R
use 3200020000,
20R, 1/8W, 1206,
Use SP6201EM5-ADJ, 200mA, S OT 23-5, DO< 500m V (2480041200 ) $0.11
Alt. TI TPS76301, ADJ, 150mA, SOT 23, DO <300m V (2480040800)
Alt. SP6201EM5-1.5, 200mA, SOT23-5, DO<500mV (2480041300 ) $0.11
Alt. AP131, 1 .5V, 300mA, SOT23-5L, DO<400m V,
SP6201EM5-ADJ
Vo=1.25 (1+R1/R2)
3240301000, 301R, 1%
R1
R2
REG5
SC431LC5SK-1
4
NC/FB
5
OUT
GND
2
603
603
B B
+3.3V_BUS
Regulator for PCIE_PVDD_18
Vout = 1.8V
Iout = 800mA MAX
B11
42r@100MHz
REG10
LT1117CST
IN3OUT
C143
C139
100nF
22uF_16V
Put copper under REG10 for heat dissipation.
Use SPX2810AM3, ADJ, 1A, SOT223, DO<1.2V (2480041400 ) $0.11
Alt. LX8117B-00CST, ADJ, 1.2A, SOT-223, DO<1.3V (2480041100)
Alt. FAN1117AS, ADJ, 1A, SOT-223, DO<1.2V (2480041000, PL9)
Alt. FAN11 1 7A S-1.8V , 1A, S OT -223, DO< 1.2V (2480020000, P L4), $0.13
Alt. LX8117A-00CST, ADJ, 1A, SOT-223, DO< 1.3V (2480002100, P L1), $0.25
Alt. AP1117 , A D J , 1 A , S OT - 22 3, D O< 1 .4 V, U se +5V_BU S Input Only, $0.10
A A
5
2
4
CASE
ADJ
1
R130
1.50K
1% 402
R131
C958
681R
10uf
1% 402 1% 402 1% 402
+PCIE_PVDD_18
C980
22uF
4
C984
47uF
6.3v
ESR 0.25ohm
C957
10uf
* R130, 3160121000, 121R, 1%, 402
R131, 316053R600, 53.6R, 1%, 402
Regulator for PCIE_VDDR
Vout = 1.2V
Iout = 2400mA MAX
+12V_BUS+5V_BUS
C184
1
2
3
REG7
EN
GND
FB
RT9194CE
1.0uF
PGOOD
VCC
DRI
6
5
4
R109 1.0K
R113
1.0K
PCIE_VDDR_EN
R111 2K
Note:
Place 1sq. In Copper Area under Q35, Q36
for heat dissipation.
www.vinafix.vn
MTD3055
12A, 60V
2.1W PD @ ambient temp
25'C with min pad size
Rds(on)=0.15R
Vdrop(min)=0.36V
Q35
MTD3055V
1
3 2
Ry1Ry2
+PCIE_VDDR
PCIE Power
3
+MVDDQ=2.1V~1.8V
Vdrop=0.9V~0.6V
Wdp=2.16W~1.44W
Q36
MTD3055V
4
4
1
3 2
DNI
3160200100, 2.0K, 1%1.2V 3160100100, 1.0K, 1%
C152
100nF
C185
22uF_6.3V
Ry2Ry1
+MVDDQ
42r@100MHz
100uF_16V
+PCIE_VDDR
L82
C133
C144
330uF_2.5V
+PCIE_PVDD_18 +12V_BUS
R496
R437
20K
402
1.5K
Rq3
CMPT3904
Q158
1
2 3
R436
Rq4
2.4K
DNI
2
PCIE PWR SEQUENCE
Circuit to hold PCI-E voltage low
wait for +VDDC for proper power sequence
PCIE_VDDR_EN
R1443
0R
1
Q157
2 3
CMPT3904
Rq5
Rq6
+12V_BUS+PCIE_VDD R_12
R506
1.5K
Q161
CMPT3904
1
R505
2.4K
DNI
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV410 DV VG VIVO 256MB DDR3
Size Docum e n t N u mb er R e v
C
Date: Sheet
R1444
R503
20K
402
1
2 3
2 3
0R
Q162
CMPT3904
105-A41800-00
1
B_VDDC_EN (25)
DNI
927Thursday, January 27, 2005
of
3
5
4
3
2
1
RV410 MEMORY CHANNELS A and B
D D
MDA[63..0]
MDA[63..0](11,12)
C C
+MVDDQ
R137
40.2R
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
Set VREF divider to 70%
B B
+MVDDQ
R138
100R
R148
40.2R
R149
100R
C149
100nF
4170010400
C148
100nF
4170010400
U1C
M31
DQA_0
M30
DQA_1
L31
DQA_2
L30
DQA_3
H30
DQA_4
G31
DQA_5
G30
DQA_6
F31
DQA_7
M27
DQA_8
M29
DQA_9
L28
DQA_10
L27
DQA_11
J27
DQA_12
H29
DQA_13
G29
DQA_14
G27
DQA_15
M26
DQA_16
L26
DQA_17
M25
DQA_18
L25
DQA_19
J25
DQA_20
G28
DQA_21
H27
DQA_22
H26
DQA_23
F26
DQA_24
G26
DQA_25
H25
DQA_26
H24
DQA_27
H23
DQA_28
H22
DQA_29
J23
DQA_30
J22
DQA_31
E23
DQA_32
D22
DQA_33
D23
DQA_34
E22
DQA_35
E20
DQA_36
F20
DQA_37
D19
DQA_38
D18
DQA_39
B19
DQA_40
B18
DQA_41
C17
DQA_42
B17
DQA_43
C14
DQA_44
B14
DQA_45
C13
DQA_46
B13
DQA_47
D17
DQA_48
E18
DQA_49
E17
DQA_50
F17
DQA_51
E15
DQA_52
E14
DQA_53
F14
DQA_54
D13
DQA_55
H18
DQA_56
H17
DQA_57
G18
DQA_58
G17
DQA_59
G15
DQA_60
G14
DQA_61
H14
DQA_62
J14
DQA_63
C31
MVREFD_0
C30
MVREFS_0
RV410
Channel A
Part 3 of 7
MEMORY INTERFACE A
DDR1 DDR2 DDR3
bidir. differential strobe
Not used bidir. strobe
For DDR2
write strobe read strobe
MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13
MAA_14
MAA_15
DQMAb_0
DQMAb_1
DQMAb_2
DQMAb_3
DQMAb_4
DQMAb_5
DQMAb_6
DQMAb_7
QSA_0
QSA_1
QSA_2
QSA_3
QSA_4
QSA_5
QSA_6
QSA_7
QSA_0B
QSA_1B
QSA_2B
QSA_3B
QSA_4B
QSA_5B
QSA_6B
QSA_7B
ODTA
ODTA1
CLKA0
CLKA0b
CKEA0
RASA0b
CASA0b
WEA0b
CSA0b_0
CSA0b_1
CLKA1
CLKA1b
CKEA1
RASA1b
CASA1b
WEA1b
CSA1b_0
CSA1b_1
U1D
B12
DQB_0
C12
DQB_1
B11
DQB_2
C11
DQB_3
C8
DQB_4
B7
DQB_5
C7
DQB_6
B6
DQB_7
F12
DQB_8
D12
DQB_9
E11
DQB_10
F11
DQB_11
F9
DQB_12
D8
DQB_13
D7
DQB_14
F7
DQB_15
G12
DQB_16
G11
DQB_17
H12
DQB_18
H11
DQB_19
H9
DQB_20
E7
DQB_21
F8
DQB_22
G8
DQB_23
G6
DQB_24
G7
DQB_25
H8
DQB_26
J8
DQB_27
K8
DQB_28
L8
DQB_29
K9
DQB_30
L9
DQB_31
K5
DQB_32
L4
DQB_33
K4
DQB_34
L5
DQB_35
N5
DQB_36
N6
DQB_37
P4
DQB_38
R4
DQB_39
P2
DQB_40
R2
DQB_41
T3
DQB_42
T2
DQB_43
W3
DQB_44
W2
DQB_45
Y3
DQB_46
Y2
DQB_47
T4
DQB_48
R5
DQB_49
T5
DQB_50
T6
DQB_51
V5
DQB_52
W5
DQB_53
W6
DQB_54
Y4
DQB_55
R8
DQB_56
T8
DQB_57
R7
DQB_58
T7
DQB_59
V7
DQB_60
W7
DQB_61
W8
DQB_62
W9
DQB_63
B3
MVREFD_1
C3
MVREFS_1
AA3
DRAM_RST
AA5
TEST_MCLK
AA2
TEST_YCLK
AA7
MEMTEST
R166243R
RV410
+MVDDQ
+MVDDQ
R158
40.2R
R159
100R
R150
40.2R
R151
100R
MDB[63..0](11,12)
C151
100nF
4170010400
C150
100nF
4170010400
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63
Set VREF divider to 70%
TEST_MCLK
TEST_YCLK
R1634.7K
R1564.7K
R1574.7K
NI
MAA0
D26
MAA1
F28
MAA2
D28
MAA3
D25
MAA4
E24
MAA5
E26
MAA6
D27
MAA7
F25
MAA8
C26
MAA9
B26
MAA10
D29
MAA11
B27
MAA12
B25
MAA13
C25
E27
CSA#1
E29
DQMA#0
H31
DQMA#1
J29
DQMA#2
J26
DQMA#3
G23
DQMA#4
E21
DQMA#5
B15
DQMA#6
D14
DQMA#7
J17
QSA0
J31
QSA1
K29
QSA2
K25
QSA3
F23
QSA4
D20
QSA5
B16
QSA6
D16
QSA7
H15
QSA#0
K31
QSA#1
K28
QSA#2
K26
QSA#3
G24
QSA#4
D21
QSA#5
C16
QSA#6
D15
QSA#7
J15
F29
D24
D31
E31
B30
RASA#
B28
CASA#
C29
WEA#
B31
CSA#0
B29
C28
B20
C19
C22
B24
B22
B21
B23
C23
MAA[13..0] (11,12)
CSA#1 (12)
DQMA#[7..0] (11,12)
QSA[7..0] (11,12)
QSA#[7..0] (11,12)
CLKA0 (11,12)
CLKA#0 (11,12)
CKEA (11,12)
RASA# (11,12)
CASA# (11,12)
WEA# (11,12)
CSA#0 (11)
CLKA1 (11,12)
CLKA#1 (11,12)
Channel B
Part 4 of 7
MEMORY INTERFACE B
DDR1 DDR2 DDR3
read strobe
Not used bidir. strobe
bidir. differential strobe
write strobe
For DDR2
MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8
MAB_9
MAB_10
MAB_11
MAB_12
MAB_13
MAB_14
MAB_15
DQMBb_0
DQMBb_1
DQMBb_2
DQMBb_3
DQMBb_4
DQMBb_5
DQMBb_6
DQMBb_7
QSB_0
QSB_1
QSB_2
QSB_3
QSB_4
QSB_5
QSB_6
QSB_7
QSB_0B
QSB_1B
QSB_2B
QSB_3B
QSB_4B
QSB_5B
QSB_6B
QSB_7B
ODTB
ODTB1
CLKB0
CLKB0b
CKEB0
RASB0b
CASB0b
WEB0b
CSB0b_0
CSB0b_1
CLKB1
CLKB1b
CKEB1
RASB1b
CASB1b
WEB1b
CSB1b_0
CSB1b_1
MAB0
G4
MAB1
E6
MAB2
E4
MAB3
H4
MAB4
J5
MAB5
G5
MAB6
F4
MAB7
H6
MAB8
G3
MAB9
G2
MAB10
D4
MAB11
F2
MAB12
H2
MAB13
H3
F5
CSB#1
D5
DQMB#0
B8
DQMB#1
D9
DQMB#2
G9
DQMB#3
K7
DQMB#4
M5
DQMB#5
V2
DQMB#6
W4
DQMB#7
T9
QSB0
B9
QSB1
D10
QSB2
H10
QSB3
K6
QSB4
N4
QSB5
U2
QSB6
U4
QSB7
V8
QSB#0
B10
QSB#1
E10
QSB#2
G10
QSB#3
J7
QSB#4
M4
QSB#5
U3
QSB#6
V4
QSB#7
V9
D6
J4
B4
B5
C2
RASB#
E2
CASB#
D3
WEB#
B2
CSB#0
D2
E3
N2
P3
L3
J2
L2
M2
K2
K3
MAB[13..0] (11,12)
CSB#1 (12)
DQMB#[7..0] (11,12)
QSB[7..0] (11,12)
QSB#[7..0] (11,12)
CLKB0 (11,12)
CLKB#0 (11,12)
CKEB (11,12)
RASB# (11,12)
CASB# (11,12)
WEB# (11,12)
CSB#0 (11)
CLKB1 (11,12)
CLKB#1 (11,12)
RESET(11,12)
A A
5
4
www.vinafix.vn
RESET
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV410 DV VG VIVO 256MB DDR3
Size Docum e n t N u mb er R e v
C
3
2
Date: Sheet
105-A41800-00
1
3
of
10 27Thursday, January 27, 2005
5
4
256 Mbit GDDRIII Channels A and B Rank 1
3
2
1
Channel A Channel B
R315
2.37K
R316
5.49K
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
+MVDDQ
MDA[63..0]
WEA#
CASA#
RASA#
RESET
CSA#0
CKEA
CLKA0
CLKA1
CLKA#0
CLKA#1
+MVDDQ
R277
2.37K
R281
5.49K
C199
100nF
4170010400
5
MDB[63..0](10,12)
+MVDDC
C228
100nF
4170010400
C248
100nF
4170010400
DQMB#[7..0](10,12)
QSB#[7..0](10,12)QSA#[7..0](10,12)
MAB[13..0](10,12)
QSB[7..0](10,12)
C229
100nF
4170010400
C249
100nF
4170010400
WEB#(10,12)
CASB#(10,12)
RASB#(10,12)
CSB#0(10)
CKEB(10, 12)
CLKB0(10,12)
CLKB1(10,12)
CLKB#0(10,12)
CLKB#1(10,12)
C230
100nF
4170010400
C250
100nF
4170010400
RESET
CLKA#0
CLKA0
CKEA
CSA#0
WEA#
RASA#
CASA#
+MVDDQ
U52
M9
BA1
M4
BA0
M3
A11
L3
A10
L10
A9
M10
A8/AP
M12
A7
M11
A6
L11
A5
K11
A4
K2
A3
L2
A2
M2
A1
M1
A0
L5
RESET
M7
CK
M6
CK
L6
CKE
L9
CS
M8
WE
L4
RAS
M5
CAS
B11
DM3
H2
DM2
H11
DM1
B2
DM0
A12
WDQS3
G1
WDQS2
G12
WDQS1
A1
WDQS0
A11
RDQS3
G2
RDQS2
G11
RDQS1
A2
RDQS0
E5
NC/VSS
E6
NC/VSS#E6
E7
NC/VSS#E7
E8
NC/VSS#E8
F5
NC/VSS#F5
F6
NC/VSS#F6
F7
NC/VSS#F7
F8
NC/VSS#F8
G5
NC/VSS#G5
G6
NC/VSS#G6
G7
NC/VSS#G7
G8
NC/VSS#G8
H5
NC/VSS#H5
H6
NC/VSS#H6
H7
NC/VSS#H7
H8
NC/VSS#H8
K8
RFU1
K5
RFU2
D2
RFU3
D11
RFU4
L7
RFU5
L8
ZQ
L1
VREF
L12
VREF#L12
HYB18T256321F-2.0
23CC564402
+MVDDC +MVDDQ +MVDDC
C93
C679
100nF
10uf
4170010400
+MVDDQ
C216
100nF
4170010400
+MVDDQ +MVDDC
C236
100nF
4170010400
VDDQ#B4
VDDQ#B6
VDDQ#B7
VDDQ#B9
VDDQ#B10
VDDQ#G3
VDDQ#G10
VDDQ#E3
VDDQ#E10
VDDQ#F3
VDDQ#F10
VDDQ#H3
VDDQ#H10
VDDQ#J3
VDDQ#J10
VDD#C7
VDD#D3
VDD#D10
VDD#K3
VDD#K6
VDD#K7
VDD#K10
VSSQ#C3
VSSQ#C4
VSSQ#C5
VSSQ#C8
VSSQ#C9
VSSQ#C10
VSSQ#D5
VSSQ#D8
VSSQ#E9
VSSQ#F4
VSSQ#F9
VSSQ#G4
VSSQ#G9
VSSQ#H4
VSSQ#H9
VSSQ#J4
VSSQ#J9
VSSQ#A3
VSSQ#A10
VSS#D6
VSS#D7
VSS#D9
VSS#J5
VSS#J6
VSS#J7
VSS#J8
VSS#K4
VSS#K9
C683
10uf
MAA13
MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0
DQMA#2
DQMA#3
DQMA#1
QSA#2
QSA#3
QSA#1
QSA#0
QSA2
QSA3
QSA1
QSA0
R938 243R
C208
100nF
4170010400
+MVDDQ
R27460.4R
R27560.4R
+MVDDQ
R27660.4R
R27860.4R
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VDDQ
VDD
VSSQ
VSS
C217
100nF
4170010400
C237
100nF
4170010400
A7
B8
A8
A9
B12
C11
C12
D12
K1
J2
J1
H1
F1
F2
E1
E2
E11
E12
F11
F12
H12
J12
J11
K12
D1
C1
C2
B1
A4
A5
B5
A6
B3
B4
B6
B7
B9
B10
G3
G10
E3
E10
F3
F10
H3
H10
J3
J10
C6
C7
D3
D10
K3
K6
K7
K10
E4
C3
C4
C5
C8
C9
C10
D5
D8
E9
F4
F9
G4
G9
H4
H9
J4
J9
A3
A10
D4
D6
D7
D9
J5
J6
J7
J8
K4
K9
C88
100nF
4170010400
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
R317
2.37K
R318
5.49K
+MVDDC
C218
100nF
4170010400
C238
100nF
4170010400
MAA13
MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0
DQMA#4
DQMA#7
DQMA#6
+MVDDQ
+MVDDC
+MVDDQ
C219
100nF
4170010400
C239
100nF
4170010400
R270
2.37K
R271
5.49K
C198
100nF
4170010400
DQMA#5
QSA#4
QSA#7
QSA#6
QSA#5
QSA4
QSA7
QSA6
QSA5
+MVDDQ +MVDDQ
R939 243R
C200
100nF
4170010400
+MVDDQ
C220
C221
100nF
100nF
4170010400
4170010400
+MVDDQ +MVDDC +MVDDQ
C241
C240
100nF
100nF
4170010400
4170010400
4
RESET
CLKA#1
CLKA1
CKEA
CSA#0
WEA#
RASA#
CASA#
M9
M4
M3
L3
L10
M10
M12
M11
L11
K11
K2
L2
M2
M1
L5
M7
M6
L6
L9
M8
L4
M5
B11
H2
H11
B2
A12
G1
G12
A1
A11
G2
G11
A2
E5
E6
E7
E8
F5
F6
F7
F8
G5
G6
G7
G8
H5
H6
H7
H8
K8
K5
D2
D11
L7
L8
L1
L12
C222
100nF
4170010400
C242
100nF
4170010400
U53
BA1
BA0
A11
A10
A9
A8/AP
A7
A6
A5
A4
A3
A2
A1
A0
RESET
CK
CK
CKE
CS
WE
RAS
CAS
DM3
VDDQ#B4
DM2
VDDQ#B6
DM1
VDDQ#B7
DM0
VDDQ#B9
VDDQ#B10
VDDQ#G3
VDDQ#G10
WDQS3
VDDQ#E3
WDQS2
WDQS1
VDDQ#E10
WDQS0
VDDQ#F3
VDDQ#F10
VDDQ#H3
RDQS3
VDDQ#H10
RDQS2
VDDQ#J3
RDQS1
VDDQ#J10
RDQS0
VDD#C7
VDD#D3
VDD#D10
NC/VSS
VDD#K3
NC/VSS#E6
VDD#K6
NC/VSS#E7
VDD#K7
NC/VSS#E8
VDD#K10
NC/VSS#F5
NC/VSS#F6
VSSQ#C3
NC/VSS#F7
VSSQ#C4
NC/VSS#F8
VSSQ#C5
NC/VSS#G5
VSSQ#C8
NC/VSS#G6
VSSQ#C9
NC/VSS#G7
VSSQ#C10
NC/VSS#G8
VSSQ#D5
NC/VSS#H5
VSSQ#D8
NC/VSS#H6
VSSQ#E9
NC/VSS#H7
VSSQ#F4
NC/VSS#H8
VSSQ#F9
VSSQ#G4
VSSQ#G9
VSSQ#H4
RFU1
VSSQ#H9
RFU2
RFU3
VSSQ#J4
RFU4
VSSQ#J9
RFU5
VSSQ#A3
VSSQ#A10
ZQ
VSS#D6
VSS#D7
VSS#D9
VSS#J5
VREF
VSS#J6
VSS#J7
VSS#J8
VSS#K4
VREF#L12
VSS#K9
HYB18T256321F-2.0
23CC564402
C680
C92
100nF
10uf
4170010400
C224
C223
100nF
100nF
4170010400
4170010400
C243
C244
100nF
100nF
4170010400
4170010400
www.vinafix.vn
MDA32
A7
DQ31
MDA33
B8
DQ30
MDA34
A8
DQ29
MDA35
A9
DQ28
MDA36
B12
DQ27
MDA37
C11
DQ26
MDA38
C12
DQ25
MDA39 MDB39
D12
DQ24
MDA56
K1
DQ23
MDA57
J2
DQ22
MDA58
J1
DQ21
MDA59
H1
DQ20
MDA60
F1
DQ19
MDA61
F2
DQ18
MDA62
E1
DQ17
MDA63
E2
DQ16
MDA48
E11
DQ15
MDA49
E12
DQ14
MDA50
F11
DQ13
MDA51
F12
DQ12
MDA52
H12
DQ11
MDA53
J12
DQ10
MDA54
J11
DQ9
MDA55
K12
DQ8
MDA40
D1
DQ7
MDA41
C1
DQ6
MDA42
C2
DQ5
MDA43
B1
DQ4
MDA44
A4
DQ3
MDA45
A5
DQ2
MDA46
B5
DQ1
MDA47
A6
DQ0
B3
VDDQ
B4
B6
B7
B9
+MVDDQ
B10
G3
G10
E3
E10
F3
F10
H3
H10
J3
J10
C6
VDD
VSSQ
VSS
C7
D3
D10
K3
K6
K7
K10
E4
C3
C4
C5
C8
C9
C10
D5
D8
E9
F4
F9
G4
G9
H4
H9
J4
J9
A3
A10
D4
D6
D7
D9
J5
J6
J7
J8
K4
K9
C214
10uf
C225
100nF
4170010400
C245
100nF
4170010400
+MVDDQ
+MVDDQ
+MVDDC
C89
100nF
4170010400
C226
100nF
4170010400
C246
100nF
4170010400
C227
100nF
4170010400
C247
100nF
4170010400
3
MDA[63..0](10,12)
MAA[13..0](10,12)
D D
WEA#(10,12)
CASA#(10,12)
RASA#(10,12)
RESET(10,12)
CSA#0(10)
CKEA(10, 12)
CLKA0(10,12)
CLKA1(10,12)
CLKA#0( 10,12)
CLKA#1( 10,12)
DQMA#[7..0](10,12)
C C
QSA[7..0](10,12)
B B
CLKA0(10,12)
A A
CLKA#0(10, 12)
CLKA1(10,12)
CLKA#1(10, 12)
R319
2.37K
R320
5.49K
+MVDDQ
+MVDDQ +MVDDC+MVDDC
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
WEB#
CASB#
RASB#
CSB#0
CKEB
CLKB0
CLKB1
CLKB#0
CLKB#1
DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6DQMA#0
DQMB#7
QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
C231
100nF
4170010400
C251
100nF
4170010400
MDB[63..0]
+MVDDQ
R279
2.37K
R283
5.49K
C197
100nF
4170010400
C232
100nF
4170010400
C252
100nF
4170010400
C210
100nF
4170010400
C212
22uF_16V
C233
100nF
4170010400
C253
100nF
4170010400
MAB13
MAB12
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0
RESET
CLKB#0
CLKB0
CKEB
CSB#0
WEB#
RASB#
CASB#
DQMB#2
DQMB#3
DQMB#1
DQMB#0
QSB#2
QSB#3
QSB#1
QSB#0
QSB2
QSB3
QSB1
QSB0
R940 243R
+MVDDC+MVDDC
+MVDDQ +MVDDC+MVDDQ
C234
100nF
4170010400
C254
100nF
4170010400
C215
10uf
M9
M4
M3
L3
L10
M10
M12
M11
L11
K11
K2
L2
M2
M1
L5
M7
M6
L6
L9
M8
L4
M5
B11
H2
H11
B2
A12
G1
G12
A1
A11
G2
G11
A2
E5
E6
E7
E8
F5
F6
F7
F8
G5
G6
G7
G8
H5
H6
H7
H8
K8
K5
D2
D11
L7
L8
L1
L12
U54
BA1
BA0
A11
A10
A9
A8/AP
A7
A6
A5
A4
A3
A2
A1
A0
RESET
CK
CK
CKE
CS
WE
RAS
CAS
DM3
VDDQ#B4
DM2
VDDQ#B6
DM1
VDDQ#B7
DM0
VDDQ#B9
VDDQ#B10
VDDQ#G3
VDDQ#G10
WDQS3
VDDQ#E3
WDQS2
WDQS1
VDDQ#E10
WDQS0
VDDQ#F3
VDDQ#F10
VDDQ#H3
RDQS3
VDDQ#H10
RDQS2
VDDQ#J3
RDQS1
VDDQ#J10
RDQS0
VDD#D10
NC/VSS
NC/VSS#E6
NC/VSS#E7
NC/VSS#E8
VDD#K10
NC/VSS#F5
NC/VSS#F6
VSSQ#C3
NC/VSS#F7
VSSQ#C4
NC/VSS#F8
VSSQ#C5
NC/VSS#G5
VSSQ#C8
NC/VSS#G6
VSSQ#C9
NC/VSS#G7
VSSQ#C10
NC/VSS#G8
VSSQ#D5
NC/VSS#H5
VSSQ#D8
NC/VSS#H6
VSSQ#E9
NC/VSS#H7
VSSQ#F4
NC/VSS#H8
VSSQ#F9
VSSQ#G4
VSSQ#G9
VSSQ#H4
RFU1
VSSQ#H9
RFU2
RFU3
VSSQ#J4
RFU4
VSSQ#J9
RFU5
VSSQ#A3
VSSQ#A10
ZQ
VREF
VREF#L12
HYB18T256321F-2.0
23CC564402
C682
10uf
C235
100nF
4170010400
C255
100nF
4170010400
2
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VDDQ
VDD
VDD#C7
VDD#D3
VDD#K3
VDD#K6
VDD#K7
VSSQ
VSS
VSS#D6
VSS#D7
VSS#D9
VSS#J5
VSS#J6
VSS#J7
VSS#J8
VSS#K4
VSS#K9
C90
100nF
4170010400
RESET
CLKB#1
CLKB1
CKEB
CSB#0
WEB#
RASB#
CASB#
U55
M9
BA1
M4
BA0
M3
A11
L3
A10
L10
A9
M10
A8/AP
M12
A7
M11
A6
L11
A5
K11
A4
K2
A3
L2
A2
M2
A1
M1
A0
L5
RESET
M7
CK
M6
CK
L6
CKE
L9
CS
M8
WE
L4
RAS
M5
CAS
B11
DM3
H2
DM2
H11
DM1
B2
DM0
A12
WDQS3
G1
WDQS2
G12
WDQS1
A1
WDQS0
A11
RDQS3
G2
RDQS2
G11
RDQS1
A2
RDQS0
E5
NC/VSS
E6
NC/VSS#E6
E7
NC/VSS#E7
E8
NC/VSS#E8
F5
NC/VSS#F5
F6
NC/VSS#F6
F7
NC/VSS#F7
F8
NC/VSS#F8
G5
NC/VSS#G5
G6
NC/VSS#G6
G7
NC/VSS#G7
G8
NC/VSS#G8
H5
NC/VSS#H5
H6
NC/VSS#H6
H7
NC/VSS#H7
H8
NC/VSS#H8
K8
RFU1
K5
RFU2
D2
RFU3
D11
RFU4
L7
RFU5
L8
ZQ
L1
VREF
L12
VREF#L12
HYB18T256321F-2.0
23CC564402
+MVDDQ
C681
10uf
105-A41800-00
1
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
VDDQ
VDDQ#B4
VDDQ#B6
VDDQ#B7
VDDQ#B9
VDDQ#B10
VDDQ#G3
VDDQ#G10
VDDQ#E3
VDDQ#E10
VDDQ#F3
VDDQ#F10
VDDQ#H3
VDDQ#H10
VDDQ#J3
VDDQ#J10
VDD#C7
VDD#D3
VDD#D10
VDD#K3
VDD#K6
VDD#K7
VDD#K10
VSSQ
VSSQ#C3
VSSQ#C4
VSSQ#C5
VSSQ#C8
VSSQ#C9
VSSQ#C10
VSSQ#D5
VSSQ#D8
VSSQ#E9
VSSQ#F4
VSSQ#F9
VSSQ#G4
VSSQ#G9
VSSQ#H4
VSSQ#H9
VSSQ#J4
VSSQ#J9
VSSQ#A3
VSSQ#A10
VSS#D6
VSS#D7
VSS#D9
VSS#J5
VSS#J6
VSS#J7
VSS#J8
VSS#K4
VSS#K9
C94
100nF
4170010400
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VDD
VSS
A7
B8
A8
A9
B12
C11
C12
D12
K1
J2
J1
H1
F1
F2
E1
E2
E11
E12
F11
F12
H12
J12
J11
K12
D1
C1
C2
B1
A4
A5
B5
A6
B3
B4
B6
B7
B9
B10
G3
G10
E3
E10
F3
F10
H3
H10
J3
J10
C6
C7
D3
D10
K3
K6
K7
K10
E4
C3
C4
C5
C8
C9
C10
D5
D8
E9
F4
F9
G4
G9
H4
H9
J4
J9
A3
A10
D4
D6
D7
D9
J5
J6
J7
J8
K4
K9
+MVDDC
11 27Thursday, January 27, 2005
C213
10uf
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
+MVDDQ
+MVDDC
C91
100nF
4170010400
3
of
MDB16
A7
MDB17
B8
MDB18
A8
MDB19
A9
MDB20
B12
MDB21
C11
MDB22
C12
MDB23
D12
MDB24
K1
MDB25
J2
MDB26
J1
MDB27
H1
MDB28
F1
MDB29
F2
MDB30
E1
MDB31
E2
MDB8
E11
MDB9
E12
MDB10
F11
MDB11
F12
MDB12
H12
MDB13
J12
MDB14
J11
MDB15
K12
MDB0
D1
MDB1
C1
MDB2
C2
MDB3
B1
MDB4
A4
MDB5
A5
MDB6
B5
MDB7
A6
B3
B4
B6
B7
B9
+MVDDQ
B10
G3
G10
E3
E10
F3
F10
H3
H10
J3
J10
C6
+MVDDC
C7
D3
D10
K3
K6
K7
K10
E4
C3
C4
C5
C8
C9
C10
D5
D8
E9
F4
F9
G4
G9
H4
H9
J4
J9
A3
A10
D4
D6
D7
D9
J5
J6
J7
J8
K4
K9
R272
2.37K
R273
5.49K
+MVDDQ
R321
2.37K
R322
5.49K
CLKB0(10,12)
CLKB#0(10,12)
CLKB1(10,12)
CLKB#1(10,12)
MAB13
MAB12
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0
DQMB#4
DQMB#7
DQMB#6
DQMB#5
QSB#4
QSB#7
QSB#6
QSB#5
QSB4
QSB7
QSB6
QSB5
R941 243R
C201
100nF
4170010400
C196
100nF
4170010400
+MVDDQ
R26060.4R
R26160.4R
+MVDDQ
R26260.4R
R26360.4R
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV410 DV VG VIVO 256MB DDR3
Size Docu m en t N u m be r Re v
C
Date: Sheet
5
4
3
2
1
256 Mbit GDDRIII Channels A and B Rank 1
Channel A Channel B
R413
2.37K
R414
5.49K
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
+MVDDQ
MDA[63..0]
WEA#
CASA#
RASA#
RESET
CSA#1
CKEA
CLKA0
CLKA1
CLKA#0
CLKA#1
+MVDDQ
R410
2.37K
R411
5.49K
C341
100nF
4170010400
MAA13
MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0
RESET
CLKA#0
CLKA0
CKEA
CSA#1
WEA#
RASA#
CASA#
DQMA#0
DQMA#1
DQMA#3
QSA#0
QSA#1
QSA#3
QSA#2
QSA0
QSA1
QSA3
QSA2
R412 243R
C340
100nF
4170010400
+MVDDQ
C342
10uf
CLKA#1
CLKA1
CKEA
CSA#1
WEA#
RASA#
CASA#
U49
M9
BA1
M4
BA0
M3
A11
L3
A10
L10
A9
M10
A8/AP
M12
A7
M11
A6
L11
A5
K11
A4
K2
A3
L2
A2
M2
A1
M1
A0
L5
RESET
M7
CK
M6
CK
L6
CKE
L9
CS
M8
WE
L4
RAS
M5
CAS
B11
DM3
H2
DM2
H11
DM1
B2
DM0
A12
WDQS3
G1
WDQS2
G12
WDQS1
A1
WDQS0
A11
RDQS3
G2
RDQS2
G11
RDQS1
A2
RDQS0
E5
NC/VSS
E6
NC/VSS#E6
E7
NC/VSS#E7
E8
NC/VSS#E8
F5
NC/VSS#F5
F6
NC/VSS#F6
F7
NC/VSS#F7
F8
NC/VSS#F8
G5
NC/VSS#G5
G6
NC/VSS#G6
G7
NC/VSS#G7
G8
NC/VSS#G8
H5
NC/VSS#H5
H6
NC/VSS#H6
H7
NC/VSS#H7
H8
NC/VSS#H8
K8
RFU1
K5
RFU2
D2
RFU3
D11
RFU4
L7
RFU5
L8
ZQ
L1
VREF
L12
VREF#L12
HYB18T256321F-2.0
23CC564402
U47
M9
BA1
M4
BA0
M3
A11
L3
A10
L10
A9
M10
A8/AP
M12
A7
M11
A6
L11
A5
K11
A4
K2
A3
L2
A2
M2
A1
M1
A0
L5
RESET
M7
CK
M6
CK
L6
CKE
L9
CS
M8
WE
L4
RAS
M5
CAS
B11
DM3
H2
H11
B2
A12
G1
G12
A1
A11
G2
G11
A2
E5
E6
E7
E8
F5
F6
F7
F8
G5
G6
G7
G8
H5
H6
H7
H8
K8
K5
D2
D11
L7
L8
L1
L12
VDDQ#B4
DM2
VDDQ#B6
DM1
VDDQ#B7
DM0
VDDQ#B9
VDDQ#B10
VDDQ#G3
VDDQ#G10
WDQS3
VDDQ#E3
WDQS2
WDQS1
VDDQ#E10
WDQS0
VDDQ#F3
VDDQ#F10
VDDQ#H3
RDQS3
VDDQ#H10
RDQS2
VDDQ#J3
RDQS1
VDDQ#J10
RDQS0
VDD#C7
VDD#D3
VDD#D10
NC/VSS
VDD#K3
NC/VSS#E6
VDD#K6
NC/VSS#E7
VDD#K7
NC/VSS#E8
VDD#K10
NC/VSS#F5
NC/VSS#F6
VSSQ#C3
NC/VSS#F7
VSSQ#C4
NC/VSS#F8
VSSQ#C5
NC/VSS#G5
VSSQ#C8
NC/VSS#G6
VSSQ#C9
NC/VSS#G7
VSSQ#C10
NC/VSS#G8
VSSQ#D5
NC/VSS#H5
VSSQ#D8
NC/VSS#H6
VSSQ#E9
NC/VSS#H7
VSSQ#F4
NC/VSS#H8
VSSQ#F9
VSSQ#G4
VSSQ#G9
VSSQ#H4
RFU1
VSSQ#H9
RFU2
RFU3
VSSQ#J4
RFU4
VSSQ#J9
RFU5
VSSQ#A3
VSSQ#A10
ZQ
VSS#D6
VSS#D7
VSS#D9
VSS#J5
VREF
VSS#J6
VSS#J7
VSS#J8
VSS#K4
VREF#L12
VSS#K9
HYB18T256321F-2.0
23CC564402
+MVDDC +MVDDQ +MVDDC
C343
C344
100nF
10uf
4170010400
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VDDQ
VDD
VSSQ
VSS
A7
B8
A8
A9
B12
C11
C12
D12
K1
J2
J1
H1
F1
F2
E1
E2
E11
E12
F11
F12
H12
J12
J11
K12
D1
C1
C2
B1
A4
A5
B5
A6
B3
B4
B6
B7
B9
B10
G3
G10
E3
E10
F3
F10
H3
H10
J3
J10
C6
C7
D3
D10
K3
K6
K7
K10
E4
C3
C4
C5
C8
C9
C10
D5
D8
E9
F4
F9
G4
G9
H4
H9
J4
J9
A3
A10
D4
D6
D7
D9
J5
J6
J7
J8
K4
K9
C345
100nF
4170010400
MDA7
MDA6
MDA5
MDA4
MDA3
MDA2
MDA1
MDA0
MDA15
MDA14
MDA13
MDA12
MDA11
MDA10
MDA9
MDA8
MDA31
MDA30
MDA29
MDA28
MDA27
MDA26
MDA25
MDA24
MDA23
MDA22
MDA21
MDA20
MDA19
MDA18
MDA17
MDA16
R419
2.37K
R420
5.49K
MAA13
MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0
DQMA#5
DQMA#6
DQMA#7
+MVDDQ
+MVDDC
+MVDDQ
R421
2.37K
R422
5.49K
C346
100nF
4170010400
DQMA#4
QSA#5
QSA#6
QSA#7
QSA#4
QSA5
QSA6
QSA7
QSA4
+MVDDQ +MVDDQ
R423 243R
C347
100nF
4170010400
C348
10uf
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
VDDQ
VDDQ#B4
VDDQ#B6
VDDQ#B7
VDDQ#B9
VDDQ#B10
VDDQ#G3
VDDQ#G10
VDDQ#E3
VDDQ#E10
VDDQ#F3
VDDQ#F10
VDDQ#H3
VDDQ#H10
VDDQ#J3
VDDQ#J10
VDD#C7
VDD#D3
VDD#D10
VDD#K3
VDD#K6
VDD#K7
VDD#K10
VSSQ
VSSQ#C3
VSSQ#C4
VSSQ#C5
VSSQ#C8
VSSQ#C9
VSSQ#C10
VSSQ#D5
VSSQ#D8
VSSQ#E9
VSSQ#F4
VSSQ#F9
VSSQ#G4
VSSQ#G9
VSSQ#H4
VSSQ#H9
VSSQ#J4
VSSQ#J9
VSSQ#A3
VSSQ#A10
VSS#D6
VSS#D7
VSS#D9
VSS#J5
VSS#J6
VSS#J7
VSS#J8
VSS#K4
VSS#K9
C349
100nF
4170010400
MDB[63..0](10,11)
MDA47
A7
MDA46
B8
MDA45
A8
MDA44
A9
MDA43
B12
MDA42
C11
MDA41
C12
MDA40 MDB40
D12
MDA55
K1
MDA54
J2
MDA53
J1
MDA52
H1
MDA51
F1
MDA50
F2
MDA49
E1
MDA48
E2
MDA63RESET
E11
MDA62
E12
MDA61
F11
MDA60
F12
MDA59
H12
MDA58
J12
MDA57
J11
DQ9
MDA56
K12
DQ8
MDA39
D1
DQ7
MDA38
C1
DQ6
MDA37
C2
DQ5
MDA36
B1
DQ4
MDA35
A4
DQ3
MDA34
A5
DQ2
MDA33
B5
DQ1
MDA32
A6
DQ0
B3
B4
B6
B7
B9
+MVDDQ
B10
G3
G10
E3
E10
F3
F10
H3
H10
J3
J10
C6
VDD
VSS
+MVDDC
C7
D3
D10
K3
K6
K7
K10
E4
C3
C4
C5
C8
C9
C10
D5
D8
E9
F4
F9
G4
G9
H4
H9
J4
J9
A3
A10
D4
D6
D7
D9
J5
J6
J7
J8
K4
K9
C350
C351
100nF
10uf
4170010400
MAB[13..0](10,11)
WEB#(10,11)
CASB#(10,11)
RASB#(10,11)
CSB#1(10)
CKEB(10, 11)
CLKB0(10,11)
CLKB1(10,11)
CLKB#0(10,11)
CLKB#1(10,11)
DQMB#[7..0](10,11)
QSB#[7..0](10,11)QSA#[7..0](10,11)
QSB[7..0](10,11)
MDA[63..0](10,11)
MAA[13..0](10,11)
D D
WEA#(10,11)
CASA#(10,11)
RASA#(10,11)
RESET(10,11)
CSA#1(10)
CKEA(10, 11)
CLKA0(10,11)
CLKA1(10,11)
CLKA#0( 10,11)
CLKA#1( 10,11)
DQMA#[7..0](10,11)
C C
QSA[7..0](10,11)
B B
R426
2.37K
R427
5.49K
+MVDDQ
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6DQMA#2
DQMB#7
QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
MDB[63..0]
WEB#
CASB#
RASB#
CSB#1
CKEB
CLKB0
CLKB1
CLKB#0
CLKB#1
R424
2.37K
R425
5.49K
C352
100nF
4170010400
+MVDDQ
C353
100nF
4170010400
C354
22uF_16V
MAB13
MAB12
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0
RESET
CLKB#0
CLKB0
CKEB
CSB#1
WEB#
RASB#
CASB#
DQMB#0
DQMB#1
DQMB#3
DQMB#2
QSB#0
QSB#1
QSB#3
QSB#2
QSB0
QSB1
QSB3
QSB2
R428 243R
+MVDDQ +MVDDC+MVDDQ
C355
10uf
M9
M4
M3
L3
L10
M10
M12
M11
L11
K11
K2
L2
M2
M1
L5
M7
M6
L6
L9
M8
L4
M5
B11
H2
H11
B2
A12
G1
G12
A1
A11
G2
G11
A2
E5
E6
E7
E8
F5
F6
F7
F8
G5
G6
G7
G8
H5
H6
H7
H8
K8
K5
D2
D11
L7
L8
L1
L12
U50
BA1
BA0
A11
A10
A9
A8/AP
A7
A6
A5
A4
A3
A2
A1
A0
RESET
CK
CK
CKE
CS
WE
RAS
CAS
DM3
VDDQ#B4
DM2
VDDQ#B6
DM1
VDDQ#B7
DM0
VDDQ#B9
VDDQ#B10
VDDQ#G3
VDDQ#G10
WDQS3
VDDQ#E3
WDQS2
WDQS1
VDDQ#E10
WDQS0
VDDQ#F3
VDDQ#F10
VDDQ#H3
RDQS3
VDDQ#H10
RDQS2
VDDQ#J3
RDQS1
VDDQ#J10
RDQS0
VDD#D10
NC/VSS
NC/VSS#E6
NC/VSS#E7
NC/VSS#E8
VDD#K10
NC/VSS#F5
NC/VSS#F6
VSSQ#C3
NC/VSS#F7
VSSQ#C4
NC/VSS#F8
VSSQ#C5
NC/VSS#G5
VSSQ#C8
NC/VSS#G6
VSSQ#C9
NC/VSS#G7
VSSQ#C10
NC/VSS#G8
VSSQ#D5
NC/VSS#H5
VSSQ#D8
NC/VSS#H6
VSSQ#E9
NC/VSS#H7
VSSQ#F4
NC/VSS#H8
VSSQ#F9
VSSQ#G4
VSSQ#G9
VSSQ#H4
RFU1
VSSQ#H9
RFU2
RFU3
VSSQ#J4
RFU4
VSSQ#J9
RFU5
VSSQ#A3
VSSQ#A10
ZQ
VREF
VREF#L12
HYB18T256321F-2.0
23CC564402
C356
10uf
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VDDQ
VDD
VDD#C7
VDD#D3
VDD#K3
VDD#K6
VDD#K7
VSSQ
VSS
VSS#D6
VSS#D7
VSS#D9
VSS#J5
VSS#J6
VSS#J7
VSS#J8
VSS#K4
VSS#K9
C357
100nF
4170010400
RESET
CLKB#1
CLKB1
CKEB
CSB#1
WEB#
RASB#
CASB#
U51
M9
M4
M3
L3
L10
M10
M12
M11
L11
K11
K2
L2
M2
M1
L5
M7
M6
L6
L9
M8
L4
M5
B11
H2
H11
B2
A12
G1
G12
A1
A11
G2
G11
A2
E5
E6
E7
E8
F5
F6
F7
F8
G5
G6
G7
G8
H5
H6
H7
H8
K8
K5
D2
D11
L7
L8
L1
L12
HYB18T256321F-2.0
23CC564402
+MVDDQ
C360
10uf
BA1
BA0
A11
A10
A9
A8/AP
A7
A6
A5
A4
A3
A2
A1
A0
RESET
CK
CK
CKE
CS
WE
RAS
CAS
DM3
DM2
DM1
DM0
WDQS3
WDQS2
WDQS1
WDQS0
RDQS3
RDQS2
RDQS1
RDQS0
NC/VSS
NC/VSS#E6
NC/VSS#E7
NC/VSS#E8
NC/VSS#F5
NC/VSS#F6
NC/VSS#F7
NC/VSS#F8
NC/VSS#G5
NC/VSS#G6
NC/VSS#G7
NC/VSS#G8
NC/VSS#H5
NC/VSS#H6
NC/VSS#H7
NC/VSS#H8
RFU1
RFU2
RFU3
RFU4
RFU5
ZQ
VREF
VREF#L12
VDDQ#B4
VDDQ#B6
VDDQ#B7
VDDQ#B9
VDDQ#B10
VDDQ#G3
VDDQ#G10
VDDQ#E3
VDDQ#E10
VDDQ#F3
VDDQ#F10
VDDQ#H3
VDDQ#H10
VDDQ#J3
VDDQ#J10
VDD#D10
VDD#K10
VSSQ#C3
VSSQ#C4
VSSQ#C5
VSSQ#C8
VSSQ#C9
VSSQ#C10
VSSQ#D5
VSSQ#D8
VSSQ#E9
VSSQ#F4
VSSQ#F9
VSSQ#G4
VSSQ#G9
VSSQ#H4
VSSQ#H9
VSSQ#J4
VSSQ#J9
VSSQ#A3
VSSQ#A10
C361
100nF
4170010400
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
VDDQ
VDD#C7
VDD#D3
VDD#K3
VDD#K6
VDD#K7
VSSQ
VSS#D6
VSS#D7
VSS#D9
VSS#J5
VSS#J6
VSS#J7
VSS#J8
VSS#K4
VSS#K9
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VDD
VSS
+MVDDC
C362
10uf
MDB47
A7
MDB46
B8
MDB45
A8
MDB44
A9
MDB43
B12
MDB42
C11
MDB41
C12
D12
MDB55
K1
MDB54
J2
MDB53
J1
MDB52
H1
MDB51
F1
MDB50
F2
MDB49
E1
MDB48
E2
MDB63
E11
MDB62
E12
MDB61
F11
MDB60
F12
MDB59
H12
MDB58
J12
MDB57
J11
MDB56
K12
MDB39
D1
MDB38
C1
MDB37
C2
MDB36
B1
MDB35
A4
MDB34
A5
MDB33
B5
MDB32
A6
B3
B4
B6
B7
B9
+MVDDQ
B10
G3
G10
E3
E10
F3
F10
H3
H10
J3
J10
C6
+MVDDC
C7
D3
D10
K3
K6
K7
K10
E4
C3
C4
C5
C8
C9
C10
D5
D8
E9
F4
F9
G4
G9
H4
H9
J4
J9
A3
A10
D4
D6
D7
D9
J5
J6
J7
J8
K4
K9
C363
100nF
4170010400
C358
100nF
4170010400
MAB13
MAB12
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0
C359
100nF
4170010400
DQMB#5
DQMB#6
DQMB#7
DQMB#4
QSB#5
QSB#6
QSB#7
QSB#4
QSB5
QSB6
QSB7
QSB4
R429 243R
MDB7
A7
MDB6
B8
MDB5
A8
MDB4
A9
MDB3
B12
MDB2
C11
MDB1
C12
MDB0
D12
MDB15
K1
MDB14
J2
MDB13
J1
MDB12
H1
MDB11
F1
MDB10
F2
MDB9
E1
MDB8
E2
MDB31
E11
MDB30
E12
MDB29
F11
MDB28
F12
MDB27
H12
MDB26
J12
MDB25
J11
MDB24
K12
MDB23
D1
MDB22
C1
MDB21
C2
MDB20
B1
MDB19
A4
MDB18
A5
MDB17
B5
MDB16
A6
B3
B4
B6
B7
B9
+MVDDQ
B10
G3
G10
E3
E10
F3
F10
H3
H10
J3
J10
C6
+MVDDC
C7
D3
D10
K3
K6
K7
K10
E4
C3
C4
C5
C8
C9
C10
D5
D8
E9
F4
F9
G4
G9
H4
H9
J4
J9
A3
A10
D4
D6
D7
D9
J5
J6
J7
J8
K4
K9
R432
2.37K
R433
5.49K
+MVDDQ
R430
2.37K
R431
5.49K
+MVDDQ
C365
C364
100nF
100nF
4170010400
A A
5
4170010400
+MVDDQ +MVDDC
C369
C370
100nF
100nF
4170010400
4170010400
+MVDDC
C366
100nF
4170010400
C371
100nF
4170010400
C367
100nF
4170010400
C372
100nF
4170010400
+MVDDQ
C374
C368
100nF
4170010400
C373
100nF
4170010400
4
C375
100nF
100nF
4170010400
4170010400
+MVDDQ +MVDDC +MVDDQ
C379
C380
100nF
100nF
4170010400
4170010400
C377
C376
100nF
100nF
4170010400
4170010400
C381
C382
100nF
100nF
4170010400
4170010400
www.vinafix.vn
C378
100nF
4170010400
C383
100nF
4170010400
+MVDDQ
+MVDDQ
C384
100nF
4170010400
C389
100nF
4170010400
C385
100nF
4170010400
C390
100nF
4170010400
3
+MVDDC
C386
100nF
4170010400
C391
100nF
4170010400
C387
100nF
4170010400
C336
100nF
4170010400
C388
100nF
4170010400
C392
100nF
4170010400
+MVDDQ +MVDDC+MVDDC
C393
100nF
4170010400
C398
100nF
4170010400
C394
100nF
4170010400
C399
100nF
4170010400
C395
100nF
4170010400
+MVDDC+MVDDC
C339
100nF
4170010400
C396
100nF
4170010400
C338
100nF
4170010400
C397
100nF
4170010400
C337
100nF
4170010400
2
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV410 DV VG VIVO 256MB DDR3
Size Docum e n t N u mb er R e v
C
Date: Sheet
105-A41800-00
1
of
12 27Thursday, January 27, 2005
3
1
2
3
4
5
6
7
8
OPTION STRAPS
GPIO[6..0]
GPIO[6..0](4)
GPIO0
A A
Overlap pads to save space
GPIO1
and to prevent assembly of
both resistors.
Layout
High logic voltageGround
Signal
GPIO[13..8]
GPIO[13..8](4)
B B
VSYNC_DAC1(4,15)
HSYNC_DAC1(4,15)
DVALID(4)
C C
D D
PSYNC(4)
DVOMODE_0(4)
1
R570 10K
R571 10K
+VDD_1.8V
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO8
GPIO9
GPIO11
GPIO12
GPIO13
+VDD_1.8V
DNI
R57210K
DNI
R57310K
2
DVOMODE_1 (4)
R331 10K
R332 10K
R333 10K
R334 10K
R205 10K DNI
R206 10K
R335 10K DNI
R336 10K
R347 10K DNI
R348 10K
R349 10K DNI
R350 10K
R351 10K DNI
R352 10K
R345 10K DNI
R346 10K
R343 10K
R344 10K DNI
R337 10K
R338 10K
R339 10K
R340 10K
R341 10K
R342 10K
R359 10K
R360 10K
R357 10K
R358 10K
R361 10K DNI
R362 10K
R363 10K DNI
R364 10K
DNI
DNI
DNI
DNI
DNI
DNI
DNI
3
RV410 Shared Straps
STRAPS
+3.3V_BUS
TRANSMIT_DE-EMPHASIS
PCIE_MODE
(ATI Internal)
TX_IEXT
FORCE _COMPLIANCE
PLL_BW
(ATI Internal)
RV410 Dedicated Straps
ZV_VOLTAGE_SEL0 DVOVMODE_0
ZV_VOLTAGE_SEL1 DVOVMODE_1
Board Straps
STRAPS VALUEDESCRIPTIONPIN
MEMTYPE(1:0)
DC_Strap1
DC_Strap2
DC_Strap3
DC_Strap4,
DEMUX_SEL
PAL/NTSC
PIN
GPIO(0)PCIE_SWING
GPIO(1)
GPIO(3:2)
GPIO(4)
GPIO(5)
GPIO(6)
GPIO(8)DEBUG_ACCESS
VSYNC
HSYNC 0RFU RFU
DVALID, PSYNC.
GPIO(10)
LCDDATA(13)
LCDDATA(14)
LCDDATA(15,19)
LCDDATA(18)
4
www.vinafix.vn
DESCRIPTION
Transmit t er S wi ng Contr ol
0: 50% Tx output swing mode
1: full Tx output swing
Transmitter De-emphasis Enable
0: Tx de- emphasis di sabled for mobil e mode
1: Tx de-emphasis enabled
PCIE mode:
00: PCI Express 1.0A mode
01: Kyrene-com patible mode
10: PCI Express 1.0 mode
11: RESERVED
Transmitter Extra Cur rent
0: normal mode
1: extra c urrent i n Tx out put stage
Force chip to g et to c omp li anc e st ate quickl y for Tester purposes
0: Normal operation
1: Force to com pli ance state
1: Reduced PLL bandwidth
0: Disabl e debug access
1: Enable debug access
If no ROM attached, controls chip IDi s. If r om attached ide ntifies ROM type.
GPIO[9,13,12,11]
000x - No ROM,CHG_ID=00
001x - No ROM, CHG_ID=01
010x - No ROM, CHG_ID=10
011x - No ROM, CHG_ID=11
1001 - 1M Serial AT25F1024 ROM (Atmel)
1010 - 1M Serial AT45DB011 ROM (Atmel)
1011 - 1M Serial M25P10 ROM (ST)
1100 - 512K Serial M25P05 ROM (ST)
1101 - 1M Serial SST45LF010 ROM (SST)
1M Serial W45B512 ROM (Wi nBond)
512K Serial W45B012 ROM (WinB ond)
1110 - 1M Serial SST25VF010 ROM (SST)
512K Serial SST25VF512 ROM (SST)
1111 - 1M NX25F011B ROM (NexFlash)
Chip IDs:
Chip ID is ba s ed on substrate fuses and CHG_ID strap (which comes from RO M if used,
or pin straps if no ROM is connected): CHG_ID = ROMIDCFG[2:1] = GPIO[13:12]
Indicates if any slave VIP host devices drove thi s in low during reset.VIP_DEVICE
0 - Slave VIP host port devices present
1 - No slave VIP host port devices reporting presence during reset
0 - Normal
1 - Not used
DVOVMODE_0 i s fo r ZV _ LC DCNT L and ZV_LCDDATA(11:0}.
0 - 3.3 V signaling
1 - 1.8 V signaling
DVOVMODE_1 is for ZV_LCDDATA(23:12)
0 - 3.3 V signaling
1 - 1.8 V signaling
Memory connected to R420 identification for BIOS
00 - Samsung GDDR 3 memory 144 Ball BGA package
01 - TBD
10 - TBD
11 - TBD
Internal TMDS Enabled
0 - Disabled
1 - Enabled
Video Capture Enabled
0 - Disabled
1 - Not detected
HDTV out detect
0 - Detected
1 - Enabled
Video capture enable
00 - DAC2 Off
01 - DAC2 On as CRT
10 - DAC2 On as TVOUT
11 - DAC2 On as TVOU T and C RT
TVO Stan dard D efault (Resi stor pul l-up and sw itch shor t to GN D)
0 - PAL (on board resistor pull-down and switch closed)
1 -NTSC (on board resistor pull-up)
5
REV. 0.5
VALUE
1
1
00
0
0
00: Full PLL Bandwidth
0Strap to set the debug muxes to bring out DEBUG signals even if registers are inaccessible
1100GPIO(9,13:11)ROMIDCFG(3:0)
1
REV. 0.2
0
0
REV. 0.3
000
1
0
1
01
1
6
+3.3V_BUS
R584 10K
DNI
R580 10K
R576 10K
41
SW1A
DIP_SWX2
PAL/NTSC (4)
+3.3V_BUS
DEMUX_SEL(4)
DC_Strap3(4,19)
GPIO10(4)
DC_Strap4 (4)
DC_Strap2 (4)
R577 10K
R581 10K
R585 10K DNI
R582 10K
R578 10K
R574 10K
DC_Strap1
R575 10K
R579 10K
R583 10K DNI
DNI
DNI
DNI
WARNING
Some of those straps must be connected to +VDD_1.8V
if ZV_LCDATA bus is set to 1.8 V.
<Variant Name>
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV410 DV VG VIVO 256MB DDR3
Size Docum e n t N u mb er R e v
C
Date: Sheet
7
105-A41800-00
3
of
13 27Thursday, January 27, 2005
8
5
4
3
2
1
TEMPERATURE SENSE AND SPEED CONTROLLED FAN
D D
+12V_BUS
B59
Bead
R1573
C1134
0R
100nF
DNI
+3.3V_BUS
C1517
0.1uF
VDD
D+
D-
C1518
100pF
1
2
3
4
C1519
2.2nF
R1682 0R
PWM
R1683 1 0R
R1609
4.7K
DNI
GPU_DPLUS
GPU_DMINUS
+12V_BUS
1
2 3
R1681
1K
Q213
MMBT2222ALT1
TACH
GPU_DPLUS (4)
GPU_DMINUS (4)
C1577
1uF
C1520 10 nF
+12V_BUS
DNI
R1631
10K
32
Q209
1
ZXM61N03FTA
DNI
R1611
0R
C1516
R1610
C C
SCL(4,16)
SDA(4,16)
ThermINT(4)
R1620 100R
R1621
R1624 0R
100R
SCL_R
SDA_R
10K
TACH
C1524
56pF
C1525
56pF
10uF
U106
8
SMBCLK
7
SMBDAT
6
ALERT
GND5PWM
LM63CIMAX
Do not install
This resistor will
be shorted in layout.
It is present to control
where the signal will be
connected to digital
ground.
B B
R1684 0R
DNI
JU1
1
2
JUl2
DUAL FOOTPRINT
MJU1
1
2
JUl1
3
Header_1X3
DNI
DNI
R16280R
DNI
R1629
10K
Not installed
A A
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV410 DV VG VIVO 256MB DDR3
Size Docum e n t N u mb er R e v
C
5
4
www.vinafix.vn
3
2
Date: Sheet
105-A41800-00
1
3
of
14 27Thursday, January 27, 2005
5
4
3
2
1
PRIMARY VGA DAC1
VSYNC_DAC1_R(17)
HSYNC_DAC1_R(17)
DDCCLK_DAC1_5V(17)
DDCDATA_DAC1_5V(17)
B_DAC1_F(17)
G_DAC1_F(17)
R_DAC1_F(17)
D D
R_DAC1(4)
G_DAC1(4)
B_DAC1(4)
R403
R401
6
SN74ACT86PW
U3C
8
R402
75.0R
75.0R
75.0R
R859 33R
R860 33R
+3.3V_BUS
R467
+3.3V_BUS
4.7K
R468
4.7K
+3.3V_BUS
CRT1DDCDATA(4)
CRT1DDCCLK(4)
C C
HSYNC_DAC1(4,13)
VSYNC_DAC1(4,13)
+3.3V_BUS
1
1
BSN20
Q13
BSN20
Q12
32
+5V_BUS
32
U3B
4
5
9
10
SN74ACT86PW
+5V_BUS
R464
6.8K
R463
6.8K
PLACE CLOSE TO ASIC
L51 47nH
L52 47nH
L53 47nH
C401
C402
C403
6.8pF
6.8pF
6.8pF
L54 47nH
L55 47nH
L56 47nH
C404
C405
8pF
8pF
C406
8pF
C408
C407
5pF
5pF
DNI DNI DNI
C409
5pF
R_DAC1_F
G_DAC1_F
B_DAC1_F
DDCDATA_DAC1_5V
DDCCLK_DAC1_5V
HSYNC_DAC1_R
VSYNC_DAC1_R
OPTIONAL ESD/HOTPLUG PROTECTION DIODES
+3.3V_BUS+3.3V_BUS
BAT54SLT1
PLACE CLOSE TO
CONNECTOR
+3.3V_BUS
+12V_BUS+12V_BUS+12V_BUS+12V_BUS
D13
D10
D11
BAT54SLT1
D12
BAT54SLT1
BAT54SLT1
D14
BAT54SLT1
DNI DN I DNI DNI DNI DNI DNI
R465 33R
R466 33R
C751
NI NI
22pF
D15
BAT54SLT1
C752
22pF
D16
BAT54SLT1
C562
100nF
PRIMARY VGA
CONNECTOR
F1
750mA
+5VCON1
B39
Bead
1
2
3
11
12
4
15
9
13
14
5
6
7
8
10
16
17
+5V_BUS
+5VCON1 (17,19)
+5V_DIN2 (17)
J5
R
G
B
MS0
MS1
MS2
MS3
NC
HS
VS
VSS
VSS#6
VSS#7
VSS#8
VSS#10
CASE
CASE#17
SLIM VGA HT 6.27MM
SECONDARY VGA DAC2
OPTIONAL ESD/HOTPLUG PROTECTION DIODES
+3.3V_BUS+3.3V_BUS +3.3V_BUS
D17
PLACE CLOSE TO ASIC
R_DAC2_F
G_DAC2_F
B_DAC2_F
C575
5pF
www.vinafix.vn
3
R_DAC2_F (17)
G_DAC2_F (17)
B_DAC2_F (17)
C451
6.8pF
1
BSN20
1
BSN20
Q15
74ACT08MTC
U2C
U2D
74ACT08MTC
L71 47nH
L72 47nH
L73 47nH
C452
C453
6.8pF
6.8pF
+5V_BUS
32
Q14
+5V_BUS
32
8
11
6.8K
R480
6.8K
R482
R31 33R
R32 33R
R_DAC2(4)
G_DAC2(4)
B_DAC2(4)
B B
CRT2DDCDATA(4)
CRT2DDCCLK(4)
A A
HSYNC_DAC2(4)
VSYNC_DAC2(4)
+5V_BUS
5
R451 75.0R
R452 75.0R
R453 75.0R
+3.3V_BUS
R479
4.7K
+3.3V_BUS
R481
4.7K
10
9
13
12
C454
C455
8pF
8pF
R825 33R
R824 33R
L74 47nH
L75 47nH
L76 47nH
C456
8pF
4
C573
C574
5pF
5pF
DNI DNI DNI
DDCDATA_DAC2_R (17)
DDCCLK_DAC2_R (17)
HSYNC_DAC2_R (17)
VSYNC_DAC2_R (17)
BAT54SLT1
D18
BAT54SLT1
+12V_BUS+12V_BUS+12V_BUS+12V_BUS
D19
BAT54SLT1
D20
BAT54SLT1
DNIDNIDNIDNI
C750
C749
22pF
22pF
DNI DNI
2
D21
BAT54SLT1
BAT54SLT1
BAT54SLT1
D23
D22
DNIDNIDNI
PLACE CLOSE TO
CONNECTOR
+5V_DIN1
1
2
3
11
12
4
15
9
13
14
5
6
7
8
10
16
17
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV410 DV VG VIVO 256MB DDR3
Size Docum e n t N u mb er R e v
C
Date: Sheet
105-A41800-00
1
+5V_DIN1 (17)
DNI
MJ4
R
G
B
DDC2_MONID0
MS0
DDC2_MONID1(SDA)
MS1
DDC2_MONID2
MS2
DDC2_MONI D3(S CL)
MS3
NC
HS
VS
VSS
VSS#6
VSS#7
VSS#8
VSS#10
CASE
CASE#17
SLIM VGA HT 6.27MM
15 27Thursday, January 27, 2005
of
3
5
D D
4
MUST BE INSTALLED IF NO
TMDS IS INSTALLED
LCDCNTL_R[3..0]
+3.3V_BUS
3
2
1
LCDCNTL_R0
LCDCNTL_R1
LCDCNTL_R2
LCDCNTL_R3
RP600A 10K
RP600B 10K
RP600C 10K
RP600D 10K
81
72
63
54
Place close to TMDS
TXCP_EXT (17)
TXCM_EXT (17)
TX2P_EXT (17)
C481 100nF
C482 100nF
C483 100nF
C484 100nF
C465
100nF
C471
22uF_10V
+3.3V_BUS
C476
100pF
TX2M_EXT ( 17)
TX1P_EXT (17)
TX1M_EXT ( 17)
TX0P_EXT (17)
TX0M_EXT ( 17)
B31 200R
C466
47uF
C477
2.2nF
+3.3V_BUS+AVCC_TMDS
Max 25 mA
+3.3V_BUS
B32
200R
22uF_10V
C1236
REG9
TL431CDBVR
+12V_BUS
R301
360R
R304
680R
4
NC
1
NC
R491
2
2K
5 3
VID/DVO_R[11..0](4)
C C
LCDCNTL_R[3..0](4)
B B
AGP_RESET#(2,18,21)
VID/DVO_R[11..0]
+3.3V_BUS
LCDCNTL_R[3..0]
+3.3V_BUS
INSTALL FOR Si164
HI = I2C SELECT,LO = I2C CTRL RESET
+3.3V_BUS
R625 1K
R620 1K
R483 5.1K
R1103
R1104 0R
Do not install
R484 0R
R492 0R
VID/DVO_R0
VID/DVO_R1
VID/DVO_R2 TX0M_EXT
VID/DVO_R3
VID/DVO_R4
VID/DVO_R5
VID/DVO_R6
VID/DVO_R7
VID/DVO_R8
VID/DVO_R9
VID/DVO_R10
VID/DVO_R11
I2C_ADDR
LCDCNTL_R1
LCDCNTL_R0
LCDCNTL_R2
LCDCNTL_R3
+VREF_TMDS
MSEN_TMDS
HPD_ExtTMDS
33K
I2C_RST
SDA(4,14)
SCL(4,14)
18
17
16
15
14
13
10
9
8
7
6
5
24
20
21
19
12
11
48
44
25
26
27
1
31
47
U37
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
CTL3/A2
HSYNC
VSYNC
DE
IDICK+
IDCK-
MSEN
EDGE/HTPLG
ISEL/RST#
SDA
SCL
GND#1
AGND#31
PD#
SiI1162
TX0+
TX1+
TX2+
TXC+
AVCC
AVCC#40
AGND
AGND#43
VREF
EXT_SWING
PVCC1
PVCC2
PGND
PGND#45
VCC#22
GND#23
TH_GND
TX0-
TX1-
TX2-
TXC-
VCC
GND
35
36
38
39
41
42
32
33
34
40
37
43
+VREF_TMDS
2
30
28
46
29
45
22
3
4
23
49
TX0P_EXT
TX1M_EXT
TX1P_EXT
TX2M_EXT
TX2P_EXT
TXCM_EXT
TXCP_EXT
C460
100pF
C461
2.2nF
EXT_SWING
C469
100pF
C472
100pF
C470
100nF
C473
100nF
C462
100nF
R1240 330R
R1241 330R
R1242 330R
R1243 330R
C463
100pF
C479
100pF
C474
2.2nF
C464
2.2nF
R485 680R
+PVCC_TMDS
C480
100nF
C475
100nF
SELECT VREF ACCORDING
TO SWING ON D[23:0]
+VDDR4
+3.3V_BUS
R486
R487
20K
20K
CMPT3904
Q32
402 402
1
Q33
2 3
CMPT3904
R488 20K
402
1
2 3
www.vinafix.vn
R489 20K
402
3
HPD_ExtTMDS_DVI (17)HPD_ExtTMDS(4)
SELECT VREF ACCORDING
TO SWING ON D[23:0]
A A
5
HPD_ExtTMDS
D35
MMBZ5222BLT1
R490
1 3
100K
4
C478
100nF
X7R
C467
100nF
X7R
R302
1.0K
R303
1.0K
2
+VREF_TMDS
<Variant Name>
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7N6
(905) 882-2600
Title
AGP RV410 DV VG VIVO 256MB DDR3
Size Docum e n t N u mb er R e v
C
Date: Sheet
105-A41800-00
1
of
16 27Thursday, January 27, 2005
3
5
4
3
2
1
PRIMARY DV I - I C ON NECTOR (DVI-I1)
(Internal TMDS + DAC2 VGA)
B38 Bead
+5V_DIN1
Place close to
the connector
C558
100nF
DVI-I1
J4
25
CASE
1
TMDS Data2-
2
TMDS Data2+
3
TMDS Data2/4 Shield
4
TMDS Data4-
5
TMDS Data4+
6
DDC Clock
7
DDC Data
8
Analog VSYNC
9
TMDS Data1-
10
TMDS Data1+
11
TMDS Data1/3 Shield
12
TMDS Data3-
13
TMDS Data3+
14
+5V Power
15
GND (for +5V)
16
Hot Plug Detect
17
TMDS Data0-
18
TMDS Data0+
19
TMDS Data0/5 Shield
20
TMDS Data5-
21
TMDS Data5+
22
TMDS Clock Shield
23
TMDS Clock+
24
TMDS Clock-
C1
Analog Red
C2
Analog Green
C3
Analog Blue
C4
Analog HYNC
C5
Analog GND
C6
Analog GND#C6
26
CASE#26
27
CASE#27
28
CASE#28
29
CASE#29
30
CASE#30
DVICONNECTOR
+5V_DIN1(15)
D D
TX2M(4)
TX2P(4)
DDCCLK_DAC2_R(15)
DDCDATA_DAC2_R(15)
VSYNC_DAC2_R(15)
TX1M(4)
TX1P(4)
+5VCON1(15,19)
TX0M(4)
TX0P(4)
TXCP(4)
TXCM(4)
R_DAC2_F(15)
G_DAC2_F(15)
B_DAC2_F(15)
HSYNC_DAC2_R(15)
C C
HPD1(4)
2 1
R456
D9
100K
2.5V
CMPT3904
Q25
+3.3V_BUS
R454
20K
402 402
2 3
CMPT3904
R455
20K
1
Q26
1
2 3
R457 20K
R458 20K
402
402
SECONDARY DVI-I CONNECTOR (DVI-I2)
(Ext TMDS + DAC1 VGA)
TX2M_EXT(16)
B B
A A
5
TX2P_EXT(16)
DDCCLK_DAC1_5V(15)
DDCDATA_DAC1_5V(15)
VSYNC_DAC1_R(15)
TX1M_EXT(16)
TX1P_EXT(16)
+5V_DIN2(15)
HPD_ExtTMDS_DVI(16)
TX0M_EXT(16)
TX0P_EXT(16)
TXCP_EXT(16)
TXCM_EXT(16)
R_DAC1_F(15)
G_DAC1_F(15)
B_DAC1_F(15)
HSYNC_DAC1_R(15)
4
www.vinafix.vn
3
+5V_DIN2
DVI-I2
J6
25
CASE
1
TMDS Data2-
2
TMDS Data2+
3
TMDS Data2/4 Shield
4
TMDS Data4-
5
TMDS Data4+
6
DDC Clock
7
DDC Data
8
Analog VSYNC
9
TMDS Data1-
10
TMDS Data1+
11
TMDS Data1/3 Shield
12
TMDS Data3-
13
TMDS Data3+
14
+5V Power
15
GND (for +5V)
16
Hot Plug Detect
17
TMDS Data0-
18
TMDS Data0+
19
TMDS Data0/5 Shield
20
TMDS Data5-
21
TMDS Data5+
22
TMDS Clock Shield
23
TMDS Clock+
24
TMDS Clock-
C1
Analog Red
C2
Analog Green
C3
Analog Blue
C4
Analog HYNC
C5
Analog GND
C6
Analog GND#C6
26
CASE#26
27
CASE#27
28
CASE#28
29
CASE#29
30
CASE#30
DVICONNECTOR
<Variant Name>
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV410 DV VG VIVO 256MB DDR3
Size Docum e n t N u mb er R e v
C
2
Date: Sheet
105-A41800-00
1
3
of
17 27Thursday, January 27, 2005
5
4
3
2
1
3.3V, 80mA RMS, 125mA MAX
12
+RTAVDD
GND_RT GND_RT
R1689
10R
C1604
1.0uF
+VADCD
+VADCA
R1703
4.7K
C1589
22uF_16V
47
49
48
66
60
61
33
34
35
36
37
38
39
40
27
28
58
59
57
56
55
43
45
44
46
50
51
52
53
54
69
70
73
74
67
68
C1591
1.0uF
VAGCVDD
VAGCVSS#49
VAGCVSS
VDACVDD
VDACBVSS
VDACJVSS
VIND0
VIND1
VIND2
VIND3
VIND4
VIND5
VIND6
VIND7
VINGATEA
VINGATEB
CF
CR
VAGCCAP
VIDEOGNDSENSE
VCLAMPCAP
VADCDVDD
VADCAVDD
VADCDVSS
VADCAVSS
COMP0
COMP1
COMP2
YF_COMP3
YR_COMP4
XTALIN
XTALOUT
TESTEN
RESETB
PLLVDD
PLLVSS
18
VSSC
26
VSSC#26
VSSC#77
VSSC#83
77
83
71
81
29
VDDR1VDDC
VDDR#71
VDDR#81
VDDR#29
VSSR#2
VSSC#100
VSSR#12
2
12
100
C1595
10nF
25
99
76
VDDC#99
VDDC#76
VSSR
VSSR#72
VSSR#3030VSSR#32
VSSR#90
82
72
90
C1596
1.0uF
41
31
VDDC#41
VDDR#31
CLKOUT0_GPIO0
CLKOUT1_GPIO1
CLKOUT2_GPIO2
VSSC#42
42
32
GND_RT
+RTVDDC
C1597
1.0uF
U111
SAD0
SAD1
SAD2
SAD3
SAD4
SAD5
SAD6
SAD7
DS_VIPCLK
AS_HCTL
SRDY_IRQB
HAD0
HAD1
SDA
SCL
ADO
ADIO
WS
BITCLK
SPDIF
BYTCLK
SYNC
Y_RED
C_GREEN
COMP_BLUE
RSET
GPIO3
GPIO4
GPIO5
GPIO6
PDATA0
PDATA1
PDATA2
PDATA3
PDATA4
PDATA5
PDATA6
PDATA7
PCLK
RAGE_THEATER
C1598
1.0uF
91
92
93
94
95
96
97
98
88
87
86
84
85
15
16
22
24
23
21
19
89
75
62
63
64
65
78
79
20
13
14
17
80
4
5
6
7
8
9
10
11
3
+3.3V_BUS
C1592
C1599
1.0uF
22uF_16V
GND_RT
RP196A 33R
RP196B 33R
R1692 47K
RP196D 33R
RP196C 33R
RP19 4D 33R
5 4
RP19 4C 33R
6 3
RP194B 33R
7 2
RP194A 33R
8 1
RP19 5D 33R
5 4
RP19 5C 33R
6 3
RP195B 33R
7 2
RP195A 33R
8 1
Place close to the Rage
Theater
R1704
12
R1687
L79
3.3uH
10R
C1593
22uF_16V
GND_RT GND_RT
81
72
54
63
R1697 10K
R1695 10K
33R
+VADCA +VADCD
C1600
1.0uF
GND_RT
GND_RT
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VID[7..0]
L80
3.3uH
C1594
22uF_16V
+3.3V_BUS
GND_RT
R1696
4.7K
12
R1688
10R
C1601
1.0uF
CLK_VIPCLK (4)
VPHCTL (4)
VHAD0 (4)
VHAD1 (4)
SPDIFOut (19)
CLK_RT (4)
VID[7..0] (4)
CLK_VIDCLK (4)
+5V_BUS
R1690
75.0R
R1693
75.0R
R1694
75.0R
B49
Bead
26 ohm
600mA
C1590
1uF
C1613 2.2uF
GND_VIN
REG8
3.3V
IN3OUT
CASE
GND
1
GND_RT
12
L69
3.3uH
C1605
22uF_16V
GND_RT
C1608 0.1uF
2
4
L67
3.3uH
C1603
22uF_16V
R1691
10R
GND_RT
C1606
1.0uF
C1610
0.068uF
C1611
C1612 2.2uF
22nf
D D
3.3uH
L68
L70
L77
1 2
3.3uH
1 2
3.3uH
1 2
C1602
330pF
C1607
330pF
C1609
330pF
CompR(19)
LumaR(19)
C C
ChromaR(19)
27MHZ
C1616
22pF
AGP_RESET#(2,16, 21)
B B
3.3uH
C1614
22uF_16V
Ca1 Ca2
L78
C1617
22pF
+RTAVDD
12
Y2
27_MHZ
2 1
R1701
10R
C1615
1.0uF
R1603 330R
R1604
1.0M
GND_RT
IMPORTANT
Layout Guide line of THEATER
#1 : Ca1 and Ca2 have to be placed as close as possible to the respective pins of Rage THEATER
#2 : GND_VIN should be seperated from Digital or Chassis Ground and have no loops
A A
5
#3 : GND_VIN should be connected to Digital GND plane at one point as close as possible to
pin 56 of THEATER
4
Put 2D line as close as possible to pin 56 of Rage Theater
GND_VIN
GND_RT
www.vinafix.vn
3
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV410 DV VG VIVO 256MB DDR3
Size Docum e n t N u mb er R e v
C
2
Date: Sheet
105-A41800-00
1
3
of
18 27Thursday, January 27, 2005
5
4
3
2
1
TV Out (SVHS) MiniDIN 7-pin
Jm1
Use 5050005000 Bead 2.5K
DC_Strap3(4,13)
TBLuma
D D
TBChroma
Connector Jm1 uses the
same footprint as Jm2
and Jm3
R878 0R
R606 220R
R608 220R
R504 220R
Rm22
Rm23
Rm24
C527
82pF
Conn_DIN_Mini_Circular_7_Pin_with_O _R ing
SCART
TBLuma_R
TBChroma_R
COMPTBComp
CompR_F
PIN1
PIN2
B52
B51
R1578
0R
J7
6
HDTV_OUT_DET#
3
Y-OUT
4
C-OUT
7
Comp_out
5
SYNC
1
GND
2
GND#2
8
CASE
9
CASE#9
10
CASE#10
SPDIF - OUT
C C
D2
BAT54SLT1
C1144
100nF
R1575 390R
R1577
100R
BLM21A121SPT
B55
C1145
100pF
U3D
SPDIFOut(18)
12
13
SN74ACT86PW
11
+5V_BUS
Not Installed
TV-OUT
PIN1
ViVO connector (Installed only if Rage Theater is installed)
SCART
TBLuma_R
TBChroma_R
CompR_MUX_BR
LumaR_MUX_BR
ChromaR_MUX_BR
Connector Jm2 uses the
same footprint as Jm1
and Jm3
Not Installed
STEREOSCOP I C DISPLAY
CONNECTOR
STEREOSYNC(4)
Not Installed
B53
Rm21
R763 0R
DNI
C753
100nF
1
2
B56
+5V_BUS
147
C1141
220pF
SN74ACT86PW
COMP
B54
C1142
220pF
+5VCON1(15,17)
U3A
Rm3
R517 0R
3
Connector Jm3 uses the
same footprint as Jm1
and Jm2
GND_VIN
DNI
B50 Bead
Bm4
COMP
DNI
PIN1
Video In Mux when Bracket and Front panel connector are installed
CompR_F
PIN1
PIN2
C1143
120pF
B20
DNI
MJ7
1
2
7
8
9
10
MiniDIN_3_Pin
1
2
7
CASE
CASE
CASE
Jm3
Jm2
MJ8
6
HDTV_OUT_DET#
3
Y-OUT
4
C-OUT
7
Comp-out
5
Comp-in
1
GND
2
GND#2
11
Luma-in
12
Chroma-in
8
CASE
9
CASE#9
10
CASE#10
9 PIN MINIDIN
11
15
C7633pF
U96
1
SEL
2
1A0
3
1A1
5
1B0
6
1B1
1C0
1C1101D0
E
PI5V330
2710000800
C7733pF
C7833pF
+5V_BUS+5V_BUS
VCC
YA
YB
YC
YD
1D1
GND
JP1
1
1
2
2
3
3
4
4
header_1x4_YELLOW
B19
120R
B6
220R
16
4
7
9
12
13
14
8
LumaR_MUX_FP
LumaR_MUX_BR
C735
100nF
4250010400
2
CompR (18)
ChromaR (18)
LumaR (18)
<Variant Name>
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV410 DV VG VIVO 256MB DDR3
Size Docum e n t N u mb er R e v
C
Date: Sheet
105-A41800-00
1
of
19 27Thursday, January 27, 2005
3
Y_DAC2 TBLuma
Y_DAC2(4)
B B
C_DAC2(4)
COMP_DAC2(4)
COMP_DAC2
C_DAC2
GND_TVVSSN
GND_TVVSSN
GND_TVVSSN
R912
75.0R
R913
75.0R
R914
75.0R
MUX BYPASS
CompR
A A
LumaR
0R
0R
0R
Not Installed
5
L20 470nH
C583
47pF
L21 470nH
C585
47pF
L22 470nH
C588
47pF
R967
ChromaR_MUX_BRChromaR
R968
CompR_MUX_BR
R969
LumaR_MUX_BR
ChromaR_MUX_FP
R9700R
CompR_MUX_FP
R9710R
LumaR_MUX_FP
R9720R
C584
47pF
C586
47pF
C587
47pF
TBChroma
TBComp
32
SW1B
DIP_SWX2
R365
10K
CompR_MUX_BR
CompR_MUX_FP
ChromaR_MUX_BR
ChromaR_MUX_FP
Not Installed
Video In Front panel connector
ChromaR_MUX_FP
CompR_MUX_FP
LumaR_MUX_FP
B16 120R
B17 120R
B18 120R
Not Installed
4
www.vinafix.vn
3
5
D D
4
3
2
1
Rialto ASIC p/n is: 218BAPAGA11F
U112A
PETp0_GFXRp0(3)
PETn0_GFXRn0(3)
PETp1_GFXRp1(3)
PETn1_GFXRn1(3)
PETp2_GFXRp2(3)
PETn2_GFXRn2(3)
PETp3_GFXRp3(3)
PETn3_GFXRn3(3)
PETp4_GFXRp4(3)
PETn4_GFXRn4(3)
PETp5_GFXRp5(3)
C C
B B
PETn5_GFXRn5(3)
PETp6_GFXRp6(3)
PETn6_GFXRn6(3)
PETp7_GFXRp7(3)
PETn7_GFXRn7(3)
PETp8_GFXRp8(3)
PETn8_GFXRn8(3)
PETp9_GFXRp9(3)
PETn9_GFXRn9(3)
PETp10_GFXRp10(3)
PETn10_GFXRn10(3)
PETp11_GFXRp11(3)
PETn11_GFXRn11(3)
PETp12_GFXRp12(3)
PETn12_GFXRn12(3)
PETp13_GFXRp13(3)
PETn13_GFXRn13(3)
PETp14_GFXRp14(3)
PETn14_GFXRn14(3)
PETp15_GFXRp15(3)
PETn15_GFXRn15(3)
PCIE_REFCLKP(3)
PCIE_REFCLKN(3)
PCIE_REFCLKP(3)
PCIE_REFCLKN(3)
R1774 49.9R R1775 33.2R
R1777 49.9R
R1776 33.2R
Place the reisitors
close to ASIC
U13
T13
T14
R14
R12
P12
P13
N13
N14
M14
M12
L12
L13
K13
K14
J14
J12
H12
H13
G13
G14
F14
F12
E12
E13
D13
D14
C14
C12
B12
B13
A13
W16
V16
Y11
W11
R20
W19
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13P
PCIE_TX13N
PCIE_TX14P
PCIE_TX14N
PCIE_TX15P
PCIE_TX15N
PCIE_REFCLKP
PCIE_REFCLKN
RefCLKP
RefCLKN
PERSTB
PCIETEST
Rialto A11
PART 1 OF 4
PCIE TX
Clock
V17
PCIE_RX0P
U17
PCIE_RX0N
P
C
I
ÂE
X
P
R
E
S
S
I
N
T
E
R
F
A
C
E
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PCIE RX
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N
PCIE_RX13P
PCIE_RX13N
PCIE_RX14P
PCIE_RX14N
PCIE_RX15P
PCIE_RX15N
Calibration
PCIE_CALRN
PCIE_CALRP
PCIE_CALI
R_EXT
U19
T19
T16
R16
R17
P17
P19
N19
N16
M16
M17
L17
L19
K19
K16
J16
J17
H17
H19
G19
G16
F16
F17
E17
E19
D19
D16
C16
C17
B17
AA21
Y21
W21
Y8
R1014 100R
R1013 150R
R1012 10K
R1770 7 5 0R
+PCIE_VDDR
GFXTp0_PERp0 (3)
GFXTn0_PERn0 (3)
GFXTp1_PERp1 (3)
GFXTn1_PERn1 (3)
GFXTp2_PERp2 (3)
GFXTn2_PERn2 (3)
GFXTp3_PERp3 (3)
GFXTn3_PERn3 (3)
GFXTp4_PERp4 (3)
GFXTn4_PERn4 (3)
GFXTp5_PERp5 (3)
GFXTn5_PERn5 (3)
GFXTp6_PERp6 (3)
GFXTn6_PERn6 (3)
GFXTp7_PERp7 (3)
GFXTn7_PERn7 (3)
GFXTp8_PERp8 (3)
GFXTn8_PERn8 (3)
GFXTp9_PERp9 (3)
GFXTn9_PERn9 (3)
GFXTp10_PERp10 (3)
GFXTn10_PERn10 (3)
GFXTp11_PERp11 (3)
GFXTn11_PERn11 (3)
GFXTp12_PERp12 (3)
GFXTn12_PERn12 (3)
GFXTp13_PERp13 (3)
GFXTn13_PERn13 (3)
GFXTp14_PERp14 (3)
GFXTn14_PERn14 (3)
GFXTp15_PERp15 (3)
GFXTn15_PERn15 (3)
PERST#(3)
PCIETEST(25)
DNI
R877
0R
402
DNI
R36
4.7K
402
Share the adjacent
pads of R36 and R877
CLK R42 R36
1.2V
3.3V
3150000000 (0R)
4
3150018100 (180R)3150030100 (300R)
<Variant Name>
DNI
www.vinafix.vn
3
2
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV410 DV VG VIVO 256MB DDR3
Size Docum e n t N u mb er R e v
C
Date: Sheet
105-A41800-00
1
of
20 27Thursday, January 27, 2005
3
A A
+3.3V_BUS
C53
100nF
402
Y6
4
VCC
2
VSS
25.000MHz
Use 100MHZ OSC
Place R36, R42 close to Y6,
Place Y6 close to the ASIC.
R42
300R
402
3
OUT
1
OE
+3.3V_BUS
100MHZ Bypass Clock
5
5
4
3
2
1
D D
C C
B B
+VDDQ_BUS
R37 47R
402
Note: Overlap the footprints of Y4, Y5.
Place Y4, Y5 close to ASIC.
OPTION 1: Crystal Circuit
C82 18pF
Y4
25.000MHz
C81 18pF
Use 18pF, 1%, Cap
A A
OPTION 2: Oscillator Circuit
+3.3V_BUS
C18
100nF
402
5
Y5 CLK
1.2V
3.3V
2 1
Y5
4
VCC
OUT
2
VSS
OE
25.000MHz
Place R27, R28 close to Y5
R27
3230022100, 220R, 5%, 603
3240221000, 221R, 1%, 603
3230033000, 33R, 5%, 603
3
1
+3.3V_BUS
AGP_SBA[7..0](2)
AGP_ST[2..0](2)
R35
1.0M
402
R27
220R
R28
130R
R28
3230013100, 130R, 5%, 603
3240127000, 127R, 1%, 603
DNI
AGP_AD[31..0](2)
AGP_C/BE#[3..0](2)
AGP_ADSTB0#(2)
AGP_ADSTB1#(2)
AGP_AGPREFCG(2)
AGP_MB_8X_DET#(2)
DNI
AGP_AGPCLK(2)
AGP_DEVSEL#(2)
AGP_FRAME#(2)
AGP_ADSTB0(2)
AGP_ADSTB1(2)
AGP_SBSTB(2)
AGP_SBSTB#(2)
AGP_DBI_LO(2)
AGP_DBI_HI(2)
+3.3V_BUS
R29
0R
402
DNI
AGP_RESET#(2,16, 18)
AGP_REQ#(2)
AGP_GNT#(2)
AGP_PAR(2)
AGP_STOP#(2)
AGP_TRDY#(2)
AGP_IRDY#(2)
AGP_INTR#(2)
AGP_WBF#(2)
AGP_RBF#(2)
AGP_SBA[7..0]
AGP_ST[2..0]
+VDDQ_BUS
AGP_AD[31..0]
AGP_C/BE#[3..0]
R46 1K
R48 1K
R49 1K
4
U112B
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
AGP_C/BE#0
AGP_C/BE#1
AGP_C/BE#2
AGP_C/BE#3
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
AGP_ST0
AGP_ST1
AGP_ST2
STP_AGPB(24)
DNI
A6
A5
B6
B5
C5
C4
C3
D4
E4
F4
F3
G4
G3
H3
H4
J3
F6
F5
G6
H7
H6
J6
J7
K7
L7
M7
M6
M5
N7
N6
P7
P6
E3
J4
G7
J5
AA2
AB3
U6
V5
E7
F7
L4
L3
M3
M4
W4
R7
T6
D2
K6
R3
U4
U3
T4
T3
P4
P3
N4
N3
W3
V4
V3
R4
C2
L6
D6
E6
R5
R6
T7
AA3
AA4
Y3
AA8
AB8
Rialto A11
www.vinafix.vn
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AD_1
AD_2
AD_3
AD_4
AD_5
AD_6
AD_7
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AD_9
AD_10
AD_11
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AD_13
AD_14
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AD_20
AD_21
AD_22
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AD_24
AD_25
AD_26
AD_27
AD_28
AD_29
AD_30
AD_31
C_BEB_0
C_BEB_1
C_BEB_2
C_BEB_3
PCICLK
RSTB
REQB
GNTB
PAR
STOPB
DEVSELB
TRDYB
IRDYB
FRAMEB
INTAB
WBFB
RBFB
AD_STBF_0
AD_STBF_1
SB_STBF
SBA_0
SBA_1
SBA_2
SBA_3
SBA_4
SBA_5
SBA_6
SBA_7
ST_0
ST_1
ST_2
SB_STBS
AD_STBS_0
AD_STBS_1
AGPVREF
AGPTEST
DBI_LO
DBI_HI
AGP8X_DETB
STP_AGPB
AGP_BUSYB
RSTB_MSK
XTO
XTI
PART 2 OF 4
PCI / AGPAGP2X
4X8X
AGP
AGP
Additional
CLK
GPIOMISC
NC
REFCLKBYP
3
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
GPIO_18
GPIO_19
GPIO_20
GPIO_21
GPIO_22
GPIO_23
GPIO_24
ROMCSB
VrefG1
PLLTEST
TESTEN
Y9
AB10
AA10
Y10
AA11
Y12
AA12
AB12
W18
Y20
AB20
AA13
AB13
AA14
AB14
AA15
AB15
AA16
AB16
AA17
AB17
AA18
AB18
Y18
AA19
Y19
W20
AB4
W6
Y4
TESTEN
B_GPIO0
B_GPIO1
B_GPIO2
B_GPIO3
B_GPIO4
B_GPIO5
B_GPIO6
B_GPIO7
B_GPIO11
B_GPIO12
B_GPIO13
B_GPIO14
B_GPIO15
B_GPIO16
B_GPIO17
B_GPIO18
B_GPIO19
B_GPIO20
B_GPIO21
B_GPIO22
B_GPIO23
B_GPIO24
B_ROMCS#
REFCLKBYP (24)
R47 1K
R45 1K
B_GPIO8
B_GPIO9
B_GPIO10
+3.3V_BUS
R589
499R
R588
499R
B_GPIO[7..0]
B_GPIO[24..11]
B_GPIO[7..0] (24)
B_GPIO[24..11] (24)
B_GPIO9
B_ROMCS#
2
R38 33R
R39 33R
R40 33R
R41 33R
ROM_SOB_GPIO8
SI/A16
SCK/WEbB_GPIO10
CSb
TO SERIAL EEPROM 512K/1M
<Variant Name>
Title
Size Docum e n t N u mb er R e v
C
Date: Sheet
ROM_SO (4)
SI/A16 (4)
SCK/WEb (4)
CSb (4)
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
AGP RV410 DV VG VIVO 256MB DDR3
105-A41800-00
1
21 27Thursday, January 27, 2005
3
of
5
D D
4
3
2
1
U112C
+B_VDDC
C647
+B_PVDD
4
C653
10nF
C101
100nF
C87
1.0uF
C649
10nF
C650
10nF
C97
10uf
C629
10nF
C100
1.0uF
1.0uF
C651
10nF
C95
10uf
C655
C658
10nF
C986
47uF
10nF
C657
10nF
+3.3V_BUS
C645
10nF
C86
22uF_16V
GND_B_PVSS
C C
B B
NOTE: Place REG1 close to ASIC.
REGULATOR FOR B_1.8V
Vin=+3.3V
Vout=+1. 8V (150mA)
+3.3V_BUS
B37
200R
A A
Use SP6201EM5-ADJ, 200mA, S OT 23-5, DO< 500m V (2480041200 ) $0.11
Alt. TI TPS76301, ADJ, 150mA, DO<300mV, SOT23 (2480040800)
Alt. TI TPS76318, 1.8V, 150MA, DO<300mV, SOT23 (2480003900)
SP6201EM5-ADJ
Vo=1.25 (1+R1/R2)
3160681000, 681R, 1%
R1
3160150100, 1.50K, 1%
R2
C107
1.0uF
+VAA_DIO
+VAA_XTL
+B_PVDD
REG1
1.8V
1
IN
3
EN
TPS76301, ADJ
Vo=1.186 (1+R1/R2)
B35 200R
B36 200R
B40 200R
4
NC/FB
5
OUT
GND
2
5
+B_1.8V
R169
681R
R1
1% 402
R168
R2
1.50K
1% 402
C108
22uF_6.3V
DNI
Dual FootPrint
C96
C674
1.0uF
1.0uF
C656
C652
10nF
10nF
C11
VDDC_1
F9
VDDC_2
K11
C84
10uF_10V
C630
C631
10nF
10nF
www.vinafix.vn
VDDC_3
B11
VDDC_4
K9
VDDC_5
F11
VDDC_6
G10
VDDC_7
G11
VDDC_8
P11
VDDC_9
P10
VDDC_10
L9
VDDC_11
L11
VDDC_12
B9
VDDC_13
F10
VDDC_14
G9
VDDC_15
L10
VDDC_16
P9
VDDC_17
C9
VDDC_18
B10
VDDC_19
C10
VDDC_20
K10
VDDC_21
AB9
VDDCI
U9
VDDR3_1
W8
VDDR3_2
U10
VDDR3_3
V9
VDDR3_4
W9
VDDR3_5
AB5
PVDD
AA5
PVSS
Rialto A11
3
C628
10nF
C85
1.0uF
C654
10nF
PLL
NC
Core
GPIO
AGP
PART 3 OF 4
P
O
W
E
R
PCI-Express
AGPDIFF
Volt COV
OSC
I/O
PCIE_PVDD_12_1
PCIE_PVDD_12_2
PCIE_PVDD_12_3
PCIE_PVDD_12_4
PCIE_PVDD_18
PCIE_VDDR_18_2
PCIE_VDDR_18_3
PCIE_VDDR_18_4
PCIE_VDDR_18_1
PCIE_VDDR_12_1
PCIE_VDDR_12_2
PCIE_VDDR_12_3
PCIE_VDDR_12_4
PCIE_VDDR_12_5
PCIE_VDDR_12_6
PCIE_VDDR_12_7
PCIE_VDDR_12_8
PCIE_VDDR_12_9
VDDP_1
VDDP_2
VDDP_3
VDDP_4
VDDP_5
VDDP_6
VDDP_7
VDDP_8
VDDP_9
VDDP_10
VDDP_11
VDDP_12
VDDP_13
VDDP_14
VDDP_15
VDDP_16
VDDP_17
VDDP_18
VDDP_19
VDDP_20
VDDP_21
VDDP_22
VDDP_23
VDDP_24
VDD15_1
VDD15_2
VDD15_3
VDD15_4
VDD15_5
VAA_DIO
AGND_DIO_1
AGND_DIO_2
VAA_XTL
AGND_XTL_1
AGND_XTL_2
F21
A21
B21
E21
A15
A16
A17
A18
A19
W13
Y13
Y14
W12
W14
Y16
W15
Y15
Y17
A4
E2
G2
L2
U2
W2
AB2
G5
K4
B4
T5
W5
B2
N2
E5
D8
E8
C8
H8
J8
M8
N8
R8
A2
B8
U8
A8
T9
V8
AB6
AA6
Y6
AB7
C103
AA7
Y7
100nF
2
+PCIE_PVDD_12
C975
1.0uF
C47
100nF
402 402
C54
100nF
+VAA_XTL
C102
1.0uF
GND_XTL
<Variant Name>
C55
100nF
C988
1.0uF
+PCIE_PVDD_18
+PCIE_VDD R_12
CP13B
C985
1.0uF
C51
100nF
C52
100nF
CP13A
10nF
8 1
CP27A
10nF
8 1
1.5V
CP13C
10nF
7 2
CP27B
10nF
7 2
+VDDC_CT
C58
10uf
C99
100nF
NOTE: THIS IS A DRAWING. THESE
GROUNDS MUST BE MANUALLY
CONNECTED TO THE GROUND PLANE
Title
Size Docum e n t N u mb er R e v
C
Date: Sheet
CP13D
10nF
10nF
6 3
5 4
+VDDQ_BUS
CP27C
CP27D
10nF
10nF
6 3
5 4
+VAA_DIO
C98
1.0uF
GND_DIO
GND_B_PVSS GND_DIO GND_XTL
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
AGP RV410 DV VG VIVO 256MB DDR3
105-A41800-00
1
3
of
22 27Thursday, January 27, 2005
5
4
3
2
1
U112D
D D
C C
B B
T17
L21
W17
C21
B19
C19
D18
E18
G18
H18
K18
L18
M19
N18
P18
M18
R19
T18
L16
H16
E16
B16
T15
P16
F15
L15
G17
K17
F18
U18
U12
V15
B18
B15
C15
D15
E15
G15
H15
J15
K15
M15
N15
P15
R15
U15
V18
V14
R18
A14
C13
P14
L14
F13
B14
J13
E14
M13
V12
U16
H14
U14
V13
J21
R13
A20
G21
A12
K21
B20
C20
D20
E20
F20
G20
H20
L20
T20
F19
J19
C18
J18
D17
N17
D12
G12
N12
T12
K12
V10
V11
W7
T11
U11
W10
PCIE_VSS_1
PCIE_VSS_2
PCIE_VSS_3
PCIE_VSS_4
PCIE_VSS_5
PCIE_VSS_6
PCIE_VSS_7
PCIE_VSS_8
PCIE_VSS_9
PCIE_VSS_10
PCIE_VSS_11
PCIE_VSS_12
PCIE_VSS_13
PCIE_VSS_14
PCIE_VSS_15
PCIE_VSS_16
PCIE_VSS_17
PCIE_VSS_18
PCIE_VSS_19
PCIE_VSS_20
PCIE_VSS_21
PCIE_VSS_22
PCIE_VSS_23
PCIE_VSS_24
PCIE_VSS_25
PCIE_VSS_26
PCIE_VSS_27
PCIE_VSS_28
PCIE_VSS_29
PCIE_VSS_30
PCIE_VSS_31
PCIE_VSS_32
PCIE_VSS_33
PCIE_VSS_34
PCIE_VSS_35
PCIE_VSS_36
PCIE_VSS_37
PCIE_VSS_38
PCIE_VSS_39
PCIE_VSS_40
PCIE_VSS_41
PCIE_VSS_42
PCIE_VSS_43
PCIE_VSS_44
PCIE_VSS_45
PCIE_VSS_46
PCIE_VSS_47
PCIE_VSS_48
PCIE_VSS_49
PCIE_VSS_50
PCIE_VSS_51
PCIE_VSS_52
PCIE_VSS_53
PCIE_VSS_54
PCIE_VSS_55
PCIE_VSS_56
PCIE_VSS_57
PCIE_VSS_58
PCIE_VSS_59
PCIE_VSS_60
PCIE_VSS_61
PCIE_VSS_62
PCIE_VSS_63
PCIE_VSS_64
PCIE_VSS_65
PCIE_VSS_66
PCIE_VSS_67
PCIE_VSS_68
PCIE_VSS_69
PCIE_VSS_70
PCIE_VSS_71
PCIE_VSS_72
PCIE_VSS_73
PCIE_VSS_74
PCIE_VSS_75
PCIE_VSS_76
PCIE_VSS_77
PCIE_VSS_78
PCIE_VSS_79
PCIE_VSS_80
PCIE_VSS_81
PCIE_VSS_82
PCIE_VSS_83
PCIE_VSS_84
PCIE_VSS_85
PCIE_VSS_86
PCIE_VSS_87
PCIE_VSS_88
PCIE_VSS_89
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
Part 4 of 4
PCI-Express GND
GPIO GND
M9
VSS_1
A10
VSS_2
H11
VSS_3
N11
VSS_4
T8
VSS_5
E10
VSS_6
R9
VSS_7
A9
VSS_8
E11
VSS_9
N10
VSS_10
D10
VSS_11
J11
VSS_12
D11
VSS_13
J9
VSS_14
H9
VSS_15
H10
VSS_16
M10
VSS_17
M11
VSS_18
R10
VSS_19
A11
VSS_20
N9
VSS_21
D9
VSS_22
E9
VSS_23
T10
VSS_24
J10
VSS_25
R11
VSS_26
V7
VSS_27
AA9
VSS_28
CORE GND
L5
VSSP_1
D3
VSSP_2
H2
VSSP_3
K2
VSSP_4
P2
VSSP_5
T2
VSSP_6
C6
VSSP_7
B3
VSSP_8
D5
VSSP_9
H5
VSSP_10
K3
VSSP_11
K5
VSSP_12
N5
VSSP_13
U5
VSSP_14
Y2
VSSP_15
P5
VSSP_16
A7
VSSP_17
B7
VSSP_18
D7
VSSP_19
VSSP_20
VSSP_21
VSSP_22
VSSP_23
VSSP_24
VSSP_25
VSSP_26
VSSP_27
VSSP_28
VSSP_29
U7
C7
F8
G8
K8
L8
P8
A3
V6
Y5
AGP GND
Rialto A11
A A
<Variant Name>
5
4
www.vinafix.vn
3
2
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV410 DV VG VIVO 256MB DDR3
Size Docum e n t N u mb er R e v
C
Date: Sheet
105-A41800-00
1
of
23 27Thursday, January 27, 2005
3
5
4
3
2
1
B_GPIO[7..0](21)
B_GPIO[7..0]
Overlap pads to save space
and to prevent assembly of
D D
both resistors.
Layout
High logic voltageGround
Signal
B_GPIO[24..11](21)
C C
B B
REFCLKBYP(21)
A A
B_GPIO[24..11]
STP_AGPB(21)
OPTION STRAPS
B_GPIO0
B_GPIO1
B_GPIO2
B_GPIO3
B_GPIO4
B_GPIO5
B_GPIO6
B_GPIO7
B_GPIO11
B_GPIO12
B_GPIO13
B_GPIO14
B_GPIO15
B_GPIO16
B_GPIO17
B_GPIO18
B_GPIO19
B_GPIO20
B_GPIO21
B_GPIO22
B_GPIO23
B_GPIO24
REFCLKBYP
STP_AGPB
R381 10K
R405 10K
R382 10K
R389 10K
R208 10K
R207 10K
R439 10K DNI
R441 10K
R445 10K DNI
R446 10K
R368 10K DNI
R442 10K
R366 10K DNI
R386 10K
R380 10K DNI
R385 10K
R384 10K DNI
R406 10K
R387 10K
R391 10K
R210 10K DNI
R209 10K
R440 10K DNI
R443 10K
R447 10K DNI
R448 10K
R369 10K DNI
R444 10K
R367 10K DNI
R390 10K
R383 10K DNI
R388 10K
R392 10K DNI
R449 10K
R379 10K DNI
R400 10K
R398 10K DNI
R399 10K
R409 10K DNI
R476 10K
R408 10K DNI
R475 10K
R438 10K DNI
R450 10K
R470 10K DNI
R474 10K
R493 10K
R494 10K
+3.3V_BUS
DNI
DNI
DNI
DNI
+VDDQ_BUS
R477
R478
0R
0R
DNI
DNI
PCIE_AGP_Bridge Shared Straps
STRAPS
GPIO(0)PCIE_PTX_PWRS_ENB
PCIE_PTX_DEE M P H _EN PCI Expr es s transmi tter de-emphasi s enable
PCIE_ICP (1:0)
PCIE_PTX_IEXT GPIO(4)0PCI Expr es s tr a ns mit ter ext ra ouptput current
DEBUG_ACCESS 1 - Set the debug bus muxes to bring out debug signals even if registers are inaccessable
PCIE_PPLL_BW GPIO(6) PCI Express P LL bandwidt h setti ng
PCIE_REVERSE_ALL GPIO(7)00 - Don't r eve rse phy si ca l PCIE lanes
PCI_RETRY_ENb
MULTIFUNC
PCIE_FORCE_
COMPLIANCE
PCIE_LINK_TIMEOUT
_OVERRIDE
MOBILE_EN REFCLKBYP
BUS_PCI_CFG_
RETRY_Enb
GPIO(1)
GPIO(3:2)
GPIO(5)
GPIO(13)
GPIO(24, 14)VGA_MONO_MODE(1:0)
GPIO(15)REFCLK_LINK_CONFIG One of the strap bit to encode the combination of:
GPIO(16)
GPIO(18:17)AGPFBSKEW(1:0)
GPIO(20:19)X1CLK_SKEW(1:0)
GPIO(21)BUSCFG Control BUS type, CLK PLL select
GPIO(22)AGP_ONLY
GPIO(23)
STP_AGPB
DESCRIPTIONPIN
PCI Expr ess tr ansmit ter power -saving enabl e bar
0 - 50% Tx output swing for mobil e applicat ions
1 - Full output swing
0 - de-emphasis disenable
1 - de-emphasis enable
Charge pump current set ting
00 - 5.0uA
01 - 10.0uA
10 - 15.0uA
11 - 20.0uA
0 - no extra current
1 - extr a current i n output st age
0 - Full P LL bandw idth
1 - Reduces PLL bandwidth
1 - Reverse phy si cal PC IE lanes
If no ROM attached, comtrols chip IDi s. If r om attached ident ifies ROM type
00 - No ROM, CHG_ID=0
01 - 512Kb Serial AT25F512 ROM (At mel) or AT24F1024 ROM (Atmel)
10 - 512K Serial M25P05A ROM (ST) or PM25LV512 (PMC)
11 - 1M Serial M25P1 0 A ROM (ST) or PM25LV010 (PMC)
0 - Enable all PCI read/write retry, retry cycle 0x3
1 - Disable PC I read/ wri te retr y
00 - only VGA controller
01 - only MONO controller
10 - neither VGA/MONO controller
11 - both VGA/MONO controller
SEND_LINK_TRA INI NG _IMM EDI AT E LY
MOBILE_EN
AGP_ONLY
....
etc,
For MULTIFUNC, when TE STEN(pin)=0,
0 = 00 - Sin gle function device
1 = 01 - T w o f u nc t ion devi ce. No A GP in ei ther f uncti on
For PCIE_FORCE_COMPLI ANC E, w hen TE STEN(pin)=1,
0 - Normal operation
1 - Force L C into compliance mode
AGP 1xclock feedback phase adjustment wrt refclk(cpuclk)
00 - refcl k sl ig ht ly e arl ier than feedback
01 - refcl k 1 t ap l at er than feedback
10 - refcl k 1 t ap earlier than feedback
11 - refclk 2 t ap ea rl i er than feedback clock
Clock phas e adj u st m ent bet ween x1clk and x2cl k
00 - 0 tap delay
01 - 1 tap delay
10 - 2 tap delay
11 - 3 tap delay
1 - for debugging, shut off VPU so the bridge is working in AGP only mode
1 - Timeout is disabled
when internal MOBILE_EN=0 ST RA P_BU S_PCI_CFG_RETRY_Enb
DEFAULT
1
1
01
0
0
10GPIO(12:11)ROMIDCFG(1: 0)
0
00
0
0
0
00
internal pulldown
00
internal pulldown
0
internal pulldown
00 - normal operation, assume VPU i s worki ng
00 - Timeout is active
0
1
<Variant Name>
5
4
www.vinafix.vn
3
2
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV410 DV VG VIVO 256MB DDR3
Size Docum e n t N u mb er R e v
C
Date: Sheet
105-A41800-00
1
of
24 27Thursday, January 27, 2005
3
5
4
3
2
1
External Power & Controls
C177
100nF
ONLY THROUGH
JU2 PINS 2 AND 3.
+12VEXT+5VEXT
D42
S3AB
C180
100nF
C179
10uF
R1685 0R
R1698 0R
For EMI
21
C178
10uF_25V
D D
Regulator for B_VDDC
Vout = 1.2V
Iout = 1000mA MAX
+3.3V_BUS
+PCIE_PVDD_18
B67
220R
R1850
1.0K
B_VDDC_EN(9)
C C
Rc1
R1852
2K
Rc2
C183
47uF
Rc1
Rc2
RT9173ACL5, TO-252-5, 3A, (2480025000)
Alt. SS6383BCE5, TO-252-5, 3A
MREG33
1
IN
REFEN4GND
RT9173ACL5
C990
1.0uF
3
6
VOUT
TAB
VCNTL
+PCIE_VDD R_12
5
2
+VDDC
DNI
805
B2 0R
Use 5050002800 (Bead, 30R, 1A, 0603)
R1851
C181
1K
402
22uF_6.3V
DNI
B43
42r@100MHz
C182
68uF_6.3V
LOW ESR
+B_VDDC
1.2V
JU2
1
JU2
2
3
4
3.5" Floppy
Power Header
+5VEXT +5V_BUS
Put copper under MREG33 for heat dissipation.
+B_VDDC Rc1 Rc2
3240215100, 2.15K, 1% 3240124100, 1.24K, 1%
1.2V
1.26V
1.31V
3240200100, 2K, 1%
3240187100, 1.87K, 1%
3240124100, 1.24K, 1%
3240124100, 1.24K, 1%
B B
EXTERNAL POWER DETECT
+5V_BUS
23
Q226
R917
562R
R918
1.0K
1
C1132
1nf
MMBT3906
R876 0R
GPIO7(4)
R875 0R
GPIO15(4)
R874 0R
GPIO16(4)
PCIETEST(20)
A A
5
4
www.vinafix.vn
DNI
DNI
3
R1567
0R
R1565
1K
+5VEXT
<Variant Name>
2
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV410 DV VG VIVO 256MB DDR3
Size Docu m en t N u m be r Re v
C
Date: Sheet
105-A41800-00
1
25 27Thursday, January 27, 2005
of
3
5
CRT
SCREWS
ASSY1
SCREW
JACKSCREW
D D
C C
ASSY
ASSY4
SCREW
JACKSCREW
ASSY
ASSY6
SCREW
PAN_HEAD
ASSY8
BRACKET
DVI, TV Out, DVI
ASSY9
BRACKET
VGA, VID OUT, DVI
ASSY10
BRACKET
VGA, DVI
DVI SCREWS
ASSY2
SCREW
JACKSCREW
ASSY
ASSY5
SCREW
JACKSCREW
ASSY
MISC. BOARD PARTS
ASSY3
1.50W_X_0.50H
ASSY
ASSY7
6_X_11
ASSY
MT1
MT_Hole_0.136_in.
620NOPN004
H103
BLANK
LABEL
ANTISTATIC
BAG
4
REF2
PCB
109-A37900-00A
REF3
ATI LOGO
LABEL
ATI_LOGO_LABEL
H104
3
2
1
HEATSINK
NA
Check if need to Add Rialto Hintsink?
B B
A A
<Variant Name>
5
4
www.vinafix.vn
3
2
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV410 DV VG VIVO 256MB DDR3
Size Docum e n t N u mb er R e v
C
Date: Sheet
105-A41800-00
1
of
27 27Thursday, January 27, 2005
3
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