How it Works
MSI
Loading...
MS-95B6
Schematics
18 pgs813.12 Kb0
Schematics
20 pgs487.42 Kb0

MSI MS-95B6 Schematics

Download
Page 1
A B C
Dell Controlled Print
REVISIONS
D
8-24-2004_10:35
1
REMC DP0
225 PBGA
REMC DP1
225 PBGA
40 DATA LINES 10 STROBES
32 DATA LINES 8 STROBES
32 DATA LINES 8 STROBES
40 DATA LINES 10 STROBES
A_SD/DQS[8,3,0,1,2]_[0:7]
B_SD/DQS[3,2,0,1]_[0:7]
A_SD/DQS[6,7,5,4]_[0:7]
B_SD/DQS[8,6,7,5,4]_[0:7]
CARD A
REV
A00
162394 A02 164090 A03
167848
RELEASE TO A-REV FROM X02
Update PWA ref. for MSI Transition
Removed Intersil as vendor for U30, 3F153 -->009TG Removed U95, R622, R624, R619, R620, R625, R621 & R626 for cost saving purposes
Added Intersil back to AVL again (U30) with addition of a 0.1uf cap
TABLE OF CONTENTS
PAGE 1: BLOCK DIAGRAM PAGE 2: PLANAR CONNECTOR
DESCRIPTIONECO DATE
4/15/03137924 5/21/04A01
6/15/04
8/3/04
APPROVED
CLAY PHENNICIE
1
2
A_MA[0:9,11:12], Rx_MA10, Rx_RASN, Rx_CASN, Rx_WEN, A_CSx, Rx_BAx_x, A_CKE
B_MA[0:9,11:12, Rx_MA10, Rx_RASN, Rx_CASN, Rx_WEN, A_CSx, Rx_BAx_x, B_CKE
MEM CARD CONNS
REMC AP
on planar
C_MA[0:9,11:12], Rx_MA10, Rx_RASN, Rx_CASN, Rx_WEN, B_CSx, Rx_BAx_x, C_CKE
DIMM_J6
DIMM_J5
DIMM_J4
DIMM_J3
DIMM_J2
DIMM_J1
PAGE 3: REMC DP0 PAGE 4: REMC DP1
PAGE 5: DIMM J2 (A R0) PAGE 6: DIMM J1 (B R0)
PAGE 7: DIMMS J4 & J6 (A R1 &R2) PAGE 8: A DATA END TERM RES
PAGE 9: DIMMS J3 & J5 (B R1 & R2)
2
PAGE 10: B DATA END TERM RES
REMC DP2
225 PBGA
REMC DP3
D_MA[0:9,11:12], Rx_MA10, Rx_RASN, Rx_CASN, Rx_WEN, B_CSx, Rx_BAx_x, D_CKE
DIMM_J10
DIMM_J9
DIMM_J8
40 DATA LINES 10 STROBES
32 DATA LINES 8 STROBES
32 DATA LINES 8 STROBES
DIMM_J12
C_SD/DQS[8,3,0,1,2]_[0:7]
D_SD/DQS[3,2,0,1]_[0:7]
C_SD/DQS[6,7,5,4]_[0:7]
DIMM_J11
CARD B
DIMM_J7
CIRCUITRY WILL BE SAME AS CARD A BUT C/D BUSSES
CALLED OUT FOR SIMULATION
PAGE 11: CLOCK BUFFER PAGE 12: ADDR & MISC END TERM RES
PAGE 13: ESM3 & RESET & SPARES & WHs PAGE 14: VREF, VTT REGULATION PAGE 15: CMD SERIES TERM RES
PAGE 16: 2.5V REGULATION PAGE 17: CLOCK ROUTING DIAGRAM
STACKUP INFO
3
4
225 PBGA
40 DATA LINES 10 STROBES
MEM CARD CONNS
R: \ Schematic_Projects \ PowerEdge \ Jaguar \ memory _card \ 6_dimm_8Y810 \ A03
I2C ADDRESSES
ASCLK/ASDATA J1 1010 000xb
J2 1010 001xb J3 1010 010xb J4 1010 011xb
J5 1010 100xb J6 1010 101xb
REMC DP0 1110 1Y0xb REMC DP1 1110 1Y1xb CLKBUF0 1101001xb
Y = 0 FOR MEM CARD A Y = 1 FOR MEM CARD B
EACH MEM CARD ON SEPARATE I2C BUS
EXPORT RESTRICTION:
THE EXPORT OF THE INFORMATION, SCHEMATICS AND OTHER TECHNICAL DATA CONTAINED IN THIS DOCUMENT IS CONTROLLED BY THE U.S. GOVERNMENT. THE EXPORT, DEEMED EXPORT OR OTHER TRANSFER OF THIS DATA TO CERTAIN COUNTRIES AND INDIVIDUALS IS RESTRICTED. ANY TRANSFER, EXPORT OR REEXPORT, MUST BE IN COMPLIANCE WITH THE U.S. EXPORT ADMINISTRATION REGULATIONS.
D_SD/DQS[8,6,7,5,4]_[0:7]
JAGUAR DDR 6
DIMM MEMORY CARD
PRODUCTION BUILD = BUILD 1 PROTOTYPE BUILD = BUILD 0
PROPRIETARY NOTE
THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP., EXCEPT AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE LOAN. NEITHER THIS ITEM NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.
Outer layers are 1.5 oz Cu Inner layers are 1.0 oz Cu
TOP - 2.1 mils
4 mils
GROUND1 - 1.4mils
4 mils
INNER 1 - 1.4 mils
15 mils
GROUND2 - 1.4 mils
4 mils
VCC (2.5V) - 1.4 mils
15 mils
INNER 2 - 1.4 mils
4 mils
GROUND3 - 1.4 mils
4 mils
BOTTOM - 2.1 mils
PWA: H6267 (MSI)
PWB: 8Y811
DRAWN
DESIGNED
CHECKED
APPROVED
APPROVED
APPROVED
APPROVED
RELEASED
50 ohm traces are 6.5 mil outer and 4.5 mil inner w/ 2W min spacing
100 ohm diff clks are 5.5 mil w/
9.5 mils separation outer and
4.5 mils w/ 20.5 mil separation inner
SCHEM: 8Y810 ASSY DWG: 8Y809
HASEEB BHUTTA 8/3/04
L MCTEER/ S DUBE/B KRUEGER
12/17/01 8/4/04DANNY KING
A CURRENT ISSUE OF THIS DRAWING MUST INCLUDE A COPY OF THE FOLLOWING ECO'S: ECO
ECO ECO ECO ECO ECO ECO ECO
TITLE
SCHEM,MEM-CRD,6DIMM,PE4600
DWG NO.
COMPUTER CORPORATION AUSTIN,TEXAS
8Y810
SHEET
3
4
A03
1 OF 188/3/2004
DCBA
Page 2
ADD*_1E891_BRKT,LF,MEC,PE4600 ADD*_6G099_BRKT, PLSTC, LF, MEC, REAR, PE4600
ADD*_7G436_ASSY, BRKT, MTG, RT, BK, MEC, PE4600 ADD*_9G342_ASSY, BRKT, MTG, RT, MEC, PE4600
ADD*_9G991_BRKT SCREW ADD*_9G991_BRKT SCREW
B D
CA
8-3-2004_15:33
1
2
2,16 2,16 2,16
15 15
15 15
15 15
15 15
15 15
15 15
15 15
15 15
15 15
16 16
6,9,12
3,4
6,9,12 6,9,12
6,9,12
5,7,12
13
2,3,5,6,8,10,12-14
NC_A2 VCC12_VCC25 VCC12_VCC25 VCC12_VCC25 NC_A6
CSTRB1
3
CSTRB0
3
CMD18 CMD21
CMD23 CMD19
CMD1 CMD7
CMD5 CMD4
CMD8 CMD9
CMD12 CMD10
CMD25 CMD31
CMD29 CMD30
MECC3 MECC1
VCC25_START
B_MA12
UNIQUE_ID
B_MA11
B_MA9
B_MA7
A_MA5 ENV_SDA
VTT_SSTL
Bracket and screw part numbers
P1
VCC25_PWRGD
1
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
A9
10
A10
11
A11
12
A12
13
A13
14
A14
15
A15
16
A16
17
A17
18
A18
19
A19
20
A20
21
A21
22
A22
23
A23
24
A24
25
A25
26
A26
27
A27
28
A28
29
A29
30
A30
31
A31
32
A32
33
A33
34
A34
35
A35
36
A36
37
A37
38
A38
39
A39
40
A40
41
A41
42
A42
43
A43
44
A44
45
A45
46
A46
47
A47
48
A48
49
A49
50
A50
51
A51
52
A52
53
A53
54
A54
55
A55
56
A56
2X165 EDGE
HETERO 1 OF 3
B1 B2 B3 B4 B5 B6 B7 B8
B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56
166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221
VCC12_VCC25 VCC12_VCC25 VCC12_VCC25
NC_B2
CMD17
CMD20 CMD16
CMD22
CMD15 CMD13
CMD14 CMD11
CMD24
CMD28
CMD26 CMD27
NC_B30
MECC2
MSTRB0
MECC0
NC_18 RESET
A_MA12
NC_50 NC_33
A_MA11
NC_31 A_MA9
NC_29 A_MA7
A_MA8 NC_27
MEM_PRES0
NC_15
ENV_SCL
CMD3 CMD6
CMD2 CMD0
2,16 2,16 2,16 15 15
15 15
15 15
15 15
15 15
15 15
15 15
15 15
15
15 15
13
5,7,12
5,7,12
5,7,12
5,7,12
5,7,12
13
13
6,9,12
5,11 5,11
7,9
6,9,12 6,9,12
11,13,14,16
6,9,12
6,9,12 6,9,12
5,7,12
7,9
7,9 7,9
7,9
7,9
5,6 5,6
5,6 7,9
7,9 7,9
15
15
2-7,9,11,13,14,16
B_MA5
ASCLK_3P3V ASDATA_3P3V
R1_MA10
B_MA3
B_MA2 VCC33
B_MA1
B_MA0
B_CKE A_CKE
R2_MA10
R1_WE_0 R2_BA1_0
A_CS_3
R1_BA0_0
R0_BA0_0 A_CS_0
R0_WE_0 R2_RAS_0
A_CS_4 A_CS_5
NC_200
MECC7 MECC6
NC_25
VCC25
57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98
99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118
A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84 A85 A86 A87 A88 A89 A90 A91 A92 A93 A94 A95 A96 A97 A98 A99 A100 A101 A102 A103 A104 A105 A106 A107 A108 A109 A110 A111 A112 A113 A114 A115 A116 A117 A118
P1
B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82 B83 B84 B85 B86 B87 B88 B89 B90 B91 B92 B93 B94 B95 B96 B97 B98
B99 B100 B101 B102 B103 B104 B105 B106 B107 B108 B109 B110 B111 B112 B113 B114 B115 B116 B117 B118
222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283
NC_P1_236
R0_MA10
R1_BA1_0
R0_BA1_0 R1_CAS_0
A_CS_2
R1_RAS_0 A_CS_1
R0_RAS_0 R0_CAS_0
R2_BA0_0
R2_WE_0
R2_CAS_0
NC_357
MSTRB1
NC_3001
NC_800
B_MA8 A_MA6
NC_22 NC_19
B_MA6
A_MA4
B_MA4 A_MA3
A_MA2
A_MA1 NC_24
NC_21 A_MA0
NC_20
MECC4 MECC5
RCMD1 RCMD2
RCMD3 RCMD0
NC_28
NC_17 NC_37
6,9,12
5,7,12
6,9,12
5,7,12 6,9,12
5,7,12 5,7,12
5,7,12
5,7,12
5,6 7,9
5,6 7,9
7,9 7,9
5,6 5,6
5,6 7,9
7,9 7,9
15 15
15 3,4,12
3,4,12 3,4,12
3,4,12
P1
119
A119
120
A120
121
A121
122
A122
123
A123
124
A124
125
A125
126
A126
127
A127
128
A128
129
A129
130
A130
131
A131
132
A132
133
A133
134
A134
135
A135
136
A136
137
A137
138
A138
139
A139
140
A140
141
A141
142
A142
143
A143
144
A144
145
A145
146
A146
147
A147
148
A148
149
A149
150
A150
151
A151
152
A152
153
A153
154
A154
155
A155
156
A156
157
A157
158
A158
159
A159
160
A160
161
A161
162
A162
163
A163
164
A164
165
A165
2X165 EDGE
HETERO 3 OF 3
3,4
15
15 15
15 15
15 15
15 15
15 15
15 15
15 15
15
2,14
NC_13
PLLRST
CSTRB2
4
CSTRB3
4
CMD38 CMD39
CMD32 CMD36
CMD33 CMD37
CMD46 CMD43
CMD48 CMD51
CMD55 CMD52
CMD63 CMD61
CMD62 CMD60
NC_A160 VCC12_VTT
NC_A163 NC_B163
MEM_PRES1 PULLED UP ON PLANAR
B119 B120 B121 B122 B123 B124 B125 B126 B127 B128 B129 B130 B131 B132 B133 B134 B135 B136 B137 B138 B139 B140 B141 B142 B143 B144 B145 B146 B147 B148 B149 B150 B151 B152 B153 B154 B155 B156 B157 B158 B159 B160 B161 B162 B163 B164 B165
284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330
NC_12 NC_11
MEM_PRES1
NC_10 NC_14
NC_ISOLATE
VTT_START
CLKIN0_N
CLKIN0_P
NC_B133
VTT_PWRGD
CMD45 CMD34
CMD44 CMD35
CMD47
CMD42
CMD41 CMD40
CMD49
CMD50
CMD54 CMD53
CMD56 CMD57
CMD59 CMD58
VCC12_VTT
SDOE
3,4,12
13
14
11 11
14
15 15
15 15
15 15
15 15
15 15
15 15
15 15
15 15
2,14
1
2
3
MEM_PRES0 GROUNDED ON PLANAR
VCC25
2-7,9,11,13,14,16
VCC25
2-7,9,11,13,14,16
2X165 EDGE
HETERO 2 OF 3
3
NC PINS CONNECTED TO VIAS (conn pin #):
100, 112, 120, 263, 278, 281, 282, 289, 290, 293
1 2
1 2
0.1uF 16V
1 2
0.1uF 16V
1 2
0.1uF 16V
2
1
1 2
0.1uF 16V
2
1
+80%-20%
.22uF 16V
1 2
0.1uF 16V
+80%-20%
.22uF 16V
0.1uF 16V
2
1
.22uF 16V
1 2
0.1uF 16V
2
1
+80%-20%
2
1
+80%-20%
.22uF 16V
2
1
+80%-20%
.22uF 16V
2
1
+80%-20%
.22uF 16V
2
1
+80%-20%
.22uF 16V
1
+80%-20%
.22uF 16V
2
.22uF 16V
2
1
+80%-20%
2
1
+80%-20%
.22uF 16V
SUB*_78020
1
+80%-20%
.22uF 16V
2
.22uF 16V
1 2
1
+80%-20%
4 4
.01UF
50V-20%
Substitution for part number consolidation
2
+80%-20%
.22uF 16V
.01UF
1 2
50V-20%
SUB*_78020
2
1
2
1
+80%-20%
.22uF 16V
2
1
+80%-20%
.22uF 16V
+80%-20%
.22uF 16V
2
1
2
1
+80%-20%
.22uF 16V
VTT_SSTL
1
+80%-20%
.22uF 16V
2
.22uF 16V
2,3,5,6,8,10,12-14
+80%-20%
SUB*_78020
1 2
.01UF
SUB*_78020
1 2
50V-20%
Substitution for part number consolidation
SUB*_78020
1 2
.01UF
50V-20%
SUB*_78020
SUB*_78020
.01UF
1 2
1 2
50V-20%
.01UF
50V-20%
.01UF
1 2
SUB*_78020
50V-20%
.01UF
50V-20%
.01UF
1 2
SUB*_78020
50V-20%
SUB*_78020
.01UF
1 2
1 2
50V-20%
SUB*_78020
.01UF
50V-20%
VCC25
2-7,9,11,13,14,16
PLANAR CONNECTOR
COMPUTER CORPORATION
AUSTIN,TEXAS
TITLE
CAPS ARE FOR DECOUPLING/BYPASS THROUGHOUT BRD
A B
PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.
DWG NO.
DC
SCHEM,MEM-CRD,6DIMM,PE4600
8Y810
SHEET
8/3/2004
A03
2 OF 18
Page 3
B D
CA
8-3-2004_15:33
R_CSTRB1
3
R_CSTRB0
3
1
12 OHM 5%
12 OHM 5%
RN406
1 8
12 OHM-5%
RN406
2 7
12 OHM-5%
RN406
3 6
12 OHM-5%
RN406
4 5
12 OHM-5%
RN338
1 8
12 OHM-5%
RN338
4 5
12 OHM-5%
RN338
3 6
12 OHM-5%
RN338
2 7
12 OHM-5%
RN408
4 5
12 OHM-5%
RN408
3 6
12 OHM-5%
RN408
2 7
12 OHM-5%
RN408
1 8
12 OHM-5%
RN409
4 5
12 OHM-5%
RN409
3 6
12 OHM-5%
RN409
2 7
12 OHM-5%
RN409
1 8
12 OHM-5%
1 2
150-5%
1 2
150-5%
A_SD0_7
21
A_SD0_3
21
B_SD0_4
B_SD0_0
B_SD0_5
NC_RN338_8
B_SD1_4
B_SD1_1
B_SD1_0
A_SD8_2
A_SD8_6
A_SD8_3
A_SD8_7
A_SD8_0
A_SD8_1
A_DQS8_0
A_DQS8_1
UNIQUE_ID
NC_RN_8
2
3
R_A_SD0_7
3
R_A_SD0_3
3
NC_RN_1
R_B_SD0_4
3
R_B_SD0_0
3
R_B_SD0_5
3
NC_RN338_1
R_B_SD1_4
3
R_B_SD1_1
3
R_B_SD1_0
3
R_A_SD8_2
3
R_A_SD8_6
3
R_A_SD8_3
3
R_A_SD8_7
3
R_A_SD8_0
3
R_A_SD8_1
3
R_A_DQS8_0
3
R_A_DQS8_1
3
REMC0_ID0
3
REMC0_ID1
3
Strapping option: ~SDOE=0 (DP Mode)
2-4,12
R_A_SD1_1
3
R_A_DQS1_0
3
R_A_SD1_4
3
R_A_SD1_0
3
R_A_SD1_7
3
R_A_SD1_6
3
4 4
R_A_DQS1_1
3
R_A_SD1_5
3
RN180
2 7
12 OHM-5%
RN180
1 8
12 OHM-5%
RN180
3 6
12 OHM-5%
RN180
4 5
12 OHM-5%
RN181
1 8
12 OHM-5%
RN181
2 7
12 OHM-5%
RN181
3 6
12 OHM-5%
RN181
4 5
12 OHM-5%
A_SD1_1
A_DQS1_0
A_SD1_4
A_SD1_0
A_SD1_7
A_SD1_6
A_DQS1_1
A_SD1_5
15
15
21
21
CSTRB1
CSTRB0
2-7,9,11,13,14,16
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
VCC25
2,4
1 2
2
2
VCC25
2-7,9,11,13,14,16
NP*
1K-5%
3
3
3
3
3
3
1K-5%
1 2
R_B_SD1_5
3
3
R_B_SD1_6
R_B_SD1_7
R_B_SD1_2
R_B_SD1_3
R_B_SD2_4
1 2
249 Ohm-1%
R_B_DQS1_0
R_B_DQS1_1
1K-5%
1 2
PU_ISOLATE_DP0
R_CSTRB0
3
R_CSTRB0
3
R_CSTRB1
3
R_CSTRB1
3
15
2,4,12 2,4,12 2,4,12 2,4,12
R_A_DQS3_1
3
R_A_DQS3_0
3
R_B_DQS2_1
3
R_B_DQS2_0
3
R_A_DQS8_1
3
R_A_DQS8_0
3
R_B_DQS3_1
3
R_B_DQS3_0
3
R_A_DQS0_1
3
R_A_DQS0_0
3
R_B_DQS0_1
3
R_B_DQS0_0
3
R_A_DQS1_1
3
R_A_DQS1_0
3
R_B_DQS1_1
3
R_B_DQS1_0
3
R_A_DQS2_1
3
R_A_DQS2_0
3
R_MSTRB0
COMP0_DP0
REMC0_ID1
3
REMC0_ID0
3
NC_DP0_B14 NC_DP0_C13 NC_DP0_B15 NC_DP0_C14
R_MECC3
15
R_MECC2
15
R_MECC1
15
R_MECC0
15
R_CMD15
15
R_CMD14
15
R_CMD13
15
R_CMD12
15
R_CMD11
15
R_CMD10
15
R_CMD9
15
R_CMD8
15
R_CMD7
15
R_CMD6
15
R_CMD5
15
R_CMD4
15
R_CMD3
15
R_CMD2
15
R_CMD1
15
R_CMD0
15
R_CMD23
15
R_CMD22
15
R_CMD21
15
R_CMD20
15
R_CMD19
15
R_CMD18
15
R_CMD17
15
R_CMD16
15
R_CMD31
15
R_CMD30
15
R_CMD29
15
R_CMD28
15
R_CMD27
15
R_CMD26
15
R_CMD25
15
R_CMD24
15
RCMD3 RCMD2 RCMD1 RCMD0
2-4,12
RN182
2 7
12 OHM-5%
RN182
1 8
12 OHM-5%
RN182
3 6
12 OHM-5%
RN182
4 5
12 OHM-5%
RN183
1 8
12 OHM-5%
RN183
2 7
12 OHM-5%
RN183
3 6
12 OHM-5%
RN183
4 5
12 OHM-5%
B_SD1_5
B_DQS1_0
B_DQS1_1
B_SD1_6
B_SD1_7
B_SD1_2
B_SD1_3
B_SD2_4
L12
D13
B14 C13 B15 C14
N15
R6 G3 D9
U24
CSTRB1_1/MA16 CSTRB1_0/NC CSTRB0_1/MA15 CSTRB0_0/CKE
MSTRB/MEMPAR
C3
COMP0
A2
RSVD2/ECS1_2
B3
RSVD1/ECS1_1
CMD9_3/D_WE1 CMD9_2/C_WE1 CMD9_1/B_WE1 CMD9_0/A_WE1
E12
CMD8_3/D_RAS1
D14
CMD8_2/C_RAS1
F11
CMD8_1/B_RAS1
D15
CMD8_0/A_RAS1
K11
CMD7_3/D_CAS1
L14
CMD7_2/C_CAS1
L13
CMD7_1/B_CAS1
M15
CMD7_0/A_CAS1
M14
CMD6_3/D_BA1_0 CMD6_2/C_BA1_0
M13
CMD6_1/B_BA1_0
L11
CMD6_0/A_BA1_0
R7
CMD5_3/B_CS7
P7
CMD5_2/A_CS7
N7
CMD5_1/B_CS6
M7
CMD5_0/A_CS6
N6
CMD4_3/B_CS5
M6
CMD4_2/A_CS5
R5
CMD4_1/B_CS4
L6
CMD4_0/A_CS4
H2
CMD3_3/B_CS3
H3
CMD3_2/A_CS3
G1
CMD3_1/B_CS2
G2
CMD3_0/A_CS2
G4
CMD2_3/B_CS1
F1
CMD2_2/A_CS1
F2
CMD2_1/B_CS0
F3
CMD2_0/A_CS0
C8
CMD1_3/D_BA0_0
A9
CMD1_2/C_BA0_0
B9
CMD1_1/B_BA0_0
C9
CMD1_0/A_BA0_0
A10
CMD0_3/D_CKE0
B10
CMD0_2/C_CKE0
C10
CMD0_1/B_CKE0
D10
CMD0_0/A_CKE0
C4
RCMD3/ECS1_0
B4
RCMD2/ECS0_2
D5
RCMD1/ECS0_1
A3
RCMD0/ECS0_0
F15
DQS8_1/WE
G11
DQS8_0/RAS
J14
DQS7_1/CAS
J13
DQS7_0/MA14
R13
DQS6_1/MA13
M11
DQS6_0/MA2
N9
DQS5_1/MA11
R9
DQS5_0/MA10
M3
DQS4_1/MA9
N1
DQS4_0/MA8
K1
DQS3_1/MA7
J4
DQS3_0/MA6
E4
DQS2_1/MA5
D2
DQS2_0/MA4
A6
DQS1_1/MA3
D7
DQS1_0/MA12
A13
DQS0_1/MA1
C12
DQS0_0/MA0
B2
ISOLATE
A4
SDOE/ALERT
REMC Version 1.0
HETERO 1 OF 2
SD8_7/D_WE SD8_6/C_WE SD8_5/B_WE
SD8_4/A_WE SD8_3/D_RAS SD8_2/C_RAS SD8_1/B_RAS SD8_0/A_RAS
SD7_7/D_CAS SD7_6/C_CAS SD7_5/B_CAS SD7_4/A_CAS
SD7_3/D_MA12 SD7_2/C_MA12 SD7_1/B_MA12 SD7_0/A_MA12
SD6_7/D_BA1_1 SD6_6/C_BA1_1 SD6_5/B_BA1_1 SD6_4/A_BA1_1
SD6_3/D_MA2 SD6_2/C_MA2 SD6_1/B_MA2 SD6_0/A_MA2
SD5_7/D_MA11 SD5_6/C_MA11 SD5_5/B_MA11 SD5_4/A_MA11 SD5_3/D_MA10 SD5_2/C_MA10 SD5_1/B_MA10 SD5_0/A_MA10
SD4_7/D_MA9 SD4_6/C_MA9 SD4_5/B_MA9 SD4_4/A_MA9 SD4_3/D_MA8 SD4_2/C_MA8 SD4_1/B_MA8 SD4_0/A_MA8
SD3_7/D_MA7 SD3_6/C_MA7 SD3_5/B_MA7 SD3_4/A_MA7 SD3_3/D_MA6 SD3_2/C_MA6 SD3_1/B_MA6 SD3_0/A_MA6
SD2_7/D_MA5 SD2_6/C_MA5 SD2_5/B_MA5 SD2_4/A_MA5 SD2_3/D_MA4 SD2_2/C_MA4 SD2_1/B_MA4 SD2_0/A_MA4
SD1_7/D_MA3 SD1_6/C_MA3 SD1_5/B_MA3 SD1_4/A_MA3
SD1_3/D_BA0_1 SD1_2/C_BA0_1 SD1_1/B_BA0_1 SD1_0/A_BA0_1
SD0_7/D_MA1 SD0_6/C_MA1 SD0_5/B_MA1 SD0_4/A_MA1 SD0_3/D_MA0 SD0_2/C_MA0 SD0_1/B_MA0 SD0_0/A_MA0
E14 E15 F13 F14 G12 G13 G15 H11
H15 H14 H13 J15 J12 K15 K14 K13
N13 R14 P13 N12 P12 R12 N11 M10
N10 P10 R10 M9 P9 M8 R8 P8
P2 N3 P1 N2 L4 M2 K5 M1
L2 L1 K3 K2 J3 J1 J2 H5
F5 E2 E3 D1 C1 D3 C2 B1
B5 A5 C6 B6 C7 A7 B7 D8
C11 A12 D11 B12 E11 A14 B13 D12
R_A_SD3_6 R_A_SD3_7 R_A_SD3_5 R_A_SD3_4 R_A_SD3_3 R_A_SD3_2 R_A_SD3_0 R_A_SD3_1
R_B_SD2_7 R_B_SD2_5 R_B_SD2_4 R_B_SD2_6 R_B_SD2_0 R_B_SD2_2 R_B_SD2_3 R_B_SD2_1
R_A_SD8_5 R_A_SD8_6 R_A_SD8_7 R_A_SD8_4 R_A_SD8_2 R_A_SD8_3 R_A_SD8_1 R_A_SD8_0
R_B_SD3_5 R_B_SD3_6 R_B_SD3_7 R_B_SD3_4 R_B_SD3_2 R_B_SD3_1 R_B_SD3_3 R_B_SD3_0
R_A_SD0_7 R_A_SD0_6 R_A_SD0_5 R_A_SD0_4 R_A_SD0_3 R_A_SD0_2 R_A_SD0_1 R_A_SD0_0
R_B_SD0_7 R_B_SD0_6 R_B_SD0_5 R_B_SD0_4 R_B_SD0_3 R_B_SD0_2 R_B_SD0_1 R_B_SD0_0
R_A_SD1_7 R_A_SD1_6 R_A_SD1_5 R_A_SD1_4 R_A_SD1_3 R_A_SD1_2 R_A_SD1_1 R_A_SD1_0
R_B_SD1_7 R_B_SD1_6 R_B_SD1_5 R_B_SD1_4 R_B_SD1_3 R_B_SD1_2 R_B_SD1_1 R_B_SD1_0
R_A_SD2_7 R_A_SD2_5 R_A_SD2_6 R_A_SD2_4 R_A_SD2_3 R_A_SD2_2 R_A_SD2_1 R_A_SD2_0
SUB*_8Y113
This is REMC version 3.0
Jaguar 2.0 Change: Changed REMC fom rev 2.0 to 3.0 (with deglitching circuit)
RN184
2 7
12 OHM-5%
RN184
1 8
12 OHM-5%
RN184
3 6
12 OHM-5%
RN184
4 5
12 OHM-5%
RN185
1 8
12 OHM-5%
RN185
2 7
12 OHM-5%
RN185
3 6
12 OHM-5%
RN185
4 5
12 OHM-5%
A_SD2_4
A_SD2_0
A_SD1_3
A_SD1_2
A_DQS2_1
A_DQS2_0
A_SD2_5
A_SD2_1
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
R_A_SD2_4
3
R_A_SD2_0
3
R_A_SD1_3
3
R_A_SD1_2
3
R_A_DQS2_1
3
R_A_DQS2_0
3
R_A_SD2_5
3
R_A_SD2_1
3
3 3 3 3 3 3 3 3
3 3 3 3 3 3 3 3
3 3 3 3 3 3 3 3
3 4 4 3 4 3 4 3
3 3 3 3 3 3 3 3
3 3 3 3 3 3 3 3
3 3 3 3 3 3 3 3
3 3 3 3 3 3 3 3
3 3 3 3 3 3 3 3
R_A_SD3_2
3
R_A_SD3_6
3
R_A_DQS3_1
3
R_A_DQS3_0
3
R_A_SD8_5
3
R_A_SD8_4
3
R_A_SD3_7
3
R_A_SD3_3
3
R_B_SD3_5
3
R_B_SD3_1
3
R_B_DQS3_0
3
R_B_DQS3_1
3
R_B_SD2_3
3
NC_RN171_2
R_B_SD3_0
3
R_B_SD3_4
3
R_A_SD3_5
3
R_A_SD3_1
3
R_A_SD3_4
3
R_A_SD3_0
3
R_A_SD2_3
3
R_A_SD2_7
3
R_A_SD2_6
3
R_A_SD2_2
3
R_B_SD2_2
3
R_B_DQS2_1
3
R_B_SD2_6
3
R_B_SD2_7
3
R_B_SD2_0
3
R_B_SD2_1
3
R_B_SD2_5
3
R_B_DQS2_0
3
R_A_SD0_2
3
R_A_SD0_6
3
R_A_DQS0_0
3
R_A_DQS0_1
3
R_A_SD0_1
3
R_A_SD0_5
3
R_A_SD0_0
3
R_A_SD0_4
3
R_B_SD0_1
3
NC_RN178_1 NC_RN178_8
R_B_DQS0_0
3
R_B_DQS0_1
3
R_B_SD0_2
3
R_B_SD0_6
3
R_B_SD0_3
3
R_B_SD0_7
3
RN168
1 8
12 OHM-5%
RN168
2 7
12 OHM-5%
RN168
3 6
12 OHM-5%
RN168
4 5
12 OHM-5%
RN169
1 8
12 OHM-5%
RN169
2 7
12 OHM-5%
RN169
3 6
12 OHM-5%
RN169
4 5
12 OHM-5%
RN170
2 7
12 OHM-5%
RN170
1 8
12 OHM-5%
RN170
3 6
12 OHM-5%
RN170
4 5
12 OHM-5%
RN171
1 8
12 OHM-5%
RN171
2 7
12 OHM-5%
RN171
3 6
12 OHM-5%
RN171
4 5
12 OHM-5%
RN172
2 7
12 OHM-5%
RN172
1 8
12 OHM-5%
RN172
3 6
12 OHM-5%
RN172
4 5
12 OHM-5%
RN173
1 8
12 OHM-5%
RN173
2 7
12 OHM-5%
RN173
3 6
12 OHM-5%
RN173
4 5
12 OHM-5%
RN174
2 7
12 OHM-5%
RN174
1 8
12 OHM-5%
RN174
3 6
12 OHM-5%
RN174
4 5
12 OHM-5%
RN175
1 8
12 OHM-5%
RN175
2 7
12 OHM-5%
RN175
3 6
12 OHM-5%
RN175
4 5
12 OHM-5%
RN176
2 7
12 OHM-5%
RN176
1 8
12 OHM-5%
RN176
3 6
12 OHM-5%
RN176
4 5
12 OHM-5%
RN177
1 8
12 OHM-5%
RN177
2 7
12 OHM-5%
RN177
3 6
12 OHM-5%
RN177
4 5
12 OHM-5%
RN178
2 7
12 OHM-5%
RN178
1 8
12 OHM-5%
RN178
3 6
12 OHM-5%
RN178
4 5
12 OHM-5%
RN179
1 8
12 OHM-5%
RN179
2 7
12 OHM-5%
RN179
3 6
12 OHM-5%
RN179
4 5
12 OHM-5%
A_SD3_2
A_SD3_6
A_DQS3_1
A_DQS3_0
A_SD8_5
A_SD8_4
A_SD3_7
A_SD3_3
B_SD3_5
B_SD3_1
B_DQS3_0
B_DQS3_1
B_SD2_3
NC_RN171_7
B_SD3_0
B_SD3_4
A_SD3_5
A_SD3_1
A_SD3_4
A_SD3_0
A_SD2_3
A_SD2_7
A_SD2_6
A_SD2_2
B_SD2_2
B_DQS2_1
B_SD2_6
B_SD2_7
B_SD2_0
B_SD2_1
B_SD2_5
B_DQS2_0
A_SD0_2
A_SD0_6
A_DQS0_0
A_DQS0_1
A_SD0_1
A_SD0_5
A_SD0_0
A_SD0_4
B_SD0_1
B_DQS0_0
B_DQS0_1
B_SD0_2
B_SD0_6
B_SD0_3
B_SD0_7
VCC25
2-7,9,11,13,14,16
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
3,14
6,9,10
6,9,10
6,9,10
6,9,10
Substitution for p/n consolidation
2-7,9,11,13,14,16
SUB*_78020
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.
1K-5%
1 2
3,14
SSTLREF_R1
VCC25
TESTMODE_DP0
4,13
R_ASDATA_DP0
3
R_ASCLK_DP0
3
SSTLREF_R1
2-7,9,11,13,14,16
C79
1 2
10V-20%
+
1
2
CLKDP0_N
11
CLKDP0_P
11
PLLRST
2,4
SRESET
VCC25
21
21
C80
.01UF
SUB*_78020
1 2
50V-20%
10V-20%
+
1uF
10V-10%
1uF
10V-10%
SUB*_78020
.01UF
50V-20%
1
2
1 2
1 2
C81
1 2
10V-20%
+
100uF
1
M12
R15 P15
P14 P11
L15
K10
J11 J10
H12
G10
F10
E13
A15 A11
.22uF 16V
.22uF 16V
.01UF
2
R2
P3
N5
PLLRST
TESTMODE
A1
RESET
L5
SDA
N4
SCK
VREF_R15 VREF_P15
D4
VREF_D4
C5
VREF_C5
VDD_P14 VDD_P11
P6
VDD_P6
M4
VDD_M4 VDD_L15
L9
VDD_L9
L7
VDD_L7 VDD_K10
K9
VDD_K9
K7
VDD_K7
K6
VDD_K6
K4
VDD_K4 VDD_J11 VDD_J10
J6
VDD_J6 VDD_H12
H4
VDD_H4
H1
VDD_H1 VDD_G10
G6
VDD_G6
VDD_F10
F9
VDD_F9
F7
VDD_F7
F6
VDD_F6
F4
VDD_F4 VDD_E13
E9
VDD_E9
E7
VDD_E7
D6
VDD_D6
B8
VDD_B8 VDD_A15 VDD_A11
1 2
+80%-20%
1 2
+80%-20%
C82
1 2
50V-20%
SUB*_78020
10V-20%
+
U24
GND_R11
GND_N14
GND_L10
GND_K12
GND_H10
GND_G14
GND_F12
GND_E10
GND_C15 GND_B11
REMC Version 1.0
HETERO 2 OF 2
SUB*_8Y113
This is REMC version 3.0
+80%-20%
.22uF 16V
+80%-20%
.22uF 16V
C2
1 2
0.1uF 16V
2-7,9,11,13,14,16
0.1uF 16V
1 2
VCC25
1
2
.01UF
50V-20%
C1
1 2
GND_R1 GND_P5
GND_N8
GND_L8 GND_L3
GND_K8 GND_J9 GND_J8 GND_J7 GND_J5
GND_H9 GND_H8 GND_H7 GND_H6
GND_G9
GND_G8 GND_G7 GND_G5
GND_F8
GND_E8 GND_E6 GND_E5 GND_E1
GND_A8
C4
1 2
.22uF 16V
1 2
21
L14
47uH 135MA
R3 P4 M5 R4
R11 R1 P5 N14 N8 L10 L8 L3 K12 K8 J9 J8 J7 J5 H10 H9 H8 H7 H6 G14 G9
22uF 10V
12
BE USED ON NEW DESIGNS.
THIS PART IS NOT TO
DPLL TEST MODE: TESTMODE = 0 AND
RCMD1 = 1 INPUTS IN DPLL TESTMODE:
R_CMD[32:53] OUTPUTS IN DPLL AND XOR TESTMODE
SDA, SCK, ~SDOE/~ALERT XOR TREE MODE: TESTMODE = 0, RCMD1 = 0,
AND ECS1[2:1] = 2'b00 MDLL TEST MODE:
G8 G7 G5 F12 F8 E10 E8 E6 E5 E1 C15 B11 A8
4-7,9,13
FSTEDG_ASCLK_2P5V
4,5
TESTMODE = 0, RCMD1 = 0, AND ECS1[2:1] = 2'b01
SDLL TREE MODE:
TESTMODE = 0, RCMD1 = 0,
AND ECS1[2:1] = 2'b10
NP*
NP*
1 2
1 2
ASDATA_2P5V
DISCONNECT REMC I2C BUS
DUE TO NO POST PROBLEM
Substitution for p/n consolidation
VCC25
21
C37
SUB*_79015
SUB*_79015
.001UF
50V-20%
2,5,6,8,10,12-14
REMC DATA PATH 0
TITLE
DWG NO.
0.1uF 16V
+80%-20%
1 2
2-7,9,11,13,14,16
VTT_SSTL
+80%-20%
.22uF 16V
1 2
0.1uF 16V
21
C38
1 2
0.1uF 16V
VCC25
2-7,9,11,13,14,16
VCC25
SUB*_79015
8.2K-5%
1 2
2-7,9,11,13,14,16
.001UF
8.2K-5%
1 2
C39
50V-20%
VCC25
R_ASDATA_DP0
R_ASCLK_DP0
SUB*_79015
21
.001UF
50V-20%
21
C40
SUB*_79015
2-7,9,11,13,14,16
21
C41
.001UF
50V-20%
COMPUTER CORPORATION
AUSTIN,TEXAS
SCHEM,MEM-CRD,6DIMM,PE4600
8Y810
SHEET
8/3/2004
3
3
SUB*_79015
21
C42
.001UF
50V-20%
3 OF 18
.001UF
50V-20%
A03
1
2
3
A B
DC
Page 4
B D
CA
8-3-2004_15:33
U25
L12
R6 G3 D9
D13
B14 C13 B15 C14
N15
CSTRB1_1/MA16 CSTRB1_0/NC CSTRB0_1/MA15 CSTRB0_0/CKE
MSTRB/MEMPAR
C3
COMP0
A2
RSVD2/ECS1_2
B3
RSVD1/ECS1_1
CMD9_3/D_WE1 CMD9_2/C_WE1 CMD9_1/B_WE1 CMD9_0/A_WE1
E12
CMD8_3/D_RAS1
D14
CMD8_2/C_RAS1
F11
CMD8_1/B_RAS1
D15
CMD8_0/A_RAS1
K11
CMD7_3/D_CAS1
L14
CMD7_2/C_CAS1
L13
CMD7_1/B_CAS1
M15
CMD7_0/A_CAS1
M14
CMD6_3/D_BA1_0 CMD6_2/C_BA1_0
M13
CMD6_1/B_BA1_0
L11
CMD6_0/A_BA1_0
R7
CMD5_3/B_CS7
P7
CMD5_2/A_CS7
N7
CMD5_1/B_CS6
M7
CMD5_0/A_CS6
N6
CMD4_3/B_CS5
M6
CMD4_2/A_CS5
R5
CMD4_1/B_CS4
L6
CMD4_0/A_CS4
H2
CMD3_3/B_CS3
H3
CMD3_2/A_CS3
G1
CMD3_1/B_CS2
G2
CMD3_0/A_CS2
G4
CMD2_3/B_CS1
F1
CMD2_2/A_CS1
F2
CMD2_1/B_CS0
F3
CMD2_0/A_CS0
C8
CMD1_3/D_BA0_0
A9
CMD1_2/C_BA0_0
B9
CMD1_1/B_BA0_0
C9
CMD1_0/A_BA0_0
A10
CMD0_3/D_CKE0
B10
CMD0_2/C_CKE0
C10
CMD0_1/B_CKE0
D10
CMD0_0/A_CKE0
C4
RCMD3/ECS1_0
B4
RCMD2/ECS0_2
D5
RCMD1/ECS0_1
A3
RCMD0/ECS0_0
F15
DQS8_1/WE
G11
DQS8_0/RAS
J14
DQS7_1/CAS
J13
DQS7_0/MA14
R13
DQS6_1/MA13
M11
DQS6_0/MA2
N9
DQS5_1/MA11
R9
DQS5_0/MA10
M3
DQS4_1/MA9
N1
DQS4_0/MA8
K1
DQS3_1/MA7
J4
DQS3_0/MA6
E4
DQS2_1/MA5
D2
DQS2_0/MA4
A6
DQS1_1/MA3
D7
DQS1_0/MA12
A13
DQS0_1/MA1
C12
DQS0_0/MA0
B2
ISOLATE
A4
SDOE/ALERT
REMC Version 1.0
HETERO 1 OF 2
SD8_7/D_WE SD8_6/C_WE SD8_5/B_WE
SD8_4/A_WE SD8_3/D_RAS SD8_2/C_RAS SD8_1/B_RAS SD8_0/A_RAS
SD7_7/D_CAS SD7_6/C_CAS SD7_5/B_CAS SD7_4/A_CAS
SD7_3/D_MA12 SD7_2/C_MA12 SD7_1/B_MA12 SD7_0/A_MA12
SD6_7/D_BA1_1 SD6_6/C_BA1_1 SD6_5/B_BA1_1 SD6_4/A_BA1_1
SD6_3/D_MA2 SD6_2/C_MA2 SD6_1/B_MA2 SD6_0/A_MA2
SD5_7/D_MA11 SD5_6/C_MA11 SD5_5/B_MA11 SD5_4/A_MA11 SD5_3/D_MA10 SD5_2/C_MA10 SD5_1/B_MA10 SD5_0/A_MA10
SD4_7/D_MA9 SD4_6/C_MA9 SD4_5/B_MA9 SD4_4/A_MA9 SD4_3/D_MA8 SD4_2/C_MA8 SD4_1/B_MA8 SD4_0/A_MA8
SD3_7/D_MA7 SD3_6/C_MA7 SD3_5/B_MA7 SD3_4/A_MA7 SD3_3/D_MA6 SD3_2/C_MA6 SD3_1/B_MA6 SD3_0/A_MA6
SD2_7/D_MA5 SD2_6/C_MA5 SD2_5/B_MA5 SD2_4/A_MA5 SD2_3/D_MA4 SD2_2/C_MA4 SD2_1/B_MA4 SD2_0/A_MA4
SD1_7/D_MA3 SD1_6/C_MA3 SD1_5/B_MA3 SD1_4/A_MA3
SD1_3/D_BA0_1 SD1_2/C_BA0_1 SD1_1/B_BA0_1 SD1_0/A_BA0_1
SD0_7/D_MA1 SD0_6/C_MA1 SD0_5/B_MA1 SD0_4/A_MA1 SD0_3/D_MA0 SD0_2/C_MA0 SD0_1/B_MA0 SD0_0/A_MA0
E14 E15 F13 F14 G12 G13 G15 H11
H15 H14 H13 J15 J12 K15 K14 K13
N13 R14 P13 N12 P12 R12 N11 M10
N10 P10 R10 M9 P9 M8 R8 P8
P2 N3 P1 N2 L4 M2 K5 M1
L2 L1 K3 K2 J3 J1 J2 H5
F5 E2 E3 D1 C1 D3 C2 B1
B5 A5 C6 B6 C7 A7 B7 D8
C11 A12 D11 B12 E11 A14 B13 D12
R_B_SD4_6 R_B_SD4_7 R_B_SD4_5 R_B_SD4_4 R_B_SD4_1 R_B_SD4_2 R_B_SD4_3 R_B_SD4_0
R_B_SD5_4 R_B_SD5_6 R_B_SD5_7 R_B_SD5_5 R_B_SD5_3 R_B_SD5_2 R_B_SD5_1 R_B_SD5_0
R_A_SD6_5 R_A_SD6_7 R_A_SD6_6 R_A_SD6_4 R_A_SD6_3 R_A_SD6_2 R_A_SD6_1 R_A_SD6_0
R_B_SD6_5 R_B_SD6_6 R_B_SD6_7 R_B_SD6_4 R_B_SD6_1 R_B_SD6_0 R_B_SD6_2 R_B_SD6_3
R_A_SD7_6 R_A_SD7_4 R_A_SD7_7 R_A_SD7_5 R_A_SD7_0 R_A_SD7_2 R_A_SD7_1 R_A_SD7_3
R_B_SD7_6 R_B_SD7_7 R_B_SD7_4 R_B_SD7_5 R_B_SD7_3 R_B_SD7_2 R_B_SD7_1 R_B_SD7_0
R_A_SD4_7 R_A_SD4_5 R_A_SD4_6 R_A_SD4_4 R_A_SD4_3 R_A_SD4_2 R_A_SD4_1 R_A_SD4_0
R_B_SD8_5 R_B_SD8_4 R_B_SD8_7 R_B_SD8_6 R_B_SD8_2 R_B_SD8_0 R_B_SD8_1 R_B_SD8_3
R_A_SD5_7 R_A_SD5_5 R_A_SD5_6 R_A_SD5_4 R_A_SD5_3 R_A_SD5_0 R_A_SD5_1 R_A_SD5_2
SUB*_8Y113
This is REMC version 3.0
Jaguar 2.0 Change: Changed REMC fom rev 2.0 to 3.0 (with deglitching circuit)
4 4 4 4 4 4 4 4
4 4 4 4 4 4 4 4
4 4 4 4 4 4 4 4
4 4 4 4 4 4 4 4
4 4 4 4 4 4 4 4
4 4 4 4 4 4 4 4
4 4 4 4 4 4 4 4
4 4 4 4 4 4 4 4
4 4 4 4 4 4 4 4
4
1
2
3
4
REMC1_ID1
4
REMC1_ID0
4
4
4
4
4
4
4
4
4
4
4
4
4
R_CSTRB3
R_CSTRB2
4
R_B_DQS8_0
4
R_B_DQS8_1
4
R_B_SD8_2
R_B_SD8_6
R_B_SD5_7
R_B_SD6_0
R_B_SD6_1
R_B_SD6_4
R_B_SD4_6
R_B_SD4_7
R_B_SD4_3
R_B_SD5_4
R_A_SD5_5
R_A_DQS5_0
4
R_A_DQS5_1
4
R_A_SD7_6
4
R_A_DQS7_1
4
R_A_SD5_1
4
R_A_SD7_1
4
R_A_SD7_3
4
R_A_SD7_7
4
R_A_SD7_2
4
R_A_DQS7_0
4
R_B_SD8_7
4
R_A_SD7_0
1 2
150-5%
1 2
150-5%
RN359
1 8
12 OHM-5%
RN359
2 7
12 OHM-5%
RN359
3 6
12 OHM-5%
RN359
4 5
12 OHM-5%
RN360
1 8
12 OHM-5%
RN360
2 7
12 OHM-5%
RN360
3 6
12 OHM-5%
RN360
4 5
12 OHM-5%
RN361
1 8
12 OHM-5%
RN361
2 7
12 OHM-5%
RN361
3 6
12 OHM-5%
RN361
4 5
12 OHM-5%
RN344
4 5
12 OHM-5%
RN344
1 8
12 OHM-5%
RN344
2 7
12 OHM-5%
RN362
1 8
12 OHM-5%
RN362
2 7
12 OHM-5%
RN344
3 6
12 OHM-5%
RN362
3 6
12 OHM-5%
1 8
12 OHM-5%
2 7
12 OHM-5%
3 6
12 OHM-5%
4 5
12 OHM-5%
12 OHM 5%
RN362
4 5
12 OHM-5%
RN407
RN407
RN407
RN407
15
15
2-7,9,11,13,14,16
UNIQUE_ID
VCC25
B_DQS8_0
B_DQS8_1
B_SD8_2
B_SD8_6
B_SD5_7
B_SD6_0
B_SD6_1
B_SD6_4
B_SD4_6
B_SD4_7
B_SD4_3
B_SD5_4
A_SD5_5
A_DQS5_0
A_DQS5_1
A_SD7_6
A_DQS7_1
A_SD5_1
A_SD7_1
A_SD7_3
A_SD7_7
A_SD7_2
A_DQS7_0
B_SD8_7
21
A_SD7_0
21
21
CSTRB3
CSTRB2
2,3
2-7,9,11,13,14,16
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
5,7,12
5,7,12
5,7,12
5,7,12
6,9,10
2
VCC25
R_CSTRB3
4
2
249 Ohm-1%
2-7,9,11,13,14,16
VCC25
1K-5%
1 2
R_CSTRB3
4
R_CSTRB2
4
R_CSTRB2
4
R_MSTRB1
15
COMP0_DP11 2 REMC1_ID1
4
REMC1_ID0
4
NC_CMD9_3_DP1 NC_CMD9_2_DP1 NC_CMD9_1_DP1 NC_CMD9_0_DP1
R_MECC7
15
R_MECC6
15
R_MECC5
15
R_MECC4
15
15 15 15 15
15 15 15 15
15 15 15 15
15 15 15 15
15 15 15 15
15 15 15 15
15 15 15 15
15 15 15 15
2,3,12 2,3,12 2,3,12 2-4,12
4 4
4 4
4 4
4 4
4 4
4 4
4 4
4 4
4 4
PU_ISOLATE_DP1
RCMD3 RCMD2 RCMD1 RCMD0
R_B_DQS4_1 R_B_DQS4_0
R_B_DQS5_1 R_B_DQS5_0
R_A_DQS6_1 R_A_DQS6_0
R_B_DQS6_1 R_B_DQS6_0
R_A_DQS7_1 R_A_DQS7_0
R_B_DQS7_1 R_B_DQS7_0
R_A_DQS4_1 R_A_DQS4_0
R_B_DQS8_1 R_B_DQS8_0
R_A_DQS5_1 R_A_DQS5_0
R_CMD63 R_CMD62 R_CMD61 R_CMD60
R_CMD59 R_CMD58 R_CMD57 R_CMD56
R_CMD55 R_CMD54 R_CMD53 R_CMD52
R_CMD51 R_CMD50 R_CMD49 R_CMD48
R_CMD47 R_CMD46 R_CMD45 R_CMD44
R_CMD43 R_CMD42 R_CMD41 R_CMD40
R_CMD39 R_CMD38 R_CMD37 R_CMD36
R_CMD35 R_CMD34 R_CMD33 R_CMD32
2,3,12
VCC25
2-7,9,11,13,14,16
Strapping option: RCMD0 = 0 (PLL enabled)
2-4,12
R_A_SD4_6
4
R_A_SD4_2
4
R_A_DQS4_1
4
4 4
R_A_DQS4_0
4
R_A_SD5_4
4
R_A_SD5_0
4
R_A_SD4_3
4
R_A_SD4_7
4
RN349
1 8
12 OHM-5%
RN349
2 7
12 OHM-5%
RN349
3 6
12 OHM-5%
RN349
4 5
12 OHM-5%
RN350
1 8
12 OHM-5%
RN350
2 7
12 OHM-5%
RN350
3 6
12 OHM-5%
RN350
4 5
12 OHM-5%
A_SD4_6
A_SD4_2
A_DQS4_1
A_DQS4_0
A_SD5_4
A_SD5_0
A_SD4_3
A_SD4_7
RCMD0
R_B_SD4_5
4
4
R_B_SD4_2
4
4
R_B_SD4_0
4
R_B_SD4_4
4
R_B_SD7_3
4
1 2
1 2
R_B_DQS4_0
R_B_DQS4_1
1K-5%1K-5%
NP*
RN369
1 8
12 OHM-5%
RN369
2 7
12 OHM-5%
RN369
3 6
12 OHM-5%
RN369
4 5
12 OHM-5%
RN370
1 8
12 OHM-5%
RN370
2 7
12 OHM-5%
RN370
3 6
12 OHM-5%
12 OHM 5%
B_SD4_5
B_DQS4_0
B_SD4_2
B_DQS4_1
NC_RN370_8NC_RN370_1
B_SD4_0
B_SD4_4
B_SD7_3
21
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
R_A_SD4_1
4
R_A_SD4_5
4
R_A_SD4_4
4
R_A_SD4_0
4
R_B_SD4_1
4
R_B_SD8_3
4
RN351
1 8
12 OHM-5%
RN351
2 7
12 OHM-5%
RN351
3 6
12 OHM-5%
RN351
4 5
12 OHM-5%
RN370
4 5
12 OHM-5%
12 OHM 5%
A_SD4_1
A_SD4_5
A_SD4_4
A_SD4_0
B_SD4_1
B_SD8_3
21
6,9,10
6,9,10
4
R_B_DQS5_1
4
R_B_SD3_2
3
R_B_SD3_6
3
R_B_SD3_3
3
R_B_SD3_7
3
R_B_SD8_4
4
R_B_SD8_5
4
R_B_SD8_0
4
R_B_SD8_1
4
R_B_SD6_5
4
R_B_DQS6_1
4
R_B_SD6_6
4
R_B_DQS6_0
4
R_B_SD6_2
4
R_B_SD6_7
4
R_B_SD6_3
4
R_A_SD6_7
4
R_A_DQS6_0
4
R_A_SD6_6
4
R_A_DQS6_1
4
R_A_SD7_5
4
R_A_SD7_4
4
R_A_SD6_3
4
R_B_SD7_6
4
R_B_SD7_4
4
R_B_DQS7_0
R_B_SD7_2
4
R_B_SD7_7
4
R_B_SD7_5
4
R_B_SD7_0
4
R_B_SD7_1
4
R_A_SD5_7
4
R_A_SD6_2
4
R_A_SD5_6
4
R_A_SD5_3
4
R_A_SD5_2
4
R_A_SD6_0
4
R_A_SD6_5
4
R_A_SD6_4
4
R_A_SD6_1
4
R_B_DQS5_0
4
R_B_DQS7_1
R_B_SD5_2
4
R_B_SD5_6
4
R_B_SD5_3
4
R_B_SD5_0
4
R_B_SD5_5
4
R_B_SD5_1
4
RN368
4 5
12 OHM-5%
RN186
1 8
12 OHM-5%
RN186
2 7
12 OHM-5%
RN186
3 6
12 OHM-5%
RN186
4 5
12 OHM-5%
RN187
1 8
12 OHM-5%
RN187
2 7
12 OHM-5%
RN187
3 6
12 OHM-5%
RN187
4 5
12 OHM-5%
RN363
1 8
12 OHM-5%
RN363
2 7
12 OHM-5%
RN363
3 6
12 OHM-5%
RN363
4 5
12 OHM-5%
RN364
1 8
12 OHM-5%
RN364
2 7
12 OHM-5%
RN364
3 6
12 OHM-5%
RN345
1 8
12 OHM-5%
RN345
2 7
12 OHM-5%
RN345
3 6
12 OHM-5%
RN345
4 5
12 OHM-5%
RN346
1 8
12 OHM-5%
RN346
2 7
12 OHM-5%
RN346
3 6
12 OHM-5%
RN365
1 8
12 OHM-5%
RN364
4 5
12 OHM-5%
RN365
2 7
12 OHM-5%
RN365
3 6
12 OHM-5%
RN365
4 5
12 OHM-5%
RN366
1 8
12 OHM-5%
RN366
2 7
12 OHM-5%
RN366
3 6
12 OHM-5%
RN347
1 8
12 OHM-5%
RN346
4 5
12 OHM-5%
RN347
2 7
12 OHM-5%
RN347
3 6
12 OHM-5%
RN347
4 5
12 OHM-5%
RN348
4 5
12 OHM-5%
RN348
1 8
12 OHM-5%
RN348
2 7
12 OHM-5%
RN348
3 6
12 OHM-5%
RN367
1 8
12 OHM-5%
RN366
4 5
12 OHM-5%
RN367
2 7
12 OHM-5%
RN367
3 6
12 OHM-5%
RN367
4 5
12 OHM-5%
RN368
1 8
12 OHM-5%
RN368
2 7
12 OHM-5%
RN368
3 6
12 OHM-5%
B_DQS5_1
B_SD3_2
B_SD3_6
B_SD3_3
B_SD3_7
B_SD8_4
B_SD8_5
B_SD8_0
B_SD8_1
B_SD6_5
B_DQS6_1
B_SD6_6
B_DQS6_0
B_SD6_2
B_SD6_7
B_SD6_3
A_SD6_7
A_DQS6_0
A_SD6_6
A_DQS6_1
A_SD7_5
A_SD7_4
A_SD6_3
B_SD7_6
B_SD7_4
B_DQS7_0
B_SD7_2
B_SD7_7
B_SD7_5
B_SD7_0
B_SD7_1
A_SD5_7
A_SD6_2
A_SD5_6
A_SD5_3
A_SD5_2
A_SD6_0
A_SD6_5
A_SD6_4
A_SD6_1
B_DQS5_0
B_DQS7_1
B_SD5_2
B_SD5_6
B_SD5_3
B_SD5_0
B_SD5_5
B_SD5_1
6,9,10
6,9,10
6,9,10
VCC25
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
4,14
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
6,9,10
PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.
SSTLREF_R2
2-7,9,11,13,14,16
SUB*_78020
10V-20%
+
1
2-7,9,11,13,14,16
VCC25
2
1K-5%
1 2
4,14
10V-20%
CLKDP1_N
11
CLKDP1_P
11
PLLRST
2,3
TESTMODE_DP1
SRESET
3,13
R_ASDATA_DP1
4
R_ASCLK_DP1
4
SSTLREF_R2
2-7,9,11,13,14,16
21
21
Substitution for p/n consolidation
1 2
+
1
2
VCC25
1uF
1 2
+
100uF
1
1 2
1 2
2
10V-10%
1uF
10V-10%
SUB*_78020
.01UF
50V-20%
10V-20%
+80%-20%
.22uF 16V
+80%-20%
.22uF 16V
.01UF
50V-20%
10V-20%
1 2
.22uF 16V
1 2
.22uF 16V
SUB*_78020
+
1 2
VCC25
1
2
.01UF
R2
P3
N5
PLLRST
M12
TESTMODE
A1
RESET
L5
SDA
N4
SCK
R15
VREF_R15
P15
VREF_P15
D4
VREF_D4
C5
VREF_C5
P14
VDD_P14
P11
VDD_P11
P6
VDD_P6
M4
VDD_M4
L15
VDD_L15
L9
VDD_L9
L7
VDD_L7
K10
VDD_K10
K9
VDD_K9
K7
VDD_K7
K6
VDD_K6
K4
VDD_K4
J11
VDD_J11
J10
VDD_J10
J6
VDD_J6
H12
VDD_H12
H4
VDD_H4
H1
VDD_H1
G10
VDD_G10
G6
VDD_G6
F10
VDD_F10
F9
VDD_F9
F7
VDD_F7
F6
VDD_F6
F4
VDD_F4
E13
VDD_E13
E9
VDD_E9
E7
VDD_E7
D6
VDD_D6
B8
VDD_B8
A15
VDD_A15
A11
VDD_A11
+80%-20%
+80%-20%
SUB*_78020
1 2
50V-20%
REMC Version 1.0
HETERO 2 OF 2
SUB*_8Y113
This is REMC version 3.0
.01UF
2-7,9,11,13,14,16
1 2
50V-20%
0.1uF 16V
U25
1 2
GND_R11
GND_R1 GND_P5
GND_N14
GND_N8
GND_L10
GND_L8 GND_L3
GND_K12
GND_K8 GND_J9 GND_J8 GND_J7 GND_J5
GND_H10
GND_H9 GND_H8 GND_H7 GND_H6
GND_G14
GND_G9
GND_G8 GND_G7 GND_G5
GND_F12
GND_F8
GND_E10
GND_E8 GND_E6 GND_E5
GND_E1 GND_C15 GND_B11
GND_A8
3,5
DISCONNECT REMC I2C BUS
1 2
0.1uF 16V
21
L15
47uH 135MA
R3 P4 M5 R4
22uF 10V
12
BE USED ON NEW DESIGNS.
THIS PART IS NOT TO
R11 R1 P5 N14 N8 L10 L8 L3 K12 K8 J9 J8 J7 J5 H10 H9 H8 H7 H6 G14 G9
G8 G7 G5 F12 F8 E10 E8 E6 E5 E1 C15 B11 A8
3,5-7,9,13
FSTEDG_ASCLK_2P5V
ASDATA_2P5V
NP*
NP*
1 2
1 2
DUE TO NO POST PROBLEM
Substitution for p/n consolidation
VCC25 SUB*_79015
21
.001UF
50V-20%
SUB*_79015
21
0.1uF 16V
2-7,9,11,13,14,16
1uF
10V-10%
1 2
1 2
0.1uF 16V
VCC25
21
1 2
2-7,9,11,13,14,16
1 2
SUB*_79015
.001UF
50V-20%
VCC25
0.1uF 16V
8.2K-5% R_ASCLK_DP1
21
.001UF
50V-20%
SUB*_79015
VCC25
21
REMC DATA PATH 1
TITLE
SCHEM,MEM-CRD,6DIMM,PE4600
DWG NO.
8Y810
8/3/2004
2-7,9,11,13,14,16
2-7,9,11,13,14,16
8.2K-5%
1 2
R_ASDATA_DP1
4
SUB*_79015
21
.001UF
50V-20%
COMPUTER CORPORATION
AUSTIN,TEXAS
SHEET
.001UF
50V-20%
SUB*_79015
21
.001UF
50V-20%
4 OF 18
21
A03
1
2
4
3
1uF
10V-10%
A B
DC
Page 5
B D
CA
8-3-2004_15:33
1
2
3
STAKE PIN FOR TEST
A_CS_0
2,6
2-7,9,11,13,14,16
J14
VCC25
VCC25
2-7,9,11,13,14,16
5-7,9,14
2,7,12 2,7,12 2,7,12 2,7,12 2,7,12 2,7,12 2,7,12 2,7,12 2,7,12 2,7,12
2,6 2,7,12 2,7,12
NP*
1
5-7,9,14
5-7,9,13 3-7,9,13
6,7,9,13
2-7,9,11,13,14,16
2-7,9,11,13,14,16
ASCLK_2P5V
ASDATA_2P5V
R0_MA10
2,6 2,6
2,6 2,6
2,6
11 11
2,7,12
NC_FETEN_J2
SSTLREF_D1
NC_VDDID_J2
NC_NC1_J2 NC_NC2_J2 A_RESET NC_NC4_J2 NC_NC5_J2 NC_CS3_J2
NC_CS2_J2 NC_CLK2_N_J2 NC_CLK2_P_J2 NC_CLK1_N_J2 NC_CLK1_P_J2 NC_BA2_J2 NC_A13_J2
VCC25
VCC25
A_MA0 A_MA1 A_MA2 A_MA3 A_MA4 A_MA5 A_MA6 A_MA7 A_MA8 A_MA9
A_MA11 A_MA12
R0_BA0_0 R0_BA1_0
A_CS_1
2,6
R0_RAS_0 R0_CAS_0
R0_WE_0
CLK_J2_P CLK_J2_N
A_CKE
NC_WP_J2
48 43 41
130
37 32
125
29
122
27 141 118 115
59
52
157 158 154
65
63
137 138
21 111
167
184
82
92
91 181 182 183
90
102 101
10
173 163
71
75
76
17
16 113 103
168 148 120 108
85
70
46
38
136 180 156 112 164 143 128 104
96 172
77
62
54
30
22
15
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
BA0 BA1
CS CS1 RAS CAS WE
CLK0_P CLK0_N
CLKE0 CLKE1
FETEN
1
VREF VDDSPD
VDDID SCL
SDA SA0 SA1 SA2 WP
NC1 NC2 RESET
9
NC4 NC5 CS3_NU CS2_NU CLK2_N_DU CLK2_P_DU CLK1_N_DU CLK1_P_DU BA2_NU A13_NU
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8
7
VDD10
VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16
SSTLREF_D1
J2
2
1
1
2
+80%-20%
.22uF 16V
DM1_DQS10
DM2_DQS11
DM3_DQS12
DM4_DQS13
DM5_DQS14
DM6_DQS15
DM7_DQS16
DM8_DQS17
2
1
+80%-20%
.22uF 16V
D0 D1 D2 D3
DQS0
DM0_DQS9
D4 D5 D6 D7 D8
D9 D10 D11
DQS1
D12 D13 D14 D15 D16 D17 D18 D19
DQS2
D20 D21 D22 D23 D24 D25 D26 D27
DQS3
D28 D29 D30 D31 D32 D33 D34 D35
DQS4
D36 D37 D38 D39 D40 D41 D42 D43
DQS5
D44 D45 D46 D47 D48 D49 D50 D51
DQS6
D52 D53 D54 D55 D56 D57 D58 D59
DQS7
D60 D61 D62 D63
ECC0 ECC1 ECC2 ECC3 DQS8
ECC4 ECC5 ECC6 ECC7
1
2
+80%-20%
.22uF 16V
2 4 6 8 5 97 94 95 98 99 12 13 19 20 14 107 105 106 109 110 23 24 28 31 25 119 114 117 121 123 33 35 39 40 36 129 126 127 131 133 53 55 57 60 56 149 146 147 150 151 61 64 68 69 67 159 153 155 161 162 72 73 79 80 78 169 165 166 170 171 83 84 87 88 86 177 174 175 178 179 44 45 49 51 47 140 134 135 142 144
+80%-20%
.22uF 16V
A_SD0_0 A_SD0_1 A_SD0_2 A_SD0_3 A_DQS0_0 A_DQS0_1 A_SD0_4 A_SD0_5 A_SD0_6 A_SD0_7 A_SD1_0 A_SD1_1 A_SD1_2 A_SD1_3 A_DQS1_0 A_DQS1_1 A_SD1_4 A_SD1_5 A_SD1_6 A_SD1_7 A_SD2_0 A_SD2_1 A_SD2_2 A_SD2_3 A_DQS2_0 A_DQS2_1 A_SD2_4 A_SD2_5 A_SD2_6 A_SD2_7
A_SD3_0 A_SD3_1 A_SD3_2 A_SD3_3 A_DQS3_0 A_DQS3_1 A_SD3_4 A_SD3_5 A_SD3_6 A_SD3_7 A_SD4_0 A_SD4_1 A_SD4_2 A_SD4_3 A_DQS4_0 A_DQS4_1 A_SD4_4 A_SD4_5 A_SD4_6 A_SD4_7 A_SD5_0 A_SD5_1 A_SD5_2 A_SD5_3 A_DQS5_0 A_DQS5_1 A_SD5_4 A_SD5_5 A_SD5_6 A_SD5_7 A_SD6_0 A_SD6_1 A_SD6_2 A_SD6_3 A_DQS6_0 A_DQS6_1 A_SD6_4 A_SD6_5 A_SD6_6 A_SD6_7 A_SD7_0 A_SD7_1 A_SD7_2 A_SD7_3 A_DQS7_0
A_DQS7_1 A_SD7_4 A_SD7_5 A_SD7_6 A_SD7_7 A_SD8_0 A_SD8_1 A_SD8_2 A_SD8_3 A_DQS8_0 A_DQS8_1 A_SD8_4 A_SD8_5 A_SD8_6 A_SD8_7
4,7,12 4,7,12
Q8
2N7002
1 2
2,11
ASCLK_3P3V
D 3
1 2
G
1
S 2
NP*
VCC25
2-7,9,11,13,14,16
Q9
2N7002
2,11
ASDATA_3P3V
D 3
1 2
G
1
S 2
NP*
1 2
VOLTAGE LEVEL CONVERSION FOR SPDs (2.5V I2C)
NP*
U95 74HC126
32
NP*
8.2K-5%
NP*
VCC25
2-7,9,11,13,14,16
5-7,9,13
1 2
VCC25
2-7,9,11,13,14,16
14
ASCLK_2P5V
1
1 2
FAST SCL EDGE REQUIRED BY REMC rev 2.0s
ASCLK_2P5V
8.2K-5% 8.2K-5%
ASDATA_2P5V
FSTEDG_ASCLK_2P5V
1
5-7,9,13
3-7,9,13
2
3,4
3
DDR SDRAM DIMM
SUB*_726NT
BE USED ON NEW DESIGNS.
THIS PART IS NOT TO
22uF 10V
1
2
BE USED ON NEW DESIGNS.
Substitution for p/n consolidation
.01UF
1 2
SUB*_78020
22uF 10V
1
2
THIS PART IS NOT TO
1 2
50V-20%
SUB*_78020
.01UF
1 2
50V-20%
.01UF
50V-20%
VCC25
SUB*_78020
.01UF
1 2
1 2
50V-20%
.01UF
50V-20%
.01UF
1 2
50V-20%
SUB*_78020
.01UF
1 2
50V-20%
SUB*_78020
1 2
.01UF
50V-20%
.01UF
1 2
50V-20%
SUB*_78020
1 2
.01UF
50V-20%
.01UF
1 2
50V-20%
.01UF
1 2
50V-20%
2-7,9,11,13,14,16
2
1
+80%-20%
.22uF 16V
VTT_SSTL
2,3,6,8,10,12-14
4 4
SUB*_78020
SUB*_78020
SUB*_78020
SUB*_78020
SUB*_78020
SUB*_78020
J2
COMPUTER CORPORATION
Put one 22 uF cap at each end of DIMM
AUSTIN,TEXAS
TITLE
A B
PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.
DWG NO.
DC
SCHEM,MEM-CRD,6DIMM,PE4600
8Y810
SHEET
8/3/2004
A03
5 OF 18
Page 6
B D
CA
8-3-2004_15:33
1
2
3
STAKE PIN FOR TEST
A_CS_1
2,5
J25
NP*
1
2-7,9,11,13,14,16
VCC25
2,9,12 2,9,12 2,9,12 2,9,12 2,9,12 2,9,12 2,9,12 2,9,12 2,9,12 2,9,12
2,9,12 2,9,12
2,9,12
5-7,9,14
5,7,9,13
3-5,7,9,13
5,7,9,13
VCC25
2-7,9,11,13,14,16
VCC25
2-7,9,11,13,14,16
R0_MA10
2,5
R0_BA0_0
2,5
R0_BA1_0
2,5
A_CS_0
2,5
R0_RAS_0
2,5
R0_CAS_0
2,5
R0_WE_0
2,5
CLK_J1_P
11
CLK_J1_N
11
B_CKE
NC_FETEN_J1
SSTLREF_D1
NC_VDDID_J1
ASCLK_2P5V ASDATA_2P5V
NC_WP_J1
NC_NC1_J1 NC_NC2_J1 A_RESET NC_NC4_J1 NC_NC5_J1 NC_CS3_J1
NC_CS2_J1 NC_CLK2_N_J1 NC_CLK2_P_J1 NC_CLK1_N_J1 NC_CLK1_P_J1 NC_BA2_J1 NC_A13_J1
B_MA0 B_MA1 B_MA2 B_MA3 B_MA4 B_MA5 B_MA6 B_MA7 B_MA8 B_MA9
B_MA11 B_MA12
48 43 41
130
37 32
125
29
122
27 141 118 115
59
52
157 158 154
65
63
137 138
21 111
167
1
184
82
92
91 181 182 183
90
102 101
10
9 173 163
71 75 76 17
16 113 103
168 148 120 108
85
70
46
38
7
136 180 156 112 164 143 128 104
96 172
77
62
54
30
22
15
5-7,9,14
SSTLREF_D1
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
BA0 BA1
CS CS1 RAS CAS WE
CLK0_P CLK0_N
CLKE0 CLKE1
FETEN VREF VDDSPD
VDDID SCL
SDA SA0 SA1 SA2 WP
NC1 NC2 RESET NC4 NC5 CS3_NU CS2_NU CLK2_N_DU CLK2_P_DU CLK1_N_DU CLK1_P_DU BA2_NU A13_NU
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD10
VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16
J1
2
1
1
2
+80%-20%
.22uF 16V
2
1
+80%-20%
.22uF 16V
1
2
+80%-20%
.22uF 16V
.22uF 16V
D0 D1 D2 D3
DQS0
DM0_DQS9
D4 D5 D6 D7 D8
D9 D10 D11
DQS1
DM1_DQS10
D12 D13 D14 D15 D16 D17 D18 D19
DQS2
DM2_DQS11
D20 D21 D22 D23 D24 D25 D26 D27
DQS3
DM3_DQS12
D28 D29 D30 D31 D32 D33 D34 D35
DQS4
DM4_DQS13
D36 D37 D38 D39 D40 D41 D42 D43
DQS5
DM5_DQS14
D44 D45 D46 D47 D48 D49 D50 D51
DQS6
DM6_DQS15
D52 D53 D54 D55 D56 D57 D58 D59
DQS7
DM7_DQS16
D60 D61 D62 D63
ECC0 ECC1 ECC2 ECC3 DQS8
DM8_DQS17
ECC4 ECC5 ECC6 ECC7
+80%-20%
2 4 6 8 5 97 94 95 98 99 12 13 19 20 14 107 105 106 109 110 23 24 28 31 25 119 114 117 121 123 33 35 39 40 36 129 126 127 131 133 53 55 57 60 56 149 146 147 150 151 61 64 68 69 67 159 153 155 161 162 72 73 79 80 78 169 165 166 170 171 83 84 87 88 86 177 174 175 178 179 44 45 49 51 47 140 134 135 142 144
B_SD0_0 B_SD0_1 B_SD0_2 B_SD0_3 B_DQS0_0 B_DQS0_1 B_SD0_4 B_SD0_5 B_SD0_6 B_SD0_7 B_SD1_0 B_SD1_1 B_SD1_2 B_SD1_3 B_DQS1_0 B_DQS1_1 B_SD1_4 B_SD1_5 B_SD1_6 B_SD1_7 B_SD2_0 B_SD2_1 B_SD2_2 B_SD2_3 B_DQS2_0 B_DQS2_1 B_SD2_4 B_SD2_5 B_SD2_6 B_SD2_7 B_SD3_0 B_SD3_1 B_SD3_2 B_SD3_3 B_DQS3_0 B_DQS3_1 B_SD3_4 B_SD3_5 B_SD3_6 B_SD3_7 B_SD4_0 B_SD4_1 B_SD4_2 B_SD4_3 B_DQS4_0 B_DQS4_1 B_SD4_4 B_SD4_5 B_SD4_6 B_SD4_7 B_SD5_0 B_SD5_1 B_SD5_2 B_SD5_3 B_DQS5_0 B_DQS5_1 B_SD5_4 B_SD5_5 B_SD5_6 B_SD5_7 B_SD6_0 B_SD6_1 B_SD6_2 B_SD6_3 B_DQS6_0 B_DQS6_1 B_SD6_4 B_SD6_5 B_SD6_6 B_SD6_7 B_SD7_0 B_SD7_1 B_SD7_2 B_SD7_3 B_DQS7_0 B_DQS7_1 B_SD7_4 B_SD7_5 B_SD7_6 B_SD7_7 B_SD8_0 B_SD8_1 B_SD8_2 B_SD8_3 B_DQS8_0 B_DQS8_1 B_SD8_4 B_SD8_5 B_SD8_6 B_SD8_7
3,9,10 3,9,10 3,9,10 3,9,10
3,9,10 3,9,10 3,9,10 3,9,10 3,9,10 3,9,10 3,9,10 3,9,10
3,9,10 3,9,10 3,9,10 3,9,10
3,9,10 3,9,10 3,9,10 3,9,10
3,9,10 3,9,10 3,9,10 3,9,10
3,9,10 3,9,10
3,9,10 3,9,10
3,9,10 3,9,10 4,9,10 4,9,10
3,9,10
3,9,10 3,9,10 3,9,10 4,9,10 4,9,10
4,9,10 4,9,10 4,9,10 4,9,10
4,9,10 4,9,10 4,9,10 4,9,10
3,9,10 3,9,10
4,9,10 4,9,10
4,9,10 4,9,10 4,9,10 4,9,10
4,9,10
4,9,10 4,9,10 4,9,10 4,9,10 4,9,10
4,9,10 4,9,10 4,9,10 4,9,10
4,9,10 4,9,10 4,9,10 4,9,10
4,9,10 4,9,10 4,9,10 4,9,10
4,9,10 4,9,10 4,9,10 4,9,10
1
2
4,9,10 4,9,10
3
4,9,10 4,9,10
4,9,10 4,9,10 4,9,10 4,9,10
4,9,10
4,9,10 4,9,10 4,9,10 4,9,10 4,9,10
DDR SDRAM DIMM
SUB*_726NT
BE USED ON NEW DESIGNS.
THIS PART IS NOT TO
22uF 10V
1
2
4 4
BE USED ON NEW DESIGNS.
THIS PART IS NOT TO
SUB*_78020
22uF 10V
1
2
1 2
.01UF
SUB*_78020
1 2
50V-20%
SUB*_78020
.01UF
1 2
50V-20%
.01UF
SUB*_78020
1 2
50V-20%
SUB*_78020
.01UF
1 2
50V-20%
Substitution for p/n consolidation
SUB*_78020
.01UF
50V-20%
SUB*_78020
1 2
.01UF
50V-20%
1 2
.01UF
50V-20%
SUB*_78020
.01UF
1 2
SUB*_78020
50V-20%
1 2
.01UF
50V-20%
SUB*_78020
.01UF
1 2
SUB*_78020
50V-20%
1 2
.01UF
50V-20%
VCC25
.01UF
1 2
SUB*_78020
50V-20%
2-7,9,11,13,14,16
2
1
+80%-20%
.22uF 16V
VTT_SSTL
2,3,5,8,10,12-14
J1
COMPUTER CORPORATION
Put one 22 uF cap at each end of DIMM
AUSTIN,TEXAS
TITLE
A B
PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.
DWG NO.
DC
SCHEM,MEM-CRD,6DIMM,PE4600
8Y810
SHEET
8/3/2004
A03
6 OF 18
Page 7
B D
CA
8-3-2004_15:33
SSTLREF_D1
2
1
1
2
+80%-20%
.22uF 16V
2
1
+80%-20%
.22uF 16V
1
2
+80%-20%
.22uF 16V
+80%-20%
.22uF 16V
5-7,9,14
SSTLREF_D1
2
1
1
2
+80%-20%
.22uF 16V
2
1
+80%-20%
.22uF 16V
1
2
+80%-20%
.22uF 16V
+80%-20%
.22uF 16V
5-7,9,14
1
1
J6
J4
2
3
STAKE PIN FOR TEST
A_CS_4
2,9
2-7,9,11,13,14,16
VCC25
J21
1
2,5,7,12 2,5,7,12 2,5,7,12 2,5,7,12 2,5,7,12 2,5,7,12 2,5,7,12 2,5,7,12 2,5,7,12 2,5,7,12
2,9 2,5,7,12 2,5,7,12
NP*
2,5,7,12
5-7,9,14
5-7,9,13
2-7,9,11,13,14,16
2-7,9,11,13,14,16
BE USED ON NEW DESIGNS.
THIS PART IS NOT TO
22uF 10V
1
2
22uF 10V
1
R2_BA0_0
2,9
R2_BA1_0
2,9
A_CS_5
2,9
R2_RAS_0
2,9
R2_CAS_0
2,9
R2_WE_0
2,9
CLK_J6_P
11
CLK_J6_N
11
A_CKE
NC_FETEN_J6
SSTLREF_D1
5-7,9,13 3-7,9,13
NC_NC1_J6 NC_NC2_J6 A_RESET NC_NC4_J6 NC_NC5_J6 NC_CS3_J6
NC_CS2_J6 NC_CLK2_N_J6 NC_CLK2_P_J6 NC_CLK1_N_J6 NC_CLK1_P_J6 NC_BA2_J6 NC_A13_J6
BE USED ON NEW DESIGNS.
THIS PART IS NOT TO
SUB*_78020
2
A_MA0 A_MA1 A_MA2 A_MA3 A_MA4 A_MA5 A_MA6 A_MA7 A_MA8
A_MA9 R2_MA10 A_MA11 A_MA12
NC_VDDID_J6
ASCLK_2P5V ASDATA_2P5V
NC_WP_J6
VCC25
VCC25
.01UF
1 2
50V-20%
SUB*_78020
1 2
SUB*_78020
.01UF
1 2
50V-20%
48 43 41
130
37 32
125
29
122
27 141 118 115
59
52
157 158 154
65
63
137 138
21 111
167
1
184
82
92
91 181 182 183
90
102 101
10
9 173 163
71 75 76 17
16 113 103
168 148 120 108
85
70
46
38
7
136 180 156 112 164 143 128 104
96 172
77
62
54
30
22
15
Substitution for p/n consolidation
.01UF
50V-20%
SUB*_78020
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
BA0 BA1
CS CS1 RAS CAS WE
CLK0_P CLK0_N
CLKE0 CLKE1
FETEN VREF VDDSPD
VDDID SCL
SDA SA0 SA1 SA2 WP
NC1 NC2 RESET NC4 NC5 CS3_NU CS2_NU CLK2_N_DU CLK2_P_DU CLK1_N_DU CLK1_P_DU BA2_NU A13_NU
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD10
VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16
SUB*_78020
.01UF
1 2
1 2
50V-20%
DDR SDRAM DIMM
SUB*_726NT
.01UF
SUB*_78020
1 2
50V-20%
SUB*_78020
.01UF
1 2
50V-20%
.01UF
SUB*_78020
1 2
50V-20%
DM0_DQS9
DM1_DQS10
DM2_DQS11
DM3_DQS12
DM4_DQS13
DM5_DQS14
DM6_DQS15
DM7_DQS16
DM8_DQS17
SUB*_78020
.01UF
1 2
50V-20%
D0 D1 D2 D3
DQS0
D4 D5 D6 D7 D8
D9 D10 D11
DQS1
D12 D13 D14 D15 D16 D17 D18 D19
DQS2
D20 D21 D22 D23 D24 D25 D26 D27
DQS3
D28 D29 D30 D31 D32 D33 D34 D35
DQS4
D36 D37 D38 D39 D40 D41 D42 D43
DQS5
D44 D45 D46 D47 D48 D49 D50 D51
DQS6
D52 D53 D54 D55 D56 D57 D58 D59
DQS7
D60 D61 D62 D63
ECC0 ECC1 ECC2 ECC3 DQS8
ECC4 ECC5 ECC6 ECC7
.01UF
50V-20%
SUB*_78020
1 2
2 4 6 8 5 97 94 95 98 99 12 13 19 20 14 107 105 106 109 110 23 24 28 31 25 119 114 117 121 123 33 35 39 40 36 129 126 127 131 133 53 55 57 60 56 149 146 147 150 151 61 64 68 69 67 159 153 155 161 162 72 73 79 80 78 169 165 166 170 171 83 84 87 88 86 177 174 175 178 179 44 45 49 51 47 140 134 135 142 144
SUB*_78020
.01UF
A_SD0_0 A_SD0_1 A_SD0_2 A_SD0_3 A_DQS0_0 A_DQS0_1 A_SD0_4 A_SD0_5 A_SD0_6 A_SD0_7 A_SD1_0 A_SD1_1 A_SD1_2 A_SD1_3 A_DQS1_0 A_DQS1_1 A_SD1_4 A_SD1_5 A_SD1_6 A_SD1_7 A_SD2_0 A_SD2_1 A_SD2_2 A_SD2_3 A_DQS2_0 A_DQS2_1 A_SD2_4 A_SD2_5 A_SD2_6 A_SD2_7 A_SD3_0 A_SD3_1 A_SD3_2 A_SD3_3 A_DQS3_0 A_DQS3_1 A_SD3_4 A_SD3_5 A_SD3_6 A_SD3_7 A_SD4_0 A_SD4_1 A_SD4_2 A_SD4_3 A_DQS4_0 A_DQS4_1 A_SD4_4 A_SD4_5 A_SD4_6 A_SD4_7 A_SD5_0 A_SD5_1 A_SD5_2 A_SD5_3 A_DQS5_0 A_DQS5_1 A_SD5_4 A_SD5_5 A_SD5_6 A_SD5_7 A_SD6_0 A_SD6_1 A_SD6_2 A_SD6_3 A_DQS6_0 A_DQS6_1 A_SD6_4 A_SD6_5 A_SD6_6 A_SD6_7 A_SD7_0 A_SD7_1 A_SD7_2 A_SD7_3 A_DQS7_0 A_DQS7_1 A_SD7_4 A_SD7_5 A_SD7_6 A_SD7_7 A_SD8_0 A_SD8_1 A_SD8_2 A_SD8_3 A_DQS8_0 A_DQS8_1 A_SD8_4 A_SD8_5 A_SD8_6 A_SD8_7
1 2
50V-20%
.01UF
SUB*_78020
1 2
50V-20%
3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8
3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8
3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8
3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8
3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8
3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8
3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8
4,5,7,8 4,5,7,8 4,5,7,8 4,5,7,8
4,5,7,8 4,5,7,8 4,5,7,8 4,5,7,8
SUB*_78020
.01UF
1 2
50V-20%
2,5,7,12 2,5,7,12 2,5,7,12
3,5,7,8 3,5,7,8
3,5,7,8 3,5,7,8
3,5,7,8 3,5,7,8
3,5,7,8 3,5,7,8
4,5,7,8 4,5,7,8
4,5,7,8 4,5,7,12 4,5,7,8 4,5,7,8
4,5,7,12 7
4,5,7,12 4,5,7,8 4,5,7,12 4,5,7,8 4,5,7,8
4,5,7,8 4,5,7,8 4,5,7,8 4,5,7,8
4,5,7,8
4,5,7,8 4,5,7,8 4,5,7,8 4,5,7,8 4,5,7,8
4,5,7,8 4,5,7,8 4,5,7,8 4,5,7,8
4,5,7,8
4,5,7,8 4,5,7,8 4,5,7,8 4,5,7,8 4,5,7,8
3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8
3,5,7,8
3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8
VCC25
.01UF
50V-20%
2-7,9,11,13,14,16
STAKE PIN FOR TEST
2,9
A_CS_2
2-7,9,11,13,14,16
J13
NP*
1
VCC25
2-7,9,11,13,14,16
2-7,9,11,13,14,16
2,5,7,12 2,5,7,12 2,5,7,12 2,5,7,12 2,5,7,12 2,5,7,12 2,5,7,12
2,9 2,5,7,12 2,5,7,12
2,5,7,12
5-7,9,14
5-7,9,13 3-7,9,13
5-7,9,13
2,9 2,9
2,9 2,9 2,9 2,9
11 11
SSTLREF_D1
NC_VDDID_J4
ASCLK_2P5V ASDATA_2P5V
NC_CLK2_N_J4 NC_CLK2_P_J4 NC_CLK1_N_J4 NC_CLK1_P_J4 NC_BA2_J4 NC_A13_J4
VCC25
VCC25
BE USED ON NEW DESIGNS.
22uF 10V
1
2
A_MA0 A_MA1 A_MA2 A_MA3 A_MA4 A_MA5 A_MA6 A_MA7 A_MA8 A_MA9
R1_MA10
A_MA11 A_MA12
R1_BA0_0 R1_BA1_0
A_CS_3 R1_RAS_0 R1_CAS_0 R1_WE_0
CLK_J4_P CLK_J4_N
A_CKE
NC_FETEN_J4
NC_WP_J4
NC_NC1_J4 NC_NC2_J4 A_RESET NC_NC4_J4 NC_NC5_J4 NC_CS3_J4 NC_CS2_J4
BE USED ON NEW DESIGNS.
THIS PART IS NOT TO
22uF 10V
THIS PART IS NOT TO
SUB*_78020
1
2
1 2
.01UF
48 43 41
130
37 32
125
29
122
27 141 118 115
59
52
157 158 154
65
63
137 138
21 111
167
1
184
82
92
91 181 182 183
90
102 101
10
9 173 163
71 75 76 17
16 113 103
168 148 120 108
85
70
46
38
7
136 180 156 112 164 143 128 104
96 172
77
62
54
30
22
15
1 2
50V-20%
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
BA0 BA1
CS CS1 RAS CAS WE
CLK0_P CLK0_N
CLKE0 CLKE1
FETEN VREF VDDSPD
VDDID SCL
SDA SA0 SA1 SA2 WP
NC1 NC2 RESET NC4 NC5 CS3_NU CS2_NU CLK2_N_DU CLK2_P_DU CLK1_N_DU CLK1_P_DU BA2_NU A13_NU
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD10
VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16
DDR SDRAM DIMM
SUB*_726NT
Substitution for p/n consolidation
SUB*_78020
.01UF
1 2
50V-20%
.01UF
50V-20%
SUB*_78020
.01UF
1 2
1 2
50V-20%
.01UF
50V-20%
SUB*_78020
.01UF
1 2
1 2
50V-20%
D0 D1 D2 D3
DQS0
DM0_DQS9
D4 D5 D6 D7 D8
D9 D10 D11
DQS1
DM1_DQS10
D12 D13 D14 D15 D16 D17 D18 D19
DQS2
DM2_DQS11
D20 D21 D22 D23 D24 D25 D26 D27
DQS3
DM3_DQS12
D28 D29 D30 D31 D32 D33 D34 D35
DQS4
DM4_DQS13
D36 D37 D38 D39 D40 D41 D42 D43
DQS5
DM5_DQS14
D44 D45 D46 D47 D48 D49 D50 D51
DQS6
DM6_DQS15
D52 D53 D54 D55 D56 D57 D58 D59
DQS7
DM7_DQS16
D60 D61 D62 D63
ECC0 ECC1 ECC2 ECC3 DQS8
DM8_DQS17
ECC4 ECC5 ECC6 ECC7
SUB*_78020
.01UF
1 2
50V-20%
.01UF
50V-20%
2 4 6 8 5 97 94 95 98 99 12 13 19 20 14 107 105 106 109 110 23 24 28 31 25 119 114 117 121 123 33 35 39 40 36 129 126 127 131 133 53 55 57 60 56 149 146 147 150 151 61 64 68 69 67 159 153 155 161 162 72 73 79 80 78 169 165 166 170 171 83 84 87 88 86 177 174 175 178 179 44 45 49 51 47 140 134 135 142 144
1 2
A_SD0_0 A_SD0_1 A_SD0_2 A_SD0_3
A_DQS0_0
A_DQS0_1
A_SD0_4 A_SD0_5 A_SD0_6 A_SD0_7 A_SD1_0 A_SD1_1 A_SD1_2
A_SD1_3
A_DQS1_0 A_DQS1_1
A_SD1_4 A_SD1_5 A_SD1_6 A_SD1_7 A_SD2_0 A_SD2_1 A_SD2_2 A_SD2_3
A_DQS2_0
A_DQS2_1
A_SD2_4 A_SD2_5 A_SD2_6 A_SD2_7
A_SD3_0
A_SD3_1 A_SD3_2 A_SD3_3
A_DQS3_0
A_DQS3_1
A_SD3_4 A_SD3_5 A_SD3_6 A_SD3_7
A_SD4_0
A_SD4_1 A_SD4_2 A_SD4_3
A_DQS4_0
A_DQS4_1
A_SD4_4 A_SD4_5 A_SD4_6 A_SD4_7 A_SD5_0 A_SD5_1 A_SD5_2 A_SD5_3
A_DQS5_0
A_DQS5_1
A_SD5_4 A_SD5_5 A_SD5_6 A_SD5_7
A_SD6_0 A_SD6_1 A_SD6_2
A_SD6_3 A_DQS6_0 A_DQS6_1
A_SD6_4
A_SD6_5
A_SD6_6
A_SD6_7
A_SD7_0
A_SD7_1
A_SD7_2
A_SD7_3
A_DQS7_0
A_DQS7_1
A_SD7_4
A_SD7_5
A_SD7_6
A_SD7_7
A_SD8_0
A_SD8_1
A_SD8_2
A_SD8_3
A_DQS8_0
A_DQS8_1
A_SD8_4
A_SD8_5
A_SD8_6
A_SD8_7
.01UF
1 2
50V-20%
SUB*_78020
.01UF
1 2
50V-20%
3,5,7,8
.01UF
3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8
3,5,7,8
3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8
3,5,7,8
3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8
3,5,7,8
3,5,7,8
4,5,7,8
4,5,7,8
1 2
50V-20%
3,5,7,8
3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8
3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8
3,5,7,8 3,5,7,8 3,5,7,8
3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8
4,5,7,8 4,5,7,12 4,5,7,8 4,5,7,8 4,5,7,12
4,5,7,12
4,5,7,8 4,5,7,12 4,5,7,8 4,5,7,8
4,5,7,8
4,5,7,8
4,5,7,8
4,5,7,8
4,5,7,8
4,5,7,8
4,5,7,8
4,5,7,8
4,5,7,8 4,5,7,8 4,5,7,8 4,5,7,8
4,5,7,8
4,5,7,8 4,5,7,8 4,5,7,8 4,5,7,8
3,5,7,8
SUB*_78020
.01UF
3,5,7,8
4,5,7,8 4,5,7,8 4,5,7,8
4,5,7,8 4,5,7,8 4,5,7,8 4,5,7,8 4,5,7,8
4,5,7,8 4,5,7,8
4,5,7,8
1 2
50V-20%
3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8
3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8 3,5,7,8
VCC25
.01UF
50V-20%
2
3
2-7,9,11,13,14,16
4 4
SUB*_78020
SUB*_78020
SUB*_78020
SUB*_78020
SUB*_78020
SUB*_78020
J4 & J6
A B
Put one 22 uF cap at each end of DIMM
PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.
TITLE
SCHEM,MEM-CRD,6DIMM,PE4600
DWG NO.
8Y810
8/3/2004
DC
COMPUTER CORPORATION
AUSTIN,TEXAS
A03
SHEET
7 OF 18
Page 8
VTT_SSTL
2,3,5,6,8,10,12-14
B D
CA
8-3-2004_15:33
1
VTT_SSTL
2,3,5,6,8,10,12-14
12
.22uF 16V
+80%-20%
Place close to RN265
2
3
4 4
A_DQS1_1
SUB*_4282E
A_DQS1_0
SUB*_4282E
A_DQS0_1
SUB*_4282E
A_SD0_0
SUB*_4282E
A_SD0_1
SUB*_4282E
A_SD0_5
SUB*_4282E
A_SD0_4
SUB*_4282E
A_DQS0_0
SUB*_4282E
A_SD1_5
SUB*_4282E
A_SD1_0
SUB*_4282E
A_SD0_2
SUB*_4282E
A_SD8_3
SUB*_4282E
A_SD0_3
SUB*_4282E
A_SD2_2
SUB*_4282E
A_SD1_1
SUB*_4282E
A_SD1_4
SUB*_4282E
A_DQS2_1
SUB*_4282E
A_SD2_1
SUB*_4282E
A_SD2_6
SUB*_4282E
A_SD0_7
SUB*_4282E
A_SD2_0
SUB*_4282E
A_SD3_0
SUB*_4282E
A_DQS2_0
SUB*_4282E
A_SD2_5
SUB*_4282E
A_SD2_7
SUB*_4282E
A_DQS3_0
SUB*_4282E
A_SD3_5
SUB*_4282E
A_SD3_4
SUB*_4282E
A_SD2_4
SUB*_4282E
A_DQS4_1
SUB*_4282E
A_SD4_2
SUB*_4282E
A_DQS3_1
SUB*_4282E
A_DQS4_0
SUB*_4282E
A_SD4_6
SUB*_4282E
A_SD2_3
SUB*_4282E
A_SD7_7
SUB*_4282E
A_SD7_2
SUB*_4282E
A_SD5_0
SUB*_4282E
A_SD3_1
SUB*_4282E
A_DQS7_0
SUB*_4282E
RN264
4 5
22-5% RN264
3 6
22-5% RN266
2 7
22-5% RN265
1 8
22-5% RN265
4 5
22-5% RN265
3 6
22-5% RN265
2 7
22-5% RN266
1 8
22-5% RN264
2 7
22-5% RN263
3 6
22-5% RN266
4 5
22-5% RN244
1 8
22-5% RN263
2 7
22-5% RN262
3 6
22-5% RN263
4 5
22-5% RN264
1 8
22-5% RN262
2 7
22-5% RN261
3 6
22-5% RN262
4 5
22-5% RN263
1 8
22-5% RN261
2 7
22-5% RN260
3 6
22-5% RN261
4 5
22-5% RN262
1 8
22-5% RN260
2 7
22-5% RN259
3 6
22-5% RN259
2 7
22-5% RN260
4 5
22-5% RN261
1 8
22-5% RN343
2 7
22-5% RN343
3 6
22-5% RN259
4 5
22-5%
RN343
1 8
22-5% RN343
4 5
22-5% RN260
1 8
22-5%
RN245
2 7
22-5% RN245
3 6
22-5%
RN342
4 5
22-5% RN259
1 8
22-5% RN245
1 8
22-5% RN244
A_SD4_3
SUB*_4282E
A_SD5_4
SUB*_4282E
A_SD5_7
SUB*_4282E
A_SD4_7
SUB*_4282E
A_SD5_6
SUB*_4282E
A_SD5_3
SUB*_4282E
A_SD6_5
SUB*_4282E
A_SD5_2
SUB*_4282E
A_SD6_4
SUB*_4282E
A_SD6_1
SUB*_4282E
A_SD6_0
SUB*_4282E
A_SD7_5
SUB*_4282E
A_SD6_2
SUB*_4282E
A_SD6_3
SUB*_4282E
A_SD0_6
SUB*_4282E
A_SD7_4
SUB*_4282E
A_DQS7_1
SUB*_4282E
A_SD7_6
SUB*_4282E
A_SD7_0
SUB*_4282E
A_SD7_1
SUB*_4282E
A_SD3_3
SUB*_4282E
A_SD3_6
SUB*_4282E
A_SD8_0
SUB*_4282E
A_SD6_7
SUB*_4282E
A_SD3_2
SUB*_4282E
A_SD8_5
SUB*_4282E
A_SD1_2
SUB*_4282E
A_SD3_7
SUB*_4282E
A_SD8_4
SUB*_4282E
A_SD1_7
SUB*_4282E
A_SD4_1
SUB*_4282E
A_SD8_1
SUB*_4282E
A_SD1_6
SUB*_4282E
A_SD4_4
SUB*_4282E
A_DQS6_0
SUB*_4282E
A_SD4_0
SUB*_4282E
A_SD1_3
SUB*_4282E
A_SD4_5
SUB*_4282E
NC_ABUS0
SUB*_4282E
RN342
2 7
22-5% RN342
3 6
22-5% RN341
4 5
22-5% RN342
1 8
22-5% RN341
2 7
22-5% RN341
3 6
22-5% RN340
4 5
22-5% RN341
1 8
22-5% RN340
2 7
22-5% RN340
3 6
22-5% RN340
1 8
22-5% RN339
4 5
22-5% RN339
1 8
22-5% RN339
2 7
22-5% RN266
3 6
22-5% RN339
3 6
22-5%
RN337
3 6
22-5% RN337
4 5
22-5% RN337
1 8
22-5% RN337
2 7
22-5% RN250
3 6
22-5% RN250
2 7
22-5% RN249
3 6
22-5% RN336
4 5
22-5% RN250
1 8
22-5% RN249
2 7
22-5% RN248
3 6
22-5% RN250
4 5
22-5% RN249
1 8
22-5% RN248
2 7
22-5% RN247
3 6
22-5% RN249
4 5
22-5% RN248
1 8
22-5% RN247
2 7
22-5% RN336
3 6
22-5% RN247
1 8
22-5% RN248
4 5
22-5% RN247
4 5
22-5% RN244
3 6
22-5%
A_DQS8_1
A_SD8_2
A_DQS8_0
A_SD8_6
SUB*_4282E
SUB*_4282E
SUB*_4282E
SUB*_4282E
All 22 ohm Rpacks have been subbed
to 33 ohm Rpacks (Dell p/n 4282E)
to fix an SI issue found during
unit test
VTT_SSTL
2,3,5,6,8,10,12-14
12
+80%-20%
.22uF 16V
Place close to RN249
VTT_SSTL
2,3,5,6,8,10,12-14
12
+80%-20%
.22uF 16V
Place close to RN250
RN410
2 7
22-5% RN410
3 6
22-5% RN410
1 8
22-5% RN410
4 5
22-5%
VTT_SSTL
2,3,5,6,8,10,12-14
12
+80%-20%
.22uF 16V
Place close to RN410
VTT_SSTL
2,3,5,6,8,10,12-14
12
.22uF 16V
12
+80%-20%
+80%-20%
.22uF 16V
1
2
3
A DATA/STROBES END TERMINATION RESISTORS
COMPUTER CORPORATION
NC_ABUS1
4 5
AUSTIN,TEXAS
22-5% RN245
4 5
22-5% RN336
1 8
22-5%
A_SD8_7
A_SD6_6
SUB*_4282E
SUB*_4282E
RN244
2 7
22-5% RN336
2 7
22-5%
PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.
TITLE
SCHEM,MEM-CRD,6DIMM,PE4600
DWG NO.
8Y810
8/3/2004
A03
SHEET
8 OF 18
SUB*_4282E
A_SD7_3
SUB*_4282E
A_DQS6_1
SUB*_4282E
A B
DC
Page 9
B D
CA
8-3-2004_15:33
5-7,9,14
SSTLREF_D1
2
1
1
2
+80%-20%
.22uF 16V
2
1
+80%-20%
.22uF 16V
1
2
+80%-20%
.22uF 16V
+80%-20%
.22uF 16V
5-7,9,14
SSTLREF_D1
2
1
1
2
+80%-20%
.22uF 16V
2
1
+80%-20%
.22uF 16V
1
2
+80%-20%
.22uF 16V
+80%-20%
.22uF 16V
1
1
J5
J3
48 43 41
130
37 32
125
29
122
27 141 118 115
59
52
157 158 154
65
63
137 138
21 111
167
184
82
92
91 181 182 183
90
102 101
10
173 163
71
75
76
17
16 113 103
168 148 120 108
85
70
46
38
136 180 156 112 164 143 128 104
96 172
77
62
54
30
22
15
1 2
50V-20%
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
BA0 BA1
CS CS1 RAS CAS WE
CLK0_P CLK0_N
CLKE0 CLKE1
FETEN
1
VREF VDDSPD
VDDID SCL
SDA SA0 SA1 SA2 WP
NC1 NC2 RESET
9
NC4 NC5 CS3_NU CS2_NU CLK2_N_DU CLK2_P_DU CLK1_N_DU CLK1_P_DU BA2_NU A13_NU
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8
7
VDD10
VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16
.01UF
50V-20%
SUB*_78020
SUB*_78020
.01UF
1 2
50V-20%
1 2
DDR SDRAM DIMM
SUB*_726NT
Substitution for p/n consolidation
SUB*_78020
.01UF
SUB*_78020
1 2
50V-20%
.01UF
50V-20%
1 2
.01UF
SUB*_78020
1 2
50V-20%
DQS0
DM0_DQS9
D10 D11
DQS1
DM1_DQS10
D12 D13 D14 D15 D16 D17 D18 D19
DQS2
DM2_DQS11
D20 D21 D22 D23 D24 D25 D26 D27
DQS3
DM3_DQS12
D28 D29 D30 D31 D32 D33 D34 D35
DQS4
DM4_DQS13
D36 D37 D38 D39 D40 D41 D42 D43
DQS5
DM5_DQS14
D44 D45 D46 D47 D48 D49 D50 D51
DQS6
DM6_DQS15
D52 D53 D54 D55 D56 D57 D58 D59
DQS7
DM7_DQS16
D60 D61 D62
D63 ECC0 ECC1 ECC2 ECC3 DQS8
DM8_DQS17
ECC4 ECC5 ECC6 ECC7
SUB*_78020
.01UF
1 2
50V-20%
D0 D1 D2 D3
D4 D5 D6 D7 D8 D9
.01UF
SUB*_78020
1 2
50V-20%
2 4 6 8 5 97 94 95 98 99 12 13 19 20 14 107 105 106 109 110 23 24 28 31 25 119 114 117 121 123 33 35 39 40 36 129 126 127 131 133 53 55 57 60 56 149 146 147 150 151 61 64 68 69 67 159 153 155 161 162 72 73 79 80 78 169 165 166 170 171 83 84 87 88 86 177 174 175 178 179 44 45 49 51 47 140 134 135 142 144
SUB*_78020
.01UF
50V-20%
B_SD0_0 B_SD0_1 B_SD0_2 B_SD0_3 B_DQS0_0 B_DQS0_1 B_SD0_4 B_SD0_5 B_SD0_6 B_SD0_7 B_SD1_0 B_SD1_1 B_SD1_2 B_SD1_3 B_DQS1_0 B_DQS1_1 B_SD1_4 B_SD1_5 B_SD1_6 B_SD1_7 B_SD2_0 B_SD2_1 B_SD2_2 B_SD2_3 B_DQS2_0 B_DQS2_1 B_SD2_4 B_SD2_5 B_SD2_6 B_SD2_7 B_SD3_0 B_SD3_1 B_SD3_2 B_SD3_3 B_DQS3_0 B_DQS3_1 B_SD3_4 B_SD3_5 B_SD3_6 B_SD3_7 B_SD4_0 B_SD4_1 B_SD4_2 B_SD4_3 B_DQS4_0 B_DQS4_1 B_SD4_4 B_SD4_5 B_SD4_6 B_SD4_7 B_SD5_0 B_SD5_1 B_SD5_2 B_SD5_3 B_DQS5_0 B_DQS5_1 B_SD5_4 B_SD5_5 B_SD5_6 B_SD5_7 B_SD6_0 B_SD6_1 B_SD6_2 B_SD6_3 B_DQS6_0 B_DQS6_1 B_SD6_4 B_SD6_5 B_SD6_6 B_SD6_7 B_SD7_0 B_SD7_1 B_SD7_2 B_SD7_3 B_DQS7_0 B_DQS7_1 B_SD7_4 B_SD7_5 B_SD7_6 B_SD7_7 B_SD8_0 B_SD8_1 B_SD8_2 B_SD8_3 B_DQS8_0 B_DQS8_1 B_SD8_4 B_SD8_5 B_SD8_6 B_SD8_7
1 2
SUB*_78020
.01UF
50V-20%
3,6,9,10 3,6,9,10 3,6,9,10 3,6,9,10
3,6,9,10 3,6,9,10 3,6,9,10 3,6,9,10 3,6,9,10 3,6,9,10 3,6,9,10 3,6,9,10
3,6,9,10 3,6,9,10 3,6,9,10 3,6,9,10
SUB*_78020
.01UF
1 2
3,6,9,10 3,6,9,10
3,6,9,10 3,6,9,10
3,6,9,10 3,6,9,10 3,6,9,10 3,6,9,10
3,6,9,10 3,6,9,10 3,6,9,10 3,6,9,10
3,6,9,10 3,6,9,10 4,6,9,10 4,6,9,10
3,6,9,10
3,6,9,10 3,6,9,10 3,6,9,10 4,6,9,10 4,6,9,10
4,6,9,10 4,6,9,10 4,6,9,10 4,6,9,10
4,6,9,10 4,6,9,10 4,6,9,10 4,6,9,10
4,6,9,10 4,6,9,10 4,6,9,10 4,6,9,10
4,6,9,10 4,6,9,10 4,6,9,10 4,6,9,10
1 2
50V-20%
3,6,9,10 3,6,9,10
4,6,9,10 4,6,9,10
4,6,9,10 4,6,9,10
4,6,9,10 4,6,9,10 4,6,9,10 4,6,9,10
4,6,9,10
4,6,9,10 4,6,9,10 4,6,9,10 4,6,9,10 4,6,9,10
4,6,9,10 4,6,9,10 4,6,9,10 4,6,9,10
4,6,9,10
4,6,9,10 4,6,9,10 4,6,9,10 4,6,9,10 4,6,9,10
4,6,9,10 4,6,9,10 4,6,9,10 4,6,9,10
4,6,9,10
4,6,9,10 4,6,9,10 4,6,9,10 4,6,9,10 4,6,9,10
VCC25
.01UF
50V-20%
2-7,9,11,13,14,16
STAKE PIN FOR TEST
A_CS_3
2,7
2-7,9,11,13,14,16
VCC25
J16
130
125
122
141 118 115
157 158 154
137 138
111
167
184
181 182 183
102 101
173 163
113 103
168 148 120 108
136 180 156 112 164 143 128 104
172
1 2
48 43 41
37 32
29
27
59 52
65 63
21
82
92 91
90
10
71 75 76 17 16
85 70 46 38
96
77 62 54 30 22 15
1
9
7
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
BA0 BA1
CS CS1 RAS CAS WE
CLK0_P CLK0_N
CLKE0 CLKE1
FETEN VREF VDDSPD
VDDID SCL
SDA SA0 SA1 SA2 WP
NC1 NC2 RESET NC4 NC5 CS3_NU CS2_NU CLK2_N_DU CLK2_P_DU CLK1_N_DU CLK1_P_DU BA2_NU A13_NU
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD10
VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16
.01UF
1 2
50V-20%
SUB*_78020
.01UF
1 2
50V-20%
.01UF
50V-20%
DDR SDRAM DIMM
SUB*_726NT
SUB*_78020
.01UF
1 2
1 2
50V-20%
.01UF
50V-20%
DM0_DQS9
DM1_DQS10
DM2_DQS11
DM3_DQS12
DM4_DQS13
DM5_DQS14
DM6_DQS15
DM7_DQS16
DM8_DQS17
SUB*_78020
.01UF
1 2
50V-20%
1 2
D0 D1 D2 D3
DQS0
D4 D5 D6 D7 D8
D9 D10 D11
DQS1
D12 D13 D14 D15 D16 D17 D18 D19
DQS2
D20 D21 D22 D23 D24 D25 D26 D27
DQS3
D28 D29 D30 D31 D32 D33 D34 D35
DQS4
D36 D37 D38 D39 D40 D41 D42 D43
DQS5
D44 D45 D46 D47 D48 D49 D50 D51
DQS6
D52 D53 D54 D55 D56 D57 D58 D59
DQS7
D60 D61 D62 D63
ECC0 ECC1 ECC2 ECC3 DQS8
ECC4 ECC5 ECC6 ECC7
.01UF
1 2
50V-20%
2 4 6 8 5 97 94 95 98 99 12 13 19 20 14 107 105 106 109 110 23 24 28 31 25 119 114 117 121 123 33 35 39 40 36 129 126 127 131 133 53 55 57 60 56 149 146 147 150 151 61 64 68 69 67 159 153 155 161 162 72 73 79 80 78 169 165 166 170 171 83 84 87 88 86 177 174 175 178 179 44 45 49 51 47 140 134 135 142 144
2,6,9,12 2,6,9,12 2,6,9,12 2,6,9,12 2,6,9,12 2,6,9,12 2,6,9,12 2,6,9,12 2,6,9,12 2,6,9,12
R1_MA10
2,7 2,6,9,12 2,6,9,12
NP*
1
11 11
2,6,9,12
NC_FETEN_J3
5-7,9,14
5-7,9,13 3-7,9,13
2-7,9,11,13,14,16
22uF 10V
1
2
ASCLK_2P5V ASDATA_2P5V
5-7,9,13
2-7,9,11,13,14,16
BE USED ON NEW DESIGNS.
BE USED ON NEW DESIGNS.
THIS PART IS NOT TO
SUB*_780201
22uF 10V
1
2
SSTLREF_D1
NC_WP_J3
NC_NC1_J3 NC_NC2_J3 A_RESET NC_NC4_J3 NC_NC5_J3 NC_CS3_J3
NC_CS2_J3 NC_CLK2_N_J3 NC_CLK2_P_J3 NC_CLK1_N_J3 NC_CLK1_P_J3 NC_BA2_J3 NC_A13_J3
VCC25
VCC25
THIS PART IS NOT TO
R1_BA0_0
2,7
R1_BA1_0
2,7
A_CS_2
2,7
R1_RAS_0
2,7
R1_CAS_0
2,7
R1_WE_0
2,7
CLK_J3_P CLK_J3_N
B_CKE
NC_VDDID_J3
Substitution for p/n consolidation
.01UF
1 2
B_MA0 B_MA1 B_MA2 B_MA3 B_MA4 B_MA5 B_MA6 B_MA7 B_MA8 B_MA9
B_MA11 B_MA12
1 2
50V-20%
SUB*_78020
.01UF
50V-20%
B_SD0_0 B_SD0_1 B_SD0_2 B_SD0_3 B_DQS0_0 B_DQS0_1 B_SD0_4 B_SD0_5 B_SD0_6 B_SD0_7 B_SD1_0 B_SD1_1 B_SD1_2 B_SD1_3 B_DQS1_0 B_DQS1_1 B_SD1_4 B_SD1_5 B_SD1_6 B_SD1_7 B_SD2_0 B_SD2_1 B_SD2_2 B_SD2_3 B_DQS2_0 B_DQS2_1 B_SD2_4 B_SD2_5 B_SD2_6 B_SD2_7 B_SD3_0 B_SD3_1 B_SD3_2 B_SD3_3 B_DQS3_0 B_DQS3_1 B_SD3_4 B_SD3_5 B_SD3_6 B_SD3_7 B_SD4_0 B_SD4_1 B_SD4_2 B_SD4_3 B_DQS4_0 B_DQS4_1 B_SD4_4 B_SD4_5 B_SD4_6 B_SD4_7 B_SD5_0 B_SD5_1 B_SD5_2 B_SD5_3 B_DQS5_0 B_DQS5_1 B_SD5_4 B_SD5_5 B_SD5_6 B_SD5_7 B_SD6_0 B_SD6_1 B_SD6_2 B_SD6_3 B_DQS6_0 B_DQS6_1 B_SD6_4 B_SD6_5 B_SD6_6 B_SD6_7 B_SD7_0 B_SD7_1 B_SD7_2 B_SD7_3 B_DQS7_0 B_DQS7_1 B_SD7_4 B_SD7_5 B_SD7_6 B_SD7_7 B_SD8_0 B_SD8_1 B_SD8_2 B_SD8_3 B_DQS8_0 B_DQS8_1 B_SD8_4 B_SD8_5 B_SD8_6 B_SD8_7
SUB*_78020
.01UF
1 2
50V-20%
.01UF
50V-20%
1 2
3,6,9,10 3,6,9,10 3,6,9,10 3,6,9,10
3,6,9,10 3,6,9,10 3,6,9,10 3,6,9,10 3,6,9,10 3,6,9,10 3,6,9,10 3,6,9,10
3,6,9,10 3,6,9,10 3,6,9,10 3,6,9,10
3,6,9,10 3,6,9,10 3,6,9,10 3,6,9,10
3,6,9,10 3,6,9,10 3,6,9,10 3,6,9,10
3,6,9,10 3,6,9,10 4,6,9,10 4,6,9,10
3,6,9,10 3,6,9,10 4,6,9,10 4,6,9,10
SUB*_78020
.01UF
50V-20%
3,6,9,10 3,6,9,10
3,6,9,10 3,6,9,10
3,6,9,10 3,6,9,10
3,6,9,10 3,6,9,10
4,6,9,10 4,6,9,10 4,6,9,10 4,6,9,10
4,6,9,10
4,6,9,10 4,6,9,10 4,6,9,10 4,6,9,10 4,6,9,10
4,6,9,10 4,6,9,10 4,6,9,10 4,6,9,10
4,6,9,10
4,6,9,10 4,6,9,10 4,6,9,10 4,6,9,10 4,6,9,10
4,6,9,10 4,6,9,10 4,6,9,10 4,6,9,10
4,6,9,10 4,6,9,10 4,6,9,10 4,6,9,10
4,6,9,10 4,6,9,10 4,6,9,10 4,6,9,10
4,6,9,10 4,6,9,10 4,6,9,10 4,6,9,10
VCC25
1 2
4,6,9,10 4,6,9,10
4,6,9,10 4,6,9,10
4,6,9,10 4,6,9,10 4,6,9,10 4,6,9,10
4,6,9,10
4,6,9,10 4,6,9,10 4,6,9,10 4,6,9,10 4,6,9,10
.01UF
50V-20%
2
3
2-7,9,11,13,14,16
2
3
STAKE PIN FOR TEST
A_CS_5
2,7
J22
NP*
1
2-7,9,11,13,14,16
NC_FETEN_J5
VCC25
5-7,9,13 3-7,9,13
5-7,9,13
2-7,9,11,13,14,16
2-7,9,11,13,14,16
BE USED ON NEW DESIGNS.
THIS PART IS NOT TO
SUB*_78020
22uF 10V
1
2
22uF 10V
2
B_MA11 B_MA12
.01UF
50V-20%
B_MA0 B_MA1 B_MA2 B_MA3 B_MA4 B_MA5 B_MA6 B_MA7 B_MA8 B_MA9
SUB*_78020
1 2
2,6,9,12 2,6,9,12 2,6,9,12 2,6,9,12 2,6,9,12 2,6,9,12 2,6,9,12 2,6,9,12 2,6,9,12 2,6,9,12
R2_MA10
2,7 2,6,9,12 2,6,9,12
R2_BA0_0
2,7
R2_BA1_0
2,7
A_CS_4
2,7
R2_RAS_0
2,7
R2_CAS_0
2,7
R2_WE_0
2,7
CLK_J5_P
11
CLK_J5_N
11
2,6,9,12
5-7,9,14
ASCLK_2P5V ASDATA_2P5V
NC_CLK2_N_J5 NC_CLK2_P_J5 NC_CLK1_N_J5 NC_CLK1_P_J5
VCC25
VCC25
BE USED ON NEW DESIGNS.
THIS PART IS NOT TO
B_CKE
SSTLREF_D1
NC_VDDID_J5
NC_WP_J5
NC_NC1_J5 NC_NC2_J5 A_RESET NC_NC4_J5
NC_NC5_J5 NC_CS3_J5 NC_CS2_J5
NC_BA2_J5 NC_A13_J5
1 2
SUB*_78020
.01UF
4 4
SUB*_78020
SUB*_78020
SUB*_78020
SUB*_78020
SUB*_78020
SUB*_78020
J3 & J5
A B
Put one 22 uF cap at each end of DIMM
PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.
TITLE
SCHEM,MEM-CRD,6DIMM,PE4600
DWG NO.
DC
8Y810
8/3/2004
COMPUTER CORPORATION
AUSTIN,TEXAS
A03
SHEET
9 OF 18
Page 10
B D
VTT_SSTL
2,3,5,6,8,10,12-14
VTT_SSTL
2,3,5,6,8,10,12-14
RN287
1 8
1
2
3
12
+80%-20%
.22uF 16V
Place close to RN288
VTT_SSTL
2,3,5,6,8,10,12-14
12
+80%-20%
.22uF 16V
Place close to RN287
VTT_SSTL
2,3,5,6,8,10,12-14
12
+80%-20%
.22uF 16V
Place close to RN286
VTT_SSTL
2,3,5,6,8,10,12-14
12
+80%-20%
.22uF 16V
Place close to RN358
22-5% RN288
1 8
22-5% RN287
4 5
22-5% RN287
3 6
22-5% RN287
2 7
22-5% RN288
2 7
22-5% RN288
4 5
22-5% RN288
3 6
22-5%
RN286
2 7
22-5% RN286
3 6
22-5% RN286
4 5
22-5% RN286
1 8
22-5% RN285
2 7
22-5% RN285
3 6
22-5% RN285
4 5
22-5% RN285
1 8
22-5%
RN284
2 7
22-5% RN283
1 8
22-5% RN284
3 6
22-5% RN284
4 5
22-5% RN284
1 8
22-5% RN283
2 7
22-5% RN283
3 6
22-5% RN283
4 5
22-5% RN282
1 8
22-5% RN282
2 7
22-5% RN282
3 6
22-5% RN282
4 5
22-5% RN281
1 8
22-5% RN281
2 7
22-5% RN281
3 6
22-5% RN281
4 5
22-5% RN358
2 7
22-5% RN358
1 8
22-5% RN358
4 5
22-5% RN358
3 6
22-5%
4 4
B_DQS0_1
SUB*_4282E
B_SD0_4
SUB*_4282E
B_SD0_2
SUB*_4282E
B_SD0_6
SUB*_4282E
B_DQS0_0
SUB*_4282E
B_SD0_0
SUB*_4282E
B_SD0_1
SUB*_4282E
B_SD0_5
SUB*_4282E
B_SD1_5
SUB*_4282E
B_DQS1_0
SUB*_4282E
B_DQS1_1
SUB*_4282E
B_SD1_1
SUB*_4282E
B_SD1_7
SUB*_4282E
B_SD1_2
SUB*_4282E
B_SD1_3
SUB*_4282E
B_SD1_6
SUB*_4282E
B_SD2_0
SUB*_4282E
B_SD2_5
SUB*_4282E
B_SD2_1
SUB*_4282E
B_DQS2_0
SUB*_4282E
B_SD2_4
SUB*_4282E
B_DQS2_1
SUB*_4282E
B_SD2_2
SUB*_4282E
B_SD2_6
SUB*_4282E
B_SD3_5
SUB*_4282E
B_SD3_1
SUB*_4282E
B_DQS3_0
SUB*_4282E
B_DQS3_1
SUB*_4282E
B_SD3_6
SUB*_4282E
B_SD3_2
SUB*_4282E
B_SD3_3
SUB*_4282E
B_SD3_7
SUB*_4282E
B_SD4_4
SUB*_4282E
B_SD4_0
SUB*_4282E
B_SD4_5
SUB*_4282E
B_SD4_1
SUB*_4282E
RN289
2 7
22-5% RN289
4 5
22-5% RN289
3 6
22-5% RN289
1 8
22-5% RN269
2 7
22-5% RN269
3 6
22-5% RN269
4 5
22-5% RN269
1 8
22-5% RN357
3 6
22-5% RN357
4 5
22-5% RN357
2 7
22-5% RN357
1 8
22-5%
B_SD5_1
SUB*_4282E
B_DQS5_1
SUB*_4282E
B_DQS5_0
SUB*_4282E
B_SD5_5
SUB*_4282E
B_SD4_3
SUB*_4282E
B_SD5_0
SUB*_4282E
B_SD5_4
SUB*_4282E
B_SD4_7
SUB*_4282E
B_DQS4_1
SUB*_4282E
B_SD4_6
SUB*_4282E
B_SD4_2
SUB*_4282E
B_DQS4_0
SUB*_4282E
VTT_SSTL
2,3,5,6,8,10,12-14
12
+80%-20%
.22uF 16V
Place close to RN269
RN271
3 6
22-5% RN271
4 5
22-5% RN271
1 8
22-5% RN271
2 7
22-5% RN270
3 6
22-5% RN270
4 5
22-5% RN270
1 8
22-5% RN270
2 7
22-5% RN267
3 6
22-5% RN267
4 5
22-5% RN267
1 8
22-5% RN267
2 7
22-5% RN272
3 6
22-5% RN272
4 5
22-5% RN272
1 8
22-5% RN272
2 7
22-5% RN273
1 8
22-5% RN273
2 7
22-5% RN273
4 5
22-5% RN273
3 6
22-5% RN274
1 8
22-5% RN274
2 7
22-5% RN274
3 6
22-5% RN274
4 5
22-5% RN268
3 6
22-5% RN268
4 5
22-5% RN268
1 8
22-5% RN268
2 7
22-5% RN354
4 5
22-5% RN354
2 7
22-5% RN356
4 5
22-5% RN356
2 7
22-5% RN354
3 6
22-5% RN353
4 5
22-5% RN354
1 8
22-5% RN353
2 7
22-5% RN356
3 6
22-5% RN356
1 8
22-5% RN353
3 6
22-5% RN353
1 8
22-5% RN355
3 6
22-5% RN355
4 5
22-5% RN355
1 8
22-5% RN355
2 7
22-5%
SUB*_4282E
B_SD1_0
SUB*_4282E
B_SD1_4
SUB*_4282E
B_SD0_7
SUB*_4282E
B_SD0_3
SUB*_4282E
B_SD3_0
SUB*_4282E
B_SD3_4
SUB*_4282E
B_SD2_7
SUB*_4282E
B_SD2_3
SUB*_4282E
B_SD8_0
SUB*_4282E
B_SD8_1
SUB*_4282E
B_SD8_4
SUB*_4282E
B_SD8_5
SUB*_4282E
B_SD8_2
SUB*_4282E
B_SD8_6
SUB*_4282E
B_DQS8_0
SUB*_4282E
B_DQS8_1
SUB*_4282E
B_SD8_3
SUB*_4282E
B_SD8_7
SUB*_4282E
NC_RN273_5
SUB*_4282E
NC_RN273_6
SUB*_4282E
B_DQS7_0
SUB*_4282E
B_SD7_7
SUB*_4282E
B_SD7_2
SUB*_4282E
B_SD7_3
SUB*_4282E
B_DQS7_1
SUB*_4282E
B_SD7_6
SUB*_4282E
B_SD7_5
SUB*_4282E
B_SD7_1
SUB*_4282E
B_SD7_0
SUB*_4282E
B_SD6_3
SUB*_4282E
B_SD6_7
SUB*_4282E
B_SD6_6
SUB*_4282E
B_SD7_4
SUB*_4282E
B_SD6_5
SUB*_4282E
B_SD6_2
SUB*_4282E
B_SD6_1
SUB*_4282E
B_DQS6_0
SUB*_4282E
B_DQS6_1
SUB*_4282E
B_SD6_4
SUB*_4282E
B_SD6_0
SUB*_4282E
B_SD5_6
SUB*_4282E
B_SD5_7
SUB*_4282E
B_SD5_2
SUB*_4282E
B_SD5_3
PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.
VTT_SSTL
12
Place close to RN271
VTT_SSTL
Place close to RN268
VTT_SSTL
12
Place close to RN356
VTT_SSTL
2,3,5,6,8,10,12-14
12
Place close to RN355
CA
2,3,5,6,8,10,12-14
+80%-20%
.22uF 16V
2,3,5,6,8,10,12-14
12
+80%-20%
.22uF 16V
2,3,5,6,8,10,12-14
+80%-20%
.22uF 16V
+80%-20%
.22uF 16V
B DATA/STROBE END TERMINATION RESISTORS
TITLE
SCHEM,MEM-CRD,6DIMM,PE4600
DWG NO.
8Y810
8-3-2004_15:33
1
2
3
COMPUTER CORPORATION
AUSTIN,TEXAS
A03
SHEET
10 OF 188/3/2004
A B
DC
Page 11
1
Jaguar 2.0 Change: Causes problems - added pullups to PLL I2C lines, and disconnected from I2C
VCC25
2-7,9,11,13,14,16
L13
NEED 3.3V FOR I2C
6.3V-10%
4.7uF
1
2
Jaguar 2.0 Change: Improved design - moved C132 from pin 1 to pin 2 of L13 for better power plane
21
0.1uF 16V C132
12
6.3V-10%
L12
4.7uF
1
2
FBOUT0_N
11
FBOUT0_P
11
21
2,5 2,5
1 2
ASDATA_3P3V ASCLK_3P3V
1 2
3300pF
3300pF
50V-10%
2,11,13,14,16
2-7,9,11,13,14,16
1 2
100-1%
1 2
50V-10%
VCC33
VCC25
1 2 NP*
0.1uF 16V
21
1 2
NP*
390pF
50V-10%
1 2
1 2
0.1uF 16V
1 2
1 2
VCC33
2,11,13,14,16
8.2K-5%
1 2
1 2
0.1uF 16V
NP*
8.2K-5%
2 2
CLKIN0_P CLKIN0_N
B D
1 2
100-1%
1 2
100-1%
11
11
CLK8_P
CLK8_N
13
CLKIN_P
14
CLKIN_N
35
FBIN_N
36
FBIN_P
37
SDA
12
SCK
16
17
4
VDDQ0
11
VDDQ1
15
I2CVDD
21
VDDQ3
28
VDDQ4
34
VDDQ5
38
VDDQ6
45
VDDQ7
1
7
8
18
24
25
31
41
42
48
U8
CLK0_P CLK0_N
CLK1_P CLK1_N
CLK2_P CLK2_N
CLK3_P CLK3_N
CLK4_P CLK4_N
CLK5_P CLK5_N
CLK6_P CLK6_N
CLK7_P CLK7_N
CLK8_P CLK8_N
CLK9_P CLK9_N
FBOUT_P FBOUT_N
2.5V PLL CLOCK DRIVER
CLK_J1_P
3
CLK_J1_N
2
CLK_J2_P
5
CLK_J2_N
6
CLK_J3_P
10
CLK_J3_N
9
CLK_J4_P
20
CLK_J4_N
19
CLK_J5_P
22
CLK_J5_N
23
CLK_J6_P
46
CLK_J6_N
47
44 43
39 40
29 30
27 26
32 33
CLKDP1_PR CLKDP1_NR
CLKDP0_PR CLKDP0_NR
HDR_CLK_P HDR_CLK_N
FBOUT0_PR FBOUT0_NR
CLK8_P CLK8_N
CLKDP0_N
3,11
CLKDP1_N
4,11
6 6
5 5
9 9
7 7
9 9
7 7
11 11
11 11
11 11
11 11
PLACE CLOSE TO REMCs
J28
1 2
1
100-1%
1
J29
NP*
HEADER FOR LOGIC ANALYZER CLOCK
NP*
CA
CLKDP0_P
CLKDP1_P
1 2
3,11
4,11
100-1%
8-3-2004_15:33
1
2
CLKDP1_NR
11
OVERLAP RESISTOR PADS AS MUCH AS POSSIBLE
OVERLAP RESISTOR PADS AS MUCH AS POSSIBLE
LOOP 1 IS THE SHORT LOOP (1 inches) LOOP 2 IS THE LONG LOOP (2 inches)
1 2
1 2 NP*
1 2
CLKDP1_N_LOOP_CONNECT
Jaguar 2.0 Change: Improved design - need to keep separate GND, AGND vias for PLL - to reduce jitter
OVERLAP RESISTOR PADS AS MUCH AS POSSIBLE
2
LOOP 1 IS THE SHORT LOOP (1 inches) LOOP 2 IS THE LONG LOOP (2 inches)
CLKDP1_N_LOOP2CLKDP1_N_LOOP1
CLKDP0_N_LOOP1CLKDP0_N_LOOP2
1 2
NP*
1 2
1 2
NP*
CLKDP1_N
4,11
CLKDP0_NR
11
1 2
NP*
1 2
1 2
NP*
CLKDP0_N_LOOP_CONNECT
1 2
1 2
NP*
1 2
CLKDP0_N
3,11
3
CLKDP1_PR
11
LOOP 1 IS THE SHORT LOOP (1 inches) LOOP 2 IS THE LONG LOOP (2 inches)
CLKDP1_P_LOOP1
1 2
1 2 NP*
1 2
CLKDP1_P_LOOP_CONNECT
CLKDP1_P_LOOP2
1 2
NP*
1 2
1 2
NP*
CLKDP1_P
4,11
CLKDP0_PR
11
OVERLAP RESISTOR PADS AS MUCH AS POSSIBLE LOOP 1 IS THE SHORT LOOP (1 inches)
LOOP 2 IS THE LONG LOOP (2 inches)
CLKDP0_P_LOOP1
1 2
1 2
NP*
1 2
CLKDP0_P_LOOP_CONNECT
CLKDP0_P_LOOP2
1 2
NP*
1 2
1 2
NP*
CLKDP0_P
3
3,11
FBOUT0_PR
11
OVERLAP RESISTOR PADS AS MUCH AS POSSIBLE
FBOUT0_P_LOOP1
1 2
NP*
1 2
1 2
NP*
FBOUT0_P_LOOP_CONNECT
FBOUT0_P_LOOP2
1 2
1 2
1 2
NP*
FBOUT0_P
LOOP LENGTHS FINE AS THEY ARE -
DO NOT CHANGE LENGTHS
11
OVERLAP RESISTOR PADS AS MUCH AS POSSIBLE
FBOUT0_N_LOOP1
4 4
1 2
NP*
FBOUT0_N_LOOP_CONNECT
FBOUT0_NR
11
1 2
NP*
1 2
FBOUT0_N_LOOP2
1 2
1 2
1 2
NP*
FBOUT0_N
11
PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.
CLOCK BUFFER
COMPUTER CORPORATION
TITLE
SCHEM,MEM-CRD,6DIMM,PE4600
DWG NO.
8Y810
8/3/2004
AUSTIN,TEXAS
A03
SHEET
11 OF 18
A B
DC
Page 12
B D
CA
8-3-2004_15:33
1
2
B_MA4
NC_RN46_2
A_MA1
B_MA2
A_MA2
B_MA3
A_MA8
B_MA11
B_MA9
A_MA7
B_MA7
B_MA0
A_MA0
2 7
51 OHM-5%
2 7
51 OHM-5%
1 8
51 OHM-5%
2 7
51 OHM-5%
3 6
51 OHM-5%
4 5
51 OHM-5%
21
51
4 5
51 OHM-5%
3 6
51 OHM-5%
2 7
51 OHM-5%
1 8
51 OHM-5%
4 5
51 OHM-5%
3 6
51 OHM-5%
VTT_SSTL
2,3,5,6,8,10,12-14
A_MA6
A_MA4
A_MA3
B_MA8
A_MA5
B_MA5
B_MA6
A_MA12
B_MA12
A_MA11
A_MA9
RCMD1
2-4
RCMD3
2-4
RCMD0
2-4
RCMD2
2-4
SDOE
2-4
B_MA1
4 5
51 OHM-5%
3 6
51 OHM-5%
1 8
51 OHM-5%
4 5
51 OHM-5%
3 6
51 OHM-5%
2 7
51 OHM-5%
1 8
51 OHM-5%
4 5
51 OHM-5%
3 6
51 OHM-5%
2 7
51 OHM-5%
1 8
51 OHM-5%
RN411
1 8
51 OHM-5%
RN411
2 7
51 OHM-5%
RN411
3 6
51 OHM-5%
RN411
4 5
51 OHM-5%
51
21
51
VTT_SSTL
2,3,5,6,8,10,12-14
1
2
21
NC_RN46_1
B_CKE
A_DQS5_0
SUB*_4282E
1 8
51 OHM-5%
51
4 5
22-5%
21
A_CKE
21
51
3
A_SD5_5
A_DQS5_1
A_SD5_1
SUB*_4282E
SUB*_4282E
SUB*_4282E
1 8
22-5%
3
3 6
22-5%
2 7
22-5%
4 4
ADDRESS END TERMINATION
COMPUTER CORPORATION
AUSTIN,TEXAS
TITLE
SCHEM,MEM-CRD,6DIMM,PE4600
PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.
A B
DWG NO.
DC
8Y810
8/3/2004
A03
SHEET
12 OF 18
Page 13
B D
CA
8-3-2004_15:33
1
1
1
1
1
NP*
1
NP*
NP*
NP*
NP*
J30
J31
J32
J33
J34
SP_VCC33_PU1 SP_VCC33_PU2
SP_VCC33_PU3 SP_VCC33_PU4
NP*
NP*
VCC33
1 2
VCC33
1 2
2,11,13,14,16
8.2K-5%
1 2
2,11,13,14,16
8.2K-5%
1 2
8.2K-5%
NP*
8.2K-5%
NP*
40RD20
40RD20
WH1
WH2
NC_WH1
NC_WH2
VCC25
2-7,9,11,13,14,16
NP*
SP_HC126_5 NC_HC126_6
VCC25
2-7,9,11,13,14,16
U95
14
74HC126
4
65
ENSURES BOTH SIDES OF MEM CARD ARE PLUGGED IN
MEM_PRES0
2
1 2
FRU I2C ADDRESS = ACh
MEM_PRES1
2
1
VCC33
2,11,13,14,16
1E161 does not have Xicor on ASL
2
GND STAKES FOR PROTO ONLY
RESET
2
VCC25
2-7,9,11,13,14,16
1 2
0.1uF 16V
VCC25
2-7,9,11,13,14,16
14
1 2
74LVC32A
VCC25
2-7,9,11,13,14,16
14
4 5
74LVC32A
U23
U23
9K205 is programmed p/n, 1E161 is blank p/n
VTT_SSTL
2,3,5,6,8,10,12-14
NP*
3
SRESET
3,4
SP_VTT_PU1
1 2
8.2K-5%
1 2
NP*
8.2K-5%
SP_VTT_PU2
VTT_SSTL
2,3,5,6,8,10,12-14
6
A_RESET
NP*
1 2
8.2K-5%
1 2
NP*
8.2K-5%
SP_HC126_12
SP_VTT_PU3 SP_VTT_PU4
150-5%
1 2
1 2
NP*
SP_HC126_9
NP*
150-5%
VCC25
VCC25
1 2
VCC25
2-7,9,11,13,14,16
NP*
2-7,9,11,13,14,16
U95
14
74HC126
10
1 2
89
VCC25
2-7,9,11,13,14,16
NP*
2-7,9,11,13,14,16
U95
14
74HC126
13
NP*
8.2K-5%
NP*
8.2K-5%
1112
NC_HC126_8
NC_HC126_11
1 2
1K-5%
1 2
1K-5%
1 2
150-5%
FRU_A0 FRU_A1 FRU_A2
U12
1
A0
2
A1
3 6
A2 SCL
4
GND1
SUB*_9K205
GND2
24C02
VCC
SDA
8 7
ENV_SCL
5
ENV_SDA
2,13 2,13
VCC33
2,11,13,14,16
1 2
0.1uF 16V
2
PD_74LVC32A_9
PD_74LVC32A_10
1 2
150-5%
1 2
150-5%
PD_74LVC32A_12
PD_74LVC32A_13
1 2
150-5%
VCC25
9
10
74LVC32A
VCC25
12 13
74LVC32A
2-7,9,11,13,14,16
14
U23
8
2-7,9,11,13,14,16
14
U23
11
NC_74LVC32A_8
NC_74LVC32A_11
SP_VCC25_PU1 SP_VCC25_PU2
SP_VCC25_PU3 SP_VCC25_PU4
NP*
NP*
1 2
VCC25
1 2
VCC25
2-7,9,11,13,14,16
8.2K-5%
1 2
2-7,9,11,13,14,16
8.2K-5%
1 2
8.2K-5%
NP*
8.2K-5%
NP*
1 2
150-5%
NP*
1 2
NP*
8.2K-5%
ADD*_42610_BAR ADD*_42753_REV
ADD*_8Y810_SCHEM ADD*_8Y811_PWB ADD*_8Y809_ASSYDRW
DEPOP SINCE PULLED UP ON PLANAR
ENV_SCL ENV_SDA
2,13 2,13
ASCLK_2P5V ASDATA_2P5V
NP*
NP*
VCC33
1 2
VCC25
1 2
2,11,13,14,16
NP*
8.2K-5%
2-7,9,11,13,14,16
8.2K-5%
1 2
1 2
8.2K-5%
NP*
8.2K-5%
3
1 2
150-5%
1 2
150-5%
SPARE GATES
Impedance coupons
Draw silkscreen box around vias only on one side. Label vias with the net name on the silkscreen box side only.
The label should be by the pin on the coupon.
2,13
ENV_SDA
Place at end of each I2C bus
3
TEMP SENSOR
VCC33
2,11,13,14,16
1 2
0.1uF 16V
U28
1
SDA
VCC
8
VCC33
2,11,13,14,16
1 2
VCC33
1 2
1K-5%
2,11,13,14,16
1 2
GNDPAD
300X175
1K-5%
MH3
MH6
IMPEDENCE
TEST POINT
MH7
1 2 3 4
1 2 3 4
INNER1_DIFF_P INNER1_DIFF_N
TOP_DIFF_P TOP_DIFF_N
4 4
IMPEDENCE
TEST POINT
V1 V2 V3 V4
V5 V6 V7 V8
IMPEDENCE
TEST POINT
MH5
IMPEDENCE
TEST POINT
GND
SIG
GND
SIG
MH1
1
2
1
2
TOP_SE
INNER1_SE
1
GND
2
SIG
IMPEDENCE
TEST POINT
1
GND
2
SIG
IMPEDENCE
TEST POINT
GND
SIG
IMPEDENCE
TEST POINT
IMPEDENCE
TEST POINT
1
2
BTM_SE
1 2 3 4
BTM_DIFF_P BTM_DIFF_N
1
GND
2
SIG
IMPEDENCE
TEST POINT
1
2
3
4
IMPEDENCE
TEST POINT
2,13
0C085 is 3.3V flavor of LM75
ENV_SCL
NC_LM75_OS
LM75 I2C ADDRESS = 9Ch
2
SCL
3
OS
4
GND
SUB*_0C085
A0
A1
A2
TEMP_A0
7
TEMP_A1
6
TEMP_A2
5
1 2
Pad to connect to chassis gnd
150-5%
ESM3 & MISC & SPARES & WIRE HOLES
COMPUTER
V9
INNER2_DIFF_P
1
1
INNER2_SE
1
CORPORATION
V10
INNER2_DIFF_N
2
2
NC_MH1_2
NC_MH12_2
2
AUSTIN,TEXAS
V11 V12
VCC25
3
4
IMPEDENCE
3 4
VCC25
3 4
TITLE
SCHEM,MEM-CRD,6DIMM,PE4600
TEST POINT
2-7,9,11,13,14,16
IMPEDENCE
TEST POINT
2-7,9,11,13,14,16
IMPEDENCE
TEST POINT
PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.
DWG NO.
8Y810
SHEET
A03
8/3/2004 13 OF 18
A B
DC
Page 14
B D
CA
8-3-2004_15:33
1
21
220pF
50V-10%
VCC25
21
220pF
2-7,9,11,13,14,16
100-1%
1 2
50V-10%
1 2
100-1%
SSTLREF_R1
21
1uF
10V-10%
VCC25
2-7,9,11,13,14,16
VCC25
2-7,9,11,13,14,16
VTT_SSTL
2,3,5,6,8,10,12-14
3
21
220pF
21
50V-10%
1 2
220pF
50V-10%
100-1%
1 2
100-1%
SSTLREF_R2
21
1uF
10V-10%
4,14
21
220pF
50V-10%
21
1 2
220pF
50V-10%
100-1%
1 2
100-1%
SSTLREF_D1
21
1uF
10V-10%
6.3V-20%
+
150uF
1 2
6.3V-20%
+
150uF
1 2
6.3V-20%
+
150uF
1 2
1
Place close to REMCs
PWM CONTROLLER SOLE SOURCED DUE TO NEED TO SINK CURRENT
Jaguar 2.0 Change: Reduced bulk capacitance from 330 to 150uF
ROOM=VTT_SSTL
2
ECAD: Connect to VTT_SSTL near RN339
2,3,5,6,8,10,12-14
4,14
VTT_SSTL
SSTLREF_R2
1 2
8.2K-5%
1 2
8.2K-5%
U10_VI+
U10_VI-
U97_VCC
3
+
2
-
4
V G
11
1 2
1 2
0.1uF 16V
U97
LM324,SM
U10_VO
1
1 2
0.1uF 16V
100K-1%
VCC12_VTT
2,14
21
2
14
VTT_PWRGD VTT_SS
VCC33
2,11,13,14,16
1 2
1K-5%
VCC33
2,11,13,14,16
1 2
VCC12_VTT
2.2K-5%
2,14
21
23.7K-1%
16V-20%
270uF
+
1 2
U96
1
VCC
2
3
VSS
4
PWRGD
5
OUTEN
6
12V_IN
15W-6A DC-DC
VERTICAL MODULE
SUB*_2R515
Non - Populated C755 added for X01
6.3V-10%
4V-20%
820uF
+
1 2
NP*
4V-20%
820uF
+
0.1uF 16V
1 2
NP*
Jaguar 2.0: Some of these caps were already there on 747JN - may have different REFDES - keep these same during ECAD
1
2
6.3V-10%
4.7uF
21
ECAD: Place VRM as per Mech Engg drawing specs
4.7uF
21
VTT_SSTL
2,3,5,6,8,10,12-14
2
3
2,14
VCC12_VTT
21
1uF
16V-10%
21
1uF
16V-10%
ECAD: Place C752 near pin 6 of VRM.
Jaguar 2.0 Change: Replaced U31 L6911B (EOL) with Vertical DC-DC Module U96
Spares
U97_VCC
V G
4
11
U97
LM324,SM
8
12
13
+
-
U97
4
V G
LM324,SM
7
11
5
+
6
-
10
+
9
-
V G
4
11
U97
LM324,SM
14
3
VIN = 12V VOUT = 1.25V
VOUT MAX CURRENT = 5 A
2
VTT_START
VCC33
2,11,13,14,16
1 2
21
1K-5%
NP*
12
NP*
Q11
2N7002
1 2
VTT_SS
D
3
1
G
S
2
NP*
1 2
NP*
2.2K-5%
14
1K-5%
1 2
1 2
1K-5%
1 2
1 2
1 2
0-5%0-5%0-5%
1K-5%
100K-1%
NP*
Jaguar 2.0 Change: Added FET and pullup/down since leaky diode degrades softstart
4 4
X02: Depop Q10 and Q11, else new risers will not work with old MB's
VREF, VTT GENERATION
Padstacks on 820 uF and 270 uF thru hole
COMPUTER CORPORATION
AUSTIN,TEXAS
cap symbols changed to new thermal relief
TITLE
SCHEM,MEM-CRD,6DIMM,PE4600
PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.
DWG NO.
8Y810
8/3/2004
A03
SHEET
14 OF 18
A B
DC
Page 15
B D
CA
8-3-2004_15:33
1
2
3
CMD10
2
CMD18
2
CMD17
2
CMD21
2
CMD14
2
CMD11
2
CMD12
2
CMD22
2
CMD19
2
CMD16
2
CMD23
2
CMD61
2
CMD57
2
CMD63
2
CMD56
2
CMD51
2
CMD50
2
CMD48
2
CMD49
2
CMD43
2
CMD40
2
CMD46
2
CMD41
2
CMD60
2
CMD58
2
CMD62
2
CMD59
2
CMD20
2
MECC6
2
MECC7
2
MECC5
2
MECC4
2
CMD52
2
CMD53
2
CMD55
2
CMD54
2
RN379
4 5
39 OHM-5%
RN371
1 8
39 OHM-5%
RN371
2 7
39 OHM-5%
RN371
3 6
39 OHM-5%
RN379
1 8
39 OHM-5%
RN379
2 7
39 OHM-5%
RN379
3 6
39 OHM-5%
RN377
4 5
39 OHM-5%
RN377
3 6
39 OHM-5%
RN377
2 7
39 OHM-5%
RN377
1 8
39 OHM-5%
RN376
4 5
39 OHM-5%
RN376
3 6
39 OHM-5%
RN376
2 7
39 OHM-5%
RN376
1 8
39 OHM-5%
RN375
4 5
39 OHM-5%
RN375
3 6
39 OHM-5%
RN375
2 7
39 OHM-5%
RN375
1 8
39 OHM-5%
RN373
4 5
39 OHM-5%
RN373
3 6
39 OHM-5%
RN373
2 7
39 OHM-5%
RN373
1 8
39 OHM-5%
RN372
4 5
39 OHM-5%
RN372
3 6
39 OHM-5%
RN372
2 7
39 OHM-5%
RN372
1 8
39 OHM-5%
RN371
4 5
39 OHM-5%
RN413
3 6
39 OHM-5%
RN413
2 7
39 OHM-5%
RN413
1 8
39 OHM-5%
RN413
4 5
39 OHM-5%
RN374
4 5
39 OHM-5%
RN374
3 6
39 OHM-5%
RN374
2 7
39 OHM-5%
RN374
1 8
39 OHM-5%
R_CMD10
R_CMD18
R_CMD17
R_CMD21
R_CMD14
R_CMD11
R_CMD12
R_CMD22
R_CMD19
R_CMD16
R_CMD23
R_CMD61
R_CMD57
R_CMD63
R_CMD56
R_CMD51
R_CMD50
R_CMD48
R_CMD49
R_CMD43
R_CMD40
R_CMD46
R_CMD41
R_CMD60
R_CMD58
R_CMD62
R_CMD59
R_CMD20
R_MECC6
R_MECC7
R_MECC5
R_MECC4
R_CMD52
R_CMD53
R_CMD55
R_CMD54
CMD15
2
3
CMD8
2
3
MECC1
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
4
4
4
4
4
4
4
4
2
MECC2
2
MECC0
2
MECC3
2
CMD38
2
CMD37
2
CMD36
2
CMD39
2
CMD9
2
CMD13
2
CMD5
2
CMD2
2
CMD4
2
CMD3
2
CMD0
2
CMD1
2
CMD6
2
CMD7
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
CMD35
CMD34
CMD33
CMD32
MSTRB0
MSTRB1
CMD47
CMD44
CMD45
CMD42
CMD30
CMD27
CMD29
CMD26
CMD31
CMD28
CMD25
CMD24
RN380
2 7
39 OHM-5%
RN380
1 8
39 OHM-5%
RN412
3 6
39 OHM-5%
RN412
2 7
39 OHM-5%
RN412
1 8
39 OHM-5%
RN412
4 5
39 OHM-5%
RN381
4 5
39 OHM-5%
RN381
3 6
39 OHM-5%
RN381
2 7
39 OHM-5%
RN381
1 8
39 OHM-5%
RN380
4 5
39 OHM-5%
RN380
3 6
39 OHM-5%
RN388
1 8
39 OHM-5%
RN388
2 7
39 OHM-5%
RN388
3 6
39 OHM-5%
RN389
2 7
39 OHM-5%
RN388
4 5
39 OHM-5%
RN389
1 8
39 OHM-5%
RN389
4 5
39 OHM-5%
RN389
3 6
39 OHM-5%
RN400
4 5
39 OHM-5%
RN400
3 6
39 OHM-5%
RN400
2 7
39 OHM-5%
RN400
1 8
39 OHM-5%
1 2
39-5%
1 2
39-5%
RN391
4 5
39 OHM-5%
RN391
3 6
39 OHM-5%
RN391
2 7
39 OHM-5%
RN391
1 8
39 OHM-5%
RN404
4 5
39 OHM-5%
RN404
3 6
39 OHM-5%
RN404
2 7
39 OHM-5%
RN404
1 8
39 OHM-5%
RN403
4 5
39 OHM-5%
RN403
3 6
39 OHM-5%
RN403
2 7
39 OHM-5%
RN403
1 8
39 OHM-5%
R_CMD15
R_CMD8
R_MECC1
R_MECC2
R_MECC0
R_MECC3
R_CMD38
R_CMD37
R_CMD36
R_CMD39
R_CMD9
R_CMD13
R_CMD5
R_CMD2
R_CMD4
R_CMD3
R_CMD0
R_CMD1
R_CMD6
R_CMD7
R_CMD35
R_CMD34
R_CMD33
R_CMD32
R_MSTRB0
SUB*_3019E
R_MSTRB1
SUB*_3019E
R_CMD47
R_CMD44
R_CMD45
R_CMD42
R_CMD30
R_CMD27
R_CMD29
R_CMD26
R_CMD31
R_CMD28
R_CMD25
R_CMD24
3
3
3
3
3
3
4
4
4
4
3
3
3
3
3
1
2
3
3
3
3
3
4
4
4
4
3
3019E sub for part consolidation (1% versus 5%)
4
4
4
4
4
3
3
3
3
3
3
3
3
3
4 4
CMD BUS/CONTROL SERIES TERM
COMPUTER CORPORATION
AUSTIN,TEXAS
TITLE
SCHEM,MEM-CRD,6DIMM,PE4600
PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.
A B
DWG NO.
DC
8Y810
SHEET
A03
8/3/2004 15 OF 18
Page 16
B D
CA
8-3-2004_17:38
1
1
2.5V VID = 1 1 0 1 0
8Y810 A03: This cap is added for Intersil HIP6004 part and will be hand
soldered after the PWAs are made by MSI. The ref des is assigned to the cap for BOM tracking purposes. STMicro L6911B parts can also use the cap. See the note at page 18 for further explanation.
D1
2 1
2
VCC12_VCC25
VCC25_START
CMSH1-40
12
+
270uF
16V-20%
21
1uF
16V-10%
12
NP*
21
2
1uF
VCC33
2,11,13,14
16V-10%
12
+
270uF
16V-20%
1 2
0.1uF 16V
1 2
NP*
0.1uF 16V
NP*
1 2
Substitution for p/n consolidation
8Y810 A03: Added Intersil back to the AVL (3F153)
SUB*_79015
2
8Y810 A01: Replaced U30 Intersil/ST with ST only (009TG) Jaguar 2.0 Change: Replaced U30 L6911B (EOL) with L6911C
X02: Changed back to L6911B and added Intersil to AVL
1
2.2K-5%
.001UF
50V-20%
VCC25_VSEN VCC25_OCSET VCC25_SS
VCC25_VID1 VCC25_VID3
VCC25_VID4 VCC25_COMP
NP*
VCC25_FB
U30
1
2
OCSET
3
SS
4
5 6 7 8 9
10 11
NOT FOR USE
ON NEW DESIGNS
LGATE
RT OVP VCC
20 19 18 17 16 15 14 13 12
VCC25_RT NC_VCC25_OVP VCC12_VCC25 VCC25_LGATE
VCC25_BOOT
VCC25_UGATE
VCC25_PHASE
2.2-5%
1 2
21
0.1uF 16V
1 2
Q3
D
2
MOSFET NCHAN
1
G
3
S
20V_20A
VERIFY P/N FITS
SUB*_0J910
1 2
0.1uF 16V
1 2
NP*
1K-5%
2
Sub is for FET w/ lower Rdson
Jaguar 2.0 Change: Added FET and pullup/down since leaky diode degrades softstart
X02: Depop Q10 and Q11, else new risers will not work with old MB's
1K-5%
1 2
NP*
21
100K-1%
NP*
Q10
2N7002
D
3
1
G
S
2
NP*
1 2
0.1uF 16V
SUB*_85444
1 2
20K-5%
1 2
2200pf
50V-10%
1 2
0.1uF 16V
1 2
0.1uF 16V
33K
L6911B
SUB*_3F153
L17
21
2.2uH 12A
21
12
+
820uF
4V-20%
12
+
820uF
4V-20%
21
1uF
16V-10%
1 2
200-5%
1 2
200-5%
VCC25_PWRGD
2
1 2
3.01K-1%
2.2-5%
Q4
D
2
MOSFET NCHAN
21
30V_20A
VERIFY P/N FITS
G
Q5
D
2
MOSFET NCHAN
1
3
S
30V_20A
VERIFY P/N FITS
21
G
1
2.2-5%
3
S
VCC25
2-7,9,11,13,14
3
VIN = 12V VOUT = 2.5V
VOUT MAX CURRENT = 10 A
50V-5%
1 2
1K-5%
21
1 2
1 2
.082uF 16V
510K-5%
1 2
20-1%
1 2
.068uF 16V
1 2
3.01K-1%
3
Padstacks on 820 uF and 270 uF thru hole cap symbols changed to new thermal relief
4 4
2.5V GENERATION
COMPUTER CORPORATION
AUSTIN,TEXAS
TITLE
SCHEM,MEM-CRD,6DIMM,PE4600
PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.
DWG NO.
8Y810
8/3/2004
A03
SHEET
16 OF 18
A B
DC
Page 17
B D
CA
MEM CARD A
8-3-2004_15:33
1
TOPOLOGY CHANGED TO REDUCE JITTER/SKEW
CLOCK SYN
REMC DP
SLOT 2 CARD EDGE CONN
1
REMC DP
2
PLL
J5J6
J2J3J4
J1
2
PLL
3
PLL
SLOT 2 CARD EDGE CONN
REMC AP
REMC DP
3
CURRENT PLL ASL:
REMC DP
PHILIPS PCK2057
ICS 93701
TI CDCV850
J5J6
4 4
J1J2J3J4
100 OHM DIFFERENTIAL TERMINATION AT EACH DP/AP
AND AT EACH PLL FEEDBACK
A B
MEM CARD B
PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.
CLOCK ROUTING DIAGRAM
TITLE
SCHEM,MEM-CRD,6DIMM,PE4600
DWG NO.
8Y810
DC
COMPUTER CORPORATION
AUSTIN,TEXAS
A03
SHEET
17 OF 188/3/2004
Page 18
B D
CA
PREVIOUS REVISIONS
ECOREV DESCRIPTION APPROVEDDATE
X00
Jaguar 2.0 Changes to PWA 747JN (A03)
new REMC 3.0, VRMs for 2.5 & VTT CKT
11/25/02
8-4-2004_14:58
S. Lolayekar, R. Lago137924-A00
1
Revision Information
Changes for Jaguar 2.0 X00 - modified from PWA 747JN rev A03
L6911B is going EOL so substituted L6911C (page 16) - P/N 7K094
Replace REMC rev 2.0 with REV 3.0 (page 3,4) P/N 8Y113
L6911B is EOL so sub VRM Module and changed VTT ckt to that of Merlot design (pg 14) - P/N 2R515
137924-A00X01
137924-A00
A01 162394
NP C755 (14) that was forgotten in X00 Depop Q10 & Q11 (for new risers to work with old MB),
new PN for L6911B (added Intersil to AVL) Updated PWA references to include H6267 (MSI) Replaced part at U30 from Intersil/ST (3F153) with ST only (009TG)
01/03/03
02/10/03
05/21/04
R. Lago
S. LolayekarX02
1
Better Soft Start Option on DC_DC converter (page 14, 16) - new circuit with FET connected between SS and GND
Improved design - moved Ferrite bead and Cap power plane connection, separated GND, AGND vias - to reduce jitter (pg 11)
Too many devices on I2C - added pullups to PLL I2C lines, and disconnected from I2C (pg 11)
Changed PWA to new part number : 8Y813 Changed Schematic P/N to 8Y810
Changed assembly drawing number to 8Y809 Changed PWB to new part number : 8Y811
2
Changes for Jaguar 2.0 X01
2
Added NP C755 on page 14 - accidently taken off on last revision
Changes for Jaguar 2.0 X02
Depop Q10 and Q11 else new risers will not work with old MB (pg 14,16) Changed P/N of L6911B due to dual source - Intersil new vendor in addition to ST, took out L6911C (pg 16)
Changes for 8Y810 A01
Changed PWA to new part number : H6267 (MSI), and updated schem. loc. - page 1
3
Removed Intersil/ST (3F153) part at U30 and replaced with ST only (009TG) - page 16
Changes for 8Y810 A02
Remove U95 for cost saving as it is not being used - pages 5 and 13 Remove R622 (8.2k resistor) as U95 is depoped - page 5
Remove R624 (8.2k resistor), R619 (150 ohm), R620 (150 ohm) as U95 is depoped - page 13
Remove R625 (8.2k resistor), R621 (150 ohm), R626 (8.2k resistor) as U95 is depoped - page 13
3
Changes for 8Y810 A03
Added Intersil back to the AVL in addition to STMicro (3F153) - page 16 Added a 0.1uF capacitor (DP/N 05735) between D1 and ground for Intersil U30 - page 16
This capacitor will be hand soldered with the rework instructions given to MSI. The cap must be placed across gnd and Vcc as close to the component (U30) as possible (less than 1 inch).
The reason for adding the 0.1uF cap is that the phase line to the Intersil voltage regulator has excessive ringing on it and we (Tower Sustaing team) believe that the ringing is being transmitted to the logic inside the Intersil part which results in an unstable comparator on the high end comparator.
The part has a low and high end comparator that tells it if the output voltage is either too low or too high. The low voltage comparator remains stable but the high end comparator will register an improper high voltage starting at about 2.47V. As the regulator is outputting 2.5V, the system will immediately register bad
voltage and reset the system. STMicro part seems to be immune to the excessive ringing (could be due to filtering inside the component). STMicro does not require a cap but there is no harm in adding the cap.
Due to the unavailability of STMico L6911B parts we had to add Intersil HIP6004B back to the AVL.
On a side note, got errors when tel file was being generated and found that had to change the pin numbers for J1, J2, J3,
J4, J5, J6 ~clk_N_DU (from pin 76 to 75) and clk_P_DU (from pin 75 to 76). Changed the attribute field of the pins.
4 4
COMPUTER CORPORATION
AUSTIN,TEXAS
TITLE
SCHEM,MEM-CRD,6DIMM,PE4600
A B
PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.
DWG NO.
DC
8Y810
8/3/2004
A03
SHEET
18 OF 18
Loading...
Buy Points How it Works FAQ Contact Us Questions and Suggestions Privacy Policy Cookie Policy Terms of Use