9612345 78 10
EC NO.DATEQTYREL FOR ASM
REL
A
PART NO.
DEVELOPMENT NO. Q/M
A
B
C
1. TITLE
B
C
2. CHANGE LOG
3. HARRIER BLOCK DIAGRAM
4. 405GP INTERFACE TO SDRAM & PCI
D
5. PPC405 MISC
D
6. 405GP PWR/GND & JTAG
7. 405GP BOOTSTRAP
8. 405GP SDRAM
E
E
9. 405GP PERIPHERAL BUS
10. FLASH / RTC
11. CLOCK OSCILLATOR & DRIVER
12. UART
F
13. RS485 DRIVERS
F
14. I2C SEEPROM AND SWITCHES
15. ETHERNET PHY
16. USB & SMP CONNECTOR
G
G
17. VIDEO COMPRESSOR
18. SDRAM 1MX16X4b
19. POWER
20. SPARE PARTS
H
I
TITLE
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
6 9
OUTSIDE MAX
INSIDE MAX
0.13
2.0
1/1SCALE:
PART NO.
TITLE
HARRIER
1-15-2003_14:44
DESIGNER
CHECKED
APPROVED
SHEET OF
02R1679
Physical Design
Brandon EllisonJames Dalton
1
20
108754321
Jeff Davis
H
I
JJ
9612345 78 10
EC NO.DATEQTYREL FOR ASM
REL
A
PART NO.
DEVELOPMENT NO. Q/M
A
Change Log:
04/01/02 - BJE - (Page 4) Added MEM_ADD Bus net.
04/01/02 - BJE - (Page 4) Synched with final Pass 1 of Management Module.
B
C
D
E
04/01/02 - BJE - (Page5) Renamed IRQ pins to IRQ to prevent confusion.
04/01/02 - BJE - (Page 5) Synched with final Pass 1 of Management Module.
04/01/02 - BJE - (Page 6) Synched with final Pass 1 of Management Module.
04/01/02 - BJE - (Page 7) Synched with final Pass 1 of Management Module.
04/01/02 - BJE - (Page 7) Changed all resistors to correct values, 3.3k PU, 1k PD.
04/01/02 - BJE - (Page 7) Changed EPB Speed from 25 MHz to 50 MHz
04/01/02 - BJE - (Page 8) Synched with final Pass 1 of Management Module.
04/01/02 - BJE - (Page 9) Synched with final Pass 1 of Management Module.
04/01/02 - BJE - (Page 10) Synched with final Pass 1 of Management Module.
04/01/02 - BJE - (Page 11) Synched with final Pass 1 of Management Module.
04/01/02 - BJE - (Page 11) New Clock chip to be entered by James Dalton
04/01/02 - BJE - (Page 12) Synched with final Pass 1 of Management Module.
04/01/02 - BJE - (Page 12) Adjusted a few cap values.
04/01/02 - BJE - (Page 12) Swapped pop options on R21 & R20.
04/01/02 - BJE - (Page 13) Synched with final Pass 1 of Management Module.
04/02/02 - JWD - (Page 16) Added values for R 528,529,530,531.
04/03/02 - BJE - (Page 5) Condor 2000 Connections on GPIO
04/03/02 - BJE - (Page 9) Condor 2000 Connections on some GPIOs
04/03/02 - BJE - (Page 15) Added Condor 2000 Connections
04/06/02 - JWD -Fixed address bit order
04/07/02 - JWD - (Page 15) Added system on detection
4/8/02 - JWD - (page 18) Removed 1.8V (not required)
04/08/02 - JWD - (Page 15) Moved differential signals around on the SMP connectors
04/11/02 - BJE - (Page 12) Added all COM signals for Modem use.
04/11/02 - BJE - (Page 12) Moved Debug Port to COM1
04/11/02 - BJE - (Page 5) Added SPI Bus to IRQ lines
04/11/02 - BJE - (Page 12) Added BERG header for 485/232 selection
04/11/02 - BJE - (Page 16) Added SPI bus option to Xilinx bus
04/11/02 - BJE - (Page 12) Changed Enable line of 232 Part to GND
Pass 5 Changes
01/15/03 - JWD - added pull-up to R485_A_RTS_N
B
C
D
E
Pass 2 Changes
F
06/13/02 - JWD - (Page 15) Removed Inverter from input pin 9 on U75
06/13/02 - JWD - (Page 15) Fixed reflected serial EPROM (U8)
06/13/02 - JWD - (Page 6) Changed U1 to powered symbol
07/26/02 - JWD - Changed DRAM to single chip for cost reduction
07/31/02 - JWD - (Page 15) Changed SMP to single connector
F
Pass 3 Changes
9/23/02 - JWD -Changed RTC data and clk pull-downs to pull-ups. Nopoped CE pull-down.
G
09/23/02 - JWD - (Page 15) Added USB switches.
09/23/02 - RMK - (Page 15) Added pull-up to USB_HUB_INT
9/23/02 RMK Changed micron part number to the full part number
9/23/02 RMK - Changed vendor part number of U83 DRAM
09/23/02 - RMK - (Page 16) Added ibm part number (77P0174) to xilinx XC2S150
G
Pass 4 Changes
10/31/02 -JWD- (Page 4) Using PCI_RESET# for manufacturing test of insane LED
10/31/02 - JWD - (Page 5) Changed signal name from GPIO18 to RS232_DETECT
H
I
10/31/02 - RMK - (Page 5) Changed RTC_INT_N to RTC_DUART_INT_N (sharing Interrupt pin)
10/31/02 - RMK - (Page 9) P_CS1# is now used for USB / DUART with ROM_ADDR12 qualifying
10/31/02 - RMK - (Page 10) Changed RTC Interupt to TIRQ_N
10/31/02 - RMK - Changed flash IBM part number to 02R1640, added coded part number 02R1641, removed socket
10/31/02 - JWD - (Page 11) Added 23.5 MHz frequency for the duart to the clock driver
10/31/02 - RMK - (Page 12) Made new page 12 with DUART circuitry
10/31/02 - RMK - (Page 14) Added nopop resistors between D and S1 on U94 and U95 to test if the switches are needed
10/31/02 - RMK - (Page 16) Made USB_CS# from logical and of P_CS1# and ROM_ADDR12
10/31/02 - JWD - (Page 16) Added com4, changed name of GPIO18 to RS232_DETECT
10-30-02-JWD-P_EXT_ACK# is used to detect BIST mode after reset.
10/31/02 - RMK - Added IBM part number for RTC (77P0248)
10/31/02 - RMK - Added IBM part number for DIALIGHT LED CR2 (26P0055)
10/31/02 - RMK - Added IBM part number for DIALIGHT LED CR3 (29L2476)
10/31/02 - RMK - Added IBM part number for TI multiplexer u96 (77P0242)
10/31/02 - RMK - Added IBM part number for Cypress clock driver (77P0247)
10/31/02 - RMK - Added IBM part number for ST switches (77P0242)
CHANGE LOG
PART NO.
H
I
02R1679
TITLE
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
6 9
OUTSIDE MAX
INSIDE MAX
0.13
2.0
1/1SCALE:
HARRIER
1-15-2003_14:44
DESIGNER
CHECKED
APPROVED
SHEET OF
Physical Design
Jeff Davis
Brandon EllisonJames Dalton
2
20
108754321
JJ
9612345 78 10
EC NO.DATEQTYREL FOR ASM
REL
A
PART NO.
DEVELOPMENT NO. Q/M
A
I2C/SMBus
B
SMP
Ethernet
RS485/RS232
B
USB
C
C
28.6 MHz
16
FPGA
USB
50 MHz
D
CPU
32
E
D
E
USBFPGA
F
MAX6315
G
PPC_RESET_N
SYSTEM
CPU
JTAG
PERIPHERAL_RESET_N
PPC_NOT_READY_N
I2C
DUART
F
G
HOST ID
H
TRST_N
JTAG
I
OR
JTAG_RST_N
FLASH
ETHERNET
H
I
Harrier Block Diagram
PART NO.
02R1679
TITLE
HARRIER
1-15-2003_14:44
DESIGNER
CHECKED
APPROVED
SHEET OF
Brandon EllisonJames Dalton
3
20
108754321
JJ
RESET
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
6 9
OUTSIDE MAX
INSIDE MAX
0.13
2.0
1/1SCALE:
9612345 78 10
REL
A
04/01/02 - BJE - (Page 4) Added MEM_ADD Bus net.
04/01/02 - BJE - (Page 4) Synched with final Pass 1 of Management Module.
04/11/02 - JWD - (Page 4) deleted PCIADR's
10/31/02 -JWD- (Page 4) Using PCI_RESET# for manufacturing test of insane LED
3.3VC
EC NO.DATEQTYREL FOR ASM
PART NO.
DEVELOPMENT NO. Q/M
A
B
R553
R554
R555
R556
R557
R559
R560
R561
R562
R563
R564
R565
8.2K
8.2K
8.2K
R566
8.2K
8.2K
E26
PCI_PAR
J24
PCI_FRAME_N
J23
PCI_IRDY_N
G26
PCI_TRDY_N
H23
PCI_STOP_N
H25
PCI_DEVSEL_N
G24
PCI_SERR_N
G25
PCI_PERR_N
B24
PCI_RESET_N
U23
PCI_GNT0_REQ_N
T23
PCI_GNT1_N
F23
PCI_GNT2_N
H26
PCI_GNT3_N
N23
PCI_GNT4_N
M24
PCI_GNT5_N
L11
HS_RTN1
L12
HS_RTN2
L13
HS_RTN3
L14
HS_RTN4
L15
HS_RTN5
L16
HS_RTN6
M11
HS_RTN7
M12
HS_RTN8
M13
HS_RTN9
M14
HS_RTN10
M15
HS_RTN11
M16
HS_RTN12
N11
HS_RTN13
N12
HS_RTN14
N13
HS_RTN15
N14
HS_RTN16
N15
HS_RTN17
N16
HS_RTN18
P11
HS_RTN19
P12
HS_RTN20
P13
HS_RTN21
P14
HS_RTN22
P15
HS_RTN23
P16
HS_RTN24
R11
HS_RTN25
R12
HS_RTN26
R13
HS_RTN27
R14
HS_RTN28
R15
HS_RTN29
R16
HS_RTN30
T11
HS_RTN31
T12
HS_RTN32
T13
HS_RTN33
T14
HS_RTN34
T15
HS_RTN35
T16
HS_RTN36
U53
PPC405GP-3BE200C
A17
PCI_AD0
B16
PCI_AD1
C17
PCI_AD2
A18
PCI_AD3
D17
PCI_AD4
C18
PCI_AD5
B18
PCI_AD6
A20
PCI_AD7
B21
PCI_AD8
A23
PCI_AD9
D21
PCI_AD10
B22
PCI_AD11
B23
PCI_AD12
C22
PCI_AD13
C26
PCI_AD14
F25
PCI_AD15
K26
PCI_AD16
L23
PCI_AD17
M25
PCI_AD18
M23
PCI_AD19
N25
PCI_AD20
M26
PCI_AD21
N26
PCI_AD22
P24
PCI_AD23
R24
PCI_AD24
R23
PCI_AD25
P23
PCI_AD26
R25
PCI_AD27
T24
PCI_AD28
U26
PCI_AD29
T25
PCI_AD30
V26
PCI_AD31
PCI_IDSEL
PCI_CLK
D19
F24
K24
R26
P26
B20
C23
C19
C21
B19
A24
G23
J25
D20
Y23
Y26
R373
5.1K
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
PCI_REQ4#
PCI_REQ5#
From Walnut
R366
10K
P_WE#
PCI_REQ0# when Internal Arbiter is Used
PCI_GNT# when using External Arbiter
Asynch Mode Use
R94
R579
8.2K
R587
8.2K
R586
R585
8.2K
PCI_C_BE0_N
PCI_C_BE1_N
PCI_C_BE2_N
PCI_C_BE3_N
P_WE_PCI_INT_N
PCI_REQ0_GNT_N
PCI_REQ1_N
PCI_REQ2_N
PCI_REQ3_N
PCI_REQ4_N
PCI_REQ5_N
SPARE_D20
SPARE_Y23
SPARE_Y26
405GP INTERFACE TO SDRAM & PCI
PART NO.
8.2K
R584
8.2K
R92
8.2K
3.3VC
8.2K
16,17
R552
8.2K
8.2K
C
D
E
8 MEM_ADD0
MEM_ADD1
8
MEM_ADD2
8
MEM_ADD3
8
MEM_ADD4
8
MEM_ADD5
8
MEM_ADD6
8
MEM_ADD7
8
MEM_ADD8
R99
R104
R105
R106
R102
R103
8
8
8
R98
22
R97
22
R95
22
R91
22
R55
22
8
8
8
8
22
RES_MEM_BSEL0#
22
RES_MEM_BSEL1#
22
RES_MEM_BSEL2#
22
RES_MEM_BSEL3#
22
22
MEM_ADD9
MEM_ADD10
MEM_ADD11
MEM_ADD12
RES_MEM_BA0
RES_MEM_BA1
RES_MEM_RAS#
RES_MEM_CAS#
RES_MEM_WE#
MEM_DQM3
MEM_DQM2
MEM_DQM1
MEM_DQM0
MEM_DQM_CB
RES_MEM_CLKEN0
RES_MEM_CLK0
F
MEM_BA0
8
MEM_BA1
8
MEM_RAS#
8
MEM_CAS#
8
MEM_WE#
G
H
MEM_CS0#
8
I
8
DQM Lines swapped to match Data Lines
R110
8
8
Up to 4 banks possible - Only using 1
3.3K
NOPOP resistors to allow for hot wiring later if needed.
NOPOP
MEM_CS1#
MEM_CS2#
MEM_CS3#
MEM_CLKEN0
MEM_CLK0
NOPOP
NOPOP
NOPOP
AE22
AC21
AE21
AD21
AF22
AE20
AC19
AE19
AD19
AC18
AF19
AD18
AC17
AB24
AC24
AF24
AB23
AC16
AC12
AC10
AC6
AA3
AC15
AD17
AF17
AE15
AC14
AB25
AC25
AC26
AA23
M_ADDR0
M_ADDR1
M_ADDR2
M_ADDR3
M_ADDR4
M_ADDR5
M_ADDR6
M_ADDR7
M_ADDR8
M_ADDR9
M_ADDR10
M_ADDR11
M_ADDR12
M_BA0
M_BA1
M_RAS_N
M_CAS_N
M_WE_N
M_DQM0
M_DQM1
M_DQM2
M_DQM3
M_DQM_CB
M_BANKSEL0_N
M_BANKSEL1_N
M_BANKSEL2_N
M_BANKSEL3_N
M_CLKEN0
M_CLKEN1
M_CLKOUT0
M_CLKOUT1
U53
PPC405GP-3BE200C
M_DATA0
M_DATA1
M_DATA2
M_DATA3
M_DATA4
M_DATA5
M_DATA6
M_DATA7
M_DATA8
M_DATA9
M_DATA10
M_DATA11
M_DATA12
M_DATA13
M_DATA14
M_DATA15
M_DATA16
M_DATA17
M_DATA18
M_DATA19
M_DATA20
M_DATA21
M_DATA22
M_DATA23
M_DATA24
M_DATA25
M_DATA26
M_DATA27
M_DATA28
M_DATA29
M_DATA30
M_DATA31
M_ECC0
M_ECC1
M_ECC2
M_ECC3
M_ECC4
M_ECC5
M_ECC6
M_ECC7
M_CLK_IN
AC13
RES_MEM_DATA30 MEM_DATA30
AE12
RES_MEM_DATA29
AD11
RES_MEM_DATA28
AC11
RES_MEM_DATA27
AF10
RES_MEM_DATA26
AE11
RES_MEM_DATA25
AD10
RES_MEM_DATA24
AF9
RES_MEM_DATA23
AD9
RES_MEM_DATA22
AE9
AD8
RES_MEM_DATA20
AF7
AC8
RES_MEM_DATA18
AD7
AE6
RES_MEM_DATA16 MEM_DATA16
AE5
AE4
RES_MEM_DATA14
AD5
AD4
RES_MEM_DATA12
AC5
AD1
RES_MEM_DATA10
AB2
AA4
RES_MEM_DATA8
AA2
RES_MEM_DATA7
AB1
RES_MEM_DATA6
Y2
RES_MEM_DATA5
W4
RES_MEM_DATA4
W2
RES_MEM_DATA3
W3
RES_MEM_DATA2
V4
RES_MEM_DATA1
W1
RES_MEM_DATA0
V3
AE14
AF15
AF14
AD13
AF13
AF12
AE13
AD12
AF4
R365
10K
Listed as Reserved in Datasheet
RN14
18
RN14
36
RN21
18
RN21
36
RN15
18
RN15
36
RN20
18
RN20
36
RN16
18
RN16
36
RN19
18
RN19
36
RN17
18
RN17
36
RN18
18
RN18
36
Using PCI_RESET# for manufacturing test of insane LED
22RES_MEM_DATA31
27
22
45
22
27
22
45
22
27
22RES_MEM_DATA21
45
22RES_MEM_DATA19
27
22RES_MEM_DATA17
45
22RES_MEM_DATA15
27
22RES_MEM_DATA13
45
22RES_MEM_DATA11
27
22RES_MEM_DATA9
45
22
22
45
22
27
22
45
MEM_DATA31
RN14
22
MEM_DATA29
RN14
MEM_DATA28
22
MEM_DATA27
RN21
MEM_DATA26
22
MEM_DATA25
RN21
MEM_DATA24
22
MEM_DATA23
RN15
MEM_DATA22
22
MEM_DATA21
RN15
MEM_DATA20
22
MEM_DATA19
RN20
MEM_DATA18
22
MEM_DATA17
RN20
22
MEM_DATA15
RN16
MEM_DATA14
22
MEM_DATA13
RN16
MEM_DATA12
22
MEM_DATA11
RN19
MEM_DATA10
22
MEM_DATA9
RN19
MEM_DATA8
22
MEM_DATA7
RN17
MEM_DATA6
22
27
RN17
RN18
RN18
MEM_DATA5
MEM_DATA4
22
MEM_DATA3
22
MEM_DATA2
MEM_DATA1
22
MEM_DATA0
PCI_PAR
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_DEVSEL#
PCI_SERR#
PCI_PERR#
PCI_RESET#
5
PCI_GNT0#
PCI_GNT1#
PCI_GNT2#
PCI_GNT3#
PCI_GNT4#
PCI_GNT5#
PCI_GNT0# when Internal Arbiter is Used
PCI_REQ# when using External Arbiter
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3.3VC
8.2K
8.2K
8.2K
R558
8.2K
8.2K
8.2K
8.2K
8.2K
B
C
D
E
F
G
H
I
02R1679
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
6 9
OUTSIDE MAX
INSIDE MAX
0.13
2.0
1/1SCALE:
TITLE
HARRIER
1-15-2003_14:44
DESIGNER
CHECKED
APPROVED
SHEET OF
Physical Design
Jeff Davis
Brandon EllisonJames Dalton
4
20
108754321
JJ
9612345 78 10
REL
A
3.3VC
EC NO.DATEQTYREL FOR ASM
PART NO.
DEVELOPMENT NO. Q/M
A
R597
1MEG
U88
GND
S1
S2
IN = 1
1
3
2
IN = 0
R594
0
R595
0
PPC405GP-3BE200C
HOST_PWR#
5
B
HOST_RST#
5
C
2_5V
C523
D
E
F
G
H
Internal Timer Input
Not currently used.
Peripheral Bus Controls
NEEDED?
100N
P_HOLD_REQ
P_EXT_REQ#
P_HOLD_PRIORITY
P_BUS_REQ
P_ERROR
PULLUP to 2.5V for PLL
BLM31A700S
L43
R522
SYS_TIMER_CLK
3.3VC
R90
R578
3.3VC
3.3K
3.3K
3.3K
C522
100N
R87
C534
16
5
16
12
16
5
16
6
6
6
6
11 33MHZ_405GP
PPC_RESET_N
6,10
RISCWATCH_HALT#
6
10U
R518
R520
3.3K
USB_HUB_INT
HOST_RST#
HOST_PCI_RST_N
SER_CLK
USB_LATCH_EMPTY
RS232_DETECT
RTC_DUART_INT_N
JTAG_TDI
JTAG_TMS
JTAG_TCK
JTAG_RST_N
R88
1K
1K
R519
3.3K
3.3VC
3.3K
R521
3.3K
10
17
A25
D22
AB26
D25
D26
C25
D24
AA24
Y25
Y24
W25
W24
V23
V25
AE24
AC22
AD22
AE26
E23
E24
V1
Y4
T2
R3
B1
CLK
X_CCLK
SYS_CLOCK
SYS_RESET_N
SYS_HALT_N
SYS_PLL_VDDA
CE0_TEST
DI1
Symbol is wrong on these three pins
DI2
DI1 DI2 RI - All test pins - No biggie.
RI
SYS_TIMER_CLK
IRQ6
GPIO23
IRQ5
GPIO22
IRQ4
GPIO21
IRQ3
GPIO20
IRQ2
GPIO19
IRQ1
GPIO18
IRQ0
GPIO17
JTAG_TDI
JTAG_TMS
JTAG_TCK
JTAG_TRST_N
P_HOLD_REQ
P_EXT_REQ_N
P_HOLD_PRIORITY
P_BUS_REQ
P_ERROR
R551
3.3VC
U53
1MEG
VCC
5
6
4
HOST_PWR_REQ#
Consider bi-directional buffers for next pass.
HOST_PWRGD/RST#
P_EXT_RESET_N
P_EXT_ACK_N
3.3VC
IN
D
SER_CLK 5
SYS_ERROR
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
P_CLK
JTAG_TDO
P_HOLD_ACK
16
16
3.3VC
U75
14
7,16
6
10,15
7
7
ERROR_LED#
43
PERCLK
17
5
12,14,16,17
5,7,10
7,17
7,16
17
ERROR_LED
AD25
AB3
AC7
AF5
AE8
AC9
FPGA = 0, RTC = 1
AF18
A22
C20
D18
E4
JTAG_TDO
AD23
PPC_NOT_READY_N
T3
Output reset to external devices.
P_HOLD_ACK
U2
P_EXT_ACK#
Y3
FPGA = 0, RTC = 1
HOST_PWR#
X_DONE
SER_DATA
I2C_SELECT
PERIPHERAL_RESET_N
FPGA_RTC
X_INIT
X_PROG
GPIO1
All GPIO's are high impedance while in reset. refer to 405gp user manual sec 23.5.1
R649
49.9
Place close to 405GP
Strapping Pins
FPGA_RTC
5,7,10
R610
10
3.3VC
U1
14
12
13
7
LV08_TSSOP14_65MM
5
14
17
11
330
2CR2
+
VEN_P/D_NUM=597-2401-213
VENDOR=DIALIGHT
COLOR=YELLOW
1
-
ERROR_LED_BUF
PCI_RESET#
16
PCI_reset is being used as a GPIO
4
10
R611
3.3VC3.3VC
330
2CR3
+
1
-
VEN_P/D_NUM=597-2301-213
VENDOR=DIALIGHT
COLOR=GREEN
PowerInsane
15
15
15
15
15
15
15
15
15
15
3.3VC
15
15
4.7K
R647
4.7K
R646
ENET_PHY_RXD3
ENET_PHY_RXD2
ENET_PHY_RXD1
ENET_PHY_RXD0
ENET_PHY_RX_ERR
ENET_PHY_RX_CLK
ENET_PHY_RX_DV
ENET_PHY_CRS
ENET_PHY_TX_CLK
ENET_PHY_COL
ENET_PHY_MDC
ENET_PHY_MDIO
R517
3.3K
12 COM1_RX
COM1_DCD#
12 COM1_CTS#
COM1_RI#
13 COM2_RX
13
COM2_CTS#
UART_RX = UART1_RX
UART_DSR_N = UART1_DSR_N
COM2 - DSR = CTS RTS = DTR
SERCLK
AD20
EMC_PHY_RXD3
AC20
EMC_PHY_RXD2
AF23
EMC_PHY_RXD1
AE23
EMC_PHY_RXD0
U24
EMC_PHY_RX_ER
AF20
EMC_PHY_RX_CLK
V24
EMC_PHY_RX_DV
W23
EMC_PHY_CRS
E25
EMC_PHY_TX_CLK
AA25
EMC_PHY_COL
H24
EMC_MDC
AD26
EMC_MDIO
AE17
UART_SERCLK
AE16
UART0_RX
AE18
UART0_DCD_N
AB4
UART0_CTS_N
AD15
UART0_RI_N
AC1
UART_RX
AC3 AD2
UART_DSR_N UART1_DTR_N
04/01/02 - BJE - (Page5) Renamed IRQ pins to IRQ to prevent confusion.
04/01/02 - BJE - (Page 5) Synched with final Pass 1 of Management Module.
04/03/02 - BJE - (Page 5) Condor 2000 Connections on GPIO
04/11/02 - BJE - (Page 5) Added SPI Bus to IRQ lines
08/16/02 - JWD - (Page 5) Added I2C_SELECT to GPIO6
08/16/02 - JWD - (Page 5) Added power and insane LED's
10/31/02 - JWD - (Page 5) Changed signal name from GPIO18 to RS232_DETECT
10/31/02 - RMK - (Page 5) Changed RTC_INT_N to RTC_DUART_INT_N (sharing Interrupt pin)
U53
PPC405GP-3BE200C
EMC_TXD3
EMC_TXD2
EMC_TXD1
EMC_TXD0
EMC_TX_ER
EMC_TX_EN
UART0_TX
UART0_DSR_N
UART0_DTR_N
UART0_RTS_N
UART1_TX
IIC_SCL
IIC_SDA
P25
L24
L25
J26
K25
K23
AF3
AE3
AF2
AD16
AC2
AD6
AE7
Strapping Pins
ENET_PHY_TX_EN
Strapping Pins
COM1_TX
COM1_DSR#
COM1_DTR#
COM1_RTS#
COM2_TX
COM2_RTS#
I2C_SCL
I2C_SDA
7,15ENET_PHY_TX_ERR
7,15
7,12
7,13
7,13
7,15ENET_PHY_TXD3
7,15ENET_PHY_TXD2
7,15ENET_PHY_TXD1
7,15ENET_PHY_TXD0
7,12
B
C
D
E
3.3VC
4.7K
R648
7
14
14
F
G
H
VENDOR=ST_MICRO
VEN_P/D_NUM=STG3157CTR
I
10
X_DOUT 5SER_DATA
17
$5I5959
U87
DIO
GND
VENDOR=ST_MICRO
VEN_P/D_NUM=STG3157CTR
S1
IN = 1
1
S2
3
2
IN = 0
3.3VC
VCC
5
IN
6
D
4
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
6 9
OUTSIDE MAX
INSIDE MAX
0.13
2.0
1/1SCALE:
PPC405 MISC
PART NO.
02R1679
TITLE
HARRIER
1-15-2003_14:44
DESIGNER
CHECKED
APPROVED
James Dalton
SHEET OF
5
108754321
Physical Design
Jeff Davis
Brandon Ellison
20
I
JJ
9612345 78 10
EC NO.DATEQTYREL FOR ASM
JTAG_RST_N
5
DEBUG PORT405 RISCWatch and JTAG
PPC_RESET_N
TRST_N
REL
3.3VC
U1
1
2
LV08_TSSOP14_65MM
14
3
7
405GP POWER
A
Place one set of THREE (100nF, 10nF, 2.2nF)
2_5V
per side within 25mils of 405GP
Place 10uF within 100mils of 405GP
C60
C59
C7
100N
B
C
D
E
F
10U
C61
C8
100N
10U
3.3VC
Place one set of THREE (100nF, 10nF, 2.2nF)
per side within 25mils of 405GP
Place 10uF within 100mils of 405GP
C66
C9
100N
10U
C69
100N
C62
C65
C68
100N
100N
100N
100N
C328
C330
C332
C334
10N
10N
10N
10N
C329
C331
C333
C335
10N
10N
10N
10N
C494
C496
C63
C64
2.2N
2.2N
2.2N
2.2N
C72
2.2N
C495
2.2N
C67
2.2N
C497
2.2N
2_5V
3.3VC
AB10
AB11
AB12
AB15
AB16
AB17
M22
U22
AA5
AB19
AB20
AB21
AB6
AB7
AB8
AA22
G22
H22
W22
Y22
AE10
AD14
U25
N24
B17
C13
E10
E11
E12
E15
E16
E17
K22
L22
R22
T22
F22
E19
E20
E21
W5
P2_5V_AB10
P2_5V_AB11
P2_5V_AB12
P2_5V_AB15
P2_5V_AB16
P2_5V_AB17
P2_5V_E10
P2_5V_E11
P2_5V_E12
P2_5V_E15
P2_5V_E16
P2_5V_E17
P2_5V_K22
K5
P2_5V_K5
P2_5V_L22
L5
P2_5V_L5
P2_5V_M22
M5
P2_5V_M5
P2_5V_R22
R5
P2_5V_R5
P2_5V_T22
T5
P2_5V_T5
P2_5V_U22
U5
P2_5V_U5
P3_3V_AA5
F5
P3_3V_F5
G5
P3_3V_G5
H5
P3_3V_H5
P3_3V_W5
Y5
P3_3V_Y5
P3_3V_AB19
P3_3V_AB20
P3_3V_AB21
P3_3V_AB6
P3_3V_AB7
P3_3V_AB8
P3_3V_AA22
P3_3V_F22
P3_3V_G22
P3_3V_H22
P3_3V_W22
P3_3V_Y22
P3_3V_E19
P3_3V_E20
P3_3V_E21
E6
P3_3V_E6
E7
P3_3V_E7
E8
P3_3V_E8
K2
P3_3V_K2
P3
P3_3V_P3
P3_3V_AE10
P3_3V_AD14
P3_3V_U25
P3_3V_N24
P3_3V_B17
P3_3V_C13
U53
PPC405GP-3BE200C
GND_A1
GND_AE1
GND_AF1
GND_A2
GND_B2
GND_AE2
GND_C3
GND_AD3
GND_D4
GND_A11
GND_A16
GND_A21
GND_AC4
GND_E5
GND_A6
GND_J5
GND_AA1
GND_P5
GND_AA26
GND_V5
GND_AB14
GND_AB5
GND_AB18
GND_AB22
GND_AF11
GND_E9
GND_AB9
GND_AF16
GND_AF21
GND_E13
GND_AB13
GND_AF25
GND_AF6
GND_E14
GND_E18
GND_E22
GND_F1
GND_F26
GND_L1
GND_L26
GND_N22
GND_N5
GND_T1
GND_T26
GND_J22
GND_H1
GND_P22
GND_AF8
GND_V22
GND_W26
GND_D23
GND_A19
GND_AC23
GND_C24
GND_AD24
GND_B25
GND_AE25
GND_AF26
GND_A26
GND_B26
A1
AE1
AF1
A2
B2
AE2
C3
AD3
D4
A11
A16
A21
AC4
E5
A6
J5
AA1
P5
AA26
V5
AB14
AB5
AB18
AB22
AF11
E9
AB9
AF16
AF21
E13
AB13
AF25
AF6
E14
E18
E22
F1
F26
L1
L26
N22
N5
T1
T26
J22
H1
P22
AF8
V22
W26
D23
A19
AC23
C24
AD24
B25
AE25
AF26
A26
B26
04/01/02 - BJE - (Page 6) Synched with final Pass 1 of Management Module.
04/10/02 - JWD - (Page 6) Moved LED's to CROW.
08/15/02 - JWD - (Page 6) Changed C7,C8,C9 to 10uF ceramic
3.3VC
R580
R581
R582
R583
10K
10K
10K
10K
0
R628
JTAG_TDO
5
JTAG_TDI
5
JTAG_TCK
5
JTAG_TMS
5
RISCWATCH_HALT#
5
J5
C10
C12C11
KEY
C16C15
2
C2
43
C4C3
65
C6C5
87
C8C7
10
NC
1211
NC
1615
1
C1
NC
9
C9
13
NOPOP
42F6867
79282-516
C13
CONN2x8HDR_KEY
NC
NC
3.3VC
1K
R226
R117
10K
5,10
PART NO.
DEVELOPMENT NO. Q/M
A
B
C
D
E
F
G
H
I
405GP PWR/GND & JTAG
PART NO.
G
H
I
02R1679
TITLE
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
$6I5250
6 9
OUTSIDE MAX
INSIDE MAX
0.13
2.0
1/1SCALE:
HARRIER
1-15-2003_14:44
DESIGNER
CHECKED
APPROVED
SHEET OF
Physical Design
Jeff Davis
Brandon EllisonJames Dalton
6
20
108754321
JJ
9612345 78 10
EC NO.DATEQTYREL FOR ASM
PART NO.
REL
A
DEVELOPMENT NO. Q/M
A
04/01/02 - BJE - (Page 7) Synched with final Pass 1 of Management Module.
04/01/02 - BJE - (Page 7) Changed all resistors to correct values, 3.3k PU, 1k PD.
04/01/02 - BJE - (Page 7) Changed EPB Speed from 25 MHz to 50 MHz
08/15/02 - JWD - (Page 7) Pulled X_PROG High so all available GPIO's have pull-ups
10/30/02 - JWD - (Page 7) Change PCI Synchronous Mode to Async (pulled-up). Added BIST detect to this input.
3.3VC 3.3VC 3.3VC3.3VC3.3VC 3.3VC 3.3VC 3.3VC 3.3VC
405GP BOOTSTRAP #1
R64
R65
B
5,12
5,15
5,15
5,12
5
9
9
9
9
COM1_TX
COM1_DTR#
COM1_RTS#
P_DMA_ACK0
P_DMA_ACK1
P_DMA_ACK2
P_DMA_ACK3
ENET_PHY_TXD3
ENET_PHY_TXD2
PLL Tuning TX DTR RTS
Choice 3 (6 <= M <=7) 0 1 0
Choice 5 (7 < M <=12) 1 0 0
Choice 6 (12 < M <= 32) 1 0 1
PLL Forward Divide Ack0 Ack1
Bypass 0 0
C
D
DIV 3 0 1
DIV 4 1 0
DIV 6 1 1
PLL Feedback Divide Ack2 Ack3
DIV 1 0 0
DIV 2 0 1
DIV 3 1 0
DIV 4 1 1
PLB Divider from CPU TxD3 TxD2
DIV 1 0 0
DIV 2 0 1
3.3K
POP
3.3K
NOPOP
R66
3.3K
POP
DIV 4 1 1
R71
3.3K
NOPOP
R67
3.3K
R68
R72
3.3K
3.3K
POP
POP
NOPOP
R73
3.3K
NOPOP
R69
3.3K
POP
NOPOP
POP
NOPOP
POP
NOPOP
NOPOP
POP
POP
NOPOP
R40
R48
R41
R47
R42
R43
R46
R45
R44
B
Strap: 1
1K
Strap: 0
1K
Strap: 1
1K
Strap: 0
1K
Strap: 1
1K
Strap: 1
1K
Strap: 0
1K
Strap: 0
1K
Strap: 1
1K
From Users Guide - Section 7
33 MHz Reference Clock
FWD Divide = 3
PLB Divider from CPU = 2
PLL Feedback Divide = 3
____
M = 18
VCO Stable (MHz) = 600
CPU Speed (MHz) = 200
PLB Speed (MHz) = 100
OPB Speed (MHz) = 50
EPB Speed (MHz) = 50
C
D
E
405GP BOOTSTRAP #2
R74
R76
3.3K
3.3K
POP
OPB Divider from PLB TxD1 TxD0
DIV 1 0 0
F
G
H
I
DIV 2 0 1
DIV 3 1 0
DIV 4 1 1
PCI Divide from PLB GPIO1 X_PROG
DIV 1 0 0
DIV 2 0 1
DIV 3 1 0
DIV 4 1 1
External Bus Divider from PLB TxErr TxEn
DIV 2 0 0
DIV 3 0 1
DIV 4 1 0
DIV 5 1 1
ROM Width TX DTR#
DIV 8 0 0
DIV 16 0 1
DIV 32 1 0
Reserved 1 1
ROM Location P_HOLD_ACK
Peripheral 0
PCI 1
PCI Synchronous Mode P_EXT_ACK#
Synch 0
Asynch 1
PCI Arbititer Enable FPGA_RTC
Internal Disable 0
Internal Enable 1
5,13
5,15
5,15
5,16
5,17
5,15
5,15
5,13
5
5,16
5,10
ENET_PHY_TXD1
ENET_PHY_TXD0
GPIO1
X_PROG
ENET_PHY_TX_ERR
ENET_PHY_TX_EN
COM2_TX
COM2_RTS#
P_HOLD_ACK
P_EXT_ACK#
FPGA_RTC
NOPOP
R75
3.3K
R80
3.3K
POP
POP
R86
3.3K
NOPOP
R81
3.3K
NOPOP
R82
3.3K
NOPOP
R83
3.3K
NOPOP
R84
3.3K
NOPOP
3.3VC3.3VC3.3VC3.3VC3.3VC3.3VC3.3VC 3.3VC3.3VC3.3VC
R85
3.3K
POP
R70
3.3VC
3.3K
POP
POP
NOPOP
NOPOP
NOPOP
POP
POP
POP
POP
POP
NOPOP
NOPOP
R49
R50
R51
R53
R61
R54
R56
R57
R58
R59
R60
Strap: 0
1K
Strap: 1
1K
Strap: 1
1K
Strap: 0
1K
Strap: 0
1K
Strap: 0
1K
Strap: 0
1K
Strap: 0
1K
Strap: 0
1K
Strap: 0
1K
Strap: 1
1K
E
F
G
H
I
405GP Bootstrap
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
6 9
OUTSIDE MAX
INSIDE MAX
0.13
2.0
PART NO.
02R1679
TITLE
1/1SCALE:
HARRIER
1-15-2003_14:44
DESIGNER
CHECKED
APPROVED
SHEET OF
Physical Design
James Dalton Brandon Ellison
7
Jeff Davis
20
108754321
JJ
9612345 78 10
7_26_02 JWD - Changed DRAM to single chip for cost reduction
9/23/02 RMK - Changed vendor part number of U83 DRAM
A
SDRAM Addresssing Mode = 2 (page 15-7 in User's Guide)
12 Bit Row Address
9 Bit Column Address
2 Bit Bank Selection
Page Size = 2kb
12 bit addressing mode.
REL
EC NO.DATEQTYREL FOR ASM
PART NO.
DEVELOPMENT NO. Q/M
A
B
3.3VC
U83
SDRAM2MX32
1
VCC0
15
VCC1
29
C
D
E
F
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
MEM_ADD04
MEM_ADD1
MEM_ADD2
MEM_ADD3
MEM_ADD4
MEM_ADD5
MEM_ADD6
MEM_ADD7
MEM_ADD8
MEM_ADD9
MEM_ADD10
MEM_BA0
MEM_BA1
MEM_DQM04
MEM_DQM14
MEM_DQM24
MEM_DQM34
MEM_RAS#
MEM_CS0#
MEM_CAS#
MEM_WE#
MEM_CLK0
MEM_CLKEN0
VCC2
43
VCC3
3
VCCQ1
9
VCCQ2
35
VCCQ3
41
VCCQ4
49
VCCQ5
55
VCCQ6
75
VCCQ7
81
VCCQ8
25
A0
26
A1
27
A2
60
A3
61
A4
62
A5
63
A6
64
A7
65
A8
66
A9
24
A10
22
BA0
23
BA1
16
DQM0
71
DQM1
28
DQM2
59
DQM3
19
RAS_N
20
CS_N
18
CAS_N
17
WE_N
68
CLK
67
CKE
44
GND1
58
GND2
72
GND3
86
GND4
DQ0
8nS
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
NC
GNDQ1
GNDQ2
GNDQ3
GNDQ4
GNDQ5
GNDQ6
GNDQ7
GNDQ8
MEM_DATA0
2
MEM_DATA1
4
MEM_DATA2
5
MEM_DATA3
7
MEM_DATA4
8
MEM_DATA5
10
MEM_DATA6
11
MEM_DATA7
13
MEM_DATA8
74
MEM_DATA9
76
MEM_DATA10
77
MEM_DATA11
79
MEM_DATA12
80
MEM_DATA13
82
MEM_DATA14
83
MEM_DATA15
85
MEM_DATA16
31
MEM_DATA17
33
MEM_DATA18
34
MEM_DATA19
36
MEM_DATA20
37
MEM_DATA21
39
MEM_DATA22
40
MEM_DATA23
42
MEM_DATA24
45
MEM_DATA25
47
MEM_DATA26
48
MEM_DATA27
50
MEM_DATA28
51
MEM_DATA29
53
MEM_DATA30
54
MEM_DATA31
56
21
6
12
32
38
46
52
78
84
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
B
C
D
E
F
G
3.3VC
3.3VC
C75
C340
H
Place one set of THREE (100nF, 10nF, 2.2nF)
per side within 25mils of module
I
C341
10N
10N
100N
C76
C502
100N
2.2N
C503
2.2N
C11
place within 50 mils
10U
405GP SDRAM (8MB)
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
6 9
OUTSIDE MAX
INSIDE MAX
0.13
2.0
PART NO.
02R1679
HARRIER
1/1SCALE:
TITLE
1-15-2003_14:44
DESIGNER
CHECKED
APPROVED
SHEET OF
Physical Design
Jeff Davis
Brandon EllisonJames Dalton
8
20
108754321
G
H
I
JJ
9612345 78 10
REL
A
04/01/02 - BJE - (Page 9) Synched with final Pass 1 of Management Module.
04/03/02 - BJE - (Page 9) Condor 2000 Connections on some GPIOs
10/31/02 - RMK - (Page 9) P_CS1# is now used for USB / DUART with ROM_ADDR12 qualifying
EC NO.DATEQTYREL FOR ASM
PART NO.
DEVELOPMENT NO. Q/M
A
B
ROM_ADDR[0:31]
R621
CABLE_DET#
R573
R6
1K
3.3K
1K
ROM_DATA[0:31]
3.3K
ROM_DATA0
ROM_DATA1
ROM_DATA2
ROM_DATA3
ROM_DATA4
ROM_DATA5
ROM_DATA6
ROM_DATA7
ROM_DATA8
ROM_DATA9
ROM_DATA10
ROM_DATA11
ROM_DATA12
ROM_DATA13
ROM_DATA14
ROM_DATA15
ROM_DATA16
ROM_DATA17
ROM_DATA18
ROM_DATA19
ROM_DATA20
ROM_DATA21
ROM_DATA22
ROM_DATA23
ROM_DATA24
ROM_DATA25
ROM_DATA26
ROM_DATA27
ROM_DATA28
ROM_DATA29
ROM_DATA30
ROM_DATA31
DMA Channels - Not Used
C16
D14
C11
U4
U3
U1
T4
R2
P4
R4
P2
R1
P1
N3
N1
M1
N2
M3
M4
N4
M2
L3
L4
K1
L2
K3
J1
K4
J3
J2
J4
H3
G1
H2
H4
D2
E2
F4
D1
C1
E3
F2
A7
P_DATA0
P_DATA1
P_DATA2
P_DATA3
P_DATA4
P_DATA5
P_DATA6
P_DATA7
P_DATA8
P_DATA9
P_DATA10
P_DATA11
P_DATA12
P_DATA13
P_DATA14
P_DATA15
P_DATA16
P_DATA17
P_DATA18
P_DATA19
P_DATA20
P_DATA21
P_DATA22
P_DATA23
P_DATA24
P_DATA25
P_DATA26
P_DATA27
P_DATA28
P_DATA29
P_DATA30
P_DATA31
P_WBE0_N
P_WBE1_N
P_WBE2_N
P_WBE3_N
P_R_W_N
P_READY
P_BLAST_N
P_DMAREQ0
P_DMAREQ1
P_DMAREQ2
P_DMAREQ3
10,12,16,17
C
D
3.3VC
R576
R577
E
F
G
H
17
17
17
17
10,12,16,17
10,17
P_WBE0#
P_WBE1#
P_WBE2#
P_WBE3#
P_R_W#
P_READY
P_BLAST#
P_DMAREQ0
P_DMAREQ1
P_DMAREQ2
P_DMAREQ3
R572
3.3K
3.3K
R71KR201KR21
R575
3.3K
R574
3.3K
U53
PPC405GP-3BE200C
P_ADDR0
P_ADDR1
P_ADDR2
P_ADDR3
P_ADDR4
P_ADDR5
P_ADDR6
P_ADDR7
P_ADDR8
P_ADDR9
P_ADDR10
P_ADDR11
P_ADDR12
P_ADDR13
P_ADDR14
P_ADDR15
P_ADDR16
P_ADDR17
P_ADDR18
P_ADDR19
P_ADDR20
P_ADDR21
P_ADDR22
P_ADDR23
P_ADDR24
P_ADDR25
P_ADDR26
P_ADDR27
P_ADDR28
P_ADDR29
P_ADDR30
P_ADDR31
P_PAR0
P_PAR1
P_PAR2
P_PAR3
P_CS0_N
P_CS1_N
P_CS2_N
P_CS3_N
P_CS4_N
P_CS5_N
P_CS6_N
P_CS7_N
P_OE_N
P_DMA_ACK0
P_DMA_ACK1
P_DMA_ACK2
P_DMA_ACK3
P_DMA_EOT_TC0
P_DMA_EOT_TC1
P_DMA_EOT_TC2
P_DMA_EOT_TC3
D5
A3
B4
B5
D6
B6
C6
D7
A5
B7
C7
D8
B8
C8
D9
A8
C9
D10
C10
A10
D11
B12
D13
D12
B13
A12
A13
C14
A14
A15
C15
D15
D3
G4
G3
E1
B3
C4
C5
A4
B9
B10
A9
B11
C2
D16
B15
B14
C12
F3
G2
V2
Y1
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
ROM_ADDR0
ROM_ADDR1
ROM_ADDR2
ROM_ADDR3
ROM_ADDR4
ROM_ADDR5
ROM_ADDR6
ROM_ADDR7
ROM_ADDR8
ROM_ADDR9
ROM_ADDR10
ROM_ADDR11
ROM_ADDR12
ROM_ADDR13
ROM_ADDR14
ROM_ADDR15
ROM_ADDR16
ROM_ADDR17
ROM_ADDR18
ROM_ADDR19
ROM_ADDR20
ROM_ADDR21
ROM_ADDR22
ROM_ADDR23
ROM_ADDR24
ROM_ADDR25
ROM_ADDR26
ROM_ADDR27
ROM_ADDR28
ROM_ADDR29
ROM_ADDR30
ROM_ADDR31
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
Parity Pins - Not Used
AD0
P_PAR0
P_PAR1
P_PAR2
P_PAR3
SMI#
I2C_INT#
DMA Acks are strapping
DMA Channels - Not Used
3.3VC
R571
3.3K
10,12,16,17
3.3VC
3.3VC
R62
R77
3.3K
P_DMA_ACK0
P_DMA_ACK1
P_DMA_ACK2
P_DMA_ACK3
P_DMA_EOT_TC0
P_DMA_EOT_TC1
P_DMA_EOT_TC2
P_DMA_EOT_TC3
3.3K
3.3VC
R2
3.3K
P_OE#
R16
3.3K
3.3VC3.3VC 3.3VC
3.3VC3.3VC
R5
R22
3.3K
3.3K
R542
0
R603
0
10,16,17
7
7
7
7
R9
3.3K
3.3K
8 bit
P_CS0#
8 bit
P_CS1#
RS232_SELECT
32 bit
P_CS3#
HOST_SMI#
R543
0
HOST_I2C_INT#
CABLE_DETECT# 16
GPIO16 16
10
Bank 0 = Boot ROM
12,16
Bank 1 = USB / DUART
13,16
17
Bank 3 = Video Compressor
16
16
B
C
D
E
F
G
H
R570
R567
R5681KR569
1K
1K
1K
I
I
405GP PERIPHERAL BUS
PART NO.
02R1679
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
$9I3783
6 9
OUTSIDE MAX
INSIDE MAX
0.13
2.0
1/1SCALE:
TITLE
HARRIER
1-15-2003_14:44
DESIGNER
CHECKED
APPROVED
SHEET OF
Physical Design
Jeff Davis
Brandon EllisonJames Dalton
9
20
108754321
JJ
9612345 78 10
REL
A
SW1
B
2
MH3
3.3VC
3.3VC
R618
3.3K
POP
1
MH1MH2
3
12
U90
MAX6315US29D3-T
M_R_N
GND RESET_N
Vth=2.93
P/D_NUM=29L2394
VCC
140 mS
R619
4
3.3K
POP
PPC_RESET_N
5,6
04/01/02 - BJE - (Page 10) Synched with final Pass 1 of Management Module.
4/6/02 - JWD -Fixed address bit order
9/23/02 - JWD -Changed RTC data and clk pull-downs to pull-ups. Nopoped CE pull-down.
10/31/02 - RMK -Changed RTC Interupt to TIRQ_N
10/31/02 - RMK -Changed flash IBM part number to 02R1640, added coded part number 02R1641, removed socket
EC NO.DATEQTYREL FOR ASM
PART NO.
DEVELOPMENT NO. Q/M
A
B
C
Place caps within 25mils of module near power pin
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
U27
FEPROM4MX8
(BYTE MODE data)
45
(A0)
DQ15_A1
25
(A1)
A0
24
(A2)
A1
23
(A3)
A2
22
(A4)
A3
21
(A5)
A4
20
(A6)
A5
19
(A7)
A6
18
(A8)
A7
8
(A9)
A8
7
(A10)
A9
6
(A11)
A10
5
(A12)
A11
4
(A13)
A12
3
(A14)
A13
2
(A15)
A14
1
(A16)
A15
48
(A17)
A16
17
(A18)
A17
16
(A19)
A18
9
(A20)
A19
10
(A21)
A20
13
(UNDEFINED)
NC
12
RESET_N
14
WP_N
26
CE_N
28
OE_N
11
WE_N
VENDOR=ST_MICRO
VEN_P/D_NUM=M29W320DB70N6
FLASH
VCC
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
BYTE_N
RY_BY_N
GND0
GND1
37
ROM_DATA7
29
ROM_DATA6
31
ROM_DATA5
33
ROM_DATA4
35
ROM_DATA3
38
ROM_DATA2
40
ROM_DATA1
42
ROM_DATA0
44
30
32
34
36
39
41
43
47
15
P_READY
46
27
CODED_P/N=02R1641
SOCKET_P/N=0782822
SOCKET_DESC=MERITEC-980020-48-02
SOCKET_QTY=0
D
ROM_ADDR[0:31]
9,12,16,17
E
3.3VC
R458
F
PPC_NOT_READY_N
5,15
G
Pin 14 hi = 16K boot block not protected
Pin 14 Low = 16K boot block protected
User Guide - Section 16.6.2 - Boot ROM must be attached to Bank 0.
H
R122
R232
4.7K
1K
NOPOP
4.7K
9,16,17
9,12,16,17
ROM_ADDR31
ROM_ADDR30
ROM_ADDR29
ROM_ADDR28
ROM_ADDR27
ROM_ADDR26
ROM_ADDR25
ROM_ADDR24
ROM_ADDR23
ROM_ADDR22
ROM_ADDR21
ROM_ADDR20
ROM_ADDR19
ROM_ADDR18
ROM_ADDR17
ROM_ADDR16
ROM_ADDR15
ROM_ADDR14
ROM_ADDR13
ROM_ADDR12
ROM_ADDR11
ROM_ADDR10
FLASHWP_N
P_CS0#
9
P_OE#
P_R_W#
3.3VC
C493
Place within 100 mils of flash
10U
3.3VC
C507
C349
C93
10N
100N
ROM_DATA[0:31]
8 bit Data Bus - Per Shane's Request
R52
9,17
100
2.2N
9,12,16,17
12
5,7
5
5
AIRQ_INT_N
RTC_INT_N
FPGA_RTC
CLK
DIO
R623
2K
3V_BAT
R596
0
3.3VC
3.3VC
R599
R598
2K
100K
R602
CR1
1
3
2
DIO_BAT54C
C551
100K
100N
100K
PWR_RTC
30
C552
100N
U89R622
Place caps as close as possible
1
2
10
4
5
6
7
8
9
VENDOR=EPSON
VEN_P/D_NUM=RTC-9701JEB-0
VDD2
VEX
VDD
AIRQ_N
TIRQ_N
CE
CLK
DI
DO
RTC-9701JE
VSOJ20
13
GND_13
12
GND_12
3
FOE
11
FOUT
0.8uA @ 3V Typ. (6.85 Years with 48mAh battery)
C
D
E
F
G
H
I
I
FLASH / RTC
PART NO.
02R1679
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
$10I4602
6 9
OUTSIDE MAX
INSIDE MAX
0.13
2.0
1/1SCALE:
TITLE
HARRIER
1-15-2003_14:44
DESIGNER
CHECKED
APPROVED
SHEET OF
10
108754321
Physical Design
Jeff Davis
Brandon EllisonJames Dalton
20
JJ
9612345 78 10
EC NO.DATEQTYREL FOR ASM
REL
A
PART NO.
DEVELOPMENT NO. Q/M
A
B
C
3.3VC
D
C3
0.1U
E
L1
BLM21P300S
0.1U
PWR3_3VC_CY2292
C4
R36
R32 10K
R23 10K
10K
11
11
10KR35
25MHZ_XTALIN
25MHZ_XTALOUT
RES_2292_OE
RES_CY2292_S0
RES_CY2292_S1
RES_CY2292_S2
U7
2
VCC2
14
VCC14
4
XTALIN
5
XTALOUT
16
SHUTDOWN_N_OE
12
S0
13
S1
15
S2_SUSPEND_N
CY2292
P/D_NUM=77P0247
CY2292ASL-019
XBUF
CPUCLK
CLKA
CLKB
CLKC
CLKD
GND3
GND11
6
8
10
9
1
7
3
11
RES_CLK25M
RES_CLK33M
RES_CLK12M
RES_CLK23.5M
C558
15P
R38
R37 40.2
R39 40.2
R637 40.2
C21
C14
C19
15P
15P
15P
NOPOP
NOPOP
NOPOP
40.2
NOPOP
NOPOP
CLK_25MHZ_BCM
33MHZ_405GP
USB_12MHZ
DUART_XTAL1
405GP CLOCK = 33.1776MHz
15
5
16
12
04/01/02 - BJE - (Page 11) Synched with final Pass 1 of Management Module.
04/01/02 - BJE - (Page 11) New Clock chip to be entered by James Dalton
10/31/02 - JWD - (Page 11) Added 23.5 MHz frequency for the duart to the clock driver
(1.8432MHz*2*9)
DUART_XTAL1 = 23.5 MHz
B
C
D
E
3.3VC
C10
R63
150
NOPOP
25MHZ_XTALOUT
33P
11
CLOCK OSCILLATOR & DRIVER
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
6 9
OUTSIDE MAX
INSIDE MAX
0.13
2.0
PART NO.
02R1679
TITLE
1/1SCALE:
HARRIER
1-15-2003_14:44
DESIGNER
CHECKED
APPROVED
SHEET OF
Verified by Cypress
11
108754321
Physical Design
Jeff Davis
Brandon EllisonJames Dalton
20
F
25MHZ_XTALIN
11
G
H
I
Keep crystal circuit close to CY2292
C6
33P
R4
100K
Y1
14
25M
Hz
EPSON
MA-306_25.0000M-C
F
G
H
I
JJ
9612345 78 10
EC NO.DATEQTYREL FOR ASM
REL
A
3.3VC
R630
2K
PART NO.
DEVELOPMENT NO. Q/M
A
POP
14.7456M Hz
33P
R631
1MEG
Y?
12
VEN_P/D_NUM=CS1014.7456MABJTR
VENDOR=CITIZEN
B
C
D
E
11,12
DUART_XTAL1
C556
NOPOP
DUART_XTAL2
12
Make DUART_XTAL* nodes as short as possible!!!
Keep crystal circuit close to DUART
C557
33P
9,10,12,16,17
ROM_ADDR[0:31]
ROM_ADDR12 = 0, selects duart
= 1, selects USB
9,16
ROM_ADDR12
P_CS1#
9,10,12,16,17
9,10,16,17
U79
12
13
3.3VC
14
7
ROM_ADDR[0:31]
ROM_DATA[0:31]
11
9,10,16,17
12
3.3VC
ROM_ADDR31
ROM_ADDR30
ROM_ADDR29
ROM_ADDR28
ROM_DATA7
ROM_DATA6
ROM_DATA5
ROM_DATA4
ROM_DATA3
ROM_DATA2
ROM_DATA1
ROM_DATA0
DUART_CS#
P_R_W#
DUART_INT_N
U99
B
C
42
VCC_42
19
VCC_19
28
A0
27
A1
26
A2
11
A3
44
D0
45
D1
46
D2
47
D3
48
D4
1
D5
2
D6
3
D7
10
CS#
15
R/W#
30
IRQ#
COM4
DUART
TXA
RXA
RTSA#
CTSA#
DTRA#
DSRA#
CDA#
RIA#
OP2A#
7
5
33
38
34
39
40
41
32
COM4_TX
COM4_RX
COM4_RTS#
COM4_CTS#
COM4_DTR#
COM4_DSR#
COM4_CD#
COM4_RI#
16
16
16
16
16
16
16
3.3VC
4.7K
R640
D
E
3.3VC
R632
U1
9
10
3.3K
DUART_INT_N
RTC_INT_N
12
10
5,14,16,17
8
3.3VC
14
7
F
RTC_DUART_INT_N
5
LV08_TSSOP14_65MM
G
H
I
3.3VC3.3VC
POP
POP
4.7K
NOPOP
4.7K
4.7K
R635
R633
NOPOP
4.7K
R636
R634
PERIPHERAL_RESET_N
11,12
12
DUART_XTAL1
DUART_XTAL2
R645
43
TXRDYA#
31
RXRDYA#
6
TXRDYB#
18
RXRDYB#
13
XTAL1
14
R644
0
0
XTAL2
12
PWRSAVE
25
CLKSEL
37
HDCNTL#
36
RESET#
24
16/68#
17
GND
VENDOR=EXAR
VEN_P/D_NUM=XR16L2751CM
COM5
TXB
RXB
RTSB#
CTSB#
DTRB#
DSRB#
CDB#
RIB#
OP2B#
3.3VC
J28
1
8
4
22
23
35
20
16
21
9
COM5_TX
COM5_RX
COM5_RTS#
COM5_CTS#
COM5_DTR#
COM5_DSR#
COM5_CD#
COM5_RI#
13
13
13
13
16
16
16
16
COM1_TX
5,7
COM1_RTS#
5,7
COM1_RX
5
COM1_CTS#
5
C1
2
C2
3
C3
4
C4
5
C5
6
C6
VENDOR=MOLEX
VEN_P/D_NUM=53780-0690
F
G
H
I
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
6 9
OUTSIDE MAX
INSIDE MAX
0.13
2.0
PART NO.
02R1679
TITLE
1/1SCALE:
HARRIER
1-15-2003_14:44
DESIGNER
CHECKED
APPROVED
SHEET OF
12
108754321
Physical Design
Jeff Davis
Brandon EllisonJames Dalton
20
JJ
9612345 78 10
REL
A
04/01/02 - BJE - (Page 12) Synched with final Pass 1 of Management Module.
04/01/02 - BJE - (Page 12) Adjusted a few cap values.
04/01/02 - BJE - (Page 12) Swapped pop options on R21 & R20.
04/11/02 - BJE - (Page 12) Added all COM signals for Modem use.
04/11/02 - BJE - (Page 12) Moved Debug Port to COM1
04/11/02 - BJE - (Page 12) Added BERG header for 485/232 selection
01/15/03 - JWD - added pull-up to R485_A_RTS_N
EC NO.DATEQTYREL FOR ASM
PART NO.
DEVELOPMENT NO. Q/M
A
B
C
08/17/02 - JWD - (Page 12) Moved RS232 Driver to Crow.
RS232_SELECT
D
E
F
9,16
COM5_RX
12
COM5_CTS#
12
COM5_RTS#
12
COM5_TX
12
May be able to second source with Pericom PI3B3257
VEN_P/D_NUM=SN74CBTLV3257PWR
3.3VC
16
PWR
4
1A
7
2A
9
3A
12
4A
GND
OE
1B1
1B2
2B1
2B2
3B1
3B2
4B1
4B2
8
VENDOR=TI
U96
15
1
S
COM5_232RX
2
3
COM5_232CTS#
5
6
COM5_232RTS#
11
10
COM5_232TX
14
13
4.7N
R457
3.3VC
27K
C246
220P
485_N_BUS_A
485_P_BUS_A
RS 485 Bus A
16
16
16
16
16
16
R237
1K
R485_A_RTS_N
3.3VC
R?
10K
1
AHC04sop
SIGNAL=3.3VC;14
SIGNAL=GND;7
U34
R485
C96
3.3VC
100N
R456
27K
R158
120
C52
U5
NOPOP
0
2
485_A_RX
485_A_CTS_N
485_A_RTS
485_A_TX
18
RO VCC
2
RE_N
3
DE
4
DI
LTC1480
GND
7
-
B
6
+
A
5
SOIC8
B
C
D
E
F
G
3.3VC
R454
27K
C97
3.3VC
100N
R455
27K
R157
120
C51
4.7N
C241
220P
485_N_BUS_B
485_P_BUS_B
RS 485 Bus B
16
16
Keep inductor/capacitor filter near connector
RS485 DRIVERS
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
6 9
OUTSIDE MAX
INSIDE MAX
0.13
2.0
PART NO.
02R1679
TITLE
1/1SCALE:
HARRIER
1-15-2003_14:44
DESIGNER
CHECKED
APPROVED
SHEET OF
13
108754321
Physical Design
Jeff Davis
Brandon EllisonJames Dalton
20
H
NOPOP
R483
0
COM2_RTS#
5,7
I
U34
AHC04sop
SIGNAL=3.3VC;14
SIGNAL=GND;7
43
COM2_RX
5
COM2_CTS#
5
COM2_TX
5,7
R238
1K
U6
18
RO VCC
2
RE_N
3
DE
4
DI
LTC1480
GND
7
-
B
6
+
A
5
SOIC8
G
H
I
JJ
9612345 78 10
REL
A
3.3VC
10K
R514
I2C_SELECT
5
B
SEEPROM = 0, HOST = 1
3.3VC
04/01/02 - BJE - (Page 13) Synched with final Pass 1 of Management Module.
10/31/02 - RMK - (Page 14) Added nopop resistors between D and S1 on U94 and U95 to test if the switches are needed
EC NO.DATEQTYREL FOR ASM
PART NO.
DEVELOPMENT NO. Q/M
A
B
3.3VC
SCL
VCC
R17
C
D
I2C_SCL
5
5
I2C_SDA
R495
POP
10K
10K
POP
3.3VC
FROM 405GP
3.3VC
J1
1
C1
E
R604
POP
3.3VC
R605
2K
2K
POP
F
G
2
C2
3
C3
4
C4
CONN1X4
MAIN I2C BUS Debug Connector
NOPOP
5
IN
6
D
4
VENDOR=ST_MICRO
VEN_P/D_NUM=STG3157CTR
SDA
VCC
5
IN
6
D
4
VENDOR=ST_MICRO
VEN_P/D_NUM=STG3157CTR
R638
3.3VC
VCC
5
IN
6
D
4
0
SCL
IN = 1
IN = 0
IN = 1
IN = 0
NOPOP
IN = 1
IN = 0
U92
TO HOST
S1
1
S2
3
2
GND
U93
S1
1
S2
3
2
GND
U94
S1
1
S2
3
2
GND
HOST_I2C_SCL
HOST_I2C_SDA
3.3VC
R606
POP
100K
R607
POP
R609
POP
100K
16
16
3.3VC
3.3VC
R608
IO_OVCC
IO_1
IO_2
IO_3
IO_4
IO_5
IO_6
IO_7
GND
100N
C553
3.3VC3.3VC3.3VC3.3VC
R79
R78
R93
R89
R109
R96
R112
R111
100K
100K
100K
100K
100K
100K
100K
POP
POP
POP
POP
POP
POP
POP
616
7
9
10
11
12
13
14
8
These pins are used identify the host that harrier is plugged into.
100K
POP
HOST_ID0
HOST_ID1
HOST_ID2
HOST_ID3
HOST_ID4
HOST_ID5
HOST_ID6
HOST_ID7
16
16
16
16
16
16
16
16
Each host will have a unique ID
100K
100K
POP
VCC A0
81
WP
SEEPROM_SCL
SEEPROM_SDA
5,12,16,17
PERIPHERAL_RESET_N
3.3VC
7
SDA
5
SERIAL-I2C
VENDOR=ST_MICRO
VEN_P/D_NUM=M24C64-WMN6T
EEPROM
3
4
5
15
1
2
A1
A2SCL
GND
A0
A1
A2
RESET_N
SCL
SDA
U91
2
36
4
U3
PCA9557
TSSOP16
C
D
E
F
G
Crows = 0
Magpie = 1
VENDOR=ST_MICRO
USB_SCL
16
USB_SDA
H
16
3.3VC
FROM EZUSB
I
$14I3841
VEN_P/D_NUM=STG3157CTR
SDA
VCC
5
IN
6
D
4
VEN_P/D_NUM=STG3157CTR
IN = 1
IN = 0
VENDOR=ST_MICRO
R639
0
NOPOP
U95
S1
1
S2
3
2
GND
I2C SEEPROM AND SWITCHES
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
6 9
OUTSIDE MAX
INSIDE MAX
0.13
2.0
1/1SCALE:
PART NO.
TITLE
HARRIER
1-15-2003_14:44
DESIGNER
CHECKED
APPROVED
SHEET OF
02R1679
Physical Design
Jeff Davis
Brandon EllisonJames Dalton
14
20
108754321
H
I
JJ
9612345 78 10
REL
A
TO DO: Get Broadcoms Approval of Layout
EC NO.DATEQTYREL FOR ASM
PART NO.
DEVELOPMENT NO. Q/M
A
B
3.3VC
C520
C519
3.3VC
+1%/-1%
49.9
R34
+5%/-5%
1N
R612
0
+1%/-1%
49.9
R33
+5%/-5%
1N
3.3VC
100N
3
20
2
55
27
28
22
46
8
1
32
29
24
40
54
63
45
7
Place all power caps as close to BCM5221 as possible.
3.3VC
C20
C518
C5
C17
100N
3.3VC
place within one inch of BCM5221
10U
2.2U
C1
C15
100N
MATCHING LENGTHS, SAME LAYER FOR PAIRS (50 Ohm SE, 100 Ohm Diff)
R613
R614
0
R615
0
0
C18
10N
2.2UC2100N
C16
10N
ENET_PHY_TX
ENET_PHY_TX_N
ENET_PHY_RX
ENET_PHY_RX_N
16
16
16
16
Please refer to "General Layout Notes" pg17 of BCM5221_apnote.pdf in /harrier/reference/
ENET_PHY_RX_CLK
5
C13
5
5
100P
5
5
5
5
NOPOP
+1%/-1%
49.9
R15
C
CLK_25MHZ_BCM
11
ENET_PHY_TX_CLK
5
ENET_PHY_TXD3
100P
5,7
ENET_PHY_TXD2
5,7
ENET_PHY_TXD1
5,7
ENET_PHY_TXD0
5,7
ENET_PHY_TX_EN
5,7
ENET_PHY_TX_ERR
5,7
C12
NOPOP
D
U2
+1%/-1%
4.7K
4.7K
NOPOP
R25
NOPOP
R24
4.7K
4.7K
1.27K
R28
R29
E
F
G
H
Place RDAC resistor as close as possible to BCM5221
NOPOP
NOPOP
3.3VC
4.7K
4.7K
R26
R27
NOPOP
NOPOP
5,10
R8
16
16
3.3VC
PPC_NOT_READY_N
RECEIVE_TP
ENET_PHY_RDAC
ENET_PHY_LNK_LED_N
ENET_PHY_SPD_TP
XMT_LED_TP
ENET_PHY_ACT_LED_N
JTAG_EN_TP
4.7K
NOPOP
R30
4.7K
NOPOP
R31
9
RESET_N
17
ENERGY_DET
23
RDAC
35
LNKLED_N
36
SPDLED_N
34
XMTLED_N
33
RCVLED_N
64
JTAG_EN
10
PHYAD0
11
PHYAD1
12
PHYAD2
13
PHYAD3
14
PHYAD4
39
FDX
37
F100
38
ANEN
21
SD+
19
SD-
15
TESTEN
18
MII_EN
16
LOW_PWR
BCM5221KPT TQFP64_5MM
ENET_PHY_MDC
5
ENET_PHY_MDIO
5
ENET_PHY_COL
5
ENET_PHY_CRS
5
R11
33.2
----68 Ohm characteristic impedance-----
52565758596053
TXER
TXEN
TXD0
TXD1
TXD2
TXD3
TXC
BCM5221
MDC
MDIO
COL
4241616251494847444350
3.3VC
-------------68 Ohm characteristic impedance--------------
R19
1.5K
POP
R14
R13
10K
10K
NOPOP
NOPOP
place 1nF capacitors as close as possible to 49.9 ohm resistors
4.7K
R511
REF_CLK
CRS/CRS_DV
456
XTALO
RXER
RXDV
262530
31
XTALI
RD+
TD-
TD+
RXD0
RXD1
RXD2
R1
22.1
RXD3
RD-
RXC
R12
33.2
49.9 ohm resistors close to PHY
+1%/-1%
49.9
R18
REGDVDD
REGAVDD
DVDD_2
DVDD_55
AVDD_27
AVDD_28
BIASVDD
OVDD_46
OVDD_8
OVDD_1
AGND_32
AGND_29
BIASGND
DGND_40
DGND_54
DGND_63
DGND_45
XTALGND
ENET_PHY_RXD3
ENET_PHY_RXD2
ENET_PHY_RXD1
ENET_PHY_RXD0
ENET_PHY_RX_DV
ENET_PHY_RX_ERR
B
C
D
E
F
G
H
I
I
ETHERNET PHY
PART NO.
02R1679
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
6 9
OUTSIDE MAX
INSIDE MAX
0.13
2.0
1/1SCALE:
TITLE
HARRIER
1-15-2003_14:44
DESIGNER
(Broadcom) Bill Fuller
CHECKED
APPROVED
SHEET OF
Physical Design
James Dalton Brandon Ellison
TO DO: verify P.D. with Broadcom
15
Jeff Davis
19
108754321
JJ
04/03/02 - BJE - (Page 15) Added Condor 2000 Connections
04/07/02 - JWD - (Page 15) Added system on detection
A
04/08/02 - JWD - (Page 15) Moved differential signals around on the SMP connectors
08/16/02 - JWD - (Page 15) Removed R514, Peripheral_Reset_N is already pulled up at R515
08/16/02 - JWD - (Page 15) Moved SEEPROM to page 13
09/23/02 - JWD - (Page 15) Added USB switches.
09/23/02 - RMK - (Page 15) Added pull-up to USB_HUB_INT
10/31/02 - RMK - (Page 16) Made USB_CS# from logical and of P_CS1# and ROM_ADDR12
10/31/02 - JWD - (Page 16) Added com4, changed name of GPIO18 to RS232_DETECT
10-30-02-JWD-P_EXT_ACK# is used to detect BIST mode after reset.
B
C
D
E
10-30-02-JWD-P_EXT_ACK# is used to detect BIST mode after reset.
F
GPIO's 1 and 16 can be used for system specific requirements.
G
3.3VC
R544
10K
H
POP
9
I
16
SYS_ON
NOPOP
9612345 78 10
EC NO.DATEQTYREL FOR ASM
PART NO.
REL
U97
GND
S1
IN = 1
1
S2
3
2
IN = 0
USB_EXT_N
16
USB_INT_N
16
3.3VC
VCC
5
IN
6
D
4
USBD_N
Internal = 0, External = 1
16
EXT_USB_PWR_GOOD
VENDOR=ST_MICRO
VEN_P/D_NUM=STG3157CTR
U98
3.3VC
J25
KEY
71
COM3_RX
16
COM3_TX
16
COM3_CTS#
16
COM3_RTS#
16
HOST_ID0
14
HOST_ID1
14
HOST_ID2
14
HOST_ID3
14
HOST_ID4
14
HOST_ID5
14
HOST_ID6
14
HOST_ID7
14
COM4_RTS#
12
USB_INT_P
16
USB_INT_N
16
RS232_SELECT9,13
P_EXT_ACK#5,7
IRQ4
5,7
9
12
12
13
13
13
12
12
13
12
12
14
14
5
9
5
5
5
HOST_PCI_RST_N
RS232_DETECT
GPIO1
GPIO16
COM5_DTR#
COM5_DSR#
COM5_232TX
COM5_232CTS#
COM5_232RX
COM5_RI#
COM5_CD#
COM5_232RTS#
COM4_TX
COM4_RX
HOST_I2C_SDA
HOST_I2C_SCL
HOST_PWRGD/RST#
HOST_PWR_REQ#
HOST_I2C_INT#
CABLE_DETECT#
12
12
9
R3
1K
12
COM4_CTS#
COM4_DTR#
HOST_SMI#
PCI3_3V
COM4_DSR#
C71
72
C72
73
C73
74
C74
75
C75
76
C76
77
C77
78
C78
79
C79
80
C80
81
C81
82
C82
83
C83
84
C84
85
C85
86
C86
87
C87
88
C88
89
C89
90
C90
91
C91
92
C92
93
C93
94
C94
95
C95
96
C96
97
C97
98
C98
99
C99
100
C100
101
C101
102
C102
103
C103
104
C104
105
C105
106
C106
107
C107
108
C108
109
C109
110
C110
111
C111
112
C112
113
C113
114
C114
115
C115
116
C116
117
C117
118
C118
119
C119
120
C120
121
C121
122
C122
123
C123
124
C124
125
C125
126
C126
127
C127
128
C128
129
C129
130
C130
131
C131
132
C132
133
C133
134
C134
135
C135
136
C136
137
C137
138
C138
139
C139
140
C140
LCD Port (Raw Digital Video)
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
C41
C42
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
C53
C54
C55
C56
C57
C58
C59
C60
C61
C62
C63
C64
C65
C66
C67
C68
C69
C70
1
C1
2
C2
3
C3
4
C4
5
C5
6
C6
7
C7
8
C8
9
C9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
4
RN62
3
RN62
2
RN62
1
RN62
4
RN63
3
RN63
2
RN63
1
RN63
4
RN64
3
RN64
2
RN64
1
RN64
R536
220
4
RN65
3
RN65
2
RN65
1
RN65
4
RN66
3
RN66
2
RN66
1
RN66
4
RN67
3
RN67
2
RN67
1
RN67
ERROR_LED_BUF
ENET_PHY_RX_N
ENET_PHY_RX
ENET_PHY_TX_N
ENET_PHY_TX
ENET_PHY_LNK_LED_N
ENET_PHY_ACT_LED_N
5
220
6
220
7
220
8
220
5
220
6
220
7
220
8
220
5
220
6
220
7
220
8
220
5
220
6
220
7
220
8
220
5
220
6
220
7
220
8
220
5
220
6
220
7
220
8
220
485_N_BUS_B
485_P_BUS_B
485_N_BUS_A
485_P_BUS_A
COM4_CD#
DV_RED6
DV_RED7
DV_RED2
DV_RED3
DV_RED4
DV_RED5
DV_GRN6
DV_GRN7
DV_BLU7
DV_HSYNC
DV_VSYNC
DV_DE
DV_CLK
DV_RED1
DV_GRN3
DV_GRN4
DV_GRN5
DV_BLU1
DV_BLU4
DV_GRN1
DV_GRN2
DV_BLU3
DV_BLU6
DV_BLU2
DV_BLU5
13
13
13
13
5
12
15
15
15
15
15
15
17
17
17
17
17
17
17
17
17
17
17
17
17,18
17
17
17
17
17
17
17
17
17
17
17
17
3V_BAT
9,10,12,17
ROM_DATA[0:31]
USB_EXT_P
16
USB_INT_P
16
16
16
16
16
S1
IN = 1
1
S2
3
2
IN = 0
GND
VENDOR=ST_MICRO
VEN_P/D_NUM=STG3157CTR
ROM_DATA7
ROM_DATA6
ROM_DATA5
ROM_DATA4
ROM_DATA3
ROM_DATA2
ROM_DATA1
ROM_DATA0
COM3_RX
COM3_TX
COM3_CTS#
COM3_RTS#
RN57
RN57
RN57
RN57
RN56
RN56
RN56
RN56
10K
10K
10K
10K
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SYS_ON
****
16
3.3VC
R627
VCC
5
IN
6
D
USBD
4
16
5.1K
R624
10K
USB_EXT_N
16
USB_EXT_P
16
3.3VC
C543
C542
2.2U
100N
U78
4
5
RN59
3
6
RN59
2
7
RN59
1
8
RN59
4
5
RN58
3
6
RN58
2
7
RN58
1
8
RN58
4
5
RN61
3
6
RN61
2
7
RN61
1
8
RN61
4
5
RN60
3
6
RN60
2
7
RN60
1
8
RN60
4
5
0
3
6
0
2
7
0
1
8
0
4
5
0
3
6
0
2
7
0
1
8
0
1
8
RN54
2
7
RN54
3
6
RN54
4
5
RN54
1
8
RN55
2
7
RN55
3
6
RN55
4
5
RN55
R527
B_OUT_FLAG
0
**
VENDOR=CYPRESS
VEN_P/D_NUM=CY7C64613-80NC
11
12
13
14
15
16
17
18
47
48
49
50
51
52
53
54
68
69
70
71
73
74
75
76
30
31
32
33
34
35
36
37
55
44
45
46
56
66
67
77
78
79
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
D0
PB1
D1
PB2
D2
PB3
D3
PB4
D4
PB5
D5
PB6
D6
PB7
D7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
B_OUT_FLAG
PE0
NC_44
NC_45
NC_46
NC_56
NC_66
NC_67
NC_77
NC_78
NC_79
CY7C64613-80NC
FIFO "A"
A_IN_FLAG
B_IN_FLAG
A_OUT_FLAG
ASEL
BSEL
AOE
SLRW
SLRD
PQFP_80
AVCC
VCC_21
VCC_41
VCC_61
VCC_1
USBD
USBD_N
XOUT
WAKEUP_N
CLKOUT
XCLK
XCLKSEL
DISCON_N
RESET_N
RDY0
RDY1
RDY2
RDY3
RDY4
RDY5
RESERVED_9
RESERVED_22
RESERVED_24
AGND
GND_10
GND_20
GND_29
GND_40
GND_43
GND_60
GND_72
GND_80
5
21
41
61
1
2
SCL
3
SDA
39
38
6
XIN
7
4
19
***
59
23
28
42
62
CTL0
57
CTL1
58
CTL2
63
64
65
0
25
26
27
9
22
24
8
10
20
29
40
43
60
72
80
R526
1K
R525
USB_LATCH_EMPTY
R532
0
R533
10K
R516
USB_HUB_INT
P_WE#
P_OE#
16
BSEL
BOE
1.5K
USB_CS#
3.3VC
USB_SCL
USB_SDA
USBD
USBD_N
USB_12MHZ
5
5,16
16
16
4,17
9,10,17
_____BOE
PerWE
_____
PerOE
6
C521
3.3VC
14
7
16
16
11
NOPOP
1U
U79
4
5
**Select PE[7..0] alternate function and make PE[7..0] outputs. (per data sheet pg25)
***Turn off the CLKOE bit in firmware so the CPU clock is not driven on CLKOUT
****If system is off, Remove power from USB pull-up.
J27
1
2
3
4
5
VEN_P/D_NUM=440247-2
VENDOR=AMP
PERIPHERAL_RESET_N
3.3VC
U79
14
9
8
10
7
ROM_ADDR12#
P_CS1#
VBUS
D-
D+
ID
GND
USB Mini-B
SH1
SH2
SH3
SH4
14
14
3.3VC
14
65
7
3.3VC
14
21
7
9,12
5,16
U75
U75
KEY
VENDOR=MOLEX
VEN_P/D_NUM=53467-1409
SMP Connector
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
OUTSIDE MAX
INSIDE MAX
0.13
2.0
6 9
1/1SCALE:
DEVELOPMENT NO. Q/M
SH1
SH2
SH3
SH4
USB_HUB_INT
5,12,14,17
BSEL
16
USB_CS#
P_R_W#
__
PerR/W
16
9,10,12,17
ROM_ADDR[0:31]
ROM_ADDR12
ROM_ADDR12 = 0, selects duart
= 1, selects USB
PART NO.
02R1679
TITLE
HARRIER
1-15-2003_14:44
DESIGNER
CHECKED
APPROVED
James Dalton Brandon Ellison
(Cypress) Ernie Buterbaugh
Zin Thein Kyaw
SHEET OF
R534
16
9,10,12,17
16
3.3VC
R625
R626
10K
BOE
108754321
10K
10K
NOPOP
3.3VC3.3VC
10K
R535
Physical Design
Jeff Davis
20
A
B
C
D
E
F
G
H
I
JJ
9612345 78 10
EC NO.DATEQTYREL FOR ASM
REL
ROM_DATA[0:31]
ROM_ADDR[0:31]
J26
2_5V
VEN_P/D_NUM=22-28-4063
VENDOR=MOLEX
NOPOP
9,10,12,16
04/11/02 - BJE - (Page 16) Added SPI bus option to Xilinx bus
08/14/02 - JWD - (Page 16) Removed configurator, added GPIO to PROG
08/16/02 - JWD - (Page 16) Removed pullup on POE# (it is pulled up at 405GP)
08/16/02 - JWD - (Page 16) Added Bank Enables and P_R_W#
09/23/02 - RMK - (Page 16) Added ibm part number (77P0174) to xilinx XC2S150
9,10,12,16
1
VCC
2
MS
3
CK
4
D1
5
D0
6
GND
VCC12
F10
F9
GND7
VCC11
F7
GND6
VCC02
F6
GND5
VCCO_03
E8F8E9
VCC01
GND4
VCCO_47
GND2
GND3
A16B2B15
A1
17
GND1
17
T10
ROM_DATA31
R11
ROM_DATA30
M11
ROM_DATA29
T11
ROM_DATA28
R16
ROM_DATA27
M14
ROM_DATA26
L14
ROM_DATA25
M15
ROM_DATA24
L12
ROM_DATA23
P16
ROM_DATA22
L13
ROM_DATA21
N16
ROM_DATA20
M16
ROM_DATA19
K14
ROM_DATA18
L16
ROM_DATA17
K13
ROM_DATA16
L15
ROM_DATA15
K12
ROM_DATA14
K16
ROM_DATA13
J16
ROM_DATA12
J14
ROM_DATA11
K15
ROM_DATA10
J15
ROM_DATA9
H16
ROM_DATA8
H14
ROM_DATA7
H15
ROM_DATA6
J13
ROM_DATA5
G16
ROM_DATA4
H13
ROM_DATA3
G14
ROM_DATA2
G15
ROM_DATA1
G12
ROM_DATA0
F16
ROM_ADDR31
G13
ROM_ADDR30
F15
ROM_ADDR29
E16
ROM_ADDR28
F14
ROM_ADDR27
D16
ROM_ADDR26
F12
ROM_ADDR25
E15
ROM_ADDR24
A8
A7
A5
A4
A10
A9
A3
OE
B12
D11
C9
B10
B8
C15
D3
C4
A15
B14
R3
M2
P2
M1
N3
M0
TST_MS
TSK_CK
TST_D1
TST_D0
CPU I/F
GCK2_SYSCLK
SD10
SD11
SD12
SD13
SD14
SD15
SD16
SD17
SD18
SD19
SD20
SD21
SD22
SD23
SD24
SD25
SD26
SD27
SD28
SD29
SD30
SD31
R/W#
CSEL
PERWE
RDY
RESET
GCK3
XO3
TMS
TCK
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
BE3
BE2
BE1
BE0
TD1
TD0
2_5V
10K
R530
R531
0
NOPOP
17
VCCX2
A
VCCO_03
VCCO_47
B
C539
C
C526
3.3VC
IND2P_FE_BLM21A121SPT
100N
1U
2_5V
IND2P_FE_BLM21A121SPT
C530
D
100N
3.3VC
E
IND2P_FE_BLM21A121SPT
C528
100N
C540
F
1U
2_5V
IND2P_FE_BLM21A121SPT
C532
G
100N
H
5
I
5
5
5
5,7
C589
Stitching caps required for split plane.
100N
C590
VCCX2
VCCX1
100N
200mA
L44
ohms
120
C525
C535
100N
200mA
L46
ohms
120
C537
C529
100N
200mA
L45
ohms
120
C527
C536
100N
200mA
L47
ohms
120
C538
C531
100N
R100
R107
R592
POP
R101
0
POP
0
POP
0
X_DOUT
X_CCLK
X_INIT
X_DONE
X_PROG
0
R108
100N
100N
0
100N
100N
U80
DV_RED1
16
DV_RED2
16
DV_RED3
16
DV_RED4
16
DV_RED5
16
DV_RED6
16
DV_RED7
16
DV_GRN1
16
16
16
16
16
16,18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
16
16
16
16
16
16
16
16
16
16
16
16
DV_GRN2
DV_GRN3
DV_GRN4
DV_GRN5
DV_GRN6
DV_GRN7
DV_BLU1
DV_BLU2
DV_BLU3
DV_BLU4
DV_BLU5
DV_BLU6
DV_BLU7
DV_HSYNC
DV_VSYNC
DV_DE
DV_CLK
COMP_SRA_11
COMP_SRA_10
COMP_SRA_9
COMP_SRA_8
COMP_SRA_7
COMP_SRA_6
COMP_SRA_5
COMP_SRA_4
COMP_SRA_3
COMP_SRA_2
COMP_SRA_1
COMP_SRA_0
COMP_SRBA1
COMP_SRBA0
COMP_SRDQMH
COMP_SRDQML
COMP_SRD_0
COMP_SRD_1
COMP_SRD_2
COMP_SRD_3
COMP_SRD_4
COMP_SRD_5
COMP_SRD_6
COMP_SRD_7
COMP_SRD_8
COMP_SRD_9
COMP_SRD_10
COMP_SRD_11
COMP_SRD_12
COMP_SRD_13
COMP_SRD_14
COMP_SRD_15
COMP_SRRAS-
COMP_SRCAS-
COMP_SRWE-
COMP_SRCKE
COMP_SRCS-
COMP_SRCLK
VCCO_03
17
C23
10U
VCCX1
17
C555
10U
VCCO_47
17
C22
10U
VCCX2
17
C554
10U
3.3VC
10K
R591
POP
POP
10K
R588
10K
R528
10K
R590
10K
R589
B3
RED1
A11
RED2
C2
RED3
A2
RED4
B1
RED5
E3
RED6
D2
RED7
A6
GRN1
A12
GRN2
C1
GRN3
F3
GRN4
E2
GRN5
E4
GRN6
D1
GRN7
B7
BLU1
E11
BLU2
E1
BLU3
F2
BLU4
G3
BLU5
F1
BLU6
F4
BLU7
F5
HSYNC
G2
VSYNC
H3
DE
N8
VCLK_GCK0
G4
SRA11
H2
SRA10
G5
SRA9
H4
SRA8
G1
SRA7
J2
SRA6
H1
SRA5
J4
SRA4
J1
SRA3
J3
SRA2
K5
SRA1
K2
SRA0
K1
SRBA1
L1
SRBA0
SRDQMH
SRDQML
SRD0
SRD1
SRD2
SRD3
SRD4
SRD5
SRD6
SRD7
SRD8
SRD9
SRD10
SRD11
SRD12
SRD13
SRD14
SRD15
SRRAS
SRCAS
SRWE
SRCKE
SRCS
SRCLK
GCK1
DIN
CCLK
INIT
DONE
PROG
SDRAM I/F
L2
K4
M1
L4
M2
L3
N1
P1
L5
N2
M4
R1
M3
N5
T2
P5
T3
T4
M6
T5
N6
R5
P6
R6
R8
D14
D15
N15
R14
P15
VENDOR=XILINX
VEN_P/D_NUM=XC2S150-5FG256C
VCCX1
17
M12
N13
P14
VCC_12
VCC_11
M5
N4
P3
VCC_9
VCC_10
VCC_8
VCC_7
Digital Video I/F
XC2S150-5FG256C
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
T1
T16
R15
L6
L7
R2
L10
L11
K9
K10
K11
VCC_6
D13D4C14
E12
VCC_5
GND25
C3
E5
VCC_4
VCC_3
VCC_2
VCC_1
VCC72
GND20
GND21
GND22
GND23
GND24
J7J8J9
K6K7K8
J10
M8
H5
H6
J5
J6
VCC71
VCC62
GND17
GND18
GND19
H10
VCC61
VCC41
VCC42
VCC51
VCC5
GND14
GND15
GND16
GND13
G9
H7H8H9
G11
G10
H11
H12
J11
J12
L9M9L8
VCC21
VCC31
VCC22
VCC32
GND8
GND9
GND10
GND11
GND12
G6G7G8
F11
VIDEO COMPRESSOR
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
OUTSIDE MAX
INSIDE MAX
0.13
2.0
6 9
1/1SCALE:
PART NO.
DEVELOPMENT NO. Q/M
3.3VC
10K
R515
R10
3.3K
P_WBE3#
P_WBE2#
P_WBE1#
P_WBE0#
P_R_W#
P_CS3#
P_OE#
P_WE#
P_READY
PERCLK
PERIPHERAL_RESET_N
PART NO.
02R1679
TITLE
HARRIER
1-15-2003_14:44
DESIGNER
CHECKED
APPROVED
James Dalton Brandon Ellison
Mario Costa (Avocent)
SHEET OF
17
108754321
9
9
9
9
9,10,12,16
9
9,10,16
4,16
9,10
5
5,12,14,16
Physical Design
Jeff Davis
20
A
B
C
D
E
F
G
H
I
JJ
9612345 78 10
EC NO.DATEQTYREL FOR ASM
PART NO.
REL
A
JWD 4/6/02 Added caps, changed power symbol to 3.3VC
DEVELOPMENT NO. Q/M
A
9/23/02 RMK Changed micron part number to the full part number
B
B
3.3VC
C
1U
100N
10N
C
Place Caps as close as possible to SDRAM
C29
D
E
F
16,17
G
Termination resistor values seems high. Verify signal quality. Try lower values and compare.
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
COMP_SRA_11
COMP_SRA_10
COMP_SRA_9
COMP_SRA_8
COMP_SRA_7
COMP_SRA_6
COMP_SRA_5
COMP_SRA_4
COMP_SRA_3
COMP_SRA_2
COMP_SRA_1
COMP_SRA_0
COMP_SRBA1
COMP_SRBA0
COMP_SRDQMH
COMP_SRDQML
COMP_SRCS-
COMP_SRCLK
COMP_SRCKE
COMP_SRWE-
COMP_SRCAS-
COMP_SRRAS-
DV_CLK
RN35
100
RN34
100
RN33
100
RN33
100
RN42
100
RN32
100
RN31
100
RN32
27
100
RN35
18
100
RN34
18
100
RN33
45
100
RN32
18
100
45
RN42
100
36
RN31
100
R593
NOPOP
0
RN35
18
100
RN35
36
45
100
RN34
36
100
RN33
27
36
100
RN32
36
100
RN31
45
100
27
RN42
45
100
27
RN31
18
100
U9
18
27
27
22
A10
34
A9
33
A8
32
A7
31
A6
30
A5
29
A4
26
A3
25
A2
24
A1
23
A0
21
BA1
20
BA0
39
DQMH
15
DQML
19
CS
38
CLK
37
CKE
16
WE
17
CAS
18
RAS
SDRAM1MX16X4B
VEN_P/D_NUM=MT48LC4M16A2TG-75
1
VDD_1
3
9
14
27
VDD_2
VDD_3
43
49
VDDQ_3
VDDQ_1
VDDQ_2
VDDQ_4
SDRAM
1Mx16x4b
TSOP54
VSS_3
VSSQ_3
VSSQ_1
VSSQ_2
VSSQ_4
46
52
VSS_1
VSS_2
284154612
DQ15A11
DQ14
DQ13
DQ12
DQ11
DQ10
NC1
NC2
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
5335
51
50
48
47
45
44
42
13
11
10
8
7
5
4
2
36
40
C28
C27
27
RN47
36
100
18
RN44
27
100
45
27
RN30
36
RN29
100
18
RN29
27
100
45
RN29
RN47
100
RN44
100
RN44
100
RN30
100
100
100
RN47
18
100
RN47
45
100
RN44
36
100
RN30
18
100
RN30
45
100
RN29
36
100
COMP_SRD_15
COMP_SRD_14
COMP_SRD_13
COMP_SRD_12
COMP_SRD_11
COMP_SRD_10
COMP_SRD_9
COMP_SRD_8
COMP_SRD_7
COMP_SRD_6
COMP_SRD_5
COMP_SRD_4
COMP_SRD_3
COMP_SRD_2
COMP_SRD_1
COMP_SRD_0
D
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
E
F
G
H
I
H
I
PART NO.
COMPRESSOR SDRAM 1MX16X4b
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
OUTSIDE MAX
INSIDE MAX
6 9
0.13
2.0
1/1SCALE:
TITLE
DESIGNER
CHECKED
APPROVED
02R1679
HARRIER
1-15-2003_14:44
James Dalton Brandon Ellison
Mario Costa (Avocent)
SHEET OF
18
108754321
Physical Design
Jeff Davis
20
JJ
9612345 78 10
8/7/02 JWD - (page 18) Removed Semtech added ST
A
REL
EC NO.DATEQTYREL FOR ASM
PART NO.
DEVELOPMENT NO. Q/M
A
B
B
2.5V for PPC 405GP and Xilinx@ 2 amp max "continuous"
C
D
E
3.3VC
C208
VENDOR=MURATA
VEN_P/D_NUM=GRM32ER61C106KC31L
10U
U85
1
EN
2
IN
GND_5
GND_6
GND_7
567
VEN_P/D_NUM=L6932D2TR.5
VENDOR=ST_MICRO
GND_8
8
OUT
PGOOD
3
4
C207
10U
100N
C46
C47
100N
100N
C88
2_5V
100N
VENDOR=AVX
VEN_P/D_NUM=0603YC104KAT2A
C89
C
D
E
F
G
H
I
PART NO.
POWER
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
6 9
OUTSIDE MAX
INSIDE MAX
0.13
2.0
1/1SCALE:
TITLE
DESIGNER
CHECKED
APPROVED
02R1679
HARRIER
1-15-2003_14:44
SHEET OF
James Dalton Brandon Ellison
19
108754321
Physical Design
Jeff Davis
20
F
G
H
I
JJ
9612345 78 10
REL
A
Decided not to reduce logic any more due to layout problems. Spare gate are good to have anyway!
EC NO.DATEQTYREL FOR ASM
PART NO.
DEVELOPMENT NO. Q/M
A
3.3VC
U1
14
4
6
B
5
7
LV08_TSSOP14_65MM
U79
1
2
3.3VC
14
3
7
B
Bypass Capacitors, place every inch
C
D
U34
5
AHC04sop
SIGNAL=3.3VC;14
SIGNAL=GND;7
U34
9
6
8
AHC04sop AHC04sop AHC04sop
SIGNAL=3.3VC;14
SIGNAL=GND;7
U34
11
10
SIGNAL=3.3VC;14
SIGNAL=GND;7
U34
13
12
SIGNAL=3.3VC;14
SIGNAL=GND;7
U75
3.3VC3.3VC
U75
14
89
7
14
1011
7
3.3VC
U75
14
1213
7
For cap check
3V_BAT2_5V3.3VC
VOLTAGE=2.5VOLTAGE=3.3
E
VOLTAGE=3
3.3VC
C559
C568
C579
100N
100N
100N
C560
C569
C580
100N
100N
100N
C561
C571
C581
100N
100N
100N
C562
C572
C582
100N
100N
100N
C563
C573
C583
100N
100N
100N
C564
C574
C584
100N
100N
100N
C565
C575
C585
100N
100N
100N
C566
C576
C586
100N
100N
100N
C567
C577
C587
100N
100N
100N
C570
100N
C578
100N
C588
100N
C
D
E
F
G
H
I
PART NO.
SPARE PARTS
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
6 9
OUTSIDE MAX
INSIDE MAX
0.13
2.0
1/1SCALE:
TITLE
DESIGNER
CHECKED
APPROVED
02R1679
HARRIER
1-15-2003_14:44
SHEET OF
James Dalton Brandon Ellison
20
108754321
Physical Design
Jeff Davis
20
F
G
H
I
JJ
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