MSI MS-9527 Schematic 0C
9612345 78 10
EC NO.DATEQTYREL FOR ASM
REL
A
PART NO.
DEVELOPMENT NO. Q/M
A
B
C
1. TITLE
B
C
2. CHANGE LOG
3. HARRIER BLOCK DIAGRAM
4. 405GP INTERFACE TO SDRAM & PCI
D
5. PPC405 MISC
D
6. 405GP PWR/GND & JTAG
7. 405GP BOOTSTRAP
8. 405GP SDRAM
E
E
9. 405GP PERIPHERAL BUS
10. FLASH / RTC
11. CLOCK OSCILLATOR & DRIVER
12. UART
F
13. RS485 DRIVERS
F
14. I2C SEEPROM AND SWITCHES
15. ETHERNET PHY
16. USB & SMP CONNECTOR
G
G
17. VIDEO COMPRESSOR
18. SDRAM 1MX16X4b
19. POWER
20. SPARE PARTS
H
I
TITLE
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
6 9
OUTSIDE MAX
INSIDE MAX
0.13
2.0
1/1SCALE:
PART NO.
TITLE
HARRIER
1-15-2003_14:44
DESIGNER
CHECKED
APPROVED
SHEET OF
02R1679
Physical Design
Brandon EllisonJames Dalton
1
20
108754321
Jeff Davis
H
I
JJ
9612345 78 10
EC NO.DATEQTYREL FOR ASM
REL
A
PART NO.
DEVELOPMENT NO. Q/M
A
Change Log:
04/01/02 - BJE - (Page 4) Added MEM_ADD Bus net.
04/01/02 - BJE - (Page 4) Synched with final Pass 1 of Management Module.
B
C
D
E
04/01/02 - BJE - (Page5) Renamed IRQ pins to IRQ to prevent confusion.
04/01/02 - BJE - (Page 5) Synched with final Pass 1 of Management Module.
04/01/02 - BJE - (Page 6) Synched with final Pass 1 of Management Module.
04/01/02 - BJE - (Page 7) Synched with final Pass 1 of Management Module.
04/01/02 - BJE - (Page 7) Changed all resistors to correct values, 3.3k PU, 1k PD.
04/01/02 - BJE - (Page 7) Changed EPB Speed from 25 MHz to 50 MHz
04/01/02 - BJE - (Page 8) Synched with final Pass 1 of Management Module.
04/01/02 - BJE - (Page 9) Synched with final Pass 1 of Management Module.
04/01/02 - BJE - (Page 10) Synched with final Pass 1 of Management Module.
04/01/02 - BJE - (Page 11) Synched with final Pass 1 of Management Module.
04/01/02 - BJE - (Page 11) New Clock chip to be entered by James Dalton
04/01/02 - BJE - (Page 12) Synched with final Pass 1 of Management Module.
04/01/02 - BJE - (Page 12) Adjusted a few cap values.
04/01/02 - BJE - (Page 12) Swapped pop options on R21 & R20.
04/01/02 - BJE - (Page 13) Synched with final Pass 1 of Management Module.
04/02/02 - JWD - (Page 16) Added values for R 528,529,530,531.
04/03/02 - BJE - (Page 5) Condor 2000 Connections on GPIO
04/03/02 - BJE - (Page 9) Condor 2000 Connections on some GPIOs
04/03/02 - BJE - (Page 15) Added Condor 2000 Connections
04/06/02 - JWD -Fixed address bit order
04/07/02 - JWD - (Page 15) Added system on detection
4/8/02 - JWD - (page 18) Removed 1.8V (not required)
04/08/02 - JWD - (Page 15) Moved differential signals around on the SMP connectors
04/11/02 - BJE - (Page 12) Added all COM signals for Modem use.
04/11/02 - BJE - (Page 12) Moved Debug Port to COM1
04/11/02 - BJE - (Page 5) Added SPI Bus to IRQ lines
04/11/02 - BJE - (Page 12) Added BERG header for 485/232 selection
04/11/02 - BJE - (Page 16) Added SPI bus option to Xilinx bus
04/11/02 - BJE - (Page 12) Changed Enable line of 232 Part to GND
Pass 5 Changes
01/15/03 - JWD - added pull-up to R485_A_RTS_N
B
C
D
E
Pass 2 Changes
F
06/13/02 - JWD - (Page 15) Removed Inverter from input pin 9 on U75
06/13/02 - JWD - (Page 15) Fixed reflected serial EPROM (U8)
06/13/02 - JWD - (Page 6) Changed U1 to powered symbol
07/26/02 - JWD - Changed DRAM to single chip for cost reduction
07/31/02 - JWD - (Page 15) Changed SMP to single connector
F
Pass 3 Changes
9/23/02 - JWD -Changed RTC data and clk pull-downs to pull-ups. Nopoped CE pull-down.
G
09/23/02 - JWD - (Page 15) Added USB switches.
09/23/02 - RMK - (Page 15) Added pull-up to USB_HUB_INT
9/23/02 RMK Changed micron part number to the full part number
9/23/02 RMK - Changed vendor part number of U83 DRAM
09/23/02 - RMK - (Page 16) Added ibm part number (77P0174) to xilinx XC2S150
G
Pass 4 Changes
10/31/02 -JWD- (Page 4) Using PCI_RESET# for manufacturing test of insane LED
10/31/02 - JWD - (Page 5) Changed signal name from GPIO18 to RS232_DETECT
H
I
10/31/02 - RMK - (Page 5) Changed RTC_INT_N to RTC_DUART_INT_N (sharing Interrupt pin)
10/31/02 - RMK - (Page 9) P_CS1# is now used for USB / DUART with ROM_ADDR12 qualifying
10/31/02 - RMK - (Page 10) Changed RTC Interupt to TIRQ_N
10/31/02 - RMK - Changed flash IBM part number to 02R1640, added coded part number 02R1641, removed socket
10/31/02 - JWD - (Page 11) Added 23.5 MHz frequency for the duart to the clock driver
10/31/02 - RMK - (Page 12) Made new page 12 with DUART circuitry
10/31/02 - RMK - (Page 14) Added nopop resistors between D and S1 on U94 and U95 to test if the switches are needed
10/31/02 - RMK - (Page 16) Made USB_CS# from logical and of P_CS1# and ROM_ADDR12
10/31/02 - JWD - (Page 16) Added com4, changed name of GPIO18 to RS232_DETECT
10-30-02-JWD-P_EXT_ACK# is used to detect BIST mode after reset.
10/31/02 - RMK - Added IBM part number for RTC (77P0248)
10/31/02 - RMK - Added IBM part number for DIALIGHT LED CR2 (26P0055)
10/31/02 - RMK - Added IBM part number for DIALIGHT LED CR3 (29L2476)
10/31/02 - RMK - Added IBM part number for TI multiplexer u96 (77P0242)
10/31/02 - RMK - Added IBM part number for Cypress clock driver (77P0247)
10/31/02 - RMK - Added IBM part number for ST switches (77P0242)
CHANGE LOG
PART NO.
H
I
02R1679
TITLE
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
6 9
OUTSIDE MAX
INSIDE MAX
0.13
2.0
1/1SCALE:
HARRIER
1-15-2003_14:44
DESIGNER
CHECKED
APPROVED
SHEET OF
Physical Design
Jeff Davis
Brandon EllisonJames Dalton
2
20
108754321
JJ
9612345 78 10
EC NO.DATEQTYREL FOR ASM
REL
A
PART NO.
DEVELOPMENT NO. Q/M
A
I2C/SMBus
B
SMP
Ethernet
RS485/RS232
B
USB
C
C
28.6 MHz
16
FPGA
USB
50 MHz
D
CPU
32
E
D
E
USBFPGA
F
MAX6315
G
PPC_RESET_N
SYSTEM
CPU
JTAG
PERIPHERAL_RESET_N
PPC_NOT_READY_N
I2C
DUART
F
G
HOST ID
H
TRST_N
JTAG
I
OR
JTAG_RST_N
FLASH
ETHERNET
H
I
Harrier Block Diagram
PART NO.
02R1679
TITLE
HARRIER
1-15-2003_14:44
DESIGNER
CHECKED
APPROVED
SHEET OF
Brandon EllisonJames Dalton
3
20
108754321
JJ
RESET
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
6 9
OUTSIDE MAX
INSIDE MAX
0.13
2.0
1/1SCALE:
9612345 78 10
REL
A
04/01/02 - BJE - (Page 4) Added MEM_ADD Bus net.
04/01/02 - BJE - (Page 4) Synched with final Pass 1 of Management Module.
04/11/02 - JWD - (Page 4) deleted PCIADR's
10/31/02 -JWD- (Page 4) Using PCI_RESET# for manufacturing test of insane LED
3.3VC
EC NO.DATEQTYREL FOR ASM
PART NO.
DEVELOPMENT NO. Q/M
A
B
R553
R554
R555
R556
R557
R559
R560
R561
R562
R563
R564
R565
8.2K
8.2K
8.2K
R566
8.2K
8.2K
E26
PCI_PAR
J24
PCI_FRAME_N
J23
PCI_IRDY_N
G26
PCI_TRDY_N
H23
PCI_STOP_N
H25
PCI_DEVSEL_N
G24
PCI_SERR_N
G25
PCI_PERR_N
B24
PCI_RESET_N
U23
PCI_GNT0_REQ_N
T23
PCI_GNT1_N
F23
PCI_GNT2_N
H26
PCI_GNT3_N
N23
PCI_GNT4_N
M24
PCI_GNT5_N
L11
HS_RTN1
L12
HS_RTN2
L13
HS_RTN3
L14
HS_RTN4
L15
HS_RTN5
L16
HS_RTN6
M11
HS_RTN7
M12
HS_RTN8
M13
HS_RTN9
M14
HS_RTN10
M15
HS_RTN11
M16
HS_RTN12
N11
HS_RTN13
N12
HS_RTN14
N13
HS_RTN15
N14
HS_RTN16
N15
HS_RTN17
N16
HS_RTN18
P11
HS_RTN19
P12
HS_RTN20
P13
HS_RTN21
P14
HS_RTN22
P15
HS_RTN23
P16
HS_RTN24
R11
HS_RTN25
R12
HS_RTN26
R13
HS_RTN27
R14
HS_RTN28
R15
HS_RTN29
R16
HS_RTN30
T11
HS_RTN31
T12
HS_RTN32
T13
HS_RTN33
T14
HS_RTN34
T15
HS_RTN35
T16
HS_RTN36
U53
PPC405GP-3BE200C
A17
PCI_AD0
B16
PCI_AD1
C17
PCI_AD2
A18
PCI_AD3
D17
PCI_AD4
C18
PCI_AD5
B18
PCI_AD6
A20
PCI_AD7
B21
PCI_AD8
A23
PCI_AD9
D21
PCI_AD10
B22
PCI_AD11
B23
PCI_AD12
C22
PCI_AD13
C26
PCI_AD14
F25
PCI_AD15
K26
PCI_AD16
L23
PCI_AD17
M25
PCI_AD18
M23
PCI_AD19
N25
PCI_AD20
M26
PCI_AD21
N26
PCI_AD22
P24
PCI_AD23
R24
PCI_AD24
R23
PCI_AD25
P23
PCI_AD26
R25
PCI_AD27
T24
PCI_AD28
U26
PCI_AD29
T25
PCI_AD30
V26
PCI_AD31
PCI_IDSEL
PCI_CLK
D19
F24
K24
R26
P26
B20
C23
C19
C21
B19
A24
G23
J25
D20
Y23
Y26
R373
5.1K
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
PCI_REQ4#
PCI_REQ5#
From Walnut
R366
10K
P_WE#
PCI_REQ0# when Internal Arbiter is Used
PCI_GNT# when using External Arbiter
Asynch Mode Use
R94
R579
8.2K
R587
8.2K
R586
R585
8.2K
PCI_C_BE0_N
PCI_C_BE1_N
PCI_C_BE2_N
PCI_C_BE3_N
P_WE_PCI_INT_N
PCI_REQ0_GNT_N
PCI_REQ1_N
PCI_REQ2_N
PCI_REQ3_N
PCI_REQ4_N
PCI_REQ5_N
SPARE_D20
SPARE_Y23
SPARE_Y26
405GP INTERFACE TO SDRAM & PCI
PART NO.
8.2K
R584
8.2K
R92
8.2K
3.3VC
8.2K
16,17
R552
8.2K
8.2K
C
D
E
8 MEM_ADD0
MEM_ADD1
8
MEM_ADD2
8
MEM_ADD3
8
MEM_ADD4
8
MEM_ADD5
8
MEM_ADD6
8
MEM_ADD7
8
MEM_ADD8
R99
R104
R105
R106
R102
R103
8
8
8
R98
22
R97
22
R95
22
R91
22
R55
22
8
8
8
8
22
RES_MEM_BSEL0#
22
RES_MEM_BSEL1#
22
RES_MEM_BSEL2#
22
RES_MEM_BSEL3#
22
22
MEM_ADD9
MEM_ADD10
MEM_ADD11
MEM_ADD12
RES_MEM_BA0
RES_MEM_BA1
RES_MEM_RAS#
RES_MEM_CAS#
RES_MEM_WE#
MEM_DQM3
MEM_DQM2
MEM_DQM1
MEM_DQM0
MEM_DQM_CB
RES_MEM_CLKEN0
RES_MEM_CLK0
F
MEM_BA0
8
MEM_BA1
8
MEM_RAS#
8
MEM_CAS#
8
MEM_WE#
G
H
MEM_CS0#
8
I
8
DQM Lines swapped to match Data Lines
R110
8
8
Up to 4 banks possible - Only using 1
3.3K
NOPOP resistors to allow for hot wiring later if needed.
NOPOP
MEM_CS1#
MEM_CS2#
MEM_CS3#
MEM_CLKEN0
MEM_CLK0
NOPOP
NOPOP
NOPOP
AE22
AC21
AE21
AD21
AF22
AE20
AC19
AE19
AD19
AC18
AF19
AD18
AC17
AB24
AC24
AF24
AB23
AC16
AC12
AC10
AC6
AA3
AC15
AD17
AF17
AE15
AC14
AB25
AC25
AC26
AA23
M_ADDR0
M_ADDR1
M_ADDR2
M_ADDR3
M_ADDR4
M_ADDR5
M_ADDR6
M_ADDR7
M_ADDR8
M_ADDR9
M_ADDR10
M_ADDR11
M_ADDR12
M_BA0
M_BA1
M_RAS_N
M_CAS_N
M_WE_N
M_DQM0
M_DQM1
M_DQM2
M_DQM3
M_DQM_CB
M_BANKSEL0_N
M_BANKSEL1_N
M_BANKSEL2_N
M_BANKSEL3_N
M_CLKEN0
M_CLKEN1
M_CLKOUT0
M_CLKOUT1
U53
PPC405GP-3BE200C
M_DATA0
M_DATA1
M_DATA2
M_DATA3
M_DATA4
M_DATA5
M_DATA6
M_DATA7
M_DATA8
M_DATA9
M_DATA10
M_DATA11
M_DATA12
M_DATA13
M_DATA14
M_DATA15
M_DATA16
M_DATA17
M_DATA18
M_DATA19
M_DATA20
M_DATA21
M_DATA22
M_DATA23
M_DATA24
M_DATA25
M_DATA26
M_DATA27
M_DATA28
M_DATA29
M_DATA30
M_DATA31
M_ECC0
M_ECC1
M_ECC2
M_ECC3
M_ECC4
M_ECC5
M_ECC6
M_ECC7
M_CLK_IN
AC13
RES_MEM_DATA30 MEM_DATA30
AE12
RES_MEM_DATA29
AD11
RES_MEM_DATA28
AC11
RES_MEM_DATA27
AF10
RES_MEM_DATA26
AE11
RES_MEM_DATA25
AD10
RES_MEM_DATA24
AF9
RES_MEM_DATA23
AD9
RES_MEM_DATA22
AE9
AD8
RES_MEM_DATA20
AF7
AC8
RES_MEM_DATA18
AD7
AE6
RES_MEM_DATA16 MEM_DATA16
AE5
AE4
RES_MEM_DATA14
AD5
AD4
RES_MEM_DATA12
AC5
AD1
RES_MEM_DATA10
AB2
AA4
RES_MEM_DATA8
AA2
RES_MEM_DATA7
AB1
RES_MEM_DATA6
Y2
RES_MEM_DATA5
W4
RES_MEM_DATA4
W2
RES_MEM_DATA3
W3
RES_MEM_DATA2
V4
RES_MEM_DATA1
W1
RES_MEM_DATA0
V3
AE14
AF15
AF14
AD13
AF13
AF12
AE13
AD12
AF4
R365
10K
Listed as Reserved in Datasheet
RN14
18
RN14
36
RN21
18
RN21
36
RN15
18
RN15
36
RN20
18
RN20
36
RN16
18
RN16
36
RN19
18
RN19
36
RN17
18
RN17
36
RN18
18
RN18
36
Using PCI_RESET# for manufacturing test of insane LED
22RES_MEM_DATA31
27
22
45
22
27
22
45
22
27
22RES_MEM_DATA21
45
22RES_MEM_DATA19
27
22RES_MEM_DATA17
45
22RES_MEM_DATA15
27
22RES_MEM_DATA13
45
22RES_MEM_DATA11
27
22RES_MEM_DATA9
45
22
22
45
22
27
22
45
MEM_DATA31
RN14
22
MEM_DATA29
RN14
MEM_DATA28
22
MEM_DATA27
RN21
MEM_DATA26
22
MEM_DATA25
RN21
MEM_DATA24
22
MEM_DATA23
RN15
MEM_DATA22
22
MEM_DATA21
RN15
MEM_DATA20
22
MEM_DATA19
RN20
MEM_DATA18
22
MEM_DATA17
RN20
22
MEM_DATA15
RN16
MEM_DATA14
22
MEM_DATA13
RN16
MEM_DATA12
22
MEM_DATA11
RN19
MEM_DATA10
22
MEM_DATA9
RN19
MEM_DATA8
22
MEM_DATA7
RN17
MEM_DATA6
22
27
RN17
RN18
RN18
MEM_DATA5
MEM_DATA4
22
MEM_DATA3
22
MEM_DATA2
MEM_DATA1
22
MEM_DATA0
PCI_PAR
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_DEVSEL#
PCI_SERR#
PCI_PERR#
PCI_RESET#
5
PCI_GNT0#
PCI_GNT1#
PCI_GNT2#
PCI_GNT3#
PCI_GNT4#
PCI_GNT5#
PCI_GNT0# when Internal Arbiter is Used
PCI_REQ# when using External Arbiter
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3.3VC
8.2K
8.2K
8.2K
R558
8.2K
8.2K
8.2K
8.2K
8.2K
B
C
D
E
F
G
H
I
02R1679
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
6 9
OUTSIDE MAX
INSIDE MAX
0.13
2.0
1/1SCALE:
TITLE
HARRIER
1-15-2003_14:44
DESIGNER
CHECKED
APPROVED
SHEET OF
Physical Design
Jeff Davis
Brandon EllisonJames Dalton
4
20
108754321
JJ
9612345 78 10
REL
A
3.3VC
EC NO.DATEQTYREL FOR ASM
PART NO.
DEVELOPMENT NO. Q/M
A
R597
1MEG
U88
GND
S1
S2
IN = 1
1
3
2
IN = 0
R594
0
R595
0
PPC405GP-3BE200C
HOST_PWR#
5
B
HOST_RST#
5
C
2_5V
C523
D
E
F
G
H
Internal Timer Input
Not currently used.
Peripheral Bus Controls
NEEDED?
100N
P_HOLD_REQ
P_EXT_REQ#
P_HOLD_PRIORITY
P_BUS_REQ
P_ERROR
PULLUP to 2.5V for PLL
BLM31A700S
L43
R522
SYS_TIMER_CLK
3.3VC
R90
R578
3.3VC
3.3K
3.3K
3.3K
C522
100N
R87
C534
16
5
16
12
16
5
16
6
6
6
6
11 33MHZ_405GP
PPC_RESET_N
6,10
RISCWATCH_HALT#
6
10U
R518
R520
3.3K
USB_HUB_INT
HOST_RST#
HOST_PCI_RST_N
SER_CLK
USB_LATCH_EMPTY
RS232_DETECT
RTC_DUART_INT_N
JTAG_TDI
JTAG_TMS
JTAG_TCK
JTAG_RST_N
R88
1K
1K
R519
3.3K
3.3VC
3.3K
R521
3.3K
10
17
A25
D22
AB26
D25
D26
C25
D24
AA24
Y25
Y24
W25
W24
V23
V25
AE24
AC22
AD22
AE26
E23
E24
V1
Y4
T2
R3
B1
CLK
X_CCLK
SYS_CLOCK
SYS_RESET_N
SYS_HALT_N
SYS_PLL_VDDA
CE0_TEST
DI1
Symbol is wrong on these three pins
DI2
DI1 DI2 RI - All test pins - No biggie.
RI
SYS_TIMER_CLK
IRQ6
GPIO23
IRQ5
GPIO22
IRQ4
GPIO21
IRQ3
GPIO20
IRQ2
GPIO19
IRQ1
GPIO18
IRQ0
GPIO17
JTAG_TDI
JTAG_TMS
JTAG_TCK
JTAG_TRST_N
P_HOLD_REQ
P_EXT_REQ_N
P_HOLD_PRIORITY
P_BUS_REQ
P_ERROR
R551
3.3VC
U53
1MEG
VCC
5
6
4
HOST_PWR_REQ#
Consider bi-directional buffers for next pass.
HOST_PWRGD/RST#
P_EXT_RESET_N
P_EXT_ACK_N
3.3VC
IN
D
SER_CLK 5
SYS_ERROR
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
P_CLK
JTAG_TDO
P_HOLD_ACK
16
16
3.3VC
U75
14
7,16
6
10,15
7
7
ERROR_LED#
43
PERCLK
17
5
12,14,16,17
5,7,10
7,17
7,16
17
ERROR_LED
AD25
AB3
AC7
AF5
AE8
AC9
FPGA = 0, RTC = 1
AF18
A22
C20
D18
E4
JTAG_TDO
AD23
PPC_NOT_READY_N
T3
Output reset to external devices.
P_HOLD_ACK
U2
P_EXT_ACK#
Y3
FPGA = 0, RTC = 1
HOST_PWR#
X_DONE
SER_DATA
I2C_SELECT
PERIPHERAL_RESET_N
FPGA_RTC
X_INIT
X_PROG
GPIO1
All GPIO's are high impedance while in reset. refer to 405gp user manual sec 23.5.1
R649
49.9
Place close to 405GP
Strapping Pins
FPGA_RTC
5,7,10
R610
10
3.3VC
U1
14
12
13
7
LV08_TSSOP14_65MM
5
14
17
11
330
2CR2
+
VEN_P/D_NUM=597-2401-213
VENDOR=DIALIGHT
COLOR=YELLOW
1
-
ERROR_LED_BUF
PCI_RESET#
16
PCI_reset is being used as a GPIO
4
10
R611
3.3VC3.3VC
330
2CR3
+
1
-
VEN_P/D_NUM=597-2301-213
VENDOR=DIALIGHT
COLOR=GREEN
PowerInsane
15
15
15
15
15
15
15
15
15
15
3.3VC
15
15
4.7K
R647
4.7K
R646
ENET_PHY_RXD3
ENET_PHY_RXD2
ENET_PHY_RXD1
ENET_PHY_RXD0
ENET_PHY_RX_ERR
ENET_PHY_RX_CLK
ENET_PHY_RX_DV
ENET_PHY_CRS
ENET_PHY_TX_CLK
ENET_PHY_COL
ENET_PHY_MDC
ENET_PHY_MDIO
R517
3.3K
12 COM1_RX
COM1_DCD#
12 COM1_CTS#
COM1_RI#
13 COM2_RX
13
COM2_CTS#
UART_RX = UART1_RX
UART_DSR_N = UART1_DSR_N
COM2 - DSR = CTS RTS = DTR
SERCLK
AD20
EMC_PHY_RXD3
AC20
EMC_PHY_RXD2
AF23
EMC_PHY_RXD1
AE23
EMC_PHY_RXD0
U24
EMC_PHY_RX_ER
AF20
EMC_PHY_RX_CLK
V24
EMC_PHY_RX_DV
W23
EMC_PHY_CRS
E25
EMC_PHY_TX_CLK
AA25
EMC_PHY_COL
H24
EMC_MDC
AD26
EMC_MDIO
AE17
UART_SERCLK
AE16
UART0_RX
AE18
UART0_DCD_N
AB4
UART0_CTS_N
AD15
UART0_RI_N
AC1
UART_RX
AC3 AD2
UART_DSR_N UART1_DTR_N
04/01/02 - BJE - (Page5) Renamed IRQ pins to IRQ to prevent confusion.
04/01/02 - BJE - (Page 5) Synched with final Pass 1 of Management Module.
04/03/02 - BJE - (Page 5) Condor 2000 Connections on GPIO
04/11/02 - BJE - (Page 5) Added SPI Bus to IRQ lines
08/16/02 - JWD - (Page 5) Added I2C_SELECT to GPIO6
08/16/02 - JWD - (Page 5) Added power and insane LED's
10/31/02 - JWD - (Page 5) Changed signal name from GPIO18 to RS232_DETECT
10/31/02 - RMK - (Page 5) Changed RTC_INT_N to RTC_DUART_INT_N (sharing Interrupt pin)
U53
PPC405GP-3BE200C
EMC_TXD3
EMC_TXD2
EMC_TXD1
EMC_TXD0
EMC_TX_ER
EMC_TX_EN
UART0_TX
UART0_DSR_N
UART0_DTR_N
UART0_RTS_N
UART1_TX
IIC_SCL
IIC_SDA
P25
L24
L25
J26
K25
K23
AF3
AE3
AF2
AD16
AC2
AD6
AE7
Strapping Pins
ENET_PHY_TX_EN
Strapping Pins
COM1_TX
COM1_DSR#
COM1_DTR#
COM1_RTS#
COM2_TX
COM2_RTS#
I2C_SCL
I2C_SDA
7,15ENET_PHY_TX_ERR
7,15
7,12
7,13
7,13
7,15ENET_PHY_TXD3
7,15ENET_PHY_TXD2
7,15ENET_PHY_TXD1
7,15ENET_PHY_TXD0
7,12
B
C
D
E
3.3VC
4.7K
R648
7
14
14
F
G
H
VENDOR=ST_MICRO
VEN_P/D_NUM=STG3157CTR
I
10
X_DOUT 5SER_DATA
17
$5I5959
U87
DIO
GND
VENDOR=ST_MICRO
VEN_P/D_NUM=STG3157CTR
S1
IN = 1
1
S2
3
2
IN = 0
3.3VC
VCC
5
IN
6
D
4
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
6 9
OUTSIDE MAX
INSIDE MAX
0.13
2.0
1/1SCALE:
PPC405 MISC
PART NO.
02R1679
TITLE
HARRIER
1-15-2003_14:44
DESIGNER
CHECKED
APPROVED
James Dalton
SHEET OF
5
108754321
Physical Design
Jeff Davis
Brandon Ellison
20
I
JJ
9612345 78 10
EC NO.DATEQTYREL FOR ASM
JTAG_RST_N
5
DEBUG PORT405 RISCWatch and JTAG
PPC_RESET_N
TRST_N
REL
3.3VC
U1
1
2
LV08_TSSOP14_65MM
14
3
7
405GP POWER
A
Place one set of THREE (100nF, 10nF, 2.2nF)
2_5V
per side within 25mils of 405GP
Place 10uF within 100mils of 405GP
C60
C59
C7
100N
B
C
D
E
F
10U
C61
C8
100N
10U
3.3VC
Place one set of THREE (100nF, 10nF, 2.2nF)
per side within 25mils of 405GP
Place 10uF within 100mils of 405GP
C66
C9
100N
10U
C69
100N
C62
C65
C68
100N
100N
100N
100N
C328
C330
C332
C334
10N
10N
10N
10N
C329
C331
C333
C335
10N
10N
10N
10N
C494
C496
C63
C64
2.2N
2.2N
2.2N
2.2N
C72
2.2N
C495
2.2N
C67
2.2N
C497
2.2N
2_5V
3.3VC
AB10
AB11
AB12
AB15
AB16
AB17
M22
U22
AA5
AB19
AB20
AB21
AB6
AB7
AB8
AA22
G22
H22
W22
Y22
AE10
AD14
U25
N24
B17
C13
E10
E11
E12
E15
E16
E17
K22
L22
R22
T22
F22
E19
E20
E21
W5
P2_5V_AB10
P2_5V_AB11
P2_5V_AB12
P2_5V_AB15
P2_5V_AB16
P2_5V_AB17
P2_5V_E10
P2_5V_E11
P2_5V_E12
P2_5V_E15
P2_5V_E16
P2_5V_E17
P2_5V_K22
K5
P2_5V_K5
P2_5V_L22
L5
P2_5V_L5
P2_5V_M22
M5
P2_5V_M5
P2_5V_R22
R5
P2_5V_R5
P2_5V_T22
T5
P2_5V_T5
P2_5V_U22
U5
P2_5V_U5
P3_3V_AA5
F5
P3_3V_F5
G5
P3_3V_G5
H5
P3_3V_H5
P3_3V_W5
Y5
P3_3V_Y5
P3_3V_AB19
P3_3V_AB20
P3_3V_AB21
P3_3V_AB6
P3_3V_AB7
P3_3V_AB8
P3_3V_AA22
P3_3V_F22
P3_3V_G22
P3_3V_H22
P3_3V_W22
P3_3V_Y22
P3_3V_E19
P3_3V_E20
P3_3V_E21
E6
P3_3V_E6
E7
P3_3V_E7
E8
P3_3V_E8
K2
P3_3V_K2
P3
P3_3V_P3
P3_3V_AE10
P3_3V_AD14
P3_3V_U25
P3_3V_N24
P3_3V_B17
P3_3V_C13
U53
PPC405GP-3BE200C
GND_A1
GND_AE1
GND_AF1
GND_A2
GND_B2
GND_AE2
GND_C3
GND_AD3
GND_D4
GND_A11
GND_A16
GND_A21
GND_AC4
GND_E5
GND_A6
GND_J5
GND_AA1
GND_P5
GND_AA26
GND_V5
GND_AB14
GND_AB5
GND_AB18
GND_AB22
GND_AF11
GND_E9
GND_AB9
GND_AF16
GND_AF21
GND_E13
GND_AB13
GND_AF25
GND_AF6
GND_E14
GND_E18
GND_E22
GND_F1
GND_F26
GND_L1
GND_L26
GND_N22
GND_N5
GND_T1
GND_T26
GND_J22
GND_H1
GND_P22
GND_AF8
GND_V22
GND_W26
GND_D23
GND_A19
GND_AC23
GND_C24
GND_AD24
GND_B25
GND_AE25
GND_AF26
GND_A26
GND_B26
A1
AE1
AF1
A2
B2
AE2
C3
AD3
D4
A11
A16
A21
AC4
E5
A6
J5
AA1
P5
AA26
V5
AB14
AB5
AB18
AB22
AF11
E9
AB9
AF16
AF21
E13
AB13
AF25
AF6
E14
E18
E22
F1
F26
L1
L26
N22
N5
T1
T26
J22
H1
P22
AF8
V22
W26
D23
A19
AC23
C24
AD24
B25
AE25
AF26
A26
B26
04/01/02 - BJE - (Page 6) Synched with final Pass 1 of Management Module.
04/10/02 - JWD - (Page 6) Moved LED's to CROW.
08/15/02 - JWD - (Page 6) Changed C7,C8,C9 to 10uF ceramic
3.3VC
R580
R581
R582
R583
10K
10K
10K
10K
0
R628
JTAG_TDO
5
JTAG_TDI
5
JTAG_TCK
5
JTAG_TMS
5
RISCWATCH_HALT#
5
J5
C10
C12C11
KEY
C16C15
2
C2
43
C4C3
65
C6C5
87
C8C7
10
NC
1211
NC
1615
1
C1
NC
9
C9
13
NOPOP
42F6867
79282-516
C13
CONN2x8HDR_KEY
NC
NC
3.3VC
1K
R226
R117
10K
5,10
PART NO.
DEVELOPMENT NO. Q/M
A
B
C
D
E
F
G
H
I
405GP PWR/GND & JTAG
PART NO.
G
H
I
02R1679
TITLE
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
$6I5250
6 9
OUTSIDE MAX
INSIDE MAX
0.13
2.0
1/1SCALE:
HARRIER
1-15-2003_14:44
DESIGNER
CHECKED
APPROVED
SHEET OF
Physical Design
Jeff Davis
Brandon EllisonJames Dalton
6
20
108754321
JJ
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