MSI MS-9197 Schematics

5

MSI

MS-9197 1U & 2U Server

Revision 0A

4

3

2

1

D D

Intel Dual Gainstown/Nehalem - DP Server processor,FC-LGA 1366 socket Inter Tylersburg / ICH9 Chipset Inter ZOAR 82575 Dual Gb Ethernet ServerEngines Server Management Controller Pilot

C C

B B

A A

MICRO-STAR INT'L CO.,LTD

MS-9197

MSI

Size Document Description Rev

C

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

Date:

5

4

3

2

Saturday, December 01, 2007

MS-9197

001_COVER

1

Sheet of

178

0A

5

4

3

2

1

MS-9197 SYSTEM BLOCK DIAGRAM

DDR3

D D

DDR3 DDR3

DDR3 DDR3 DDR3

Channel 0

Channel 1

Channel 2

PCI-E SLOT*16

CPU0

GAINSTOWN

PCI-E*16

CSI

CPU1

GAINSTOWN

CSI

Channel 0

Channel 1

Channel 2

DDR3 DDR3 DDR3

IOH

FOR RAID CARD

PCI-E SLOT*8

PCI-E*4

TYLERSBURG

C C

PCI-E SLOT*16

USB Front*2 USB Rear*2

B B

USB Internal*2

PCI-E*12

PCI-E*4

USB 2.0

ESI*4

ICH9

PCI-E*1

USB

LPC

ZOAR

BMC

SIO

VIDEO

LAN

FLASH

SPI

SATA

TPM

DDR2

SPI FLASH

MiniSAS

A A

MICRO-STAR INT'L CO.,LTD

MS-9197

MSI

Size Document Description Rev

Custom

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

Date:

5

4

3

2

Saturday, December 01, 2007

MS-9197

002_Block_Diagram

1

Sheet of

278

0A

5

9197 Mechanical

4

3

2

1

D D

MINISAS1

JSGPIO1

JFL1

C C

JFP1JFR1

CPU0CPU1

FAN CTL SKU

1U

PWM2 PWM3

PWM_CPU

PWM7 TACH7

B B

PWM7 TACH7_BAK

PWM6 TACH6 PWM6 TACH6_BAK

PWM5 TACH5 PWM5 TACH5_BAK

PWM4 TACH4 PWM4 TACH4_BAK

PWM3 TACH3 PWM3 TACH3_BAK

PWM2 TACH2 PWM2 TACH2_BAK

PWM1 TACH1 PWM1 TACH1_BAK

PWM4 PWM5 PWM1

PWM_DIMM

PWM6 PWM7 PWM_PWR

PWM7 TACH7 PWM7 TACH7_BAK

PWM6 TACH6 PWM6 TACH6_BAK

PWM5 TACH5 PWM5 TACH5_BAK

PWM2 TACH2 PWM2 TACH2_BAK

PWM1 TACH1 PWM1 TACH1_BAK

PWM2 PWM5

PWM1 PWM6

2U

PWM_CPU

PWM_DIMM

PWM7 PWM_PWR

A A

MICRO-STAR INT'L CO.,LTD

MS-9197

MSI

Size Document Description Rev

Custom

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

Date:

5

4

3

2

Saturday, December 01, 2007

MS-9197

003_Board Mechanical

Sheet of

1

0A

378

0A

5

POWER_CONNECTOR

+12V_CPU0 +12V_CPU1

ATX_CONNECTOR

24PIN

D D

12V_CONNECTOR

8PIN

+12V_DDR3_CPU

-12V +5V +5VSB +3.3V

+12V +5V +3.3V

+12V1

+12V2

+12V3

C C

+12V3

+12V4

+12V_CPU0

+12V_CPU1

+12V_DDR3_CPU

+12V

CPU VCORE VR11.1

1.5V DDR3 VR10

CPU VTT VR11.1

CPU VTT

PV_VCCP_CPU0

PV_VCCP_CPU1

+1.5V_DDR3_CPU0

+0.75V_DDR3_CPU0

+1.5V_DDR3_CPU1

+0.75V_DDR3_CPU1

+1.1V_CPU0

+1.1V_CPU1

VR11.1

B B

1.1V IOH

+1.1V_IOH

ISL6545

A A

5

4

CPU0

CPU1

DDR3*6

DDR3 VTT

DDR3*6

DDR3 VTT

CPU0

18.4A

CPU1

18.4A

IOH

22.9A

ICH9

2mA

PCIE1~2 SLOT

PCIE3 SLOT

SYSTEM FAN*4

4

110A

81A

3.9A

81A

3.9A

8A

2.1A

6A

+5V +5VSB

+5VSB

SWITCH

+5VDUAL

+5V +1.5V_ICH

1.5V ICH9 ISL6545

1.05V ICH9 APL5913

+1.05V_ICH

3

+3.3VSB

ICH9

USB2.0

ICH9

IOH

ICH9

PCIE1 SLOT

3

2.53A

45mA

1.63A

2mA

6A

2mA

5A

+3.3VSB

+3.3V

SWITCH

1.8V IOH BSC059N

1.8V CPU0 BSC059N

2

0.404A

0.25A

48mA

2.3A

23mA

0.25A

+2.5VDUAL

1.54A

0.4A

0.9A

10A

9A

3A

1.1V IOH BSC059N

1.8V IOH BSC059N

1.8V ZOAR BSC059N

1V ZOAR BSC059N

1.2V BMC BSC059N

+1.8VDUAL

+1.8VDUAL_ZOAR

+1VDUAL_ZOAR

+1.2VDUAL_BMC

MSI

+3.3VDUAL +1.1VDUAL_IOH

2.5VDUAL BSC059N

CLK MNG

IOH

PCIE*3

ZOAR

SPI*2

PILOT II

+1.8V_IOH

+1.8V_CPU0_PLL

+1.8V_CPU1_PLL

IOH

XDP1

CPU0

CPU1

PCIE1 SLOT

PCIE2 SLOT

PCIE3 SLOT

2

1

IOH

0.9V VTT

1.3A

DDR2_VTT

W83310DG

DDR2

10mA

PILOT II

0.9V VTT

0.557A

0.15A

+0.9VDUAL

W83310DG

IOH

ZOAR

PILOT II

MICRO-STAR INT'L CO.,LTD

Size Document Description Rev

Size Document Description Rev Custom

Custom

Custom Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

1

MS-9197

004_POWER_MAP

0.18A

0.856A

1.18A

0.63A

Sheet of

478

0A

5

82575

D D

ZOAR1

4

LAN*2

3

2

1

RJ45

82575

LAN*2

RJ45

ZOAR2

RJ45

LAN_USB1

USB0

USB1

C C

USB2

USB3

USB4

USB5

RJ45

USB*2

REAR_USB

FRONT_USB

BMC

PILOT 2

B B

PS/2_Bus

JKBMS1

PS/2

VGA_COM1

SERIAL

VGA_COM1

VGA_COM CONNECTOR

ICH 9

SATA_Bus

A A

5

4

SATA_1~SATA_6

SATA

MICRO-STAR INT'L CO.,LTD

MS-9197

MSI

Size Document Description Rev

B

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

Date:

3

2

Saturday, December 01, 2007

MS-9197

005_I/O_MAP

Sheet of

1

0A

578

5

4

3

2

1

CLK_133M_CPU0

CLK_133M_CPU1

D D

133M

CLK_133M_IOH_CSI0

CLK_133M_IOH_CSI1

CPU0

CPU1

IOH

TYLERSBURG

ICS8634

FOR NON-ME

CLK_100M_ICH_ESI

CLK_100M_ICH_SATA

CLK_100M_ICH_PCIE

C C

CK410B+

100M33M

ICS932

ICH9

CLK_50M_IOH_ME

CLK_133M_IOH_ME

CK_MNG_133

CLK_50M_NIC

CLK_50M_IBMCA

CLK_50M_ETH_REF

CLK_50M_PHY_REF

25MHZ

Crystal

CLK_100M_IBMC

CLK_25M_PLD

CLK_50M_NIC

CPLD

ZOAR

CLK_100M_DB800

CLK_48M_USB_ICH

CLK_48M_USB_IBMC

48MREF0

BMC

CLK_33M_IBMC

B B

CLK_33M_ICH

CLK_33M_TPM_R

CLK_33M_DEBUG_R

TPM

DEBUG PORT

PILOT II

CLK_100M_IOH_PE0CLK

CLK_100M_IOH_PE1CLK

DB803

(100M)

CLK_100M_NIC

CLK_100M_SLOT1

CLK_100M_SLOT2

CLK_100M_SLOT3

PCI-E SLOT

CLK_14M_ICH

14.3181MHZ

A A

Crystal

MICRO-STAR INT'L CO.,LTD

MS-9197

MSI

Size Document Description Rev

Custom

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

Date:

5

4

3

2

Saturday, December 01, 2007

MS-9197

006_CLK_MAP

1

Sheet of

678

0A

5

4

3

Front Panel

Thermal Sensor

2

1

ADDR

TYLARSBURG

D D

IOH

ADDR 0XE0

PCI-E X8 Slot

PCI-E X16 Slot

PCA9515

SMBus Isolator

PCA9515

SMBus Isolator

HW Monitor ADT7462

ADDR 0X58

HW Monitor ADT7462

ADDR 0X5C

FRU ROM

3.3VDUAL

SDA4/SCL4

IPMB Header

C C

5VDUAL

PCA9515

SMBus Isolator

3.3VDUAL SDA0/SCL0

3.3VDUAL

SDA1/SCL1

SDA2/SCL2

3.3VDUAL

ADDR 0XAE

PCA9515

SMBus Isolator

PECI CY8C21234

ADDR 0X

PILOT II

BackPanel

Power

5VDUAL

ADDR

B B

PCA9515

SMBus Isolator

3.3VDUAL SDA3/SCL3

SDA5/SCL5

CHANNEL A0

CHANNEL A1

CHANNEL B0

3.3VDUAL

CPU1 DDR3 DIMMCPU0 DDR3 DIMM

CHANNEL A0

CHANNEL A1

CHANNEL B0

PCA9515

SMBus Isolator

CLK_MNG

ADDR 0XD0

IOH

ADDR 0XE0

ICH9

ADDR

3.3V

CLK410B+

ADDR 0XD2

DB803

ADDR 0XDC

XDP

CHANNEL B1

CHANNEL C0

CHANNEL C1

CHANNEL B1

CHANNEL C0

CHANNEL C1

ZOAR

SMBus SWITCH

PCA9545

SDA0/SCL0

A A

5

4

3

SDA1/SCL1

MICRO-STAR INT'L CO.,LTD

MS-9197

MSI

Size Document Description Rev

C

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

Date:

2

Saturday, December 01, 2007

MS-9197

007_SMBUS_MAP

1

Sheet of

778

0A

5

4

3

2

1

M_A_RESET_N

D D

ZOAR

PILIOT 2

TPM_DISABLE

74LCX

TPM

M_B_RESET_N

M_C_RESET_N

M_D_RESET_N

M_E_RESET_N

M_F_RESET_N

CPU0 CPU1

XDP0

RST_LPC_N

PWRGD_NIC_PWROK

C C

74LCX244

RST_PCIE_SLOT_13_N

RST_PCIE_SLOT_2_N

RST_IOH_CORERST_N

B B

PCIE SLOT 1

RST_PLTRST_N

RTC PIN HEADER

JTAG_IOH_TRST_N

XDP1

RTC_RST#

ICH9

RST_IOH_CLINK_N

RST_LTRESET_N RST_RSM_N

JTAG_CPU_TRST_N RST_CPU_RESET_N

IOH

PCIE SLOT 2

PCIRST_ICH9#

PCIE SLOT 3

SMBUS PCA9545

2MS DELAY

RST_IOH_CORERST_DELAYED_N

A A

MICRO-STAR INT'L CO.,LTD

MS-9197

MSI

Size Document Description Rev

Custom

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

Date:

5

4

3

2

Saturday, December 01, 2007

MS-9197

008_RESET_MAP

Sheet of

1

0A

878

0A

5

D D

C C

4

3

2

1

B B

A A

MICRO-STAR INT'L CO.,LTD

MS-9197

MSI

Size Document Description Rev

B

Date:

5

4

3

2

Date:

009_POWER SEQUENCE

Saturday, December 01, 2007

MS-9197

Sheet of

1

0A

978

5

4

3

2

1

ICH9 GPIO LIST

GPIO

GPIO[0] GPIO[1] GPIO[2] GPIO[3]

D D

C C

B B

A A

GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] 3.3V GPIO[11] GPIO[12] GPIO[13] GPIO[14] GPIO[15] GPIO[16] GPIO[17] GPIO[18] GPIO[19] GPIO[20] GPIO[21] GPIO[22] GPIO[23] GPIO[24] GPIO[25] GPIO[26] GPIO[27] GPIO[28] GPIO[29] GPIO[30] GPIO[31] GPIO[32] GPIO[33] GPIO[34] GPIO[35] GPIO[36] GPIO[37] GPIO[38] GPIO[39] GPIO[40] GPIO[41] GPIO[42] GPIO[43] GPIO[44] GPIO[45] GPIO[46] GPIO[47] GPIO[48] GPIO[49] GPIO[50] GPIO[51] GPIO[52] GPIO[53] GPIO[54] GPIO[55] GPIO[56] GPIO[57] GPIO[58] GPIO[59] GPIO[60]

Alt Func Tol

PMSYNC# TACH1 PIRQ[E]# PIRQ[F]# PIRQ[G]# PIRQ[H]# TACH[2] TACH[3] unmuxed WOL_EN CLGPIO1 SMBALERT# unmuxed unmuxed CLGPIO2 STP_PCI# unmuxed TACH0 unmuxed SATA1GP unmuxed SATA0GP SCLOCK LDRQ1# MEM_LED STP_CPU# S4_STATE# QRT_STATE0 QRT_STATE1 OC5# OC6# OC7# unmuxed unmuxed unmuxed SATACLKREQ# SATA2GP SATA3GP SLOAD SDATAOUT0 OC[1]# OC[2]# OC[3]# OC[4]# OC[8]# OC[9]# OC[10]# OC[11]# SDATAOUT1 unmuxed REQ1# GNT1# REQ2# GNT2# REQ3# GNT3# unmuxed CLGPIO5 SPI_CS1# OC[0]# LINKALERT#

I/O/NC

I/O I/O I/OD I/OD I/OD I/OD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 3.3V I/O I/O I/O I/O Core I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

Power

Core Core Core Core Core Core Core Core Resume Resume Resume Resume Resume Resume Resume Resume Core Core Core Core Core Core Core Core Resume Resume Resume Resume Resume Resume Resume Resume Core Core Core Core Core Core Core Core Resume Resume Resume 3.3V Resume Resume Resume Resume Resume Core Core

Core Core Core Core Core Resume Resume Resume Resume Resume

3.3V

3.3V 5V 5V 5V 5V

3.3V

3.3V 5V

3.3V

Default

GPI GPI GPI GPI GPI GPI GPI GPI GPO Native GPI Native GPO GPI GPI Native GPO GPI GPO GPI GPO GPI GPI Native GPO Native Native GPO GPO Native Native Native GPO GPO GPO GPO GPI GPI GPI GPI Native Native Native Native Native Native Native Native GPI GPO Native Native Native Native Native Native GPI GPI GPI Native Native

Signal Name

BP_PRESENCE FRB3#_ICH unused unused unused unused FM_IOH_ERR_N0 NMI_BTN_N BMC_SCI_N FM_IOH_ERR_N1 IRQ_IBMC_ICH_SCI_N ASF_SMBALERT_N DUTY_REQ_SMI_N IRQ_IBMC_ICH_SCI_WHEA_N IRQ_IBMC_ICH_SMI_WHEA_N FM_IOH_ERR_N2 SPI_HOLD#_GP16 PASSWORD_CLEAR SPI_WP#_GP18 DUTY_REQUEST0 FP_PWR_LED_N DUTY_REQUEST0

Alt Func

unused RAID_KEY RAID_SEL

RST_REQ#

FM_LAN_DEV_OFF_N DUTY_REQ_MIS_N

Alt Func Alt Func Alt Func

MB VERSION MB VERSION MB VERSION RECOVERY DUTY_REQUEST1 DUTY_REQUEST2

Alt Func Alt Func

unused

Alt Func Alt Func Alt Func

Pull-up Pull-up Pull-up Pull-up

Alt Func

DMI_STRAP CSI_TTL_CPU0_PRCHT_N unused CSI_TTL_CPU1_PRCHT_N unused unused unused

2.5HD_SEL P66DET

Alt Func

1U_2U_SEL

Alt Func

PILOT II GPIO LIST

GPIO

GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] GPIO[11] GPIO[12] GPIO[13] GPIO[14] GPIO[15] GPIO[16] GPIO[17] GPIO[18] GPIO[19] GPIO[20] GPIO[21] GPIO[22] GPIO[23] GPIO[24] GPIO[25] GPIO[26] GPIO[27] GPIO[28] GPIO[29] GPIO[30] GPIO[31]

Use Type

In In In OD OD In In out In Out In In In Out In Out Out In Out In In Out Out In Out Out Out In In In In In

Active Polarity

LowGPIO[0] Low Low Low Low Low Low High Low Low Low Low Low Low Low Low Low Low Low Low Low High High Low High High High High High High High High

Default

Signal Name

BMC_SEL_N CSI_TTL_CATERR_N FM_IOH_THERMALERT_N FM_CPU0_DISABLE_N FM_CPU1_DISABLE_N THERM_PRE_SET# ID_BTN_N TPM_DISABLE_N DUTY_REQ_MIS_N DUTY_REQ_SMI_N CSI_TTL_CPU0_THERMTRIP_N CSI_TTL_CPU1_THERMTRIP_N FRB3#_PILOT_N BMC_SPI_WE# FORCE_MODE# BMC_SPI_RST# BMC_SCI_N RST_REQ# SYS_ID_LED_N CSI_CPU0_SKTOCC_N CSI_CPU1_SKTOCC_N SYSRDY_LED

SYS_FLT_LED

IRQ_IOH_ICH_SMI_N RMII_LAN_TX_EN RMII_LAN_TXD1

RMII_LAN_TXD0

RMII_LAN_RXD1 RMII_LAN_RXD0 RMII_LAN_CRS_DV RMII_IBMC_IOH_RX_ER CLK_50M_IBMCA

MICRO-STAR INT'L CO.,LTD

MS-9197

MSI

Size Document Description Rev

C

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

Date:

5

4

3

2

Saturday, December 01, 2007

MS-9197

010_GPIO_LIST

0A

10 78

0A

Sheet of

1

5

4

3

2

1

Power Connector

+12V

RN26

JPWR2

+12V_CPU0

+

D D

C C

+5VSB

C634

0.1u_0402

C552

0.1u_0402

+3.3V

C671

0.1u_0402

C581

0.1u_0402

C736

0.1u_0402

+

EC52

EC52 1000u_16V

1000u_16V

+5V

-12V

+3.3V

13

GND

14

GND

15

GND

16

5V

17

5V

18

GND

19

GND

20

-12V

21

3.3V

22

GND

23

GND

24

GND

POWERCONN

JPWR2

12V3 12V3 12V2 12V2 12V1 12V1

3.3V

GND

5VSB

PWOK

PSON

1 2 3 4 5 6 7 8 9 10 11 12

C554

1000p_0402

+12V_DDR3_CPU

+12V_CPU1

+12V_CPU0

+3.3V

+5VSB

C553

X_0.1u_0402

+5V

C635

0.1u_0402

PWRGD_PS (76)

FM_PS_ON_N (75)

+3.3V+12V_CPU1 +12V_DDR3_CPU +12V_DDR3_CPU

C557

0.1u_0402

For Minimum Load Close to power connector

RN26

1

2

3

4

5

6

7

8

X_200R_8P4R

C551

C551 X_0.01u

X_0.01u

+12V

JPWR1

5

+12V1

6

+12V1

7

+12V3

8

+12V3

POWERCONN2X4

B B

A A

5

4

12V4 12V4

3.3V

1 2 3

5V

4

EC42

+

1000u_16V

+5V +3.3V

EC40

+

100u_25V

3

EC41

+

1000u_16V

MICRO-STAR INT'L CO.,LTD

MS-9197

MSI

Size Document Description Rev

B

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

Date:

2

Saturday, December 01, 2007

MS-9197

011_SSI_POWER_CONNECTOR

1

11 78

Sheet of

0A

5

4

3

2

1

+3.3VDUAL+5VSB

R620

R620 X_0

X_0

D D

0.9V DUAL (780mA)

R6210R621 0

U48

8 7 6 5

C353

0.1u_0402

U48

VREF2 ENABLE VCTRL BOOT_SEL

VREF1

GND9

W83310DS

9

GND2

VOUT

1

VIN

2 3 4

C333

C333 X_0.1u_0402

X_0.1u_0402

C332

0.1u_0402

+1.8VDUAL

R583

R583 1K_1%_0402

1K_1%_0402

R582

R582 1K_1%_0402

1K_1%_0402

+3.3VSB (1.41A)

+5VSB +3.3VSB

C420

C420 X_0.1u_0402

X_0.1u_0402

C421

0.1u_0402

3

U61

VIN

AP1084K

VOUT1 VOUT2

ADJ

2 4 1

3VDUAL_ADJ

C419

C419 X_0.1u_0402

X_0.1u_0402

R1

R2

R785

R785 200_1%_0402

200_1%_0402

R784

R784 332_1%_0402

332_1%_0402

C410

0.1u_0402

C409

C409 22u_1206

22u_1206

+3.3VSB

EC29

+

100u_25V

+0.9VDUAL+1.8VDUAL

EC23

+

100u_25V

Vout=Vref(1+R2/R1)+Iadj*R2

1.8V DUAL (1.21A)

5

C9081uC908 1u

+1.8VDUAL+2.5VDUAL

Q5

+

EC4

EC4 560u_4V

560u_4V

PWRGD_PS_BUF_GATED

C904

0.01u_0402

PWRGD_PS_BUF_GATED(17,18,72,76,77)

+3.3VDUAL (1.0A)

S0 0.93A / S3,S4,S5 0.88A

+5VSB +3.3VDUAL+12V +3.3VSB

R786

4.7K

DS

Q81

Q81 2N7002

2N7002

G

+5VDUAL (3.0A)

S0 3.0A / S3,S4,S5 0.65A

+5VSB +5VDUAL+12V +5VSB

R706

4.7K

DS

Q83

Q83 2N7002

2N7002

G

D S

DS

G

+3.3V

Q82

Q82 SI2305DS

SI2305DS

Q62

Q62 IPD06N03LA_TO252

IPD06N03LA_TO252

AC

12

+

EC27

EC27 1000u_6.3V

1000u_6.3V

D16

D16 1N5817

1N5817

C3591uC359 1u

3A

+2.5VDUAL_REF

R1020 49.9_1%_0402R1020 49.9_1%_0402

R1021

C C

C8201uC820 1u

130_1%_0402

+9VDUAL

3

+

2

-

4 8

1

U13A

U13A LM358MX

LM358MX

4 3 2 1

N-S4841NHT1G

+9V DUAL

+5VDUAL +12V +9VDUAL

D19

D19 1N5817

+5VDUAL

R1077

8.2K_0402

53

2 1

U23

U23 7S14_SOT23-5

B B

C910

0.01u_0402

7S14_SOT23-5

4

C909 10u_1206C909 10u_1206

1N5817

D9 1N5817D9 1N5817

AC

C907

C907 10u_1206

10u_1206

D8 1N4148SD81N4148S

R1287

R1278

4.7K

2.5V DUAL

+2.5VDUAL_REF

A A

+5VDUAL

5

R1019

R1019 100_0402

100_0402

VR1

VR1 TS2431LT

TS2431LT

3 1

+9VDUAL

3

+

1

2

-

U35A

2

C8191uC819 1u

4 8

U35A LM358MX

LM358MX

+3.3VDUAL +2.5VDUAL

4 3 2 1

N-S4841NHT1G

+3.3VDUAL

4 3 2 1

N-S4841NHT1G

4

5

Q29

12

+

EC14

EC14 1000u_6.3V

5

Q30

1000u_6.3V

3

PWRGD_PS_BUF_GATED

4.7K

DS

Q141

Q141 2N7002

2N7002

G

R1287

4.7K

G

Q142

G

MSI

Q142 SI2305DS

SI2305DS

D S

DS

Q59

Q59 IPD06N03LA_TO252

IPD06N03LA_TO252

+5V

Size Document Description Rev

Custom

Date:

DS

Q143

Q143 2N7002

2N7002

G

2

AC

D15

D15 1N5817

1N5817

3A

12

+

EC24

EC24 1000u_6.3V

1000u_6.3V

MICRO-STAR INT'L CO.,LTD

012_0.9_1.8_2.5_3.3_5_9_VDUAL

Saturday, December 01, 2007

MS-9197

C3681uC368 1u

Sheet of

1

12 78

0A

5

4

+5V

3

2

1

BMC 1.2V DUAL (S0 630mA/S3 450mA)

ICH 1.5V(4.21A)

D D

Vref = 0.6V

+5V

Q24

1 2 3 4 5

NN-SP8K10S_SOP8-RH

C912 10p_0402C912 10p_0402 C911 1500pC911 1500p

R1085 47KR1085 47K

5

U31

7

COMP

6

FB

3

UGATE

VCC

BOOT

PHASE

LGATE

GND

ISL6545CBZ

2 1

8 4

C184 0.22uC184 0.22u

R295

R295 X_1.8K_1%

X_1.8K_1%

R296 0_0805R296 0_0805

R294 0_0805R294 0_0805

C1831uC183 1u

8 7 6

+

EC10

EC10 390u_6.3V

390u_6.3V

R328

2.2_0805

C193

C193 1000p

1000p

CHOKE1

1 2

1.2uH

R1087

R1087 3K_1%

3K_1%

12

+

EC12

EC12 1000u_6.3V

1000u_6.3V

+1.5V_ICH

C232

C232 22u_1206

22u_1206

R1030 150_1%_0402R1030 150_1%_0402

C233

C233 22u_1206

22u_1206

C8411uC841 1u

R1031

R1031 140_1%_0402

140_1%_0402

5

+

6

7

-

U13B

U13B LM358MX

LM358MX

4 8

Q8

3 1

N-FDS6676AS

4

+1.2VDUAL_BMC+2.5VDUAL+2.5VDUAL_REF +9VDUAL

5 6 72 8

EC8

+

100u_25V

C C

R1086

R1086 2K_1%

2K_1%

ICH 1.05V (1.63A)

+5V

+3.3V+1.5V_ICH

U34

R406

R407

1K_0402

B B

PWRGD_P1V05_ICH(14,17,18,76)

A A

5

1K_0402

U34

7

POK

8

EN

C9191uC919 1u

6

5

VIN

VCNTL

9

VIN#9

4

VOUT

3

VOUT#3

2

FB

GND

APL5913KAC

1

R2

Vout=0.8(1+R1/R2)

4

R1

R409 43K_1%R409 43K_1% C227 0.033u_0402C227 0.033u_0402

R408

R408 137K_1%_0402

137K_1%_0402

+1.5V_ICH

C224

C224 22u_1206

22u_1206

+1.05V_ICH

EC13

+

100u_25V

MICRO-STAR INT'L CO.,LTD

MS-9197

MSI

Size Document Description Rev

B

Date:

3

2

Date:

013_ICH_POWER_&_BMC_1.2VDUAL

Saturday, December 01, 2007

MS-9197

Sheet of

1

13 78

0A

5

4

3

2

1

TBG 1.1V/22.9A

+12V

C9131uC913

R320 47KR320 47K

B

1u

5

UGATE

VCC

BOOT

PHASE LGATE

GND

ISL6545CBZ

3

R307

R307 X_4.7K_0402

X_4.7K_0402

PWRGD_CPU0_VTT

Q25

Q25 2N3904

2N3904

E C

+3.3V+3.3V

R337

R337 X_4.7K_0402

X_4.7K_0402

PWRGD_CPU1_VTT

Q27

2N3904

E C

2

R374 2.2_1%_0805R374 2.2_1%_0805

1 8

R401 1_0805R401 1_0805

4

R1

+12V

D D

PWRGD_PLD_IOH_P1V1_EN_R(72)

PWRGD_P1V05_ICH(13,17,18,76)

C C

+5V

R315

R315 10K_1%_0402

10K_1%_0402

R314

2.8K_1%_0402

+1.1V_IOH

R360 X_0R360 X_0

+3.3V

3

+

2

-

4 8

1

U28A

U28A LM358MX

LM358MX

R361

DS

4.7K_0402

DS

Q31

Q31 2N7002

2N7002

G

Q32

Q32 2N7002

2N7002

R309 10K_0402R309 10K_0402

R310 10K_0402R310 10K_0402

C201 10p_0402C201 10p_0402 C200 1500pC200 1500p

7

6

+3.3V +3.3V

R308

4.7K_0402

Q26

B

2N3904

E C

R338

4.7K_0402

Q28

B

2N3904

E C

U32

COMP

FB

Vref = 0.6V

CHOK1 1uH_22ACHOK1 1uH_22A

R399 0_0805R399 0_0805

C215 0.1uC215 0.1u

R400

22K_0.1%

R2

R1088 845_1%_0402R1088 845_1%_0402

R1089

0.6*(1+R2/R1)

1K_1%_0402

PWRGD_CPU0_VTT (16,17,25,26,29,72)

PWRGD_IOH_P1V1 (52,72)

PWRGD_CPU1_VTT (16,18,33,72)

4 3 2 1

N-S4841NHT1G

Q34

4 3 2 1

N-S4835NT1G

5

Q33

C236

CT1

+

10u_1206

270u_16V

+1.1V_IOH

5

R411

2.2_1%_0805

C238

C238 1000p

1000p

L3 1uH_40AL3 1uH_40A

R352

R352 X_845_1%_0402

X_845_1%_0402

C199 X_10p_0402C199 X_10p_0402

R339 0_0402R339 0_0402

12

+

EC17

EC17 330u_2.5V

330u_2.5V

12

+

EC58

EC58 330u_2.5V

330u_2.5V

+1.1V_IOH +1.1V_IOH

12

+

EC67

EC67 X_330u_2.5V

X_330u_2.5V

12

+

EC15

EC15 330u_2.5V

330u_2.5V

12

EC68

EC68 X_330u_2.5V

X_330u_2.5V

12

+

22.8A

EC18

EC18 330u_2.5V

330u_2.5V

RESERVE

Base on Rework 42_5

IOH 1.1V DUAL (1.6A)

5

Q39

N-S4841NHT1G

4 3 2 1

N-S4841NHT1G

+1.1VDUAL_IOH+2.5VDUAL_REF +2.5VDUAL+9VDUAL

+

EC16

EC16 560u_4V

560u_4V

+1.8V_IOH+3.3V+12V+2.5VDUAL_REF

5

Q54

EC22

+

100u_25V

MSI

3

2

MICRO-STAR INT'L CO.,LTD

MS-9197

Size Document Description Rev

Custom

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

MS-9197

014_IOH_1.1_1.8V

Sheet of

1

14 78

0A

B B

R1094 210_1%_0402R1094 210_1%_0402

C9291uC929 1u

R1098

R1098 120_1%_0402

120_1%_0402

5

+

6

-

U35B

U35B LM358MX

LM358MX

4 8

4

7

3 2 1

IOH 1.8V (1.94A)

U45

R546

1.3K_1%_0402

U45

1

+IN

2

V-

-IN3OUTPUT

LM321MFX_SOT23-5-RH

5

V+

4

+12V

R560

A A

PWRGD_IOH_P1V1

5

R560

4.7K_0402

DS

Q55

Q55 2N7002

2N7002

G

R547

R547 499_1%

499_1%

DS

Q56

C3111uC311

2N7002

G

1u

4

5

D D

4

3

2

1

ZOAR/BMC 1.8V DUAL (1.7A)

+1.8VDUAL_ZOAR+2.5VDUAL+2.5VDUAL_REF +9VDUAL

5

Q12

R236 49.9_1%_0402R236 49.9_1%_0402

R237

C1461uC146 1u

130_1%_0402

C C

3

+

-

4 8

1

U18A

U18A LM358MX

LM358MX

2

4 3 2 1

N-S4841NHT1G

Q12

+

EC9

EC9 560u_4V

560u_4V

ZOAR/BMC 1.0V DUAL (S0 1.19A/S3 548mA)

+9VDUAL

+1VDUAL_ZOAR+2.5VDUAL+2.5VDUAL_REF

R210 191_1%_0402R210 191_1%_0402

B B

+1.8VDUAL_ZOAR

R235 0R235 0

A A

5

+5VDUAL

DS

G

C1281uC128 1u

R1046

4.7K_0402

Q124

Q124 2N7002

2N7002

R1045

R1045 130_1%_0402

130_1%_0402

DS

G

Q123

Q123 2N7002

2N7002

5

+

6

7

-

U18B

U18B LM358MX

LM358MX

4 8

4

Q9

3 1

N-FDS6676AS

4

5 6 72 8

+

EC7

EC7 560u_4V

560u_4V

MICRO-STAR INT'L CO.,LTD

MS-9197

MSI

Size Document Description Rev

B

Date:

3

2

Date:

015_ZOAR_1.8_1.2_VDUAL

Saturday, December 01, 2007

MS-9197

Sheet of

1

15 78

0A

5

4

3

2

1

PWRGD_CPU0_DDR3VTT_SFR_EN

+3.3V +3.3V

R889

4.7K_0402

D D

PWRGD_CPU0_VDD_GTL(19,29)

PWRGD_CPU0_VTT(14,17,25,26,29,72)

C C

PWRGD_CPU0_VDD_GTL

PWRGD_CPU0_VTT

PWRGD_CPU0_DDR3

PWRGD_CPU0_VDD_GTL_R

R914 10K_0402R914 10K_0402

R741

10K_1%_0402

R715

10K_1%_0402

PWRGD_CPU0_VTT_R

PWRGD_CPU0_DDR3_R

B

E C

B

E C

+3.3V

B

E C

PWRGD_CPU0_VDD_N

Q90

Q90 2N3904

2N3904

R740

4.7K_0402

Q70

Q70 2N3904

2N3904

R739

4.7K_0402

PWRGD_CPU0_DDR3_N

Q67

Q67 2N3904

2N3904

R873

4.7K_0402

PWRGD_CPU0_DDR3

Q88

B

2N3904

E C

+3.3V+3.3V

R714

4.7K_0402

Q69

B

2N3904

E C

PWRGD_CPU0_DDR3VTT_SFR_EN

Q66

B

2N3904

E C

PWRGD_CPU0_DDR3 (72)

PWRGD_CPU0_DDR3VTT_SFR_EN (21,22)

PWRGD_CPU1_DDR3VTT_SFR_EN

+3.3V +3.3V

R730

4.7K_0402

B

E C

+3.3V

B

E C

+3.3V

B

E C

PWRGD_CPU1_VDD_N

Q74

Q74 2N3904

2N3904

R728

4.7K_0402

PWRGD_CPU1_VTT_N

Q63

Q63 2N3904

2N3904

R727

4.7K_0402

PWRGD_CPU1_DDR3_N

Q71

Q71 2N3904

2N3904

B B

PWRGD_CPU1_VDD_GTL(20,33)

PWRGD_CPU1_VTT(14,18,33,72)

A A

5

PWRGD_CPU1_VDD_GTL

PWRGD_CPU1_VTT

PWRGD_CPU1_DDR3

PWRGD_CPU1_VDD_GTL_R

R744 10K_0402R744 10K_0402

R717

10K_1%_0402

R726

10K_1%_0402

PWRGD_CPU1_VTT_R

PWRGD_CPU1_DDR3_R

4

R729

4.7K_0402

PWRGD_CPU1_DDR3

Q73

B

2N3904

E C

+3.3V

R683

4.7K_0402

Q64

B

2N3904

E C

3

PWRGD_CPU1_DDR3VTT_SFR_EN

Q72

B

2N3904

E C

PWRGD_CPU1_DDR3 (72)

PWRGD_CPU1_DDR3VTT_SFR_EN (21,22)

MSI

Size Document Description Rev

Custom

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

Date:

2

Saturday, December 01, 2007

MICRO-STAR INT'L CO.,LTD

MS-9197

016_MEMORY_SWITCH

1

16 78

Sheet of

0A

5

4

3

2

1

ISL6314CR POWER CKT FOR VTT 1.1V

EC35

EC35 330u_2.5V

330u_2.5V

+12V_VTT0

4 3 2 1

N-S4841NHT1G

4 3 2 1

N-S4835NT1G

12

+

EC39

EC39 X_330u_2.5V

X_330u_2.5V

C382

C382 10u_1206

R761

2.2_0805

C406

C406 1000p

1000p

10u_1206

PHASE_CPU0 ISEN_CPU0

L22 1uH_40AL22 1uH_40A

SP1

SP1 X_Short PAD 0402

X_Short PAD 0402

+1.1V_CPU0

18A

SP3

5

Q75

5

Q76

12

+

EC38

EC38 X_330u_2.5V

X_330u_2.5V

+12V+5V

D D

PWRGD_CPU0_VTT(14,16,25,26,29,72)

PWRGD_PLD_CPU0_VTT_EN_R(72)

PWRGD_P1V05_ICH(13,14,18,76)

C C

VSENSE_DIE_CPU0_VTT_P(29)

VSENSE_DIE_CPU0_VTT_N(29)

B B

CPU0_VTT_VID(29) CPU0_VTT_VID2(29) CPU0_VTT_VID1(29)

R696 0_0402R696 0_0402

R697 0_0402R697 0_0402

+3.3V

C4071uC407 1u

R1308 X_0R1308 X_0

+1.1V_CPU0

+5V

R713

R713 100K_0402

100K_0402

R725

R725 X_0_0402

X_0_0402

R753

2.7K_0402

R772 0R772 0 R773 0R773 0 R774 0R774 0

C1116

C1116 X_0.1u_0402

X_0.1u_0402

R1326

R1326 100_0402

100_0402

P0VTT_SENSE+

P0VTT_SENSE-

R1325

R1325 100_0402

100_0402

C1120

C1120 X_0.01u_0402

X_0.01u_0402

C392

0.01u_0402

VID_CPU0VTT7 VID_CPU0VTT6 VID_CPU0VTT5 VID_CPU0VTT4 VID_CPU0VTT3 VID_CPU0VTT2 VID_CPU0VTT1 VID_CPU0VTT0

C383

C383 X_0.01u_0402

X_0.01u_0402

C1119

C1119 X_0.1u_0402

X_0.1u_0402

R737

64.9K_1%_0402

R752

R752 100K_0402

100K_0402

1 17 32 25 26 27 28 29 30 31

12

11

5

4

3

2

6X6 QFN

R711

2.2

C3871uC387 1u

U60

PGOOD EN VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

VSEN

RGND

OFS REF

FS SS

BOTTOM PAD CONNECT TO GND Through 8 VIAs

18

VCC

GND

33

PVCC BOOT

UGATE PHASE

LGATE

ISEN+

ISEN-

ISENNO

OCSET

NC

VDIFF

DVC

FB

COMP

APA

ISL6314CR

C1123

C1123 1u_0805

1u_0805

19

R736 2.2_1%_0805R736 2.2_1%_0805

22

U_G_VTT0

23

PH_VTT0

24

L_G_VTT0

21

ISEN_CPU0

16 15

PHASE_CPU0

14

R695

13

1.58K_1%

20

10

R712 4.99K_1%_0402R712 4.99K_1%_0402

8

9

7

6

R724

2.2

C391 0.1uC391 0.1u

R693 16.9K_1%_0402R693 16.9K_1%_0402

R694 30K_1%_0402R694 30K_1%_0402

C378 10000p_0402C378 10000p_0402

C1122 1000p_0402C1122 1000p_0402

R1311 3K_1%R1311 3K_1%

PWRGD_PS_BUF_GATED(12,18,72,76,77)

C377 0.1u_0402C377 0.1u_0402

R699 220_1%_0402R699 220_1%_0402 R698 2K_1%_0402R698 2K_1%_0402

C379 1000p_0402C379 1000p_0402

C1118 22pC1118 22p

R1307

R1307 20K_1%_0402

20K_1%_0402

C372

C372 2200p

2200p

C1117 2200p_0402C1117 2200p_0402

C376

0.1u_0402

R77610K_0402 R77610K_0402

R1321 0_0805R1321 0_0805 R751 10K_0402R751 10K_0402

R1312 0_0805R1312 0_0805

+3.3V

R775

4.7K_0402

B

+1.1V_CPU0

12

+

EC33

EC33 330u_2.5V

330u_2.5V

B

Q78

Q78 2N3904

2N3904

E C

12

+

PWRGD_CPU0_VTT

Q77

Q77 2N3904

2N3904

E C

Base on Rework 42_5

+12V +12V_VTT0

A A

CT3

+

CD270U16V

5

+3.3V

R771 X_1K_0402R771 X_1K_0402 R767 1K_0402R767 1K_0402 R1324 X_1K_0402R1324 X_1K_0402 R768 X_1K_0402R768 X_1K_0402CHOK3 0.68uH_25ACHOK3 0.68uH_25A R763 0_0402R763 0_0402 R769 X_1K_0402R769 X_1K_0402 R770 X_1K_0402R770 X_1K_0402 R1323 1K_0402R1323 1K_0402 R1322 X_1K_0402R1322 X_1K_0402

4

VID_CPU0VTT7 VID_CPU0VTT6 VID_CPU0VTT5 VID_CPU0VTT4 VID_CPU0VTT3 VID_CPU0VTT2 VID_CPU0VTT1 VID_CPU0VTT0

R766 0_0402R766 0_0402 R762 X_0_0402R762 X_0_0402 R1320 0_0402R1320 0_0402

R764 0_0402R764 0_0402 R765 0_0402R765 0_0402 R1319 X_0_0402R1319 X_0_0402 R1318 0_0402R1318 0_0402

MICRO-STAR INT'L CO.,LTD

MS-9197

MSI

Size Document Description Rev

Custom

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

Date:

3

2

Saturday, December 01, 2007

MS-9197

017_CPU0_VTT_POWER

1

Sheet of

17 78

0A

5

4

3

2

1

ISL6314CR POWER CKT FOR VTT 1.1V

+12V+5V

D D

PWRGD_CPU1_VTT(14,16,33,72) PWRGD_PLD_CPU1_VTT_EN_R(72)

PWRGD_P1V05_ICH(13,14,17,76)

C C

VSENSE_DIE_CPU1_VTT_P(33)

VSENSE_DIE_CPU1_VTT_N(33)

B B

CPU1_VTT_VID(33) CPU1_VTT_VID2(33) CPU1_VTT_VID1(33)

R758 0_0402R758 0_0402

R757 0_0402R757 0_0402

+3.3V

C3751uC375 1u

R1313 X_0R1313 X_0

+1.1V_CPU1

+5V

R720

R720 100K_0402

100K_0402

R687

2.7K_0402

R679 0R679 0 R677 0R677 0 R673 0R673 0

C1124

C1124 X_0.1u_0402

X_0.1u_0402

R824

R824 100_0402

100_0402

P1VTT_SENSE+

P1VTT_SENSE-

R825

R825 100_0402

100_0402

C1126

C1126 X_0.01u_0402

X_0.01u_0402

VID_CPU1VTT7 VID_CPU1VTT6 VID_CPU1VTT5 VID_CPU1VTT4 VID_CPU1VTT3 VID_CPU1VTT2 VID_CPU1VTT1 VID_CPU1VTT0

C403

C403 X_0.01u_0402

X_0.01u_0402

C1127

C1127 X_0.1u_0402

X_0.1u_0402

U58

1

PGOOD

17

EN

32

VID7

25

VID6

26

VID5

27

VID4

28

VID3

29

VID2

30

VID1

31

VID0

12

VSEN

11

RGND

5

OFS

4

REF

3

FS

2

SS

6X6 QFN

C385

R721

R721 X_0_0402

X_0_0402

C385

0.01u_0402

R708

R707

100K_0402

64.9K_1%_0402

BOTTOM PAD CONNECT TO GND Through 8 VIAs

C4051uC405 1u

R750

2.2

18

PVCC

VCC

BOOT

UGATE PHASE

LGATE

ISEN+

ISEN-

ISENNO

OCSET

NC

VDIFF

DVC

FB

COMP

APA

GND

ISL6314CR

33

C390

C390 1u_0805

1u_0805

19

R722 2.2_1%_0805R722 2.2_1%_0805

22

U_G_VTT1

23

PH_VTT1

24

L_G_VTT1

21

ISEN_CPU1

16 15

PHASE_CPU1

14

R749

13

1.58K_1%

20

10

R734 4.99K_1%_0402R734 4.99K_1%_0402

8

9

7

6

R735

2.2

C386 0.1uC386 0.1u

R760 16.9K_1%_0402R760 16.9K_1%_0402

R759 30K_1%_0402R759 30K_1%_0402

C404 10000p_0402C404 10000p_0402

C389 1000p_0402C389 1000p_0402

R733 3K_1%R733 3K_1%

PWRGD_PS_BUF_GATED(12,17,72,76,77)

C413 0.1u_0402C413 0.1u_0402

R748 220_1%_0402R748 220_1%_0402 R756 2K_1%_0402R756 2K_1%_0402

C401 1000p_0402C401 1000p_0402

C411 22pC411 22p

R747 20K_1%_0402

20K_1%_0402

R709 0_0805R709 0_0805 R710 10K_0402R710 10K_0402

R723 0_0805R723 0_0805

C1125

0.1u_0402

C412

C412 2200p

2200p

+1.1V_CPU1

12

+

EC32

EC32 X_330u_2.5V

X_330u_2.5V

C402 2200p_0402C402 2200p_0402R747

+3.3V

R686

4.7K_0402

R66510K_0402 R66510K_0402

B

E C

B

Q60

Q60 2N3904

2N3904

PWRGD_CPU1_VTT

Q61

Q61 2N3904

2N3904

E C

EC37

EC37 330u_2.5V

330u_2.5V

+12V_VTT1

4 3 2 1

N-S4841NHT1G

N-S4841NHT1G Q80

Q80

4 3 2 1

N-S4835NT1G

12

+

EC34

EC34 X_330u_2.5V

X_330u_2.5V

C415

C415 10u_1206

R783

2.2_0805

C417

C417 1000p

1000p

10u_1206

PHASE_CPU1 ISEN_CPU1

L21 1uH_40AL21 1uH_40A

SP2

SP2 X_Short PAD 0402

X_Short PAD 0402

+1.1V_CPU1

18A

SP4

5

Q79

5

12

+

EC36

EC36 330u_2.5V

330u_2.5V

Base on Rework 42_5

+12V +12V_VTT1

A A

5

CHOK2 0.68uH_25ACHOK2 0.68uH_25A

+

CD270U16V

CT2

+3.3V

R672 X_1K_0402R672 X_1K_0402 R1298 1K_0402R1298 1K_0402 R1299 X_1K_0402R1299 X_1K_0402 R678 X_1K_0402R678 X_1K_0402 R676 X_1K_0402R676 X_1K_0402 R675 X_1K_0402R675 X_1K_0402 R674 1K_0402R674 1K_0402 R1300 X_1K_0402R1300 X_1K_0402

VID_CPU1VTT7 VID_CPU1VTT6 VID_CPU1VTT5 VID_CPU1VTT4 VID_CPU1VTT3 VID_CPU1VTT2 VID_CPU1VTT1 VID_CPU1VTT0

4

R688 0_0402R688 0_0402 R1301 X_0_0402R1301 X_0_0402 R1302 0_0402R1302 0_0402 R692 0_0402R692 0_0402 R691 0_0402R691 0_0402 R690 0_0402R690 0_0402 R689 X_0_0402R689 X_0_0402 R1303 0_0402R1303 0_0402

MICRO-STAR INT'L CO.,LTD

MS-9197

MSI

Size Document Description Rev

Custom

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

Date:

3

2

Saturday, December 01, 2007

MS-9197

018_CPU1_VTT_POWER

1

Sheet of

18 78

0A

5

4

3

2

1

+12V_DDR3_CPU0_L

PVCC1_2

BOOT1

UGATE1 PHASE1 LGATE1

ISEN1+

ISEN1-

BOOT2

UGATE2 PHASE2 LGATE2

ISEN2+

ISEN2-

PVCC3

BOOT3

UGATE3 PHASE3 LGATE3

ISEN3+

ISEN3-

ISEN4+

ISEN4-

PWM4

EN_PH4

ISL6312CR

+12V_DDR3_CPU

29

R941 2.2_1%_0805R941 2.2_1%_0805

31

U_G1_DDR0

32

PH1_DDR0

33

L_G1_DDR0

30

35 34

PH1

2.8K_1%_0402

2.8K_1%_0402 R939 2.2_1%_0805R939 2.2_1%_0805

27

U_G2_DDR0

26

PH2_DDR0

25

L_G2_DDR0

28

19 20

PH2

2.8K_1%_0402

42

R907 2.2_1%_0805R907 2.2_1%_0805

40

U_G3_DDR0

39

PH3_DDR0

38

L_G3_DDR0

41

44 43

PH3

2.8K_1%_0402

21 22

24

R929 0_0402R929 0_0402

23

R940

2.2

C706

C706 1u_0805

1u_0805

R1427

R1393

R1391 2.2_1%_0805R1391 2.2_1%_0805

C665

C665 1u_0805

1u_0805

R902

C707 0.1uC707 0.1u

C705 0.1uC705 0.1u

C689 0.1uC689 0.1u

+5V

R943 0_0402R943 0_0402

C1218 0.1u_0402C1218 0.1u_0402 R942 X_4.7K_1%_0402R942 X_4.7K_1%_0402

R906 0_0402R906 0_0402 C687 0.1u_0402C687 0.1u_0402

R913 X_4.7K_1%_0402R913 X_4.7K_1%_0402

+12V_DDR3_CPU

R887 0_0402R887 0_0402 C1180 0.1u_0402C1180 0.1u_0402

R901 X_4.7K_1%_0402R901 X_4.7K_1%_0402

C710

0.1u_0402

C1206

0.1u_0402

C649

0.1u_0402

ISEN1

ISEN2

ISEN3

R1457 0_0805R1457 0_0805 R1470 10KR1470 10K

R1443 0_0805R1443 0_0805 R1458 10KR1458 10K

R1456 0_0805R1456 0_0805 R1469 10KR1469 10K

5

4 3 2 1

N-S4841NHT1G

5

Q112

4 3 2 1

N-S4835NT1G

+12V_DDR3_CPU0_L

5

4 3 2 1

N-S4841NHT1G

5

Q111

4 3 2 1

N-S4835NT1G

+12V_DDR3_CPU0_L

5

4 3 2 1

N-S4841NHT1G

5

Q113

4 3 2 1

N-S4835NT1G

Q121

Q120

Q122

R966

2.2_1%_0805

C745

C745 1000p

1000p

R965

2.2_1%_0805

C744

C744 1000p

1000p

R967

2.2_1%_0805

C746

C746 1000p

1000p

C1251

C1251 10u_1206

10u_1206

C1248

C1248 10u_1206

10u_1206

C1249

C1249 10u_1206

10u_1206

C1252

C1252 10u_1206

10u_1206

CHOK17 0.155uH 31ACHOK17 0.155uH 31A

PH1 ISEN1

C1247

C1247 10u_1206

10u_1206

CHOK16 0.155uH 31ACHOK16 0.155uH 31A

PH2 ISEN2

C1250

C1250 10u_1206

10u_1206

CHOK18 0.155uH 31ACHOK18 0.155uH 31A

PH3 ISEN3

+1.5V_DDR3_CPU0

R930

R930 1K_0402

1K_0402

C700

R1351 3K_1%R1351 3K_1%

R1354

C700

0.1u_0402

P0_DDR_VID7 P0_DDR_VID6 P0_DDR_VID5 P0_DDR_VID4 P0_DDR_VID3 P0_DDR_VID2 P0_DDR_VID1 P0_DDR_VID0

C647 560pC647 560p

R898

R898 27K_1%_0402

27K_1%_0402

C1182 X_560pC1182 X_560p

P0_DDR_SENSE+

P0_DDR_SENSE-

C641

0.01u_0402

R888

64.9K_1%

R866

240K

37 36 46 47 48

1 2 3 4 5 6

13 14

15

16

18

17

12

7 8

11 45

9

C1181

4.7u_1206

U67

C688

0.1u_0402

D D

PWRGD_CPU0_VDD_GTL(16,29) PWRGD_PLD_CPU0_DDR3_EN_R(72)

FM_SLPS4_N(20,57,64,72)

C C

+5V +5V +5V

0.1u_0402

R886 560_1%R886 560_1%

+1.5V_DDR3_CPU0

R864 X_100K_0402R864 X_100K_0402

R1349 X_5.1K_1%R1349 X_5.1K_1%

R867 X_1K_0402R867 X_1K_0402

R945 0R945 0 R944 X_0R944 X_0

R868

R868 0_0402

0_0402

C648 47p_0402C648 47p_0402

R899 X_0_0402R899 X_0_0402

X_200_1%_0402

R905 0_0402R905 0_0402

R900 0_0402R900 0_0402

R865

R865 X_39.2K_1%_0402

X_39.2K_1%_0402

R1350

2.2

10

PGOOD EN

VCC VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VRSEL

COMP FB

IDROOP

VDIFF

VSEN

RGND

OFS DRSEL/SCL OVPSEL/SDA REF

FS SS/RST/A0

GND

49

BOTTOM PAD CONNECT TO GND Through 8 VIAs

SP26

SP22

X_Short PAD 0402

SP27

SP27 X_Short PAD 0402

X_Short PAD 0402

SP25

SP25 X_Short PAD 0402

X_Short PAD 0402

+1.5V_DDR3_CPU0+5V

SP23

SP23 X_Short PAD 0402

X_Short PAD 0402

SP21

SP21 X_Short PAD 0402

X_Short PAD 0402

1.5V/ 80A

+

C451 10uC451 10u C509 10uC509 10u C441 10uC441 10u C432 10uC432 10u C487 10uC487 10u C508 10uC508 10u C481 10uC481 10u C440 10uC440 10u C491 10uC491 10u C489 10uC489 10u C439 10uC439 10u C507 10uC507 10u C428 10uC428 10u C461 10uC461 10u C449 10uC449 10u C429 10uC429 10u C516 10uC516 10u C488 10uC488 10u C467 10uC467 10u C433 10uC433 10u

C533 10uC533 10u C460 10uC460 10u

5

+12V_DDR3_CPU0_L+12V_DDR3_CPU

R1338

4.7K_0402

R857

R857 X_4.7K_0402

X_4.7K_0402

+3.3V+3.3V+3.3V+3.3V

2

R1346

R1346 X_4.7K_0402

X_4.7K_0402

R871

4.7K_0402

R1337

4.7K_0402

R858

R858 X_4.7K_0402

X_4.7K_0402

R1345

4.7K_0402

R872

R872 X_4.7K_0402

X_4.7K_0402

R1336

R1336 X_4.7K_0402

X_4.7K_0402

R859

4.7K_0402

MICRO-STAR INT'L CO.,LTD

MS-9197

MSI

Size Document Description Rev

C

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

MS-9197

019_CPU0_DDR3_POWER

1

Sheet of

19 78

0A

CT7CD270U16V+CT7CD270U16V

OSCON

22u*26

+1.5V_DDR3_CPU0

C650 22u_1206C650 22u_1206 C669 22u_1206C669 22u_1206 C654 22u_1206C654 22u_1206 C1204 22u_1206C1204 22u_1206 C1202 22u_1206C1202 22u_1206 C1177 22u_1206C1177 22u_1206 C1203 22u_1206C1203 22u_1206 C1185 22u_1206C1185 22u_1206 C1187 22u_1206C1187 22u_1206 C653 22u_1206C653 22u_1206 C1179 22u_1206C1179 22u_1206 C683 22u_1206C683 22u_1206 C681 22u_1206C681 22u_1206 C666 22u_1206C666 22u_1206 C668 22u_1206C668 22u_1206 C667 22u_1206C667 22u_1206 C684 22u_1206C684 22u_1206 C682 22u_1206C682 22u_1206 C1174 22u_1206C1174 22u_1206 C1184 22u_1206C1184 22u_1206 C1186 22u_1206C1186 22u_1206C424 10uC424 10u C652 22u_1206C652 22u_1206 C651 22u_1206C651 22u_1206 C1175 22u_1206C1175 22u_1206 C1205 22u_1206C1205 22u_1206 C1178 22u_1206C1178 22u_1206

VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

0011101.51250

1

001110 0 1.50625 10111 1 0 1.50000

330u*3

+1.5V_DDR3_CPU0

+

12

EC49

330u_2.5V

12

EC54

330u_2.5V

+

12

EC55

330u_2.5V

RESERVE

+1.5V_DDR3_CPU0

+

12

+

12

EC66

EC63

X_330u_2.5V

4

P0_DDR_VID7 P0_DDR_VID6 P0_DDR_VID5 P0_DDR_VID4 P0_DDR_VID3 P0_DDR_VID2 P0_DDR_VID1 P0_DDR_VID0

3

+3.3V +3.3V+3.3V+3.3V

R1347

R1339

4.7K_0402

R856

R856 X_4.7K_0402

X_4.7K_0402

R1347

4.7K_0402

R870

R870 X_4.7K_0402

X_4.7K_0402

R1348

R1348 X_4.7K_0402

X_4.7K_0402

R869

4.7K_0402

CHOK21 0.68uH_25ACHOK21 0.68uH_25A

B B

10u_0603*23

+1.5V_DDR3_CPU0

A A

5

4

3

2

1

+12V_DDR3_CPU1_L

+1.5V_DDR3_CPU1+5V

SP31

SP30

X_Short PAD 0402

SP32

SP24

X_Short PAD 0402

CHOK15 0.155uH 31ACHOK15 0.155uH 31A

SP29

SP28

X_Short PAD 0402

PVCC1_2

BOOT1

UGATE1 PHASE1 LGATE1

ISEN1+ ISEN1-

BOOT2

UGATE2 PHASE2 LGATE2

ISEN2+ ISEN2-

PVCC3

BOOT3

UGATE3 PHASE3 LGATE3

ISEN3+ ISEN3-

ISEN4+ ISEN4-

PWM4

EN_PH4

ISL6312CR

+12V_DDR3_CPU

29

R909 2.2_1%_0805R909 2.2_1%_0805

31

U_G11_DDR1

32

PH11_DDR1

33

L_G11_DDR1

30

35 34

PH11

2.8K_1%_0402

2.8K_1%_0402 R895 2.2_1%_0805R895 2.2_1%_0805

27

U_G22_DDR1

26

PH22_DDR1

25

L_G22_DDR1

28

19 20

PH22

2.8K_1%_0402

42

R934 2.2_1%_0805R934 2.2_1%_0805

40

U_G33_DDR1

39

PH33_DDR1

38

L_G33_DDR1

41

44 43

PH33

2.8K_1%_0402

21 22

24

R881 0_0402R881 0_0402

23

R903

2.2

C679

C679 1u_0805

1u_0805

R908

R860

R1436 2.2_1%_0805R1436 2.2_1%_0805

C703

C703 1u_0805

1u_0805

R946

C686 0.1uC686 0.1u

C663 0.1uC663 0.1u

C708 0.1uC708 0.1u

+5V

R916 0_0402R916 0_0402

C690 0.1u_0402C690 0.1u_0402 R915 X_4.7K_1%_0402R915 X_4.7K_1%_0402

C645 0.1u_0402C645 0.1u_0402 R1386 X_4.7K_1%_0402R1386 X_4.7K_1%_0402

+12V_DDR3_CPU

R935 0_0402R935 0_0402 C704 0.1u_0402C704 0.1u_0402

R1435 X_4.7K_1%_0402R1435 X_4.7K_1%_0402

ISEN11

C691

0.1u_0402

ISEN22

C639

0.1u_0402

ISEN33

C709

0.1u_0402

R1485 0_0805R1485 0_0805 R1484 10KR1484 10K

R1487 0_0805R1487 0_0805 R1486 10KR1486 10K

R1482 0_0805R1482 0_0805 R1483 10KR1483 10K

4 3 2 1

N-S4841NHT1G

Q115

4 3 2 1

N-BSC032N03SG

+12V_DDR3_CPU1_L

4 3 2 1

N-S4841NHT1G

Q114

4 3 2 1

N-BSC032N03SG

+12V_DDR3_CPU1_L

4 3 2 1

N-S4841NHT1G

Q116

4 3 2 1

N-BSC032N03SG

5

Q118

5

Q117

5

Q119

5

R969

2.2_1%_0805

C740

C740 1000p

1000p

R968

2.2_1%_0805

C739

C739 1000p

1000p

R970

2.2_1%_0805

C741

C741 1000p

1000p

C1267

C1267 10u_1206

10u_1206

C1265

C1265 10u_1206

10u_1206

C1263

C1263 10u_1206

10u_1206

C1266

C1266 10u_1206

10u_1206

CHOK14 0.155uH 31ACHOK14 0.155uH 31A

PH11 ISEN11

C1268

C1268 10u_1206

10u_1206

CHOK13 0.155uH 31ACHOK13 0.155uH 31A

PH22 ISEN22

C1264

C1264 10u_1206

10u_1206

PH33 ISEN33

+1.5V_DDR3_CPU1

R933

R933 1K_0402

1K_0402

C701

C702

0.1u_0402

D D

PWRGD_CPU1_VDD_GTL(16,33)

PWRGD_PLD_CPU1_DDR3_EN_R(72) FM_SLPS4_N(19,57,64,72)

C C

+5V +5V +5V

0.1u_0402

R863 560_1%R863 560_1%

+1.5V_DDR3_CPU1

R897 X_100K_0402R897 X_100K_0402

R912 X_5.1K_1%R912 X_5.1K_1%

R910 X_1K_0402R910 X_1K_0402

R931 0R931 0 R932 X_0R932 X_0

R911

R911 0_0402

0_0402

X_200_1%_0402

R883 0_0402R883 0_0402

R884 0_0402R884 0_0402

C701

0.1u_0402

P1_DDR_VID7 P1_DDR_VID6 P1_DDR_VID5 P1_DDR_VID4 P1_DDR_VID3 P1_DDR_VID2 P1_DDR_VID1 P1_DDR_VID0

R855 3K_1%R855 3K_1%

C646 47p_0402C646 47p_0402

R885 X_0_0402R885 X_0_0402 R882 0_0402R882 0_0402

R862

R896

R896 X_39.2K_1%_0402

X_39.2K_1%_0402

C640 560pC640 560p

R861

R861 27K_1%_0402

27K_1%_0402

C636 X_560pC636 X_560p

P1_DDR_SENSE+

P1_DDR_SENSE-

C664

0.01u_0402

R1426

64.9K_1%

R904

240K

37 36 46 47 48

1 2 3 4 5 6

13 14

15

16

18

17

12

7 8

11 45

9

C680

4.7u_1206

U68

R1394

2.2

10

PGOOD EN

VCC VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VRSEL

COMP FB

IDROOP

VDIFF

VSEN

RGND

OFS DRSEL/SCL OVPSEL/SDA REF

FS SS/RST/A0

GND

49

BOTTOM PAD CONNECT TO GND Through 8 VIAs

1.5V/ 80A

+

C535 10uC535 10u C493 10uC493 10u C541 10uC541 10u C534 10uC534 10u C452 10uC452 10u C548 10uC548 10u C455 10uC455 10u C543 10uC543 10u C469 10uC469 10u C542 10uC542 10u C463 10uC463 10u C492 10uC492 10u C483 10uC483 10u C470 10uC470 10u C536 10uC536 10u C511 10uC511 10u C447 10uC447 10u C484 10uC484 10u C482 10uC482 10u C462 10uC462 10u C453 10uC453 10u C485 10uC485 10u C454 10uC454 10u C519 10uC519 10u C520 10uC520 10u

5

+12V_DDR3_CPU1_L+12V_DDR3_CPU

R1425

4.7K_0402

R918

R918 X_4.7K_0402

X_4.7K_0402

+3.3V+3.3V+3.3V+3.3V

2

R1432

R1432 X_4.7K_0402

X_4.7K_0402

R938

4.7K_0402

R1433

4.7K_0402

R937

R937 X_4.7K_0402

X_4.7K_0402

R1434

4.7K_0402

R936

R936 X_4.7K_0402

X_4.7K_0402

R1439

R1439 X_4.7K_0402

X_4.7K_0402

R947

4.7K_0402

MSI

MICRO-STAR INT'L CO.,LTD

MS-9197

Size Document Description Rev

C

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

MS-9197

020_CPU1_DDR3_POWER

Sheet of

1

20 78

0A

CT4CD270U16V+CT4CD270U16V

OSCON

+1.5V_DDR3_CPU1

C677 22u_1206C677 22u_1206 C1211 22u_1206C1211 22u_1206 C673 22u_1206C673 22u_1206 C657 22u_1206C657 22u_1206 C675 22u_1206C675 22u_1206 C1210 22u_1206C1210 22u_1206 C1199 22u_1206C1199 22u_1206 C660 22u_1206C660 22u_1206 C1197 22u_1206C1197 22u_1206 C662 22u_1206C662 22u_1206 C643 22u_1206C643 22u_1206 C1212 22u_1206C1212 22u_1206 C1208 22u_1206C1208 22u_1206 C644 22u_1206C644 22u_1206 C678 22u_1206C678 22u_1206 C1200 22u_1206C1200 22u_1206 C658 22u_1206C658 22u_1206 C1198 22u_1206C1198 22u_1206 C659 22u_1206C659 22u_1206 C1201 22u_1206C1201 22u_1206 C676 22u_1206C676 22u_1206 C1209 22u_1206C1209 22u_1206 C1196 22u_1206C1196 22u_1206 C674 22u_1206C674 22u_1206 C661 22u_1206C661 22u_1206 C1207 22u_1206C1207 22u_1206

VID6 VID5 VID4 VID3 VID2 VID1 VID0 VDAC

0011101.51250

1

001110 0 1.50625 10111 1 0 1.50000

330u*3

+1.5V_DDR3_CPU1

+

12

+

EC50

330u_2.5V

12

EC56

330u_2.5V

+

12

EC51

330u_2.5V

RESERVE

+1.5V_DDR3_CPU1

+

12

+

12

EC65

EC64

X_330u_2.5V

4

P1_DDR_VID7 P1_DDR_VID6 P1_DDR_VID5 P1_DDR_VID4 P1_DDR_VID3 P1_DDR_VID2 P1_DDR_VID1 P1_DDR_VID0

3

+3.3V +3.3V+3.3V+3.3V

R1424

R1403

R1402

R1402 X_4.7K_0402

X_4.7K_0402

R919

4.7K_0402

R917

R917 X_4.7K_0402

X_4.7K_0402

4.7K_0402

R920

R920 X_4.7K_0402

X_4.7K_0402

CHOK20 0.68uH_25ACHOK20 0.68uH_25A

B B

10u_0603*23 22u*26

+1.5V_DDR3_CPU1

A A

5

4

3

2

1

+0.75V DDR3 CPU0 (3.9A)

D D

+5V

R893

R893 10K_0402

10K_0402

Q101

B

2N3904

C C

PWRGD_PLD_CPU0_DDR_VTT_EN(72) PWRGD_CPU0_DDR3VTT_SFR_EN(16,22)

PWRGD_PLD_CPU0_DDR_VTT_EN PWRGD_CPU0_DDR3VTT_SFR_EN

R878 X_0R878 X_0 R877 49.9_1%R877 49.9_1%

Q91

B

2N3904

E C

2N3904

E C

7

6

C656 10p_0402C656 10p_0402 C655 1500pC655 1500p

Vref = 0.6V

U66

COMP

FB

5

UGATE

VCC

BOOT

PHASE LGATE

GND

ISL6545CBZ

3

R890 47KR890 47K

C6851uC685 1u

R892 0_0805R892 0_0805

2

C670 0.22uC670 0.22u

1 8

R891 1_0805R891 1_0805

4

R876

R876 X_1.8K_1%

X_1.8K_1%

FEEDBACK_DDR3_CPU0

+1.5V_DDR3_CPU0

Q102

2

3

4

N-SP8K10S

81

7

6

5

CHOK19 1uH_22ACHOK19 1uH_22A

R874

R874 3K_1%

3K_1%

R875

R875 12K_1%

12K_1%

12

+

EC57

EC57 820u_2.5V

820u_2.5V

+0.75V_DDR3_CPU0

C1226

C1227

10u_1206

+0.75V DDR3 CPU1 (3.9A)

+1.5V_DDR3_CPU1

B B

Vref = 0.6V

+5V

R894

R894 10K_0402

10K_0402

Q89

B

2N3904

PWRGD_PLD_CPU1_DDR_VTT_EN(72) PWRGD_CPU1_DDR3VTT_SFR_EN(16,22)

A A

PWRGD_PLD_CPU1_DDR_VTT_EN PWRGD_CPU1_DDR3VTT_SFR_EN

R1352 X_0R1352 X_0 R1353 49.9_1%R1353 49.9_1%

Q149

B

2N3904

E C

C642 10p_0402C642 10p_0402 C638 1500pC638 1500p

+5V

5

U65

7

COMP

6

FB

UGATE

VCC

BOOT

PHASE LGATE

GND

ISL6545CBZ

3

R880 47KR880 47K

C6721uC672 1u

R1390 0_0805R1390 0_0805

2

C637 0.22uC637 0.22u

1 8

R1389 1_0805R1389 1_0805

4

R879

R879 X_1.8K_1%

X_1.8K_1%

FEEDBACK_DDR3_CPU1

Q92

2

3

4

N-SP8K10S

81

7

6

5

CHOK12 1uH_22ACHOK12 1uH_22A

R1387

R1387 3K_1%

3K_1%

R1388

R1388 12K_1%

12K_1%

12

+

EC53

EC53 820u_2.5V

820u_2.5V

+0.75V_DDR3_CPU1

C1214

C1213

10u_1206

MICRO-STAR INT'L CO.,LTD

MS-9197

MSI

Size Document Description Rev

B

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

Date:

5

4

3

2

Saturday, December 01, 2007

MS-9197

021_CPU0_&_CPU1_DDR3_VTT

1

21 78

Sheet of

0A

5

4

3

2

1

CPU0 SFR 1.8V (1.0A)

+5V

D D

PWRGD_CPU0_SFR(72)

PWRGD_PLD_CPU0_SFR_EN(72) PWRGD_CPU0_DDR3VTT_SFR_EN(16,21)

C C

PWRGD_PLD_CPU0_SFR_EN PWRGD_CPU0_DDR3VTT_SFR_EN

R701 0R701 0 R700 X_0R700 X_0

+3.3V

R702

R702 1K_0402

1K_0402

C3801uC380 1u

6

U59

5

VIN

VCNTL

9

POK

EN

VIN#9

VOUT

VOUT#3

FB

GND

APL5913KAC

1

4 3

2

R754 43K_1%R754 43K_1% C408 0.033u_0402C408 0.033u_0402

R738

R738 34K_1%_0402

34K_1%_0402

7

8

+3.3V

+1.8V_CPU0_PLL

C388

C388 22u_1206

22u_1206

EC31

+

100u_25V

CPU1 SFR 1.8V (1.0A)

B B

+3.3V

R685

R685 1K_0402

1K_0402

PWRGD_CPU1_SFR(72)

PWRGD_PLD_CPU1_SFR_EN(72) PWRGD_CPU1_DDR3VTT_SFR_EN(16,21)

A A

5

PWRGD_PLD_CPU1_SFR_EN PWRGD_CPU1_DDR3VTT_SFR_EN

R684 0R684 0 R719 X_0R719 X_0

4

+5V

C3741uC374 1u

6

U57

5

VIN

VCNTL

9

POK

EN

VIN#9

VOUT

VOUT#3

FB

GND

APL5913KAC

1

4 3

2

R746 43K_1%R746 43K_1% C400 0.033u_0402C400 0.033u_0402

R732

R732 34K_1%_0402

34K_1%_0402

3

7

8

+3.3V

+1.8V_CPU1_PLL

C381

C381 22u_1206

22u_1206

EC30

+

100u_25V

MICRO-STAR INT'L CO.,LTD

MS-9197

MSI

Size Document Description Rev

B

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

Date:

2

Saturday, December 01, 2007

MS-9197

022_CPU0_&_CPU1_SFR_PLL

1

22 78

Sheet of

0A

5

+12V_CPU0

R984

R984 10K_1%_0402

10K_1%_0402

R1498 1K_1%_0402R1498 1K_1%_0402

EN_PWR_CPU0

C1256

0.1u_0402

+1.8V_CPU0_PLL

C729 1000p_0402C729 1000p_0402

C728 22pC728 22p 680pC730 680pC730

R950 200R950 200

V_6334_CPU0

R1513

X_1M

C1235

0.22u_0402

R1472 X_1K_0402R1472 X_1K_0402 R1474 X_1K_0402R1474 X_1K_0402 R1473 X_1K_0402R1473 X_1K_0402 R1475 X_1K_0402R1475 X_1K_0402 R1488 X_1K_0402R1488 X_1K_0402 R1490 X_1K_0402R1490 X_1K_0402 R1489 1K_0402R1489 1K_0402 R1491 1K_0402R1491 1K_0402

0.1u_0402

R1499 X_0R1499 X_0

P0_SENSE+ P0_SENSE-

R1445

R1445 10K_1%_0402

10K_1%_0402

R955

27.4K_1%

D D

PWRGD_CPU0_VCCP(72,76)

PWRGD_PLD_CPU0_EN(72)

VID_CPU07(29) VID_CPU06(29)

+3.3V

VID_CPU05(29) VID_CPU04(29) VID_CPU03(29)

R1463

VID_CPU02(29)

4.7K

VID_CPU01(29)

V1_CPU0

R1449 0R1449 0

VID_CPU00(29)

V2

R1447 20K_1%_0402R1447 20K_1%_0402

C1234

C1234 X_0.1u_0402

X_0.1u_0402

R1448 1K_1%_0402R1448 1K_1%_0402

C1236

0.01u_0402

R1450

R1450 15K_1%_0402

15K_1%_0402

PV_VCCP_CPU0

R833

R834

R1462

R1462 X_0

X_0

R1460

R1460 22K

22K

VR_CPU0_IOUT(29)

R1461 X_0R1461 X_0

R1446 2.4K_0402R1446 2.4K_0402

C1228

C1228 X_0.1u_0402

X_0.1u_0402

C1229

C1229 X_0.1u_0402

X_0.1u_0402

FM_CPU0_PSI_N(29)

100_1%_0402

CD270U16V

R1437 0_0402R1437 0_0402

R1438 0_0402R1438 0_0402

100_1%_0402

V_6334_CPU0

COIL2CH-1.2U18A COIL2CH-1.2U18A

CT6

+

VSENSE_DIE_CPU0_P(29)

C C

B B

VSENSE_DIE_CPU0_N(29)

+12V_CPU0 +12VP0_FET

C1257

C1257 X_0.1u_0402

X_0.1u_0402

VID_CPU07 VID_CPU06 VID_CPU05 VID_CPU04 VID_CPU03 VID_CPU02 VID_CPU01 VID_CPU00

EN_PWR_CPU0

C1258

0.1u_0402

VID_CPU00 VID_CPU01 VID_CPU02 VID_CPU03 VID_CPU04 VID_CPU05 VID_CPU06 VID_CPU07

4

+3.3V

R1502

R1502 1K_0402

1K_0402

36 33

40

1 2 3 4 5 6 7 8

13 14

15 17

16

9

11 12

32 10 18 38

37 39

V_6334_CPU0

U98

VR_RDY EN_VTT

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 PSI#

COMP FB

VDIFF VSEN

RGND OFS DAC

REF EN_PWR IMON TCOMP VR_HOT

VR_FAN TM

35

R1503

R1503 2K_0805

2K_0805

R1501

243K_1%

243K_1% RT1

RT1 10KRT1%

10KRT1%

R964 1K_0402R964 1K_0402 R963 1K_0402R963 1K_0402 R977 1K_0402R977 1K_0402 R975 1K_0402R975 1K_0402 R978 1K_0402R978 1K_0402 R976 1K_0402R976 1K_0402 R983 X_1K_0402R983 X_1K_0402 R982 X_1K_0402R982 X_1K_0402

+5V

R951

2.2

19

VCC

PWM1 ISEN1-

ISEN1+

PWM2 ISEN2-

ISEN2+

PWM3 ISEN3-

ISEN3+

PWM4 ISEN4-

ISEN4+

FS34SS

GND

ISL6334CRZ_QFN40-RH

41

R1500

64.9K_1%_0402

+1.1V_CPU0

C716

C716 1u_0805

1u_0805

26 27 28

20 21 22

31 30 29

25 24 23

V_6334_CPU0

PH1_CPU0

2.8K_1%_0402

C1254 68pC1254 68p

PH2_CPU0

2.8K_1%_0402

C1233 68pC1233 68p

PH3_CPU0

2.8K_1%_0402

C1253 68pC1253 68p

PH4_CPU0

2.8K_1%_0402

C1242 68pC1242 68p

PWM1_CPU0

R1471

0.1u_0402

R979 432_1%R979 432_1%

PWM2_CPU0

R1444

0.1u_0402

R959 432_1%R959 432_1%

PWM3_CPU0

R1497

0.1u_0402

R985 432_1%R985 432_1%

PWM4_CPU0

R1459

C743

0.1u_0402

R960 432_1%R960 432_1%

C749

C731

C752

ISEN1_CPU0

ISEN2_CPU0

ISEN3_CPU0

ISEN4_CPU0

2.2_1%_0805

C1244

0.1u_0402

2.2_1%_0805

C1232

0.1u_0402

C1255

0.1u_0402

C1241

0.1u_0402

2.2_1%_0805

3

+12V_CPU0

R1359

R1360

R1 R2

X_0_0805

C1

+12V_CPU0

R1367

R1369

X_0_0805

+12V_CPU0

R1355

R1357

X_0_0805

+12V_CPU0

R1363

R1365

X_0_0805

R1 R2 C1

R1429 2.2_1%_0805R1429 2.2_1%_0805

R1361

R1361 0_0805

0_0805

PWM1_CPU0

C1189 1uC1189 1u

C1269

0.1u

R1414 2.2_1%_0805R1414 2.2_1%_0805

R1368

R1368 0_0805

0_0805

PWM2_CPU0

C1191 1uC1191 1u

C1270

0.1u

R1409 2.2_1%_0805R1409 2.2_1%_0805

R1356

R1356 0_0805

0_0805

PWM3_CPU0

C1188 1uC1188 1u

C1271

0.1u

R1412 2.2_1%_0805R1412 2.2_1%_0805

R1364

R1364 0_0805

0_0805

PWM4_CPU0

C1190 1uC1190 1u

C1272

0.1u

ISL6622ISL6612

POP NON POP

POPNON POP

NON POP POP

ISL6622

U91

2

BOOT

UGATE

9

PHASE

VCC

8

GND

UVCC

7

PVCC

LGATE

4

PWM

5

GND

EP_GND

GD SEL

3

ISL6622

U93

2

BOOT

UGATE

9

PHASE

VCC

8

GND

UVCC

7

PVCC

LGATE

4

PWM

5

GND

EP_GND

GD SEL

3

ISL6622

U87

2

BOOT

UGATE

9

PHASE

VCC

8

GND

UVCC

7

PVCC

LGATE

4

PWM

5

GND

EP_GND

GD SEL

3

ISL6622

U92

2

BOOT

UGATE

9

PHASE

VCC

8

GND

UVCC

7

PVCC

LGATE

4

PWM

5

GND

EP_GND

GD SEL

3

1 10

6 11

1 10

6 11

1 10

6 11

1 10

6 11

U_G1_CPU0 PHASE1_CPU0

C1219 0.1uC1219 0.1u

L_G1_CPU0

U_G2_CPU0 PHASE2_CPU0

C1221 0.1uC1221 0.1u

L_G2_CPU0

U_G3_CPU0 PHASE3_CPU0

C1215 0.1uC1215 0.1u

L_G3_CPU0

U_G4_CPU0 PHASE4_CPU0

C1220 0.1uC1220 0.1u

L_G4_CPU0

2

U_G1_CPU0

R1411 1_0805R1411 1_0805

PHASE1_CPU0 L_G1_CPU0

U_G2_CPU0

R1415 1_0805R1415 1_0805

PHASE2_CPU0 L_G2_CPU0

U_G3_CPU0

R1428 1_0805R1428 1_0805

PHASE3_CPU0 L_G3_CPU0

U_G4_CPU0

R1430 1_0805R1430 1_0805

PHASE4_CPU0 L_G4_CPU0

R1397 10K_0402R1397 10K_0402

R1358 0_0805R1358 0_0805

R1398 10K_0402R1398 10K_0402

R1366 0_0805R1366 0_0805

R1410 10K_0402R1410 10K_0402

R1392 0_0805R1392 0_0805

R1413 10K_0402R1413 10K_0402

R1362 0_0805R1362 0_0805

+12VP0_FET

4 3 2 1

N-S4841NHT1G

N-S4841NHT1G Q99

Q99

4 3 2 1

NS4833NT1G

+12VP0_FET

4 3 2 1

N-S4841NHT1G

Q97

4 3 2 1

NS4833NT1G

+12VP0_FET

4 3 2 1

N-S4841NHT1G

Q100

4 3 2 1

NS4833NT1G

+12VP0_FET

4 3 2 1

N-S4841NHT1G

Q98

4 3 2 1

NS4833NT1G

C733 10u_1206C733 10u_1206 C718 10u_1206C718 10u_1206

5

Q109

5

C732 10u_1206C732 10u_1206 C734 10u_1206C734 10u_1206

5

Q107

5

C717 10u_1206C717 10u_1206 C735 10u_1206C735 10u_1206

5

Q110

5

C720 10u_1206C720 10u_1206 C719 10u_1206C719 10u_1206

5

Q108

5

R927

2.2_1%_0805

R925

2.2_1%_0805

R928

2.2_1%_0805

R926

2.2_1%_0805

CHOK10 0.155uH 31ACHOK10 0.155uH 31A

C698

C698 2200p

2200p

PH1_CPU0

CHOK8 0.155uH 31ACHOK8 0.155uH 31A

C696

C696 2200p

2200p

PH2_CPU0

CHOK11 0.155uH 31ACHOK11 0.155uH 31A

C699

C699 2200p

2200p

PH3_CPU0

CHOK9 0.155uH 31ACHOK9 0.155uH 31A

C697

C697 2200p

2200p

PH4_CPU0

SP10

SP10 X_Short PAD 0402

X_Short PAD 0402

SP12

SP12 X_Short PAD 0402

X_Short PAD 0402

SP9

SP9 X_Short PAD 0402

X_Short PAD 0402

SP11

SP11 X_Short PAD 0402

X_Short PAD 0402

1

SP5

SP5 X_Short PAD 0402

X_Short PAD 0402

ISEN1_CPU0

SP7

SP7 X_Short PAD 0402

X_Short PAD 0402

ISEN2_CPU0

SP8

SP8 X_Short PAD 0402

X_Short PAD 0402

ISEN3_CPU0

SP6

SP6 X_Short PAD 0402

X_Short PAD 0402

ISEN4_CPU0

PV_VCCP_CPU0

10u*11

PV_VCCP_CPU0

C558 10u_0805C558 10u_0805 C576 10u_0805C576 10u_0805 C620 10u_0805C620 10u_0805 C621 10u_0805C621 10u_0805 C577 10u_0805C577 10u_0805 C589 10u_0805C589 10u_0805 C565 10u_0805C565 10u_0805 C578 10u_0805C578 10u_0805 C594 10u_0805C594 10u_0805 C592 10u_0805C592 10u_0805 C579 10u_0805C579 10u_0805

A A

10u*25

PV_VCCP_CPU0

C567 10u_0805C567 10u_0805 C588 10u_0805C588 10u_0805 C623 10u_0805C623 10u_0805 C622 10u_0805C622 10u_0805 C590 10u_0805C590 10u_0805 C591 10u_0805C591 10u_0805 C624 10u_0805C624 10u_0805 C626 10u_0805C626 10u_0805 C593 10u_0805C593 10u_0805 C580 10u_0805C580 10u_0805 C595 10u_0805C595 10u_0805 C597 10u_0805C597 10u_0805 C569 10u_0805C569 10u_0805 C625 10u_0805C625 10u_0805 C599 10u_0805C599 10u_0805 C596 10u_0805C596 10u_0805 C627 10u_0805C627 10u_0805 C598 10u_0805C598 10u_0805 C628 10u_0805C628 10u_0805 C600 10u_0805C600 10u_0805 C629 10u_0805C629 10u_0805 C632 10u_0805C632 10u_0805 C566 10u_0805C566 10u_0805 C568 10u_0805C568 10u_0805 C570 10u_0805C570 10u_0805

5

22u*26 on socket

PV_VCCP_CPU0

C504 22u_1206C504 22u_1206 C477 22u_1206C477 22u_1206 C478 22u_1206C478 22u_1206 C479 22u_1206C479 22u_1206 C501 22u_1206C501 22u_1206 C527 22u_1206C527 22u_1206 C505 22u_1206C505 22u_1206 C502 22u_1206C502 22u_1206 C526 22u_1206C526 22u_1206 C529 22u_1206C529 22u_1206 C480 22u_1206C480 22u_1206 C503 22u_1206C503 22u_1206 C528 22u_1206C528 22u_1206 C1134 22u_1206C1134 22u_1206 C1135 22u_1206C1135 22u_1206 C1136 22u_1206C1136 22u_1206 C1150 22u_1206C1150 22u_1206 C1149 22u_1206C1149 22u_1206 C1164 22u_1206C1164 22u_1206 C1161 22u_1206C1161 22u_1206 C1163 22u_1206C1163 22u_1206 C1148 22u_1206C1148 22u_1206 C1147 22u_1206C1147 22u_1206 C1133 22u_1206C1133 22u_1206 C1146 22u_1206C1146 22u_1206 C1162 22u_1206C1162 22u_1206

4

330u*3 on top side

PV_VCCP_CPU0

+

12

EC46

EC48

330u_2.5V

PV_VCCP_CPU0

+

12

+

12

EC62

EC61

X_330u_2.5V

+

12

EC47

330u_2.5V

MICRO-STAR INT'L CO.,LTD

MS-9197

MSI

Size Document Description Rev

C

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

Date:

3

2

Saturday, December 01, 2007

MS-9197

023_CPU0_VCORE

1

Sheet of

23 78

0A

5

+12V_CPU1

R1506

R1506 10K_1%_0402

10K_1%_0402

R1507 1K_1%_0402R1507 1K_1%_0402

EN_PWR_CPU1

C1260

0.1u_0402

D D

PWRGD_CPU1_VCCP(72,76)

PWRGD_PLD_CPU1_EN(72)

+1.8V_CPU1_PLL

VID_CPU17(33)

R958

4.7K

V1_CPU1

R1453 0R1453 0

VID_CPU16(33) VID_CPU15(33) VID_CPU14(33) VID_CPU13(33) VID_CPU12(33) VID_CPU11(33) VID_CPU10(33)

V2

R953 20K_1%_0402R953 20K_1%_0402

C1239 22pC1239 22p

C1238

C1238 X_0.1u_0402

X_0.1u_0402

R1454 1K_1%_0402R1454 1K_1%_0402

C1240

0.01u_0402

R1455

R1455 15K_1%_0402

15K_1%_0402

680pC711 680pC711

R1514

C1243

0.22u_0402

+3.3V

100_1%_0402

V_6334_CPU1

VR_CPU1_IOUT(33)

CT5

R1468 X_0R1468 X_0

PV_VCCP_CPU1

R1331

R1330

R1467

R1467 X_0

X_0

R1466

R1466 22K

22K

R954 2.4K_0402R954 2.4K_0402

C1230

C1230 X_0.1u_0402

X_0.1u_0402

C1231

C1231 X_0.1u_0402

X_0.1u_0402

OSCON

FM_CPU1_PSI_N(33)

CD270U16V

R1441 0_0402R1441 0_0402

R1442 0_0402R1442 0_0402

COIL1CH-1.2U18A COIL1CH-1.2U18A

+

VSENSE_DIE_CPU1_P(33)

VSENSE_DIE_CPU1_N(33)

C C

B B

+12V_CPU1 +12VP1_FET

R1508 X_0R1508 X_0

C721 1000p_0402C721 1000p_0402

R948 200R948 200

P1_SENSE+ P1_SENSE-

V_6334_CPU1

X_1M

R1452

R1452 10K_1%_0402

10K_1%_0402

R1440

27.4K_1%

R1480 X_1K_0402R1480 X_1K_0402 R1478 X_1K_0402R1478 X_1K_0402 R1481 X_1K_0402R1481 X_1K_0402 R1479 X_1K_0402R1479 X_1K_0402 R1495 X_1K_0402R1495 X_1K_0402 R1493 X_1K_0402R1493 X_1K_0402 R1496 X_1K_0402R1496 X_1K_0402 R1494 1K_0402R1494 1K_0402

C1261

C1261 X_0.1u_0402

X_0.1u_0402

VID_CPU17 VID_CPU16 VID_CPU15 VID_CPU14 VID_CPU13 VID_CPU12 VID_CPU11 VID_CPU10

EN_PWR_CPU1

+3.3V

V_6334_CPU1

C1262

0.1u_0402

R1511

R1511 1K_0402

1K_0402

36 33

40

13 14

15 17

16

11 12

32 10 18 38

37 39

4

1 2 3 4 5 6 7 8

9

R1512

R1512 2K_0805

2K_0805

R1510

243K_1%

243K_1% RT2

RT2 10KRT1%

10KRT1%

VID_CPU10 VID_CPU11 VID_CPU12 VID_CPU13 VID_CPU14 VID_CPU15 VID_CPU16 VID_CPU17

U99

VR_RDY EN_VTT

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 PSI#

COMP FB

VDIFF VSEN

RGND OFS DAC

REF EN_PWR IMON TCOMP VR_HOT

VR_FAN TM

+5V

6X6 QFN

19

VCC

FS34SS

35

R1509

64.9K_1%_0402

R961 1K_0402R961 1K_0402 R962 1K_0402R962 1K_0402 R971 1K_0402R971 1K_0402 R973 1K_0402R973 1K_0402 R972 1K_0402R972 1K_0402 R974 1K_0402R974 1K_0402 R980 X_1K_0402R980 X_1K_0402 R981 X_1K_0402R981 X_1K_0402

R949

2.2

C722

C722 1u_0805

1u_0805

26

PWM1

27

ISEN1-

28

ISEN1+

20

PWM2

21

ISEN2-

22

ISEN2+

31

PWM3

30

ISEN3-

29

ISEN3+

25

PWM4

24

ISEN4-

23

ISEN4+

GND

ISL6334CRZ_QFN40-RH

41

V_6334_CPU1

PH1_CPU1

2.8K_1%_0402

C748 68pC748 68p

PH2_CPU1

2.8K_1%_0402

C737 68pC737 68p

PH3_CPU1

2.8K_1%_0402

C750 68pC750 68p

PH4_CPU1

2.8K_1%_0402

C738 68pC738 68p

+1.1V_CPU1

PWM1_CPU1

R1476

0.1u_0402

R1492 432_1%R1492 432_1%

PWM2_CPU1

R1451

0.1u_0402

R1465 432_1%R1465 432_1%

PWM3_CPU1

R1505

0.1u_0402

R1504 432_1%R1504 432_1%

PWM4_CPU1

R1477

C742

0.1u_0402

R1464 432_1%R1464 432_1%

C747

C723

C751

ISEN1_CPU1

ISEN2_CPU1

ISEN3_CPU1

ISEN4_CPU1

C1245

0.1u_0402

C1237

0.1u_0402

C1259

0.1u_0402

C1246

0.1u_0402

+12V_CPU1

R1375

2.2_1%_0805

+12V_CPU1

R1383

2.2_1%_0805

+12V_CPU1

R1371

2.2_1%_0805

+12V_CPU1

R1379

2.2_1%_0805

3

R1377

X_0_0805

R1385

X_0_0805

R1373

X_0_0805

R1381

X_0_0805

R1417 2.2_1%_0805R1417 2.2_1%_0805

R1376

R1376 0_0805

0_0805

PWM1_CPU1

C1193 1uC1193 1u

C1273

0.1u

R1422 2.2_1%_0805R1422 2.2_1%_0805

R1384

R1384 0_0805

0_0805

PWM2_CPU1

C1195 1uC1195 1u

C1274

0.1u

R1416 2.2_1%_0805R1416 2.2_1%_0805

R1372

R1372 0_0805

0_0805

PWM3_CPU1

C1192 1uC1192 1u

C1275

0.1u

R1420 2.2_1%_0805R1420 2.2_1%_0805

R1380

R1380 0_0805

0_0805

PWM4_CPU1

C1194 1uC1194 1u

C1276

0.1u

2

U_G1_CPU1

ISL6622

U89

2

BOOT

9

VCC

8

GND

UVCC

7

PVCC

4

PWM

5

GND

GD SEL

3

U94

2

BOOT

9

VCC

8

GND

UVCC

7

PVCC

4

PWM

5

GND

GD SEL

3

U88

2

BOOT

9

VCC

8

GND

UVCC

7

PVCC

4

PWM

5

GND

GD SEL

3

U90

2

BOOT

9

VCC

8

GND

UVCC

7

PVCC

4

PWM

5

GND

GD SEL

3

UGATE PHASE

LGATE

EP_GND

ISL6622

UGATE PHASE

LGATE

EP_GND

ISL6622

UGATE PHASE

LGATE

EP_GND

ISL6622

UGATE PHASE

LGATE

EP_GND

1 10

6 11

1 10

6 11

1 10

6 11

1 10

6 11

U_G1_CPU1 PHASE1_CPU1

C1223 0.1uC1223 0.1u

L_G1_CPU1

U_G2_CPU1 PHASE2_CPU1

C1216 0.1uC1216 0.1u

L_G2_CPU1

U_G3_CPU1 PHASE3_CPU1

C1222 0.1uC1222 0.1u

L_G3_CPU1

U_G4_CPU1 PHASE4_CPU1

C1224 0.1uC1224 0.1u

L_G4_CPU1

R1419 1_0805R1419 1_0805

PHASE1_CPU1 L_G1_CPU1

U_G2_CPU1

R1423 1_0805R1423 1_0805

PHASE2_CPU1 L_G2_CPU1

U_G3_CPU1

R1431 1_0805R1431 1_0805

PHASE3_CPU1 L_G3_CPU1

U_G4_CPU1

R1421 1_0805R1421 1_0805

PHASE4_CPU1 L_G4_CPU1

R1418 10K_0402R1418 10K_0402

R1374 0_0805R1374 0_0805

R1401 10K_0402R1401 10K_0402

R1382 0_0805R1382 0_0805

R1399 10K_0402R1399 10K_0402

R1370 0_0805R1370 0_0805

R1400 10K_0402R1400 10K_0402

R1378 0_0805R1378 0_0805

+12VP1_FET

4 3 2 1

N-S4841NHT1G

N-S4841NHT1G Q95

Q95

4 3 2 1

NS4833NT1G

+12VP1_FET

4 3 2 1

N-S4841NHT1G

Q93

4 3 2 1

NS4833NT1G

+12VP1_FET

4 3 2 1

N-S4841NHT1G

Q96

4 3 2 1

NS4833NT1G

+12VP1_FET

4 3 2 1

N-S4841NHT1G

Q94

4 3 2 1

NS4833NT1G

C714 10u_1206C714 10u_1206 C713 10u_1206C713 10u_1206

5

Q105

5

C724 10u_1206C724 10u_1206 C727 10u_1206C727 10u_1206

5

Q103

5

C715 10u_1206C715 10u_1206 C712 10u_1206C712 10u_1206

5

Q106

5

C725 10u_1206C725 10u_1206 C726 10u_1206C726 10u_1206

5

Q104

5

R923

2.2_1%_0805

R921

2.2_1%_0805

R924

2.2_1%_0805

R922

2.2_1%_0805

CHOK6 0.155uH 31ACHOK6 0.155uH 31A

C694

C694 2200p

2200p

PH1_CPU1

CHOK4 0.155uH 31ACHOK4 0.155uH 31A

C692

C692 2200p

2200p

PH2_CPU1

CHOK7 0.155uH 31ACHOK7 0.155uH 31A

C695

C695 2200p

2200p

PH3_CPU1

CHOK5 0.155uH 31ACHOK5 0.155uH 31AR1381

C693

C693 2200p

2200p

PH4_CPU1

SP16

SP16 X_Short PAD 0402

X_Short PAD 0402

SP20

SP20 X_Short PAD 0402

X_Short PAD 0402

SP14

SP14 X_Short PAD 0402

X_Short PAD 0402

SP18

SP18 X_Short PAD 0402

X_Short PAD 0402

1

SP15

SP15 X_Short PAD 0402

X_Short PAD 0402

ISEN1_CPU1

SP19

SP19 X_Short PAD 0402

X_Short PAD 0402

ISEN2_CPU1

SP13

SP13 X_Short PAD 0402

X_Short PAD 0402

ISEN3_CPU1

SP17

SP17 X_Short PAD 0402

X_Short PAD 0402

ISEN4_CPU1

0.5V~1.6V/110A

PV_VCCP_CPU1

10u*11 10u*25

PV_VCCP_CPU1PV_VCCP_CPU1

C561 10u_0805C561 10u_0805 C606 10u_0805C606 10u_0805 C603 10u_0805C603 10u_0805 C604 10u_0805C604 10u_0805 C563 10u_0805C563 10u_0805 C571 10u_0805C571 10u_0805 C607 10u_0805C607 10u_0805 C610 10u_0805C610 10u_0805 C586 10u_0805C586 10u_0805 C560 10u_0805C560 10u_0805 C564 10u_0805C564 10u_0805 C523 22u_1206C523 22u_1206

A A

5

C585 10u_0805C585 10u_0805 C584 10u_0805C584 10u_0805 C575 10u_0805C575 10u_0805 C605 10u_0805C605 10u_0805 C572 10u_0805C572 10u_0805 C608 10u_0805C608 10u_0805 C587 10u_0805C587 10u_0805 C611 10u_0805C611 10u_0805 C612 10u_0805C612 10u_0805 C617 10u_0805C617 10u_0805 C619 10u_0805C619 10u_0805 C618 10u_0805C618 10u_0805 C614 10u_0805C614 10u_0805 C609 10u_0805C609 10u_0805 C602 10u_0805C602 10u_0805 C582 10u_0805C582 10u_0805 C601 10u_0805C601 10u_0805 C583 10u_0805C583 10u_0805 C559 10u_0805C559 10u_0805 C573 10u_0805C573 10u_0805 C574 10u_0805C574 10u_0805 C613 10u_0805C613 10u_0805 C616 10u_0805C616 10u_0805 C615 10u_0805C615 10u_0805 C562 10u_0805C562 10u_0805

22u*26 on socket

PV_VCCP_CPU1

C476 22u_1206C476 22u_1206 C475 22u_1206C475 22u_1206 C474 22u_1206C474 22u_1206 C473 22u_1206C473 22u_1206 C500 22u_1206C500 22u_1206 C499 22u_1206C499 22u_1206 C498 22u_1206C498 22u_1206 C497 22u_1206C497 22u_1206 C496 22u_1206C496 22u_1206 C525 22u_1206C525 22u_1206

C522 22u_1206C522 22u_1206 C524 22u_1206C524 22u_1206 C1139 22u_1206C1139 22u_1206 C1138 22u_1206C1138 22u_1206 C1137 22u_1206C1137 22u_1206 C1151 22u_1206C1151 22u_1206 C1152 22u_1206C1152 22u_1206 C1167 22u_1206C1167 22u_1206 C1166 22u_1206C1166 22u_1206 C1165 22u_1206C1165 22u_1206 C1140 22u_1206C1140 22u_1206 C1168 22u_1206C1168 22u_1206 C1153 22u_1206C1153 22u_1206 C1154 22u_1206C1154 22u_1206 C1155 22u_1206C1155 22u_1206

330u*3 on top side

PV_VCCP_CPU1

+

12

EC43

330u_2.5V

PV_VCCP_CPU1

+

12

EC60

X_330u_2.5V

4

+

12

EC44

330u_2.5V

+

12

EC59

X_330u_2.5V

+

12

EC45

330u_2.5V

RESERVE

MICRO-STAR INT'L CO.,LTD

MS-9197

MSI

Size Document Description Rev

C

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

Date:

3

2

Saturday, December 01, 2007

MS-9197

024_CPU1_VCORE

1

Sheet of

24 78

0A

5

C1086

0.1u_0402

110

+3.3V_CK410B

166.67

100.001

CLK_100M_ICH_ESI_DP (56)

CLK_100M_ICH_ESI_DN (56)

CLK_100M_ICH_SATA_DP (56)

CLK_100M_ICH_SATA_DN (56)

CLK_100M_IBMC_DP (63)

CLK_100M_IBMC_DN (63)

CLK_100M_DB800_DP (26)

CLK_100M_DB800_DN (26)

CLK_100M_ICH_PCIE_DP (54)

CLK_100M_ICH_PCIE_DN (54)

+3.3V

FB18

FB18 600Ohm_0805

600Ohm_0805

C1085

C1080

0.1u_0402

10u_1206

C1108

C1108 10u_1206

10u_1206

SMB_HOST_3V3_CLK(26,74,77) SMB_HOST_3V3_DAT(26,74,77)

FS_C FS_B FS_A CPU_MHZ

0 0 1 133.33

10

DEFAULT=100MHZ

R577 49.9_1%_0402R577 49.9_1%_0402

R578 49.9_1%_0402R578 49.9_1%_0402

R576 49.9_1%_0402R576 49.9_1%_0402

R575 49.9_1%_0402R575 49.9_1%_0402

R573 49.9_1%_0402R573 49.9_1%_0402

R574 49.9_1%_0402R574 49.9_1%_0402

R572 49.9_1%_0402R572 49.9_1%_0402

R571 49.9_1%_0402R571 49.9_1%_0402

R580 49.9_1%_0402R580 49.9_1%_0402

R579 49.9_1%_0402R579 49.9_1%_0402

CLK_100M_DB800_R_DP CLK_100M_DB800_R_DN

CLK_100M_IBMC_R_DP CLK_100M_IBMC_R_DN

CLK_100M_SATA_R_DP CLK_100M_SATA_R_DN

CLK_100M_ESI_R_DP CLK_100M_ESI_R_DN

CLK_100M_ICH_PCIER_DP CLK_100M_ICH_PCIER_DN

C1087

0.1u_0402

R661

R661 X_2.7K_0402

X_2.7K_0402

R645

R645 1K_0402

1K_0402

R12741R1274 1

C1109

0.1u_0402

R662

2.7K_0402

R647

R647 X_1K_0402

X_1K_0402

5

R590 33_0402R590 33_0402

R591 33_0402R591 33_0402

R589 33_0402R589 33_0402

R588 33_0402R588 33_0402

R586 33_0402R586 33_0402

R587 33_0402R587 33_0402

R585 33_0402R585 33_0402

R584 33_0402R584 33_0402

R593 33_0402R593 33_0402

R592 33_0402R592 33_0402

D D

R12621R1262 1

C1081

C1081 10u_1206

10u_1206

C C

+3.3V

R660

2.7K_0402

R644

R644 X_1K_0402

X_1K_0402

B B

CLK_100M_ESI_R_DP

CLK_100M_ESI_R_DN

CLK_100M_SATA_R_DP

CLK_100M_SATA_R_DN

CLK_100M_IBMC_R_DP

CLK_100M_IBMC_R_DN

CLK_100M_DB800_R_DP

A A

CLK_100M_DB800_R_DN

CLK_100M_ICH_PCIER_DP

CLK_100M_ICH_PCIER_DN

4

R1275

2.2

C1114

C1113

10u_1206

0.1u_0402

U2C1

35

VDDA

38

VDDCPU<2>

47

VDDCPU<1>

44

VDDCPU<0>

28

VDDSRC<2>

25

VDDSRC<1>

15

VDDSRC<0>

8

VDDPCI<1>

1

VDDPCI<0>

53

VDDREF

12

VDD48

26

SRCCLKT4

27

SRCCLKC4

24

SRCCLKT3

23

SRCCLKC3

21

SRCCLKT2

22

SRCCLKC2

19

SRCCLKT1

18

SRCCLKC1

16

SRCCLKT0

17

SRCCLKC0

29

SCLK

30

SDATA

48

FS_A

49

FS_B_TEST_MODE

56

FS_C_TEST_SEL

34

GNDA

41

GNDCPU

20

GNDSRC

7

GNDPCI<1>

2

GNDPCI<0>

50

GNDREF

14

GND48

ICS932

VTT_PWRGD_N_PD

SMBUS ADDRESS - 0XD2

4

REF1 REF0

CPUCLKT3

CPUCLKC3

CPUCLKT2

CPUCLKC2

CPUCLKT1

CPUCLKC1

CPUCLKT0

CPUCLKC0 PCICLK_F<2> PCICLK_F<1> PCICLK_F<0>

PCICLK<3> PCICLK<2> PCICLK<1> PCICLK<0>

48MHZ

IREF

CK410B+

3

+3.3V +3.3V_CK410B

R632 0_0402R632 0_0402

Y6 14.31818MHzY6 14.31818MHz

C361

52

X1

51

X2

54

CLK_14M_ICH_R

55

CLK_133M_IOH_CSI0_R_DP

37

CLK_133M_IOH_CSI0_R_DN

36

CLK_133M_IOH_CSI1_R_DP

40

CLK_133M_IOH_CSI1_R_DN

39

CLK_133M_CPU0_R_DP

43

CLK_133M_CPU0_R_DN

42

CLK_133M_CPU1_R_DP

46

CLK_133M_CPU1_R_DN

45

CLK_33M_DEBUG_R

11

CLK_33M_TPM_R_DP

10

CLK_33M_ICH_R

9 6 5

CLK_33M_IBMC_R

4 3

CLK_48M_USB_R

13

PWRGD_CPU0_M_VTT

31

33

32

NC

CLK_48M_USB_R

CLK_33M_ICH_R PCI_CLK_33M_ICH

C356 33p_0402C356 33p_0402

3

C361 33p_0402

33p_0402

+3.3V

R635

R635 475_1%_0402

475_1%_0402

R646 33_0402R646 33_0402 R594 10_0402R594 10_0402 R564 10_0402R564 10_0402

R595 33_0402R595 33_0402 R597 33_0402R597 33_0402 R596 33_0402R596 33_0402 R565 33_0402R565 33_0402

R637 33_1%_0402R637 33_1%_0402

R636 33_1%_0402R636 33_1%_0402

R639 33_1%_0402R639 33_1%_0402

R638 33_1%_0402R638 33_1%_0402

R641 33_1%_0402R641 33_1%_0402

R640 33_1%_0402R640 33_1%_0402

R643 33_1%_0402R643 33_1%_0402

R642 33_1%_0402R642 33_1%_0402

R634

4.7K_0402

DS

FB19 600Ohm_0805FB19 600Ohm_0805

Q146

G

2N7002

CLK_14M_ICHCLK_14M_ICH_R CLK_48M_USB_ICH CLK_48M_USB_IBMC

CLK_33M_DEBUGCLK_33M_DEBUG_R CLK_33M_IBMCCLK_33M_IBMC_R CLK_33M_TPM_RCLK_33M_TPM_R_DP

R653 49.9_1%_0402R653 49.9_1%_0402

R652 49.9_1%_0402R652 49.9_1%_0402

R655 49.9_1%_0402R655 49.9_1%_0402

R654 49.9_1%_0402R654 49.9_1%_0402

R657 49.9_1%_0402R657 49.9_1%_0402

R656 49.9_1%_0402R656 49.9_1%_0402

R659 49.9_1%_0402R659 49.9_1%_0402

R658 49.9_1%_0402R658 49.9_1%_0402

PWRGD_CPU0_VTT (14,16,17,26,29,72)

2

C1112

C1104

C1104 10u_1206

10u_1206

2

C1112

0.1u_0402

CLK_14M_ICH (57) CLK_48M_USB_ICH (56) CLK_48M_USB_IBMC (63)

CLK_33M_DEBUG (60) CLK_33M_IBMC (63) CLK_33M_TPM_R (60) PCI_CLK_33M_ICH (56)

MSI

1

C1110

C1111

0.1u_0402

CLK_133M_IOH_CSI0_DP (48)

CLK_133M_IOH_CSI0_DN (48)

CLK_133M_IOH_CSI1_DP (48)

CLK_133M_IOH_CSI1_DN (48)

CLK_133M_CPU0_DP (29)

CLK_133M_CPU0_DN (29)

CLK_133M_CPU1_DP (33)

CLK_133M_CPU1_DN (33)

C1110

0.1u_0402

CLK_14M_ICH CLK_48M_USB_ICH CLK_48M_USB_IBMC CLK_33M_DEBUG CLK_33M_IBMC CLK_33M_TPM_R PCI_CLK_33M_ICH

C1090

0.1u_0402

C1089

0.1u_0402

CI25 10p_0402CI25 10p_0402 CI21 10p_0402CI21 10p_0402 CI19 10p_0402CI19 10p_0402 CI22 10p_0402CI22 10p_0402 CI24 10p_0402CI24 10p_0402 CI23 10p_0402CI23 10p_0402 CI20 10p_0402CI20 10p_0402

C1088

0.1u_0402

EMI

MICRO-STAR INT'L CO.,LTD

MS-9197

Size Document Description Rev

B

Date:

025_CK410B+_CLOCK_GENERATOR

Saturday, December 01, 2007

MS-9197

Sheet of

1

25 78

0A

5

+3.3V_DB800 +3.3V_DB800 +3.3V_DB800_A

U33

R348

R347

2.7K_0402

D D

R346

R346 X_1K_1%_0402

X_1K_1%_0402

C C

2.7K_0402

R350

R350 X_1K_1%_0402

X_1K_1%_0402

+3.3V

R405

R405 1K_1%_0402

1K_1%_0402

CLK_100M_DB800_DP(25) CLK_100M_DB800_DN(25)

SMB_HOST_3V3_CLK(25,74,77) SMB_HOST_3V3_DAT(25,74,77)

PWRGD_CPU0_VTT(14,16,17,25,29,72)

R393 1K_1%_0402R393 1K_1%_0402

PU_DB800_PLL_MODE

PU_DB800_LOWBW

PU_DB800_OE_INV

R404

R404 475_1%_0402

475_1%_0402

R1093

R1093 1K_1%_0402

1K_1%_0402

OE_INV 0 OE_0~OE_7 High Low PWRDWN_N High activeLow active

U33

4 5 1

22 23 24

26 27 28

44 36 35 43

7 15 14

6 40

46 48

39 31 19 11

2

DB803

SRC_IN_P SRC_IN_N SRC_DIV_N

BYPASS_N_PLL SCLK SDATA

PWRDWN_N DIF_STOP_N HIGH_BW_N

OE_7 OE_6 OE_5 OE_4 OE_3 OE_2 OE_1 OE_0

OE_INV IREF VDD_A

VDD4 VDD3 VDD2 VDD1 VDD0

4

R403 33_0402R403 33_0402 R394 33_0402R394 33_0402 R381 33_0402R381 33_0402 R380 33_0402R380 33_0402 R379 33_0402R379 33_0402 R369 33_0402R369 33_0402 R368 33_0402R368 33_0402 R357 33_0402R357 33_0402 R370 33_0402R370 33_0402 R358 33_0402R358 33_0402 R382 33_0402R382 33_0402 R371 33_0402R371 33_0402 R384 33_0402R384 33_0402 R383 33_0402R383 33_0402 R396 33_0402R396 33_0402 R395 33_0402R395 33_0402

DIF_7_P

DIF_7_N

DIF_6_P

DIF_6_N

DIF_5_P

DIF_5_N

DIF_4_P

DIF_4_N

DIF_3_P

DIF_3_N

DIF_2_P

DIF_2_N

DIF_1_P

DIF_1_N

DIF_0_P

DIF_0_N

LOCK

GND_A

GND4 GND3 GND2 GND1 GND0

ICS9D803

CLK_100M_SLOT1_R_DP

42

CLK_100M_SLOT1_R_DN

41

CLK_100M_SLOT2_R_DP

38

CLK_100M_SLOT2_R_DN

37

CLK_100M_SLOT3_R_DP

34

CLK_100M_SLOT3_R_DN

33

CLK_100M_SLOT4_R_DP

30

CLK_100M_SLOT4_R_DN

29

CLK_100M_SLOT5_R_DP

20

CLK_100M_SLOT5_R_DN

21

CLK_100M_IOH_PE0CLK_R_DP

16

CLK_100M_IOH_PE0CLK_R_DN

17

CLK_100M_IOH_PE1CLK_R_DP

12

CLK_100M_IOH_PE1CLK_R_DN

13

CLK_100M_NIC_R_DP

8

CLK_100M_NIC_R_DN

9

45

47 32

25 18 10 3

1

3

R402 49.9_1%_0402R402 49.9_1%_0402 R392 49.9_1%_0402R392 49.9_1%_0402 R378 49.9_1%_0402R378 49.9_1%_0402 R377 49.9_1%_0402R377 49.9_1%_0402 R376 49.9_1%_0402R376 49.9_1%_0402 R367 49.9_1%_0402R367 49.9_1%_0402 R366 49.9_1%_0402R366 49.9_1%_0402 R356 49.9_1%_0402R356 49.9_1%_0402 R372 49.9_1%_0402R372 49.9_1%_0402 R359 49.9_1%_0402R359 49.9_1%_0402 R385 49.9_1%_0402R385 49.9_1%_0402 R373 49.9_1%_0402R373 49.9_1%_0402 R387 49.9_1%_0402R387 49.9_1%_0402 R386 49.9_1%_0402R386 49.9_1%_0402 R398 49.9_1%_0402R398 49.9_1%_0402 R397 49.9_1%_0402R397 49.9_1%_0402

CLK_100M_SLOT1_DP (54) CLK_100M_SLOT1_DN (54) CLK_100M_SLOT2_DP (54) CLK_100M_SLOT2_DN (54) CLK_100M_SLOT3_DP (54) CLK_100M_SLOT3_DN (54) CLK_100M_SLOT4_DP (54) CLK_100M_SLOT4_DN (54) CLK_100M_SLOT5_DP (55) CLK_100M_SLOT5_DN (55) CLK_100M_IOH_PE0CLK_DP (50) CLK_100M_IOH_PE0CLK_DN (50) CLK_100M_IOH_PE1CLK_DP (50) CLK_100M_IOH_PE1CLK_DN (50) CLK_100M_NIC_DP (61) CLK_100M_NIC_DN (61)

2

+3.3V +3.3V_DB800

FB17 600Ohm_0805FB17 600Ohm_0805

C928

C928 10u_1206

10u_1206

+3.3VDUAL +3.3VSB_MNG

FB15 600Ohm_0805FB15 600Ohm_0805

C773

C765

C421uC42 1u

C779

C779 10u_1206

10u_1206

C765

0.1u_0402

C778

0.1u_0402

C7801uC780 1u

+3.3VSB_MNG

R38

2.2

C43

0.01u_0402

+3.3VSB_MNG_IOH +3.3VSB_MNG

C917

C915

0.1u_0402

+3.3V_DB800 +3.3V_DB800_A

R410

2.2

C235

C235 10u_1206

10u_1206

R96

2.2

C55

0.01u_0402

C914

0.1u_0402

1

C916

0.1u_0402

C231

0.1u_0402

+3.3VSB_MNG_RMII

C591uC59 1u

C918

+3.3V

R520R52 0

+3.3VSB_MNG

R116

4.7K_0402

B B

C74

0.1u_0402

FB10 X_600Ohm_0805FB10 X_600Ohm_0805

+3.3VDUAL

R123

R123 1K_1%_0402

1K_1%_0402

C75

0.1u_0402

C50

0.01u_0402

C49

C49 27p_0402

27p_0402

25MHzY125MHz

R99 0R99 0

Y1

C461uC46 1u

SMB_CK_MNG_3V3SB_CLK SMB_CK_MNG_3V3SB_DAT

C48

C48 27p_0402

27p_0402

+3.3VSB_MNG_RMII+3.3VSB_MNG+3.3VSB_MNG_IOH

U10

34

VDD_50<1>

26

VDD_50<0>

2

VDD_96

9

VDD_133

23

VDD_33

15

VDD_REF

12

VDD_32K

38

SCL

39

SDA

30

OE_50B

31

OE_50A

5

OE_96

6

OE_133

19

XTAL_IN

20

XTAL_OUT

40

VTT_PWRGD_PWRDWN_N

22

33P33MHZ_SMBADR

R98

R98 1K_1%_0402

1K_1%_0402

32P768KHZ

25MHZ<1> 25MHZ<0>

50MHZ<7> 50MHZ<6> 50MHZ<5> 50MHZ<4> 50MHZ<3> 50MHZ<2> 50MHZ<1> 50MHZ<0>

DOT_96_P DOT_96_N

CPU_133_P CPU_133_N

IREF

GND_50<1> GND_50<0>

GND_133

GND<2> GND<1> GND<0>

VSSREF

GND_32K

CK_MNG_133

13 17

CLK_25M_R_PLD

16 24

25

ETH_TXCLK_R

28

ETH_RXCLK_R

29

CLK_50M_R_NIC

32 33 36 37

3 4

CLK_133M_IOH_ME_R_DP

7

CLK_133M_IOH_ME_R_DN

8 11 35

27 10 41 21 1

18 14

R65

R65 475_1%_0402

475_1%_0402

R64 33_0402R64 33_0402

R97 22_0402R97 22_0402 R106 22_0402R106 22_0402 R117 22_0402R117 22_0402 R118 22_0402R118 22_0402 R119 22_0402R119 22_0402 R120 22_0402R120 22_0402

R70 X_33_0402R70 X_33_0402 R69 X_33_0402R69 X_33_0402

Ball Pin

IOH N27

CLK_25M_PLD

ETH_TXCLK ETH_RXCLK CLK_50M_NIC CLK_50M_IBMCACLK_50M_R_IBMCA CLK_50M_ETH_REFCLK_50M_ETH_R_REF CLK_50M_PHY_REFCLK_50M_PHY_R_REF

R71

49.9_1%_0402

Pin name

ME_CLK_SRC

CLK_IOH_ME_DP CLK_IOH_ME_DN

R72

49.9_1%_0402

CLK_25M_PLD (72)

ETH_TXCLK (66) ETH_RXCLK (66) CLK_50M_NIC (61) CLK_50M_IBMCA (64) CLK_50M_ETH_REF (63) CLK_50M_PHY_REF (66)

CLK_IOH_ME_DP (49) CLK_IOH_ME_DN (49)

CLK_25M_PLD ETH_TXCLK ETH_RXCLK CLK_50M_NIC CLK_50M_IBMCA CLK_50M_ETH_REF CLK_50M_PHY_REF

EMI

CI1 10p_0402CI1 10p_0402 CI2 10p_0402CI2 10p_0402 CI3 10p_0402CI3 10p_0402 CI5 10p_0402CI5 10p_0402 CI6 10p_0402CI6 10p_0402 CI7 10p_0402CI7 10p_0402 CI8 10p_0402CI8 10p_0402

Definition

Used for ME default clock source:"1": PLL - clock from external source (default) "0" Ring Oscillator (back-up) - clock from internal source.

So CLK_IOH_ME_DP/N is unused

+3.3VDUAL

R1014

R1013

X_1K_0402

A A

5

4

SMB_CK_MNG_3V3SB_CLK SMB_CK_MNG_3V3SB_DAT

3

R121 0R121 0 R122 0R122 0

SMB_HOST_3V3SB_CLK (49,57,64,77) SMB_HOST_3V3SB_DAT (49,57,64,77)

2

MICRO-STAR INT'L CO.,LTD

MS-9197

MSI

Size Document Description Rev

C

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

MS-9197

026_CLK_BUFFER_&_CK-MNG_GEN

1

Sheet of

26 78

0A

5

CSI_CPU0_CPU1_CLK_DP(31) CSI_CPU0_CPU1_CLK_DN(31) CSI_CPU1_CPU0_CLK_DP(31) CSI_CPU1_CPU0_CLK_DN(31) CSI_CPU0_CMP0(29)

D D

C C

B B

CSI_CPU0_CPU1_CLK_DP CSI_CPU0_CPU1_CLK_DN CSI_CPU1_CPU0_CLK_DP CSI_CPU1_CPU0_CLK_DN CSI_CPU0_CMP0

CSI_CPU0_CPU1_DP19(31) CSI_CPU0_CPU1_DP18(31) CSI_CPU0_CPU1_DP17(31) CSI_CPU0_CPU1_DP16(31) CSI_CPU0_CPU1_DP15(31) CSI_CPU0_CPU1_DP14(31) CSI_CPU0_CPU1_DP13(31) CSI_CPU0_CPU1_DP12(31) CSI_CPU0_CPU1_DP11(31) CSI_CPU0_CPU1_DP10(31) CSI_CPU0_CPU1_DP9(31) CSI_CPU0_CPU1_DP8(31) CSI_CPU0_CPU1_DP7(31) CSI_CPU0_CPU1_DP6(31) CSI_CPU0_CPU1_DP5(31) CSI_CPU0_CPU1_DP4(31) CSI_CPU0_CPU1_DP3(31) CSI_CPU0_CPU1_DP2(31) CSI_CPU0_CPU1_DP1(31) CSI_CPU0_CPU1_DP0(31)

CSI_CPU0_CPU1_DN19(31) CSI_CPU0_CPU1_DN18(31) CSI_CPU0_CPU1_DN17(31) CSI_CPU0_CPU1_DN16(31) CSI_CPU0_CPU1_DN15(31) CSI_CPU0_CPU1_DN14(31) CSI_CPU0_CPU1_DN13(31) CSI_CPU0_CPU1_DN12(31) CSI_CPU0_CPU1_DN11(31) CSI_CPU0_CPU1_DN10(31) CSI_CPU0_CPU1_DN9(31) CSI_CPU0_CPU1_DN8(31) CSI_CPU0_CPU1_DN7(31) CSI_CPU0_CPU1_DN6(31) CSI_CPU0_CPU1_DN5(31) CSI_CPU0_CPU1_DN4(31) CSI_CPU0_CPU1_DN3(31) CSI_CPU0_CPU1_DN2(31) CSI_CPU0_CPU1_DN1(31) CSI_CPU0_CPU1_DN0(31)

CSI_CPU1_CPU0_DP19(31) CSI_CPU1_CPU0_DP18(31) CSI_CPU1_CPU0_DP17(31) CSI_CPU1_CPU0_DP16(31) CSI_CPU1_CPU0_DP15(31) CSI_CPU1_CPU0_DP14(31) CSI_CPU1_CPU0_DP13(31) CSI_CPU1_CPU0_DP12(31) CSI_CPU1_CPU0_DP11(31) CSI_CPU1_CPU0_DP10(31) CSI_CPU1_CPU0_DP9(31) CSI_CPU1_CPU0_DP8(31) CSI_CPU1_CPU0_DP7(31) CSI_CPU1_CPU0_DP6(31) CSI_CPU1_CPU0_DP5(31) CSI_CPU1_CPU0_DP4(31) CSI_CPU1_CPU0_DP3(31) CSI_CPU1_CPU0_DP2(31) CSI_CPU1_CPU0_DP1(31) CSI_CPU1_CPU0_DP0(31)

CSI_CPU1_CPU0_DN19(31) CSI_CPU1_CPU0_DN18(31) CSI_CPU1_CPU0_DN17(31) CSI_CPU1_CPU0_DN16(31) CSI_CPU1_CPU0_DN15(31) CSI_CPU1_CPU0_DN14(31) CSI_CPU1_CPU0_DN13(31) CSI_CPU1_CPU0_DN12(31) CSI_CPU1_CPU0_DN11(31) CSI_CPU1_CPU0_DN10(31) CSI_CPU1_CPU0_DN9(31) CSI_CPU1_CPU0_DN8(31) CSI_CPU1_CPU0_DN7(31) CSI_CPU1_CPU0_DN6(31) CSI_CPU1_CPU0_DN5(31) CSI_CPU1_CPU0_DN4(31) CSI_CPU1_CPU0_DN3(31) CSI_CPU1_CPU0_DN2(31) CSI_CPU1_CPU0_DN1(31) CSI_CPU1_CPU0_DN0(31)

CSI_CPU0_CPU1_DP19 CSI_CPU0_CPU1_DP18 CSI_CPU0_CPU1_DP17 CSI_CPU0_CPU1_DP16 CSI_CPU0_CPU1_DP15 CSI_CPU0_CPU1_DP14 CSI_CPU0_CPU1_DP13 CSI_CPU0_CPU1_DP12 CSI_CPU0_CPU1_DP11 CSI_CPU0_CPU1_DP10 CSI_CPU0_CPU1_DP9 CSI_CPU0_CPU1_DP8 CSI_CPU0_CPU1_DP7 CSI_CPU0_CPU1_DP6 CSI_CPU0_CPU1_DP5 CSI_CPU0_CPU1_DP4 CSI_CPU0_CPU1_DP3 CSI_CPU0_CPU1_DP2 CSI_CPU0_CPU1_DP1 CSI_CPU0_CPU1_DP0

CSI_CPU0_CPU1_DN19 CSI_CPU0_CPU1_DN18 CSI_CPU0_CPU1_DN17 CSI_CPU0_CPU1_DN16 CSI_CPU0_CPU1_DN15 CSI_CPU0_CPU1_DN14 CSI_CPU0_CPU1_DN13 CSI_CPU0_CPU1_DN12 CSI_CPU0_CPU1_DN11 CSI_CPU0_CPU1_DN10 CSI_CPU0_CPU1_DN9 CSI_CPU0_CPU1_DN8 CSI_CPU0_CPU1_DN7 CSI_CPU0_CPU1_DN6 CSI_CPU0_CPU1_DN5 CSI_CPU0_CPU1_DN4 CSI_CPU0_CPU1_DN3 CSI_CPU0_CPU1_DN2 CSI_CPU0_CPU1_DN1 CSI_CPU0_CPU1_DN0

CSI_CPU1_CPU0_DP19 CSI_CPU1_CPU0_DP18 CSI_CPU1_CPU0_DP17 CSI_CPU1_CPU0_DP16 CSI_CPU1_CPU0_DP15 CSI_CPU1_CPU0_DP14 CSI_CPU1_CPU0_DP13 CSI_CPU1_CPU0_DP12 CSI_CPU1_CPU0_DP11 CSI_CPU1_CPU0_DP10 CSI_CPU1_CPU0_DP9 CSI_CPU1_CPU0_DP8 CSI_CPU1_CPU0_DP7 CSI_CPU1_CPU0_DP6 CSI_CPU1_CPU0_DP5 CSI_CPU1_CPU0_DP4 CSI_CPU1_CPU0_DP3 CSI_CPU1_CPU0_DP2 CSI_CPU1_CPU0_DP1 CSI_CPU1_CPU0_DP0

CSI_CPU1_CPU0_DN19 CSI_CPU1_CPU0_DN18 CSI_CPU1_CPU0_DN17 CSI_CPU1_CPU0_DN16 CSI_CPU1_CPU0_DN15 CSI_CPU1_CPU0_DN14 CSI_CPU1_CPU0_DN13 CSI_CPU1_CPU0_DN12 CSI_CPU1_CPU0_DN11 CSI_CPU1_CPU0_DN10 CSI_CPU1_CPU0_DN9 CSI_CPU1_CPU0_DN8 CSI_CPU1_CPU0_DN7 CSI_CPU1_CPU0_DN6 CSI_CPU1_CPU0_DN5 CSI_CPU1_CPU0_DN4 CSI_CPU1_CPU0_DN3 CSI_CPU1_CPU0_DN2 CSI_CPU1_CPU0_DN1 CSI_CPU1_CPU0_DN0

AG42

AF42 AR41 AR42

AL43 AE40

AD38 AB39 AC39 AC41 AD40 AC43 AD42 AE42

AF43 AG40

AJ43 AK42 AH41 AK40 AH40

AJ38 AK37

AF39 AG38

AF40 AE38 AB38 AC38 AC40 AD39 AB43 AC42 AE41 AE43 AG41 AH43

AJ42 AH42 AK41

AJ40

AJ39 AK38 AG39 AH38

AP38 AN39 AP41 AM42 AN40 AN43 AP42 AT40 AT43 AU42 AU40 AW40 AU39 BA38 AW37 BA36 AW36 AV36 AU38 AT37

AR38 AP39 AP40 AM41 AM40 AM43 AN42 AR40 AR43 AT42 AU41 AV40 AT39 AY38 AW38 BA37 AY36 AV37 AV38 AU37

CSI0_CLKTX_DP CSI0_CLKTX_DN CSI0_CLKRX_DP CSI0_CLKRX_DN CSI0_COMP

CSI0_DTX_DP<19> CSI0_DTX_DP<18> CSI0_DTX_DP<17> CSI0_DTX_DP<16> CSI0_DTX_DP<15> CSI0_DTX_DP<14> CSI0_DTX_DP<13> CSI0_DTX_DP<12> CSI0_DTX_DP<11> CSI0_DTX_DP<10> CSI0_DTX_DP<9> CSI0_DTX_DP<8> CSI0_DTX_DP<7> CSI0_DTX_DP<6> CSI0_DTX_DP<5> CSI0_DTX_DP<4> CSI0_DTX_DP<3> CSI0_DTX_DP<2> CSI0_DTX_DP<1> CSI0_DTX_DP<0>

CSI0_DTX_DN<19> CSI0_DTX_DN<18> CSI0_DTX_DN<17> CSI0_DTX_DN<16> CSI0_DTX_DN<15> CSI0_DTX_DN<14> CSI0_DTX_DN<13> CSI0_DTX_DN<12> CSI0_DTX_DN<11> CSI0_DTX_DN<10> CSI0_DTX_DN<9> CSI0_DTX_DN<8> CSI0_DTX_DN<7> CSI0_DTX_DN<6> CSI0_DTX_DN<5> CSI0_DTX_DN<4> CSI0_DTX_DN<3> CSI0_DTX_DN<2> CSI0_DTX_DN<1> CSI0_DTX_DN<0>

CSI0_DRX_DP<19> CSI0_DRX_DP<18> CSI0_DRX_DP<17> CSI0_DRX_DP<16> CSI0_DRX_DP<15> CSI0_DRX_DP<14> CSI0_DRX_DP<13> CSI0_DRX_DP<12> CSI0_DRX_DP<11> CSI0_DRX_DP<10> CSI0_DRX_DP<9> CSI0_DRX_DP<8> CSI0_DRX_DP<7> CSI0_DRX_DP<6> CSI0_DRX_DP<5> CSI0_DRX_DP<4> CSI0_DRX_DP<3> CSI0_DRX_DP<2> CSI0_DRX_DP<1> CSI0_DRX_DP<0>

CSI0_DRX_DN<19> CSI0_DRX_DN<18> CSI0_DRX_DN<17> CSI0_DRX_DN<16> CSI0_DRX_DN<15> CSI0_DRX_DN<14> CSI0_DRX_DN<13> CSI0_DRX_DN<12> CSI0_DRX_DN<11> CSI0_DRX_DN<10> CSI0_DRX_DN<9> CSI0_DRX_DN<8> CSI0_DRX_DN<7> CSI0_DRX_DN<6> CSI0_DRX_DN<5> CSI0_DRX_DN<4> CSI0_DRX_DN<3> CSI0_DRX_DN<2> CSI0_DRX_DN<1> CSI0_DRX_DN<0>

4

U63A

Gainstown

1/10

Gainstown

CSI1_CLKTX_DP

CSI1_CLKTX_DN

CS1_CLKRX_DP

CSI1_CLKRX_DN

CSI1_COMP

CSI1_DTX_DP<19> CSI1_DTX_DP<18> CSI1_DTX_DP<17> CSI1_DTX_DP<16> CSI1_DTX_DP<15> CSI1_DTX_DP<14> CSI1_DTX_DP<13> CSI1_DTX_DP<12> CSI1_DTX_DP<11> CSI1_DTX_DP<10>

CSI1_DTX_DP<9> CSI1_DTX_DP<8> CSI1_DTX_DP<7> CSI1_DTX_DP<6> CSI1_DTX_DP<5> CSI1_DTX_DP<4> CSI1_DTX_DP<3> CSI1_DTX_DP<2> CSI1_DTX_DP<1> CSI1_DTX_DP<0>

CSI1_DTX_DN<19> CSI1_DTX_DN<18> CSI1_DTX_DN<17> CSI1_DTX_DN<16> CSI1_DTX_DN<15> CSI1_DTX_DN<14> CSI1_DTX_DN<13> CSI1_DTX_DN<12> CSI1_DTX_DN<11> CSI1_DTX_DN<10>

CSI1_DTX_DN<9> CSI1_DTX_DN<8> CSI1_DTX_DN<7> CSI1_DTX_DN<6> CSI1_DTX_DN<5> CSI1_DTX_DN<4> CSI1_DTX_DN<3> CSI1_DTX_DN<2> CSI1_DTX_DN<1> CSI1_DTX_DN<0>

CSI1_DRX_DP<19> CSI1_DRX_DP<18> CSI1_DRX_DP<17> CSI1_DRX_DP<16> CSI1_DRX_DP<15> CSI1_DRX_DP<14> CSI1_DRX_DP<13> CSI1_DRX_DP<12> CSI1_DRX_DP<11> CSI1_DRX_DP<10>

CSI1_DRX_DP<9> CSI1_DRX_DP<8> CSI1_DRX_DP<7> CSI1_DRX_DP<6> CSI1_DRX_DP<5> CSI1_DRX_DP<4> CSI1_DRX_DP<3> CSI1_DRX_DP<2> CSI1_DRX_DP<1> CSI1_DRX_DP<0>

CS1_DRX_DN<19> CSI1_DRX_DN<18> CSI1_DRX_DN<17> CSI1_DRX_DN<16> CSI1_DRX_DN<15> CSI1_DRX_DN<14> CSI1_DRX_DN<13> CSI1_DRX_DN<12> CSI1_DRX_DN<11> CSI1_DRX_DN<10>

CSI1_DRX_DN<9> CSI1_DRX_DN<8> CSI1_DRX_DN<7> CSI1_DRX_DN<6> CSI1_DRX_DN<5> CSI1_DRX_DN<4> CSI1_DRX_DN<3> CSI1_DRX_DN<2> CSI1_DRX_DN<1> CSI1_DRX_DN<0>

CSI_CPU0_IOH_CLK_DP

AF6

CSI_CPU0_IOH_CLK_DN

AE6

CSI_IOH_CPU0_CLK_DP

AT6

CSI_IOH_CPU0_CLK_DN

AR6

CSI_CPU0_CMP1

AL6

CSI_CPU0_IOH_DP19

AC8

CSI_CPU0_IOH_DP18

AD5

CSI_CPU0_IOH_DN17

AD6

CSI_CPU0_IOH_DN16

AB6

CSI_CPU0_IOH_DP15

AC4

CSI_CPU0_IOH_DP14

AE3

CSI_CPU0_IOH_DP13

AC3

CSI_CPU0_IOH_DP12

AD2

CSI_CPU0_IOH_DP11

AE1

CSI_CPU0_IOH_DP10

AF2

CSI_CPU0_IOH_DP9

AH2

CSI_CPU0_IOH_DP8

AH3

CSI_CPU0_IOH_DP7

AK1

CSI_CPU0_IOH_DP6

AJ3

CSI_CPU0_IOH_DP5

AG7

CSI_CPU0_IOH_DP4

AJ4

CSI_CPU0_IOH_DP3

AK6

CSI_CPU0_IOH_DP2

AH6

CSI_CPU0_IOH_DP1

AJ8

CSI_CPU0_IOH_DP0

AG8

CSI_CPU0_IOH_DN19

AD8

CSI_CPU0_IOH_DN18

AE5

CSI_CPU0_IOH_DP17

AD7

CSI_CPU0_IOH_DP16

AC6

CSI_CPU0_IOH_DN15

AD4

CSI_CPU0_IOH_DN14

AE4

CSI_CPU0_IOH_DN13

AB3

CSI_CPU0_IOH_DN12

AD3

CSI_CPU0_IOH_DN11

AD1

CSI_CPU0_IOH_DN10

AF3

CSI_CPU0_IOH_DN9

AG2

CSI_CPU0_IOH_DN8

AH4

CSI_CPU0_IOH_DN7

AJ1

CSI_CPU0_IOH_DN6

AJ2

CSI_CPU0_IOH_DN5

AG6

CSI_CPU0_IOH_DN4

AK4

CSI_CPU0_IOH_DN3

AK5

CSI_CPU0_IOH_DN2

AJ6

CSI_CPU0_IOH_DN1

AJ7

CSI_CPU0_IOH_DN0

AH8

CSI_IOH_CPU0_DP0

AM8

CSI_IOH_CPU0_DN1

AM6

CSI_IOH_CPU0_DP2

AN5

CSI_IOH_CPU0_DN3

AM4

CSI_IOH_CPU0_DP4

AP3

CSI_IOH_CPU0_DP5

AM2

CSI_IOH_CPU0_DP6

AN1

CSI_IOH_CPU0_DP7

AP2

CSI_IOH_CPU0_DP8

AR4

CSI_IOH_CPU0_DP9

AT1

CSI_IOH_CPU0_DP10

AT3

CSI_IOH_CPU0_DP11

AU4

CSI_IOH_CPU0_DP12

AW4

CSI_IOH_CPU0_DP13

AU7

CSI_IOH_CPU0_DP14

AY6

CSI_IOH_CPU0_DP15

BA7

CSI_IOH_CPU0_DP16

AV5

CSI_IOH_CPU0_DP17

AY8

CSI_IOH_CPU0_DP18

AV7

CSI_IOH_CPU0_DP19

AU8

CSI_IOH_CPU0_DN0

AL8

CSI_IOH_CPU0_DP1

AM7

CSI_IOH_CPU0_DN2

AN6

CSI_IOH_CPU0_DP3

AN4

CSI_IOH_CPU0_DN4

AP4

CSI_IOH_CPU0_DN5

AM3

CSI_IOH_CPU0_DN6

AM1

CSI_IOH_CPU0_DN7

AN2

CSI_IOH_CPU0_DN8

AR5

CSI_IOH_CPU0_DN9

AR1

CSI_IOH_CPU0_DN10

AT2

CSI_IOH_CPU0_DN11

AU3

CSI_IOH_CPU0_DN12

AW3

CSI_IOH_CPU0_DN13

AU6

CSI_IOH_CPU0_DN14

AY5

CSI_IOH_CPU0_DN15

BA6

CSI_IOH_CPU0_DN16

AW5

CSI_IOH_CPU0_DN17

BA8

CSI_IOH_CPU0_DN18

AW7

CSI_IOH_CPU0_DN19

AV8

3

CSI_CPU0_IOH_CLK_DP (48) CSI_CPU0_IOH_CLK_DN (48) CSI_IOH_CPU0_CLK_DP (48) CSI_IOH_CPU0_CLK_DN (48)

CSI_CPU0_CMP1 (29)

CSI_CPU0_IOH_DP19 (48) CSI_CPU0_IOH_DP18 (48) CSI_CPU0_IOH_DN17 (48) CSI_CPU0_IOH_DN16 (48) CSI_CPU0_IOH_DP15 (48) CSI_CPU0_IOH_DP14 (48) CSI_CPU0_IOH_DP13 (48) CSI_CPU0_IOH_DP12 (48) CSI_CPU0_IOH_DP11 (48) CSI_CPU0_IOH_DP10 (48) CSI_CPU0_IOH_DP9 (48) CSI_CPU0_IOH_DP8 (48) CSI_CPU0_IOH_DP7 (48) CSI_CPU0_IOH_DP6 (48) CSI_CPU0_IOH_DP5 (48) CSI_CPU0_IOH_DP4 (48) CSI_CPU0_IOH_DP3 (48) CSI_CPU0_IOH_DP2 (48) CSI_CPU0_IOH_DP1 (48) CSI_CPU0_IOH_DP0 (48)

CSI_CPU0_IOH_DN19 (48) CSI_CPU0_IOH_DN18 (48) CSI_CPU0_IOH_DP17 (48) CSI_CPU0_IOH_DP16 (48) CSI_CPU0_IOH_DN15 (48) CSI_CPU0_IOH_DN14 (48) CSI_CPU0_IOH_DN13 (48) CSI_CPU0_IOH_DN12 (48) CSI_CPU0_IOH_DN11 (48) CSI_CPU0_IOH_DN10 (48) CSI_CPU0_IOH_DN9 (48) CSI_CPU0_IOH_DN8 (48) CSI_CPU0_IOH_DN7 (48) CSI_CPU0_IOH_DN6 (48) CSI_CPU0_IOH_DN5 (48) CSI_CPU0_IOH_DN4 (48) CSI_CPU0_IOH_DN3 (48) CSI_CPU0_IOH_DN2 (48) CSI_CPU0_IOH_DN1 (48) CSI_CPU0_IOH_DN0 (48)

CSI_IOH_CPU0_DP0 (48)

CSI_IOH_CPU0_DN1 (48)

CSI_IOH_CPU0_DP2 (48)

CSI_IOH_CPU0_DN3 (48)

CSI_IOH_CPU0_DP4 (48)

CSI_IOH_CPU0_DP5 (48)

CSI_IOH_CPU0_DP6 (48)

CSI_IOH_CPU0_DP7 (48)

CSI_IOH_CPU0_DP8 (48)

CSI_IOH_CPU0_DP9 (48)

CSI_IOH_CPU0_DP10 (48)

CSI_IOH_CPU0_DP11 (48)

CSI_IOH_CPU0_DP12 (48)

CSI_IOH_CPU0_DP13 (48)

CSI_IOH_CPU0_DP14 (48)

CSI_IOH_CPU0_DP15 (48)

CSI_IOH_CPU0_DP16 (48)

CSI_IOH_CPU0_DP17 (48)

CSI_IOH_CPU0_DP18 (48)

CSI_IOH_CPU0_DP19 (48)

CSI_IOH_CPU0_DN0 (48)

CSI_IOH_CPU0_DP1 (48)

CSI_IOH_CPU0_DN2 (48)

CSI_IOH_CPU0_DP3 (48)

CSI_IOH_CPU0_DN4 (48)

CSI_IOH_CPU0_DN5 (48)

CSI_IOH_CPU0_DN6 (48)

CSI_IOH_CPU0_DN7 (48)

CSI_IOH_CPU0_DN8 (48)

CSI_IOH_CPU0_DN9 (48)

CSI_IOH_CPU0_DN10 (48)

CSI_IOH_CPU0_DN11 (48)

CSI_IOH_CPU0_DN12 (48)

CSI_IOH_CPU0_DN13 (48)

CSI_IOH_CPU0_DN14 (48)

CSI_IOH_CPU0_DN15 (48)

CSI_IOH_CPU0_DN16 (48)

CSI_IOH_CPU0_DN17 (48)

CSI_IOH_CPU0_DN18 (48)

CSI_IOH_CPU0_DN19 (48)

2

U63B

M_A_DQ[63..0](36,37)

M_A_ECC[7..0](36,37)

M_A_MA_PAR(36,37)

M_A_PAR_ERR_N1(37) M_A_PAR_ERR_N0(36)

M_A_ODT[3..0](36,37)

M_A_DQ63 M_A_DQ62 M_A_DQ61 M_A_DQ60 M_A_DQ59 M_A_DQ58 M_A_DQ57 M_A_DQ56 M_A_DQ55 M_A_DQ54 M_A_DQ53 M_A_DQ52 M_A_DQ51 M_A_DQ50 M_A_DQ49 M_A_DQ48 M_A_DQ47 M_A_DQ46 M_A_DQ45 M_A_DQ44 M_A_DQ43 M_A_DQ42 M_A_DQ41 M_A_DQ40 M_A_DQ39 M_A_DQ38 M_A_DQ37 M_A_DQ36 M_A_DQ35 M_A_DQ34 M_A_DQ33 M_A_DQ32 M_A_DQ31 M_A_DQ30 M_A_DQ29 M_A_DQ28 M_A_DQ27 M_A_DQ26 M_A_DQ25 M_A_DQ24 M_A_DQ23 M_A_DQ22 M_A_DQ21 M_A_DQ20 M_A_DQ19 M_A_DQ18 M_A_DQ17 M_A_DQ16 M_A_DQ15 M_A_DQ14 M_A_DQ13 M_A_DQ12 M_A_DQ11 M_A_DQ10 M_A_DQ9 M_A_DQ8 M_A_DQ7 M_A_DQ6 M_A_DQ5 M_A_DQ4 M_A_DQ3 M_A_DQ2 M_A_DQ1 M_A_DQ0

M_A_ECC7 M_A_ECC6 M_A_ECC5 M_A_ECC4 M_A_ECC3 M_A_ECC2 M_A_ECC1 M_A_ECC0

M_A_MA_PAR

M_A_PAR_ERR_N1 M_A_PAR_ERR_N0

M_A_ODT3 M_A_ODT2 M_A_ODT1 M_A_ODT0

W4

V4 U3 U1

Y3

Y2

V1 U4

T3 R4 N3 M3

T2

T1 N2 N1

L2

L3 H3 G1 M1

L1 H1 H2

F2

F3 C6

B6 G3

F1 C4

B5

B38 C38 D42 D41 D37

A38 C41 D40

F42

F43

J41

J42

E43

E42 H43 H41

L42

L43

P41

P42

K43

K42 N43 N41

T42 U41

W42 W40

R42 R43

V41

W41

C34

B34

A37 C37 C33

F32

A36 C36

B20

A27

B28 D25

C7

B11

C9

F12

Gainstown

DDR0_DQ<63> DDR0_DQ<62> DDR0_DQ<61> DDR0_DQ<60> DDR0_DQ<59> DDR0_DQ<58> DDR0_DQ<57> DDR0_DQ<56> DDR0_DQ<55> DDR0_DQ<54> DDR0_DQ<53> DDR0_DQ<52> DDR0_DQ<51> DDR0_DQ<50> DDR0_DQ<49> DDR0_DQ<48> DDR0_DQ<47> DDR0_DQ<46> DDR0_DQ<45> DDR0_DQ<44> DDR0_DQ<43> DDR0_DQ<42> DDR0_DQ<41> DDR0_DQ<40> DDR0_DQ<39> DDR0_DQ<38> DDR0_DQ<37> DDR0_DQ<36> DDR0_DQ<35> DDR0_DQ<34> DDR0_DQ<33> DDR0_DQ<32> DDR0_DQ<31> DDR0_DQ<30> DDR0_DQ<29> DDR0_DQ<28> DDR0_DQ<27> DDR0_DQ<26> DDR0_DQ<25> DDR0_DQ<24> DDR0_DQ<23> DDR0_DQ<22> DDR0_DQ<21> DDR0_DQ<20> DDR0_DQ<19> DDR0_DQ<18> DDR0_DQ<17> DDR0_DQ<16> DDR0_DQ<15> DDR0_DQ<14> DDR0_DQ<13> DDR0_DQ<12> DDR0_DQ<11> DDR0_DQ<10> DDR0_DQ<9> DDR0_DQ<8> DDR0_DQ<7> DDR0_DQ<6> DDR0_DQ<5> DDR0_DQ<4> DDR0_DQ<3> DDR0_DQ<2> DDR0_DQ<1> DDR0_DQ<0>

DDR0_ECC<7> DDR0_ECC<6> DDR0_ECC<5> DDR0_ECC<4> DDR0_ECC<3> DDR0_ECC<2> DDR0_ECC<1> DDR0_ECC<0>

DDR0_MA_PAR DDR0_PAR_ERR_N<2>

DDR0_PAR_ERR_N<1> DDR0_PAR_ERR_N<0>

DDR0_ODT<3> DDR0_ODT<2> DDR0_ODT<1> DDR0_ODT<0>

2/10

Gainstown

DDR0_DQS_P<17> DDR0_DQS_P<16> DDR0_DQS_P<15> DDR0_DQS_P<14> DDR0_DQS_P<13> DDR0_DQS_P<12> DDR0_DQS_P<11> DDR0_DQS_P<10>

DDR0_DQS_P<9> DDR0_DQS_P<8> DDR0_DQS_P<7> DDR0_DQS_P<6> DDR0_DQS_P<5> DDR0_DQS_P<4> DDR0_DQS_P<3> DDR0_DQS_P<2> DDR0_DQS_P<1> DDR0_DQS_P<0>

DDR0_DQS_N<17> DDR0_DQS_N<16> DDR0_DQS_N<15> DDR0_DQS_N<14> DDR0_DQS_N<13> DDR0_DQS_N<12> DDR0_DQS_N<11> DDR0_DQS_N<10>

DDR0_DQS_N<9> DDR0_DQS_N<8> DDR0_DQS_N<7> DDR0_DQS_N<6> DDR0_DQS_N<5> DDR0_DQS_N<4> DDR0_DQS_N<3> DDR0_DQS_N<2> DDR0_DQS_N<1> DDR0_DQS_N<0>

DDR0_MA<15> DDR0_MA<14> DDR0_MA<13> DDR0_MA<12> DDR0_MA<11> DDR0_MA<10>

DDR0_MA<9> DDR0_MA<8> DDR0_MA<7> DDR0_MA<6> DDR0_MA<5> DDR0_MA<4> DDR0_MA<3> DDR0_MA<2> DDR0_MA<1> DDR0_MA<0>

DDR0_BA<2> DDR0_BA<1> DDR0_BA<0>

DDR0_CLK_P<3> DDR0_CLK_P<2> DDR0_CLK_P<1> DDR0_CLK_P<0>

DDR0_CLK_N<3> DDR0_CLK_N<2> DDR0_CLK_N<1> DDR0_CLK_N<0>

DDR0_CS_N7_DDR_ODT<5> DDR0_CS_N6_DDR_ODT<4>

DDR0_CS_N<5> DDR0_CS_N<4> DDR0_CS_N<3> DDR0_CS_N<2> DDR0_CS_N<1> DDR0_CS_N<0>

DDR0_CKE<3> DDR0_CKE<2> DDR0_CKE<1> DDR0_CKE<0>

DDR0_WE_N DDR0_RAS_N DDR0_CAS_N

DDR0_RESET_N

B36 V2 P2 J2 D5 D39 H42 N42 V43 D34 W2 R2 K2 E3 B39 F41 L41 T43

B35 V3 P1 J1 D4 C39 G43 M43 V42 D35 W1 R3 K3 E4 B40 G41 M41 U43

B29 A28 A10 B26 A26 B19 C26 B25 A25 C24 B24 B23 D24 C23 B21 A20

C28 A16 B16

E20 F18 D19 J19

E19 E18 C19 K19

B8 C11 A7 B15 B9 C13 B10 G15

B31 B30 A30 C29

B13 A15 C12

D32

M_A_DQS_DP17 M_A_DQS_DP16 M_A_DQS_DP15 M_A_DQS_DP14 M_A_DQS_DP13 M_A_DQS_DP12 M_A_DQS_DP11 M_A_DQS_DP10 M_A_DQS_DP9 M_A_DQS_DP8 M_A_DQS_DP7 M_A_DQS_DP6 M_A_DQS_DP5 M_A_DQS_DP4 M_A_DQS_DP3 M_A_DQS_DP2 M_A_DQS_DP1 M_A_DQS_DP0

M_A_DQS_DN17 M_A_DQS_DN16 M_A_DQS_DN15 M_A_DQS_DN14 M_A_DQS_DN13 M_A_DQS_DN12 M_A_DQS_DN11 M_A_DQS_DN10 M_A_DQS_DN9 M_A_DQS_DN8 M_A_DQS_DN7 M_A_DQS_DN6 M_A_DQS_DN5 M_A_DQS_DN4 M_A_DQS_DN3 M_A_DQS_DN2 M_A_DQS_DN1 M_A_DQS_DN0

M_A_MA15 M_A_MA14 M_A_MA13 M_A_MA12 M_A_MA11 M_A_MA10 M_A_MA9 M_A_MA8 M_A_MA7 M_A_MA6 M_A_MA5 M_A_MA4 M_A_MA3 M_A_MA2 M_A_MA1 M_A_MA0

M_A_BA2 M_A_BA1 M_A_BA0

M_A_CK_DP3 M_A_CK_DP2

M_A_CK_DP1 M_A_CK_DP0

M_A_CK_DN3 M_A_CK_DN2

M_A_CK_DN1 M_A_CK_DN0

M_A_CS_N7 M_A_CS_N6 M_A_CS_N5 M_A_CS_N4 M_A_CS_N3 M_A_CS_N2 M_A_CS_N1 M_A_CS_N0

M_A_CKE3 M_A_CKE2 M_A_CKE1 M_A_CKE0

M_A_WE_N M_A_RAS_N M_A_CAS_N

M_A_RESET_N

1

M_A_DQS_DP[17..0] (36,37)

M_A_DQS_DN[17..0] (36,37)

M_A_MA[15..0] (36,37)

M_A_BA[2..0] (36,37)

M_A_CK_DP3 (37) M_A_CK_DP2 (36) M_A_CK_DP1 (37) M_A_CK_DP0 (36)

M_A_CK_DN3 (37) M_A_CK_DN2 (36) M_A_CK_DN1 (37) M_A_CK_DN0 (36) M_A_CS_N[7..0] (36,37)

M_A_CKE[3..0] (36,37)

M_A_WE_N (36,37) M_A_RAS_N (36,37) M_A_CAS_N (36,37)

M_A_RESET_N (36,37)

A A

MICRO-STAR INT'L CO.,LTD

MS-9197

MSI

Size Document Description Rev

C

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

Date:

5

4

3

2

Saturday, December 01, 2007

MS-9197

027_CPU0(1/4)

1

Sheet of

27 78

0A

5

Gainstown

M_B_DQ[63..0](38,39)

D D

C C

M_B_ECC[7..0](38,39) M_C_ECC[7..0](40,41)

M_B_MA_PAR(38,39)

M_B_PAR_ERR_N1(39) M_B_PAR_ERR_N0(38)

M_B_ODT[3..0](38,39)

B B

M_B_DQ63 M_B_DQ62 M_B_DQ61 M_B_DQ60 M_B_DQ59 M_B_DQ58 M_B_DQ57 M_B_DQ56 M_B_DQ55 M_B_DQ54 M_B_DQ53 M_B_DQ52 M_B_DQ51 M_B_DQ50 M_B_DQ49 M_B_DQ48 M_B_DQ47 M_B_DQ46 M_B_DQ45 M_B_DQ44 M_B_DQ43 M_B_DQ42 M_B_DQ41 M_B_DQ40 M_B_DQ39 M_B_DQ38 M_B_DQ37 M_B_DQ36 M_B_DQ35 M_B_DQ34 M_B_DQ33 M_B_DQ32 M_B_DQ31 M_B_DQ30 M_B_DQ29 M_B_DQ28 M_B_DQ27 M_B_DQ26 M_B_DQ25 M_B_DQ24 M_B_DQ23 M_B_DQ22 M_B_DQ21 M_B_DQ20 M_B_DQ19 M_B_DQ18 M_B_DQ17 M_B_DQ16 M_B_DQ15 M_B_DQ14 M_B_DQ13 M_B_DQ12 M_B_DQ11 M_B_DQ10 M_B_DQ9 M_B_DQ8 M_B_DQ7 M_B_DQ6 M_B_DQ5 M_B_DQ4 M_B_DQ3 M_B_DQ2 M_B_DQ1 M_B_DQ0

M_B_ECC7 M_B_ECC6 M_B_ECC5 M_B_ECC4 M_B_ECC3 M_B_ECC2 M_B_ECC1 M_B_ECC0

M_B_MA_PAR

M_B_PAR_ERR_N1 M_B_PAR_ERR_N0

M_B_ODT3 M_B_ODT2 M_B_ODT1 M_B_ODT0

AB36 AA35

AA36 AA37

W9

AA7

W5

V9

W10

Y10

W7 W6

R7 R8

M6

J4 T5 R5 K5 K4 J5

G5

H9

G9

H4

G4

J6 H8 F6 D6

G8

F10

F5 E5 E8

E9 K30 L32 H34

J34

J32 K32 L33 H33 H36

J36

M36

N34

J35 K35

M34 M35

N38 N37 R35 R34 N39 P39 P35 P34 Y39 Y40

Y34 Y35

G35 E34 F37 E37 G36 E33 F36 D36

D20 F25

E25 C22

F11 D14

C8

D11

Gainstown

DDR1_DQ<63> DDR1_DQ<62> DDR1_DQ<61> DDR1_DQ<60> DDR1_DQ<59> DDR1_DQ<58> DDR1_DQ<57> DDR1_DQ<56> DDR1_DQ<55> DDR1_DQ<54> DDR1_DQ<53> DDR1_DQ<52> DDR1_DQ<51> DDR1_DQ<50> DDR1_DQ<49> DDR1_DQ<48> DDR1_DQ<47> DDR1_DQ<46> DDR1_DQ<45> DDR1_DQ<44> DDR1_DQ<43> DDR1_DQ<42> DDR1_DQ<41> DDR1_DQ<40> DDR1_DQ<39> DDR1_DQ<38> DDR1_DQ<37> DDR1_DQ<36> DDR1_DQ<35> DDR1_DQ<34> DDR1_DQ<33> DDR1_DQ<32> DDR1_DQ<31> DDR1_DQ<30> DDR1_DQ<29> DDR1_DQ<28> DDR1_DQ<27> DDR1_DQ<26> DDR1_DQ<25> DDR1_DQ<24> DDR1_DQ<23> DDR1_DQ<22> DDR1_DQ<21> DDR1_DQ<20> DDR1_DQ<19> DDR1_DQ<18> DDR1_DQ<17> DDR1_DQ<16> DDR1_DQ<15> DDR1_DQ<14> DDR1_DQ<13> DDR1_DQ<12> DDR1_DQ<11> DDR1_DQ<10> DDR1_DQ<9> DDR1_DQ<8> DDR1_DQ<7> DDR1_DQ<6> DDR1_DQ<5> DDR1_DQ<4> DDR1_DQ<3> DDR1_DQ<2> DDR1_DQ<1> DDR1_DQ<0>

DDR1_ECC<7> DDR1_ECC<6> DDR1_ECC<5> DDR1_ECC<4> DDR1_ECC<3> DDR1_ECC<2> DDR1_ECC<1> DDR1_ECC<0>

DDR1_MA_PAR DDR1_PAR_ERR_N<2>

DDR1_PAR_ERR_N<1> DDR1_PAR_ERR_N<0>

DDR1_ODT<3> DDR1_ODT<2> DDR1_ODT<1> DDR1_ODT<0>

4

U63C

DDR1_CS_N7_DDR_ODT<5> DDR1_CS_N6_DDR_ODT<4>

3/10

Gainstown

DDR1_DQS_P<17> DDR1_DQS_P<16> DDR1_DQS_P<15> DDR1_DQS_P<14> DDR1_DQS_P<13> DDR1_DQS_P<12> DDR1_DQS_P<11> DDR1_DQS_P<10>

DDR1_DQS_P<9> DDR1_DQS_P<8> DDR1_DQS_P<7> DDR1_DQS_P<6> DDR1_DQS_P<5> DDR1_DQS_P<4> DDR1_DQS_P<3> DDR1_DQS_P<2> DDR1_DQS_P<1> DDR1_DQS_P<0>

DDR1_DQS_N<17> DDR1_DQS_N<16> DDR1_DQS_N<15> DDR1_DQS_N<14> DDR1_DQS_N<13> DDR1_DQS_N<12> DDR1_DQS_N<11> DDR1_DQS_N<10>

DDR1_DQS_N<9> DDR1_DQS_N<8> DDR1_DQS_N<7> DDR1_DQS_N<6> DDR1_DQS_N<5> DDR1_DQS_N<4> DDR1_DQS_N<3> DDR1_DQS_N<2> DDR1_DQS_N<1> DDR1_DQS_N<0>

DDR0_MA<15> DDR0_MA<14> DDR0_MA<13> DDR0_MA<12> DDR1_MA<11> DDR1_MA<10>

DDR1_MA<9> DDR1_MA<8> DDR1_MA<7> DDR1_MA<6> DDR1_MA<5> DDR1_MA<4> DDR1_MA<3> DDR1_MA<2> DDR1_MA<1> DDR1_MA<0>

DDR1_BA<2> DDR1_BA<1> DDR1_BA<0>

DDR1_CLK_P<3> DDR1_CLK_P<2> DDR1_CLK_P<1> DDR1_CLK_P<0>

DDR1_CLK_N<3> DDR1_CLK_N<2> DDR1_CLK_N<1> DDR1_CLK_N<0>

DDR1_CS_N<5> DDR1_CS_N<4> DDR1_CS_N<3> DDR1_CS_N<2> DDR1_CS_N<1> DDR1_CS_N<0>

DDR1_CKE<3> DDR1_CKE<2> DDR1_CKE<1> DDR1_CKE<0>

DDR1_WE_N DDR1_RAS_N DDR1_CAS_N

DDR1_RESET_N

F35 Y4 M5 H7 F8 K34 L37 P36 AA40 G33 Y8 L6 H6 E7 L30 L35 R38 Y38

E35 Y5 M4 J7 F7 K33 K37 P37 AA41 G34 Y9 L5 G6 D7 L31 L36 R37 Y37

F26 H26 B14 E24 E23 H14 G24 E22 D22 J27 F22 K28 L28 J17 J16 J14

H27 K13 C18

H18 K18 G19 C21

H19 L18 G20 D21

E12 C14 E10 C17 E13 E15 A8 D12

C27 D27 E27 H28

G13 G14 E14

D29

M_B_DQS_DP17 M_B_DQS_DP16 M_B_DQS_DP15 M_B_DQS_DP14 M_B_DQS_DP13 M_B_DQS_DP12 M_B_DQS_DP11 M_B_DQS_DP10 M_B_DQS_DP9 M_B_DQS_DP8 M_B_DQS_DP7 M_B_DQS_DP6 M_B_DQS_DP5 M_B_DQS_DP4 M_B_DQS_DP3 M_B_DQS_DP2 M_B_DQS_DP1 M_B_DQS_DP0

M_B_DQS_DN17 M_B_DQS_DN16 M_B_DQS_DN15 M_B_DQS_DN14 M_B_DQS_DN13 M_B_DQS_DN12 M_B_DQS_DN11 M_B_DQS_DN10 M_B_DQS_DN9 M_B_DQS_DN8 M_B_DQS_DN7 M_B_DQS_DN6 M_B_DQS_DN5 M_B_DQS_DN4 M_B_DQS_DN3 M_B_DQS_DN2 M_B_DQS_DN1 M_B_DQS_DN0

M_B_MA15 M_B_MA14 M_B_MA13 M_B_MA12 M_B_MA11 M_B_MA10 M_B_MA9 M_B_MA8 M_B_MA7 M_B_MA6 M_B_MA5 M_B_MA4 M_B_MA3 M_B_MA2 M_B_MA1 M_B_MA0

M_B_BA2 M_B_BA0

M_B_CK_DP3 M_B_CK_DP2 M_B_CK_DP1 M_B_CK_DP0

M_B_CK_DN3 M_B_CK_DN2 M_B_CK_DN1 M_B_CK_DN0

M_B_CS_N7 M_B_CS_N6 M_B_CS_N5 M_B_CS_N4 M_B_CS_N3 M_B_CS_N2 M_B_CS_N1 M_B_CS_N0

M_B_CKE3 M_B_CKE2 M_B_CKE1 M_B_CKE0

M_B_WE_N M_B_RAS_N M_B_CAS_N

M_B_RESET_N

3

M_B_DQS_DP[17..0] (38,39)

M_B_DQS_DN[17..0] (38,39)

M_B_MA[15..0] (38,39)

M_B_BA[2..0] (38,39)

M_B_CK_DP3 (39) M_B_CK_DP2 (38) M_B_CK_DP1 (39) M_B_CK_DP0 (38)

M_B_CK_DN3 (39) M_B_CK_DN2 (38) M_B_CK_DN1 (39) M_B_CK_DN0 (38) M_B_CS_N[7..0] (38,39)

M_B_CKE[3..0] (38,39)

M_B_WE_N (38,39) M_B_RAS_N (38,39) M_B_CAS_N (38,39)

M_B_RESET_N (38,39)

2

U63D

M_C_DQ[63..0](40,41)

M_C_MA_PAR(40,41)

M_C_PAR_ERR_N1(41) M_C_PAR_ERR_N0(40)

M_C_ODT[3..0](40,41)

M_C_DQ63 M_C_DQ62 M_C_DQ61 M_C_DQ60 M_C_DQ59 M_C_DQ58 M_C_DQ57 M_C_DQ56 M_C_DQ55 M_C_DQ54 M_C_DQ53 M_C_DQ52 M_C_DQ51 M_C_DQ50 M_C_DQ49 M_C_DQ48 M_C_DQ47 M_C_DQ46 M_C_DQ45 M_C_DQ44 M_C_DQ43 M_C_DQ42 M_C_DQ41 M_C_DQ40 M_C_DQ39 M_C_DQ38 M_C_DQ37 M_C_DQ36 M_C_DQ35 M_C_DQ34 M_C_DQ33 M_C_DQ32 M_C_DQ31 M_C_DQ30 M_C_DQ29 M_C_DQ28 M_C_DQ27 M_C_DQ26 M_C_DQ25 M_C_DQ24 M_C_DQ23 M_C_DQ22 M_C_DQ21 M_C_DQ20 M_C_DQ19 M_C_DQ18 M_C_DQ17 M_C_DQ16 M_C_DQ15 M_C_DQ14 M_C_DQ13

M_C_DQ11 M_C_DQ10 M_C_DQ9 M_C_DQ8 M_C_DQ7 M_C_DQ6 M_C_DQ5 M_C_DQ4 M_C_DQ3 M_C_DQ2 M_C_DQ1 M_C_DQ0

M_C_ECC7 M_C_ECC6 M_C_ECC5 M_C_ECC4 M_C_ECC3 M_C_ECC2 M_C_ECC1 M_C_ECC0

M_C_MA_PAR

M_C_PAR_ERR_N1 M_C_PAR_ERR_N0

M_C_ODT3 M_C_ODT2 M_C_ODT1 M_C_ODT0

U9 V8 T7

T6 U10 T10

U6

U5

R9 R10

N7

N8 P10

P9

N6

P7

M8

L8 M10 L11

N9

M9 K10 L10 L12 H12 G10 G11 L13 H13

J12 K12 E38 F38 G39 H39 H37

J37 F40 G40 K38 L40 N36 P40

J39

J40 M40 M39 R40 T41 V39

W39

T36 R39 U39 U38 V38 V37 V34 U34 U36 V36

W35 W34

F30 F31

J30

J31 E30 E29 F33 H32

B18 F23

J25 F21

D10 D15 F13 L16

Gainstown

DDR2_DQ<63> DDR2_DQ<62> DDR2_DQ<61> DDR2_DQ<60> DDR2_DQ<59> DDR2_DQ<58> DDR2_DQ<57> DDR2_DQ<56> DDR2_DQ<55> DDR2_DQ<54> DDR2_DQ<53> DDR2_DQ<52> DDR2_DQ<51> DDR2_DQ<50> DDR2_DQ<49> DDR2_DQ<48> DDR2_DQ<47> DDR2_DQ<46> DDR2_DQ<45> DDR2_DQ<44> DDR2_DQ<43> DDR2_DQ<42> DDR2_DQ<41> DDR2_DQ<40> DDR2_DQ<39> DDR2_DQ<38> DDR2_DQ<37> DDR2_DQ<36> DDR2_DQ<35> DDR2_DQ<34> DDR2_DQ<33> DDR2_DQ<32> DDR2_DQ<31> DDR2_DQ<30> DDR2_DQ<29> DDR2_DQ<28> DDR2_DQ<27> DDR2_DQ<26> DDR2_DQ<25> DDR2_DQ<24> DDR2_DQ<23> DDR2_DQ<22> DDR2_DQ<21> DDR2_DQ<20> DDR2_DQ<19> DDR2_DQ<18> DDR2_DQ<17> DDR2_DQ<16> DDR2_DQ<15> DDR2_DQ<14> DDR2_DQ<13> DDR2_DQ<12> DDR2_DQ<11> DDR2_DQ<10> DDR2_DQ<9> DDR2_DQ<8> DDR2_DQ<7> DDR2_DQ<6> DDR2_DQ<5> DDR2_DQ<4> DDR2_DQ<3> DDR2_DQ<2> DDR2_DQ<1> DDR2_DQ<0>

DDR2_ECC<7> DDR2_ECC<6> DDR2_ECC<5> DDR2_ECC<4> DDR2_ECC<3> DDR2_ECC<2> DDR2_ECC<1> DDR2_ECC<0>

DDR2_MA_PAR DDR2_PAR_ERR_N<2>

DDR2_PAR_ERR_N<1> DDR2_PAR_ERR_N<0>

DDR2_ODT<3> DDR2_ODT<2> DDR2_ODT<1> DDR2_ODT<0>

DDR2_CS_N7_DDR2_ODT<5> DDR2_CS_N6_DDR2_ODT<4>

4/10

Gainstown

DDR1_DQS_P<17> DDR1_DQS_P<16> DDR1_DQS_P<15> DDR1_DQS_P<14> DDR1_DQS_P<13> DDR1_DQS_P<12> DDR2_DQS_P<11> DDR2_DQS_P<10>

DDR2_DQS_P<9> DDR2_DQS_P<8> DDR2_DQS_P<7> DDR2_DQS_P<6> DDR2_DQS_P<5> DDR2_DQS_P<4> DDR2_DQS_P<3> DDR2_DQS_P<2> DDR2_DQS_P<1> DDR2_DQS_P<0>

DDR2_DQS_N<17> DDR2_DQS_N<16> DDR2_DQS_N<15> DDR2_DQS_N<14> DDR2_DQS_N<13> DDR2_DQS_N<12> DDR2_DQS_N<11> DDR2_DQS_N<10>

DDR2_DQS_N<9> DDR2_DQS_N<8> DDR2_DQS_N<7> DDR2_DQS_N<6> DDR2_DQS_N<5> DDR2_DQS_N<4> DDR2_DQS_N<3> DDR2_DQS_N<2> DDR2_DQS_N<1> DDR2_DQS_N<0>

DDR0_MA<15> DDR0_MA<14> DDR0_MA<13> DDR0_MA<12> DDR2_MA<11> DDR2_MA<10>

DDR2_MA<9> DDR2_MA<8> DDR2_MA<7> DDR2_MA<6> DDR2_MA<5> DDR2_MA<4> DDR2_MA<3> DDR2_MA<2> DDR2_MA<1> DDR2_MA<0>

DDR2_BA<2> DDR2_BA<1> DDR2_BA<0>

DDR2_CLK_P<3> DDR2_CLK_P<2> DDR2_CLK_P<1> DDR2_CLK_P<0>

DDR2_CLK_N<3> DDR2_CLK_N<2> DDR2_CLK_N<1> DDR2_CLK_N<0>

DDR2_CS_N<5> DDR2_CS_N<4> DDR2_CS_N<3> DDR2_CS_N<2> DDR2_CS_N<1> DDR2_CS_N<0>

DDR2_CKE<3> DDR2_CKE<2> DDR2_CKE<1> DDR2_CKE<0>

DDR2_WE_N DDR2_RAS_N DDR2_CAS_N

DDR2_RESET_N

H31 V6 N4 K9 H11 H38 M38 U40 U35 G29 U8 P6 L7 J10 E39 K40 T37 W37

G31 V7 P4 K8 J11 G38 L38 T40 T35 G30 T8 P5 K7 J9 E40 K39 T38 W36

G25 H24 F15 G23 H23 H17 H22 L25 J24 K22 K23 F20 J20 G18 K17 A18

L26 F17 A17

L22 H21 L20 J22

L21 G21 K20 J21

J15 L17 D9 E17 H16 D16 K14 G16

L27 D26 G26 J26

C16 D17 F16

E32

M_C_DQS_DP17 M_C_DQS_DP16 M_C_DQS_DP15 M_C_DQS_DP14 M_C_DQS_DP13 M_C_DQS_DP12 M_C_DQS_DP11 M_C_DQS_DP10 M_C_DQS_DP9 M_C_DQS_DP8 M_C_DQS_DP7 M_C_DQS_DP6 M_C_DQS_DP5 M_C_DQS_DP4 M_C_DQS_DP3 M_C_DQS_DP2 M_C_DQS_DP1 M_C_DQS_DP0

M_C_DQS_DN17 M_C_DQS_DN16 M_C_DQS_DN15 M_C_DQS_DN14 M_C_DQS_DN13 M_C_DQS_DN12 M_C_DQS_DN11 M_C_DQS_DN10 M_C_DQS_DN9 M_C_DQS_DN8 M_C_DQS_DN7 M_C_DQS_DN6 M_C_DQS_DN5 M_C_DQS_DN4 M_C_DQS_DN3 M_C_DQS_DN2 M_C_DQS_DN1 M_C_DQS_DN0

M_C_MA15 M_C_MA14 M_C_MA13 M_C_MA12 M_C_MA11 M_C_MA10 M_C_MA9 M_C_MA8 M_C_MA7 M_C_MA6 M_C_MA5 M_C_MA4 M_C_MA3 M_C_MA2M_C_DQ12 M_C_MA1 M_C_MA0

M_C_BA2 M_C_BA1M_B_BA1 M_C_BA0

M_C_CK_DP3 M_C_CK_DP2 M_C_CK_DP1 M_C_CK_DP0

M_C_CK_DN3 M_C_CK_DN2 M_C_CK_DN1 M_C_CK_DN0

M_C_CS_N7 M_C_CS_N6 M_C_CS_N5 M_C_CS_N4 M_C_CS_N3 M_C_CS_N2 M_C_CS_N1 M_C_CS_N0

M_C_CKE3 M_C_CKE2 M_C_CKE1 M_C_CKE0

M_C_WE_N M_C_RAS_N M_C_CAS_N

M_C_RESET_N

1

M_C_DQS_DP[17..0] (40,41)

M_C_DQS_DN[17..0] (40,41)

M_C_MA[15..0] (40,41)

M_C_BA[2..0] (40,41)

M_C_CK_DP3 (41) M_C_CK_DP2 (40) M_C_CK_DP1 (41) M_C_CK_DP0 (40)

M_C_CK_DN3 (41) M_C_CK_DN2 (40) M_C_CK_DN1 (41) M_C_CK_DN0 (40) M_C_CS_N[7..0] (40,41)

M_C_CKE[3..0] (40,41)

M_C_WE_N (40,41) M_C_RAS_N (40,41) M_C_CAS_N (40,41)

M_C_RESET_N (40,41)

A A

MICRO-STAR INT'L CO.,LTD

MS-9197

MSI

Size Document Description Rev

C

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

Date:

5

4

3

2

Saturday, December 01, 2007

MS-9197

028_CPU0(2/4)

1

Sheet of

28 78

0A

5

RST_CPU_RESET_N(33,49,74)

CSI_CATERR_N(33,35) CSI_CPU0_THERMTRIP_N(35)

D D

C C

B B

A A

CSI_CPU0_PRCHT_N(35,69) CSI_CPU0_SKTOCC_N(64,75,76)

IRQ_CPU0_RDIMM_EVENT_N(36,37,38,39,40,41)

PECI_CPU(33,67,70)

CLK_133M_CPU0_DP(25) CLK_133M_CPU0_DN(25)

CLK_133M_CPU0_ITP_DP(73) CLK_133M_CPU0_ITP_DN(73)

PWRGD_CPU_GTL(33,57,74)

PWRGD_CPU0_VDD_GTL(16,19)

VID_CPU0[7..0](23)

CPU0_VTT_VID(17) FM_CPU0_PSI_N(23)

VR_CPU0_IOUT(23)

VSENSE_DIE_CPU0_P(23) VSENSE_DIE_CPU0_N(23)

VSENSE_DIE_CPU0_VTT_P(17) VSENSE_DIE_CPU0_VTT_N(17)

XDP_CPU0_PRDY_N(74) XDP_CPU0_PREQ_N(74)

XDP_CPU0_MBP_N[7..0](73)

JTAG_CPU_TRST_N(33,74) JTAG_CPU_TCLK(33,74) JTAG_CPU_TMS(33,74) JTAG_CPU0_TDI(74) JTAG_CPU0_TDO(74)

5

RST_CPU_RESET_N CSI_CATERR_N CSI_CPU0_THERMTRIP_N CSI_CPU0_PRCHT_N CSI_CPU0_SKTOCC_N

CSI_CPU0_CMPSTH M_CPU0_DDR_COMP[2]

M_CPU0_DDR_COMP[1] M_CPU0_DDR_COMP[0]

PECI_CPU FM_PECI_CPU0_ID

CLK_133M_CPU0_DP CLK_133M_CPU0_DN CLK_133M_CPU0_ITP_DP CLK_133M_CPU0_ITP_DN

R801 0R801 0

PWRGD_CPU0_VDD_GTL PWRGD_CPU0_VTT_GTL

VID_CPU07 VID_CPU06 VID_CPU05 VID_CPU04 VID_CPU03 VID_CPU02 VID_CPU01

VID_CPU00 CPU0_VTT_VID FM_CPU0_PSI_N

P1V5_DDR3_VREF_CPU0 PV_VTT_VREF_CPU0

VR_CPU0_IOUT VSENSE_DIE_CPU0_P

VSENSE_DIE_CPU0_N VSENSE_DIE_CPU0_VTT_P

VSENSE_DIE_CPU0_VTT_N CPU_DBR_RST_N

XDP_CPU0_PRDY_N XDP_CPU0_PREQ_N

JTAG_CPU_TRST_N JTAG_CPU_TCLK JTAG_CPU_TMS JTAG_CPU0_TDI JTAG_CPU0_TDO

R802 X_0R802 X_0

RST_CPU_RESET_N CSI_CATERR_N

XDP_CPU0_MBP_N7 XDP_CPU0_MBP_N6 XDP_CPU0_MBP_N5 XDP_CPU0_MBP_N4 XDP_CPU0_MBP_N3 XDP_CPU0_MBP_N2 XDP_CPU0_MBP_N1 XDP_CPU0_MBP_N0

R812 X_49.9_1%_0402R812 X_49.9_1%_0402 R818 75_0402R818 75_0402

AL39 AC37 AG37 AG35 AG36

AB5

AB41

AC1

Y7

AA8

AH36 AK35

AJ35 AH35

AA5 AA4

AR7 AA6

AB35

AN8 AP8

AP9 AN10 AM10

AN9

AL9

AL10

AV6

AP7

L23

AJ37

AK8

AR9

AR8 AE36

AE37

AF10

B41

C42

E2 D2 C3 D1 B4 C2 A5 B3

AH9 AH10 AG10

AJ9

AJ10

RST_IBMC_SYS_RST_NCPU_DBR_RST_N

+1.1V_CPU0

4

RESET_N CAT_ERR_N THERMTRIP_N PROCHOT_N SKTOCC_N DDR_THERM_N COMP0

DDR_COMP<2> DDR_COMP<1> DDR_COMP<0>

PECI PECI_ID

BCLK_DP BCLK_DN BCLK_ITP_DP BCLK_ITP_DN

VCCPWRGOOD VDDPWRGOOD VTTPWRGOOD

VID<7> VID<6> VID5_CSC<2> VID4_CSC<1> VID3_CSC<0> VID2_MSID<2> VID1_MSID<1> VID0_MSID<0> VTT_VID PSI_N

DDR_VREF GTLREF

ISENSE VCC_SENSE

VSS_SENSE VTTD_SENSE

VSS_SENSE_VTTD DBR_N

PRDY_N PREQ_N

BPM_N<7> BPM_N<6> BPM_N<5> BPM_N<4> BPM_N<3> BPM_N<2> BPM_N<1> BPM_N<0>

TRST_N TCK TMS TDI TDO

RST_IBMC_SYS_RST_N (57,65,71)CPU_DBR_RST_N(33)

C556

0.1u_0402

4

U63E

Gainstown

5/10

Gainstown

FM_PECI_CPU0_ID

RSVD<66> RSVD<65> RSVD<64> RSVD<63> RSVD<62> RSVD<61> RSVD<60> RSVD<59> RSVD<58> RSVD<57> RSVD<56> RSVD<55> RSVD<54> RSVD<53> RSVD<52> RSVD<51> RSVD<50> RSVD<49> RSVD<48> RSVD<47> RSVD<46> RSVD<45> RSVD<44> RSVD<43> RSVD<42> RSVD<41> RSVD<40> RSVD<39> RSVD<38> RSVD<37> RSVD<36> RSVD<35> RSVD<34>

RSVD<32> RSVD<31> RSVD<30> RSVD<29> RSVD<28> RSVD<27> RSVD<26> RSVD<25> RSVD<24> RSVD<23> RSVD<22> RSVD<21> RSVD<20> RSVD<19>

RSVD<17> RSVD<16> RSVD<15> RSVD<14> RSVD<13> RSVD<12> RSVD<11> RSVD<10>

RSVD<9> RSVD<8> RSVD<7> RSVD<6> RSVD<5> RSVD<4> RSVD<3> RSVD<2> RSVD<1> RSVD<0>

B33 F27 K25 K27 D30 K29 J29 G28 H29 E28 F28 A31 C32 C31 D31 AL3 AL38 AG1 AF1 AK7 AT5 AT4 V11 U11 A40 AL4 AL5 AL41 AL40 K24 AK36 K15 L15

AU2 BA40 AY40 AW41 AY41 AW42 AV43 AV42 AV1 AY3 AW2 AV2 AY4 BA4

AF4 AF7 AG4 AG5 AH5 AK2 AM36 AM38 AN36 AN38 AR36 AR37 AT36 AV3 AV35 AW39 AY35 AY39

+1.1V_CPU0

R839

R839 X_49.9_1%_0402

X_49.9_1%_0402

R840

49.9_1%_0402

3

+1.1V_CPU0

R805

49.9_1%_0402

3

CPU0_VTT_VID2 (17)

CPU0_VTT_VID1 (17)

+1.1V_CPU0

R842

R842 X_100_1%

X_100_1%

R841

R841 X_100_1%

X_100_1%

PV_VTT_VREF_CPU0

C555

C555 X_0.1u_0402

X_0.1u_0402

+1.5V_DDR3_CPU0

R826

R826 X_100_1%

X_100_1%

R1329

R1329 X_100_1%

X_100_1%

PWRGD_CPU0_VTT(14,16,17,25,26,72)

2

P1V5_DDR3_VREF_CPU0

C1142

C1142 X_0.1u_0402

X_0.1u_0402

PWRGD_CPU0_VTT

CSI_CPU0_CMP1(27) CSI_CPU0_CMP0(27)

2

1

+1.1V_CPU0

R803

R803 X_1K_1%_0402

X_1K_1%_0402

FM_CPU0_PSI_N

R804

R804 X_1K_1%_0402

X_1K_1%_0402

+1.1V_CPU0

+5V

R845

R847

100_1%_0402

1K_1%_0402

R848 4.7K_0402R848 4.7K_0402

CSI_CPU0_CMP1 CSI_CPU0_CMP0 CSI_CPU0_CMPSTH M_CPU0_DDR_COMP[2] M_CPU0_DDR_COMP[1] M_CPU0_DDR_COMP[0]

CSI_CPU0_SKTOCC_N

MICRO-STAR INT'L CO.,LTD

MSI

Size Document Description Rev

B

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

Q87

Q87 2N3904

2N3904

R806 21_1%R806 21_1% R844 21_1%R844 21_1% R846 49.9_1%_0402R846 49.9_1%_0402 R807 130_1%_0402R807 130_1%_0402 R820 24.9_1%_0402R820 24.9_1%_0402 R819 100_1%_0402R819 100_1%_0402

R843 4.7K_0402R843 4.7K_0402

MS-9197

PWRGD_CPU0_VTT_GTL

Q86

Q86 2N3904

2N3904

+3.3VDUAL

029_CPU0(3/4)

1

29 78

Sheet of

0A

5

+1.5V_DDR3_CPU0 +1.1V_CPU0

U63F

A14

VDDQ<44>

A19

VDDQ<43>

A24

VDDQ<42>

A29

VDDQ<41>

A9

VDDQ<40>

B12

VDDQ<39>

B17

VDDQ<38>

B22

VDDQ<37>

B27

VDDQ<36>

B32

VDDQ<35>

AH11 AH33

AK11 AK12 AK13 AK15 AK16 AK18 AK19 AK21 AK24 AK25 AK27 AK28 AK30 AK31 AK33

AM12 AM13 AM15 AM16 AM18 AM19 AM21 AM24 AM25 AM27 AM28 AM30 AM31 AM33 AM34 AN12 AN13 AN15 AN16

AJ11 AJ33

AL12 AL13 AL15 AL16 AL18 AL19 AL21 AL24 AL25 AL27 AL28 AL30 AL31 AL33 AL34

B7 C10 C15 C20 C25 C30

D13

D18 D23 D28 E11 E16 E21 E26 E31 F14 F19 F24

G17 G22 G27 H15 H20 H25

J18 J23 J28

K16 K21 K26

L14 L19 L24

M17 M27

U33 V33

W33

VCC<209> VCC<208> VCC<207> VCC<206> VCC<205> VCC<204> VCC<203> VCC<202> VCC<201> VCC<200> VCC<199> VCC<198> VCC<197> VCC<196> VCC<195> VCC<194> VCC<193> VCC<192> VCC<191> VCC<190> VCC<189> VCC<188> VCC<187> VCC<186> VCC<185> VCC<184> VCC<183> VCC<182> VCC<181> VCC<180> VCC<179> VCC<178> VCC<177> VCC<176> VCC<175> VCC<174> VCC<173> VCC<172> VCC<171> VCC<170> VCC<169> VCC<168> VCC<167> VCC<166> VCC<165> VCC<164> VCC<163> VCC<162> VCC<161> VCC<160> VCC<159> VCC<158> VCC<157>

VDDQ<34> VDDQ<33> VDDQ<32> VDDQ<31> VDDQ<30> VDDQ<29> VDDQ<28> VDDQ<27> VDDQ<26> VDDQ<25> VDDQ<24> VDDQ<23> VDDQ<22> VDDQ<21> VDDQ<20> VDDQ<19> VDDQ<18> VDDQ<17> VDDQ<16> VDDQ<15> VDDQ<14> VDDQ<13> VDDQ<12> VDDQ<11> VDDQ<10> VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1> VDDQ<0>

VCCPLL<2> VCCPLL<1> VCCPLL<0>

D D

+1.8V_CPU0_PLL

C C

PV_VCCP_CPU0 PV_VCCP_CPU0

B B

A A

U63F

Gainstown

6/10

Gainstown

U63G

Gainstown

7/10

Gainstown

VCC<156> VCC<155> VCC<154> VCC<153> VCC<152> VCC<151> VCC<150> VCC<149> VCC<148> VCC<147> VCC<146> VCC<145> VCC<144> VCC<143> VCC<142> VCC<141> VCC<140> VCC<139> VCC<138> VCC<137> VCC<136> VCC<135> VCC<134> VCC<133> VCC<132> VCC<131> VCC<130> VCC<129> VCC<128> VCC<127> VCC<126> VCC<125> VCC<124> VCC<123> VCC<122> VCC<121> VCC<120> VCC<119> VCC<118> VCC<117> VCC<116> VCC<115> VCC<114> VCC<113> VCC<112> VCC<111> VCC<110> VCC<109> VCC<108> VCC<107> VCC<106> VCC<105> VCC<104>

VTTD<25> VTTD<24> VTTD<23> VTTD<22> VTTD<21> VTTD<20> VTTD<19> VTTD<18> VTTD<17> VTTD<16> VTTD<15> VTTD<14> VTTD<13> VTTD<12> VTTD<11> VTTD<10>

VTTD<9> VTTD<8> VTTD<7> VTTD<6> VTTD<5> VTTD<4> VTTD<3> VTTD<2> VTTD<1> VTTD<0>

VTTA<7> VTTA<6> VTTA<5> VTTA<4> VTTA<3> VTTA<2> VTTA<1> VTTA<0>

AN18 AN19 AN21 AN24 AN25 AN27 AN28 AN30 AN31 AN33 AN34 AP12 AP13 AP15 AP16 AP18 AP19 AP21 AP24 AP25 AP27 AP28 AP30 AP31 AP33 AP34 AR10 AR12 AR13 AR15 AR16 AR18 AR19 AR21 AR24 AR25 AR27 AR28 AR30 AR31 AR33 AR34 AT10 AT12 AT13 AT15 AT16 AT18 AT19 AT21 AT24 AT25 AT27

PV_VCCP_CPU0 PV_VCCP_CPU0

AF37 AA10 AA11 AA33 AB10 AB11 AB33 AB34 AB8 AB9 AC10 AC11 AC33 AC34 AC35 AD34 AD35 AD36 AD9 AE34 AE35 AE8 AE9 AF36 AF8 AF9

AG34 AF34 AF33 AF11 AE33 AE11 AE10 AD10

AT28 AT30 AT31 AT33 AT34

AU10 AU12 AU13 AU15 AU16 AU18 AU19 AU21 AU24 AU25 AU27 AU28 AU30 AU31 AU33 AU34

AV10 AV12 AV13 AV15 AV16 AV18 AV19 AV21 AV24 AV25 AV27 AV28 AV30 AV31 AV33 AV34

AW10 AW12 AW13 AW15 AW16 AW18 AW19 AW21 AW24 AW25 AW27 AW28

4

U63H

VCC<103> VCC<102> VCC<101> VCC<100> VCC<99>

AT9

VCC<98> VCC<97> VCC<96> VCC<95> VCC<94> VCC<93> VCC<92> VCC<91> VCC<90> VCC<89> VCC<88> VCC<87> VCC<86> VCC<85> VCC<84> VCC<83> VCC<82>

AU9

VCC<81> VCC<80> VCC<79> VCC<78> VCC<77> VCC<76> VCC<75> VCC<74> VCC<73> VCC<72> VCC<71> VCC<70> VCC<69> VCC<68> VCC<67> VCC<66> VCC<65>

AV9

VCC<64> VCC<63> VCC<62> VCC<61> VCC<60> VCC<59> VCC<58> VCC<57> VCC<56> VCC<55> VCC<54> VCC<53> VCC<52>

U63H

Gainstown

8/10

Gainstown

+1.1V_CPU0

+1.8V_CPU0_PLL +1.5V_DDR3_CPU0

AW30

VCC<51>

AW31

VCC<50>

AW33

VCC<49>

AW34

VCC<48>

AW9

VCC<47>

AY10

VCC<46>

AY12

VCC<45>

AY13

VCC<44>

AY15

VCC<43>

AY16

VCC<42>

AY18

VCC<41>

AY19

VCC<40>

AY21

VCC<39>

AY24

VCC<38>

AY25

VCC<37>

AY27

VCC<36>

AY28

VCC<35>

AY30

VCC<34>

AY31

VCC<33>

AY33

VCC<32>

AY34

VCC<31>

AY9

VCC<30>

BA10

VCC<29>

BA12

VCC<28>

BA13

VCC<27>

BA15

VCC<26>

BA16

VCC<25>

BA18

VCC<24>

BA19

VCC<23>

BA24

VCC<22>

BA25

VCC<21>

BA27

VCC<20>

BA28

VCC<19>

BA30

VCC<18>

BA9

VCC<17>

M11

VCC<16>

M13

VCC<15>

M15

VCC<14>

M19

VCC<13>

M21

VCC<12>

M23

VCC<11>

M25

VCC<10>

M29

VCC<9>

M31

VCC<8>

M33

VCC<7>

N11

VCC<6>

N33

VCC<5>

R11

VCC<4>

R33

VCC<3>

T11

VCC<2>

T33

VCC<1>

W11

VCC<0>

PLACE UNDER CPU PACKAGE 2 0805 10 UF CAPS AND 2 0805 22UF CAPS FOR VTTA 2 0805 10 UF CAPS AND 2 1206 47UF CAPS FOR VTTD

C1132

C1129

10u_0805

C486

C530

C530 10u_0805

10u_0805

C486 10u_0805

10u_0805

C1128

C1128 10u_0805

10u_0805

C506

C506 10u_0805

10u_0805

3

U63I

Y6 Y41 Y36 Y33 Y11

Y1

W8 W43 W38

W3

V5 V40 V35 V10

U7 U42 U37

U2

T9

T4 T39 T34

R6 R41 R36

R1

P8 P43 P38 P33

P3 P11

N5 N40 N35 N10

M7 M42 M37 M32 M30 M28 M26 M24 M22 M20

M2 M18 M16 M14 M12

L9

L4 L39 L34 L29

K6 K41 K36 K31 K11

K1

J8 J43 J38 J33

J3 J13

H5 H40 H35 H30 H10

G7 G42 G37 G32

G2 G12

C1172

10u_0805

VSS<309> VSS<308> VSS<307> VSS<306> VSS<305> VSS<304> VSS<303> VSS<302> VSS<301> VSS<300> VSS<299> VSS<298> VSS<297> VSS<296> VSS<295> VSS<294> VSS<293> VSS<292> VSS<291> VSS<290> VSS<289> VSS<288> VSS<287> VSS<286> VSS<285> VSS<284> VSS<283> VSS<282> VSS<281> VSS<280> VSS<279> VSS<278> VSS<277> VSS<276> VSS<275> VSS<274> VSS<273> VSS<272> VSS<271> VSS<270> VSS<269> VSS<268> VSS<267> VSS<266> VSS<265> VSS<264> VSS<263> VSS<262> VSS<261> VSS<260> VSS<259> VSS<258> VSS<257> VSS<256> VSS<255> VSS<254> VSS<253> VSS<252> VSS<251> VSS<250> VSS<249> VSS<248> VSS<247> VSS<246> VSS<245> VSS<244> VSS<243> VSS<242> VSS<241> VSS<240> VSS<239> VSS<238> VSS<237> VSS<236> VSS<235> VSS<234> VSS<233> VSS<232> VSS<231>

C514

C514 10u_0805

10u_0805

C515

C515 10u_0805

10u_0805

U63I

Gainstown

9/10

Gainstown

C465

C465 10u_0805

10u_0805

C1145

C1158

22u_0805

C1170

C1170 10u_0805

10u_0805

C1157

C1157 22u_0805

22u_0805

VSS<230> VSS<229> VSS<228> VSS<227> VSS<226> VSS<225> VSS<224> VSS<223> VSS<222> VSS<221> VSS<220> VSS<219> VSS<218> VSS<217> VSS<216> VSS<215> VSS<214> VSS<213> VSS<212> VSS<211> VSS<210> VSS<209> VSS<208> VSS<207> VSS<206> VSS<205> VSS<204> VSS<203> VSS<202> VSS<201> VSS<200> VSS<199> VSS<198> VSS<197> VSS<196> VSS<195> VSS<194> VSS<193> VSS<192> VSS<191> VSS<190> VSS<189> VSS<188> VSS<187> VSS<186> VSS<185> VSS<184> VSS<183> VSS<182> VSS<181> VSS<180> VSS<179> VSS<178> VSS<177> VSS<176> VSS<175> VSS<174> VSS<173> VSS<172> VSS<171> VSS<170> VSS<169> VSS<168> VSS<167> VSS<166> VSS<165> VSS<164> VSS<163> VSS<162> VSS<161> VSS<160> VSS<159> VSS<158> VSS<157> VSS<156> VSS<155> VSS<154> VSS<153>

C1160

C1160 10u_0805

10u_0805

F9 F4 F39 F34 F29 E6 E41 E36 E1 D8 D43 D38 D33 D3 C5 C43 C40 C35 BA5 BA39 BA35 BA3 BA29 BA26 BA20 BA17 BA14 BA11 B42 B37 B2 AY7 AY42 AY37 AY32 AY29 AY26 AY23 AY22 AY20 AY2 AY17 AY14 AY11 AW8 AW6 AW35 AW32 AW29 AW26 AW23 AW22 AW20 AW17 AW14 AW11 AW1 AV41 AV4 AV39 AV32 AV29 AV26 AV23 AV22 AV20 AV17 AV14 AV11 AU5 AU43 AU36 AU35 AU32 AU29 AU26 AU23 AU22

C539

C539 22u_0805

22u_0805

2

C458

C458 22u_0805

22u_0805

C459

C459 47u_1206

47u_1206

C540

C540 47u_1206

47u_1206

AU20 AU17 AU14 AU11

AT41 AT38 AT35 AT32 AT29 AT26 AT23 AT22 AT20 AT17 AT14 AT11 AR39 AR35 AR32

AR29 AR26 AR23 AR22 AR20

AR17 AR14 AR11

AP43 AP37 AP36 AP35 AP32 AP29 AP26 AP23 AP22 AP20 AP17 AP14 AP11 AP10

AN41 AN37 AN35 AN32

AN29 AN26 AN23 AN22 AN20 AN17 AN14 AN11

AM39 AM37 AM35 AM32 AM29 AM26 AM23 AM22 AM20 AM17 AM14 AM11

1

U63J

VSS<152> VSS<151> VSS<150> VSS<149>

AU1

VSS<148>

AT8

VSS<147>

AT7

VSS<146> VSS<145> VSS<144> VSS<143> VSS<142> VSS<141> VSS<140> VSS<139> VSS<138> VSS<137> VSS<136> VSS<135> VSS<134> VSS<133> VSS<132> VSS<131>

AR3

VSS<130> VSS<129> VSS<128> VSS<127> VSS<126> VSS<125>

AR2

VSS<124> VSS<123> VSS<122> VSS<121>

AP6

VSS<120>

AP5

VSS<119> VSS<118> VSS<117> VSS<116> VSS<115> VSS<114> VSS<113> VSS<112> VSS<111> VSS<110> VSS<109> VSS<108> VSS<107> VSS<106> VSS<105>

AP1

VSS<104>

AN7

VSS<103> VSS<102> VSS<101> VSS<100> VSS<99>

AN3

VSS<98> VSS<97> VSS<96> VSS<95> VSS<94> VSS<93> VSS<92> VSS<91> VSS<90>

AM9

VSS<89>

AM5

VSS<88> VSS<87> VSS<86> VSS<85> VSS<84> VSS<83> VSS<82> VSS<81> VSS<80> VSS<79> VSS<78> VSS<77> VSS<76>

AL7

VSS<75>

U63J

Gainstown

10/10

Gainstown

VSS<74> VSS<73> VSS<72> VSS<71> VSS<70> VSS<69> VSS<68> VSS<67> VSS<66> VSS<65> VSS<64> VSS<63> VSS<62> VSS<61> VSS<60> VSS<59> VSS<58> VSS<57> VSS<56> VSS<55> VSS<54> VSS<53> VSS<52> VSS<51> VSS<50> VSS<49> VSS<48> VSS<47> VSS<46> VSS<45> VSS<44> VSS<43> VSS<42> VSS<41> VSS<40> VSS<39> VSS<38> VSS<37> VSS<36> VSS<35> VSS<34> VSS<33> VSS<32> VSS<31> VSS<30> VSS<29> VSS<28> VSS<27> VSS<26> VSS<25> VSS<24> VSS<23> VSS<22> VSS<21> VSS<20> VSS<19> VSS<18> VSS<17> VSS<16> VSS<15> VSS<14> VSS<13> VSS<12> VSS<11> VSS<10>

VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> VSS<0>

AL42 AL37 AL36 AL35 AL32 AL29 AL26 AL23 AL22 AL20 AL2 AL17 AL14 AL11 AL1 AK9 AK43 AK39 AK34 AK32 AK3 AK29 AK26 AK23 AK22 AK20 AK17 AK14 AK10 AJ5 AJ41 AJ36 AJ34 AH7 AH39 AH37 AH34 AH1 AG9 AG43 AG33 AG3 AG11 AF5 AF41 AF38 AF35 AE7 AE39 AE2 AD43 AD41 AD37 AD33 AD11 AC9 AC7 AC5 AC36 AC2 AB7 AB42 AB40 AB4 AB37 AA9 AA39 AA38 AA34 AA3 A6 A41 A4 A39 A35

1

VSS

2

VSS

3

VSS

4

VSS

5

VSS

6

VSS

7

VSS

8

VSS

9

VSS

10

VSS

11

VSS

12

VSS

13

VSS

14

VSS

15

VSS

16

VSS

CAP on SOCKET

MICRO-STAR INT'L CO.,LTD

MS-9197

MSI

Size Document Description Rev

C

Date:

Saturday, December 01, 2007

Date:

Saturday, December 01, 2007

Date:

5

4

3

2

Saturday, December 01, 2007

MS-9197

030_CPU0(4/4)

1

Sheet of

30 78

0A

5

U64A

CSI_CPU1_IOH_CLK_DN(48) CSI_CPU1_IOH_CLK_DP(48) CSI_IOH_CPU1_CLK_DN(48) CSI_IOH_CPU1_CLK_DP(48)

CSI_CPU1_IOH_DN0(48) CSI_CPU1_IOH_DN1(48)

D D

C C

B B

CSI_CPU1_IOH_DN2(48) CSI_CPU1_IOH_DN3(48) CSI_CPU1_IOH_DN4(48) CSI_CPU1_IOH_DN5(48) CSI_CPU1_IOH_DN6(48) CSI_CPU1_IOH_DN7(48) CSI_CPU1_IOH_DN8(48) CSI_CPU1_IOH_DN9(48) CSI_CPU1_IOH_DN10(48) CSI_CPU1_IOH_DN11(48) CSI_CPU1_IOH_DN12(48) CSI_CPU1_IOH_DN13(48) CSI_CPU1_IOH_DN14(48) CSI_CPU1_IOH_DN15(48) CSI_CPU1_IOH_DN16(48) CSI_CPU1_IOH_DP17(48) CSI_CPU1_IOH_DN18(48) CSI_CPU1_IOH_DN19(48)

CSI_CPU1_IOH_DP0(48) CSI_CPU1_IOH_DP1(48) CSI_CPU1_IOH_DP2(48) CSI_CPU1_IOH_DP3(48) CSI_CPU1_IOH_DP4(48) CSI_CPU1_IOH_DP5(48) CSI_CPU1_IOH_DP6(48) CSI_CPU1_IOH_DP7(48) CSI_CPU1_IOH_DP8(48) CSI_CPU1_IOH_DP9(48) CSI_CPU1_IOH_DP10(48) CSI_CPU1_IOH_DP11(48) CSI_CPU1_IOH_DP12(48) CSI_CPU1_IOH_DP13(48) CSI_CPU1_IOH_DP14(48) CSI_CPU1_IOH_DP15(48) CSI_CPU1_IOH_DP16(48) CSI_CPU1_IOH_DN17(48) CSI_CPU1_IOH_DP18(48) CSI_CPU1_IOH_DP19(48)

CSI_IOH_CPU1_DN19(48) CSI_IOH_CPU1_DN18(48) CSI_IOH_CPU1_DN17(48) CSI_IOH_CPU1_DN16(48) CSI_IOH_CPU1_DN15(48) CSI_IOH_CPU1_DN14(48) CSI_IOH_CPU1_DN13(48) CSI_IOH_CPU1_DN12(48) CSI_IOH_CPU1_DN11(48) CSI_IOH_CPU1_DN10(48) CSI_IOH_CPU1_DN9(48) CSI_IOH_CPU1_DN8(48) CSI_IOH_CPU1_DN7(48) CSI_IOH_CPU1_DN6(48) CSI_IOH_CPU1_DN5(48) CSI_IOH_CPU1_DN4(48) CSI_IOH_CPU1_DN3(48) CSI_IOH_CPU1_DN2(48) CSI_IOH_CPU1_DP1(48) CSI_IOH_CPU1_DN0(48)

CSI_IOH_CPU1_DP19(48) CSI_IOH_CPU1_DP18(48) CSI_IOH_CPU1_DP17(48) CSI_IOH_CPU1_DP16(48) CSI_IOH_CPU1_DP15(48) CSI_IOH_CPU1_DP14(48) CSI_IOH_CPU1_DP13(48) CSI_IOH_CPU1_DP12(48) CSI_IOH_CPU1_DP11(48) CSI_IOH_CPU1_DP10(48) CSI_IOH_CPU1_DP9(48) CSI_IOH_CPU1_DP8(48) CSI_IOH_CPU1_DP7(48) CSI_IOH_CPU1_DP6(48) CSI_IOH_CPU1_DP5(48) CSI_IOH_CPU1_DP4(48) CSI_IOH_CPU1_DP3(48) CSI_IOH_CPU1_DP2(48) CSI_IOH_CPU1_DN1(48) CSI_IOH_CPU1_DP0(48)

CSI_CPU1_IOH_CLK_DN

CSI_CPU1_IOH_CLK_DP

CSI_IOH_CPU1_CLK_DN

CSI_IOH_CPU1_CLK_DP

CSI_CPU1_IOH_DN0 CSI_CPU1_IOH_DN1 CSI_CPU1_IOH_DN2 CSI_CPU1_IOH_DN3 CSI_CPU1_IOH_DN4 CSI_CPU1_IOH_DN5 CSI_CPU1_IOH_DN6 CSI_CPU1_IOH_DN7 CSI_CPU1_IOH_DN8 CSI_CPU1_IOH_DN9 CSI_CPU1_IOH_DN10 CSI_CPU1_IOH_DN11 CSI_CPU1_IOH_DN12 CSI_CPU1_IOH_DN13 CSI_CPU1_IOH_DN14 CSI_CPU1_IOH_DN15 CSI_CPU1_IOH_DN16 CSI_CPU1_IOH_DP17 CSI_CPU1_IOH_DN18 CSI_CPU1_IOH_DN19

CSI_CPU1_IOH_DP0 CSI_CPU1_IOH_DP1 CSI_CPU1_IOH_DP2 CSI_CPU1_IOH_DP3 CSI_CPU1_IOH_DP4 CSI_CPU1_IOH_DP5 CSI_CPU1_IOH_DP6 CSI_CPU1_IOH_DP7 CSI_CPU1_IOH_DP8 CSI_CPU1_IOH_DP9 CSI_CPU1_IOH_DP10 CSI_CPU1_IOH_DP11 CSI_CPU1_IOH_DP12 CSI_CPU1_IOH_DP13 CSI_CPU1_IOH_DP14 CSI_CPU1_IOH_DP15 CSI_CPU1_IOH_DP16 CSI_CPU1_IOH_DN17 CSI_CPU1_IOH_DP18 CSI_CPU1_IOH_DP19

CSI_IOH_CPU1_DN19 CSI_IOH_CPU1_DN18 CSI_IOH_CPU1_DN17 CSI_IOH_CPU1_DN16 CSI_IOH_CPU1_DN15 CSI_IOH_CPU1_DN14 CSI_IOH_CPU1_DN13 CSI_IOH_CPU1_DN12 CSI_IOH_CPU1_DN11 CSI_IOH_CPU1_DN10 CSI_IOH_CPU1_DN9 CSI_IOH_CPU1_DN8 CSI_IOH_CPU1_DN7 CSI_IOH_CPU1_DN6 CSI_IOH_CPU1_DN5 CSI_IOH_CPU1_DN4 CSI_IOH_CPU1_DN3 CSI_IOH_CPU1_DN2 CSI_IOH_CPU1_DP1 CSI_IOH_CPU1_DN0

CSI_IOH_CPU1_DP19 CSI_IOH_CPU1_DP18 CSI_IOH_CPU1_DP17 CSI_IOH_CPU1_DP16 CSI_IOH_CPU1_DP15 CSI_IOH_CPU1_DP14 CSI_IOH_CPU1_DP13 CSI_IOH_CPU1_DP12 CSI_IOH_CPU1_DP11 CSI_IOH_CPU1_DP10 CSI_IOH_CPU1_DP9 CSI_IOH_CPU1_DP8 CSI_IOH_CPU1_DP7 CSI_IOH_CPU1_DP6 CSI_IOH_CPU1_DP5 CSI_IOH_CPU1_DP4 CSI_IOH_CPU1_DP3 CSI_IOH_CPU1_DP2 CSI_IOH_CPU1_DN1 CSI_IOH_CPU1_DP0

AG42 AR41

AR42

AE40 AD38 AB39 AC39 AC41 AD40 AC43 AD42 AE42

AG40 AK42

AH41 AK40 AH40

AK37 AG38

AE38 AB38 AC38 AC40 AD39 AB43 AC42 AE41 AE43 AG41 AH43

AH42 AK41

AK38 AG39 AH38

AP38 AN39 AP41 AM42 AN40 AN43 AP42 AT40 AT43 AU42 AU40

AW40

AU39 BA38

AW37

BA36

AW36

AV36 AU38 AT37

AR38 AP39 AP40 AM41 AM40 AM43 AN42 AR40 AR43 AT42 AU41 AV40 AT39 AY38

AW38

BA37 AY36 AV37 AV38 AU37

AF42

AL43

AF43 AJ43

AJ38 AF39

AF40

AJ42

AJ40 AJ39

CSI0_CLKTX_DP CSI0_CLKTX_DN CSI0_CLKRX_DP CSI0_CLKRX_DN CSI0_COMP

CSI0_DTX_DP<19> CSI0_DTX_DP<18> CSI0_DTX_DP<17> CSI0_DTX_DP<16> CSI0_DTX_DP<15> CSI0_DTX_DP<14> CSI0_DTX_DP<13> CSI0_DTX_DP<12> CSI0_DTX_DP<11> CSI0_DTX_DP<10> CSI0_DTX_DP<9> CSI0_DTX_DP<8> CSI0_DTX_DP<7> CSI0_DTX_DP<6> CSI0_DTX_DP<5> CSI0_DTX_DP<4> CSI0_DTX_DP<3> CSI0_DTX_DP<2> CSI0_DTX_DP<1> CSI0_DTX_DP<0>

CSI0_DTX_DN<19> CSI0_DTX_DN<18> CSI0_DTX_DN<17> CSI0_DTX_DN<16> CSI0_DTX_DN<15> CSI0_DTX_DN<14> CSI0_DTX_DN<13> CSI0_DTX_DN<12> CSI0_DTX_DN<11> CSI0_DTX_DN<10> CSI0_DTX_DN<9> CSI0_DTX_DN<8> CSI0_DTX_DN<7> CSI0_DTX_DN<6> CSI0_DTX_DN<5> CSI0_DTX_DN<4> CSI0_DTX_DN<3> CSI0_DTX_DN<2> CSI0_DTX_DN<1> CSI0_DTX_DN<0>

CSI0_DRX_DP<19> CSI0_DRX_DP<18> CSI0_DRX_DP<17> CSI0_DRX_DP<16> CSI0_DRX_DP<15> CSI0_DRX_DP<14> CSI0_DRX_DP<13> CSI0_DRX_DP<12> CSI0_DRX_DP<11> CSI0_DRX_DP<10> CSI0_DRX_DP<9> CSI0_DRX_DP<8> CSI0_DRX_DP<7> CSI0_DRX_DP<6> CSI0_DRX_DP<5> CSI0_DRX_DP<4> CSI0_DRX_DP<3> CSI0_DRX_DP<2> CSI0_DRX_DP<1> CSI0_DRX_DP<0>

CSI0_DRX_DN<19> CSI0_DRX_DN<18> CSI0_DRX_DN<17> CSI0_DRX_DN<16> CSI0_DRX_DN<15> CSI0_DRX_DN<14> CSI0_DRX_DN<13> CSI0_DRX_DN<12> CSI0_DRX_DN<11> CSI0_DRX_DN<10> CSI0_DRX_DN<9> CSI0_DRX_DN<8> CSI0_DRX_DN<7> CSI0_DRX_DN<6> CSI0_DRX_DN<5> CSI0_DRX_DN<4> CSI0_DRX_DN<3> CSI0_DRX_DN<2> CSI0_DRX_DN<1> CSI0_DRX_DN<0>

Gainstown

1/10

Gainstown

4

CSI1_CLKTX_DP CSI1_CLKTX_DN CS1_CLKRX_DP CSI1_CLKRX_DN