MSI MS-9192 Schematic 0502

1

MSI

MS-9192 1U & 2U Server

Revision 0A

Intel Dual FC-LGA4 771 Dempsey/Woodcrest/Clovertown Processor
Intel Blackford / ESB2 Chipset
LSI 1068 SAS Controller
Intel Gilgal 82563EB Dual Gb Ethernet PHY
ServerEngines Server Management Controller Pilot

Title Page

System Block Diagram
Voltage Table

A A

2
3

4Power Block Diagram
Clock Block Diagram 5
SMBus Block Diagram 6
JTAG Block Diagram
System Reset Block Diagram

Processor 0
Processor 1

MCH (Blackford)
Fully buffered DIMMs
FBDs Reset and Decoupling Caps.
ESB2

Firmware Hub
SATA and USB Connectors

7

8

9-11

12-14

15-22

23-34

35

36-44

45

46

Title Page

LAN (Gilgal)Cover Sheet 1

PCI Express X8 Slots
POLIT2
Clocks (CK410B/DB1900/DB800)
Thermtrip
CPU BSEL Level Translation
EPLD / RSMRST#
Extended Debug Port (XDP)
Hardware monitor
PECI Poller
Back Panel Connector
Power Connector and NMI
Processor 0 VREG (VR11)

Processor 1 VREG (VR11)
VCORE Decoupling Cap.

47-49
50
51-52
53-57
58-60
61
62
63
64
65
66
67
68
69-70

71-72
73

Title Page

FBD 1.8V VREG

1.5V VREG280 Pin PCI-X/PCI-E Slot
FSB VTT 1.2V /FBD VTT 0.9V VREG
Standby / MISC VREG
Impedance Test / mouting hole
Manual Parts
VT1135S Option Parts
GPIO Maping
Reset and Power Good PLD Logic
Power On/Off and Reset Sequence
History
Reserved Page

74
75
76
77
78
79
80-83
84

85
86

88-89
90

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

1

http://www.msi.com.tw

Micro Star Restricted Secret

Cover Sheet

MS-9192

Last Revision Date:

Friday, April 27, 2007

Sheet

190

Rev

0A

of

System Block Diagram

1

VRM 11
For CPU0

1.2V VRD
FSB VTT

PCI-E X8 Slot

PCI-E X8 Slot

1.5VSBY
VREG

3.3VSBY
VREG

A A

280 PIN SLOT

( PCI-X & PCI-E X8 )

1.5V VRD

BNB+FBD
ESB2

CPU0
FC-LGA4 771 Processor

FSB0 / 1066/1333MHz FSB

PCI Express X8

4GB/s

PCI Express X8

4GB/s

PCI Express X8

PCI-X 100/133

Port #4&5

Port #6&7

PCI Express X8 ESI X4
4GB/s

Port #1&2

(X8)

CPU1
FC-LGA4 771 Processor

Blackford

MCH

FSB1 / 1066/1333MHz FSB

Port #0Port #2&3

2GB/s

Port #3Port #4

(ESI)(X8)

FBD CH0

FBD CH1

FBD CH2

FBD CH3

DIMM #00

DIMM #10

DIMM #20

DIMM #30

SATA

Ultra DMA 66/100

SATA 0~5

ATA Primary

VRM 11
For CPU1

DIMM #01

DIMM #11

DIMM #21

DIMM #31

DIMM #02

DIMM #12

DIMM #22

DIMM #32

NOTE:

Channel 0 & 1 Makes Branch 0
Channel 2 & 3 Makes Branch 1

1.8V VRD

0.9V VRD

CK410B

DB1900

DB800

FBD Clocks

PCI-E Clocks

ESB2

Serial EEPROM

USB2.0

Port #6

Port #0

(X1)

PCI Express X1

KUMERAN

ServerEngines

LPC

Pilot II

USB2.0 Port 0~5

Dual Gb PHY

GILGAL

VGA
PS2 KB/MS
Serial Port *2

Gb LAN

Gb LAN

Port #0,1,4,5 Front
Port #2,3 Rear

RJ45

RJ45

Port #1 Rear
Port #2 Front

Gilgal internal
VREG Circuitry

FWH

TPM 1.2

BMC
Flash

10/100

PHY

1

RJ45

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

Micro Star Restricted Secret

System Block Diagram

MS-9192

Last Revision Date:

Friday, April 27, 2007

Sheet

290

Rev

0A

of

Voltage Table

1

Voltage
Level

+3.3V

+5V

+5V

Netname

P3V3
P5V
P5VSB

Generated
From

AC
AC
AC

STBY

-12V
+12V1
+12V2
+12V3

VID_CPU0 P12V_CPU0
VID_CPU1

+1.2V

A A

+1.5V

+1.5V

P-12V

P12V
P12V_CPU1
P12V_CPU0

VCORE0
VCORE1

P_VTT

P1V5

P1V5_AUX

AC
AC
AC
AC

P12V_CPU1
P5V

P12V

P3V3_AUX

AUX

+1.8V

P1V8 P12V

+0.9V

+3.3V
STBY

+3.3V
AUX

+1.8V1
AUX

+1.2V1
AUX

+1.8V2
AUX
+1.2V2
AUX

F_VTT P1V8

P3VSB

P5VSB

P3V3_AUX P3V3 /

P3VSB

P1V8LAN
P1V2LAN

P1V8_AUX

P1V2_AUX

P3V3_AUX
P3V3_AUX
P3V3_AUX
P3V3_AUX

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

1

http://www.msi.com.tw

Micro Star Restricted Secret

Voltage Table

MS-9192

Last Revision Date:

Sheet

Friday, April 27, 2007

390

Rev

0A

of

Power Block Diagram

1

+12V3

16A/18Apk

+12V2

16A/18Apk

+12V1

16A/18Apk

P12V3 P5VSB

CPU VREG
VR11

P12V2

CPU VREG
VR11

P12V1

1.8V FBD
VREG

VCORE0

VCORE0

P1V8

0.9V FBD
VTT VREG

CPU0

CPU1

12 FBDs

F_VTT

150A

150A

95.52A

FBD VTT

3.48A

5VSBY

3A/3.5Apk

+3V3

24A

P3V3

3.3VSB
VREG

SWITCH

P3VSB

P3V3_AUX

AUX1.5V
VREG

Active:2A

Standby:1A

AUX1.8V1

Active:0.85A

VREG

Standby:0.24A

AUX1.2V1

Active:0.58A

VREG

Standby:0.05A

ESB2

0.066A

P1V5_AUX

P1V8LAN

P1V2LAN

ESB2

1.4A

GILGAL

0.85A

GILGAL

0.58A

PCI-E & PCI-X slots

PCI-E & PCI-X slots

A A

+5V

30A

P5V

1.5V VREG

FSB VTT
VREG

P1V5

P_VTT

1.2V ?A

MCH

12 FBDs

ESB2

CPU 0/1 VTT

19.1A

5.8A

48A

8A

PILOT

0.05A

AUX1.8V2
VREG

AUX1.2V2
VREG

P1V8_AUX

P1V2_AUX

PILOT

PILOT

USB *6

3A

PCI-X Slot

MCH

4.8A

ESB2

1.8A

5A

PCI-E & PCI-X slots

1

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

Micro Star Restricted Secret

Power Block Diagram

MS-9192

Last Revision Date:

Friday, April 27, 2007

Sheet

490

Rev

0A

of

Clock Block Diagram

1

2

CK_H_FBD0_P/N

CK_H_FBD1_P/N

CK_H_FBD2_P/N

CK_H_FBD3_P/N

CK_H_FBD4_P/N

CK_H_FBD5_P/N

CK_H_FBD6_P/N

CK_H_FBD7_P/N

CK_H_FBD8_P/N

CK_H_FBD9_P/N

CK_H_FBD10_P/N

CK_H_FBD11_P/N

PILOT

REFCLKP/N

2

REFCLKP/N

2

REFCLKP/N

2

DB1900

DIF_0P/N

DIF_1P/N

CK410B

CPU_1P/N

CPU_2P/N

CK_H_P0 (267/333MHz)

CK_H_P1 (267/333MHz)

BCLK0/1

2

BCLK0/1

2

CPU0

CPU1

XDP (CPU)

XDP0_BCLK_P/N

CLK

2

DIF_17P/N

DIF_2P/N

DIF_3P/N

DIF_4P/N

DIF_5P/N

USB_48

PCIF_1

REF_1

CK_H_FBD (267/333MHz)

CK_H_MCH (267/333MHz)

MCH_100CLK_P/N (100MHz)

SRC_100CLK_P/N (100MHz)

ESI_100CLK_P/N (100MHz)

ESB2_100CLK_P/N (100MHz)

SATA_100CLK_P/N (100MHz)

CK_48M_ESB

ESB2_PCLK

ESB_14MHZ

Blackford

FBD01CLKP/N

CORECLKP/N

2

2

2

2

PECLKP/N

32.768KHz
Crystal

ESICLK100P/N

PECLKP/N

SATACLKP/N

CLK48

PCICLK

CLK14

FBD23CLKP/N

2

ESB2

SER_CLK_IN

PXPCLKO_0

PXPCLKO_1

2

2

SK_LAN_CLK

PXPCLK0

PXPCLK1

62.5MHz
OSC

FBD01CLK_P/N

FBD23CLK_P/N

2

Gilgal LAN

PHY_CLK_OUT

25MHz
Crystal

SRC_INP/N

DB800

CLK

CLK

CPU_3P/N

CPU_0P/N

BCLK 267/333MHz

SRC_4P/N

SRC_0P/N

SRC_2P/N

SRC_1P/N

A A

SRC_3P/N

Serial Ref Clk 100MHz

CLK_INP/N

2

DIF_15P/N

DIF_16P/N

DIF_5P/N

PCIE_SAS_SRC_P/N

ESB:PCI-X 133

ESB:PCI-X 133

DIF_2P/N

DIF_6P/N

DIF_7P/N

DIF_6P/N

DIF_7P/N

DIF_8P/N

DIF_9P/N

DIF_10P/N

DIF_11P/N

PCIE2_100CLK_P/N0

PCIE1_100CLK_P/N0

PCIE1_100CLK_P/N1

2

2

2

2

2

2

2

2

2

2

2

2

ESB:PCI-E X8

ESB:PCI-E X8

ESB:PCI-E X8

SCKP/N

SCKP/N

SCKP/N

SCKP/N

SCKP/N

SCKP/N

SCKP/N

SCKP/N

SCKP/N

SCKP/N

SCKP/N

SCKP/N

FB DIMM00

FB DIMM01

FB DIMM02

FB DIMM10

FB DIMM11

FB DIMM12

FB DIMM20

FB DIMM21

FB DIMM22

FB DIMM30

FB DIMM31

FB DIMM32

14.318MHz
Crystal

PCIF_2

PCI_0

PCI_3

PCIF_0

PCI_2

SIO_PCLK

FWH_PCLK

PLD_33MHZ_CLK

XDP0_33MHZ_CLK

DEBUG_33MHZ_CLK

CK_48M_PILOT

FWH

CLK

PLD

GCK1

XDP (CPU)

CLK

LPC DBG

CLK

CLKI

LCLK

PILOT

48MHz OSC

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

1

http://www.msi.com.tw

Micro Star Restricted Secret

Clock Block Diagram

MS-9192

Last Revision Date:

Friday, April 27, 2007

Sheet

590

Rev

0A

of

SMBus Block Diagram

1

DIMM #00

Serial EEPROM: 0XA0
AMB:ADDR 0XB0

CLK410B

ADDR 0XD2

Blackford

DB800

ADDR 0XDC

DB1900

ADDR 0XDE

CPU XDP

CPU0 VCORE
VRD11

ADDR

CPU1 VCORE

A A

VRD11

ADDR

MAIN_SMB

0 ohm

ADDR

3.3V

ESB2

SDTA/SCLK
(0XC2)

SPD0SDA/SPD0SCL
(Master SPD, 100KHz)

SPD1SDA/SPD1SCL

(Master SPD, 100KHz)

SPD2SDA/SPD2SCL

(Master SPD, 100KHz)

SPD3SDA/SPD3SCL

(Master SPD, 100KHz)

CFGSMBDATA/CFGSMBCLK

(Slave, 100KHz, 0XC0)

3.3V

3.3V

3.3V

3.3V

3.3V

DIMM #10 DIMM #11 DIMM #12

Serial EEPROM: 0XA0
AMB:ADDR 0XB0

DIMM #20

Serial EEPROM: 0XA0
AMB:ADDR 0XB0

DIMM #30 DIMM #31 DIMM #32

Serial EEPROM: 0XA0
AMB:ADDR 0XB0

MCH_SPD0_SMB

MCH_SPD1_SMB

MCH_SPD2_SMB

MCH_SPD3_SMB

PCI-E X8 Slot

PCI-E X8 Slot

1.8V VREG

ADDR

PCA9515

SMBus Isolator

3.3V AUX

SMBDATA/SMBCLK

PCA9515

SMBus Isolator

280 PIN PCI-X & PCI-E Slot

WHEA ROM

ADDR 0XAE

IPMB Header

5VSB

PCA9515

SMBus Isolator

3.3V AUX

3.3V AUX

SDA4/SCL4

SDA0/SCL0

3.3V AUX

SDA1/SCL1

SDA2/SCL2

3.3V AUX

DIMM #01

Serial EEPROM: 0XA2
AMB:ADDR 0XB2

Serial EEPROM: 0XA2 Serial EEPROM: 0XA4
AMB:ADDR 0XB2

DIMM #21

Serial EEPROM: 0XA2
AMB:ADDR 0XB2

Serial EEPROM: 0XA2 Serial EEPROM: 0XA4
AMB:ADDR 0XB2

DIMM #02

Serial EEPROM: 0XA4

AMB:ADDR 0XB4

AMB:ADDR 0XB4

DIMM #22

Serial EEPROM: 0XA4

AMB:ADDR 0XB4

AMB:ADDR 0XB4

HW Monitor

ADT7462

ADDR 0X5C

HW Monitor

ADT7462

ADDR 0X5C

FRU ROM

ADDR 0XAE

SDA0/SCL0

SMBus

Selector

SDA1/SCL1

SDA2/SCL2

SDA3/SCL3

SDA/SCL

BackPanel

Power

ADDR

5VSB

PCA9515

SMBus Isolator

3.3V AUX

Front Panel

Thermal Sensor

ADDR

SDA3/SCL3

PILOT

1

SDA5/SCL5

3.3V AUX

PCA9515

SMBus Isolator

PECI
CY8C21234

ADDR 0X

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

Micro Star Restricted Secret

SMBus Block Diagram

MS-9192

Last Revision Date:

Friday, April 27, 2007

Sheet

690

Rev

0A

of

JTAG Block Diagram

1

XDP0_TDI_FSB1

P_VTT

51 OHM

P_VTT

51 OHM

1
2

1

3
4

GTL-TTL

Translator

TRST#

TDO

TDI

TMS TRST#

TDI

CPU1

XDP0_TDO_FSB1

TDO

TCK

51 OHM

GND

XDP0_TDI_ESB
XDP0_TRST_ESB#

1K OHM

GND

P_VTT

51 OHM

TDI
TRST#

XDP0_TMS_ESB

TMS

TMS

ESB2

GTL-TTL

Translator

ESB2 in chain

TDO

TCK

XDP0_TCK1_ESB

TCK

JUMPER 0

1-2, 3-4 : CPU0 in chain
2-3 : CPU0 bypass

JUMPER 1

1-2, 3-4 : CPU1 in chain
2-3 : CPU1 bypass

P3V3

1K OHM

1K OHM

P_VTT

XDP0_TDI_MAIN

TDI

TCK0

CPU XDP0
Connector

TDO

TMS

TRST#

A A

TCK1

0 OHM

51 OHM

XDP0_TDI_FSB0

P_VTT

51 OHM

XDP0_TDI_MCH

1
2
3
4

TDI

TMS TRST#

0

TDI

TMS

CPU0

XDP0_TCK0

XDP0_TDO_FSB0
XDP0_TDI_MAIN_JMP

XDP0_TDO_MAIN
XDP0_TMS_MAIN
XDP0_TRST#

TRST#

MCH

TCK

TDO

TCK

TDO

MCH in chain

51 OHM

GND

XDP0_TDO_MCH

P_VTT

51 OHM

51 OHM

GND

XDP0_TCK1

P_VTT

51 OHM

1

XDP0_TMS_GTL

XDP0_TDO_ESB

0 OHM

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

Micro Star Restricted Secret

GND

JTAG Block Diagram

MS-9192

Last Revision Date:

Friday, April 27, 2007

Sheet

Rev

0A

of

790

System Reset Block Diagram

1

VRM0_PWRGD

CK410B

PWRDOWN

DB800

PWRDOWN_N

CPU_VRD_PWRGD

EPLD

CPU0_SKTOCC#

VRM1_PWRGD

CPU1_SKTOCC#

POWER SUPPLY

PWOK

PSON#

ONCTL#

VDDPWR_GD

EPLD

PS_PWROK_BUF

GPIO8

PWBTOUTn

SLPS3n

SLPS5n

PILOT

CPU_VRD_PWRGD

EPLD

100 ms

Delay

PWR_BT_SSI_#

SYS_PWRGD_BUFF

3.3V STBY

SYS_PWRGD_3_3V

RSMRST#

PWRBTN_N

SLP_S3_N

SLP_S4_N

PERST_N

PXPWROK

PWROK

VRMPWRGD

RSMRST_N

LAN_PWR_GD

PWR BTN

3.3VAUX

10Kohms

GND

PWR_BT_IN#

A A

PLTRST_BUFF1#

THERMTRIP0_N

THERMTRIP1_N

ONCTLn

PWBTINn

PCIRSTn

GPIO19

GPIO20

RST BTN

10Kohms

GND

ESB_SYS_RST_N

SYS_RESET_N

ESB2

PHY_PWR_DOWN PHYRST_0_N

PHY_PWR_GD

Pwrgd

CPU1 VRD

Pwrgd

3.3VAUX

CPU_PWR_GD

PLTRST_IN_N

PXPCIRST_N

THRMTRIP_N

PHY_RESET_NPHY_SLEEP

CPU0 VRD

OE

VID[6..0]

OE

VID[6..0]

INIT_N

INIT3_3V_N

PLTRST_N

PCIRST_N

GPIO33

THERMTRIP_N

VRD0_EN

P0VID[6..0]

VRD1_EN

P1VID[6..0]

CPU_PWRGD

INIT#_3_3V

ESB_PLTRST#

PXPCIRST_N

EPLD
CPU0

EPLD
CPU1

FSB_INIT#

FWH

INIT#

RST_N

PLTRST_BUFF1#

EPLD

280 Pin Slot, SAS 1068

FBD_RESET

ESB_SYS_RST_N

PLTRST_N

DBR_N

INIT_N

PWRGOOD

DBR_N

INIT_N

PWRGOOD

IDE_RSTDRV_N

IDE

CPU0

CPU1

Blackford

PLTRST_N

FSB VTT VRD

VTTPWRGD

THERMTRIP_N

RESET#

VTTPWRGD

THERMTRIP_N

RESET#

FSB1RESET_N

FSB0RESET_N

PWRGOOD

SYS_PWRGD_3_3V

EPLD

SYS_PWRGD_3_3V

FBD_BR0_RST#

GLUE

FBD_BR1_RST#

LOGIC

STAT

VTT_PWRGD

FSB0_THERMTRIP_N

FSB1_THERMTRIP_N

FSB1_RESET_N

FSB0_RESET_N

DIMM#00,01,02,10,11,12
DIMM#20,21,22,30,31,32

Level
Translation
GTL to 3.3V

Level
Translation

3.3V to GTL

ESB_SYS_RST_N

RESET_IN#

PWRGOOD

VTT_PWRGD_3_3V

PLD_VTT_PWRGD_3_3V

GLUE

LOGIC

RESET_OUT#

XDP

EPLD

THERMTRIP_N
THERMTRIP0_N
THERMTRIP1_N

ESB2

PILOT

Gilgal

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

1

http://www.msi.com.tw

Micro Star Restricted Secret

System Reset Block Diagram

MS-9192

Last Revision Date:

Friday, April 27, 2007

Sheet

890

Rev

0A

of

5

4

3

2

1

P0 Intel LGA771 Signal

VCC0_SENSE2
VSS0_SENSE2
VCC0_SENSE1

D11

FSB0_D15

D14#

C12

FSB0_D14

FSB0_D13

AL7

AL8

VSS_DIE_SENSE2

VCC_DIE_SENSE2

D13#

D12#D8D11#

B12

FSB0_D12

AN3

VCC_DIE_SENSE

C11

FSB0_D11

AN4

VSS_DIE_SENSE

D10#

B10

FSB0_D10

FSB0_D9

VSS0_SENSE1

D9#

D8#

A11

A10

FSB0_D8

FSB0_A[35..3]15

FSB0_DBI#[3..0]15

FSB0_RESET_N15

FSB0_RSP_N15

FSB0_BPRI_N15

FSB0_TRDY_N15

FSB0_DEFER_N15

FSB0_FORCEPR#69

FSB_IGNNE#12,40

FSB_STPCLK#12,40

XDP0_TDI_FSB064
XDP0_TDO_FSB064
XDP0_TMS_MAIN12,20,64

XDP0_TRST#12,20,64
FSB0_GTL_IERR#62
FSB0_PROCHOT#65

FSB0_ADS_N15
FSB0_BNR_N15

FSB0_HIT_N15

FSB0_DBSY_N15

FSB0_DRDY_N15

FSB0_HITM_N15

FSB0_LOCK_N15

FSB0_BINIT_N15

FSB0_MCERR_N15

CPU0_SKTOCC#54,62,63,65

P0THERMDA265
P0THERMDC265

P0THERMDA65

P0THERMDC65

CPU_DBR_RST#12,64

R1208 0

FSB0_VIDSEL63,69

FSB0_BSEL062

FSB0_BSEL162

FSB0_BSEL262

FSB0_D[63..0]15

FSB_A20M#12,40

FSB_NMI12,40
FSB_INTR12,40

FSB_INIT#12,40,67

XDP0_TCK012,64

FSB_FERR#12,40

P0_MS_ID163
P0_MS_ID063

CPU_DBR_RST#

P0_THERMTRIP_N

D D

C C

CPU1_TESTBUS12

B B

A A

FSB0_A[35..3]
FSB0_DBI#[3..0]
FSB0_D[63..0]

FSB0_DBI#0
FSB0_DBI#1
FSB0_DBI#2
FSB0_DBI#3

FSB0_RESET_N
FSB0_RSP_N
FSB0_BPRI_N
FSB0_TRDY_N
FSB0_DEFER_N

CPU0_SMI_N
FSB_A20M#
FSB0_FORCEPR#
FSB_NMI
FSB_INTR
FSB_IGNNE#
FSB_STPCLK#
FSB_INIT#

XDP0_TCK0
XDP0_TDI_FSB0
XDP0_TDO_FSB0
XDP0_TMS_MAIN
XDP0_TRST#

FSB0_GTL_IERR#
FSB_FERR#
FSB0_PROCHOT#
P0_THERMTRIP_N

FSB0_ADS_N
FSB0_BNR_N
FSB0_HIT_N
FSB0_DBSY_N
FSB0_DRDY_N
FSB0_HITM_N
FSB0_LOCK_N
FSB0_BINIT_N
FSB0_MCERR_N

CPU0_SKTOCC#
P0THERMDA2
P0THERMDC2
P0THERMDA
P0THERMDC

CPU_DBR_RST#
CPU0_BOOT

CPU0_TESTBUS

P0_LL_ID1
P0_LL_ID0
P0_MS_ID1
P0_MS_ID0

FSB0_BSEL0
FSB0_BSEL1
FSB0_BSEL2

FSB0_D63
FSB0_D62
FSB0_D61
FSB0_D60
FSB0_D59
FSB0_D58
FSB0_D57
FSB0_D56
FSB0_D55
FSB0_D54

R712 0

R720 2.2

A8

DBI0#

G11

DBI1#

D19

DBI2#

C20

DBI3#

G23

RESET#

H4

RSP#

G8

BPRI#

E3

TRDY#

G7

DEFER#

P2

SMI#

K3

A20M#

AK6

FORCEPR#

L1

LINT1/NMI

K1

LINT0/INTR

N2

IGNNE#

M3

STPCLK#

P3

INIT#

AE1

TCK

AD1

TDI

AF1

TDO

AC1

TMS

AG1

TRST#

AB2

IERR#

R3

FERR#/PBE#

AL2

PROCHOT#

M2

THERMTRIP#

D2

ADS#

C2

BNR#

D4

HIT#

B2

DBSY#

C1

DRDY#

E4

HITM#

C3

LOCK#

AD3

BINIT#

AB3

MCERR#

AE8

SKTOCC#

AJ7

THERMDA2

AH7

THERMDC2

AL1

THERMDA

AK1

THERMDC

AC2

DBR#

Y1

BOOTSELECT

AH2

TEST_BUS

AN7

VID_SELECT

AA2

LL_ID1

V2

LL_ID0

V1

MS_ID1

W1

MS_ID0

G29

BSEL0

H30

BSEL1

G30

BSEL2

B22

D63#

A22

D62#

A19

D61#

B19

D60#

B21

D59#

C21

D58#

B18

D57#

A17

D56#

B16

D55#

C18

D54#

FSB0_D53

ESB_SYS_RST# 40,54,67,68

FSB0_THERMTRIP_N 61

B15

D53#

FSB0_D52

C14

D52#

FSB0_D51

C15

D51#

A14

FSB0_D50

D50#

D17

FSB0_D49

FSB0_A35

D49#

FSB0_D48

AJ6

D20

A35#

D48#

FSB0_A33

FSB0_A34

AJ5

A34#

D47#

G22

FSB0_D46

FSB0_D47

AH5

D22

FSB0_A32

A33#

D46#

FSB0_D45

AH4

E22

FSB0_A31

A32#

D45#

FSB0_D44

AG5

G21

FSB0_A30

AG4

A31#

D44#

F21

FSB0_D43

FSB0_A29

AG6

A30#

D43#

E21

FSB0_D42

FSB0_A28

A29#

D42#

FSB0_D41

AF4

F20

FSB0_A27

AF5

A28#

D41#

E19

FSB0_D40

A27#

D40#

FSB0_A26

AB4

A26#

D39#

E18

FSB0_D39

FSB0_A25

AC5

A25#

D38#

F18

FSB0_D38

FSB0_A24

AB5

A24#

D37#

F17

FSB0_D37

FSB0_A23

AA5

A23#

D36#

G17

FSB0_D36

FSB0_A22

AD6

A22#

D35#

G18

FSB0_D35

FSB0_A21

FSB0_D34

FSB0_A19

AA4

A21#

A20#Y4A19#Y6A18#W6A17#

FSB0_A17

AB6

A16#W5A15#V4A14#V5A13#U4A12#U5A11#T4A10#

FSB0_A11

FSB0_A12

FSB0_A13

FSB0_A18

FSB0_A14

FSB0_A16

FSB0_A20

FSB0_A15

LGA771

PART 1

FSB Signal

D34#

D33#

D32#

D31#

D30#

D29#

D28#

D27#

D26#

D25#

D24#

F15

F14

FSB0_D30

G14

FSB0_D29

FSB0_D27

FSB0_D28

G13

E13

FSB0_D25

FSB0_D26

D13

F12

FSB0_D24

E16

E15

FSB0_D33

FSB0_D32

G16

G15

FSB0_D31

FSB0_A10

FSB0_A8

FSB0_A9

U6

A9#T5A8#R4A7#M4A6#L4A5#L5A4#P6A3#

D23#

D22#

D21#

F11

E10

D10

FSB0_D22

FSB0_D23

FSB0_D21

FSB0_A7

FSB0_A4

FSB0_A3

FSB0_A6

FSB0_A5

M5

D20#D7D19#E9D18#F9D17#F8D16#G9D15#

FSB0_D17

FSB0_D19

FSB0_D20

FSB0_D18

FSB0_D16

P0VID5

P0VID6

P0VID4

P0VID3

AM5

AL4

AK4

AL6

VID6

VID5

VID4

GTLREF_DATA_C1

GTLREF_ADD_C1

GTLREF_DATA_C0

GTLREF_ADD_C0

D7#A7D6#B7D5#B6D4#A5D3#C6D2#A4D1#C5D0#

FSB0_D5

FSB0_D7

FSB0_D2

FSB0_D3

FSB0_D4

FSB0_D1

FSB0_D6

R1273 0
R1274 0
R1275 0
R1276 0

P0VID1

P0VID0

P0VID2

AM3

AL5

AM2

VID3

VID2

VID1

VID0

BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#

REQ4#
REQ3#
REQ2#
REQ1#
REQ0#

TESTHI11
TESTHI10

TESTHI9
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0

BCLK1
BCLK0

RS2#
RS1#
RS0#

AP1#
AP0#
BR1#
BR0#

PWRGOOD

COMP7
COMP6
COMP5
COMP4
COMP3
COMP2
COMP1
COMP0

DP3#
DP2#
DP1#
DP0#

ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#

DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#

TEJAS

B4

FSB0_D0

CPU1A

CPU0_DISABLE_N54,65

P0_GTLREF_DATA1

F2

P0_GTLREF_ADD1

H2

P0_GTLREF_DATA0

G10

P0_GTLREF_ADD0

H1

FSB0_BPM_N5

AG3

FSB0_BPM_N4

AF2

FSB0_BPM_N3

AG2

FSB0_BPM_N2

AD2

FSB0_BPM_N1

AJ1

FSB0_BPM_N0

AJ2

FSB0_REQ_N4

J6

FSB0_REQ_N3

K6

FSB0_REQ_N2

M6

FSB0_REQ_N1

J5

FSB0_REQ_N0

K4

H_TESTHI11

L2

H_TESTHI10

P1

FSB0_BPMB_N2

G4

FSB0_BPMB_N3

G3
F24
G24
G26
G27
G25
F25
W3
F26

CK_H_P0_N

G28

CK_H_P0

F28

FSB0_RS2_N

A3

FSB0_RS1_N

F5

FSB0_RS0_N

B3

FSB0_AP1

U3

FSB0_AP0

U2

FSB0_BR_N1

H5

FSB0_BR_N0

F3

CPU_PWRGD

N1

H_COMP7

AE3

H_COMP6

Y3

H_COMP5

T2

H_COMP4

J2

H_COMP3

R1

H_COMP2

G2

H_COMP1

T1

H_COMP0

A13

FSB0_DP_N3

J17

FSB0_DP_N2

H16

FSB0_DP_N1

H15

FSB0_DP_N0

J16

FSB0_ADSTB_N1

AD5

FSB0_ADSTB_N0

R6

FSB0_DSTBP_N3

C17

FSB0_DSTBP_N2

G19

FSB0_DSTBP_N1

E12

FSB0_DSTBP_N0

B9

FSB0_DSTBN_N3

A16

FSB0_DSTBN_N2

G20

FSB0_DSTBN_N1

G12

FSB0_DSTBN_N0

C8

FSB_SMI#12,40,54

VCC0_SENSE 69

VSS0_SENSE 69

P0VID[6..0]
FSB0_BPM_N[5..0]
FSB0_REQ_N[4..0]
FSB0_DP_N[3..0]
FSB0_ADSTB_N[1..0]
FSB0_DSTBP_N[3..0]
FSB0_DSTBN_N[3..0]

R727 51
R728 51
R729 51
R730 51

H_TESTHI2

R731 51

H_TESTHI1

R732 51

CK_H_P0_N 58
CK_H_P0 58

FSB0_RS2_N 15
FSB0_RS1_N 15
FSB0_RS0_N 15

FSB0_AP1 15
FSB0_AP0 15
FSB0_BR_N1 15
FSB0_BR_N0 15
CPU_PWRGD 12,40,64

R705 49.9RST
R706 49.9RST
R734 49.9RST
R736 49.9RST
R737 49.9RST
R738 49.9RST
R739 49.9RST
R740 49.9RST

P_VTT

CPU0 SMI Voltage Translation

R1385
220

6
1

FSB0_BPMB_N2
FSB0_BPMB_N3

P_VTT

U3026

VCC

A
B4C
BE

GND

PI5C3303

P0VID[6..0] 69
FSB0_BPM_N[5..0] 15,64
FSB0_REQ_N[4..0] 15
FSB0_DP_N[3..0] 15
FSB0_ADSTB_N[1..0] 15
FSB0_DSTBP_N[3..0] 15
FSB0_DSTBN_N[3..0] 15

FSB0_BPMB_N2 64
FSB0_BPMB_N3 64

P_VTT

Place BPMB Termination Near CPU

P_VTT

Max Length 1.2 inches

C1033
X_0.1u

P_VTT

R3387
X_220

2
5
3

P5V

CPU0_SMI_N

49.9RST

100RST

49.9RST

100RST

BE=High, C=B

5

4

3

2

Processor 0 Termination

Place Termination Close to CPU At End of Bus

P_VTT

R713 51
R714 51
R715 51
R717 51
R718 51

R719 51

R716 X_51

R735 X_51
R1380 X_220
R1381 X_220
R1382 X_220
R1383 X_220
R1384 X_220

R1386 220
R1277 300

R3384 510
R3385 510
R3386 510

P3V3_AUX

R1219 4.7K

Place BPM Termination Near CPU

P_VTT

R721 51
R722 51
R723 51
R724 51

P0_LL_ID0
P0_LL_ID1

P0_MS_ID1
P0_MS_ID0

P_VTT

800mV at 1.2V FSB Vtt

Minmum trace and width as wide as possible
12 mils

R742

P0_GTLREF_ADD0

R743

C1034
1u

P_VTT

800mV at 1.2V FSB Vtt

Minmum trace and width as wide as possible

R744

12 mils

P0_GTLREF_ADD1

R751

C1037
1u

Micro Star Restricted Secret

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

RB1

0

C1035
220P

RB2

0

C1038
220P

P0 Intel LGA771 Signal

MS-9192

FSB0_BR_N1
FSB0_BR_N0
FSB0_GTL_IERR#
FSB0_THERMTRIP_N
FSB_FERR#

FSB0_RESET_N

FSB0_PROCHOT#
CPU0_BOOT
FSB_A20M#
FSB_STPCLK#
FSB_IGNNE#
FSB_INIT#
FSB_INTR

FSB_NMI
CPU_PWRGD

FSB0_BSEL0
FSB0_BSEL1
FSB0_BSEL2

CPU0_SKTOCC#

FSB0_BPM_N3
FSB0_BPM_N2
FSB0_BPM_N1
FSB0_BPM_N0

R1206
X_4.7K

R703 X_51
R704 X_51

P0_GTLREF_DATA0

C1036
220P

P0_GTLREF_DATA1

C1039
220P

Last Revision Date:

Friday, April 27, 2007

Sheet

990

1

P3V3

R1207
X_4.7K

of

Rev

0A

5

P0 Intel LGA771 Power

4

3

2

1

VCORE0

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCORE0

AF22

AF21

VCC

VCC

VCC

VCC

Y8

Y30

AF8

Y29

AF9

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCCU8VCCV8VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCCW8VCC

VCC

VCC

VCC

VCC

VCC

VCC

Y23

Y24

Y25

Y26

Y27

Y28

W30

W29

W28

W27

W26

W25

W24

W23

U25

U26

U27

U28

U29

U30

AH28

AH29

AH30

AH8

AH9

AJ11

AJ12

AJ14

AJ15

AJ18

AJ19

AJ21

AJ22

AJ25

AJ26

AJ8

AJ9

AK11

AK12

AK14

AK15

AK18

AK19

AK21

AK22

AK25

AK26

AK8

AK9

AL11

AL12

AL14

AL15

AL18

AL19

AL21

AL22

AL25

AL26

AL29

AL30

AL9

AM11

AM12

AM14

AM15

AM18

AM19

AM21

AM22

AM25

AM26

AM29

AM30

AM8

AM9

AN11

AN12

AN14

AN15

AN18

AN19

AN21

AN22

CPU1B

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCCIOPLL

LGA771

PART 2
Power

VTTPWRGD

VTT_OUT1
VTT_OUT0

VCC

VCC

NONE

NONE

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCCJ8VCCJ9VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCCK8VCCL8VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCCM8VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCCN8VCCP8VCCR8VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCCT8VCC

VCC

J10

J11

J12

J13

J14

J15

J18

J19

J20

J21

J22

J23

J24

J25

J26

J27

J28

J29

T30

U23

U24

N29

N30

N23

N24

N25

N26

N27

N28

M29

M30

M23

M24

M25

M26

M27

M28

K30

K29

K28

K27

K26

T23

T24

T25

T26

T27

T28

T29

K25

K24

K23

J30

AN8

AN9

AN25

AN26

AN29

AN30

VCCA
VSSA

VCCPLL

VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT

VTT_SEL

TEJAS

A23
B23
D23
C23

F30
E30
A25
A26
B25
B26
B27
B28
B29
B30
C25
C26
C27
C28
C29
C30
D25
D26
D27
D28
D29
D30

AM6
AA1
J1
F27

H0_VCCA
H0_VSSA
H0_VCCPLL

VTT_PWRGD

R3472 0

P_VTT

VTT_PWRGD 13,63

VTT_SELVTT_SEL0

Support
Harpertown

＆

Wolfdale

CPU

VTT_SEL 13,76

AH27

AH26

AH25

AH22

AH21

AH19

AH18

AH15

AH14

AH12

AH11

AG9

AG8

AG30

AG29

AG28

AG27

AG26

AG25

AG22

AG21

AG19

AG18

AG15

AG14

AG12

AG11

D D

VCORE0

AF19
AF18
AF15
AF14
AF12
AF11

AE9
AE23
AE22
AE21
AE19
AE18
AE15

C C

B B

AE14
AE12
AE11

AD8
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23

AC8
AC30
AC29
AC28
AC27
AC26
AC25
AC24
AC23

AB8

AA8

P_VTT

L17 10uH-0805-0.1A
L18 10uH-0805-0.1A

A A

5

Minmum trace and width as wide as possible
< 12 mils

C3128
22u-1206

P1V5

R62

0

C1020
103P

C3129
X_10u-1206

C1021

4.7u-0805

H0_VCCA

C1019
X_1u

H0_VSSA

H0_VCCPLL

C1022

4.7u-0805

4

P_VTT

C1029
10u-1206

C1030
10u-1206

3

C1031

0.1u

C1032

0.1u

P_VTT

C1025

0.1u

C1026

0.1u

C1027

0.1u

2

C1028

0.1u

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

P0 Intel LGA771 Power

Micro Star Restricted Secret

MS-9192

Last Revision Date:

Friday, April 27, 2007

Sheet

1

10 90

of

Rev

0A

5

P0 Intel LGA771 GND

4

3

2

1

R702

B13

RESVDF6RESVD

VSS

VSS

AF3

AF30

R702

X_49.9RST

P5

E1

RESVDJ3RESVDN4RESVD

RESVD

VSS

VSS

VSS

AF6

AF7

AG10

AG13

Nocona-T
Optional

VSS

AG16

D D

R555

C C

B B

X_0-0402

R1212

X_0

FSB0_BPMB_N1

F1
A12
A15
A18

A2
A21
A24

A6

A9

AA23
AA24
AA25
AA26
AA27
AA28
AA29

AA3

AA30

AA6
AA7

AB1
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30

AB7

AC3

AC6

AC7

AD4

AD7
AE10
AE13
AE16
AE17

AE2
AE20
AE24
AE25
AE26
AE27
AE28

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

D16

RESVDC9RESVD

VSS

VSS

AE29

AE30

A20

AE5

P0TESTIN

W2

RESVD

VSS

AE7

VSS

AC4

AE4

D14

E23

RESVD

VSS

VSS

AF24

AF25

F23

RESVDE5RESVDE6RESVDE7RESVD

VSS

VSS

VSS

AF26

AF27

AF28

AF29

VSS

E24

RESVD

RESVD

RESVDD1RESVD

RESVDG6RESVD

RESVDG5RESVD

VSS

VSS

VSS

VSS

VSS

VSS

AF10

AF13

AF16

AF17

AF20

AF23

Dempsey-T Dempsey/Woodcrest
Stuffed No Stuffed

AN27

AN6

RESVD

VSS

AG23

AJ3

RESVD

VSS

AG24

AK3

RESVD

VSS

AG7

F29

RESVD

VSS

AH1

AN28

NONE

NONE

VSS

VSS

VSS

AH10

AH13

AH16

VSSY7VSSY5VSSY2VSSW7VSSW4VSSV7VSSV6VSS

VSS

VSS

VSS

AH17

AH20

AH23

AE6

AN5

RESVDN5RESVD

RESVD

VSS

VSS

VSS

AG17

AG20

TP92

V30

V29

VSSV3VSS

V28

VSS

V27

VSS

V26

V25

VSS

P0TESTIN

V24

V23

VSS

VSS

VSS

VSSU7VSSU1VSST7VSST6VSST3VSSR7VSSR5VSS

R733 51

P_VTT

R30

R29

R28

R27

R26

R25

R24

R23

P30

P29

P28

P27

P26

P25

P24

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSSR2VSSP7VSSP4VSS

VSS

VSS

VSS

VSS

VSS

P23

VSS

VSS

VSSN7VSSN6VSSN3VSSM7VSSM1VSSL7VSSL6VSS

L30

L29

VSSL3VSS

L28

VSS

L27

VSS

L26

L25

VSS

LGA771

PART 3

GND

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

AJ4

AH3

AH6

AJ10

AJ13

AJ16

AJ17

AJ20

AJ23

AJ24

AJ27

AJ28

AJ29

AH24

AJ30

AK10

AK13

AK16

AK17

AK2

AK20

AK23

AK24

AK27

AK28

AK29

AK30

AK5

AK7

AL10

AL13

AL16

AL17

AL20

AL23

AL24

AL27

AL28

AL3

AM1

AM10

AM13

AM16

AM17

AM20

AM23

AN1

AM4

AM7

AN10

AM24

AM27

AN13

AM28

Place BPMB Termination Near CPU

R745 51

VSS

VSS

AN24

R746 51

VSSB5VSS

VSSB1VSS

B8

B11

B14

VSS

VSS

B17

P_VTTRSVD_PECI 14,55,66

L24

L23

VSS

VSS

VSS

VSSK7VSSK5VSSK2VSSJ7VSSJ4VSSH9VSSH8VSSH7VSSH6VSSH3VSS

VSS

VSS

VSS

VSS

VSS

AN2

AN16

AN17

AN20

AN23

H29

VSS

B20

H28

B24

H27

VSS

VSS

FSB0_BPMB_N1
FSB0_BPMB_N0

H26

H25

H24

VSS

VSS

VSS

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSC4VSS

TEJAS

C7

CPU1C

H23
H22
H21
H20
H19
H18
H17
H14
H13
H12
H11
H10
G1
F7
F4
F22
F19
F16
F13
F10
E8
E29
E28
E27
E26
E25
E20
E2
E17
E14
E11
D9
D6
D5
D3
D24
D21
D18
D15
D12
C24
C22
C19
C16
C13
C10

FSB0_BPMB_N1 64
FSB0_BPMB_N0 64

FSB0_BPMB_N0

R556
X_0-0402

A A

Intel Document Title: Enterprise System Design Conference - Taipei
REV. NO. 1.0 REF, NO. 19091

Page 142: For each Socket change new RSVD lands A24 and E29
Page 142: Connect W2 and U1 together on each Socket,

from VSS to no-connects on the motherboard

and terminate with a 51ohms resistor to VTT.

5

4

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

3

2

http://www.msi.com.tw

P0 Intel LGA771 GND

MS-9192

Last Revision Date:

Friday, April 27, 2007

Sheet

1

11 90

Rev

0A

of

Micro Star Restricted Secret

5

4

3

2

1

P1 Intel LGA771 Signal

VCC1_SENSE2

D11

FSB1_D15

FSB1_D14

D14#

C12

AL8

VCC_DIE_SENSE2

D13#

B12

FSB1_D12

FSB1_D13

AL7

AN3

VCC_DIE_SENSE

VSS_DIE_SENSE2

D12#D8D11#

C11

FSB1_D11

VSS1_SENSE2
VCC1_SENSE1
VSS1_SENSE1

AN4

VSS_DIE_SENSE

D10#

D9#

B10

A11

FSB1_D10

FSB1_D9

FSB1_A[35..3]16

FSB1_DBI#[3..0]16

FSB1_D[63..0]16

D D

FSB1_FORCEPR#71

C C

FSB1_GTL_IERR#62
FSB1_PROCHOT#65

B B

A A

FSB1_A[35..3]
FSB1_DBI#[3..0]
FSB1_D[63..0]

FSB1_A29

A30#

D43#

FSB1_D42

AG6

E21

FSB1_A28

AF4

A29#

D42#

F20

FSB1_D41

A28#

D41#

FSB1_A27

AF5

A27#

D40#

E19

FSB1_D40

FSB1_A26

AB4

A26#

D39#

E18

FSB1_D39

FSB1_A25

AC5

A25#

D38#

F18

FSB1_D38

FSB1_A24

AB5

A24#

D37#

F17

FSB1_D37

FSB1_A23

AA5

A23#

D36#

G17

FSB1_D36

FSB1_A22

FSB1_D35

FSB1_A15

FSB1_A18

FSB1_A14

FSB1_A20

AD6

AA4

A22#

A21#

FSB1_A17

FSB1_A19

AB6

A20#Y4A19#Y6A18#W6A17#

FSB1_A13

FSB1_A12

FSB1_A16

A16#W5A15#V4A14#V5A13#U4A12#U5A11#T4A10#

LGA771

PART 1

FSB Signal

D35#

D34#

D33#

D32#

D31#

D30#

D29#

D28#

D27#

D26#

F15

F14

E16

G18

FSB1_D33

FSB1_D34

E15

G16

FSB1_D32

G15

FSB1_D31

FSB1_D30

G14

FSB1_D29

FSB1_D28

G13

FSB1_D26

FSB1_D27

E13

D13

FSB1_D25

FSB1_A33

FSB1_A31

FSB1_A30

FSB1_A32

FSB1_A34

FSB1_A35

AJ6

AJ5

AH5

AH4

AG5

AG4

A35#

A34#

A33#

A32#

D50#

D49#

D48#

D47#

D46#

A14

E22

D17

D20

D22

G22

FSB1_D47

FSB1_D46

FSB1_D48

FSB1_D49

FSB1_D45

FSB1_THERMTRIP_N 61

D45#

G21

FSB1_D44

A31#

D44#

F21

FSB1_D43

FSB1_DBI#0
FSB1_DBI#1
FSB1_DBI#2
FSB1_DBI#3

FSB1_RESET_N16,64

FSB1_RSP_N16

FSB1_BPRI_N16

FSB1_TRDY_N16

FSB1_DEFER_N16

FSB_A20M#9,40

FSB_NMI9,40
FSB_INTR9,40

FSB_IGNNE#9,40

FSB_STPCLK#9,40

FSB_INIT#9,40,67

XDP0_TCK09,64

XDP0_TDI_FSB164
XDP0_TDO_FSB164
XDP0_TMS_MAIN9,20,64

XDP0_TRST#9,20,64

FSB_FERR#9,40

FSB1_ADS_N16
FSB1_BNR_N16

FSB1_HIT_N16 CK_H_P1_N 58

FSB1_DBSY_N16

FSB1_DRDY_N16

FSB1_HITM_N16

FSB1_LOCK_N16

FSB1_BINIT_N16

FSB1_MCERR_N16

CPU1_SKTOCC#54,63,65

P1THERMDA265
P1THERMDC265

P1THERMDA65

P1THERMDC65

CPU_DBR_RST#9,64

CPU1_TESTBUS9

FSB1_VIDSEL63,71

P1_MS_ID163
P1_MS_ID063

FSB1_BSEL062
FSB1_BSEL162
FSB1_BSEL262

FSB1_RESET_N
FSB1_RSP_N
FSB1_BPRI_N
FSB1_TRDY_N
FSB1_DEFER_N

CPU1_SMI_N
FSB_A20M#
FSB1_FORCEPR#
FSB_NMI
FSB_INTR
FSB_IGNNE#
FSB_STPCLK#
FSB_INIT#

XDP0_TCK0
XDP0_TDI_FSB1
XDP0_TDO_FSB1
XDP0_TMS_MAIN
XDP0_TRST#

FSB1_GTL_IERR#
FSB_FERR#
FSB1_PROCHOT#

P1_THERMTRIP_N

FSB1_ADS_N
FSB1_BNR_N
FSB1_HIT_N
FSB1_DBSY_N
FSB1_DRDY_N
FSB1_HITM_N
FSB1_LOCK_N
FSB1_BINIT_N
FSB1_MCERR_N

CPU1_SKTOCC#
P1THERMDA2
P1THERMDC2
P1THERMDA
P1THERMDC

CPU_DBR_RST#
CPU1_BOOT

CPU1_TESTBUS

P1_LL_ID1
P1_LL_ID0
P1_MS_ID1
P1_MS_ID0

FSB1_BSEL0
FSB1_BSEL1
FSB1_BSEL2

FSB1_D63
FSB1_D62
FSB1_D61
FSB1_D60
FSB1_D59
FSB1_D58
FSB1_D57
FSB1_D56
FSB1_D55
FSB1_D54

P1_THERMTRIP_N

A8
G11
D19
C20

G23

H4

G8

E3

G7

P2

K3
AK6

L1
K1
N2

M3

P3

AE1
AD1
AF1
AC1
AG1

AB2

R3

AL2

M2

D2
C2
D4
B2
C1
E4
C3

AD3
AB3

AE8
AJ7
AH7
AL1
AK1

AC2

Y1

AH2
AN7

AA2

V2
V1

W1

G29
H30
G30

B22
A22
A19
B19
B21
C21
B18
A17
B16
C18

R674 2.2

DBI0#
DBI1#
DBI2#
DBI3#

RESET#
RSP#
BPRI#
TRDY#
DEFER#

SMI#
A20M#
FORCEPR#
LINT1/NMI
LINT0/INTR
IGNNE#
STPCLK#
INIT#

TCK
TDI
TDO
TMS
TRST#

IERR#
FERR#/PBE#
PROCHOT#
THERMTRIP#

ADS#
BNR#
HIT#
DBSY#
DRDY#
HITM#
LOCK#
BINIT#
MCERR#

SKTOCC#
THERMDA2
THERMDC2
THERMDA
THERMDC

DBR#
BOOTSELECT

TEST_BUS
VID_SELECT

LL_ID1
LL_ID0
MS_ID1
MS_ID0

BSEL0
BSEL1
BSEL2

D63#
D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#

D53#

B15

FSB1_D53

D52#

C14

FSB1_D52

D51#

C15

FSB1_D51

FSB1_D50

FSB1_A21

FSB1_A11

D25#

FSB1_D24

U6

D24#

F12

F11

FSB1_D23 FSB1_A10

FSB1_A7

FSB1_A6

FSB1_A9

FSB1_A8

A9#T5A8#R4A7#M4A6#L4A5#L5A4#P6A3#

D23#

D22#

D21#

D20#D7D19#E9D18#F9D17#F8D16#G9D15#

E10

D10

FSB1_D19

FSB1_D20

FSB1_D21

FSB1_D22

FSB1_A5

FSB1_D18

FSB1_A4

FSB1_D17

FSB1_A3

M5

FSB1_D16

P1VID6

P1VID5

AM5

AL4

VID6

GTLREF_DATA_C1

GTLREF_ADD_C1

GTLREF_DATA_C0

GTLREF_ADD_C0

D8#

D7#A7D6#B7D5#B6D4#A5D3#C6D2#A4D1#C5D0#

A10

FSB1_D4

FSB1_D3

FSB1_D8

FSB1_D6

FSB1_D5

FSB1_D7

R1269 0
R1270 0
R1271 0
R1272 0

P1VID3

P1VID2

P1VID4

AK4

AL6

VID5

VID4

VID3

PWRGOOD

FSB1_D0

FSB1_D2

FSB1_D1

P1VID1

P1VID0

AM3

AL5

AM2

VID2

VID1

BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#

REQ4#
REQ3#
REQ2#
REQ1#
REQ0#

TESTHI11
TESTHI10

TESTHI9
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0

BCLK1
BCLK0

RS2#
RS1#
RS0#

AP1#
AP0#
BR1#
BR0#

COMP7
COMP6
COMP5
COMP4
COMP3
COMP2
COMP1
COMP0

DP3#
DP2#
DP1#
DP0#

ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#

DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#

B4

CPU2A

VID0

TEJAS

F2
H2
G10
H1

AG3
AF2
AG2
AD2
AJ1
AJ2

J6
K6
M6
J5
K4

L2
P1
G4
G3
F24
G24
G26
G27
G25
F25
W3
F26

G28
F28

A3
F5
B3

U3
U2
H5
F3

N1
AE3
Y3
T2
J2
R1
G2
T1
A13

J17
H16
H15
J16

AD5
R6
C17
G19
E12
B9
A16
G20
G12
C8

CPU1_DISABLE_N54,65

P1_GTLREF_DATA1
P1_GTLREF_ADD1
P1_GTLREF_DATA0
P1_GTLREF_ADD0

FSB1_BPM_N5
FSB1_BPM_N4
FSB1_BPM_N3
FSB1_BPM_N2
FSB1_BPM_N1
FSB1_BPM_N0

FSB1_REQ_N4
FSB1_REQ_N3
FSB1_REQ_N2
FSB1_REQ_N1
FSB1_REQ_N0

FSB1_TESTHI11
FSB1_TESTHI10
FSB1_BPMB_N2
FSB1_BPMB_N3

FSB1_TESTHI2
FSB1_TESTHI1

CK_H_P1_N
CK_H_P1

FSB1_RS2_N
FSB1_RS1_N
FSB1_RS0_N

FSB1_AP1
FSB1_AP0
FSB1_BR_N1
FSB1_BR_N0

H1_COMP7
H1_COMP6
H1_COMP5
H1_COMP4
H1_COMP3
H1_COMP2
H1_COMP1
H1_COMP0

FSB1_DP_N3
FSB1_DP_N2
FSB1_DP_N1
FSB1_DP_N0

FSB1_ADSTB_N1
FSB1_ADSTB_N0
FSB1_DSTBP_N3
FSB1_DSTBP_N2
FSB1_DSTBP_N1
FSB1_DSTBP_N0
FSB1_DSTBN_N3
FSB1_DSTBN_N2
FSB1_DSTBN_N1
FSB1_DSTBN_N0

FSB_SMI#9,40,54

VCC1_SENSE 71

VSS1_SENSE 71

P1VID[6..0]
FSB1_BPM_N[5..0]
FSB1_REQ_N[4..0]
FSB1_DP_N[3..0]
FSB1_ADSTB_N[1..0]
FSB1_DSTBP_N[3..0]
FSB1_DSTBN_N[3..0]

FSB1_BPMB_N2
FSB1_BPMB_N3

R681 51
R682 51
R683 51
R684 51

R685 51
R686 51

CK_H_P1 58
FSB1_RS2_N 16

FSB1_RS1_N 16
FSB1_RS0_N 16

FSB1_AP1 16
FSB1_AP0 16
FSB1_BR_N1 16
FSB1_BR_N0 16
CPU_PWRGD 9,40,64

R658 49.9RST
R657 49.9RST
R688 49.9RST
R690 49.9RST
R691 49.9RST
R692 49.9RST
R693 49.9RST
R694 49.9RST

P_VTT

P_VTT

Place BPMB Termination Near CPU

P_VTT

CPU1 SMI Voltage Translation

U3027

A
B4C
BE

PI5C3303

VCC

GND

2
5
3

6
1

P1VID[6..0] 71
FSB1_BPM_N[5..0] 16,64
FSB1_REQ_N[4..0] 16
FSB1_DP_N[3..0] 16
FSB1_ADSTB_N[1..0] 16
FSB1_DSTBP_N[3..0] 16
FSB1_DSTBN_N[3..0] 16

FSB1_BPMB_N2 64
FSB1_BPMB_N3 64

Max Length 1.2 inches

C1012
X_0.1u

P_VTT

P5V

CPU1_SMI_N

R3391
X_220

49.9RST

100RST

49.9RST

100RST

BE=High, C=B

5

4

3

2

Processor 1 Termination

Place Termination Close to CPU At End of Bus

P_VTT

R673 51
R670 51
R672 51
R669 51
R671 51

R668 X_51
R689 X_51

R3388 510
R3389 510
R3390 510

P3V3_AUX

R1218 4.7K

Place BPM Termination Near CPU

P_VTT

R675 51
R676 51
R677 51
R678 51

P1_LL_ID0
P1_LL_ID1

P1_MS_ID1
P1_MS_ID0

P_VTT

800mV at 1.2V FSB Vtt

Minmum trace and width as wide as possible

R696

12 mils

P1_GTLREF_ADD0

R697

C1013
1u

P_VTT

800mV at 1.2V FSB Vtt

Minmum trace and width as wide as possible
12 mils

R698

P1_GTLREF_ADD1

R701

C1016
1u

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

R1196

C1014
220P

R699

C1017
220P

Micro Star Restricted Secret

P1 Intel LGA771 Signal

FSB1_BR_N1
FSB1_BR_N0
FSB1_GTL_IERR#
FSB1_THERMTRIP_N
FSB1_RESET_N

FSB1_PROCHOT#
CPU1_BOOT

FSB1_BSEL0
FSB1_BSEL1
FSB1_BSEL2

CPU1_SKTOCC#

FSB1_BPM_N3
FSB1_BPM_N2
FSB1_BPM_N1
FSB1_BPM_N0

R1194
X_4.7K

R655 X_51
R656 X_51

0

0

MS-9192

Last Revision Date:

Friday, April 27, 2007

Sheet

1

P3V3

R1195
X_4.7K

P1_GTLREF_DATA0

C1015
220P

P1_GTLREF_DATA1

C1018
220P

of

12 90

Rev

0A

5

4

3

2

1

P1 Intel LGA771 Power

VCORE1

D D

AH27

AH26

AH25

AH22

AH21

AH19

AH18

AH15

AH14

AH12

AH11

AG9

AG8

AG30

AG29

AG28

AG27

AG26

AG25

AG22

AG21

AG19

AG18

AG15

AG14

AG12

AG11

AF9

AF8

AF22

AF21

VCORE1

AF19
AF18
AF15
AF14
AF12
AF11

AE9
AE23
AE22
AE21
AE19
AE18
AE15
AE14

C C

B B

AE12
AE11

AD8
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23

AC8
AC30
AC29
AC28
AC27
AC26
AC25
AC24
AC23

AB8

AA8

VCORE1

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCC

VCC

VCC

VCC

Y8

Y30

Y29

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

Y24

Y25

Y26

Y27

Y28

Y23

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCCW8VCC

W26

W27

W28

W29

W30

VCC

VCC

VCC

VCC

VCC

VCC

VCCU8VCCV8VCC

VCC

VCC

VCC

U30

W23

W24

W25

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

U25

U26

U27

U28

U29

AH28

AH29

AH30

AH8

AH9

AJ11

AJ12

AJ14

AJ15

AJ18

AJ19

AJ21

AJ22

AJ25

AJ26

AJ8

AJ9

AK11

AK12

AK14

AK15

AK18

AK19

AK21

AK22

AK25

AK26

AK8

AK9

AL11

AL12

AL14

AL15

AL18

AL19

AL21

AL22

AL25

AL26

AL29

AL30

AL9

AM11

AM12

AM14

AM15

AM18

AM19

AM21

AM22

AM25

AM26

AM29

AM30

AM8

AM9

AN11

AN12

AN14

AN15

AN18

AN19

AN21

AN22

CPU2B

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

LGA771

PART 2
Power

VCC

VCCA
VSSA

VCCPLL

VCCIOPLL

VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT

VTTPWRGD

VTT_OUT1
VTT_OUT0

VTT_SEL

A23
B23
D23
C23

F30
E30
A25
A26
B25
B26
B27
B28
B29
B30
C25
C26
C27
C28
C29
C30
D25
D26
D27
D28
D29
D30

AM6
AA1
J1
F27

H1_VCCA
H1_VSSA
H1_VCCPLL

P_VTT

VTT_PWRGD

VTT_SEL1 VTT_SEL

R3473 0

VTT_PWRGD 10,63

VTT_SEL 10,76

Support

VCC

J10

J11

J12

J13

J14

J15

J18

J19

J20

J21

J22

J23

J24

J25

J26

J27

J28

J29

T30

U23

U24

N29

N30

N23

N24

N25

N26

N27

N28

M29

M30

M23

M24

M25

M26

M27

M28

K30

K29

K28

K27

K26

T23

T24

T25

T26

T27

T28

T29

K25

K24

K23

J30

AN8

AN9

AN25

AN26

TEJAS

AN29

AN30

VCC

VCC

NONE

NONE

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCCJ8VCCJ9VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCCK8VCCL8VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCCM8VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCCN8VCCP8VCCR8VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCCT8VCC

Harpertown

＆

Wolfdale

CPU

P_VTT

L15 10uH-0805-0.1A
L16 10uH-0805-0.1A

A A

5

Minmum trace and width as wide as possible
< 12 mils

C3130
22u-1206

P1V5

R55

0

C999
103P

4

C3131
X_10u-1206

C1000

4.7u-0805

H1_VCCA

C998
X_1u

H1_VSSA

H1_VCCPLL

C1001

4.7u-0805

P_VTT

C1008
10u-1206

3

C1009
10u-1206

C1010

0.1u

C1011

0.1u

P_VTT

C1004

0.1u

2

C1005

0.1u

C1006

0.1u

C1007

0.1u

Micro Star Restricted Secret

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

P1 Intel LGA771 Power

MS-9192

Last Revision Date:

Friday, April 27, 2007

Sheet

1

13 90

of

Rev

0A

5

P1 Intel LGA771 GND

4

3

2

1

R654

R654

X_49.9RST

E1

RESVDJ3RESVDN4RESVD

RESVD

VSS

VSS

VSS

AF6

AF7

VSS

AG10

P5

AG13

Nocona-T
Optional

AE6

RESVDN5RESVD

VSS

VSS

AG16

AG17

VSS

A20

AE5

P1TESTIN

W2

RESVD

VSS

AE7

VSS

RESVDG5RESVD

VSS

AF10

RSVD_PECI 11,55,66

AC4

AE4

D14

E24

VSS

AF13

E23

RESVD

RESVD

RESVDD1RESVD

RESVD

RESVDG6RESVD

VSS

VSS

VSS

VSS

VSS

VSS

AF16

AF17

AF20

AF23

AF24

AF25

AF26

F23

RESVDE5RESVDE6RESVDE7RESVD

RESVDF6RESVD

VSS

VSS

VSS

VSS

VSS

AF3

AF27

AF28

AF29

B13

AF30

D D

FSB1_BPMB_N1

D16

F1

VSS

A12
A15
A18

A21
A24

R567

C C

B B

X_0-0402

AA23
AA24
AA25
AA26
AA27
AA28
AA29

AA3

AA30

AA6
AA7
AB1

AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30

AB7
AC3
AC6
AC7
AD4
AD7

AE10
AE13
AE16
AE17

AE2

AE20
AE24
AE25
AE26
AE27
AE28

RESVDC9RESVD
VSS
VSS
VSS

A2

VSS
VSS
VSS

A6

VSS

A9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

AE29

AE30

Dempsey-T Dempsey/Woodcrest
Stuffed No Stuffed

AN27

AN6

RESVD

VSS

AG23

AJ3

RESVD

VSS

AG24

AK3

AG7

F29

RESVD

RESVD

VSS

VSS

AH1

AN28

NONE

NONE

VSS

VSS

VSS

AH10

AH13

AH16

VSSY7VSSY5VSSY2VSSW7VSSW4VSSV7VSSV6VSS

VSS

VSS

VSS

VSS

AH3

AH17

AH20

AH23

AH24

VSS

AN5

RESVD

VSS

AG20

VSS

V30

V29

V28

VSSV3VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

AH6

AJ10

AJ13

AJ16

AJ17

AJ20

AJ23

TP101

R741 51

P1TESTIN

V27

V26

V25

V24

V23

VSS

VSS

VSS

VSS

VSS

VSSU7VSSU1VSST7VSST6VSST3VSSR7VSSR5VSS

LGA771

PART 3

GND

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

AJ4

AJ24

AJ27

AJ28

AJ29

AJ30

AK10

AK13

AK16

AK17

AK2

VSS

VSS

AK20

R30

VSS

AK23

R29

VSS

VSS

AK24

R28

VSS

VSS

AK27

R27

VSS

VSS

AK28

P_VTT

R26

R25

VSS

VSS

AK29

AK30

R24

VSS

VSS

AK5

VSS

VSS

R23

AK7

VSS

VSS

AL10

P30

VSSR2VSSP7VSSP4VSS

VSS

VSS

VSS

VSS

AL13

AL16

AL17

P29

VSS

VSS

AL20

P28

VSS

VSS

AL23

P27

VSS

VSS

AL24

P26

VSS

VSS

AL27

P25

VSS

VSS

AL28

P24

VSS

VSS

AL3

P23

VSS

VSSN7VSSN6VSSN3VSSM7VSSM1VSSL7VSSL6VSS

VSS

VSS

VSS

VSS

VSS

VSS

AM1

AM10

AM13

AM16

AM17

AM20

AM23

VSS

L30

L29

VSSL3VSS

VSS

VSS

VSS

VSS

AM4

AM24

AM27

AM28

Place BPMB Termination Near CPU

R747 51
R748 51

L23

VSS

VSSK7VSSK5VSSK2VSSJ7VSSJ4VSSH9VSSH8VSSH7VSSH6VSSH3VSS

VSS

VSSB5VSS

VSS

VSS

VSS

VSSB1VSS

B8

AN20

AN23

AN24

VSS

AN2

AN17

L28

AM7

P_VTT

L27

VSS

VSS

AN1

VSS

VSS

L26

AN10

VSS

VSS

L25

AN13

VSS

VSS

L24

VSS

VSS

AN16

B11

B14

VSS

VSS

B17

FSB1_BPMB_N1
FSB1_BPMB_N0

H29

H28

H27

H26

VSS

VSS

VSS

VSS

VSS

VSSC4VSS

C7

B20

B24

H25

H24

VSS

TEJAS

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

CPU2C

H23
H22
H21
H20
H19
H18
H17
H14
H13
H12
H11
H10
G1
F7
F4
F22
F19
F16
F13
F10
E8
E29
E28
E27
E26
E25
E20
E2
E17
E14
E11
D9
D6
D5
D3
D24
D21
D18
D15
D12
C24
C22
C19
C16
C13
C10

FSB1_BPMB_N1 64
FSB1_BPMB_N0 64

FSB1_BPMB_N0

R568
X_0-0402

A A

Intel Document Title: Enterprise System Design Conference - Taipei
REV. NO. 1.0 REF, NO. 19091

Page 142: For each Socket change new RSVD lands A24 and E29
Page 142: Connect W2 and U1 together on each Socket,

from VSS to no-connects on the motherboard

and terminate with a 51ohms resistor to VTT.

5

4

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

3

2

http://www.msi.com.tw

P1 Intel LGA771 GND

MS-9192

Last Revision Date:

Friday, April 27, 2007

Sheet

1

14 90

Rev

0A

of

Micro Star Restricted Secret

5

4

3

2

1

Blackford FSB0

FSB0_D63
FSB0_D62
FSB0_D61
FSB0_D60

D D

C C

B B

A A

FSB0_D[63..0]9

FSB0_DBI#[3..0]9
FSB0_DSTBP_N[3..0]9
FSB0_DSTBN_N[3..0]9

5

FSB0_D[63..0]
FSB0_DBI#[3..0]
FSB0_DSTBP_N[3..0]
FSB0_DSTBN_N[3..0]

CK_H_MCH58

CK_H_MCH_N58

4

FSB0_D59
FSB0_D58
FSB0_D57
FSB0_D56
FSB0_D55
FSB0_D54
FSB0_D53
FSB0_D52
FSB0_D51
FSB0_D50
FSB0_D49
FSB0_D48
FSB0_D47
FSB0_D46
FSB0_D45
FSB0_D44
FSB0_D43
FSB0_D42
FSB0_D41
FSB0_D40
FSB0_D39
FSB0_D38
FSB0_D37
FSB0_D36
FSB0_D35
FSB0_D34
FSB0_D33
FSB0_D32
FSB0_D31
FSB0_D30
FSB0_D29
FSB0_D28
FSB0_D27
FSB0_D26
FSB0_D25
FSB0_D24
FSB0_D23
FSB0_D22
FSB0_D21
FSB0_D20
FSB0_D19
FSB0_D18
FSB0_D17
FSB0_D16
FSB0_D15
FSB0_D14
FSB0_D13
FSB0_D12
FSB0_D11
FSB0_D10
FSB0_D9
FSB0_D8
FSB0_D7
FSB0_D6
FSB0_D5
FSB0_D4
FSB0_D3
FSB0_D2
FSB0_D1
FSB0_D0

FSB0_DBI#3
FSB0_DBI#2
FSB0_DBI#1
FSB0_DBI#0

FSB0_DSTBP_N3
FSB0_DSTBP_N2
FSB0_DSTBP_N1
FSB0_DSTBP_N0

FSB0_DSTBN_N3
FSB0_DSTBN_N2
FSB0_DSTBN_N1
FSB0_DSTBN_N0

CK_H_MCH
CK_H_MCH_N

AE37
AE36
AH36
AG36

AF38
AE38
AH38

AJ38

AJ37
AG35
AK36

AL37

AL36

AL38

AJ34

AF37
AE28
AD29

AF28
AC31
AE29
AC30
AD30
AE31
AE32
AD35

AF33
AG32

AF31
AE34
AG30
AG33
AM37
AK35
AM34
AM38
AP38
AN36

AL35
AN35
AP36

AT37
AU36
AP34

AT36
AP35

AL34
AN33

AJ33
AG27
AG29
AM33
AH31

AJ30
AH32

AJ31

AL31
AK30
AN32
AH29
AK29
AH28

AL29

AJ28
AH37

AF30
AP37

AL32
AH35

AD33
AR38
AK33

AH34
AD32
AR37
AK32

AN17
AP17

BLACKFORD 4/11

FSB0_D63
FSB0_D62
FSB0_D61
FSB0_D60
FSB0_D59
FSB0_D58
FSB0_D57
FSB0_D56
FSB0_D55
FSB0_D54
FSB0_D53
FSB0_D52
FSB0_D51
FSB0_D50
FSB0_D49
FSB0_D48
FSB0_D47
FSB0_D46
FSB0_D45
FSB0_D44
FSB0_D43
FSB0_D42
FSB0_D41
FSB0_D40
FSB0_D39
FSB0_D38
FSB0_D37
FSB0_D36
FSB0_D35
FSB0_D34
FSB0_D33
FSB0_D32
FSB0_D31
FSB0_D30
FSB0_D29
FSB0_D28
FSB0_D27
FSB0_D26
FSB0_D25
FSB0_D24
FSB0_D23
FSB0_D22
FSB0_D21
FSB0_D20
FSB0_D19
FSB0_D18
FSB0_D17
FSB0_D16
FSB0_D15
FSB0_D14
FSB0_D13
FSB0_D12
FSB0_D11
FSB0_D10
FSB0_D9
FSB0_D8
FSB0_D7
FSB0_D6
FSB0_D5
FSB0_D4
FSB0_D3
FSB0_D2
FSB0_D1
FSB0_D0

FSB0_DBI3
FSB0_DBI2
FSB0_DBI1
FSB0_DBI0

FSB0_DSTBP3
FSB0_DSTBP2
FSB0_DSTBP1
FSB0_DSTBP0

FSB0_DSTBN3
FSB0_DSTBN2
FSB0_DSTBN1
FSB0_DSTBN0

CORECLKP
CORECLKN

FSB 0

U45D

FSB0_A35
FSB0_A34
FSB0_A33
FSB0_A32
FSB0_A31
FSB0_A30
FSB0_A29
FSB0_A28
FSB0_A27
FSB0_A26
FSB0_A25
FSB0_A24
FSB0_A23
FSB0_A22
FSB0_A21
FSB0_A20
FSB0_A19
FSB0_A18
FSB0_A17
FSB0_A16
FSB0_A15
FSB0_A14
FSB0_A13
FSB0_A12
FSB0_A11
FSB0_A10

FSB0_A9
FSB0_A8
FSB0_A7
FSB0_A6
FSB0_A5
FSB0_A4
FSB0_A3

FSB0_REQ4
FSB0_REQ3
FSB0_REQ2
FSB0_REQ1
FSB0_REQ0

FSB0_ADSTB1
FSB0_ADSTB0

FSB0_BPRI_N
FSB0_DEFER_N
FSB0_RESET_N

FSB0_RS2
FSB0_RS1
FSB0_RS0

FSB0_RSP_N

FSB0_TRDY_N

FSB0_ADS_N

FSB0_AP1
FSB0_AP0

FSB0_BINIT_N

FSB0_BNR_N

FSB0_BPM5

FSB0_BPM4
FSB0_BREQ1
FSB0_BREQ0

FSB0_DBSY_N

FSB0_DP3
FSB0_DP2
FSB0_DP1
FSB0_DP0

FSB0_DRDY_N

FSB0_HIT_N

FSB0_HITM_N

FSB0_LOCK_N

FSB0_MCERR_N

PSEL2
PSEL1
PSEL0

FSB0_VREF

FSB0_VREF

FSB0_VREF

BLACKFORD G1

3

AV22
AU22
AR22
AP22
AV24
AT23
AU23
AV25
AT24
AR25
AU26
AT26
AT27
AU25
AU28
AR24
AR27
AP25
AV28
AF22
AG23
AF25
AH22
AL22
AJ22
AG24
AM22
AH23
AP26
AN26
AM25
AN24
AL25

AJ25
AJ24
AK24
AH25
AL26

AP23
AL23

AU34
AV34
AN30
AU31
AL28
AV31
AN27
AT32

AU29
AK26
AH26
AK27
AV30
AP29
AR28
AG26
AM28
AR30
AN29
AP31
AT33
AR31
AT29
AU32
AV33
AT30
AJ27

AB1
AB2
AC1

AF34
AM30
AM27

FSB0_A35
FSB0_A34
FSB0_A33
FSB0_A32
FSB0_A31
FSB0_A30
FSB0_A29
FSB0_A28
FSB0_A27
FSB0_A26
FSB0_A25
FSB0_A24
FSB0_A23
FSB0_A22
FSB0_A21
FSB0_A20
FSB0_A19
FSB0_A18
FSB0_A17
FSB0_A16
FSB0_A15
FSB0_A14
FSB0_A13
FSB0_A12
FSB0_A11
FSB0_A10
FSB0_A9
FSB0_A8
FSB0_A7
FSB0_A6
FSB0_A5
FSB0_A4
FSB0_A3

FSB0_REQ_N4
FSB0_REQ_N3
FSB0_REQ_N2
FSB0_REQ_N1
FSB0_REQ_N0

FSB0_ADSTB_N1
FSB0_ADSTB_N0

FSB0_BPRI_N
FSB0_DEFER_N
FSB0_RESET_N
FSB0_RS2_N
FSB0_RS1_N
FSB0_RS0_N
FSB0_RSP_N
FSB0_TRDY_N

FSB0_ADS_N
FSB0_AP1
FSB0_AP0
FSB0_BINIT_N
FSB0_BNR_N
FSB0_BPM_N5
FSB0_BPM_N4
FSB0_BR_N1
FSB0_BR_N0
FSB0_DBSY_N
FSB0_DP_N3
FSB0_DP_N2
FSB0_DP_N1
FSB0_DP_N0
FSB0_DRDY_N
FSB0_HIT_N
FSB0_HITM_N
FSB0_LOCK_N
FSB0_MCERR_N

MCH_SEL2
MCH_SEL1
MCH_SEL0

FSB0_VREF

FSB0_BPRI_N 9
FSB0_DEFER_N 9
FSB0_RESET_N 9
FSB0_RS2_N 9
FSB0_RS1_N 9
FSB0_RS0_N 9
FSB0_RSP_N 9
FSB0_TRDY_N 9

FSB0_ADS_N 9

FSB0_BINIT_N 9
FSB0_BNR_N 9

FSB0_DBSY_N 9

FSB0_DRDY_N 9
FSB0_HIT_N 9
FSB0_HITM_N 9
FSB0_LOCK_N 9
FSB0_MCERR_N 9

MCH_SEL2 62
MCH_SEL1 62
MCH_SEL0 62

FSB0_A[35..3]
FSB0_REQ_N[4..0]
FSB0_ADSTB_N[1..0]
FSB0_AP[1..0]
FSB0_BPM_N[5..0]
FSB0_BR_N[1..0]
FSB0_DP_N[3..0]

FSB0_A[35..3] 9
FSB0_REQ_N[4..0] 9
FSB0_ADSTB_N[1..0] 9
FSB0_AP[1..0] 9
FSB0_BPM_N[5..0] 9,64
FSB0_BR_N[1..0] 9
FSB0_DP_N[3..0] 9

MCH FSB0 VREF CKTS

800mV at 1.2V FSB Vtt

P_VTT

2

Minmum trace and width as wide as possible
12 mils

R646

49.9RST

R651
100RST

C988
1u

R1267

0

C989
220P

Micro Star Restricted Secret

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

Blackford FSB0

MS-9192

Last Revision Date:

Friday, April 27, 2007

Sheet

1

FSB0_VREF

C990
220P

15 90

of

Rev

0A

5

Blackford FSB1

FSB1_D[63..0]12

D D

C C

MCH_FSB_SLWCTRL#63

FSB1_DBI#[3..0]12
FSB1_DSTBP_N[3..0]12
FSB1_DSTBN_N[3..0]12

MCH FSB SLEW Control

To Set FSB Slew Control Manually Follow Table Below:

B B

Stuffing Options SLEWMCH_FSB_SLEWCTRL

Roption = Stuffed
Roption = Empty

A A

5

FSB1_D[63..0]
FSB1_DBI#[3..0]
FSB1_DSTBP_N[3..0]
FSB1_DSTBN_N[3..0]

R1251
X_100

0
1

P1V5

R1266
1K

MCH_FSB_SLWCTRL

Q38

B

MMBT3904

E C

2.5V/ns

3.75 or 5V/ns

R3392
X_100

Roption

4

FSB1_D63
FSB1_D62
FSB1_D61
FSB1_D60
FSB1_D59
FSB1_D58
FSB1_D57
FSB1_D56
FSB1_D55
FSB1_D54
FSB1_D53
FSB1_D52
FSB1_D51
FSB1_D50
FSB1_D49
FSB1_D48
FSB1_D47
FSB1_D46
FSB1_D45
FSB1_D44
FSB1_D43
FSB1_D42
FSB1_D41
FSB1_D40
FSB1_D39
FSB1_D38
FSB1_D37
FSB1_D36
FSB1_D35
FSB1_D34
FSB1_D33
FSB1_D32
FSB1_D31
FSB1_D30
FSB1_D29
FSB1_D28
FSB1_D27
FSB1_D26
FSB1_D25
FSB1_D24
FSB1_D23
FSB1_D22
FSB1_D21
FSB1_D20
FSB1_D19
FSB1_D18
FSB1_D17
FSB1_D16
FSB1_D15
FSB1_D14
FSB1_D13
FSB1_D12
FSB1_D11
FSB1_D10
FSB1_D9
FSB1_D8
FSB1_D7
FSB1_D6
FSB1_D5
FSB1_D4
FSB1_D3
FSB1_D2
FSB1_D1
FSB1_D0

FSB1_DBI#3
FSB1_DBI#2
FSB1_DBI#1
FSB1_DBI#0

FSB1_DSTBP_N3
FSB1_DSTBP_N2
FSB1_DSTBP_N1
FSB1_DSTBP_N0

FSB1_DSTBN_N3
FSB1_DSTBN_N2
FSB1_DSTBN_N1
FSB1_DSTBN_N0

MCH_CORE_VCCA
MCH_FSB_VCCA
MCH_CORE_VSSA

4

AF16

AG14

AJ16
AJ15

AG15

AF15

AJ13
AL16
AP16
AH16
AN15
AL14

AM15

AN14

AM16

AH14
AP14
AR12
AR13
AP11
AP13
AT12
AT11
AV12
AV10
AU10

AV9
AT8
AR9
AT9
AU8

AV7
AK12
AL13
AL11

AM13

AN11

AM12

AN12

AN9

AN8

AP8

AM9
AM6

AK9

AN6

AL8

AL7
AU5
AR7
AU7
AR6
AT6
AV4
AV6
AT5
AT3
AT2
AR4
AR3
AR1
AP4
AP5
AP1

AH13
AU11
AK11

AP7

AK15
AR10

AM10

AU4

AK14
AP10
AL10

AU3

AT17
AU17
AU16

BLACKFORD 5/11

FSB1_D63
FSB1_D62
FSB1_D61
FSB1_D60
FSB1_D59
FSB1_D58
FSB1_D57
FSB1_D56
FSB1_D55
FSB1_D54
FSB1_D53
FSB1_D52
FSB1_D51
FSB1_D50
FSB1_D49
FSB1_D48
FSB1_D47
FSB1_D46
FSB1_D45
FSB1_D44
FSB1_D43
FSB1_D42
FSB1_D41
FSB1_D40
FSB1_D39
FSB1_D38
FSB1_D37
FSB1_D36
FSB1_D35
FSB1_D34
FSB1_D33
FSB1_D32
FSB1_D31
FSB1_D30
FSB1_D29
FSB1_D28
FSB1_D27
FSB1_D26
FSB1_D25
FSB1_D24
FSB1_D23
FSB1_D22
FSB1_D21
FSB1_D20
FSB1_D19
FSB1_D18
FSB1_D17
FSB1_D16
FSB1_D15
FSB1_D14
FSB1_D13
FSB1_D12
FSB1_D11
FSB1_D10
FSB1_D9
FSB1_D8
FSB1_D7
FSB1_D6
FSB1_D5
FSB1_D4
FSB1_D3
FSB1_D2
FSB1_D1
FSB1_D0

FSB1_DBI3
FSB1_DBI2
FSB1_DBI1
FSB1_DBI0

FSB1_DSTBP3
FSB1_DSTBP2
FSB1_DSTBP1
FSB1_DSTBP0

FSB1_DSTBN3
FSB1_DSTBN2
FSB1_DSTBN1
FSB1_DSTBN0

COREVCCA
FSBVCCA
COREVSSA

FSB 1

3

U45E

FSB1_A35
FSB1_A34
FSB1_A33
FSB1_A32
FSB1_A31
FSB1_A30
FSB1_A29
FSB1_A28
FSB1_A27
FSB1_A26
FSB1_A25
FSB1_A24
FSB1_A23
FSB1_A22
FSB1_A21
FSB1_A20
FSB1_A19
FSB1_A18
FSB1_A17
FSB1_A16
FSB1_A15
FSB1_A14
FSB1_A13
FSB1_A12
FSB1_A11
FSB1_A10

FSB1_A9
FSB1_A8
FSB1_A7
FSB1_A6
FSB1_A5
FSB1_A4
FSB1_A3

FSB1_REQ4
FSB1_REQ3
FSB1_REQ2
FSB1_REQ1
FSB1_REQ0

FSB1_ADSTB1
FSB1_ADSTB0

FSB1_BPRI_N
FSB1_DEFER_N
FSB1_RESET_N

FSB1_RS2
FSB1_RS1
FSB1_RS0

FSB1_RSP_N

FSB1_TRDY_N

FSB1_ADS_N

FSB1_AP1
FSB1_AP0

FSB1_BINIT_N

FSB1_BNR_N

FSB1_BPM5

FSB1_BPM4
FSB1_BREQ1
FSB1_BREQ0

FSB1_DBSY_N

FSB1_DP3
FSB1_DP2
FSB1_DP1
FSB1_DP0

FSB1_DRDY_N

FSB1_HIT_N

FSB1_HITM_N

FSB1_LOCK_N

FSB1_MCERR_N

FSBCRES

FSBODTCRES

FSBSLWCRES

FSBSLWCTRL

FSB1_VREF

FSB1_VREF

FSB1_VREF

BLACKFORD G1

3

FSB1_A35

AC3

FSB1_A34

AC4

FSB1_A33

AD2

FSB1_A32

AE1

FSB1_A31

AE2

FSB1_A30

AE4

FSB1_A29

AD3

FSB1_A28

AF3

FSB1_A27

AF1

FSB1_A26

AJ3

FSB1_A25

AH1

FSB1_A24

AH2

FSB1_A23

AD5

FSB1_A22

AC6

FSB1_A21

AE5

FSB1_A20

AD6

FSB1_A19

AH5

FSB1_A18

AG5

FSB1_A17

AF4

FSB1_A16

AA12

FSB1_A15

AC7

FSB1_A14

AB10

FSB1_A13

AC9

FSB1_A12

AD8

FSB1_A11

AF6

FSB1_A10

AB11

FSB1_A9

AE7

FSB1_A8

AF7

FSB1_A7

AG8

FSB1_A6

AH8

FSB1_A5

AC12

FSB1_A4

AD9

FSB1_A3

AD12

FSB1_REQ_N4

AE10

FSB1_REQ_N3

AF9

FSB1_REQ_N2

AJ6

FSB1_REQ_N1

AD11

FSB1_REQ_N0

AG9

FSB1_ADSTB_N1

AG3

FSB1_ADSTB_N0

AC10

FSB1_BPRI_N

AJ10

FSB1_DEFER_N

AJ9

FSB1_RESET_N

AE11

FSB1_RS2_N

AL5

FSB1_RS1_N

AL1

FSB1_RS0_N

AK5

FSB1_RSP_N

AK2

FSB1_TRDY_N

AK6

FSB1_ADS_N

AP2

FSB1_AP1

AG10

FSB1_AP0

AG12

FSB1_BINIT_N

AJ4

FSB1_BNR_N

AK3

FSB1_BPM_N5

AN3

FSB1_BPM_N4

AN2

FSB1_BR_N1

AM1

FSB1_BR_N0

AL2

FSB1_DBSY_N

AM4

FSB1_DP_N3

AF13

FSB1_DP_N2

AF12

FSB1_DP_N1

AJ12

FSB1_DP_N0

AG11

FSB1_DRDY_N

AM3

FSB1_HIT_N

AK8

FSB1_HITM_N

AJ7

FSB1_LOCK_N

AL4

FSB1_MCERR_N

AH11

MCH_FSB_CRES

AT35

MCH_FSB_ODTCRES

AR34

MCH_FSB_SLWCRES

AU35

MCH_FSB_SLWCTRL

AV13

FSB1_VREF

AT14
AN5
AH4

FSB1_BPRI_N 12
FSB1_DEFER_N 12
FSB1_RESET_N 12,64
FSB1_RS2_N 12
FSB1_RS1_N 12
FSB1_RS0_N 12
FSB1_RSP_N 12
FSB1_TRDY_N 12

FSB1_ADS_N 12

FSB1_BINIT_N 12
FSB1_BNR_N 12

FSB1_DBSY_N 12

FSB1_DRDY_N 12
FSB1_HIT_N 12
FSB1_HITM_N 12
FSB1_LOCK_N 12
FSB1_MCERR_N 12

2

FSB1_A[35..3]
FSB1_REQ_N[4..0]
FSB1_ADSTB_N[1..0]
FSB1_AP[1..0]
FSB1_BPM_N[5..0]
FSB1_BR_N[1..0]
FSB1_DP_N[3..0]

FSB1_A[35..3] 12
FSB1_REQ_N[4..0] 12
FSB1_ADSTB_N[1..0] 12
FSB1_AP[1..0] 12
FSB1_BPM_N[5..0] 12,64
FSB1_BR_N[1..0] 12
FSB1_DP_N[3..0] 12

MCH FSB PLL/COMP/VREF CKTS

MCH_FSB_CRES

R647
649RST

P_VTT

800mV at 1.2V FSB Vtt

Minmum trace and width as wide as possible
12 mils

R650

49.9RST

R652
100RST

Route MCH_CORE_VSSA Between
MCH_FSB_VCCA and MCH_CORE_VCCA
Width=25mils, Space=10mils

P1V5

P1V5

2

R649

0.499RST

R653

0.499RST

L13

4.7uH-0805-30mA

L14

4.7uH-0805-30mA

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

R648

49.9RST

MCH_FSB_ODTCRES
MCH_FSB_SLWCRES

R1268

0

C991
22u-1206

C996
22u-1206

C994
220P

C993
1u

Micro Star Restricted Secret

Blackford FSB1

MS-9192

1

FSB1_VREF

C995
220P

MCH_FSB_VCCA

C992

0.1u

MCH_CORE_VSSA

MCH_CORE_VCCA

C997

0.1u

MCH_CORE_VSSA

Last Revision Date:

Friday, April 27, 2007

Sheet

16 90

1

Rev

0A

of

5

4

3

2

1

Blackford FBD Interface 1

U45A

FBD_CH0_NB_P[13..0]23
FBD_CH0_NB_N[13..0]23

D D

C C

B B

A A

FBD_CH1_NB_P[13..0]26
FBD_CH1_NB_N[13..0]26

FBD_CH0_NB_P[13..0]
FBD_CH0_NB_N[13..0]
FBD_CH1_NB_P[13..0]
FBD_CH1_NB_N[13..0] FBD_CH1_SB_N[9..0]

FBD01CLKP59
FBD01CLKN59

5

FBD_CH0_NB_P13
FBD_CH0_NB_P12
FBD_CH0_NB_P11
FBD_CH0_NB_P10

FBD_CH0_NB_P9
FBD_CH0_NB_P8

FBD_CH0_NB_P6
FBD_CH0_NB_P5
FBD_CH0_NB_P4
FBD_CH0_NB_P3
FBD_CH0_NB_P2
FBD_CH0_NB_P1
FBD_CH0_NB_P0

FBD_CH0_NB_N13
FBD_CH0_NB_N12
FBD_CH0_NB_N11
FBD_CH0_NB_N10

FBD_CH0_NB_N9
FBD_CH0_NB_N8
FBD_CH0_NB_N7
FBD_CH0_NB_N6
FBD_CH0_NB_N5
FBD_CH0_NB_N4
FBD_CH0_NB_N3
FBD_CH0_NB_N2
FBD_CH0_NB_N1

FBD_CH1_NB_P13
FBD_CH1_NB_P12
FBD_CH1_NB_P11
FBD_CH1_NB_P10

FBD_CH1_NB_P9
FBD_CH1_NB_P8
FBD_CH1_NB_P7
FBD_CH1_NB_P6
FBD_CH1_NB_P5
FBD_CH1_NB_P4
FBD_CH1_NB_P3
FBD_CH1_NB_P2
FBD_CH1_NB_P1
FBD_CH1_NB_P0

FBD_CH1_NB_N13
FBD_CH1_NB_N12
FBD_CH1_NB_N11
FBD_CH1_NB_N10

FBD_CH1_NB_N9
FBD_CH1_NB_N8
FBD_CH1_NB_N7
FBD_CH1_NB_N6
FBD_CH1_NB_N5
FBD_CH1_NB_N4
FBD_CH1_NB_N3
FBD_CH1_NB_N2
FBD_CH1_NB_N1
FBD_CH1_NB_N0

FBD01CLKP
FBD01CLKN

FBD01VCCA
FBD01VSSA

BLACKFORD 1/11

V29

FBD0NBIP13

U30

FBD0NBIP12

U36

FBD0NBIP11

V35

FBD0NBIP10

W34

FBD0NBIP9

U33

FBD0NBIP8

V32

FBD0NBIP7

T31

FBD0NBIP6

W28

FBD0NBIP5

U28

FBD0NBIP4

V27

FBD0NBIP3

AB31

FBD0NBIP2

Y30

FBD0NBIP1

Y27

FBD0NBIP0

V30

FBD0NBIN13

U31

FBD0NBIN12

U37

FBD0NBIN11

V36

FBD0NBIN10

W35

FBD0NBIN9

U34

FBD0NBIN8

V33

FBD0NBIN7

T32

FBD0NBIN6

W29

FBD0NBIN5

T28

FBD0NBIN4

U27

FBD0NBIN3

AB32

FBD0NBIN2

Y31

FBD0NBIN1

Y28

FBD0NBIN0

K31

FBD1NBIP13

M32

FBD1NBIP12

G38

FBD1NBIP11

H36

FBD1NBIP10

F36

FBD1NBIP9

J35

FBD1NBIP8

K34

FBD1NBIP7

L33

FBD1NBIP6

L30

FBD1NBIP5

M29

FBD1NBIP4

N28

FBD1NBIP3

L27

FBD1NBIP2

M26

FBD1NBIP1

P27

FBD1NBIP0

K32

FBD1NBIN13

N32

FBD1NBIN12

H38

FBD1NBIN11

H37

FBD1NBIN10

F37

FBD1NBIN9

K35

FBD1NBIN8

L34

FBD1NBIN7

M33

FBD1NBIN6

L31

FBD1NBIN5

M30

FBD1NBIN4

N29

FBD1NBIN3

L28

FBD1NBIN2

M27

FBD1NBIN1

P28

FBD1NBIN0

R38

FBD01CLKP

T38

FBD01CLKN

T35

FBD01VCCA

T34

FBD01VSSA

4

FBD0SBOP9
FBD0SBOP8
FBD0SBOP7
FBD0SBOP6
FBD0SBOP5
FBD0SBOP4
FBD0SBOP3
FBD0SBOP2
FBD0SBOP1
FBD0SBOP0

Northbound

Southbound

FBD0SBON9
FBD0SBON8

Channel 0

FBD0SBON7
FBD0SBON6
FBD0SBON5
FBD0SBON4
FBD0SBON3
FBD0SBON2
FBD0SBON1
FBD0SBON0

FBD1SBOP9
FBD1SBOP8
FBD1SBOP7
FBD1SBOP6
FBD1SBOP5
FBD1SBOP4
FBD1SBOP3
FBD1SBOP2
FBD1SBOP1

Northbound

FBD1SBOP0

Southbound

FBD1SBON9

Channel 1

FBD1SBON8
FBD1SBON7
FBD1SBON6
FBD1SBON5
FBD1SBON4
FBD1SBON3
FBD1SBON2
FBD1SBON1
FBD1SBON0

FBD0SCL
FBD0SDA

FBD1SCL
FBD1SDA

FBDICOMPBIAS

FBDRESIN

FBDBGBIASEXT

BLACKFORD G1

AA36
AC34
AB35
AB37
AA38
Y36
Y34
AA32
V38
W32

AA35
AC33
AB34
AC37
AB38
Y37
Y33
AA33
W38
W31

N38
R33
P34
R36
P37
N34
M35
K38
L36
J36

N37
R32
P33
R35
P36
N35
M36
L38
L37
J37

H13
G13

J16
K15

F35
E36
E37

FBD_CH0_SB_P9
FBD_CH0_SB_P8
FBD_CH0_SB_P7
FBD_CH0_SB_P6
FBD_CH0_SB_P5
FBD_CH0_SB_P4
FBD_CH0_SB_P3FBD_CH0_NB_P7
FBD_CH0_SB_P2
FBD_CH0_SB_P1
FBD_CH0_SB_P0

FBD_CH0_SB_N9
FBD_CH0_SB_N8
FBD_CH0_SB_N7
FBD_CH0_SB_N6
FBD_CH0_SB_N5
FBD_CH0_SB_N4
FBD_CH0_SB_N3
FBD_CH0_SB_N2
FBD_CH0_SB_N1
FBD_CH0_SB_N0FBD_CH0_NB_N0

FBD_CH1_SB_P9
FBD_CH1_SB_P8
FBD_CH1_SB_P7
FBD_CH1_SB_P6
FBD_CH1_SB_P5
FBD_CH1_SB_P4
FBD_CH1_SB_P3
FBD_CH1_SB_P2
FBD_CH1_SB_P1
FBD_CH1_SB_P0

FBD_CH1_SB_N9
FBD_CH1_SB_N8
FBD_CH1_SB_N7
FBD_CH1_SB_N6
FBD_CH1_SB_N5
FBD_CH1_SB_N4
FBD_CH1_SB_N3
FBD_CH1_SB_N2
FBD_CH1_SB_N1
FBD_CH1_SB_N0

FBD0SCL
FBD0SDA

FBD1SCL
FBD1SDA

FBDICOMBIAS
FBDRESIN
FBDBGBIASEXT

FBD0SCL 23,24,25
FBD0SDA 23,24,25

FBD1SCL 26,27,28
FBD1SDA 26,27,28

3

FBD_CH0_SB_P[9..0]
FBD_CH0_SB_N[9..0]
FBD_CH1_SB_P[9..0]

FBD0SDA
FBD0SCL
FBD1SCL
FBD1SDA

FBD_CH0_SB_P[9..0] 23
FBD_CH0_SB_N[9..0] 23
FBD_CH1_SB_P[9..0] 26
FBD_CH1_SB_N[9..0] 26

RN17

1 2
3 4
5 6
7 8

4.7K-8P4R

P3V3

P3V3

MCH FBD PLL/COMP CKTS

P1V5

R639

R640

100RST

100RST

R644

R645

51.1RST

121RST

Route FBD VCCA with Corresponding VSSA
As Differential Pair
Width=25mils, Space=10mils

P1V5

R643

0.499RST

L12

4.7uH-0805-30mA
C986
22u-1206

SMBus Selector

Address : 1110 001Z

U3028

C3228

0.1u

19

SDA

18

SCL

1

A0

2

A1

3

A2

P3V3

20

VDD

10

VSS

PHL-PCA9544-SO20

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

SDA0

SCL0

SDA1

SCL1

SDA2

SCL2

SDA3

SCL3

INT0
INT1
INT2
INT3

INTOUT

Micro Star Restricted Secret

SMBDAT_FBD54
SMBCLK_FBD54

2

R3279 100
R3280 100
R3281 100

R641
100RST

FBDRESIN
FBDBGBIASEXT
FBDICOMBIAS

FBD01VCCA

C987

0.1u

FBD01VSSA

FBD0SDA

5

FBD0SCL

6

FBD1SDA

8

FBD1SCL

9

FBD2SDA

12

FBD2SCL

13

FBD3SDA

15

FBD3SCL

16
4

7
11
14

17

Blackford FBD Interface1

MS-9192

Last Revision Date:

Friday, April 27, 2007

Sheet

1

FBD2SDA 18,29,30,31
FBD2SCL 18,29,30,31

FBD3SDA 18,32,33,34
FBD3SCL 18,32,33,34

Rev

0A

17 90

of

5

4

3

2

1

Blackford FBD Interface 2

FBD_CH2_NB_P[13..0]29

D D

C C

B B

A A

FBD_CH2_NB_N[13..0]29
FBD_CH3_NB_P[13..0]32
FBD_CH3_NB_N[13..0]32

5

FBD_CH2_NB_P[13..0]
FBD_CH2_NB_N[13..0]
FBD_CH3_NB_P[13..0]
FBD_CH3_NB_N[13..0]

FBD_CH2_NB_P13
FBD_CH2_NB_P12
FBD_CH2_NB_P11
FBD_CH2_NB_P10
FBD_CH2_NB_P9
FBD_CH2_NB_P8
FBD_CH2_NB_P7
FBD_CH2_NB_P6
FBD_CH2_NB_P5
FBD_CH2_NB_P4
FBD_CH2_NB_P3
FBD_CH2_NB_P2
FBD_CH2_NB_P1
FBD_CH2_NB_P0

FBD_CH2_NB_N13
FBD_CH2_NB_N12
FBD_CH2_NB_N11
FBD_CH2_NB_N10

FBD_CH2_NB_N9
FBD_CH2_NB_N8
FBD_CH2_NB_N7
FBD_CH2_NB_N6
FBD_CH2_NB_N5
FBD_CH2_NB_N4
FBD_CH2_NB_N3
FBD_CH2_NB_N2
FBD_CH2_NB_N1
FBD_CH2_NB_N0

FBD_CH3_NB_P13
FBD_CH3_NB_P12
FBD_CH3_NB_P11
FBD_CH3_NB_P10
FBD_CH3_NB_P9
FBD_CH3_NB_P8
FBD_CH3_NB_P7
FBD_CH3_NB_P6
FBD_CH3_NB_P5
FBD_CH3_NB_P4
FBD_CH3_NB_P3
FBD_CH3_NB_P2
FBD_CH3_NB_P1
FBD_CH3_NB_P0

FBD_CH3_NB_N13
FBD_CH3_NB_N12
FBD_CH3_NB_N11
FBD_CH3_NB_N10

FBD_CH3_NB_N9
FBD_CH3_NB_N8
FBD_CH3_NB_N7
FBD_CH3_NB_N6
FBD_CH3_NB_N5
FBD_CH3_NB_N4
FBD_CH3_NB_N3
FBD_CH3_NB_N2
FBD_CH3_NB_N1
FBD_CH3_NB_N0

FBD23CLKP59
FBD23CLKN59

FBD23CLKP
FBD23CLKN

FBD23VCCA
FBD23VSSA

4

BLACKFORD 2/11

C31

FBD2NBIP13

B32

FBD2NBIP12

D38

FBD2NBIP11

C37

FBD2NBIP10

C36

FBD2NBIP9

B35

FBD2NBIP8

C34

FBD2NBIP7

B33

FBD2NBIP6

B30

FBD2NBIP5

B29

FBD2NBIP4

C28

FBD2NBIP3

B27

FBD2NBIP2

B26

FBD2NBIP1

C25

FBD2NBIP0

B31

FBD2NBIN13

A32

FBD2NBIN12

E38

FBD2NBIN11

D37

FBD2NBIN10

B36

FBD2NBIN9

A35

FBD2NBIN8

B34

FBD2NBIN7

A33

FBD2NBIN6

A30

FBD2NBIN5

A29

FBD2NBIN4

B28

FBD2NBIN3

A27

FBD2NBIN2

A26

FBD2NBIN1

B25

FBD2NBIN0

D20

FBD3NBIP13

C21

FBD3NBIP12

D25

FBD3NBIP11

E24

FBD3NBIP10

F23

FBD3NBIP9

A24

FBD3NBIP8

D23

FBD3NBIP7

B22

FBD3NBIP6

D19

FBD3NBIP5

A19

FBD3NBIP4

B18

FBD3NBIP3

C17

FBD3NBIP2

F18

FBD3NBIP1

G20

FBD3NBIP0

C20

FBD3NBIN13

B21

FBD3NBIN12

D26

FBD3NBIN11

E25

FBD3NBIN10

F24

FBD3NBIN9

B24

FBD3NBIN8

C23

FBD3NBIN7

A22

FBD3NBIN6

E19

FBD3NBIN5

B19

FBD3NBIN4

C18

FBD3NBIN3

D17

FBD3NBIN2

E18

FBD3NBIN1

F20

FBD3NBIN0

D28

FBD23CLKP

E28

FBD23CLKN

E27

FBD23VCCA

F27

FBD23VSSA

Northbound

Channel 2

Northbound

Channel 3

U45B

FBD2SBOP9
FBD2SBOP8
FBD2SBOP7
FBD2SBOP6
FBD2SBOP5
FBD2SBOP4
FBD2SBOP3
FBD2SBOP2
FBD2SBOP1
FBD2SBOP0

Southbound

FBD2SBON9
FBD2SBON8
FBD2SBON7
FBD2SBON6
FBD2SBON5
FBD2SBON4
FBD2SBON3
FBD2SBON2
FBD2SBON1
FBD2SBON0

FBD3SBOP9
FBD3SBOP8
FBD3SBOP7
FBD3SBOP6
FBD3SBOP5
FBD3SBOP4
FBD3SBOP3
FBD3SBOP2
FBD3SBOP1
FBD3SBOP0

Southbound

FBD3SBON9
FBD3SBON8
FBD3SBON7
FBD3SBON6
FBD3SBON5
FBD3SBON4
FBD3SBON3
FBD3SBON2
FBD3SBON1
FBD3SBON0

FBD2SCL
FBD2SDA

FBD3SCL
FBD3SDA

BLACKFORD G1

3

FBD_CH2_SB_P9

E33

FBD_CH2_SB_P8

J32

FBD_CH2_SB_P7

H33

FBD_CH2_SB_P6

G34

FBD_CH2_SB_P5

D34

FBD_CH2_SB_P4

F32

FBD_CH2_SB_P3

D31

FBD_CH2_SB_P2

E30

FBD_CH2_SB_P1

F29

FBD_CH2_SB_P0

G28

FBD_CH2_SB_N9

E34

FBD_CH2_SB_N8

J33

FBD_CH2_SB_N7

H34

FBD_CH2_SB_N6

G35

FBD_CH2_SB_N5

D35

FBD_CH2_SB_N4

F33

FBD_CH2_SB_N3

D32

FBD_CH2_SB_N2

E31

FBD_CH2_SB_N1

F30

FBD_CH2_SB_N0

G29

FBD_CH3_SB_P9

H22

FBD_CH3_SB_P8

K19

FBD_CH3_SB_P7

H18

FBD_CH3_SB_P6

G19

FBD_CH3_SB_P5

J21

FBD_CH3_SB_P4

G23

FBD_CH3_SB_P3

J24

FBD_CH3_SB_P2

H25

FBD_CH3_SB_P1

G26

FBD_CH3_SB_P0

D22

FBD_CH3_SB_N9

H21

FBD_CH3_SB_N8

K18

FBD_CH3_SB_N7

J18

FBD_CH3_SB_N6

H19

FBD_CH3_SB_N5

J20

FBD_CH3_SB_N4

G22

FBD_CH3_SB_N3

J23

FBD_CH3_SB_N2

H24

FBD_CH3_SB_N1

G25

FBD_CH3_SB_N0

E22

F15
E15

H15
H16

FBD2SCL
FBD2SDA

FBD3SCL
FBD3SDA

FBD_CH2_SB_P[9..0]
FBD_CH2_SB_N[9..0]
FBD_CH3_SB_P[9..0]
FBD_CH3_SB_N[9..0]

FBD2SCL 17,29,30,31
FBD2SDA 17,29,30,31

FBD3SCL 17,32,33,34
FBD3SDA 17,32,33,34

FBD_CH2_SB_P[9..0] 29
FBD_CH2_SB_N[9..0] 29
FBD_CH3_SB_P[9..0] 32
FBD_CH3_SB_N[9..0] 32

P1V5

2

Route FBD VCCA with Corresponding VSSA
As Differential Pair
Width=25mils, Space=10mils

R642

0.499RST

L11

4.7uH-0805-30mA

FBD2SDA
FBD2SCL
FBD3SDA
FBD3SCL

C984
22u-1206

RN16

1 2
3 4
5 6
7 8

4.7K-8P4R

Micro Star Restricted Secret

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

Blackford FBD Interface2

MS-9192

Last Revision Date:

Friday, April 27, 2007

Sheet

1

FBD23VCCA

C985

0.1u

FBD23VSSA

P3V3

18 90

of

Rev

0A

5

4

3

2

1

Blackford PCI-E Interface

MCH_EXP0_RXP336
MCH_EXP0_RXP236
MCH_EXP0_RXP136

D D

C C

B B

A A

MCH_EXP0_RXP036
MCH_EXP0_RXN336

MCH_EXP0_RXN236
MCH_EXP0_RXN136
MCH_EXP0_RXN036

MCH_EXP2_RXP336
MCH_EXP2_RXP236
MCH_EXP2_RXP136
MCH_EXP2_RXP036

MCH_EXP2_RXN336
MCH_EXP2_RXN236
MCH_EXP2_RXN136
MCH_EXP2_RXN036

MCH_EXP3_RXP336
MCH_EXP3_RXP236
MCH_EXP3_RXP136
MCH_EXP3_RXP036

MCH_EXP3_RXN336
MCH_EXP3_RXN236
MCH_EXP3_RXN136
MCH_EXP3_RXN036

MCH_EXP4_RXP351
MCH_EXP4_RXP251
MCH_EXP4_RXP151
MCH_EXP4_RXP051

MCH_EXP4_RXN351
MCH_EXP4_RXN251
MCH_EXP4_RXN151
MCH_EXP4_RXN051

MCH_EXP5_RXP351
MCH_EXP5_RXP251
MCH_EXP5_RXP151
MCH_EXP5_RXP051

MCH_EXP5_RXN351
MCH_EXP5_RXN251
MCH_EXP5_RXN151
MCH_EXP5_RXN051

MCH_EXP6_RXP351
MCH_EXP6_RXP251
MCH_EXP6_RXP151
MCH_EXP6_RXP051

MCH_EXP6_RXN351
MCH_EXP6_RXN251
MCH_EXP6_RXN151
MCH_EXP6_RXN051

MCH_EXP7_RXP351
MCH_EXP7_RXP251
MCH_EXP7_RXP151
MCH_EXP7_RXP051

MCH_EXP7_RXN351
MCH_EXP7_RXN251
MCH_EXP7_RXN151
MCH_EXP7_RXN051

MCH_100CLK_P58
MCH_100CLK_N58

5

MCH_EXP0_RXP3
MCH_EXP0_RXP2
MCH_EXP0_RXP1
MCH_EXP0_RXP0

MCH_EXP0_RXN3
MCH_EXP0_RXN2
MCH_EXP0_RXN1
MCH_EXP0_RXN0

MCH_EXP2_RXP3
MCH_EXP2_RXP2
MCH_EXP2_RXP1
MCH_EXP2_RXP0

MCH_EXP2_RXN3
MCH_EXP2_RXN2
MCH_EXP2_RXN1
MCH_EXP2_RXN0

MCH_EXP3_RXP3
MCH_EXP3_RXP2
MCH_EXP3_RXP1
MCH_EXP3_RXP0

MCH_EXP3_RXN3
MCH_EXP3_RXN2
MCH_EXP3_RXN1
MCH_EXP3_RXN0

MCH_EXP4_RXP3
MCH_EXP4_RXP2
MCH_EXP4_RXP1
MCH_EXP4_RXP0

MCH_EXP4_RXN3
MCH_EXP4_RXN2
MCH_EXP4_RXN1
MCH_EXP4_RXN0

MCH_EXP5_RXP3
MCH_EXP5_RXP2
MCH_EXP5_RXP1
MCH_EXP5_RXP0

MCH_EXP5_RXN3
MCH_EXP5_RXN2
MCH_EXP5_RXN1
MCH_EXP5_RXN0

MCH_EXP6_RXP3
MCH_EXP6_RXP2
MCH_EXP6_RXP1
MCH_EXP6_RXP0

MCH_EXP6_RXN3
MCH_EXP6_RXN2
MCH_EXP6_RXN1
MCH_EXP6_RXN0

MCH_EXP7_RXP3
MCH_EXP7_RXP2
MCH_EXP7_RXP1
MCH_EXP7_RXP0

MCH_EXP7_RXN3
MCH_EXP7_RXN2
MCH_EXP7_RXN1
MCH_EXP7_RXN0

MCH_100CLK_P
MCH_100CLK_N

MCH_PE_VCCA
MCH_PE_VSSA

MCH_PE_VSSBG
MCH_PE_VCCBG

BLACKFORD 3/11

AA5

PE0RP3

AB8

PE0RP2

Y4

PE0RP1

Y10

PE0RP0

AA6

PE0RN3

AB7

PE0RN2

Y3

PE0RN1

Y9

PE0RN0

T1

PE2RP3

P3

PE2RP2

N4

PE2RP1

T5

PE2RP0

U1

PE2RN3

R3

PE2RN2

P4

PE2RN1

R5

PE2RN0

U9

PE3RP3

W7

PE3RP2

V5

PE3RP1

V2

PE3RP0

U10

PE3RN3

W8

PE3RN2

V6

PE3RN1

W2

PE3RN0

K10

PE4RP3

D10

PE4RP2

G11

PE4RP1

F12

PE4RP0

L10

PE4RN3

E10

PE4RN2

F11

PE4RN1

E12

PE4RN0

G7

PE5RP3

F8

PE5RP2

C9

PE5RP1

H10

PE5RP0

H7

PE5RN3

G8

PE5RN2

B9

PE5RN1

G10

PE5RN0

J8

PE6RP3

F6

PE6RP2

E4

PE6RP1

C6

PE6RP0

K8

PE6RN3

F5

PE6RN2

E3

PE6RN1

C5

PE6RN0

K4

PE7RP3

H3

PE7RP2

D1

PE7RP1

F3

PE7RP0

L4

PE7RN3

H4

PE7RN2

E1

PE7RN1

F2

PE7RN0

J2

PECLKP

K2

PECLKN

K1

PEVCCA

L1

PEVSSA

N11

PEVSSBG

R11

PEVCCBG

4

PORT0

PORT2PORT3PORT4PORT5PORT6PORT7

U45C

PE0TP3
PE0TP2
PE0TP1
PE0TP0

PE0TN3
PE0TN2
PE0TN1
PE0TN0

PE2TP3
PE2TP2
PE2TP1
PE2TP0

PE2TN3
PE2TN2
PE2TN1
PE2TN0

PE3TP3
PE3TP2
PE3TP1
PE3TP0

PE3TN3
PE3TN2
PE3TN1
PE3TN0

PE4TP3
PE4TP2
PE4TP1
PE4TP0

PE4TN3
PE4TN2
PE4TN1
PE4TN0

PE5TP3
PE5TP2
PE5TP1
PE5TP0

PE5TN3
PE5TN2
PE5TN1
PE5TN0

PE6TP3
PE6TP2
PE6TP1
PE6TP0

PE6TN3
PE6TN2
PE6TN1
PE6TN0

PE7TP3
PE7TP2
PE7TP1
PE7TP0

PE7TN3
PE7TN2
PE7TN1
PE7TN0

PEICOMPI

PERCOMPO

PEWIDTH3
PEWIDTH2
PEWIDTH1
PEWIDTH0

BLACKFORD G1

AA8
AB4
AA3
Y7

AA9
AB5
AA2
Y6

R2
N1
U4
T8

T2
P1
T4
T7

V8
U6
W5
U3

V9
U7
W4
V3

J11
C11
C12
H12

K11
D11
B12
J12

D7
D8
F9
J9

E7
C8
E9
H9

H6
C3
D5
M9

J6
C2
D4
M8

J5
K7
G2
G5

K5
L7
G1
G4

R12
P12

W10
W11
Y12
AA11

MCH_E0_TXP3
MCH_E0_TXP2
MCH_E0_TXP1
MCH_E0_TXP0

MCH_E0_TXN3
MCH_E0_TXN2
MCH_E0_TXN1
MCH_E0_TXN0

MCH_E2_TXP3
MCH_E2_TXP2
MCH_E2_TXP1
MCH_E2_TXP0

MCH_E2_TXN3
MCH_E2_TXN2
MCH_E2_TXN1
MCH_E2_TXN0

MCH_E3_TXP3
MCH_E3_TXP2
MCH_E3_TXP1
MCH_E3_TXP0

MCH_E3_TXN3
MCH_E3_TXN2
MCH_E3_TXN1
MCH_E3_TXN0

MCH_E4_TXP3
MCH_E4_TXP2
MCH_E4_TXP1
MCH_E4_TXP0

MCH_E4_TXN3
MCH_E4_TXN2
MCH_E4_TXN1
MCH_E4_TXN0

MCH_E5_TXP3
MCH_E5_TXP2
MCH_E5_TXP1
MCH_E5_TXP0

MCH_E5_TXN3
MCH_E5_TXN2
MCH_E5_TXN1
MCH_E5_TXN0

MCH_E6_TXP3
MCH_E6_TXP2
MCH_E6_TXP1
MCH_E6_TXP0

MCH_E6_TXN3
MCH_E6_TXN2
MCH_E6_TXN1
MCH_E6_TXN0

MCH_E7_TXP3
MCH_E7_TXP2
MCH_E7_TXP1
MCH_E7_TXP0

MCH_E7_TXN3
MCH_E7_TXN2
MCH_E7_TXN1
MCH_E7_TXN0

MCH_PE_COMP

PEWIDTH3
PEWIDTH2
PEWIDTH1
PEWIDTH0

C533 0.1u-0402
C534 0.1u-0402
C535 0.1u-0402
C536 0.1u-0402

C529 0.1u-0402
C530 0.1u-0402
C531 0.1u-0402
C532 0.1u-0402

C561 0.1u-0402
C562 0.1u-0402
C563 0.1u-0402
C564 0.1u-0402

C553 0.1u-0402
C554 0.1u-0402
C555 0.1u-0402
C556 0.1u-0402

C557 0.1u-0402
C558 0.1u-0402
C559 0.1u-0402
C560 0.1u-0402

C549 0.1u-0402
C550 0.1u-0402
C551 0.1u-0402
C552 0.1u-0402

C639 0.1u
C637 0.1u
C635 0.1u
C633 0.1u

C640 0.1u
C638 0.1u
C636 0.1u
C634 0.1u

C647 0.1u
C645 0.1u
C643 0.1u
C641 0.1u

C648 0.1u
C646 0.1u
C644 0.1u
C642 0.1u

C782 0.1u
C785 0.1u
C787 0.1u
C789 0.1u

C784 0.1u
C786 0.1u
C788 0.1u
C790 0.1u

C773 0.1u
C775 0.1u
C777 0.1u
C779 0.1u

C774 0.1u
C776 0.1u
C778 0.1u
C780 0.1u

R630 24.9RST

R3393 0

3

MCH_EXP0_TXP3 36
MCH_EXP0_TXP2 36
MCH_EXP0_TXP1 36
MCH_EXP0_TXP0 36

MCH_EXP0_TXN3 36
MCH_EXP0_TXN2 36
MCH_EXP0_TXN1 36
MCH_EXP0_TXN0 36

MCH_EXP2_TXP3 36
MCH_EXP2_TXP2 36
MCH_EXP2_TXP1 36
MCH_EXP2_TXP0 36

MCH_EXP2_TXN3 36
MCH_EXP2_TXN2 36
MCH_EXP2_TXN1 36
MCH_EXP2_TXN0 36

MCH_EXP3_TXP3 36
MCH_EXP3_TXP2 36
MCH_EXP3_TXP1 36
MCH_EXP3_TXP0 36

MCH_EXP3_TXN3 36
MCH_EXP3_TXN2 36
MCH_EXP3_TXN1 36
MCH_EXP3_TXN0 36

MCH_EXP4_TXP3 51
MCH_EXP4_TXP2 51
MCH_EXP4_TXP1 51
MCH_EXP4_TXP0 51

MCH_EXP4_TXN3 51
MCH_EXP4_TXN2 51
MCH_EXP4_TXN1 51
MCH_EXP4_TXN0 51

MCH_EXP5_TXP3 51
MCH_EXP5_TXP2 51
MCH_EXP5_TXP1 51
MCH_EXP5_TXP0 51

MCH_EXP5_TXN3 51
MCH_EXP5_TXN2 51
MCH_EXP5_TXN1 51
MCH_EXP5_TXN0 51

MCH_EXP6_TXP3 51
MCH_EXP6_TXP2 51
MCH_EXP6_TXP1 51
MCH_EXP6_TXP0 51

MCH_EXP6_TXN3 51
MCH_EXP6_TXN2 51
MCH_EXP6_TXN1 51
MCH_EXP6_TXN0 51

MCH_EXP7_TXP3 51
MCH_EXP7_TXP2 51
MCH_EXP7_TXP1 51
MCH_EXP7_TXP0 51

MCH_EXP7_TXN3 51
MCH_EXP7_TXN2 51
MCH_EXP7_TXN1 51
MCH_EXP7_TXN0 51

P1V5

PEWIDTH_0 51

P1V5

PEWIDTH3
PEWIDTH2
PEWIDTH1
PEWIDTH0

R634 1K
R635 100
R636 1K
R638 1K

PEWIDTH[3:0] PORT2 PORT4 PORT7PORT6PORT3 PORT5

0000
0001
0010
0011
0100

OTHERS

1000
1001
1010

1011(default)

1100

OTHERS

1111

X4 X4
X4
X4
X4
X4

X4X4X4X4X4 X4
X4
X4
X4

X8
X8

X4

X4 X4

X16

------RESERVED-------

X8

X4X4X4X4X4 X4

X8
X8
X8
X8

X8

X4 X4

X8

X16

------RESERVED-------

Automatic Link negotiation (Not Support)

Port 0 (ESI) is always set to X4 width.

MCH PCI-E PLL/COMP/BAND GAP CKTS

P5V

C981
1u

2.50V Reference

3

Top View

12

Route MCH_PE_VCCBG With MCH_PE_VSSBG
As Differential Pair

R632

Width=25mils, Space=10mils

220

1

U46
LM431AIM3/Vf=2.5V

3 2

P1V5

2

R633

0.499RST

Route MCH_PE_VCCA With MCH_PE_VSSA
As Differential Pair
Width=25mils, Space=10mils

R631

0.499RST

L10

4.7uH-0805-30mA

L9

4.7uH-0805-30mA

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

MCH_PE_VCCBG

C982
22u-1206

R637
0

Keep Stub Between 0ohm resistor
And 22uF Cap As Short As Possible

C979
22u-1206

Micro Star Restricted Secret

Blackford PCI-E Interface

X8

X8

X8

X8

C983

0.1u

MCH_PE_VSSBG

MCH_PE_VCCA

C980

0.1u

MCH_PE_VSSA

MS-9192

Last Revision Date:

Friday, April 27, 2007

Sheet

1

19 90

of

Rev

0A

5

4

3

2

1

Blackford XDP Interface

D D

BLACKFORD 6/11

SYS_PWRGD_3_3V35,37,40,50,63,77

PLTRST_N37,63

MCH_ERR_N238
MCH_ERR_N138
MCH_ERR_N038

C C

MCH_ERR_N2
MCH_ERR_N1
MCH_ERR_N0

B B

A A

R660 X_1K
R661 X_1K
R662 X_1K

XDP1_COMCRES

XDP1_ODTCRES
XDP1_SLWCRES

5

SYS_PWRGD_3_3V

PLTRST_N

MCH_ERR_N2
MCH_ERR_N1
MCH_ERR_N0

P3V3

R1286

49.9RST

R1287
549RST

H17
G17

P10

M12

AR15

AK17

T37
D29
N10

AR16

AP32
AP28

AM7
AG6

M11
AE8

AG2

AH7

AJ1

AK23
AM24
AM31
AN23
AR33

AV27

D2
A5
E6

M3
N5
P7
R9

L3
M5
P6
R8
N2
M6
N8

M2

L6
N7
P9

R6
H1

W1

Y1

J3

PWRGOOD
PLTRST_N

ERR_N2
ERR_N1
ERR_N0

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

4

U45F

CFG_SCL
CFG_SDA

GPIO_SCL
GPIO_SDA

TCK

TDO
TMS

TRST_N

TDIO_ANODE

TDIO_CATHODE

XDPD_N15
XDPD_N14
XDPD_N13
XDPD_N12
XDPD_N11
XDPD_N10

XDPD_N9
XDPD_N8
XDPD_N7
XDPD_N6
XDPD_N5
XDPD_N4
XDPD_N3
XDPD_N2
XDPD_N1
XDPD_N0

XDPDSTBP_N

XDPDSTBN_N

XDPRDY_N

XDPODTCRES
XDPSLWCRES
XDPCOMCRES

TESTHI

TESTHI_V3REF
TESTHI_V3REF

BLACKFORD G1

K14
J14

K13
L12

A6
B7

TDI

B6
A7
A8

A4
B4

E16
D16
A15
C16
A16
A14
B15
D15
B14
B13
E14
A12
D13
A10
B10
A11

C14
C13

A17
G14

J15
F14

AC36

G16
F17

SMBus Voltage Translation

R3284

R3283

4.7K

4.7K

R3163 X_5.1K
R3164 X_5.1K

XDP0_TCK1
MCH_TDI
XDP0_TDO_MCH
XDP0_TMS_MAIN
XDP0_TRST_MCH_N

XDP1_ODTCRES
XDP1_SLWCRES
XDP1_COMCRES

TESTHI0

TESTHI_V3REF1
TESTHI_V3REF0

U3029

1

NC

2

SCL0

SCL1

3

SDA0

SDA1

GND4EN

PCA9515

R3383 0

MCH_TDI

R1245 51

P_VTT

Place pull-up resistors close to MCH.

For A-stepping MCH, not install R267;
For B-stepping MCH, MUST install R267.

R627 1K

R628 5.1K
R629 5.1K

P3V3P3V3

P3V3

R3282

4.7K

8

VCC

7
6
5

P3V3

XDP0_TCK1 64
XDP0_TDI_MAIN 64

XDP0_TMS_MAIN 9,12,64

R3303 51

XDP0_TMS_MAIN

P1V5

P3V3

3

SMBCLK_BF 54
SMBDAT_BF 54

P_VTT

XDP GTL/TTL Level translation

P3V3

P3V3

R1289

R1288

X_1K

U87

XDP0_TDO_MCH
XDP0_TMS_MAIN XDP0_TMS_ESB
XDP0_TCK1
XDP0_TRST#

P_VTT

R1294

49.9RST

R1295
100RST

R1290 51

R1292

1K

C1410
1u

SYS_PWRGD_3_3V

2

A0

3

A1

5

A2

6

A3

1

DIR

4

GTLREF

P3V3

R1297
1K

XDP0_TDO_ESB39

R3022

X_2.2K

XDP0_TRST#9,12,64

R1298

1.6K

VCC3

GND1
GND2
GND3

GTL2005

P_VTT

R3155
X_330

B0
B1
B2
B3

Q117
X_MMBT3904

XDP0_TRST#

Reserved For Greencreek A1

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

2

http://www.msi.com.tw

X_1K

13
12
10
9

14

7
8
11

P_VTT

R1296
330

Q110
MMBT3904

XDP0_TDI_ESB

XDP0_TCK1_ESB
XDP0_TRST#_ESB

P3V3

C1409

0.1u

P_VTT

R3304
51

Q109
MMBT3904

P_VTT

R1244
X_51

Q118
X_MMBT3904

R3450

0

R1293
1K

XDP0_TDO_MAIN 64

XDP0_TRST_MCH_N

R3029
X_20K

Micro Star Restricted Secret

Blackford XDP Interface

MS-9192

Last Revision Date:

Friday, April 27, 2007

Sheet

XDP0_TDI_ESB 39
XDP0_TMS_ESB 39
XDP0_TCK1_ESB 39
XDP0_TRST#_ESB 39

R1291
1K

20 90

1

Rev

0A

of

5

4

3

2

1

Blackford Power/GND

P1V5 P1V5 P_VTT

D D

C C

B B

A A

P3V3

AL17

VCC

L16

VCC

L17

VCC

L18

VCC

L19

VCC

M16

VCC

M17

VCC

M18

VCC

N17

VCC

N19

VCC

P16

VCC

P18

VCC

P20

VCC

P22

VCC

P24

VCC

R15

VCC

R17

VCC

R19

VCC

R21

VCC

R23

VCC

T16

VCC

T18

VCC

T20

VCC

T22

VCC

T24

VCC

U15

VCC

U17

VCC

U19

VCC

U21

VCC

U23

VCC

V16

VCC

V18

VCC

V20

VCC

V22

VCC

V24

VCC

W15

VCC

W17

VCC

W19

VCC

W21

VCC

W23

VCC

Y16

VCC

Y18

VCC

Y20

VCC

Y22

VCC

Y24

VCC

AA15

VCC

AA17

VCC

AA19

VCC

AA21

VCC

AA23

VCC

AB16

VCC

AB18

VCC

AB20

VCC

AB22

VCC

AB24

VCC

AC15

VCC

AC17

VCC

AC19

VCC

AC21

VCC

AC23

VCC

AH10

VCCSF

AE35

VCCSF

AA13

VCCSF

AB13

VCCSF

AB14

VCCSF

AC25

VCCSF

AC26

VCCSF

AD26

VCCSF

L24

VCCSEN

F13

V3REF

5

BLACKFORD 7/11

U45G

VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD
VCCFBD

VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE
VCCPE

BLACKFORD G1

A20
E20
E23
F25
H20
H23
K21
K22
K23
L20
L21
L22
L23
M20
M21
M22
M23
M24
M25
N20
N21
N22
N23
N24
N25
N26
P25
P26
R25
T25
T26
T27
U25
U26
V25
V26
W25
W26
Y25
Y26
AA25
AA26
AA27
AB25
AB26

G12
J10
L2
L8
L13
L14
L15
M13
M14
M15
N6
N12
N13
N14
N15
P13
P14
R4
R10
R13
R14
T13
T14
U2
U8
U13
U14
V13
V14
W6
W12
W13
W14
Y13
Y14

BLACKFORD 8/11

AC13

VTT

AC14

VTT

AD13

VTT

AD14

VTT

AD15

VTT

AD16

VTT

AD17

VTT

AD18

VTT

AD19

VTT

AD20

VTT

AD21

VTT

AD22

VTT

AD23

VTT

AD24

VTT

AD25

VTT

AE13

VTT

AE14

VTT

AE15

VTT

AE16

VTT

AE17

VTT

AE18

VTT

AE19

VTT

AE20

VTT

AE21

VTT

AE22

VTT

AE23

VTT

AE24

VTT

AE25

VTT

AE26

VTT

AF18

VTT

AF19

VTT

AF20

VTT

AF21

VTT

AG18

VTT

AG19

VTT

AG20

VTT

AG21

VTT

AH18

VTT

AH19

VTT

AH20

VTT

AH21

VTT

AJ18

VTT

AJ19

VTT

AJ20

VTT

AJ21

VTT

AK18

VTT

AK19

VTT

AK20

VTT

AK21

VTT

AL18

VTT

AL19

VTT

AL20

VTT

AL21

VTT

AM18

VTT

AM19

VTT

AM20

VTT

AM21

VTT

AN18

VTT

AN19

VTT

AN20

VTT

AN21

VTT

AP18

VTT

AP19

VTT

AP20

VTT

AP21

VTT

AR18

VTT

AR19

VTT

AR20

VTT

AR21

VTT

AT18

VTT

AT19

VTT

AT20

VTT

AT21

VTT

AU18

VTT

AU19

VTT

AU20

VTT

AU21

VTT

AV18

VTT

AV19

VTT

AV20

VTT

AV21

VTT

4

U45H

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BLACKFORD G1

C30
C32
C33
C35
C38
D3
D6
D9
D12
D14
D18
D21
D24
D27
D30
D33
D36
E2
E5
E8
E11
E13
E17
E26
E29
E32
E35
F1
F4
F7
F10
F16
F19
F22
F26
F28
F31
F34
F38
G3
G6
G9
G15
G18
G21
G24
G27
G30
G33
G36
G37
H2
H5
H8
H11
H14
H26
H29
H32
H35
J1
J4
J7
J13
J17
J19
J22
J25
J28
J31
J34
J38
K3
K6
K9
K12
K16
K17
K20
K24
K27

BLACKFORD 9/11

AM5

VSS

AM8

VSS

AM11

VSS

AM14

VSS

AM17

VSS

AM23

VSS

AM26

VSS

AM29

VSS

AM32

VSS

AM35

VSS

AM36

VSS

AN1

VSS

AN4

VSS

AN7

VSS

AN10

VSS

AN13

VSS

AN16

VSS

AN22

VSS

AN25

VSS

AN28

VSS

AN31

VSS

AN34

VSS

AN37

VSS

AN38

VSS

AP3

VSS

AP6

VSS

AP9

VSS

AP12

VSS

AP15

VSS

AP24

VSS

AP27

VSS

AP30

VSS

AP33

VSS

AR2

VSS

AR5

VSS

AR8

VSS

AR11

VSS

AR14

VSS

AR17

VSS

AR23

VSS

AR26

VSS

AR29

VSS

AR32

VSS

AR35

VSS

AR36

VSS

AT1

VSS

AT4

VSS

AT7

VSS

AT10

VSS

AT13

VSS

C29

VSS

AT16

VSS

AT22

VSS

AT25

VSS

AT28

VSS

AT31

VSS

AT34

VSS

AT38

VSS

AU2

VSS

AU6

VSS

AU9

VSS

AU12

VSS

AU15

VSS

AU24

VSS

AU27

VSS

AU30

VSS

AU33

VSS

AU37

VSS

AV3

VSS

AV5

VSS

AV8

VSS

AV11

VSS

AV14

VSS

AV17

VSS

AV23

VSS

AV26

VSS

AV29

VSS

AV32

VSS

AV35

VSS

AV36

VSS

BLACKFORD G1

3

U45I

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AD36
AD37
AD38
AE3
AE6
AE9
AE12
AE30
AE33
AF2
AF5
AF8
AF10
AF11
AF14
AF17
AF23
AF24
AF26
AF27
AF29
AF32
AF35
AF36
AG1
AG4
AG7
AG13
AG16
AG22
AG25
AG28
AG31
AG34
AG37
AG38
AH3
AH6
AH9
AH12
AH15
AH24
AH27
AH30
AH33
AJ2
AJ5
AJ8
AJ11
AJ14
AJ17
AJ23
AJ26
AJ29
AJ32
AJ35
AJ36
AK1
AK4
AK7
AK10
AK13
AK16
AK22
AK25
AK28
AK31
AK34
AK37
AK38
AL3
AL6
AL9
AL12
AL15
AL24
AL27
AL30
AL33
AM2

BLACKFORD 10/11

V17

VSS

V19

VSS

V21

VSS

V23

VSS

V28

VSS

V31

VSS

V34

VSS

V37

VSS

W3

VSS

W9

VSS

W16

VSS

W18

VSS

W20

VSS

W22

VSS

W24

VSS

W27

VSS

W30

VSS

W33

VSS

W36

VSS

W37

VSS

Y2

VSS

Y5

VSS

Y8

VSS

Y11

VSS

Y15

VSS

Y17

VSS

Y19

VSS

Y21

VSS

Y23

VSS

Y29

VSS

Y32

VSS

Y35

VSS

Y38

VSS

AA1

VSS

AA4

VSS

AA7

VSS

AA10

VSS

AA14

VSS

AA16

VSS

AA18

VSS

AA20

VSS

AA22

VSS

AA24

VSS

AA28

VSS

AA31

VSS

AA34

VSS

AA37

VSS

AB3

VSS

AB6

VSS

AB9

VSS

AB12

VSS

AB15

VSS

AB17

VSS

AB19

VSS

AB21

VSS

AB23

VSS

AB27

VSS

AB30

VSS

AB33

VSS

AB36

VSS

AC2

VSS

AC5

VSS

AC8

VSS

AC11

VSS

AC16

VSS

AC18

VSS

AC20

VSS

AC22

VSS

AC24

VSS

AC29

VSS

AC32

VSS

AC35

VSS

AC38

VSS

AD1

VSS

AD4

VSS

AD7

VSS

AD10

VSS

AD28

VSS

AD31

VSS

AD34

VSS

U45J

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BLACKFORD G1

2

K30
K33
K36
K37
L5
L11
L26
L29
L32
L35
M1
M4
M7
M10
M19
M28
M31
M34
M37
M38
N3
N9
N16
N18
N27
N30
N33
N36
P2
P5
P8
P11
P15
P17
P19
P21
P23
P29
P32
P35
P38
R1
R7
R16
R18
R20
R22
R24
R28
R31
R34
R37
T3
T6
T9
T12
T15
T17
T19
T21
T23
T30
T33
T36
U5
U11
U16
U18
U20
U22
U24
U29
U32
U35
U38
V1
V4
V7
V10
V15

BLACKFORD 11/11

AC27

VSS

AB28

VSS

AA29

VSS

AE27

VSS

AC28

VSS

AB29

VSS

A3

VSS

A9

VSS

A13

VSS

A18

VSS

A21

VSS

A23

VSS

A25

VSS

A28

VSS

A31

VSS

A34

VSS

A36

VSS

B2

VSS

B3

VSS

B5

VSS

B8

VSS

B11

VSS

B16

VSS

B17

VSS

B20

VSS

B23

VSS

B37

VSS

C1

VSS

C4

VSS

C7

VSS

C10

VSS

C15

VSS

C19

VSS

C22

VSS

C24

VSS

C26

VSS

C27

VSS

T11

VSS

VSSQUIET

BLACKFORD G1

Micro Star Restricted Secret

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

U45K

AU13

VSS

V12

VSS

AT15

VSS

T10

VSS

AH17

VSS

AV16

VSS

AV15

VSS

U12

VSS

AU14

VSS

V11

VSS

AG17

VSS

AA30

VSS

J27

VSS

K26

VSS

F21

VSS

H28

VSS

J26

VSS

K25

VSS

E21

VSS

H27

VSS

K29

VSS

J30

VSS

H31

VSS

G32

VSS

K28

VSS

J29

VSS

H30

VSS

G31

VSS

R27

VSS

R29

VSS

P30

VSS

N31

VSS

R26

VSS

T29

VSS

R30

VSS

P31

VSS

AD27

VSS

L25

VSSSEN

L9

Blackford Power/GND

MS-9192

Last Revision Date:

Friday, April 27, 2007

Sheet

1

21 90

of

Rev

0A

5

Blackford Decoupling Cap.

4

3

2

1

D D

C C

B B

MCH 1.5V Decoupling Caps.

P1V5

C873
1u

C890
1u

C830
1u

C839
1u

C840
1u

C876

C879

1u

1u

C893

C808

1u

1u

C833

C836

1u

1u

C8421uC845

1u

C843

C846

1u

1u

C882
1u

C811
1u

C838
1u

C848
1u

C849
1u

P1V5

P1V5

P1V5

P1V5

C867
1u

C885
1u

C815
1u

C853
1u

C863
1u

C870
1u

C888
1u

C827
1u

C856
1u

C865
1u

C814
1u

C841
1u

C851
1u

C852
1u

C809
1u

C844
1u

C854
1u

C855
1u

C812
1u

C850

C847

1u

1u

C857

C860

1u

1u

C8581uC861

1u

MCH FSB VTT Decoupling Caps.

P_VTT

C877
1u

C872
1u

C880

4.7u-1206

C816

4.7u-1206

C875
1u

C837

4.7u-1206

C883

4.7u-1206

C819

4.7u-1206

C878
1u

C822

4.7u-1206

C881
1u

C886

4.7u-1206

C884
1u

C825

4.7u-1206

C887
1u

C810

4.7u-1206

C828

4.7u-1206

C889
1u

P_VTT

P_VTT

P_VTT

C874
1u

C813

4.7u-1206

C869
1u

C834

4.7u-1206

C831

4.7u-1206

C891
1u

C8941uC868

1u

C871
1u

V3VREF Decoupling Caps.

P3V3

C892
1u

P1V5

C866

C864
1u

A A

5

C859

1u

4.7u-1206

C862

4.7u-1206

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

4

3

2

http://www.msi.com.tw

Blackford Decoupling Cap.

MS-9192

Last Revision Date:

Friday, April 27, 2007

Sheet

1

22 90

Rev

0A

of

Micro Star Restricted Secret

5

4

3

2

1

FBD Channel 0 DIMM 0

DIMM11A

FBD_CH0_NB_P[13..0]17

D D

C C

B B

A A

FBD_CH0_NB_N[13..0]17

FBD_CH0_SB_P[9..0]17
FBD_CH0_SB_N[9..0]17

5

FBD_CH0_NB_P[13..0]
FBD_CH0_NB_N[13..0]
FBD_CH0_SB_P[9..0]
FBD_CH0_SB_N[9..0]

CK_H_FBD059

CK_H_FBD0_N59

FBD_BR0_RST#24,25,26,27,28,35

FBD_CH0_NB_P13
FBD_CH0_NB_P12
FBD_CH0_NB_P11
FBD_CH0_NB_P10
FBD_CH0_NB_P9
FBD_CH0_NB_P8
FBD_CH0_NB_P7
FBD_CH0_NB_P6
FBD_CH0_NB_P5
FBD_CH0_NB_P4
FBD_CH0_NB_P3
FBD_CH0_NB_P2
FBD_CH0_NB_P1
FBD_CH0_NB_P0

FBD_CH0_NB_N13
FBD_CH0_NB_N12
FBD_CH0_NB_N11
FBD_CH0_NB_N10
FBD_CH0_NB_N9
FBD_CH0_NB_N8
FBD_CH0_NB_N7
FBD_CH0_NB_N6
FBD_CH0_NB_N5
FBD_CH0_NB_N4
FBD_CH0_NB_N3
FBD_CH0_NB_N2
FBD_CH0_NB_N1
FBD_CH0_NB_N0

FBD_CH0_SB_P9
FBD_CH0_SB_P8
FBD_CH0_SB_P7
FBD_CH0_SB_P6
FBD_CH0_SB_P5
FBD_CH0_SB_P4
FBD_CH0_SB_P3
FBD_CH0_SB_P2
FBD_CH0_SB_P1
FBD_CH0_SB_P0

FBD_CH0_SB_N9
FBD_CH0_SB_N8
FBD_CH0_SB_N7
FBD_CH0_SB_N6
FBD_CH0_SB_N5
FBD_CH0_SB_N4
FBD_CH0_SB_N3
FBD_CH0_SB_N2
FBD_CH0_SB_N1
FBD_CH0_SB_N0

CK_H_FBD0
CK_H_FBD0_N

FBD_BR0_RST#

4

102

103
100

228
229

136

207
206
165
164

40
48
66
63
60
57
54
51
37
34
31
28
25
22

41
49
67
64
61
58
55
52
38
35
32
29
26
23

90
99

96
93
82
79
76
73
70

91

97
94
83
80
77
74
71

16

17

87
86
45
44

FBDIMM-1/2

PNP13
PNP12
PNP11
PNP10
PNP9
PNP8

Primarily Northbound

PNP7
PNP6
PNP5
PNP4
PNP3
PNP2
PNP1
PNP0

PNN13
PNN12
PNN11
PNN10
PNN9
PNN8
PNN7
PNN6
PNN5
PNN4
PNN3
PNN2
PNN1
PNN0

PSP9
PSP8

Primarily Southbound

PSP7
PSP6
PSP5
PSP4
PSP3
PSP2
PSP1
PSP0

PSN9
PSN8
PSN7
PSN6
PSN5
PSN4
PSN3
PSN2
PSN1
PSN0

SCKP
SCKN

VID1
VID0

RESET_N

RFUCLK
RFUCLK
RFUCLK
RFUCLK
RFUCLK
RFUCLK
RFUCLK
RFUCLK

SNP13
SNP12
SNP11
SNP10

SNP9
SNP8
SNP7
SNP6
SNP5
SNP4
SNP3
SNP2
SNP1
SNP0

SNN13
SNN12
SNN11
SNN10

SNN9
SNN8
SNN7

Secondary NorthboundSecondary Southbound

SNN6
SNN5
SNN4
SNN3
SNN2
SNN1
SNN0

SSP9
SSP8
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0

SSN9
SSN8
SSN7
SSN6
SSN5
SSN4
SSN3
SSN2
SSN1
SSN0

SCL
SDA

SA2
SA1
SA0

M_TEST

RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU

FBDIMM240

168
186
183
180
177
174
171
157
154
151
148
145
142

161
169
187
184
181
178
175
172
158
155
152
149
146
143

210
222
219
216
213
202
199
196
193
190

211
223
220
217
214
203
200
197
194
191

120
119

118
240
239

137
20
19
106
105
139
140
225
226

CH0_NB_P12
CH0_NB_P11
CH0_NB_P10
CH0_NB_P9
CH0_NB_P8
CH0_NB_P7
CH0_NB_P6
CH0_NB_P5
CH0_NB_P4
CH0_NB_P3
CH0_NB_P2
CH0_NB_P1
CH0_NB_P0

CH0_NB_N13
CH0_NB_N12
CH0_NB_N11
CH0_NB_N10
CH0_NB_N9
CH0_NB_N8
CH0_NB_N7
CH0_NB_N6
CH0_NB_N5
CH0_NB_N4
CH0_NB_N3
CH0_NB_N2
CH0_NB_N1
CH0_NB_N0

CH0_SB_P9
CH0_SB_P8
CH0_SB_P7
CH0_SB_P6
CH0_SB_P5
CH0_SB_P4
CH0_SB_P3
CH0_SB_P2
CH0_SB_P1
CH0_SB_P0

CH0_SB_N9
CH0_SB_N8
CH0_SB_N7
CH0_SB_N6
CH0_SB_N5
CH0_SB_N4
CH0_SB_N3
CH0_SB_N2
CH0_SB_N1
CH0_SB_N0

FBD0SCL
FBD0SDA

FBD00SA2
FBD00SA1
FBD00SA0

3

CH0_NB_P13

160

CH0_NB_P[13..0]
CH0_NB_N[13..0]
CH0_SB_P[9..0]
CH0_SB_N[9..0]

FBD00SA2
FBD00SA1
FBD00SA0

CH0_NB_P[13..0] 24
CH0_NB_N[13..0] 24
CH0_SB_P[9..0] 24
CH0_SB_N[9..0] 24

R11731KR1174

DIMM SPD SMBus Address 0XA0
AMB SMBus Address
LAI SPD SMBus Address
LAI IOX SMBus Address

FBD0SCL 17,24,25
FBD0SDA 17,24,25

R1175
1K

1K

0XB0
0X20
0X70

2

P1V8 P1V5

FBDIMM-2/2

231

VDD

232

VDD

233

VDD

235

VDD

236

VDD

116

VDD

115

VDD

113

VDD

112

VDD

111

VDD

109

VDD

108

VDD

127

VDD

126

VDD

125

VDD

123

VDD

122

VDD

121

VDD

7

VDD

6

VDD

5

VDD

3

VDD

2

VDD

1

VDD

234

VSS

230

VSS

227

VSS

224

VSS

221

VSS

218

VSS

215

VSS

212

VSS

209

VSS

208

VSS

205

VSS

204

VSS

201

VSS

198

VSS

195

VSS

192

VSS

189

VSS

188

VSS

185

VSS

182

VSS

179

VSS

176

VSS

173

VSS

170

VSS

167

VSS

166

VSS

163

VSS

162

VSS

159

VSS

156

VSS

153

VSS

150

VSS

114

VSS

110

VSS

104

VSS

107

VSS

101

VSS

98

VSS

95

VSS

92

VSS

DIMM11B

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VTT
VTT
VTT
VTT

VDDSPD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

FBDIMM240

133
132
130
129
13
12
10
9

237
135
117
15

238

89
88
85
84
81
78
75
72
69
68
65
62
59
56
53
50
47
46
43
42
39
36
33
30
147
144
141
138
134
131
128
124
27
24
21
18
14
11
8
4

F_VTT

Micro Star Restricted Secret

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

FBD Channel 0 DIMM 0

MS-9192

Last Revision Date:

Friday, April 27, 2007

Sheet

P3V3

C3229

0.1u

Share 0.1uF Cap.
Between VDDSPD Pins
Of DIMM0 & DIMM1

23 90

1

of

Rev

0A

5

4

3

2

1

FBD Channel 0 DIMM 1

DIMM12A

CH0_NB_P[13..0]23

D D

C C

B B

A A

CH0_NB_N[13..0]23

CH0_SB_P[9..0]23
CH0_SB_N[9..0]23

5

CH0_NB_P[13..0] R_CH0_NB_P[13..0]
CH0_NB_N[13..0] R_CH0_NB_N[13..0]
CH0_SB_P[9..0]
CH0_SB_N[9..0]

CK_H_FBD159

CK_H_FBD1_N59

FBD_BR0_RST#23,25,26,27,28,35

CH0_NB_P13
CH0_NB_P12
CH0_NB_P11
CH0_NB_P10
CH0_NB_P9
CH0_NB_P8
CH0_NB_P7
CH0_NB_P6
CH0_NB_P5
CH0_NB_P4
CH0_NB_P3
CH0_NB_P2
CH0_NB_P1
CH0_NB_P0

CH0_NB_N13
CH0_NB_N12
CH0_NB_N11
CH0_NB_N10
CH0_NB_N9
CH0_NB_N8
CH0_NB_N7
CH0_NB_N6
CH0_NB_N5
CH0_NB_N4
CH0_NB_N3
CH0_NB_N2
CH0_NB_N1
CH0_NB_N0

CH0_SB_P9
CH0_SB_P8
CH0_SB_P7
CH0_SB_P6
CH0_SB_P5
CH0_SB_P4
CH0_SB_P3
CH0_SB_P2
CH0_SB_P1
CH0_SB_P0

CH0_SB_N9
CH0_SB_N8
CH0_SB_N7
CH0_SB_N6
CH0_SB_N5
CH0_SB_N4
CH0_SB_N3
CH0_SB_N2
CH0_SB_N1
CH0_SB_N0

CK_H_FBD1
CK_H_FBD1_N

FBD_BR0_RST#

4

102

103
100

228
229

136

207
206
165
164

40
48
66
63
60
57
54
51
37
34
31
28
25
22

41
49
67
64
61
58
55
52
38
35
32
29
26
23

90
99

96
93
82
79
76
73
70

91

97
94
83
80
77
74
71

16

17

87
86
45
44

FBDIMM-1/2

PNP13
PNP12
PNP11
PNP10
PNP9
PNP8

Primarily Northbound

PNP7
PNP6
PNP5
PNP4
PNP3
PNP2
PNP1
PNP0

PNN13
PNN12
PNN11
PNN10
PNN9
PNN8
PNN7
PNN6
PNN5
PNN4
PNN3
PNN2
PNN1
PNN0

PSP9
PSP8

Primarily Southbound

PSP7
PSP6
PSP5
PSP4
PSP3
PSP2
PSP1
PSP0

PSN9
PSN8
PSN7
PSN6
PSN5
PSN4
PSN3
PSN2
PSN1
PSN0

SCKP
SCKN

VID1
VID0

RESET_N

RFUCLK
RFUCLK
RFUCLK
RFUCLK
RFUCLK
RFUCLK
RFUCLK
RFUCLK

SNP13
SNP12
SNP11
SNP10

SNP9
SNP8
SNP7
SNP6
SNP5
SNP4
SNP3
SNP2
SNP1
SNP0

SNN13
SNN12
SNN11
SNN10

SNN9
SNN8
SNN7

Secondary NorthboundSecondary Southbound

SNN6
SNN5
SNN4
SNN3
SNN2
SNN1
SNN0

SSP9
SSP8
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0

SSN9
SSN8
SSN7
SSN6
SSN5
SSN4
SSN3
SSN2
SSN1
SSN0

SCL
SDA

SA2
SA1
SA0

M_TEST

RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU

FBDIMM240

168
186
183
180
177
174
171
157
154
151
148
145
142

161
169
187
184
181
178
175
172
158
155
152
149
146
143

210
222
219
216
213
202
199
196
193
190

211
223
220
217
214
203
200
197
194
191

120
119

118
240
239

137
20
19
106
105
139
140
225
226

R_CH0_NB_P12
R_CH0_NB_P11
R_CH0_NB_P10
R_CH0_NB_P9
R_CH0_NB_P8
R_CH0_NB_P7
R_CH0_NB_P6
R_CH0_NB_P5
R_CH0_NB_P4
R_CH0_NB_P3
R_CH0_NB_P2
R_CH0_NB_P1
R_CH0_NB_P0

R_CH0_NB_N13
R_CH0_NB_N12
R_CH0_NB_N11
R_CH0_NB_N10
R_CH0_NB_N9
R_CH0_NB_N8
R_CH0_NB_N7
R_CH0_NB_N6
R_CH0_NB_N5
R_CH0_NB_N4
R_CH0_NB_N3
R_CH0_NB_N2
R_CH0_NB_N1
R_CH0_NB_N0

R_CH0_SB_P9
R_CH0_SB_P8
R_CH0_SB_P7
R_CH0_SB_P6
R_CH0_SB_P5
R_CH0_SB_P4
R_CH0_SB_P3
R_CH0_SB_P2
R_CH0_SB_P1
R_CH0_SB_P0

R_CH0_SB_N9
R_CH0_SB_N8
R_CH0_SB_N7
R_CH0_SB_N6
R_CH0_SB_N5
R_CH0_SB_N4
R_CH0_SB_N3
R_CH0_SB_N2
R_CH0_SB_N1
R_CH0_SB_N0

FBD0SCL
FBD0SDA

FBD01SA2
FBD01SA1
FBD01SA0

3

R_CH0_NB_P13

160

R_CH0_SB_P[9..0]
R_CH0_SB_N[9..0]

FBD01SA2
FBD01SA1
FBD01SA0

DIMM SPD SMBus Address 0XA2
AMB SMBus Address
LAI SPD SMBus Address
LAI IOX SMBus Address

FBD0SCL 17,23,25
FBD0SDA 17,23,25

R_CH0_NB_P[13..0] 25
R_CH0_NB_N[13..0] 25
R_CH0_SB_P[9..0] 25
R_CH0_SB_N[9..0] 25

P3V3

R1171
1K

R1177

R1176

1K

1K

0XB2
0X22
0X72

2

P1V8 P1V5

FBDIMM-2/2

231

VDD

232

VDD

233

VDD

235

VDD

236

VDD

116

VDD

115

VDD

113

VDD

112

VDD

111

VDD

109

VDD

108

VDD

127

VDD

126

VDD

125

VDD

123

VDD

122

VDD

121

VDD

7

VDD

6

VDD

5

VDD

3

VDD

2

VDD

1

VDD

234

VSS

230

VSS

227

VSS

224

VSS

221

VSS

218

VSS

215

VSS

212

VSS

209

VSS

208

VSS

205

VSS

204

VSS

201

VSS

198

VSS

195

VSS

192

VSS

189

VSS

188

VSS

185

VSS

182

VSS

179

VSS

176

VSS

173

VSS

170

VSS

167

VSS

166

VSS

163

VSS

162

VSS

159

VSS

156

VSS

153

VSS

150

VSS

114

VSS

110

VSS

104

VSS

107

VSS

101

VSS

98

VSS

95

VSS

92

VSS

DIMM12B

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VTT
VTT
VTT
VTT

VDDSPD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

FBDIMM240

133
132
130
129
13
12
10
9

237
135
117
15

238

89
88
85
84
81
78
75
72
69
68
65
62
59
56
53
50
47
46
43
42
39
36
33
30
147
144
141
138
134
131
128
124
27
24
21
18
14
11
8
4

F_VTT

Micro Star Restricted Secret

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

FBD Channel 0 DIMM 1

MS-9192

Last Revision Date:

Friday, April 27, 2007

Sheet

P3V3

C3230

0.1u

Share 0.1uF Cap.
Between VDDSPD Pins
Of DIMM0 & DIMM1

24 90

1

of

Rev

0A

5

4

3

2

1

FBD Channel 0 DIMM 2

DIMM13A

R_CH0_NB_P[13..0]24

D D

C C

B B

A A

R_CH0_NB_N[13..0]24

R_CH0_SB_P[9..0]24
R_CH0_SB_N[9..0]24

5

R_CH0_NB_P[13..0]
R_CH0_NB_N[13..0]
R_CH0_SB_P[9..0]
R_CH0_SB_N[9..0]

CK_H_FBD259

CK_H_FBD2_N59

FBD_BR0_RST#23,24,26,27,28,35

R_CH0_NB_P13
R_CH0_NB_P12
R_CH0_NB_P11
R_CH0_NB_P10
R_CH0_NB_P9
R_CH0_NB_P8
R_CH0_NB_P7
R_CH0_NB_P6
R_CH0_NB_P5
R_CH0_NB_P4
R_CH0_NB_P3
R_CH0_NB_P2
R_CH0_NB_P1
R_CH0_NB_P0

R_CH0_NB_N13
R_CH0_NB_N12
R_CH0_NB_N11
R_CH0_NB_N10
R_CH0_NB_N9
R_CH0_NB_N8
R_CH0_NB_N7
R_CH0_NB_N6
R_CH0_NB_N5
R_CH0_NB_N4
R_CH0_NB_N3
R_CH0_NB_N2
R_CH0_NB_N1
R_CH0_NB_N0

R_CH0_SB_P9
R_CH0_SB_P8
R_CH0_SB_P7
R_CH0_SB_P6
R_CH0_SB_P5
R_CH0_SB_P4
R_CH0_SB_P3
R_CH0_SB_P2
R_CH0_SB_P1
R_CH0_SB_P0

R_CH0_SB_N9
R_CH0_SB_N8
R_CH0_SB_N7
R_CH0_SB_N6
R_CH0_SB_N5
R_CH0_SB_N4
R_CH0_SB_N3
R_CH0_SB_N2
R_CH0_SB_N1
R_CH0_SB_N0

CK_H_FBD2
CK_H_FBD2_N

FBD_BR0_RST#

4

102

103
100

228
229

136

207
206
165
164

40
48
66
63
60
57
54
51
37
34
31
28
25
22

41
49
67
64
61
58
55
52
38
35
32
29
26
23

90
99

96
93
82
79
76
73
70

91

97
94
83
80
77
74
71

16

17

87
86
45
44

FBDIMM-1/2

PNP13
PNP12
PNP11
PNP10
PNP9
PNP8

Primarily Northbound

PNP7
PNP6
PNP5
PNP4
PNP3
PNP2
PNP1
PNP0

PNN13
PNN12
PNN11
PNN10
PNN9
PNN8
PNN7
PNN6
PNN5
PNN4
PNN3
PNN2
PNN1
PNN0

PSP9
PSP8

Primarily Southbound

PSP7
PSP6
PSP5
PSP4
PSP3
PSP2
PSP1
PSP0

PSN9
PSN8
PSN7
PSN6
PSN5
PSN4
PSN3
PSN2
PSN1
PSN0

SCKP
SCKN

VID1
VID0

RESET_N

RFUCLK
RFUCLK
RFUCLK
RFUCLK
RFUCLK
RFUCLK
RFUCLK
RFUCLK

160

SNP13

168

SNP12

186

SNP11

183

SNP10

180

SNP9

177

SNP8

174

SNP7

171

SNP6

157

SNP5

154

SNP4

151

SNP3

148

SNP2

145

SNP1

142

SNP0

161

SNN13

169

SNN12

187

SNN11

184

SNN10

181

SNN9

178

SNN8

175

SNN7

172

Secondary NorthboundSecondary Southbound

SNN6

158

SNN5

155

SNN4

152

SNN3

149

SNN2

146

SNN1

143

SNN0

210

SSP9

222

SSP8

219

SSP7

216

SSP6

213

SSP5

202

SSP4

199

SSP3

196

SSP2

193

SSP1

190

SSP0

211

SSN9

223

SSN8

220

SSN7

217

SSN6

214

SSN5

203

SSN4

200

SSN3

197

SSN2

194

SSN1

191

SSN0

FBD0SCL

120

SCL
SDA

SA2
SA1
SA0

M_TEST

RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU

FBDIMM240

119
118

240
239

137
20
19
106
105
139
140
225
226

FBD0SDA
FBD02SA2

FBD02SA1
FBD02SA0

3

P3V3

R1172

R1178
1K

1K

R1179
1K

FBD02SA2
FBD02SA1
FBD02SA0

DIMM SPD SMBus Address 0XA4
AMB SMBus Address
LAI SPD SMBus Address
LAI IOX SMBus Address

FBD0SCL 17,23,24
FBD0SDA 17,23,24

0XB4
0X24
0X74

2

P1V8 P1V5

FBDIMM-2/2

231

VDD

232

VDD

233

VDD

235

VDD

236

VDD

116

VDD

115

VDD

113

VDD

112

VDD

111

VDD

109

VDD

108

VDD

127

VDD

126

VDD

125

VDD

123

VDD

122

VDD

121

VDD

7

VDD

6

VDD

5

VDD

3

VDD

2

VDD

1

VDD

234

VSS

230

VSS

227

VSS

224

VSS

221

VSS

218

VSS

215

VSS

212

VSS

209

VSS

208

VSS

205

VSS

204

VSS

201

VSS

198

VSS

195

VSS

192

VSS

189

VSS

188

VSS

185

VSS

182

VSS

179

VSS

176

VSS

173

VSS

170

VSS

167

VSS

166

VSS

163

VSS

162

VSS

159

VSS

156

VSS

153

VSS

150

VSS

114

VSS

110

VSS

104

VSS

107

VSS

101

VSS

98

VSS

95

VSS

92

VSS

DIMM13B

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VTT
VTT
VTT
VTT

VDDSPD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

FBDIMM240

133
132
130
129
13
12
10
9

237
135
117
15

238

89
88
85
84
81
78
75
72
69
68
65
62
59
56
53
50
47
46
43
42
39
36
33
30
147
144
141
138
134
131
128
124
27
24
21
18
14
11
8
4

F_VTT

Micro Star Restricted Secret

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

FBD Channel 0 DIMM 2

MS-9192

Last Revision Date:

Friday, April 27, 2007

Sheet

P3V3

C3231

0.1u

Share 0.1uF Cap.
Between VDDSPD Pins
Of DIMM0 & DIMM1

25 90

1

of

Rev

0A

5

4

3

2

1

FBD Channel 1 DIMM 0

DIMM21A

FBD_CH1_NB_P[13..0]17

D D

C C

B B

A A

FBD_CH1_NB_N[13..0]17

FBD_CH1_SB_P[9..0]17
FBD_CH1_SB_N[9..0]17

5

FBD_CH1_NB_P[13..0]
FBD_CH1_NB_N[13..0]
FBD_CH1_SB_P[9..0]
FBD_CH1_SB_N[9..0]

CK_H_FBD359

CK_H_FBD3_N59

FBD_BR0_RST#23,24,25,27,28,35

FBD_CH1_NB_P13
FBD_CH1_NB_P12
FBD_CH1_NB_P11
FBD_CH1_NB_P10
FBD_CH1_NB_P9
FBD_CH1_NB_P8
FBD_CH1_NB_P7
FBD_CH1_NB_P6
FBD_CH1_NB_P5
FBD_CH1_NB_P4
FBD_CH1_NB_P3
FBD_CH1_NB_P2
FBD_CH1_NB_P1
FBD_CH1_NB_P0

FBD_CH1_NB_N13
FBD_CH1_NB_N12
FBD_CH1_NB_N11
FBD_CH1_NB_N10
FBD_CH1_NB_N9
FBD_CH1_NB_N8
FBD_CH1_NB_N7
FBD_CH1_NB_N6
FBD_CH1_NB_N5
FBD_CH1_NB_N4
FBD_CH1_NB_N3
FBD_CH1_NB_N2
FBD_CH1_NB_N1
FBD_CH1_NB_N0

FBD_CH1_SB_P9
FBD_CH1_SB_P8
FBD_CH1_SB_P7
FBD_CH1_SB_P6
FBD_CH1_SB_P5
FBD_CH1_SB_P4
FBD_CH1_SB_P3
FBD_CH1_SB_P2
FBD_CH1_SB_P1
FBD_CH1_SB_P0

FBD_CH1_SB_N9
FBD_CH1_SB_N8
FBD_CH1_SB_N7
FBD_CH1_SB_N6
FBD_CH1_SB_N5
FBD_CH1_SB_N4
FBD_CH1_SB_N3
FBD_CH1_SB_N2
FBD_CH1_SB_N1
FBD_CH1_SB_N0

CK_H_FBD3
CK_H_FBD3_N

FBD_BR0_RST#

4

102

103
100

228
229

136

207
206
165
164

40
48
66
63
60
57
54
51
37
34
31
28
25
22

41
49
67
64
61
58
55
52
38
35
32
29
26
23

90
99

96
93
82
79
76
73
70

91

97
94
83
80
77
74
71

16

17

87
86
45
44

FBDIMM-1/2

PNP13
PNP12
PNP11
PNP10
PNP9
PNP8

Primarily Northbound

PNP7
PNP6
PNP5
PNP4
PNP3
PNP2
PNP1
PNP0

PNN13
PNN12
PNN11
PNN10
PNN9
PNN8
PNN7
PNN6
PNN5
PNN4
PNN3
PNN2
PNN1
PNN0

PSP9
PSP8

Primarily Southbound

PSP7
PSP6
PSP5
PSP4
PSP3
PSP2
PSP1
PSP0

PSN9
PSN8
PSN7
PSN6
PSN5
PSN4
PSN3
PSN2
PSN1
PSN0

SCKP
SCKN

VID1
VID0

RESET_N

RFUCLK
RFUCLK
RFUCLK
RFUCLK
RFUCLK
RFUCLK
RFUCLK
RFUCLK

SNP13
SNP12
SNP11
SNP10

SNP9
SNP8
SNP7
SNP6
SNP5
SNP4
SNP3
SNP2
SNP1
SNP0

SNN13
SNN12
SNN11
SNN10

SNN9
SNN8
SNN7

Secondary NorthboundSecondary Southbound

SNN6
SNN5
SNN4
SNN3
SNN2
SNN1
SNN0

SSP9
SSP8
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0

SSN9
SSN8
SSN7
SSN6
SSN5
SSN4
SSN3
SSN2
SSN1
SSN0

SCL
SDA

SA2
SA1
SA0

M_TEST

RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU

FBDIMM240

168
186
183
180
177
174
171
157
154
151
148
145
142

161
169
187
184
181
178
175
172
158
155
152
149
146
143

210
222
219
216
213
202
199
196
193
190

211
223
220
217
214
203
200
197
194
191

120
119

118
240
239

137
20
19
106
105
139
140
225
226

CH1_NB_P12
CH1_NB_P11
CH1_NB_P10
CH1_NB_P9
CH1_NB_P8
CH1_NB_P7
CH1_NB_P6
CH1_NB_P5
CH1_NB_P4
CH1_NB_P3
CH1_NB_P2
CH1_NB_P1
CH1_NB_P0

CH1_NB_N13
CH1_NB_N12
CH1_NB_N11
CH1_NB_N10
CH1_NB_N9
CH1_NB_N8
CH1_NB_N7
CH1_NB_N6
CH1_NB_N5
CH1_NB_N4
CH1_NB_N3
CH1_NB_N2
CH1_NB_N1
CH1_NB_N0

CH1_SB_P9
CH1_SB_P8
CH1_SB_P7
CH1_SB_P6
CH1_SB_P5
CH1_SB_P4
CH1_SB_P3
CH1_SB_P2
CH1_SB_P1
CH1_SB_P0

CH1_SB_N9
CH1_SB_N8
CH1_SB_N7
CH1_SB_N6
CH1_SB_N5
CH1_SB_N4
CH1_SB_N3
CH1_SB_N2
CH1_SB_N1
CH1_SB_N0

FBD1SCL
FBD1SDA

FBD10SA2
FBD10SA1
FBD10SA0

3

CH1_NB_P13

160

CH1_NB_P[13..0]
CH1_NB_N[13..0]
CH1_SB_P[9..0]
CH1_SB_N[9..0]

FBD10SA2
FBD10SA1
FBD10SA0

CH1_NB_P[13..0] 27
CH1_NB_N[13..0] 27
CH1_SB_P[9..0] 27
CH1_SB_N[9..0] 27

R1164
1K

DIMM SPD SMBus Address 0XA0
AMB SMBus Address
LAI SPD SMBus Address
LAI IOX SMBus Address

FBD1SCL 17,27,28
FBD1SDA 17,27,28

R1165
1K

R1166
1K

0XB0
0X20
0X70

2

P1V8 P1V5

FBDIMM-2/2

231

VDD

232

VDD

233

VDD

235

VDD

236

VDD

116

VDD

115

VDD

113

VDD

112

VDD

111

VDD

109

VDD

108

VDD

127

VDD

126

VDD

125

VDD

123

VDD

122

VDD

121

VDD

7

VDD

6

VDD

5

VDD

3

VDD

2

VDD

1

VDD

234

VSS

230

VSS

227

VSS

224

VSS

221

VSS

218

VSS

215

VSS

212

VSS

209

VSS

208

VSS

205

VSS

204

VSS

201

VSS

198

VSS

195

VSS

192

VSS

189

VSS

188

VSS

185

VSS

182

VSS

179

VSS

176

VSS

173

VSS

170

VSS

167

VSS

166

VSS

163

VSS

162

VSS

159

VSS

156

VSS

153

VSS

150

VSS

114

VSS

110

VSS

104

VSS

107

VSS

101

VSS

98

VSS

95

VSS

92

VSS

DIMM21B

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VTT
VTT
VTT
VTT

VDDSPD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

FBDIMM240

133
132
130
129
13
12
10
9

237
135
117
15

238

89
88
85
84
81
78
75
72
69
68
65
62
59
56
53
50
47
46
43
42
39
36
33
30
147
144
141
138
134
131
128
124
27
24
21
18
14
11
8
4

F_VTT

Micro Star Restricted Secret

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

FBD Channel 1 DIMM 0

MS-9192

Last Revision Date:

Friday, April 27, 2007

Sheet

P3V3

C3232

0.1u

Share 0.1uF Cap.
Between VDDSPD Pins
Of DIMM0 & DIMM1

26 90

1

of

Rev

0A

5

4

3

2

1

FBD Channel 1 DIMM 1

DIMM22A

CH1_NB_P[13..0]26

D D

C C

B B

A A

CH1_NB_N[13..0]26

CH1_SB_P[9..0]26
CH1_SB_N[9..0]26

5

CH1_NB_P[13..0]
CH1_NB_N[13..0]
CH1_SB_P[9..0]
CH1_SB_N[9..0]

CK_H_FBD459

CK_H_FBD4_N59

FBD_BR0_RST#23,24,25,26,28,35

CH1_NB_P13
CH1_NB_P12
CH1_NB_P11
CH1_NB_P10
CH1_NB_P9
CH1_NB_P8
CH1_NB_P7
CH1_NB_P6
CH1_NB_P5
CH1_NB_P4
CH1_NB_P3
CH1_NB_P2
CH1_NB_P1
CH1_NB_P0

CH1_NB_N13
CH1_NB_N12
CH1_NB_N11
CH1_NB_N10
CH1_NB_N9
CH1_NB_N8
CH1_NB_N7
CH1_NB_N6
CH1_NB_N5
CH1_NB_N4
CH1_NB_N3
CH1_NB_N2
CH1_NB_N1
CH1_NB_N0

CH1_SB_P9
CH1_SB_P8
CH1_SB_P7
CH1_SB_P6
CH1_SB_P5
CH1_SB_P4
CH1_SB_P3
CH1_SB_P2
CH1_SB_P1
CH1_SB_P0

CH1_SB_N9
CH1_SB_N8
CH1_SB_N7
CH1_SB_N6
CH1_SB_N5
CH1_SB_N4
CH1_SB_N3
CH1_SB_N2
CH1_SB_N1
CH1_SB_N0

CK_H_FBD4
CK_H_FBD4_N

FBD_BR0_RST#

4

102

103
100

228
229

136

207
206
165
164

40
48
66
63
60
57
54
51
37
34
31
28
25
22

41
49
67
64
61
58
55
52
38
35
32
29
26
23

90
99

96
93
82
79
76
73
70

91

97
94
83
80
77
74
71

16

17

87
86
45
44

FBDIMM-1/2

PNP13
PNP12
PNP11
PNP10
PNP9
PNP8

Primarily Northbound

PNP7
PNP6
PNP5
PNP4
PNP3
PNP2
PNP1
PNP0

PNN13
PNN12
PNN11
PNN10
PNN9
PNN8
PNN7
PNN6
PNN5
PNN4
PNN3
PNN2
PNN1
PNN0

PSP9
PSP8

Primarily Southbound

PSP7
PSP6
PSP5
PSP4
PSP3
PSP2
PSP1
PSP0

PSN9
PSN8
PSN7
PSN6
PSN5
PSN4
PSN3
PSN2
PSN1
PSN0

SCKP
SCKN

VID1
VID0

RESET_N

RFUCLK
RFUCLK
RFUCLK
RFUCLK
RFUCLK
RFUCLK
RFUCLK
RFUCLK

SNP13
SNP12
SNP11
SNP10

SNP9
SNP8
SNP7
SNP6
SNP5
SNP4
SNP3
SNP2
SNP1
SNP0

SNN13
SNN12
SNN11
SNN10

SNN9
SNN8
SNN7

Secondary NorthboundSecondary Southbound

SNN6
SNN5
SNN4
SNN3
SNN2
SNN1
SNN0

SSP9
SSP8
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0

SSN9
SSN8
SSN7
SSN6
SSN5
SSN4
SSN3
SSN2
SSN1
SSN0

SCL
SDA

SA2
SA1
SA0

M_TEST

RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU

FBDIMM240

168
186
183
180
177
174
171
157
154
151
148
145
142

161
169
187
184
181
178
175
172
158
155
152
149
146
143

210
222
219
216
213
202
199
196
193
190

211
223
220
217
214
203
200
197
194
191

120
119

118
240
239

137
20
19
106
105
139
140
225
226

R_CH1_NB_P12
R_CH1_NB_P11
R_CH1_NB_P10
R_CH1_NB_P9
R_CH1_NB_P8
R_CH1_NB_P7
R_CH1_NB_P6
R_CH1_NB_P5
R_CH1_NB_P4
R_CH1_NB_P3
R_CH1_NB_P2
R_CH1_NB_P1
R_CH1_NB_P0

R_CH1_NB_N13
R_CH1_NB_N12
R_CH1_NB_N11
R_CH1_NB_N10
R_CH1_NB_N9
R_CH1_NB_N8
R_CH1_NB_N7
R_CH1_NB_N6
R_CH1_NB_N5
R_CH1_NB_N4
R_CH1_NB_N3
R_CH1_NB_N2
R_CH1_NB_N1
R_CH1_NB_N0

R_CH1_SB_P9
R_CH1_SB_P8
R_CH1_SB_P7
R_CH1_SB_P6
R_CH1_SB_P5
R_CH1_SB_P4
R_CH1_SB_P3
R_CH1_SB_P2
R_CH1_SB_P1
R_CH1_SB_P0

R_CH1_SB_N9
R_CH1_SB_N8
R_CH1_SB_N7
R_CH1_SB_N6
R_CH1_SB_N5
R_CH1_SB_N4
R_CH1_SB_N3
R_CH1_SB_N2
R_CH1_SB_N1
R_CH1_SB_N0

FBD1SCL
FBD1SDA

FBD11SA2
FBD11SA1
FBD11SA0

3

R_CH1_NB_P13

160

R_CH1_NB_P[13..0]
R_CH1_NB_N[13..0]
R_CH1_SB_P[9..0]
R_CH1_SB_N[9..0]

FBD11SA2
FBD11SA1
FBD11SA0

R_CH1_NB_P[13..0] 28
R_CH1_NB_N[13..0] 28
R_CH1_SB_P[9..0] 28
R_CH1_SB_N[9..0] 28

P3V3

R1162
1K

DIMM SPD SMBus Address 0XA2
AMB SMBus Address
LAI SPD SMBus Address
LAI IOX SMBus Address

FBD1SCL 17,26,28
FBD1SDA 17,26,28

R1167
1K

R1168
1K

0XB2
0X22
0X72

2

P1V8 P1V5

FBDIMM-2/2

231

VDD

232

VDD

233

VDD

235

VDD

236

VDD

116

VDD

115

VDD

113

VDD

112

VDD

111

VDD

109

VDD

108

VDD

127

VDD

126

VDD

125

VDD

123

VDD

122

VDD

121

VDD

7

VDD

6

VDD

5

VDD

3

VDD

2

VDD

1

VDD

234

VSS

230

VSS

227

VSS

224

VSS

221

VSS

218

VSS

215

VSS

212

VSS

209

VSS

208

VSS

205

VSS

204

VSS

201

VSS

198

VSS

195

VSS

192

VSS

189

VSS

188

VSS

185

VSS

182

VSS

179

VSS

176

VSS

173

VSS

170

VSS

167

VSS

166

VSS

163

VSS

162

VSS

159

VSS

156

VSS

153

VSS

150

VSS

114

VSS

110

VSS

104

VSS

107

VSS

101

VSS

98

VSS

95

VSS

92

VSS

DIMM22B

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VTT
VTT
VTT
VTT

VDDSPD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

FBDIMM240

133
132
130
129
13
12
10
9

237
135
117
15

238

89
88
85
84
81
78
75
72
69
68
65
62
59
56
53
50
47
46
43
42
39
36
33
30
147
144
141
138
134
131
128
124
27
24
21
18
14
11
8
4

F_VTT

Micro Star Restricted Secret

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

FBD Channel 1 DIMM 1

MS-9192

Last Revision Date:

Friday, April 27, 2007

Sheet

P3V3

C3233

0.1u

Share 0.1uF Cap.
Between VDDSPD Pins
Of DIMM0 & DIMM1

27 90

1

of

Rev

0A