MSI MS-9192 Schematic 0502

Page 1
1
MSI
MS-9192 1U & 2U Server
Revision 0A
Intel Dual FC-LGA4 771 Dempsey/Woodcrest/Clovertown Processor Intel Blackford / ESB2 Chipset LSI 1068 SAS Controller Intel Gilgal 82563EB Dual Gb Ethernet PHY ServerEngines Server Management Controller Pilot
Title Page
System Block Diagram Voltage Table
A A
2 3
4Power Block Diagram Clock Block Diagram 5 SMBus Block Diagram 6 JTAG Block Diagram System Reset Block Diagram
Processor 0 Processor 1
MCH (Blackford) Fully buffered DIMMs FBDs Reset and Decoupling Caps. ESB2
Firmware Hub SATA and USB Connectors
7
8
9-11
12-14
15-22
23-34
35
36-44
45
46
Title Page
LAN (Gilgal)Cover Sheet 1
PCI Express X8 Slots POLIT2 Clocks (CK410B/DB1900/DB800) Thermtrip CPU BSEL Level Translation EPLD / RSMRST# Extended Debug Port (XDP) Hardware monitor PECI Poller Back Panel Connector Power Connector and NMI Processor 0 VREG (VR11)
Processor 1 VREG (VR11) VCORE Decoupling Cap.
47-49 50 51-52 53-57 58-60 61 62 63 64 65 66 67 68 69-70
71-72 73
Title Page
FBD 1.8V VREG
1.5V VREG280 Pin PCI-X/PCI-E Slot FSB VTT 1.2V /FBD VTT 0.9V VREG Standby / MISC VREG Impedance Test / mouting hole Manual Parts VT1135S Option Parts GPIO Maping Reset and Power Good PLD Logic Power On/Off and Reset Sequence History Reserved Page
74 75 76 77 78 79 80-83 84
85 86
88-89 90
Title Document Number
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
1
http://www.msi.com.tw
Micro Star Restricted Secret
Cover Sheet
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
190
Rev
0A
of
Page 2
System Block Diagram
1
VRM 11 For CPU0
1.2V VRD FSB VTT
PCI-E X8 Slot
PCI-E X8 Slot
1.5VSBY VREG
3.3VSBY VREG
A A
280 PIN SLOT
( PCI-X & PCI-E X8 )
1.5V VRD
BNB+FBD ESB2
CPU0 FC-LGA4 771 Processor
FSB0 / 1066/1333MHz FSB
PCI Express X8
4GB/s
PCI Express X8
4GB/s
PCI Express X8
PCI-X 100/133
Port #4&5
Port #6&7
PCI Express X8 ESI X4 4GB/s
Port #1&2
(X8)
CPU1 FC-LGA4 771 Processor
Blackford
MCH
FSB1 / 1066/1333MHz FSB
Port #0Port #2&3
2GB/s
Port #3Port #4
(ESI)(X8)
FBD CH0
FBD CH1
FBD CH2
FBD CH3
DIMM #00
DIMM #10
DIMM #20
DIMM #30
SATA
Ultra DMA 66/100
SATA 0~5
ATA Primary
VRM 11 For CPU1
DIMM #01
DIMM #11
DIMM #21
DIMM #31
DIMM #02
DIMM #12
DIMM #22
DIMM #32
NOTE:
Channel 0 & 1 Makes Branch 0 Channel 2 & 3 Makes Branch 1
1.8V VRD
0.9V VRD
CK410B
DB1900
DB800
FBD Clocks
PCI-E Clocks
ESB2
Serial EEPROM
USB2.0
Port #6
Port #0
(X1)
PCI Express X1
KUMERAN
ServerEngines
LPC
Pilot II
USB2.0 Port 0~5
Dual Gb PHY
GILGAL
VGA PS2 KB/MS Serial Port *2
Gb LAN
Gb LAN
Port #0,1,4,5 Front Port #2,3 Rear
RJ45
RJ45
Port #1 Rear Port #2 Front
Gilgal internal VREG Circuitry
FWH
TPM 1.2
BMC Flash
10/100
PHY
1
RJ45
Title Document Number
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
Micro Star Restricted Secret
System Block Diagram
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
290
Rev
0A
of
Page 3
Voltage Table
1
Voltage Level
+3.3V
+5V
+5V
Netname
P3V3 P5V P5VSB
Generated From
AC AC AC
STBY
-12V +12V1 +12V2 +12V3
VID_CPU0 P12V_CPU0 VID_CPU1
+1.2V
A A
+1.5V
+1.5V
P-12V
P12V P12V_CPU1 P12V_CPU0
VCORE0 VCORE1
P_VTT
P1V5
P1V5_AUX
AC AC AC AC
P12V_CPU1 P5V
P12V
P3V3_AUX
AUX
+1.8V
P1V8 P12V
+0.9V
+3.3V STBY
+3.3V AUX
+1.8V1 AUX
+1.2V1 AUX
+1.8V2 AUX +1.2V2 AUX
F_VTT P1V8
P3VSB
P5VSB
P3V3_AUX P3V3 /
P3VSB
P1V8LAN P1V2LAN
P1V8_AUX
P1V2_AUX
P3V3_AUX P3V3_AUX P3V3_AUX P3V3_AUX
Title Document Number
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
1
http://www.msi.com.tw
Micro Star Restricted Secret
Voltage Table
MS-9192
Last Revision Date:
Sheet
Friday, April 27, 2007
390
Rev
0A
of
Page 4
Power Block Diagram
1
+12V3
16A/18Apk
+12V2
16A/18Apk
+12V1
16A/18Apk
P12V3 P5VSB
CPU VREG VR11
P12V2
CPU VREG VR11
P12V1
1.8V FBD VREG
VCORE0
VCORE0
P1V8
0.9V FBD VTT VREG
CPU0
CPU1
12 FBDs
F_VTT
150A
150A
95.52A
FBD VTT
3.48A
5VSBY
3A/3.5Apk
+3V3
24A
P3V3
3.3VSB VREG
SWITCH
P3VSB
P3V3_AUX
AUX1.5V VREG
Active:2A
Standby:1A
AUX1.8V1
Active:0.85A
VREG
Standby:0.24A
AUX1.2V1
Active:0.58A
VREG
Standby:0.05A
ESB2
0.066A
P1V5_AUX
P1V8LAN
P1V2LAN
ESB2
1.4A
GILGAL
0.85A
GILGAL
0.58A
PCI-E & PCI-X slots
PCI-E & PCI-X slots
A A
+5V
30A
P5V
1.5V VREG
FSB VTT VREG
P1V5
P_VTT
1.2V ?A
MCH
12 FBDs
ESB2
CPU 0/1 VTT
19.1A
5.8A
48A
8A
PILOT
0.05A
AUX1.8V2 VREG
AUX1.2V2 VREG
P1V8_AUX
P1V2_AUX
PILOT
PILOT
USB *6
3A
PCI-X Slot
MCH
4.8A
ESB2
1.8A
5A
PCI-E & PCI-X slots
1
Title Document Number
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
Micro Star Restricted Secret
Power Block Diagram
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
490
Rev
0A
of
Page 5
Clock Block Diagram
1
2
CK_H_FBD0_P/N
CK_H_FBD1_P/N
CK_H_FBD2_P/N
CK_H_FBD3_P/N
CK_H_FBD4_P/N
CK_H_FBD5_P/N
CK_H_FBD6_P/N
CK_H_FBD7_P/N
CK_H_FBD8_P/N
CK_H_FBD9_P/N
CK_H_FBD10_P/N
CK_H_FBD11_P/N
PILOT
REFCLKP/N
2
REFCLKP/N
2
REFCLKP/N
2
DB1900
DIF_0P/N
DIF_1P/N
CK410B
CPU_1P/N
CPU_2P/N
CK_H_P0 (267/333MHz)
CK_H_P1 (267/333MHz)
BCLK0/1
2
BCLK0/1
2
CPU0
CPU1
XDP (CPU)
XDP0_BCLK_P/N
CLK
2
DIF_17P/N
DIF_2P/N
DIF_3P/N
DIF_4P/N
DIF_5P/N
USB_48
PCIF_1
REF_1
CK_H_FBD (267/333MHz)
CK_H_MCH (267/333MHz)
MCH_100CLK_P/N (100MHz)
SRC_100CLK_P/N (100MHz)
ESI_100CLK_P/N (100MHz)
ESB2_100CLK_P/N (100MHz)
SATA_100CLK_P/N (100MHz)
CK_48M_ESB
ESB2_PCLK
ESB_14MHZ
Blackford
FBD01CLKP/N
CORECLKP/N
2
2
2
2
PECLKP/N
32.768KHz Crystal
ESICLK100P/N
PECLKP/N
SATACLKP/N
CLK48
PCICLK
CLK14
FBD23CLKP/N
2
ESB2
SER_CLK_IN
PXPCLKO_0
PXPCLKO_1
2
2
SK_LAN_CLK
PXPCLK0
PXPCLK1
62.5MHz OSC
FBD01CLK_P/N
FBD23CLK_P/N
2
Gilgal LAN
PHY_CLK_OUT
25MHz Crystal
SRC_INP/N
DB800
CLK
CLK
CPU_3P/N
CPU_0P/N
BCLK 267/333MHz
SRC_4P/N
SRC_0P/N
SRC_2P/N
SRC_1P/N
A A
SRC_3P/N
Serial Ref Clk 100MHz
CLK_INP/N
2
DIF_15P/N
DIF_16P/N
DIF_5P/N
PCIE_SAS_SRC_P/N
ESB:PCI-X 133
ESB:PCI-X 133
DIF_2P/N
DIF_6P/N
DIF_7P/N
DIF_6P/N
DIF_7P/N
DIF_8P/N
DIF_9P/N
DIF_10P/N
DIF_11P/N
PCIE2_100CLK_P/N0
PCIE1_100CLK_P/N0
PCIE1_100CLK_P/N1
2
2
2
2
2
2
2
2
2
2
2
2
ESB:PCI-E X8
ESB:PCI-E X8
ESB:PCI-E X8
SCKP/N
SCKP/N
SCKP/N
SCKP/N
SCKP/N
SCKP/N
SCKP/N
SCKP/N
SCKP/N
SCKP/N
SCKP/N
SCKP/N
FB DIMM00
FB DIMM01
FB DIMM02
FB DIMM10
FB DIMM11
FB DIMM12
FB DIMM20
FB DIMM21
FB DIMM22
FB DIMM30
FB DIMM31
FB DIMM32
14.318MHz Crystal
PCIF_2
PCI_0
PCI_3
PCIF_0
PCI_2
SIO_PCLK
FWH_PCLK
PLD_33MHZ_CLK
XDP0_33MHZ_CLK
DEBUG_33MHZ_CLK
CK_48M_PILOT
FWH
CLK
PLD
GCK1
XDP (CPU)
CLK
LPC DBG
CLK
CLKI
LCLK
PILOT
48MHz OSC
Title Document Number
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
1
http://www.msi.com.tw
Micro Star Restricted Secret
Clock Block Diagram
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
590
Rev
0A
of
Page 6
SMBus Block Diagram
1
DIMM #00
Serial EEPROM: 0XA0 AMB:ADDR 0XB0
CLK410B
ADDR 0XD2
Blackford
DB800
ADDR 0XDC
DB1900
ADDR 0XDE
CPU XDP
CPU0 VCORE VRD11
ADDR
CPU1 VCORE
A A
VRD11
ADDR
MAIN_SMB
0 ohm
ADDR
3.3V
ESB2
SDTA/SCLK (0XC2)
SPD0SDA/SPD0SCL (Master SPD, 100KHz)
SPD1SDA/SPD1SCL
(Master SPD, 100KHz)
SPD2SDA/SPD2SCL
(Master SPD, 100KHz)
SPD3SDA/SPD3SCL
(Master SPD, 100KHz)
CFGSMBDATA/CFGSMBCLK
(Slave, 100KHz, 0XC0)
3.3V
3.3V
3.3V
3.3V
3.3V
DIMM #10 DIMM #11 DIMM #12
Serial EEPROM: 0XA0 AMB:ADDR 0XB0
DIMM #20
Serial EEPROM: 0XA0 AMB:ADDR 0XB0
DIMM #30 DIMM #31 DIMM #32
Serial EEPROM: 0XA0 AMB:ADDR 0XB0
MCH_SPD0_SMB
MCH_SPD1_SMB
MCH_SPD2_SMB
MCH_SPD3_SMB
PCI-E X8 Slot
PCI-E X8 Slot
1.8V VREG
ADDR
PCA9515
SMBus Isolator
3.3V AUX
SMBDATA/SMBCLK
PCA9515
SMBus Isolator
280 PIN PCI-X & PCI-E Slot
WHEA ROM
ADDR 0XAE
IPMB Header
5VSB
PCA9515
SMBus Isolator
3.3V AUX
3.3V AUX
SDA4/SCL4
SDA0/SCL0
3.3V AUX
SDA1/SCL1
SDA2/SCL2
3.3V AUX
DIMM #01
Serial EEPROM: 0XA2 AMB:ADDR 0XB2
Serial EEPROM: 0XA2 Serial EEPROM: 0XA4 AMB:ADDR 0XB2
DIMM #21
Serial EEPROM: 0XA2 AMB:ADDR 0XB2
Serial EEPROM: 0XA2 Serial EEPROM: 0XA4 AMB:ADDR 0XB2
DIMM #02
Serial EEPROM: 0XA4
AMB:ADDR 0XB4
AMB:ADDR 0XB4
DIMM #22
Serial EEPROM: 0XA4
AMB:ADDR 0XB4
AMB:ADDR 0XB4
HW Monitor
ADT7462
ADDR 0X5C
HW Monitor
ADT7462
ADDR 0X5C
FRU ROM
ADDR 0XAE
SDA0/SCL0
SMBus
Selector
SDA1/SCL1
SDA2/SCL2
SDA3/SCL3
SDA/SCL
BackPanel
Power
ADDR
5VSB
PCA9515
SMBus Isolator
3.3V AUX
Front Panel
Thermal Sensor
ADDR
SDA3/SCL3
PILOT
1
SDA5/SCL5
3.3V AUX
PCA9515
SMBus Isolator
PECI CY8C21234
ADDR 0X
Title Document Number
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
Micro Star Restricted Secret
SMBus Block Diagram
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
690
Rev
0A
of
Page 7
JTAG Block Diagram
1
XDP0_TDI_FSB1
P_VTT
51 OHM
P_VTT
51 OHM
1 2
1
3 4
GTL-TTL
Translator
TRST#
TDO
TDI
TMS TRST#
TDI
CPU1
XDP0_TDO_FSB1
TDO
TCK
51 OHM
GND
XDP0_TDI_ESB XDP0_TRST_ESB#
1K OHM
GND
P_VTT
51 OHM
TDI TRST#
XDP0_TMS_ESB
TMS
TMS
ESB2
GTL-TTL
Translator
ESB2 in chain
TDO
TCK
XDP0_TCK1_ESB
TCK
JUMPER 0
1-2, 3-4 : CPU0 in chain 2-3 : CPU0 bypass
JUMPER 1
1-2, 3-4 : CPU1 in chain 2-3 : CPU1 bypass
P3V3
1K OHM
1K OHM
P_VTT
XDP0_TDI_MAIN
TDI
TCK0
CPU XDP0 Connector
TDO
TMS
TRST#
A A
TCK1
0 OHM
51 OHM
XDP0_TDI_FSB0
P_VTT
51 OHM
XDP0_TDI_MCH
1 2 3 4
TDI
TMS TRST#
0
TDI
TMS
CPU0
XDP0_TCK0
XDP0_TDO_FSB0 XDP0_TDI_MAIN_JMP
XDP0_TDO_MAIN XDP0_TMS_MAIN XDP0_TRST#
TRST#
MCH
TCK
TDO
TCK
TDO
MCH in chain
51 OHM
GND
XDP0_TDO_MCH
P_VTT
51 OHM
51 OHM
GND
XDP0_TCK1
P_VTT
51 OHM
1
XDP0_TMS_GTL
XDP0_TDO_ESB
0 OHM
Title Document Number
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
Micro Star Restricted Secret
GND
JTAG Block Diagram
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
Rev
0A
of
790
Page 8
System Reset Block Diagram
1
VRM0_PWRGD
CK410B
PWRDOWN
DB800
PWRDOWN_N
CPU_VRD_PWRGD
EPLD
CPU0_SKTOCC#
VRM1_PWRGD
CPU1_SKTOCC#
POWER SUPPLY
PWOK
PSON#
ONCTL#
VDDPWR_GD
EPLD
PS_PWROK_BUF
GPIO8
PWBTOUTn
SLPS3n
SLPS5n
PILOT
CPU_VRD_PWRGD
EPLD
100 ms
Delay
PWR_BT_SSI_#
SYS_PWRGD_BUFF
3.3V STBY
SYS_PWRGD_3_3V
RSMRST#
PWRBTN_N
SLP_S3_N
SLP_S4_N
PERST_N
PXPWROK
PWROK
VRMPWRGD
RSMRST_N
LAN_PWR_GD
PWR BTN
3.3VAUX
10Kohms
GND
PWR_BT_IN#
A A
PLTRST_BUFF1#
THERMTRIP0_N
THERMTRIP1_N
ONCTLn
PWBTINn
PCIRSTn
GPIO19
GPIO20
RST BTN
10Kohms
GND
ESB_SYS_RST_N
SYS_RESET_N
ESB2
PHY_PWR_DOWN PHYRST_0_N
PHY_PWR_GD
Pwrgd
CPU1 VRD
Pwrgd
3.3VAUX
CPU_PWR_GD
PLTRST_IN_N
PXPCIRST_N
THRMTRIP_N
PHY_RESET_NPHY_SLEEP
CPU0 VRD
OE
VID[6..0]
OE
VID[6..0]
INIT_N
INIT3_3V_N
PLTRST_N
PCIRST_N
GPIO33
THERMTRIP_N
VRD0_EN
P0VID[6..0]
VRD1_EN
P1VID[6..0]
CPU_PWRGD
INIT#_3_3V
ESB_PLTRST#
PXPCIRST_N
EPLD CPU0
EPLD CPU1
FSB_INIT#
FWH
INIT#
RST_N
PLTRST_BUFF1#
EPLD
280 Pin Slot, SAS 1068
FBD_RESET
ESB_SYS_RST_N
PLTRST_N
DBR_N
INIT_N
PWRGOOD
DBR_N
INIT_N
PWRGOOD
IDE_RSTDRV_N
IDE
CPU0
CPU1
Blackford
PLTRST_N
FSB VTT VRD
VTTPWRGD
THERMTRIP_N
RESET#
VTTPWRGD
THERMTRIP_N
RESET#
FSB1RESET_N
FSB0RESET_N
PWRGOOD
SYS_PWRGD_3_3V
EPLD
SYS_PWRGD_3_3V
FBD_BR0_RST#
GLUE
FBD_BR1_RST#
LOGIC
STAT
VTT_PWRGD
FSB0_THERMTRIP_N
FSB1_THERMTRIP_N
FSB1_RESET_N
FSB0_RESET_N
DIMM#00,01,02,10,11,12 DIMM#20,21,22,30,31,32
Level Translation GTL to 3.3V
Level Translation
3.3V to GTL
ESB_SYS_RST_N
RESET_IN#
PWRGOOD
VTT_PWRGD_3_3V
PLD_VTT_PWRGD_3_3V
GLUE
LOGIC
RESET_OUT#
XDP
EPLD
THERMTRIP_N THERMTRIP0_N THERMTRIP1_N
ESB2
PILOT
Gilgal
Title Document Number
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
1
http://www.msi.com.tw
Micro Star Restricted Secret
System Reset Block Diagram
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
890
Rev
0A
of
Page 9
5
4
3
2
1
P0 Intel LGA771 Signal
VCC0_SENSE2 VSS0_SENSE2 VCC0_SENSE1
D11
FSB0_D15
D14#
C12
FSB0_D14
FSB0_D13
AL7
AL8
VSS_DIE_SENSE2
VCC_DIE_SENSE2
D13#
D12#D8D11#
B12
FSB0_D12
AN3
VCC_DIE_SENSE
C11
FSB0_D11
AN4
VSS_DIE_SENSE
D10#
B10
FSB0_D10
FSB0_D9
VSS0_SENSE1
D9#
D8#
A11
A10
FSB0_D8
FSB0_A[35..3]15
FSB0_DBI#[3..0]15
FSB0_RESET_N15
FSB0_RSP_N15
FSB0_BPRI_N15
FSB0_TRDY_N15
FSB0_DEFER_N15
FSB0_FORCEPR#69
FSB_IGNNE#12,40
FSB_STPCLK#12,40
XDP0_TDI_FSB064 XDP0_TDO_FSB064 XDP0_TMS_MAIN12,20,64
XDP0_TRST#12,20,64 FSB0_GTL_IERR#62 FSB0_PROCHOT#65
FSB0_ADS_N15 FSB0_BNR_N15
FSB0_HIT_N15
FSB0_DBSY_N15
FSB0_DRDY_N15
FSB0_HITM_N15
FSB0_LOCK_N15
FSB0_BINIT_N15
FSB0_MCERR_N15
CPU0_SKTOCC#54,62,63,65
P0THERMDA265 P0THERMDC265
P0THERMDA65
P0THERMDC65
CPU_DBR_RST#12,64
R1208 0
FSB0_VIDSEL63,69
FSB0_BSEL062
FSB0_BSEL162
FSB0_BSEL262
FSB0_D[63..0]15
FSB_A20M#12,40
FSB_NMI12,40 FSB_INTR12,40
FSB_INIT#12,40,67
XDP0_TCK012,64
FSB_FERR#12,40
P0_MS_ID163 P0_MS_ID063
CPU_DBR_RST#
P0_THERMTRIP_N
D D
C C
CPU1_TESTBUS12
B B
A A
FSB0_A[35..3] FSB0_DBI#[3..0] FSB0_D[63..0]
FSB0_DBI#0 FSB0_DBI#1 FSB0_DBI#2 FSB0_DBI#3
FSB0_RESET_N FSB0_RSP_N FSB0_BPRI_N FSB0_TRDY_N FSB0_DEFER_N
CPU0_SMI_N FSB_A20M# FSB0_FORCEPR# FSB_NMI FSB_INTR FSB_IGNNE# FSB_STPCLK# FSB_INIT#
XDP0_TCK0 XDP0_TDI_FSB0 XDP0_TDO_FSB0 XDP0_TMS_MAIN XDP0_TRST#
FSB0_GTL_IERR# FSB_FERR# FSB0_PROCHOT# P0_THERMTRIP_N
FSB0_ADS_N FSB0_BNR_N FSB0_HIT_N FSB0_DBSY_N FSB0_DRDY_N FSB0_HITM_N FSB0_LOCK_N FSB0_BINIT_N FSB0_MCERR_N
CPU0_SKTOCC# P0THERMDA2 P0THERMDC2 P0THERMDA P0THERMDC
CPU_DBR_RST# CPU0_BOOT
CPU0_TESTBUS
P0_LL_ID1 P0_LL_ID0 P0_MS_ID1 P0_MS_ID0
FSB0_BSEL0 FSB0_BSEL1 FSB0_BSEL2
FSB0_D63 FSB0_D62 FSB0_D61 FSB0_D60 FSB0_D59 FSB0_D58 FSB0_D57 FSB0_D56 FSB0_D55 FSB0_D54
R712 0
R720 2.2
A8
DBI0#
G11
DBI1#
D19
DBI2#
C20
DBI3#
G23
RESET#
H4
RSP#
G8
BPRI#
E3
TRDY#
G7
DEFER#
P2
SMI#
K3
A20M#
AK6
FORCEPR#
L1
LINT1/NMI
K1
LINT0/INTR
N2
IGNNE#
M3
STPCLK#
P3
INIT#
AE1
TCK
AD1
TDI
AF1
TDO
AC1
TMS
AG1
TRST#
AB2
IERR#
R3
FERR#/PBE#
AL2
PROCHOT#
M2
THERMTRIP#
D2
ADS#
C2
BNR#
D4
HIT#
B2
DBSY#
C1
DRDY#
E4
HITM#
C3
LOCK#
AD3
BINIT#
AB3
MCERR#
AE8
SKTOCC#
AJ7
THERMDA2
AH7
THERMDC2
AL1
THERMDA
AK1
THERMDC
AC2
DBR#
Y1
BOOTSELECT
AH2
TEST_BUS
AN7
VID_SELECT
AA2
LL_ID1
V2
LL_ID0
V1
MS_ID1
W1
MS_ID0
G29
BSEL0
H30
BSEL1
G30
BSEL2
B22
D63#
A22
D62#
A19
D61#
B19
D60#
B21
D59#
C21
D58#
B18
D57#
A17
D56#
B16
D55#
C18
D54#
FSB0_D53
ESB_SYS_RST# 40,54,67,68
FSB0_THERMTRIP_N 61
B15
D53#
FSB0_D52
C14
D52#
FSB0_D51
C15
D51#
A14
FSB0_D50
D50#
D17
FSB0_D49
FSB0_A35
D49#
FSB0_D48
AJ6
D20
A35#
D48#
FSB0_A33
FSB0_A34
AJ5
A34#
D47#
G22
FSB0_D46
FSB0_D47
AH5
D22
FSB0_A32
A33#
D46#
FSB0_D45
AH4
E22
FSB0_A31
A32#
D45#
FSB0_D44
AG5
G21
FSB0_A30
AG4
A31#
D44#
F21
FSB0_D43
FSB0_A29
AG6
A30#
D43#
E21
FSB0_D42
FSB0_A28
A29#
D42#
FSB0_D41
AF4
F20
FSB0_A27
AF5
A28#
D41#
E19
FSB0_D40
A27#
D40#
FSB0_A26
AB4
A26#
D39#
E18
FSB0_D39
FSB0_A25
AC5
A25#
D38#
F18
FSB0_D38
FSB0_A24
AB5
A24#
D37#
F17
FSB0_D37
FSB0_A23
AA5
A23#
D36#
G17
FSB0_D36
FSB0_A22
AD6
A22#
D35#
G18
FSB0_D35
FSB0_A21
FSB0_D34
FSB0_A19
AA4
A21#
A20#Y4A19#Y6A18#W6A17#
FSB0_A17
AB6
A16#W5A15#V4A14#V5A13#U4A12#U5A11#T4A10#
FSB0_A11
FSB0_A12
FSB0_A13
FSB0_A18
FSB0_A14
FSB0_A16
FSB0_A20
FSB0_A15
LGA771
PART 1
FSB Signal
D34#
D33#
D32#
D31#
D30#
D29#
D28#
D27#
D26#
D25#
D24#
F15
F14
FSB0_D30
G14
FSB0_D29
FSB0_D27
FSB0_D28
G13
E13
FSB0_D25
FSB0_D26
D13
F12
FSB0_D24
E16
E15
FSB0_D33
FSB0_D32
G16
G15
FSB0_D31
FSB0_A10
FSB0_A8
FSB0_A9
U6
A9#T5A8#R4A7#M4A6#L4A5#L5A4#P6A3#
D23#
D22#
D21#
F11
E10
D10
FSB0_D22
FSB0_D23
FSB0_D21
FSB0_A7
FSB0_A4
FSB0_A3
FSB0_A6
FSB0_A5
M5
D20#D7D19#E9D18#F9D17#F8D16#G9D15#
FSB0_D17
FSB0_D19
FSB0_D20
FSB0_D18
FSB0_D16
P0VID5
P0VID6
P0VID4
P0VID3
AM5
AL4
AK4
AL6
VID6
VID5
VID4
GTLREF_DATA_C1
GTLREF_ADD_C1
GTLREF_DATA_C0
GTLREF_ADD_C0
D7#A7D6#B7D5#B6D4#A5D3#C6D2#A4D1#C5D0#
FSB0_D5
FSB0_D7
FSB0_D2
FSB0_D3
FSB0_D4
FSB0_D1
FSB0_D6
R1273 0 R1274 0 R1275 0 R1276 0
P0VID1
P0VID0
P0VID2
AM3
AL5
AM2
VID3
VID2
VID1
VID0
BPM5# BPM4# BPM3# BPM2# BPM1# BPM0#
REQ4# REQ3# REQ2# REQ1# REQ0#
TESTHI11 TESTHI10
TESTHI9 TESTHI8 TESTHI7 TESTHI6 TESTHI5 TESTHI4 TESTHI3 TESTHI2 TESTHI1 TESTHI0
BCLK1 BCLK0
RS2# RS1# RS0#
AP1# AP0# BR1# BR0#
PWRGOOD
COMP7 COMP6 COMP5 COMP4 COMP3 COMP2 COMP1 COMP0
DP3# DP2# DP1# DP0#
ADSTB1# ADSTB0# DSTBP3# DSTBP2# DSTBP1#
DSTBP0# DSTBN3# DSTBN2# DSTBN1# DSTBN0#
TEJAS
B4
FSB0_D0
CPU1A
CPU0_DISABLE_N54,65
P0_GTLREF_DATA1
F2
P0_GTLREF_ADD1
H2
P0_GTLREF_DATA0
G10
P0_GTLREF_ADD0
H1
FSB0_BPM_N5
AG3
FSB0_BPM_N4
AF2
FSB0_BPM_N3
AG2
FSB0_BPM_N2
AD2
FSB0_BPM_N1
AJ1
FSB0_BPM_N0
AJ2
FSB0_REQ_N4
J6
FSB0_REQ_N3
K6
FSB0_REQ_N2
M6
FSB0_REQ_N1
J5
FSB0_REQ_N0
K4
H_TESTHI11
L2
H_TESTHI10
P1
FSB0_BPMB_N2
G4
FSB0_BPMB_N3
G3 F24 G24 G26 G27 G25 F25 W3 F26
CK_H_P0_N
G28
CK_H_P0
F28
FSB0_RS2_N
A3
FSB0_RS1_N
F5
FSB0_RS0_N
B3
FSB0_AP1
U3
FSB0_AP0
U2
FSB0_BR_N1
H5
FSB0_BR_N0
F3
CPU_PWRGD
N1
H_COMP7
AE3
H_COMP6
Y3
H_COMP5
T2
H_COMP4
J2
H_COMP3
R1
H_COMP2
G2
H_COMP1
T1
H_COMP0
A13
FSB0_DP_N3
J17
FSB0_DP_N2
H16
FSB0_DP_N1
H15
FSB0_DP_N0
J16
FSB0_ADSTB_N1
AD5
FSB0_ADSTB_N0
R6
FSB0_DSTBP_N3
C17
FSB0_DSTBP_N2
G19
FSB0_DSTBP_N1
E12
FSB0_DSTBP_N0
B9
FSB0_DSTBN_N3
A16
FSB0_DSTBN_N2
G20
FSB0_DSTBN_N1
G12
FSB0_DSTBN_N0
C8
FSB_SMI#12,40,54
VCC0_SENSE 69
VSS0_SENSE 69
P0VID[6..0] FSB0_BPM_N[5..0] FSB0_REQ_N[4..0] FSB0_DP_N[3..0] FSB0_ADSTB_N[1..0] FSB0_DSTBP_N[3..0] FSB0_DSTBN_N[3..0]
R727 51 R728 51 R729 51 R730 51
H_TESTHI2
R731 51
H_TESTHI1
R732 51
CK_H_P0_N 58 CK_H_P0 58
FSB0_RS2_N 15 FSB0_RS1_N 15 FSB0_RS0_N 15
FSB0_AP1 15 FSB0_AP0 15 FSB0_BR_N1 15 FSB0_BR_N0 15 CPU_PWRGD 12,40,64
R705 49.9RST R706 49.9RST R734 49.9RST R736 49.9RST R737 49.9RST R738 49.9RST R739 49.9RST R740 49.9RST
P_VTT
CPU0 SMI Voltage Translation
R1385 220
6 1
FSB0_BPMB_N2 FSB0_BPMB_N3
P_VTT
U3026
VCC
A B4C BE
GND
PI5C3303
P0VID[6..0] 69 FSB0_BPM_N[5..0] 15,64 FSB0_REQ_N[4..0] 15 FSB0_DP_N[3..0] 15 FSB0_ADSTB_N[1..0] 15 FSB0_DSTBP_N[3..0] 15 FSB0_DSTBN_N[3..0] 15
FSB0_BPMB_N2 64 FSB0_BPMB_N3 64
P_VTT
Place BPMB Termination Near CPU
P_VTT
Max Length 1.2 inches
C1033 X_0.1u
P_VTT
R3387 X_220
2 5 3
P5V
CPU0_SMI_N
49.9RST
100RST
49.9RST
100RST
BE=High, C=B
5
4
3
2
Processor 0 Termination
Place Termination Close to CPU At End of Bus
P_VTT
R713 51 R714 51 R715 51 R717 51 R718 51
R719 51
R716 X_51
R735 X_51 R1380 X_220 R1381 X_220 R1382 X_220 R1383 X_220 R1384 X_220
R1386 220 R1277 300
R3384 510 R3385 510 R3386 510
P3V3_AUX
R1219 4.7K
Place BPM Termination Near CPU
P_VTT
R721 51 R722 51 R723 51 R724 51
P0_LL_ID0 P0_LL_ID1
P0_MS_ID1 P0_MS_ID0
P_VTT
800mV at 1.2V FSB Vtt
Minmum trace and width as wide as possible 12 mils
R742
P0_GTLREF_ADD0
R743
C1034 1u
P_VTT
800mV at 1.2V FSB Vtt
Minmum trace and width as wide as possible
R744
12 mils
P0_GTLREF_ADD1
R751
C1037 1u
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
RB1
0
C1035 220P
RB2
0
C1038 220P
P0 Intel LGA771 Signal
MS-9192
FSB0_BR_N1 FSB0_BR_N0 FSB0_GTL_IERR# FSB0_THERMTRIP_N FSB_FERR#
FSB0_RESET_N
FSB0_PROCHOT# CPU0_BOOT FSB_A20M# FSB_STPCLK# FSB_IGNNE# FSB_INIT# FSB_INTR
FSB_NMI CPU_PWRGD
FSB0_BSEL0 FSB0_BSEL1 FSB0_BSEL2
CPU0_SKTOCC#
FSB0_BPM_N3 FSB0_BPM_N2 FSB0_BPM_N1 FSB0_BPM_N0
R1206 X_4.7K
R703 X_51 R704 X_51
P0_GTLREF_DATA0
C1036 220P
P0_GTLREF_DATA1
C1039 220P
Last Revision Date:
Friday, April 27, 2007
Sheet
990
1
P3V3
R1207 X_4.7K
of
Rev
0A
Page 10
5
P0 Intel LGA771 Power
4
3
2
1
VCORE0
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
VCORE0
AF22
AF21
VCC
VCC
VCC
VCC
Y8
Y30
AF8
Y29
AF9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCU8VCCV8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCW8VCC
VCC
VCC
VCC
VCC
VCC
VCC
Y23
Y24
Y25
Y26
Y27
Y28
W30
W29
W28
W27
W26
W25
W24
W23
U25
U26
U27
U28
U29
U30
AH28
AH29
AH30
AH8
AH9
AJ11
AJ12
AJ14
AJ15
AJ18
AJ19
AJ21
AJ22
AJ25
AJ26
AJ8
AJ9
AK11
AK12
AK14
AK15
AK18
AK19
AK21
AK22
AK25
AK26
AK8
AK9
AL11
AL12
AL14
AL15
AL18
AL19
AL21
AL22
AL25
AL26
AL29
AL30
AL9
AM11
AM12
AM14
AM15
AM18
AM19
AM21
AM22
AM25
AM26
AM29
AM30
AM8
AM9
AN11
AN12
AN14
AN15
AN18
AN19
AN21
AN22
CPU1B
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCIOPLL
LGA771
PART 2 Power
VTTPWRGD
VTT_OUT1 VTT_OUT0
VCC
VCC
NONE
NONE
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCJ8VCCJ9VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCK8VCCL8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCM8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCN8VCCP8VCCR8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCT8VCC
VCC
J10
J11
J12
J13
J14
J15
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
T30
U23
U24
N29
N30
N23
N24
N25
N26
N27
N28
M29
M30
M23
M24
M25
M26
M27
M28
K30
K29
K28
K27
K26
T23
T24
T25
T26
T27
T28
T29
K25
K24
K23
J30
AN8
AN9
AN25
AN26
AN29
AN30
VCCA VSSA
VCCPLL
VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT
VTT_SEL
TEJAS
A23 B23 D23 C23
F30 E30 A25 A26 B25 B26 B27 B28 B29 B30 C25 C26 C27 C28 C29 C30 D25 D26 D27 D28 D29 D30
AM6 AA1 J1 F27
H0_VCCA H0_VSSA H0_VCCPLL
VTT_PWRGD
R3472 0
P_VTT
VTT_PWRGD 13,63
VTT_SELVTT_SEL0
Support Harpertown
&
Wolfdale
CPU
VTT_SEL 13,76
AH27
AH26
AH25
AH22
AH21
AH19
AH18
AH15
AH14
AH12
AH11
AG9
AG8
AG30
AG29
AG28
AG27
AG26
AG25
AG22
AG21
AG19
AG18
AG15
AG14
AG12
AG11
D D
VCORE0
AF19 AF18 AF15 AF14 AF12 AF11
AE9 AE23 AE22 AE21 AE19 AE18 AE15
C C
B B
AE14 AE12 AE11
AD8 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23
AC8 AC30 AC29 AC28 AC27 AC26 AC25 AC24 AC23
AB8
AA8
P_VTT
L17 10uH-0805-0.1A L18 10uH-0805-0.1A
A A
5
Minmum trace and width as wide as possible < 12 mils
C3128 22u-1206
P1V5
R62
0
C1020 103P
C3129 X_10u-1206
C1021
4.7u-0805
H0_VCCA
C1019 X_1u
H0_VSSA
H0_VCCPLL
C1022
4.7u-0805
4
P_VTT
C1029 10u-1206
C1030 10u-1206
3
C1031
0.1u
C1032
0.1u
P_VTT
C1025
0.1u
C1026
0.1u
C1027
0.1u
2
C1028
0.1u
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
P0 Intel LGA771 Power
Micro Star Restricted Secret
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
10 90
of
Rev
0A
Page 11
5
P0 Intel LGA771 GND
4
3
2
1
R702
B13
RESVDF6RESVD
VSS
VSS
AF3
AF30
R702
X_49.9RST
P5
E1
RESVDJ3RESVDN4RESVD
RESVD
VSS
VSS
VSS
AF6
AF7
AG10
AG13
Nocona-T Optional
VSS
AG16
D D
R555
C C
B B
X_0-0402
R1212
X_0
FSB0_BPMB_N1
F1 A12 A15 A18
A2 A21 A24
A6
A9
AA23 AA24 AA25 AA26 AA27 AA28 AA29
AA3
AA30
AA6 AA7
AB1 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30
AB7
AC3
AC6
AC7
AD4
AD7 AE10 AE13 AE16 AE17
AE2 AE20 AE24 AE25 AE26 AE27 AE28
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
D16
RESVDC9RESVD
VSS
VSS
AE29
AE30
A20
AE5
P0TESTIN
W2
RESVD
VSS
AE7
VSS
AC4
AE4
D14
E23
RESVD
VSS
VSS
AF24
AF25
F23
RESVDE5RESVDE6RESVDE7RESVD
VSS
VSS
VSS
AF26
AF27
AF28
AF29
VSS
E24
RESVD
RESVD
RESVDD1RESVD
RESVDG6RESVD
RESVDG5RESVD
VSS
VSS
VSS
VSS
VSS
VSS
AF10
AF13
AF16
AF17
AF20
AF23
Dempsey-T Dempsey/Woodcrest Stuffed No Stuffed
AN27
AN6
RESVD
VSS
AG23
AJ3
RESVD
VSS
AG24
AK3
RESVD
VSS
AG7
F29
RESVD
VSS
AH1
AN28
NONE
NONE
VSS
VSS
VSS
AH10
AH13
AH16
VSSY7VSSY5VSSY2VSSW7VSSW4VSSV7VSSV6VSS
VSS
VSS
VSS
AH17
AH20
AH23
AE6
AN5
RESVDN5RESVD
RESVD
VSS
VSS
VSS
AG17
AG20
TP92
V30
V29
VSSV3VSS
V28
VSS
V27
VSS
V26
V25
VSS
P0TESTIN
V24
V23
VSS
VSS
VSS
VSSU7VSSU1VSST7VSST6VSST3VSSR7VSSR5VSS
R733 51
P_VTT
R30
R29
R28
R27
R26
R25
R24
R23
P30
P29
P28
P27
P26
P25
P24
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSR2VSSP7VSSP4VSS
VSS
VSS
VSS
VSS
VSS
P23
VSS
VSS
VSSN7VSSN6VSSN3VSSM7VSSM1VSSL7VSSL6VSS
L30
L29
VSSL3VSS
L28
VSS
L27
VSS
L26
L25
VSS
LGA771
PART 3
GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ4
AH3
AH6
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
AJ24
AJ27
AJ28
AJ29
AH24
AJ30
AK10
AK13
AK16
AK17
AK2
AK20
AK23
AK24
AK27
AK28
AK29
AK30
AK5
AK7
AL10
AL13
AL16
AL17
AL20
AL23
AL24
AL27
AL28
AL3
AM1
AM10
AM13
AM16
AM17
AM20
AM23
AN1
AM4
AM7
AN10
AM24
AM27
AN13
AM28
Place BPMB Termination Near CPU
R745 51
VSS
VSS
AN24
R746 51
VSSB5VSS
VSSB1VSS
B8
B11
B14
VSS
VSS
B17
P_VTTRSVD_PECI 14,55,66
L24
L23
VSS
VSS
VSS
VSSK7VSSK5VSSK2VSSJ7VSSJ4VSSH9VSSH8VSSH7VSSH6VSSH3VSS
VSS
VSS
VSS
VSS
VSS
AN2
AN16
AN17
AN20
AN23
H29
VSS
B20
H28
B24
H27
VSS
VSS
FSB0_BPMB_N1 FSB0_BPMB_N0
H26
H25
H24
VSS
VSS
VSS
VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSSC4VSS
TEJAS
C7
CPU1C
H23 H22 H21 H20 H19 H18 H17 H14 H13 H12 H11 H10 G1 F7 F4 F22 F19 F16 F13 F10 E8 E29 E28 E27 E26 E25 E20 E2 E17 E14 E11 D9 D6 D5 D3 D24 D21 D18 D15 D12 C24 C22 C19 C16 C13 C10
FSB0_BPMB_N1 64 FSB0_BPMB_N0 64
FSB0_BPMB_N0
R556 X_0-0402
A A
Intel Document Title: Enterprise System Design Conference - Taipei REV. NO. 1.0 REF, NO. 19091
Page 142: For each Socket change new RSVD lands A24 and E29 Page 142: Connect W2 and U1 together on each Socket,
from VSS to no-connects on the motherboard
and terminate with a 51ohms resistor to VTT.
5
4
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
3
2
http://www.msi.com.tw
P0 Intel LGA771 GND
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
11 90
Rev
0A
of
Micro Star Restricted Secret
Page 12
5
4
3
2
1
P1 Intel LGA771 Signal
VCC1_SENSE2
D11
FSB1_D15
FSB1_D14
D14#
C12
AL8
VCC_DIE_SENSE2
D13#
B12
FSB1_D12
FSB1_D13
AL7
AN3
VCC_DIE_SENSE
VSS_DIE_SENSE2
D12#D8D11#
C11
FSB1_D11
VSS1_SENSE2 VCC1_SENSE1 VSS1_SENSE1
AN4
VSS_DIE_SENSE
D10#
D9#
B10
A11
FSB1_D10
FSB1_D9
FSB1_A[35..3]16
FSB1_DBI#[3..0]16
FSB1_D[63..0]16
D D
FSB1_FORCEPR#71
C C
FSB1_GTL_IERR#62 FSB1_PROCHOT#65
B B
A A
FSB1_A[35..3] FSB1_DBI#[3..0] FSB1_D[63..0]
FSB1_A29
A30#
D43#
FSB1_D42
AG6
E21
FSB1_A28
AF4
A29#
D42#
F20
FSB1_D41
A28#
D41#
FSB1_A27
AF5
A27#
D40#
E19
FSB1_D40
FSB1_A26
AB4
A26#
D39#
E18
FSB1_D39
FSB1_A25
AC5
A25#
D38#
F18
FSB1_D38
FSB1_A24
AB5
A24#
D37#
F17
FSB1_D37
FSB1_A23
AA5
A23#
D36#
G17
FSB1_D36
FSB1_A22
FSB1_D35
FSB1_A15
FSB1_A18
FSB1_A14
FSB1_A20
AD6
AA4
A22#
A21#
FSB1_A17
FSB1_A19
AB6
A20#Y4A19#Y6A18#W6A17#
FSB1_A13
FSB1_A12
FSB1_A16
A16#W5A15#V4A14#V5A13#U4A12#U5A11#T4A10#
LGA771
PART 1
FSB Signal
D35#
D34#
D33#
D32#
D31#
D30#
D29#
D28#
D27#
D26#
F15
F14
E16
G18
FSB1_D33
FSB1_D34
E15
G16
FSB1_D32
G15
FSB1_D31
FSB1_D30
G14
FSB1_D29
FSB1_D28
G13
FSB1_D26
FSB1_D27
E13
D13
FSB1_D25
FSB1_A33
FSB1_A31
FSB1_A30
FSB1_A32
FSB1_A34
FSB1_A35
AJ6
AJ5
AH5
AH4
AG5
AG4
A35#
A34#
A33#
A32#
D50#
D49#
D48#
D47#
D46#
A14
E22
D17
D20
D22
G22
FSB1_D47
FSB1_D46
FSB1_D48
FSB1_D49
FSB1_D45
FSB1_THERMTRIP_N 61
D45#
G21
FSB1_D44
A31#
D44#
F21
FSB1_D43
FSB1_DBI#0 FSB1_DBI#1 FSB1_DBI#2 FSB1_DBI#3
FSB1_RESET_N16,64
FSB1_RSP_N16
FSB1_BPRI_N16
FSB1_TRDY_N16
FSB1_DEFER_N16
FSB_A20M#9,40
FSB_NMI9,40 FSB_INTR9,40
FSB_IGNNE#9,40
FSB_STPCLK#9,40
FSB_INIT#9,40,67
XDP0_TCK09,64
XDP0_TDI_FSB164 XDP0_TDO_FSB164 XDP0_TMS_MAIN9,20,64
XDP0_TRST#9,20,64
FSB_FERR#9,40
FSB1_ADS_N16 FSB1_BNR_N16
FSB1_HIT_N16 CK_H_P1_N 58
FSB1_DBSY_N16
FSB1_DRDY_N16
FSB1_HITM_N16
FSB1_LOCK_N16
FSB1_BINIT_N16
FSB1_MCERR_N16
CPU1_SKTOCC#54,63,65
P1THERMDA265 P1THERMDC265
P1THERMDA65
P1THERMDC65
CPU_DBR_RST#9,64
CPU1_TESTBUS9
FSB1_VIDSEL63,71
P1_MS_ID163 P1_MS_ID063
FSB1_BSEL062 FSB1_BSEL162 FSB1_BSEL262
FSB1_RESET_N FSB1_RSP_N FSB1_BPRI_N FSB1_TRDY_N FSB1_DEFER_N
CPU1_SMI_N FSB_A20M# FSB1_FORCEPR# FSB_NMI FSB_INTR FSB_IGNNE# FSB_STPCLK# FSB_INIT#
XDP0_TCK0 XDP0_TDI_FSB1 XDP0_TDO_FSB1 XDP0_TMS_MAIN XDP0_TRST#
FSB1_GTL_IERR# FSB_FERR# FSB1_PROCHOT#
P1_THERMTRIP_N
FSB1_ADS_N FSB1_BNR_N FSB1_HIT_N FSB1_DBSY_N FSB1_DRDY_N FSB1_HITM_N FSB1_LOCK_N FSB1_BINIT_N FSB1_MCERR_N
CPU1_SKTOCC# P1THERMDA2 P1THERMDC2 P1THERMDA P1THERMDC
CPU_DBR_RST# CPU1_BOOT
CPU1_TESTBUS
P1_LL_ID1 P1_LL_ID0 P1_MS_ID1 P1_MS_ID0
FSB1_BSEL0 FSB1_BSEL1 FSB1_BSEL2
FSB1_D63 FSB1_D62 FSB1_D61 FSB1_D60 FSB1_D59 FSB1_D58 FSB1_D57 FSB1_D56 FSB1_D55 FSB1_D54
P1_THERMTRIP_N
A8 G11 D19 C20
G23
H4
G8
E3
G7
P2
K3 AK6
L1 K1 N2
M3
P3
AE1 AD1 AF1 AC1 AG1
AB2
R3
AL2
M2
D2 C2 D4 B2 C1 E4 C3
AD3 AB3
AE8 AJ7 AH7 AL1 AK1
AC2
Y1
AH2 AN7
AA2
V2 V1
W1
G29 H30 G30
B22 A22 A19 B19 B21 C21 B18 A17 B16 C18
R674 2.2
DBI0# DBI1# DBI2# DBI3#
RESET# RSP# BPRI# TRDY# DEFER#
SMI# A20M# FORCEPR# LINT1/NMI LINT0/INTR IGNNE# STPCLK# INIT#
TCK TDI TDO TMS TRST#
IERR# FERR#/PBE# PROCHOT# THERMTRIP#
ADS# BNR# HIT# DBSY# DRDY# HITM# LOCK# BINIT# MCERR#
SKTOCC# THERMDA2 THERMDC2 THERMDA THERMDC
DBR# BOOTSELECT
TEST_BUS VID_SELECT
LL_ID1 LL_ID0 MS_ID1 MS_ID0
BSEL0 BSEL1 BSEL2
D63# D62# D61# D60# D59# D58# D57# D56# D55# D54#
D53#
B15
FSB1_D53
D52#
C14
FSB1_D52
D51#
C15
FSB1_D51
FSB1_D50
FSB1_A21
FSB1_A11
D25#
FSB1_D24
U6
D24#
F12
F11
FSB1_D23 FSB1_A10
FSB1_A7
FSB1_A6
FSB1_A9
FSB1_A8
A9#T5A8#R4A7#M4A6#L4A5#L5A4#P6A3#
D23#
D22#
D21#
D20#D7D19#E9D18#F9D17#F8D16#G9D15#
E10
D10
FSB1_D19
FSB1_D20
FSB1_D21
FSB1_D22
FSB1_A5
FSB1_D18
FSB1_A4
FSB1_D17
FSB1_A3
M5
FSB1_D16
P1VID6
P1VID5
AM5
AL4
VID6
GTLREF_DATA_C1
GTLREF_ADD_C1
GTLREF_DATA_C0
GTLREF_ADD_C0
D8#
D7#A7D6#B7D5#B6D4#A5D3#C6D2#A4D1#C5D0#
A10
FSB1_D4
FSB1_D3
FSB1_D8
FSB1_D6
FSB1_D5
FSB1_D7
R1269 0 R1270 0 R1271 0 R1272 0
P1VID3
P1VID2
P1VID4
AK4
AL6
VID5
VID4
VID3
PWRGOOD
FSB1_D0
FSB1_D2
FSB1_D1
P1VID1
P1VID0
AM3
AL5
AM2
VID2
VID1
BPM5# BPM4# BPM3# BPM2# BPM1# BPM0#
REQ4# REQ3# REQ2# REQ1# REQ0#
TESTHI11 TESTHI10
TESTHI9 TESTHI8 TESTHI7 TESTHI6 TESTHI5 TESTHI4 TESTHI3 TESTHI2 TESTHI1 TESTHI0
BCLK1 BCLK0
RS2# RS1# RS0#
AP1# AP0# BR1# BR0#
COMP7 COMP6 COMP5 COMP4 COMP3 COMP2 COMP1 COMP0
DP3# DP2# DP1# DP0#
ADSTB1# ADSTB0# DSTBP3# DSTBP2# DSTBP1#
DSTBP0# DSTBN3# DSTBN2# DSTBN1# DSTBN0#
B4
CPU2A
VID0
TEJAS
F2 H2 G10 H1
AG3 AF2 AG2 AD2 AJ1 AJ2
J6 K6 M6 J5 K4
L2 P1 G4 G3 F24 G24 G26 G27 G25 F25 W3 F26
G28 F28
A3 F5 B3
U3 U2 H5 F3
N1 AE3 Y3 T2 J2 R1 G2 T1 A13
J17 H16 H15 J16
AD5 R6 C17 G19 E12 B9 A16 G20 G12 C8
CPU1_DISABLE_N54,65
P1_GTLREF_DATA1 P1_GTLREF_ADD1 P1_GTLREF_DATA0 P1_GTLREF_ADD0
FSB1_BPM_N5 FSB1_BPM_N4 FSB1_BPM_N3 FSB1_BPM_N2 FSB1_BPM_N1 FSB1_BPM_N0
FSB1_REQ_N4 FSB1_REQ_N3 FSB1_REQ_N2 FSB1_REQ_N1 FSB1_REQ_N0
FSB1_TESTHI11 FSB1_TESTHI10 FSB1_BPMB_N2 FSB1_BPMB_N3
FSB1_TESTHI2 FSB1_TESTHI1
CK_H_P1_N CK_H_P1
FSB1_RS2_N FSB1_RS1_N FSB1_RS0_N
FSB1_AP1 FSB1_AP0 FSB1_BR_N1 FSB1_BR_N0
H1_COMP7 H1_COMP6 H1_COMP5 H1_COMP4 H1_COMP3 H1_COMP2 H1_COMP1 H1_COMP0
FSB1_DP_N3 FSB1_DP_N2 FSB1_DP_N1 FSB1_DP_N0
FSB1_ADSTB_N1 FSB1_ADSTB_N0 FSB1_DSTBP_N3 FSB1_DSTBP_N2 FSB1_DSTBP_N1 FSB1_DSTBP_N0 FSB1_DSTBN_N3 FSB1_DSTBN_N2 FSB1_DSTBN_N1 FSB1_DSTBN_N0
FSB_SMI#9,40,54
VCC1_SENSE 71
VSS1_SENSE 71
P1VID[6..0] FSB1_BPM_N[5..0] FSB1_REQ_N[4..0] FSB1_DP_N[3..0] FSB1_ADSTB_N[1..0] FSB1_DSTBP_N[3..0] FSB1_DSTBN_N[3..0]
FSB1_BPMB_N2 FSB1_BPMB_N3
R681 51 R682 51 R683 51 R684 51
R685 51 R686 51
CK_H_P1 58 FSB1_RS2_N 16
FSB1_RS1_N 16 FSB1_RS0_N 16
FSB1_AP1 16 FSB1_AP0 16 FSB1_BR_N1 16 FSB1_BR_N0 16 CPU_PWRGD 9,40,64
R658 49.9RST R657 49.9RST R688 49.9RST R690 49.9RST R691 49.9RST R692 49.9RST R693 49.9RST R694 49.9RST
P_VTT
P_VTT
Place BPMB Termination Near CPU
P_VTT
CPU1 SMI Voltage Translation
U3027
A B4C BE
PI5C3303
VCC
GND
2 5 3
6 1
P1VID[6..0] 71 FSB1_BPM_N[5..0] 16,64 FSB1_REQ_N[4..0] 16 FSB1_DP_N[3..0] 16 FSB1_ADSTB_N[1..0] 16 FSB1_DSTBP_N[3..0] 16 FSB1_DSTBN_N[3..0] 16
FSB1_BPMB_N2 64 FSB1_BPMB_N3 64
Max Length 1.2 inches
C1012 X_0.1u
P_VTT
P5V
CPU1_SMI_N
R3391 X_220
49.9RST
100RST
49.9RST
100RST
BE=High, C=B
5
4
3
2
Processor 1 Termination
Place Termination Close to CPU At End of Bus
P_VTT
R673 51 R670 51 R672 51 R669 51 R671 51
R668 X_51 R689 X_51
R3388 510 R3389 510 R3390 510
P3V3_AUX
R1218 4.7K
Place BPM Termination Near CPU
P_VTT
R675 51 R676 51 R677 51 R678 51
P1_LL_ID0 P1_LL_ID1
P1_MS_ID1 P1_MS_ID0
P_VTT
800mV at 1.2V FSB Vtt
Minmum trace and width as wide as possible
R696
12 mils
P1_GTLREF_ADD0
R697
C1013 1u
P_VTT
800mV at 1.2V FSB Vtt
Minmum trace and width as wide as possible 12 mils
R698
P1_GTLREF_ADD1
R701
C1016 1u
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
R1196
C1014 220P
R699
C1017 220P
Micro Star Restricted Secret
P1 Intel LGA771 Signal
FSB1_BR_N1 FSB1_BR_N0 FSB1_GTL_IERR# FSB1_THERMTRIP_N FSB1_RESET_N
FSB1_PROCHOT# CPU1_BOOT
FSB1_BSEL0 FSB1_BSEL1 FSB1_BSEL2
CPU1_SKTOCC#
FSB1_BPM_N3 FSB1_BPM_N2 FSB1_BPM_N1 FSB1_BPM_N0
R1194 X_4.7K
R655 X_51 R656 X_51
0
0
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
P3V3
R1195 X_4.7K
P1_GTLREF_DATA0
C1015 220P
P1_GTLREF_DATA1
C1018 220P
of
12 90
Rev
0A
Page 13
5
4
3
2
1
P1 Intel LGA771 Power
VCORE1
D D
AH27
AH26
AH25
AH22
AH21
AH19
AH18
AH15
AH14
AH12
AH11
AG9
AG8
AG30
AG29
AG28
AG27
AG26
AG25
AG22
AG21
AG19
AG18
AG15
AG14
AG12
AG11
AF9
AF8
AF22
AF21
VCORE1
AF19 AF18 AF15 AF14 AF12 AF11
AE9 AE23 AE22 AE21 AE19 AE18 AE15 AE14
C C
B B
AE12 AE11
AD8 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23
AC8 AC30 AC29 AC28 AC27 AC26 AC25 AC24 AC23
AB8
AA8
VCORE1
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
VCC
VCC
VCC
VCC
Y8
Y30
Y29
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Y24
Y25
Y26
Y27
Y28
Y23
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCW8VCC
W26
W27
W28
W29
W30
VCC
VCC
VCC
VCC
VCC
VCC
VCCU8VCCV8VCC
VCC
VCC
VCC
U30
W23
W24
W25
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
U25
U26
U27
U28
U29
AH28
AH29
AH30
AH8
AH9
AJ11
AJ12
AJ14
AJ15
AJ18
AJ19
AJ21
AJ22
AJ25
AJ26
AJ8
AJ9
AK11
AK12
AK14
AK15
AK18
AK19
AK21
AK22
AK25
AK26
AK8
AK9
AL11
AL12
AL14
AL15
AL18
AL19
AL21
AL22
AL25
AL26
AL29
AL30
AL9
AM11
AM12
AM14
AM15
AM18
AM19
AM21
AM22
AM25
AM26
AM29
AM30
AM8
AM9
AN11
AN12
AN14
AN15
AN18
AN19
AN21
AN22
CPU2B
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
LGA771
PART 2 Power
VCC
VCCA VSSA
VCCPLL
VCCIOPLL
VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT
VTTPWRGD
VTT_OUT1 VTT_OUT0
VTT_SEL
A23 B23 D23 C23
F30 E30 A25 A26 B25 B26 B27 B28 B29 B30 C25 C26 C27 C28 C29 C30 D25 D26 D27 D28 D29 D30
AM6 AA1 J1 F27
H1_VCCA H1_VSSA H1_VCCPLL
P_VTT
VTT_PWRGD
VTT_SEL1 VTT_SEL
R3473 0
VTT_PWRGD 10,63
VTT_SEL 10,76
Support
VCC
J10
J11
J12
J13
J14
J15
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
T30
U23
U24
N29
N30
N23
N24
N25
N26
N27
N28
M29
M30
M23
M24
M25
M26
M27
M28
K30
K29
K28
K27
K26
T23
T24
T25
T26
T27
T28
T29
K25
K24
K23
J30
AN8
AN9
AN25
AN26
TEJAS
AN29
AN30
VCC
VCC
NONE
NONE
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCJ8VCCJ9VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCK8VCCL8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCM8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCN8VCCP8VCCR8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCT8VCC
Harpertown
&
Wolfdale
CPU
P_VTT
L15 10uH-0805-0.1A L16 10uH-0805-0.1A
A A
5
Minmum trace and width as wide as possible < 12 mils
C3130 22u-1206
P1V5
R55
0
C999 103P
4
C3131 X_10u-1206
C1000
4.7u-0805
H1_VCCA
C998 X_1u
H1_VSSA
H1_VCCPLL
C1001
4.7u-0805
P_VTT
C1008 10u-1206
3
C1009 10u-1206
C1010
0.1u
C1011
0.1u
P_VTT
C1004
0.1u
2
C1005
0.1u
C1006
0.1u
C1007
0.1u
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
P1 Intel LGA771 Power
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
13 90
of
Rev
0A
Page 14
5
P1 Intel LGA771 GND
4
3
2
1
R654
R654
X_49.9RST
E1
RESVDJ3RESVDN4RESVD
RESVD
VSS
VSS
VSS
AF6
AF7
VSS
AG10
P5
AG13
Nocona-T Optional
AE6
RESVDN5RESVD
VSS
VSS
AG16
AG17
VSS
A20
AE5
P1TESTIN
W2
RESVD
VSS
AE7
VSS
RESVDG5RESVD
VSS
AF10
RSVD_PECI 11,55,66
AC4
AE4
D14
E24
VSS
AF13
E23
RESVD
RESVD
RESVDD1RESVD
RESVD
RESVDG6RESVD
VSS
VSS
VSS
VSS
VSS
VSS
AF16
AF17
AF20
AF23
AF24
AF25
AF26
F23
RESVDE5RESVDE6RESVDE7RESVD
RESVDF6RESVD
VSS
VSS
VSS
VSS
VSS
AF3
AF27
AF28
AF29
B13
AF30
D D
FSB1_BPMB_N1
D16
F1
VSS
A12 A15 A18
A21 A24
R567
C C
B B
X_0-0402
AA23 AA24 AA25 AA26 AA27 AA28 AA29
AA3
AA30
AA6 AA7 AB1
AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30
AB7 AC3 AC6 AC7 AD4 AD7
AE10 AE13 AE16 AE17
AE2
AE20 AE24 AE25 AE26 AE27 AE28
RESVDC9RESVD VSS VSS VSS
A2
VSS VSS VSS
A6
VSS
A9
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS
AE29
AE30
Dempsey-T Dempsey/Woodcrest Stuffed No Stuffed
AN27
AN6
RESVD
VSS
AG23
AJ3
RESVD
VSS
AG24
AK3
AG7
F29
RESVD
RESVD
VSS
VSS
AH1
AN28
NONE
NONE
VSS
VSS
VSS
AH10
AH13
AH16
VSSY7VSSY5VSSY2VSSW7VSSW4VSSV7VSSV6VSS
VSS
VSS
VSS
VSS
AH3
AH17
AH20
AH23
AH24
VSS
AN5
RESVD
VSS
AG20
VSS
V30
V29
V28
VSSV3VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AH6
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
TP101
R741 51
P1TESTIN
V27
V26
V25
V24
V23
VSS
VSS
VSS
VSS
VSS
VSSU7VSSU1VSST7VSST6VSST3VSSR7VSSR5VSS
LGA771
PART 3
GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ4
AJ24
AJ27
AJ28
AJ29
AJ30
AK10
AK13
AK16
AK17
AK2
VSS
VSS
AK20
R30
VSS
AK23
R29
VSS
VSS
AK24
R28
VSS
VSS
AK27
R27
VSS
VSS
AK28
P_VTT
R26
R25
VSS
VSS
AK29
AK30
R24
VSS
VSS
AK5
VSS
VSS
R23
AK7
VSS
VSS
AL10
P30
VSSR2VSSP7VSSP4VSS
VSS
VSS
VSS
VSS
AL13
AL16
AL17
P29
VSS
VSS
AL20
P28
VSS
VSS
AL23
P27
VSS
VSS
AL24
P26
VSS
VSS
AL27
P25
VSS
VSS
AL28
P24
VSS
VSS
AL3
P23
VSS
VSSN7VSSN6VSSN3VSSM7VSSM1VSSL7VSSL6VSS
VSS
VSS
VSS
VSS
VSS
VSS
AM1
AM10
AM13
AM16
AM17
AM20
AM23
VSS
L30
L29
VSSL3VSS
VSS
VSS
VSS
VSS
AM4
AM24
AM27
AM28
Place BPMB Termination Near CPU
R747 51 R748 51
L23
VSS
VSSK7VSSK5VSSK2VSSJ7VSSJ4VSSH9VSSH8VSSH7VSSH6VSSH3VSS
VSS
VSSB5VSS
VSS
VSS
VSS
VSSB1VSS
B8
AN20
AN23
AN24
VSS
AN2
AN17
L28
AM7
P_VTT
L27
VSS
VSS
AN1
VSS
VSS
L26
AN10
VSS
VSS
L25
AN13
VSS
VSS
L24
VSS
VSS
AN16
B11
B14
VSS
VSS
B17
FSB1_BPMB_N1 FSB1_BPMB_N0
H29
H28
H27
H26
VSS
VSS
VSS
VSS
VSS
VSSC4VSS
C7
B20
B24
H25
H24
VSS
TEJAS
VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
CPU2C
H23 H22 H21 H20 H19 H18 H17 H14 H13 H12 H11 H10 G1 F7 F4 F22 F19 F16 F13 F10 E8 E29 E28 E27 E26 E25 E20 E2 E17 E14 E11 D9 D6 D5 D3 D24 D21 D18 D15 D12 C24 C22 C19 C16 C13 C10
FSB1_BPMB_N1 64 FSB1_BPMB_N0 64
FSB1_BPMB_N0
R568 X_0-0402
A A
Intel Document Title: Enterprise System Design Conference - Taipei REV. NO. 1.0 REF, NO. 19091
Page 142: For each Socket change new RSVD lands A24 and E29 Page 142: Connect W2 and U1 together on each Socket,
from VSS to no-connects on the motherboard
and terminate with a 51ohms resistor to VTT.
5
4
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
3
2
http://www.msi.com.tw
P1 Intel LGA771 GND
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
14 90
Rev
0A
of
Micro Star Restricted Secret
Page 15
5
4
3
2
1
Blackford FSB0
FSB0_D63 FSB0_D62 FSB0_D61 FSB0_D60
D D
C C
B B
A A
FSB0_D[63..0]9
FSB0_DBI#[3..0]9 FSB0_DSTBP_N[3..0]9 FSB0_DSTBN_N[3..0]9
5
FSB0_D[63..0] FSB0_DBI#[3..0] FSB0_DSTBP_N[3..0] FSB0_DSTBN_N[3..0]
CK_H_MCH58
CK_H_MCH_N58
4
FSB0_D59 FSB0_D58 FSB0_D57 FSB0_D56 FSB0_D55 FSB0_D54 FSB0_D53 FSB0_D52 FSB0_D51 FSB0_D50 FSB0_D49 FSB0_D48 FSB0_D47 FSB0_D46 FSB0_D45 FSB0_D44 FSB0_D43 FSB0_D42 FSB0_D41 FSB0_D40 FSB0_D39 FSB0_D38 FSB0_D37 FSB0_D36 FSB0_D35 FSB0_D34 FSB0_D33 FSB0_D32 FSB0_D31 FSB0_D30 FSB0_D29 FSB0_D28 FSB0_D27 FSB0_D26 FSB0_D25 FSB0_D24 FSB0_D23 FSB0_D22 FSB0_D21 FSB0_D20 FSB0_D19 FSB0_D18 FSB0_D17 FSB0_D16 FSB0_D15 FSB0_D14 FSB0_D13 FSB0_D12 FSB0_D11 FSB0_D10 FSB0_D9 FSB0_D8 FSB0_D7 FSB0_D6 FSB0_D5 FSB0_D4 FSB0_D3 FSB0_D2 FSB0_D1 FSB0_D0
FSB0_DBI#3 FSB0_DBI#2 FSB0_DBI#1 FSB0_DBI#0
FSB0_DSTBP_N3 FSB0_DSTBP_N2 FSB0_DSTBP_N1 FSB0_DSTBP_N0
FSB0_DSTBN_N3 FSB0_DSTBN_N2 FSB0_DSTBN_N1 FSB0_DSTBN_N0
CK_H_MCH CK_H_MCH_N
AE37 AE36 AH36 AG36
AF38 AE38 AH38
AJ38
AJ37 AG35 AK36
AL37
AL36
AL38
AJ34
AF37 AE28 AD29
AF28 AC31 AE29 AC30 AD30 AE31 AE32 AD35
AF33 AG32
AF31 AE34 AG30 AG33 AM37 AK35 AM34 AM38 AP38 AN36
AL35 AN35 AP36
AT37 AU36 AP34
AT36 AP35
AL34 AN33
AJ33 AG27 AG29 AM33 AH31
AJ30 AH32
AJ31
AL31 AK30 AN32 AH29 AK29 AH28
AL29
AJ28 AH37
AF30 AP37
AL32 AH35
AD33 AR38 AK33
AH34 AD32 AR37 AK32
AN17 AP17
BLACKFORD 4/11
FSB0_D63 FSB0_D62 FSB0_D61 FSB0_D60 FSB0_D59 FSB0_D58 FSB0_D57 FSB0_D56 FSB0_D55 FSB0_D54 FSB0_D53 FSB0_D52 FSB0_D51 FSB0_D50 FSB0_D49 FSB0_D48 FSB0_D47 FSB0_D46 FSB0_D45 FSB0_D44 FSB0_D43 FSB0_D42 FSB0_D41 FSB0_D40 FSB0_D39 FSB0_D38 FSB0_D37 FSB0_D36 FSB0_D35 FSB0_D34 FSB0_D33 FSB0_D32 FSB0_D31 FSB0_D30 FSB0_D29 FSB0_D28 FSB0_D27 FSB0_D26 FSB0_D25 FSB0_D24 FSB0_D23 FSB0_D22 FSB0_D21 FSB0_D20 FSB0_D19 FSB0_D18 FSB0_D17 FSB0_D16 FSB0_D15 FSB0_D14 FSB0_D13 FSB0_D12 FSB0_D11 FSB0_D10 FSB0_D9 FSB0_D8 FSB0_D7 FSB0_D6 FSB0_D5 FSB0_D4 FSB0_D3 FSB0_D2 FSB0_D1 FSB0_D0
FSB0_DBI3 FSB0_DBI2 FSB0_DBI1 FSB0_DBI0
FSB0_DSTBP3 FSB0_DSTBP2 FSB0_DSTBP1 FSB0_DSTBP0
FSB0_DSTBN3 FSB0_DSTBN2 FSB0_DSTBN1 FSB0_DSTBN0
CORECLKP CORECLKN
FSB 0
U45D
FSB0_A35 FSB0_A34 FSB0_A33 FSB0_A32 FSB0_A31 FSB0_A30 FSB0_A29 FSB0_A28 FSB0_A27 FSB0_A26 FSB0_A25 FSB0_A24 FSB0_A23 FSB0_A22 FSB0_A21 FSB0_A20 FSB0_A19 FSB0_A18 FSB0_A17 FSB0_A16 FSB0_A15 FSB0_A14 FSB0_A13 FSB0_A12 FSB0_A11 FSB0_A10
FSB0_A9 FSB0_A8 FSB0_A7 FSB0_A6 FSB0_A5 FSB0_A4 FSB0_A3
FSB0_REQ4 FSB0_REQ3 FSB0_REQ2 FSB0_REQ1 FSB0_REQ0
FSB0_ADSTB1 FSB0_ADSTB0
FSB0_BPRI_N FSB0_DEFER_N FSB0_RESET_N
FSB0_RS2 FSB0_RS1 FSB0_RS0
FSB0_RSP_N
FSB0_TRDY_N
FSB0_ADS_N
FSB0_AP1 FSB0_AP0
FSB0_BINIT_N
FSB0_BNR_N
FSB0_BPM5
FSB0_BPM4 FSB0_BREQ1 FSB0_BREQ0
FSB0_DBSY_N
FSB0_DP3 FSB0_DP2 FSB0_DP1 FSB0_DP0
FSB0_DRDY_N
FSB0_HIT_N
FSB0_HITM_N
FSB0_LOCK_N
FSB0_MCERR_N
PSEL2 PSEL1 PSEL0
FSB0_VREF
FSB0_VREF
FSB0_VREF
BLACKFORD G1
3
AV22 AU22 AR22 AP22 AV24 AT23 AU23 AV25 AT24 AR25 AU26 AT26 AT27 AU25 AU28 AR24 AR27 AP25 AV28 AF22 AG23 AF25 AH22 AL22 AJ22 AG24 AM22 AH23 AP26 AN26 AM25 AN24 AL25
AJ25 AJ24 AK24 AH25 AL26
AP23 AL23
AU34 AV34 AN30 AU31 AL28 AV31 AN27 AT32
AU29 AK26 AH26 AK27 AV30 AP29 AR28 AG26 AM28 AR30 AN29 AP31 AT33 AR31 AT29 AU32 AV33 AT30 AJ27
AB1 AB2 AC1
AF34 AM30 AM27
FSB0_A35 FSB0_A34 FSB0_A33 FSB0_A32 FSB0_A31 FSB0_A30 FSB0_A29 FSB0_A28 FSB0_A27 FSB0_A26 FSB0_A25 FSB0_A24 FSB0_A23 FSB0_A22 FSB0_A21 FSB0_A20 FSB0_A19 FSB0_A18 FSB0_A17 FSB0_A16 FSB0_A15 FSB0_A14 FSB0_A13 FSB0_A12 FSB0_A11 FSB0_A10 FSB0_A9 FSB0_A8 FSB0_A7 FSB0_A6 FSB0_A5 FSB0_A4 FSB0_A3
FSB0_REQ_N4 FSB0_REQ_N3 FSB0_REQ_N2 FSB0_REQ_N1 FSB0_REQ_N0
FSB0_ADSTB_N1 FSB0_ADSTB_N0
FSB0_BPRI_N FSB0_DEFER_N FSB0_RESET_N FSB0_RS2_N FSB0_RS1_N FSB0_RS0_N FSB0_RSP_N FSB0_TRDY_N
FSB0_ADS_N FSB0_AP1 FSB0_AP0 FSB0_BINIT_N FSB0_BNR_N FSB0_BPM_N5 FSB0_BPM_N4 FSB0_BR_N1 FSB0_BR_N0 FSB0_DBSY_N FSB0_DP_N3 FSB0_DP_N2 FSB0_DP_N1 FSB0_DP_N0 FSB0_DRDY_N FSB0_HIT_N FSB0_HITM_N FSB0_LOCK_N FSB0_MCERR_N
MCH_SEL2 MCH_SEL1 MCH_SEL0
FSB0_VREF
FSB0_BPRI_N 9 FSB0_DEFER_N 9 FSB0_RESET_N 9 FSB0_RS2_N 9 FSB0_RS1_N 9 FSB0_RS0_N 9 FSB0_RSP_N 9 FSB0_TRDY_N 9
FSB0_ADS_N 9
FSB0_BINIT_N 9 FSB0_BNR_N 9
FSB0_DBSY_N 9
FSB0_DRDY_N 9 FSB0_HIT_N 9 FSB0_HITM_N 9 FSB0_LOCK_N 9 FSB0_MCERR_N 9
MCH_SEL2 62 MCH_SEL1 62 MCH_SEL0 62
FSB0_A[35..3] FSB0_REQ_N[4..0] FSB0_ADSTB_N[1..0] FSB0_AP[1..0] FSB0_BPM_N[5..0] FSB0_BR_N[1..0] FSB0_DP_N[3..0]
FSB0_A[35..3] 9 FSB0_REQ_N[4..0] 9 FSB0_ADSTB_N[1..0] 9 FSB0_AP[1..0] 9 FSB0_BPM_N[5..0] 9,64 FSB0_BR_N[1..0] 9 FSB0_DP_N[3..0] 9
MCH FSB0 VREF CKTS
800mV at 1.2V FSB Vtt
P_VTT
2
Minmum trace and width as wide as possible 12 mils
R646
49.9RST
R651 100RST
C988 1u
R1267
0
C989 220P
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
Blackford FSB0
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
FSB0_VREF
C990 220P
15 90
of
Rev
0A
Page 16
5
Blackford FSB1
FSB1_D[63..0]12
D D
C C
MCH_FSB_SLWCTRL#63
FSB1_DBI#[3..0]12 FSB1_DSTBP_N[3..0]12 FSB1_DSTBN_N[3..0]12
MCH FSB SLEW Control
To Set FSB Slew Control Manually Follow Table Below:
B B
Stuffing Options SLEWMCH_FSB_SLEWCTRL
Roption = Stuffed Roption = Empty
A A
5
FSB1_D[63..0] FSB1_DBI#[3..0] FSB1_DSTBP_N[3..0] FSB1_DSTBN_N[3..0]
R1251 X_100
0 1
P1V5
R1266 1K
MCH_FSB_SLWCTRL
Q38
B
MMBT3904
E C
2.5V/ns
3.75 or 5V/ns
R3392 X_100
Roption
4
FSB1_D63 FSB1_D62 FSB1_D61 FSB1_D60 FSB1_D59 FSB1_D58 FSB1_D57 FSB1_D56 FSB1_D55 FSB1_D54 FSB1_D53 FSB1_D52 FSB1_D51 FSB1_D50 FSB1_D49 FSB1_D48 FSB1_D47 FSB1_D46 FSB1_D45 FSB1_D44 FSB1_D43 FSB1_D42 FSB1_D41 FSB1_D40 FSB1_D39 FSB1_D38 FSB1_D37 FSB1_D36 FSB1_D35 FSB1_D34 FSB1_D33 FSB1_D32 FSB1_D31 FSB1_D30 FSB1_D29 FSB1_D28 FSB1_D27 FSB1_D26 FSB1_D25 FSB1_D24 FSB1_D23 FSB1_D22 FSB1_D21 FSB1_D20 FSB1_D19 FSB1_D18 FSB1_D17 FSB1_D16 FSB1_D15 FSB1_D14 FSB1_D13 FSB1_D12 FSB1_D11 FSB1_D10 FSB1_D9 FSB1_D8 FSB1_D7 FSB1_D6 FSB1_D5 FSB1_D4 FSB1_D3 FSB1_D2 FSB1_D1 FSB1_D0
FSB1_DBI#3 FSB1_DBI#2 FSB1_DBI#1 FSB1_DBI#0
FSB1_DSTBP_N3 FSB1_DSTBP_N2 FSB1_DSTBP_N1 FSB1_DSTBP_N0
FSB1_DSTBN_N3 FSB1_DSTBN_N2 FSB1_DSTBN_N1 FSB1_DSTBN_N0
MCH_CORE_VCCA MCH_FSB_VCCA MCH_CORE_VSSA
4
AF16
AG14
AJ16 AJ15
AG15
AF15
AJ13 AL16 AP16 AH16 AN15 AL14
AM15
AN14
AM16
AH14 AP14 AR12 AR13 AP11 AP13 AT12 AT11 AV12 AV10 AU10
AV9 AT8 AR9 AT9 AU8
AV7 AK12 AL13 AL11
AM13
AN11
AM12
AN12
AN9
AN8
AP8
AM9 AM6
AK9
AN6
AL8
AL7 AU5 AR7 AU7 AR6 AT6 AV4 AV6 AT5 AT3 AT2 AR4 AR3 AR1 AP4 AP5 AP1
AH13 AU11 AK11
AP7
AK15 AR10
AM10
AU4
AK14 AP10 AL10
AU3
AT17 AU17 AU16
BLACKFORD 5/11
FSB1_D63 FSB1_D62 FSB1_D61 FSB1_D60 FSB1_D59 FSB1_D58 FSB1_D57 FSB1_D56 FSB1_D55 FSB1_D54 FSB1_D53 FSB1_D52 FSB1_D51 FSB1_D50 FSB1_D49 FSB1_D48 FSB1_D47 FSB1_D46 FSB1_D45 FSB1_D44 FSB1_D43 FSB1_D42 FSB1_D41 FSB1_D40 FSB1_D39 FSB1_D38 FSB1_D37 FSB1_D36 FSB1_D35 FSB1_D34 FSB1_D33 FSB1_D32 FSB1_D31 FSB1_D30 FSB1_D29 FSB1_D28 FSB1_D27 FSB1_D26 FSB1_D25 FSB1_D24 FSB1_D23 FSB1_D22 FSB1_D21 FSB1_D20 FSB1_D19 FSB1_D18 FSB1_D17 FSB1_D16 FSB1_D15 FSB1_D14 FSB1_D13 FSB1_D12 FSB1_D11 FSB1_D10 FSB1_D9 FSB1_D8 FSB1_D7 FSB1_D6 FSB1_D5 FSB1_D4 FSB1_D3 FSB1_D2 FSB1_D1 FSB1_D0
FSB1_DBI3 FSB1_DBI2 FSB1_DBI1 FSB1_DBI0
FSB1_DSTBP3 FSB1_DSTBP2 FSB1_DSTBP1 FSB1_DSTBP0
FSB1_DSTBN3 FSB1_DSTBN2 FSB1_DSTBN1 FSB1_DSTBN0
COREVCCA FSBVCCA COREVSSA
FSB 1
3
U45E
FSB1_A35 FSB1_A34 FSB1_A33 FSB1_A32 FSB1_A31 FSB1_A30 FSB1_A29 FSB1_A28 FSB1_A27 FSB1_A26 FSB1_A25 FSB1_A24 FSB1_A23 FSB1_A22 FSB1_A21 FSB1_A20 FSB1_A19 FSB1_A18 FSB1_A17 FSB1_A16 FSB1_A15 FSB1_A14 FSB1_A13 FSB1_A12 FSB1_A11 FSB1_A10
FSB1_A9 FSB1_A8 FSB1_A7 FSB1_A6 FSB1_A5 FSB1_A4 FSB1_A3
FSB1_REQ4 FSB1_REQ3 FSB1_REQ2 FSB1_REQ1 FSB1_REQ0
FSB1_ADSTB1 FSB1_ADSTB0
FSB1_BPRI_N FSB1_DEFER_N FSB1_RESET_N
FSB1_RS2 FSB1_RS1 FSB1_RS0
FSB1_RSP_N
FSB1_TRDY_N
FSB1_ADS_N
FSB1_AP1 FSB1_AP0
FSB1_BINIT_N
FSB1_BNR_N
FSB1_BPM5
FSB1_BPM4 FSB1_BREQ1 FSB1_BREQ0
FSB1_DBSY_N
FSB1_DP3 FSB1_DP2 FSB1_DP1 FSB1_DP0
FSB1_DRDY_N
FSB1_HIT_N
FSB1_HITM_N
FSB1_LOCK_N
FSB1_MCERR_N
FSBCRES
FSBODTCRES
FSBSLWCRES
FSBSLWCTRL
FSB1_VREF
FSB1_VREF
FSB1_VREF
BLACKFORD G1
3
FSB1_A35
AC3
FSB1_A34
AC4
FSB1_A33
AD2
FSB1_A32
AE1
FSB1_A31
AE2
FSB1_A30
AE4
FSB1_A29
AD3
FSB1_A28
AF3
FSB1_A27
AF1
FSB1_A26
AJ3
FSB1_A25
AH1
FSB1_A24
AH2
FSB1_A23
AD5
FSB1_A22
AC6
FSB1_A21
AE5
FSB1_A20
AD6
FSB1_A19
AH5
FSB1_A18
AG5
FSB1_A17
AF4
FSB1_A16
AA12
FSB1_A15
AC7
FSB1_A14
AB10
FSB1_A13
AC9
FSB1_A12
AD8
FSB1_A11
AF6
FSB1_A10
AB11
FSB1_A9
AE7
FSB1_A8
AF7
FSB1_A7
AG8
FSB1_A6
AH8
FSB1_A5
AC12
FSB1_A4
AD9
FSB1_A3
AD12
FSB1_REQ_N4
AE10
FSB1_REQ_N3
AF9
FSB1_REQ_N2
AJ6
FSB1_REQ_N1
AD11
FSB1_REQ_N0
AG9
FSB1_ADSTB_N1
AG3
FSB1_ADSTB_N0
AC10
FSB1_BPRI_N
AJ10
FSB1_DEFER_N
AJ9
FSB1_RESET_N
AE11
FSB1_RS2_N
AL5
FSB1_RS1_N
AL1
FSB1_RS0_N
AK5
FSB1_RSP_N
AK2
FSB1_TRDY_N
AK6
FSB1_ADS_N
AP2
FSB1_AP1
AG10
FSB1_AP0
AG12
FSB1_BINIT_N
AJ4
FSB1_BNR_N
AK3
FSB1_BPM_N5
AN3
FSB1_BPM_N4
AN2
FSB1_BR_N1
AM1
FSB1_BR_N0
AL2
FSB1_DBSY_N
AM4
FSB1_DP_N3
AF13
FSB1_DP_N2
AF12
FSB1_DP_N1
AJ12
FSB1_DP_N0
AG11
FSB1_DRDY_N
AM3
FSB1_HIT_N
AK8
FSB1_HITM_N
AJ7
FSB1_LOCK_N
AL4
FSB1_MCERR_N
AH11
MCH_FSB_CRES
AT35
MCH_FSB_ODTCRES
AR34
MCH_FSB_SLWCRES
AU35
MCH_FSB_SLWCTRL
AV13
FSB1_VREF
AT14 AN5 AH4
FSB1_BPRI_N 12 FSB1_DEFER_N 12 FSB1_RESET_N 12,64 FSB1_RS2_N 12 FSB1_RS1_N 12 FSB1_RS0_N 12 FSB1_RSP_N 12 FSB1_TRDY_N 12
FSB1_ADS_N 12
FSB1_BINIT_N 12 FSB1_BNR_N 12
FSB1_DBSY_N 12
FSB1_DRDY_N 12 FSB1_HIT_N 12 FSB1_HITM_N 12 FSB1_LOCK_N 12 FSB1_MCERR_N 12
2
FSB1_A[35..3] FSB1_REQ_N[4..0] FSB1_ADSTB_N[1..0] FSB1_AP[1..0] FSB1_BPM_N[5..0] FSB1_BR_N[1..0] FSB1_DP_N[3..0]
FSB1_A[35..3] 12 FSB1_REQ_N[4..0] 12 FSB1_ADSTB_N[1..0] 12 FSB1_AP[1..0] 12 FSB1_BPM_N[5..0] 12,64 FSB1_BR_N[1..0] 12 FSB1_DP_N[3..0] 12
MCH FSB PLL/COMP/VREF CKTS
MCH_FSB_CRES
R647 649RST
P_VTT
800mV at 1.2V FSB Vtt
Minmum trace and width as wide as possible 12 mils
R650
49.9RST
R652 100RST
Route MCH_CORE_VSSA Between MCH_FSB_VCCA and MCH_CORE_VCCA Width=25mils, Space=10mils
P1V5
P1V5
2
R649
0.499RST
R653
0.499RST
L13
4.7uH-0805-30mA
L14
4.7uH-0805-30mA
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
R648
49.9RST
MCH_FSB_ODTCRES MCH_FSB_SLWCRES
R1268
0
C991 22u-1206
C996 22u-1206
C994 220P
C993 1u
Micro Star Restricted Secret
Blackford FSB1
MS-9192
1
FSB1_VREF
C995 220P
MCH_FSB_VCCA
C992
0.1u
MCH_CORE_VSSA
MCH_CORE_VCCA
C997
0.1u
MCH_CORE_VSSA
Last Revision Date:
Friday, April 27, 2007
Sheet
16 90
1
Rev
0A
of
Page 17
5
4
3
2
1
Blackford FBD Interface 1
U45A
FBD_CH0_NB_P[13..0]23 FBD_CH0_NB_N[13..0]23
D D
C C
B B
A A
FBD_CH1_NB_P[13..0]26 FBD_CH1_NB_N[13..0]26
FBD_CH0_NB_P[13..0] FBD_CH0_NB_N[13..0] FBD_CH1_NB_P[13..0] FBD_CH1_NB_N[13..0] FBD_CH1_SB_N[9..0]
FBD01CLKP59 FBD01CLKN59
5
FBD_CH0_NB_P13 FBD_CH0_NB_P12 FBD_CH0_NB_P11 FBD_CH0_NB_P10
FBD_CH0_NB_P9 FBD_CH0_NB_P8
FBD_CH0_NB_P6 FBD_CH0_NB_P5 FBD_CH0_NB_P4 FBD_CH0_NB_P3 FBD_CH0_NB_P2 FBD_CH0_NB_P1 FBD_CH0_NB_P0
FBD_CH0_NB_N13 FBD_CH0_NB_N12 FBD_CH0_NB_N11 FBD_CH0_NB_N10
FBD_CH0_NB_N9 FBD_CH0_NB_N8 FBD_CH0_NB_N7 FBD_CH0_NB_N6 FBD_CH0_NB_N5 FBD_CH0_NB_N4 FBD_CH0_NB_N3 FBD_CH0_NB_N2 FBD_CH0_NB_N1
FBD_CH1_NB_P13 FBD_CH1_NB_P12 FBD_CH1_NB_P11 FBD_CH1_NB_P10
FBD_CH1_NB_P9 FBD_CH1_NB_P8 FBD_CH1_NB_P7 FBD_CH1_NB_P6 FBD_CH1_NB_P5 FBD_CH1_NB_P4 FBD_CH1_NB_P3 FBD_CH1_NB_P2 FBD_CH1_NB_P1 FBD_CH1_NB_P0
FBD_CH1_NB_N13 FBD_CH1_NB_N12 FBD_CH1_NB_N11 FBD_CH1_NB_N10
FBD_CH1_NB_N9 FBD_CH1_NB_N8 FBD_CH1_NB_N7 FBD_CH1_NB_N6 FBD_CH1_NB_N5 FBD_CH1_NB_N4 FBD_CH1_NB_N3 FBD_CH1_NB_N2 FBD_CH1_NB_N1 FBD_CH1_NB_N0
FBD01CLKP FBD01CLKN
FBD01VCCA FBD01VSSA
BLACKFORD 1/11
V29
FBD0NBIP13
U30
FBD0NBIP12
U36
FBD0NBIP11
V35
FBD0NBIP10
W34
FBD0NBIP9
U33
FBD0NBIP8
V32
FBD0NBIP7
T31
FBD0NBIP6
W28
FBD0NBIP5
U28
FBD0NBIP4
V27
FBD0NBIP3
AB31
FBD0NBIP2
Y30
FBD0NBIP1
Y27
FBD0NBIP0
V30
FBD0NBIN13
U31
FBD0NBIN12
U37
FBD0NBIN11
V36
FBD0NBIN10
W35
FBD0NBIN9
U34
FBD0NBIN8
V33
FBD0NBIN7
T32
FBD0NBIN6
W29
FBD0NBIN5
T28
FBD0NBIN4
U27
FBD0NBIN3
AB32
FBD0NBIN2
Y31
FBD0NBIN1
Y28
FBD0NBIN0
K31
FBD1NBIP13
M32
FBD1NBIP12
G38
FBD1NBIP11
H36
FBD1NBIP10
F36
FBD1NBIP9
J35
FBD1NBIP8
K34
FBD1NBIP7
L33
FBD1NBIP6
L30
FBD1NBIP5
M29
FBD1NBIP4
N28
FBD1NBIP3
L27
FBD1NBIP2
M26
FBD1NBIP1
P27
FBD1NBIP0
K32
FBD1NBIN13
N32
FBD1NBIN12
H38
FBD1NBIN11
H37
FBD1NBIN10
F37
FBD1NBIN9
K35
FBD1NBIN8
L34
FBD1NBIN7
M33
FBD1NBIN6
L31
FBD1NBIN5
M30
FBD1NBIN4
N29
FBD1NBIN3
L28
FBD1NBIN2
M27
FBD1NBIN1
P28
FBD1NBIN0
R38
FBD01CLKP
T38
FBD01CLKN
T35
FBD01VCCA
T34
FBD01VSSA
4
FBD0SBOP9 FBD0SBOP8 FBD0SBOP7 FBD0SBOP6 FBD0SBOP5 FBD0SBOP4 FBD0SBOP3 FBD0SBOP2 FBD0SBOP1 FBD0SBOP0
Northbound
Southbound
FBD0SBON9 FBD0SBON8
Channel 0
FBD0SBON7 FBD0SBON6 FBD0SBON5 FBD0SBON4 FBD0SBON3 FBD0SBON2 FBD0SBON1 FBD0SBON0
FBD1SBOP9 FBD1SBOP8 FBD1SBOP7 FBD1SBOP6 FBD1SBOP5 FBD1SBOP4 FBD1SBOP3 FBD1SBOP2 FBD1SBOP1
Northbound
FBD1SBOP0
Southbound
FBD1SBON9
Channel 1
FBD1SBON8 FBD1SBON7 FBD1SBON6 FBD1SBON5 FBD1SBON4 FBD1SBON3 FBD1SBON2 FBD1SBON1 FBD1SBON0
FBD0SCL FBD0SDA
FBD1SCL FBD1SDA
FBDICOMPBIAS
FBDRESIN
FBDBGBIASEXT
BLACKFORD G1
AA36 AC34 AB35 AB37 AA38 Y36 Y34 AA32 V38 W32
AA35 AC33 AB34 AC37 AB38 Y37 Y33 AA33 W38 W31
N38 R33 P34 R36 P37 N34 M35 K38 L36 J36
N37 R32 P33 R35 P36 N35 M36 L38 L37 J37
H13 G13
J16 K15
F35 E36 E37
FBD_CH0_SB_P9 FBD_CH0_SB_P8 FBD_CH0_SB_P7 FBD_CH0_SB_P6 FBD_CH0_SB_P5 FBD_CH0_SB_P4 FBD_CH0_SB_P3FBD_CH0_NB_P7 FBD_CH0_SB_P2 FBD_CH0_SB_P1 FBD_CH0_SB_P0
FBD_CH0_SB_N9 FBD_CH0_SB_N8 FBD_CH0_SB_N7 FBD_CH0_SB_N6 FBD_CH0_SB_N5 FBD_CH0_SB_N4 FBD_CH0_SB_N3 FBD_CH0_SB_N2 FBD_CH0_SB_N1 FBD_CH0_SB_N0FBD_CH0_NB_N0
FBD_CH1_SB_P9 FBD_CH1_SB_P8 FBD_CH1_SB_P7 FBD_CH1_SB_P6 FBD_CH1_SB_P5 FBD_CH1_SB_P4 FBD_CH1_SB_P3 FBD_CH1_SB_P2 FBD_CH1_SB_P1 FBD_CH1_SB_P0
FBD_CH1_SB_N9 FBD_CH1_SB_N8 FBD_CH1_SB_N7 FBD_CH1_SB_N6 FBD_CH1_SB_N5 FBD_CH1_SB_N4 FBD_CH1_SB_N3 FBD_CH1_SB_N2 FBD_CH1_SB_N1 FBD_CH1_SB_N0
FBD0SCL FBD0SDA
FBD1SCL FBD1SDA
FBDICOMBIAS FBDRESIN FBDBGBIASEXT
FBD0SCL 23,24,25 FBD0SDA 23,24,25
FBD1SCL 26,27,28 FBD1SDA 26,27,28
3
FBD_CH0_SB_P[9..0] FBD_CH0_SB_N[9..0] FBD_CH1_SB_P[9..0]
FBD0SDA FBD0SCL FBD1SCL FBD1SDA
FBD_CH0_SB_P[9..0] 23 FBD_CH0_SB_N[9..0] 23 FBD_CH1_SB_P[9..0] 26 FBD_CH1_SB_N[9..0] 26
RN17
1 2 3 4 5 6 7 8
4.7K-8P4R
P3V3
P3V3
MCH FBD PLL/COMP CKTS
P1V5
R639
R640
100RST
100RST
R644
R645
51.1RST
121RST
Route FBD VCCA with Corresponding VSSA As Differential Pair Width=25mils, Space=10mils
P1V5
R643
0.499RST
L12
4.7uH-0805-30mA C986 22u-1206
SMBus Selector
Address : 1110 001Z
U3028
C3228
0.1u
19
SDA
18
SCL
1
A0
2
A1
3
A2
P3V3
20
VDD
10
VSS
PHL-PCA9544-SO20
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
SDA0
SCL0
SDA1
SCL1
SDA2
SCL2
SDA3
SCL3
INT0 INT1 INT2 INT3
INTOUT
Micro Star Restricted Secret
SMBDAT_FBD54 SMBCLK_FBD54
2
R3279 100 R3280 100 R3281 100
R641 100RST
FBDRESIN FBDBGBIASEXT FBDICOMBIAS
FBD01VCCA
C987
0.1u
FBD01VSSA
FBD0SDA
5
FBD0SCL
6
FBD1SDA
8
FBD1SCL
9
FBD2SDA
12
FBD2SCL
13
FBD3SDA
15
FBD3SCL
16 4
7 11 14
17
Blackford FBD Interface1
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
FBD2SDA 18,29,30,31 FBD2SCL 18,29,30,31
FBD3SDA 18,32,33,34 FBD3SCL 18,32,33,34
Rev
0A
17 90
of
Page 18
5
4
3
2
1
Blackford FBD Interface 2
FBD_CH2_NB_P[13..0]29
D D
C C
B B
A A
FBD_CH2_NB_N[13..0]29 FBD_CH3_NB_P[13..0]32 FBD_CH3_NB_N[13..0]32
5
FBD_CH2_NB_P[13..0] FBD_CH2_NB_N[13..0] FBD_CH3_NB_P[13..0] FBD_CH3_NB_N[13..0]
FBD_CH2_NB_P13 FBD_CH2_NB_P12 FBD_CH2_NB_P11 FBD_CH2_NB_P10 FBD_CH2_NB_P9 FBD_CH2_NB_P8 FBD_CH2_NB_P7 FBD_CH2_NB_P6 FBD_CH2_NB_P5 FBD_CH2_NB_P4 FBD_CH2_NB_P3 FBD_CH2_NB_P2 FBD_CH2_NB_P1 FBD_CH2_NB_P0
FBD_CH2_NB_N13 FBD_CH2_NB_N12 FBD_CH2_NB_N11 FBD_CH2_NB_N10
FBD_CH2_NB_N9 FBD_CH2_NB_N8 FBD_CH2_NB_N7 FBD_CH2_NB_N6 FBD_CH2_NB_N5 FBD_CH2_NB_N4 FBD_CH2_NB_N3 FBD_CH2_NB_N2 FBD_CH2_NB_N1 FBD_CH2_NB_N0
FBD_CH3_NB_P13 FBD_CH3_NB_P12 FBD_CH3_NB_P11 FBD_CH3_NB_P10 FBD_CH3_NB_P9 FBD_CH3_NB_P8 FBD_CH3_NB_P7 FBD_CH3_NB_P6 FBD_CH3_NB_P5 FBD_CH3_NB_P4 FBD_CH3_NB_P3 FBD_CH3_NB_P2 FBD_CH3_NB_P1 FBD_CH3_NB_P0
FBD_CH3_NB_N13 FBD_CH3_NB_N12 FBD_CH3_NB_N11 FBD_CH3_NB_N10
FBD_CH3_NB_N9 FBD_CH3_NB_N8 FBD_CH3_NB_N7 FBD_CH3_NB_N6 FBD_CH3_NB_N5 FBD_CH3_NB_N4 FBD_CH3_NB_N3 FBD_CH3_NB_N2 FBD_CH3_NB_N1 FBD_CH3_NB_N0
FBD23CLKP59 FBD23CLKN59
FBD23CLKP FBD23CLKN
FBD23VCCA FBD23VSSA
4
BLACKFORD 2/11
C31
FBD2NBIP13
B32
FBD2NBIP12
D38
FBD2NBIP11
C37
FBD2NBIP10
C36
FBD2NBIP9
B35
FBD2NBIP8
C34
FBD2NBIP7
B33
FBD2NBIP6
B30
FBD2NBIP5
B29
FBD2NBIP4
C28
FBD2NBIP3
B27
FBD2NBIP2
B26
FBD2NBIP1
C25
FBD2NBIP0
B31
FBD2NBIN13
A32
FBD2NBIN12
E38
FBD2NBIN11
D37
FBD2NBIN10
B36
FBD2NBIN9
A35
FBD2NBIN8
B34
FBD2NBIN7
A33
FBD2NBIN6
A30
FBD2NBIN5
A29
FBD2NBIN4
B28
FBD2NBIN3
A27
FBD2NBIN2
A26
FBD2NBIN1
B25
FBD2NBIN0
D20
FBD3NBIP13
C21
FBD3NBIP12
D25
FBD3NBIP11
E24
FBD3NBIP10
F23
FBD3NBIP9
A24
FBD3NBIP8
D23
FBD3NBIP7
B22
FBD3NBIP6
D19
FBD3NBIP5
A19
FBD3NBIP4
B18
FBD3NBIP3
C17
FBD3NBIP2
F18
FBD3NBIP1
G20
FBD3NBIP0
C20
FBD3NBIN13
B21
FBD3NBIN12
D26
FBD3NBIN11
E25
FBD3NBIN10
F24
FBD3NBIN9
B24
FBD3NBIN8
C23
FBD3NBIN7
A22
FBD3NBIN6
E19
FBD3NBIN5
B19
FBD3NBIN4
C18
FBD3NBIN3
D17
FBD3NBIN2
E18
FBD3NBIN1
F20
FBD3NBIN0
D28
FBD23CLKP
E28
FBD23CLKN
E27
FBD23VCCA
F27
FBD23VSSA
Northbound
Channel 2
Northbound
Channel 3
U45B
FBD2SBOP9 FBD2SBOP8 FBD2SBOP7 FBD2SBOP6 FBD2SBOP5 FBD2SBOP4 FBD2SBOP3 FBD2SBOP2 FBD2SBOP1 FBD2SBOP0
Southbound
FBD2SBON9 FBD2SBON8 FBD2SBON7 FBD2SBON6 FBD2SBON5 FBD2SBON4 FBD2SBON3 FBD2SBON2 FBD2SBON1 FBD2SBON0
FBD3SBOP9 FBD3SBOP8 FBD3SBOP7 FBD3SBOP6 FBD3SBOP5 FBD3SBOP4 FBD3SBOP3 FBD3SBOP2 FBD3SBOP1 FBD3SBOP0
Southbound
FBD3SBON9 FBD3SBON8 FBD3SBON7 FBD3SBON6 FBD3SBON5 FBD3SBON4 FBD3SBON3 FBD3SBON2 FBD3SBON1 FBD3SBON0
FBD2SCL FBD2SDA
FBD3SCL FBD3SDA
BLACKFORD G1
3
FBD_CH2_SB_P9
E33
FBD_CH2_SB_P8
J32
FBD_CH2_SB_P7
H33
FBD_CH2_SB_P6
G34
FBD_CH2_SB_P5
D34
FBD_CH2_SB_P4
F32
FBD_CH2_SB_P3
D31
FBD_CH2_SB_P2
E30
FBD_CH2_SB_P1
F29
FBD_CH2_SB_P0
G28
FBD_CH2_SB_N9
E34
FBD_CH2_SB_N8
J33
FBD_CH2_SB_N7
H34
FBD_CH2_SB_N6
G35
FBD_CH2_SB_N5
D35
FBD_CH2_SB_N4
F33
FBD_CH2_SB_N3
D32
FBD_CH2_SB_N2
E31
FBD_CH2_SB_N1
F30
FBD_CH2_SB_N0
G29
FBD_CH3_SB_P9
H22
FBD_CH3_SB_P8
K19
FBD_CH3_SB_P7
H18
FBD_CH3_SB_P6
G19
FBD_CH3_SB_P5
J21
FBD_CH3_SB_P4
G23
FBD_CH3_SB_P3
J24
FBD_CH3_SB_P2
H25
FBD_CH3_SB_P1
G26
FBD_CH3_SB_P0
D22
FBD_CH3_SB_N9
H21
FBD_CH3_SB_N8
K18
FBD_CH3_SB_N7
J18
FBD_CH3_SB_N6
H19
FBD_CH3_SB_N5
J20
FBD_CH3_SB_N4
G22
FBD_CH3_SB_N3
J23
FBD_CH3_SB_N2
H24
FBD_CH3_SB_N1
G25
FBD_CH3_SB_N0
E22
F15 E15
H15 H16
FBD2SCL FBD2SDA
FBD3SCL FBD3SDA
FBD_CH2_SB_P[9..0] FBD_CH2_SB_N[9..0] FBD_CH3_SB_P[9..0] FBD_CH3_SB_N[9..0]
FBD2SCL 17,29,30,31 FBD2SDA 17,29,30,31
FBD3SCL 17,32,33,34 FBD3SDA 17,32,33,34
FBD_CH2_SB_P[9..0] 29 FBD_CH2_SB_N[9..0] 29 FBD_CH3_SB_P[9..0] 32 FBD_CH3_SB_N[9..0] 32
P1V5
2
Route FBD VCCA with Corresponding VSSA As Differential Pair Width=25mils, Space=10mils
R642
0.499RST
L11
4.7uH-0805-30mA
FBD2SDA FBD2SCL FBD3SDA FBD3SCL
C984 22u-1206
RN16
1 2 3 4 5 6 7 8
4.7K-8P4R
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
Blackford FBD Interface2
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
FBD23VCCA
C985
0.1u
FBD23VSSA
P3V3
18 90
of
Rev
0A
Page 19
5
4
3
2
1
Blackford PCI-E Interface
MCH_EXP0_RXP336 MCH_EXP0_RXP236 MCH_EXP0_RXP136
D D
C C
B B
A A
MCH_EXP0_RXP036 MCH_EXP0_RXN336
MCH_EXP0_RXN236 MCH_EXP0_RXN136 MCH_EXP0_RXN036
MCH_EXP2_RXP336 MCH_EXP2_RXP236 MCH_EXP2_RXP136 MCH_EXP2_RXP036
MCH_EXP2_RXN336 MCH_EXP2_RXN236 MCH_EXP2_RXN136 MCH_EXP2_RXN036
MCH_EXP3_RXP336 MCH_EXP3_RXP236 MCH_EXP3_RXP136 MCH_EXP3_RXP036
MCH_EXP3_RXN336 MCH_EXP3_RXN236 MCH_EXP3_RXN136 MCH_EXP3_RXN036
MCH_EXP4_RXP351 MCH_EXP4_RXP251 MCH_EXP4_RXP151 MCH_EXP4_RXP051
MCH_EXP4_RXN351 MCH_EXP4_RXN251 MCH_EXP4_RXN151 MCH_EXP4_RXN051
MCH_EXP5_RXP351 MCH_EXP5_RXP251 MCH_EXP5_RXP151 MCH_EXP5_RXP051
MCH_EXP5_RXN351 MCH_EXP5_RXN251 MCH_EXP5_RXN151 MCH_EXP5_RXN051
MCH_EXP6_RXP351 MCH_EXP6_RXP251 MCH_EXP6_RXP151 MCH_EXP6_RXP051
MCH_EXP6_RXN351 MCH_EXP6_RXN251 MCH_EXP6_RXN151 MCH_EXP6_RXN051
MCH_EXP7_RXP351 MCH_EXP7_RXP251 MCH_EXP7_RXP151 MCH_EXP7_RXP051
MCH_EXP7_RXN351 MCH_EXP7_RXN251 MCH_EXP7_RXN151 MCH_EXP7_RXN051
MCH_100CLK_P58 MCH_100CLK_N58
5
MCH_EXP0_RXP3 MCH_EXP0_RXP2 MCH_EXP0_RXP1 MCH_EXP0_RXP0
MCH_EXP0_RXN3 MCH_EXP0_RXN2 MCH_EXP0_RXN1 MCH_EXP0_RXN0
MCH_EXP2_RXP3 MCH_EXP2_RXP2 MCH_EXP2_RXP1 MCH_EXP2_RXP0
MCH_EXP2_RXN3 MCH_EXP2_RXN2 MCH_EXP2_RXN1 MCH_EXP2_RXN0
MCH_EXP3_RXP3 MCH_EXP3_RXP2 MCH_EXP3_RXP1 MCH_EXP3_RXP0
MCH_EXP3_RXN3 MCH_EXP3_RXN2 MCH_EXP3_RXN1 MCH_EXP3_RXN0
MCH_EXP4_RXP3 MCH_EXP4_RXP2 MCH_EXP4_RXP1 MCH_EXP4_RXP0
MCH_EXP4_RXN3 MCH_EXP4_RXN2 MCH_EXP4_RXN1 MCH_EXP4_RXN0
MCH_EXP5_RXP3 MCH_EXP5_RXP2 MCH_EXP5_RXP1 MCH_EXP5_RXP0
MCH_EXP5_RXN3 MCH_EXP5_RXN2 MCH_EXP5_RXN1 MCH_EXP5_RXN0
MCH_EXP6_RXP3 MCH_EXP6_RXP2 MCH_EXP6_RXP1 MCH_EXP6_RXP0
MCH_EXP6_RXN3 MCH_EXP6_RXN2 MCH_EXP6_RXN1 MCH_EXP6_RXN0
MCH_EXP7_RXP3 MCH_EXP7_RXP2 MCH_EXP7_RXP1 MCH_EXP7_RXP0
MCH_EXP7_RXN3 MCH_EXP7_RXN2 MCH_EXP7_RXN1 MCH_EXP7_RXN0
MCH_100CLK_P MCH_100CLK_N
MCH_PE_VCCA MCH_PE_VSSA
MCH_PE_VSSBG MCH_PE_VCCBG
BLACKFORD 3/11
AA5
PE0RP3
AB8
PE0RP2
Y4
PE0RP1
Y10
PE0RP0
AA6
PE0RN3
AB7
PE0RN2
Y3
PE0RN1
Y9
PE0RN0
T1
PE2RP3
P3
PE2RP2
N4
PE2RP1
T5
PE2RP0
U1
PE2RN3
R3
PE2RN2
P4
PE2RN1
R5
PE2RN0
U9
PE3RP3
W7
PE3RP2
V5
PE3RP1
V2
PE3RP0
U10
PE3RN3
W8
PE3RN2
V6
PE3RN1
W2
PE3RN0
K10
PE4RP3
D10
PE4RP2
G11
PE4RP1
F12
PE4RP0
L10
PE4RN3
E10
PE4RN2
F11
PE4RN1
E12
PE4RN0
G7
PE5RP3
F8
PE5RP2
C9
PE5RP1
H10
PE5RP0
H7
PE5RN3
G8
PE5RN2
B9
PE5RN1
G10
PE5RN0
J8
PE6RP3
F6
PE6RP2
E4
PE6RP1
C6
PE6RP0
K8
PE6RN3
F5
PE6RN2
E3
PE6RN1
C5
PE6RN0
K4
PE7RP3
H3
PE7RP2
D1
PE7RP1
F3
PE7RP0
L4
PE7RN3
H4
PE7RN2
E1
PE7RN1
F2
PE7RN0
J2
PECLKP
K2
PECLKN
K1
PEVCCA
L1
PEVSSA
N11
PEVSSBG
R11
PEVCCBG
4
PORT0
PORT2PORT3PORT4PORT5PORT6PORT7
U45C
PE0TP3 PE0TP2 PE0TP1 PE0TP0
PE0TN3 PE0TN2 PE0TN1 PE0TN0
PE2TP3 PE2TP2 PE2TP1 PE2TP0
PE2TN3 PE2TN2 PE2TN1 PE2TN0
PE3TP3 PE3TP2 PE3TP1 PE3TP0
PE3TN3 PE3TN2 PE3TN1 PE3TN0
PE4TP3 PE4TP2 PE4TP1 PE4TP0
PE4TN3 PE4TN2 PE4TN1 PE4TN0
PE5TP3 PE5TP2 PE5TP1 PE5TP0
PE5TN3 PE5TN2 PE5TN1 PE5TN0
PE6TP3 PE6TP2 PE6TP1 PE6TP0
PE6TN3 PE6TN2 PE6TN1 PE6TN0
PE7TP3 PE7TP2 PE7TP1 PE7TP0
PE7TN3 PE7TN2 PE7TN1 PE7TN0
PEICOMPI
PERCOMPO
PEWIDTH3 PEWIDTH2 PEWIDTH1 PEWIDTH0
BLACKFORD G1
AA8 AB4 AA3 Y7
AA9 AB5 AA2 Y6
R2 N1 U4 T8
T2 P1 T4 T7
V8 U6 W5 U3
V9 U7 W4 V3
J11 C11 C12 H12
K11 D11 B12 J12
D7 D8 F9 J9
E7 C8 E9 H9
H6 C3 D5 M9
J6 C2 D4 M8
J5 K7 G2 G5
K5 L7 G1 G4
R12 P12
W10 W11 Y12 AA11
MCH_E0_TXP3 MCH_E0_TXP2 MCH_E0_TXP1 MCH_E0_TXP0
MCH_E0_TXN3 MCH_E0_TXN2 MCH_E0_TXN1 MCH_E0_TXN0
MCH_E2_TXP3 MCH_E2_TXP2 MCH_E2_TXP1 MCH_E2_TXP0
MCH_E2_TXN3 MCH_E2_TXN2 MCH_E2_TXN1 MCH_E2_TXN0
MCH_E3_TXP3 MCH_E3_TXP2 MCH_E3_TXP1 MCH_E3_TXP0
MCH_E3_TXN3 MCH_E3_TXN2 MCH_E3_TXN1 MCH_E3_TXN0
MCH_E4_TXP3 MCH_E4_TXP2 MCH_E4_TXP1 MCH_E4_TXP0
MCH_E4_TXN3 MCH_E4_TXN2 MCH_E4_TXN1 MCH_E4_TXN0
MCH_E5_TXP3 MCH_E5_TXP2 MCH_E5_TXP1 MCH_E5_TXP0
MCH_E5_TXN3 MCH_E5_TXN2 MCH_E5_TXN1 MCH_E5_TXN0
MCH_E6_TXP3 MCH_E6_TXP2 MCH_E6_TXP1 MCH_E6_TXP0
MCH_E6_TXN3 MCH_E6_TXN2 MCH_E6_TXN1 MCH_E6_TXN0
MCH_E7_TXP3 MCH_E7_TXP2 MCH_E7_TXP1 MCH_E7_TXP0
MCH_E7_TXN3 MCH_E7_TXN2 MCH_E7_TXN1 MCH_E7_TXN0
MCH_PE_COMP
PEWIDTH3 PEWIDTH2 PEWIDTH1 PEWIDTH0
C533 0.1u-0402 C534 0.1u-0402 C535 0.1u-0402 C536 0.1u-0402
C529 0.1u-0402 C530 0.1u-0402 C531 0.1u-0402 C532 0.1u-0402
C561 0.1u-0402 C562 0.1u-0402 C563 0.1u-0402 C564 0.1u-0402
C553 0.1u-0402 C554 0.1u-0402 C555 0.1u-0402 C556 0.1u-0402
C557 0.1u-0402 C558 0.1u-0402 C559 0.1u-0402 C560 0.1u-0402
C549 0.1u-0402 C550 0.1u-0402 C551 0.1u-0402 C552 0.1u-0402
C639 0.1u C637 0.1u C635 0.1u C633 0.1u
C640 0.1u C638 0.1u C636 0.1u C634 0.1u
C647 0.1u C645 0.1u C643 0.1u C641 0.1u
C648 0.1u C646 0.1u C644 0.1u C642 0.1u
C782 0.1u C785 0.1u C787 0.1u C789 0.1u
C784 0.1u C786 0.1u C788 0.1u C790 0.1u
C773 0.1u C775 0.1u C777 0.1u C779 0.1u
C774 0.1u C776 0.1u C778 0.1u C780 0.1u
R630 24.9RST
R3393 0
3
MCH_EXP0_TXP3 36 MCH_EXP0_TXP2 36 MCH_EXP0_TXP1 36 MCH_EXP0_TXP0 36
MCH_EXP0_TXN3 36 MCH_EXP0_TXN2 36 MCH_EXP0_TXN1 36 MCH_EXP0_TXN0 36
MCH_EXP2_TXP3 36 MCH_EXP2_TXP2 36 MCH_EXP2_TXP1 36 MCH_EXP2_TXP0 36
MCH_EXP2_TXN3 36 MCH_EXP2_TXN2 36 MCH_EXP2_TXN1 36 MCH_EXP2_TXN0 36
MCH_EXP3_TXP3 36 MCH_EXP3_TXP2 36 MCH_EXP3_TXP1 36 MCH_EXP3_TXP0 36
MCH_EXP3_TXN3 36 MCH_EXP3_TXN2 36 MCH_EXP3_TXN1 36 MCH_EXP3_TXN0 36
MCH_EXP4_TXP3 51 MCH_EXP4_TXP2 51 MCH_EXP4_TXP1 51 MCH_EXP4_TXP0 51
MCH_EXP4_TXN3 51 MCH_EXP4_TXN2 51 MCH_EXP4_TXN1 51 MCH_EXP4_TXN0 51
MCH_EXP5_TXP3 51 MCH_EXP5_TXP2 51 MCH_EXP5_TXP1 51 MCH_EXP5_TXP0 51
MCH_EXP5_TXN3 51 MCH_EXP5_TXN2 51 MCH_EXP5_TXN1 51 MCH_EXP5_TXN0 51
MCH_EXP6_TXP3 51 MCH_EXP6_TXP2 51 MCH_EXP6_TXP1 51 MCH_EXP6_TXP0 51
MCH_EXP6_TXN3 51 MCH_EXP6_TXN2 51 MCH_EXP6_TXN1 51 MCH_EXP6_TXN0 51
MCH_EXP7_TXP3 51 MCH_EXP7_TXP2 51 MCH_EXP7_TXP1 51 MCH_EXP7_TXP0 51
MCH_EXP7_TXN3 51 MCH_EXP7_TXN2 51 MCH_EXP7_TXN1 51 MCH_EXP7_TXN0 51
P1V5
PEWIDTH_0 51
P1V5
PEWIDTH3 PEWIDTH2 PEWIDTH1 PEWIDTH0
R634 1K R635 100 R636 1K R638 1K
PEWIDTH[3:0] PORT2 PORT4 PORT7PORT6PORT3 PORT5
0000 0001 0010 0011 0100
OTHERS
1000 1001 1010
1011(default)
1100
OTHERS
1111
X4 X4 X4 X4 X4 X4
X4X4X4X4X4 X4 X4 X4 X4
X8 X8
X4
X4 X4
X16
------RESERVED-------
X8
X4X4X4X4X4 X4
X8 X8 X8 X8
X8
X4 X4
X8
X16
------RESERVED-------
Automatic Link negotiation (Not Support)
Port 0 (ESI) is always set to X4 width.
MCH PCI-E PLL/COMP/BAND GAP CKTS
P5V
C981 1u
2.50V Reference
3
Top View
12
Route MCH_PE_VCCBG With MCH_PE_VSSBG As Differential Pair
R632
Width=25mils, Space=10mils
220
1
U46 LM431AIM3/Vf=2.5V
3 2
P1V5
2
R633
0.499RST
Route MCH_PE_VCCA With MCH_PE_VSSA As Differential Pair Width=25mils, Space=10mils
R631
0.499RST
L10
4.7uH-0805-30mA
L9
4.7uH-0805-30mA
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
MCH_PE_VCCBG
C982 22u-1206
R637 0
Keep Stub Between 0ohm resistor And 22uF Cap As Short As Possible
C979 22u-1206
Micro Star Restricted Secret
Blackford PCI-E Interface
X8
X8
X8
X8
C983
0.1u
MCH_PE_VSSBG
MCH_PE_VCCA
C980
0.1u
MCH_PE_VSSA
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
19 90
of
Rev
0A
Page 20
5
4
3
2
1
Blackford XDP Interface
D D
BLACKFORD 6/11
SYS_PWRGD_3_3V35,37,40,50,63,77
PLTRST_N37,63
MCH_ERR_N238 MCH_ERR_N138 MCH_ERR_N038
C C
MCH_ERR_N2 MCH_ERR_N1 MCH_ERR_N0
B B
A A
R660 X_1K R661 X_1K R662 X_1K
XDP1_COMCRES
XDP1_ODTCRES XDP1_SLWCRES
5
SYS_PWRGD_3_3V
PLTRST_N
MCH_ERR_N2 MCH_ERR_N1 MCH_ERR_N0
P3V3
R1286
49.9RST
R1287 549RST
H17 G17
P10
M12
AR15
AK17
T37 D29 N10
AR16
AP32 AP28
AM7 AG6
M11 AE8
AG2
AH7
AJ1
AK23 AM24 AM31 AN23 AR33
AV27
D2 A5 E6
M3 N5 P7 R9
L3 M5 P6 R8 N2 M6 N8
M2
L6 N7 P9
R6 H1
W1
Y1
J3
PWRGOOD PLTRST_N
ERR_N2 ERR_N1 ERR_N0
RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
4
U45F
CFG_SCL CFG_SDA
GPIO_SCL GPIO_SDA
TCK
TDO TMS
TRST_N
TDIO_ANODE
TDIO_CATHODE
XDPD_N15 XDPD_N14 XDPD_N13 XDPD_N12 XDPD_N11 XDPD_N10
XDPD_N9 XDPD_N8 XDPD_N7 XDPD_N6 XDPD_N5 XDPD_N4 XDPD_N3 XDPD_N2 XDPD_N1 XDPD_N0
XDPDSTBP_N
XDPDSTBN_N
XDPRDY_N
XDPODTCRES XDPSLWCRES XDPCOMCRES
TESTHI
TESTHI_V3REF TESTHI_V3REF
BLACKFORD G1
K14 J14
K13 L12
A6 B7
TDI
B6 A7 A8
A4 B4
E16 D16 A15 C16 A16 A14 B15 D15 B14 B13 E14 A12 D13 A10 B10 A11
C14 C13
A17 G14
J15 F14
AC36
G16 F17
SMBus Voltage Translation
R3284
R3283
4.7K
4.7K
R3163 X_5.1K R3164 X_5.1K
XDP0_TCK1 MCH_TDI XDP0_TDO_MCH XDP0_TMS_MAIN XDP0_TRST_MCH_N
XDP1_ODTCRES XDP1_SLWCRES XDP1_COMCRES
TESTHI0
TESTHI_V3REF1 TESTHI_V3REF0
U3029
1
NC
2
SCL0
SCL1
3
SDA0
SDA1
GND4EN
PCA9515
R3383 0
MCH_TDI
R1245 51
P_VTT
Place pull-up resistors close to MCH.
For A-stepping MCH, not install R267; For B-stepping MCH, MUST install R267.
R627 1K
R628 5.1K R629 5.1K
P3V3P3V3
P3V3
R3282
4.7K
8
VCC
7 6 5
P3V3
XDP0_TCK1 64 XDP0_TDI_MAIN 64
XDP0_TMS_MAIN 9,12,64
R3303 51
XDP0_TMS_MAIN
P1V5
P3V3
3
SMBCLK_BF 54 SMBDAT_BF 54
P_VTT
XDP GTL/TTL Level translation
P3V3
P3V3
R1289
R1288
X_1K
U87
XDP0_TDO_MCH XDP0_TMS_MAIN XDP0_TMS_ESB XDP0_TCK1 XDP0_TRST#
P_VTT
R1294
49.9RST
R1295 100RST
R1290 51
R1292
1K
C1410 1u
SYS_PWRGD_3_3V
2
A0
3
A1
5
A2
6
A3
1
DIR
4
GTLREF
P3V3
R1297 1K
XDP0_TDO_ESB39
R3022
X_2.2K
XDP0_TRST#9,12,64
R1298
1.6K
VCC3
GND1 GND2 GND3
GTL2005
P_VTT
R3155 X_330
B0 B1 B2 B3
Q117 X_MMBT3904
XDP0_TRST#
Reserved For Greencreek A1
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
2
http://www.msi.com.tw
X_1K
13 12 10 9
14
7 8 11
P_VTT
R1296 330
Q110 MMBT3904
XDP0_TDI_ESB
XDP0_TCK1_ESB XDP0_TRST#_ESB
P3V3
C1409
0.1u
P_VTT
R3304 51
Q109 MMBT3904
P_VTT
R1244 X_51
Q118 X_MMBT3904
R3450
0
R1293 1K
XDP0_TDO_MAIN 64
XDP0_TRST_MCH_N
R3029 X_20K
Micro Star Restricted Secret
Blackford XDP Interface
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
XDP0_TDI_ESB 39 XDP0_TMS_ESB 39 XDP0_TCK1_ESB 39 XDP0_TRST#_ESB 39
R1291 1K
20 90
1
Rev
0A
of
Page 21
5
4
3
2
1
Blackford Power/GND
P1V5 P1V5 P_VTT
D D
C C
B B
A A
P3V3
AL17
VCC
L16
VCC
L17
VCC
L18
VCC
L19
VCC
M16
VCC
M17
VCC
M18
VCC
N17
VCC
N19
VCC
P16
VCC
P18
VCC
P20
VCC
P22
VCC
P24
VCC
R15
VCC
R17
VCC
R19
VCC
R21
VCC
R23
VCC
T16
VCC
T18
VCC
T20
VCC
T22
VCC
T24
VCC
U15
VCC
U17
VCC
U19
VCC
U21
VCC
U23
VCC
V16
VCC
V18
VCC
V20
VCC
V22
VCC
V24
VCC
W15
VCC
W17
VCC
W19
VCC
W21
VCC
W23
VCC
Y16
VCC
Y18
VCC
Y20
VCC
Y22
VCC
Y24
VCC
AA15
VCC
AA17
VCC
AA19
VCC
AA21
VCC
AA23
VCC
AB16
VCC
AB18
VCC
AB20
VCC
AB22
VCC
AB24
VCC
AC15
VCC
AC17
VCC
AC19
VCC
AC21
VCC
AC23
VCC
AH10
VCCSF
AE35
VCCSF
AA13
VCCSF
AB13
VCCSF
AB14
VCCSF
AC25
VCCSF
AC26
VCCSF
AD26
VCCSF
L24
VCCSEN
F13
V3REF
5
BLACKFORD 7/11
U45G
VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD VCCFBD
VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE VCCPE
BLACKFORD G1
A20 E20 E23 F25 H20 H23 K21 K22 K23 L20 L21 L22 L23 M20 M21 M22 M23 M24 M25 N20 N21 N22 N23 N24 N25 N26 P25 P26 R25 T25 T26 T27 U25 U26 V25 V26 W25 W26 Y25 Y26 AA25 AA26 AA27 AB25 AB26
G12 J10 L2 L8 L13 L14 L15 M13 M14 M15 N6 N12 N13 N14 N15 P13 P14 R4 R10 R13 R14 T13 T14 U2 U8 U13 U14 V13 V14 W6 W12 W13 W14 Y13 Y14
BLACKFORD 8/11
AC13
VTT
AC14
VTT
AD13
VTT
AD14
VTT
AD15
VTT
AD16
VTT
AD17
VTT
AD18
VTT
AD19
VTT
AD20
VTT
AD21
VTT
AD22
VTT
AD23
VTT
AD24
VTT
AD25
VTT
AE13
VTT
AE14
VTT
AE15
VTT
AE16
VTT
AE17
VTT
AE18
VTT
AE19
VTT
AE20
VTT
AE21
VTT
AE22
VTT
AE23
VTT
AE24
VTT
AE25
VTT
AE26
VTT
AF18
VTT
AF19
VTT
AF20
VTT
AF21
VTT
AG18
VTT
AG19
VTT
AG20
VTT
AG21
VTT
AH18
VTT
AH19
VTT
AH20
VTT
AH21
VTT
AJ18
VTT
AJ19
VTT
AJ20
VTT
AJ21
VTT
AK18
VTT
AK19
VTT
AK20
VTT
AK21
VTT
AL18
VTT
AL19
VTT
AL20
VTT
AL21
VTT
AM18
VTT
AM19
VTT
AM20
VTT
AM21
VTT
AN18
VTT
AN19
VTT
AN20
VTT
AN21
VTT
AP18
VTT
AP19
VTT
AP20
VTT
AP21
VTT
AR18
VTT
AR19
VTT
AR20
VTT
AR21
VTT
AT18
VTT
AT19
VTT
AT20
VTT
AT21
VTT
AU18
VTT
AU19
VTT
AU20
VTT
AU21
VTT
AV18
VTT
AV19
VTT
AV20
VTT
AV21
VTT
4
U45H
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
BLACKFORD G1
C30 C32 C33 C35 C38 D3 D6 D9 D12 D14 D18 D21 D24 D27 D30 D33 D36 E2 E5 E8 E11 E13 E17 E26 E29 E32 E35 F1 F4 F7 F10 F16 F19 F22 F26 F28 F31 F34 F38 G3 G6 G9 G15 G18 G21 G24 G27 G30 G33 G36 G37 H2 H5 H8 H11 H14 H26 H29 H32 H35 J1 J4 J7 J13 J17 J19 J22 J25 J28 J31 J34 J38 K3 K6 K9 K12 K16 K17 K20 K24 K27
BLACKFORD 9/11
AM5
VSS
AM8
VSS
AM11
VSS
AM14
VSS
AM17
VSS
AM23
VSS
AM26
VSS
AM29
VSS
AM32
VSS
AM35
VSS
AM36
VSS
AN1
VSS
AN4
VSS
AN7
VSS
AN10
VSS
AN13
VSS
AN16
VSS
AN22
VSS
AN25
VSS
AN28
VSS
AN31
VSS
AN34
VSS
AN37
VSS
AN38
VSS
AP3
VSS
AP6
VSS
AP9
VSS
AP12
VSS
AP15
VSS
AP24
VSS
AP27
VSS
AP30
VSS
AP33
VSS
AR2
VSS
AR5
VSS
AR8
VSS
AR11
VSS
AR14
VSS
AR17
VSS
AR23
VSS
AR26
VSS
AR29
VSS
AR32
VSS
AR35
VSS
AR36
VSS
AT1
VSS
AT4
VSS
AT7
VSS
AT10
VSS
AT13
VSS
C29
VSS
AT16
VSS
AT22
VSS
AT25
VSS
AT28
VSS
AT31
VSS
AT34
VSS
AT38
VSS
AU2
VSS
AU6
VSS
AU9
VSS
AU12
VSS
AU15
VSS
AU24
VSS
AU27
VSS
AU30
VSS
AU33
VSS
AU37
VSS
AV3
VSS
AV5
VSS
AV8
VSS
AV11
VSS
AV14
VSS
AV17
VSS
AV23
VSS
AV26
VSS
AV29
VSS
AV32
VSS
AV35
VSS
AV36
VSS
BLACKFORD G1
3
U45I
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AD36 AD37 AD38 AE3 AE6 AE9 AE12 AE30 AE33 AF2 AF5 AF8 AF10 AF11 AF14 AF17 AF23 AF24 AF26 AF27 AF29 AF32 AF35 AF36 AG1 AG4 AG7 AG13 AG16 AG22 AG25 AG28 AG31 AG34 AG37 AG38 AH3 AH6 AH9 AH12 AH15 AH24 AH27 AH30 AH33 AJ2 AJ5 AJ8 AJ11 AJ14 AJ17 AJ23 AJ26 AJ29 AJ32 AJ35 AJ36 AK1 AK4 AK7 AK10 AK13 AK16 AK22 AK25 AK28 AK31 AK34 AK37 AK38 AL3 AL6 AL9 AL12 AL15 AL24 AL27 AL30 AL33 AM2
BLACKFORD 10/11
V17
VSS
V19
VSS
V21
VSS
V23
VSS
V28
VSS
V31
VSS
V34
VSS
V37
VSS
W3
VSS
W9
VSS
W16
VSS
W18
VSS
W20
VSS
W22
VSS
W24
VSS
W27
VSS
W30
VSS
W33
VSS
W36
VSS
W37
VSS
Y2
VSS
Y5
VSS
Y8
VSS
Y11
VSS
Y15
VSS
Y17
VSS
Y19
VSS
Y21
VSS
Y23
VSS
Y29
VSS
Y32
VSS
Y35
VSS
Y38
VSS
AA1
VSS
AA4
VSS
AA7
VSS
AA10
VSS
AA14
VSS
AA16
VSS
AA18
VSS
AA20
VSS
AA22
VSS
AA24
VSS
AA28
VSS
AA31
VSS
AA34
VSS
AA37
VSS
AB3
VSS
AB6
VSS
AB9
VSS
AB12
VSS
AB15
VSS
AB17
VSS
AB19
VSS
AB21
VSS
AB23
VSS
AB27
VSS
AB30
VSS
AB33
VSS
AB36
VSS
AC2
VSS
AC5
VSS
AC8
VSS
AC11
VSS
AC16
VSS
AC18
VSS
AC20
VSS
AC22
VSS
AC24
VSS
AC29
VSS
AC32
VSS
AC35
VSS
AC38
VSS
AD1
VSS
AD4
VSS
AD7
VSS
AD10
VSS
AD28
VSS
AD31
VSS
AD34
VSS
U45J
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
BLACKFORD G1
2
K30 K33 K36 K37 L5 L11 L26 L29 L32 L35 M1 M4 M7 M10 M19 M28 M31 M34 M37 M38 N3 N9 N16 N18 N27 N30 N33 N36 P2 P5 P8 P11 P15 P17 P19 P21 P23 P29 P32 P35 P38 R1 R7 R16 R18 R20 R22 R24 R28 R31 R34 R37 T3 T6 T9 T12 T15 T17 T19 T21 T23 T30 T33 T36 U5 U11 U16 U18 U20 U22 U24 U29 U32 U35 U38 V1 V4 V7 V10 V15
BLACKFORD 11/11
AC27
VSS
AB28
VSS
AA29
VSS
AE27
VSS
AC28
VSS
AB29
VSS
A3
VSS
A9
VSS
A13
VSS
A18
VSS
A21
VSS
A23
VSS
A25
VSS
A28
VSS
A31
VSS
A34
VSS
A36
VSS
B2
VSS
B3
VSS
B5
VSS
B8
VSS
B11
VSS
B16
VSS
B17
VSS
B20
VSS
B23
VSS
B37
VSS
C1
VSS
C4
VSS
C7
VSS
C10
VSS
C15
VSS
C19
VSS
C22
VSS
C24
VSS
C26
VSS
C27
VSS
T11
VSS
VSSQUIET
BLACKFORD G1
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
U45K
AU13
VSS
V12
VSS
AT15
VSS
T10
VSS
AH17
VSS
AV16
VSS
AV15
VSS
U12
VSS
AU14
VSS
V11
VSS
AG17
VSS
AA30
VSS
J27
VSS
K26
VSS
F21
VSS
H28
VSS
J26
VSS
K25
VSS
E21
VSS
H27
VSS
K29
VSS
J30
VSS
H31
VSS
G32
VSS
K28
VSS
J29
VSS
H30
VSS
G31
VSS
R27
VSS
R29
VSS
P30
VSS
N31
VSS
R26
VSS
T29
VSS
R30
VSS
P31
VSS
AD27
VSS
L25
VSSSEN
L9
Blackford Power/GND
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
21 90
of
Rev
0A
Page 22
5
Blackford Decoupling Cap.
4
3
2
1
D D
C C
B B
MCH 1.5V Decoupling Caps.
P1V5
C873 1u
C890 1u
C830 1u
C839 1u
C840 1u
C876
C879
1u
1u
C893
C808
1u
1u
C833
C836
1u
1u
C8421uC845
1u
C843
C846
1u
1u
C882 1u
C811 1u
C838 1u
C848 1u
C849 1u
P1V5
P1V5
P1V5
P1V5
C867 1u
C885 1u
C815 1u
C853 1u
C863 1u
C870 1u
C888 1u
C827 1u
C856 1u
C865 1u
C814 1u
C841 1u
C851 1u
C852 1u
C809 1u
C844 1u
C854 1u
C855 1u
C812 1u
C850
C847
1u
1u
C857
C860
1u
1u
C8581uC861
1u
MCH FSB VTT Decoupling Caps.
P_VTT
C877 1u
C872 1u
C880
4.7u-1206
C816
4.7u-1206
C875 1u
C837
4.7u-1206
C883
4.7u-1206
C819
4.7u-1206
C878 1u
C822
4.7u-1206
C881 1u
C886
4.7u-1206
C884 1u
C825
4.7u-1206
C887 1u
C810
4.7u-1206
C828
4.7u-1206
C889 1u
P_VTT
P_VTT
P_VTT
C874 1u
C813
4.7u-1206
C869 1u
C834
4.7u-1206
C831
4.7u-1206
C891 1u
C8941uC868
1u
C871 1u
V3VREF Decoupling Caps.
P3V3
C892 1u
P1V5
C866
C864 1u
A A
5
C859
1u
4.7u-1206
C862
4.7u-1206
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
4
3
2
http://www.msi.com.tw
Blackford Decoupling Cap.
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
22 90
Rev
0A
of
Micro Star Restricted Secret
Page 23
5
4
3
2
1
FBD Channel 0 DIMM 0
DIMM11A
FBD_CH0_NB_P[13..0]17
D D
C C
B B
A A
FBD_CH0_NB_N[13..0]17
FBD_CH0_SB_P[9..0]17 FBD_CH0_SB_N[9..0]17
5
FBD_CH0_NB_P[13..0] FBD_CH0_NB_N[13..0] FBD_CH0_SB_P[9..0] FBD_CH0_SB_N[9..0]
CK_H_FBD059
CK_H_FBD0_N59
FBD_BR0_RST#24,25,26,27,28,35
FBD_CH0_NB_P13 FBD_CH0_NB_P12 FBD_CH0_NB_P11 FBD_CH0_NB_P10 FBD_CH0_NB_P9 FBD_CH0_NB_P8 FBD_CH0_NB_P7 FBD_CH0_NB_P6 FBD_CH0_NB_P5 FBD_CH0_NB_P4 FBD_CH0_NB_P3 FBD_CH0_NB_P2 FBD_CH0_NB_P1 FBD_CH0_NB_P0
FBD_CH0_NB_N13 FBD_CH0_NB_N12 FBD_CH0_NB_N11 FBD_CH0_NB_N10 FBD_CH0_NB_N9 FBD_CH0_NB_N8 FBD_CH0_NB_N7 FBD_CH0_NB_N6 FBD_CH0_NB_N5 FBD_CH0_NB_N4 FBD_CH0_NB_N3 FBD_CH0_NB_N2 FBD_CH0_NB_N1 FBD_CH0_NB_N0
FBD_CH0_SB_P9 FBD_CH0_SB_P8 FBD_CH0_SB_P7 FBD_CH0_SB_P6 FBD_CH0_SB_P5 FBD_CH0_SB_P4 FBD_CH0_SB_P3 FBD_CH0_SB_P2 FBD_CH0_SB_P1 FBD_CH0_SB_P0
FBD_CH0_SB_N9 FBD_CH0_SB_N8 FBD_CH0_SB_N7 FBD_CH0_SB_N6 FBD_CH0_SB_N5 FBD_CH0_SB_N4 FBD_CH0_SB_N3 FBD_CH0_SB_N2 FBD_CH0_SB_N1 FBD_CH0_SB_N0
CK_H_FBD0 CK_H_FBD0_N
FBD_BR0_RST#
4
102
103 100
228 229
136
207 206 165 164
40 48 66 63 60 57 54 51 37 34 31 28 25 22
41 49 67 64 61 58 55 52 38 35 32 29 26 23
90 99
96 93 82 79 76 73 70
91
97 94 83 80 77 74 71
16
17
87 86 45 44
FBDIMM-1/2
PNP13 PNP12 PNP11 PNP10 PNP9 PNP8
Primarily Northbound
PNP7 PNP6 PNP5 PNP4 PNP3 PNP2 PNP1 PNP0
PNN13 PNN12 PNN11 PNN10 PNN9 PNN8 PNN7 PNN6 PNN5 PNN4 PNN3 PNN2 PNN1 PNN0
PSP9 PSP8
Primarily Southbound
PSP7 PSP6 PSP5 PSP4 PSP3 PSP2 PSP1 PSP0
PSN9 PSN8 PSN7 PSN6 PSN5 PSN4 PSN3 PSN2 PSN1 PSN0
SCKP SCKN
VID1 VID0
RESET_N
RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK
SNP13 SNP12 SNP11 SNP10
SNP9 SNP8 SNP7 SNP6 SNP5 SNP4 SNP3 SNP2 SNP1 SNP0
SNN13 SNN12 SNN11 SNN10
SNN9 SNN8 SNN7
Secondary NorthboundSecondary Southbound
SNN6 SNN5 SNN4 SNN3 SNN2 SNN1 SNN0
SSP9 SSP8 SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0
SSN9 SSN8 SSN7 SSN6 SSN5 SSN4 SSN3 SSN2 SSN1 SSN0
SCL SDA
SA2 SA1 SA0
M_TEST
RFU RFU RFU RFU RFU RFU RFU RFU
FBDIMM240
168 186 183 180 177 174 171 157 154 151 148 145 142
161 169 187 184 181 178 175 172 158 155 152 149 146 143
210 222 219 216 213 202 199 196 193 190
211 223 220 217 214 203 200 197 194 191
120 119
118 240 239
137 20 19 106 105 139 140 225 226
CH0_NB_P12 CH0_NB_P11 CH0_NB_P10 CH0_NB_P9 CH0_NB_P8 CH0_NB_P7 CH0_NB_P6 CH0_NB_P5 CH0_NB_P4 CH0_NB_P3 CH0_NB_P2 CH0_NB_P1 CH0_NB_P0
CH0_NB_N13 CH0_NB_N12 CH0_NB_N11 CH0_NB_N10 CH0_NB_N9 CH0_NB_N8 CH0_NB_N7 CH0_NB_N6 CH0_NB_N5 CH0_NB_N4 CH0_NB_N3 CH0_NB_N2 CH0_NB_N1 CH0_NB_N0
CH0_SB_P9 CH0_SB_P8 CH0_SB_P7 CH0_SB_P6 CH0_SB_P5 CH0_SB_P4 CH0_SB_P3 CH0_SB_P2 CH0_SB_P1 CH0_SB_P0
CH0_SB_N9 CH0_SB_N8 CH0_SB_N7 CH0_SB_N6 CH0_SB_N5 CH0_SB_N4 CH0_SB_N3 CH0_SB_N2 CH0_SB_N1 CH0_SB_N0
FBD0SCL FBD0SDA
FBD00SA2 FBD00SA1 FBD00SA0
3
CH0_NB_P13
160
CH0_NB_P[13..0] CH0_NB_N[13..0] CH0_SB_P[9..0] CH0_SB_N[9..0]
FBD00SA2 FBD00SA1 FBD00SA0
CH0_NB_P[13..0] 24 CH0_NB_N[13..0] 24 CH0_SB_P[9..0] 24 CH0_SB_N[9..0] 24
R11731KR1174
DIMM SPD SMBus Address 0XA0 AMB SMBus Address LAI SPD SMBus Address LAI IOX SMBus Address
FBD0SCL 17,24,25 FBD0SDA 17,24,25
R1175 1K
1K
0XB0 0X20 0X70
2
P1V8 P1V5
FBDIMM-2/2
231
VDD
232
VDD
233
VDD
235
VDD
236
VDD
116
VDD
115
VDD
113
VDD
112
VDD
111
VDD
109
VDD
108
VDD
127
VDD
126
VDD
125
VDD
123
VDD
122
VDD
121
VDD
7
VDD
6
VDD
5
VDD
3
VDD
2
VDD
1
VDD
234
VSS
230
VSS
227
VSS
224
VSS
221
VSS
218
VSS
215
VSS
212
VSS
209
VSS
208
VSS
205
VSS
204
VSS
201
VSS
198
VSS
195
VSS
192
VSS
189
VSS
188
VSS
185
VSS
182
VSS
179
VSS
176
VSS
173
VSS
170
VSS
167
VSS
166
VSS
163
VSS
162
VSS
159
VSS
156
VSS
153
VSS
150
VSS
114
VSS
110
VSS
104
VSS
107
VSS
101
VSS
98
VSS
95
VSS
92
VSS
DIMM11B
VCC VCC VCC VCC VCC VCC VCC VCC
VTT VTT VTT VTT
VDDSPD
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
FBDIMM240
133 132 130 129 13 12 10 9
237 135 117 15
238
89 88 85 84 81 78 75 72 69 68 65 62 59 56 53 50 47 46 43 42 39 36 33 30 147 144 141 138 134 131 128 124 27 24 21 18 14 11 8 4
F_VTT
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
FBD Channel 0 DIMM 0
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
P3V3
C3229
0.1u
Share 0.1uF Cap. Between VDDSPD Pins Of DIMM0 & DIMM1
23 90
1
of
Rev
0A
Page 24
5
4
3
2
1
FBD Channel 0 DIMM 1
DIMM12A
CH0_NB_P[13..0]23
D D
C C
B B
A A
CH0_NB_N[13..0]23
CH0_SB_P[9..0]23 CH0_SB_N[9..0]23
5
CH0_NB_P[13..0] R_CH0_NB_P[13..0] CH0_NB_N[13..0] R_CH0_NB_N[13..0] CH0_SB_P[9..0] CH0_SB_N[9..0]
CK_H_FBD159
CK_H_FBD1_N59
FBD_BR0_RST#23,25,26,27,28,35
CH0_NB_P13 CH0_NB_P12 CH0_NB_P11 CH0_NB_P10 CH0_NB_P9 CH0_NB_P8 CH0_NB_P7 CH0_NB_P6 CH0_NB_P5 CH0_NB_P4 CH0_NB_P3 CH0_NB_P2 CH0_NB_P1 CH0_NB_P0
CH0_NB_N13 CH0_NB_N12 CH0_NB_N11 CH0_NB_N10 CH0_NB_N9 CH0_NB_N8 CH0_NB_N7 CH0_NB_N6 CH0_NB_N5 CH0_NB_N4 CH0_NB_N3 CH0_NB_N2 CH0_NB_N1 CH0_NB_N0
CH0_SB_P9 CH0_SB_P8 CH0_SB_P7 CH0_SB_P6 CH0_SB_P5 CH0_SB_P4 CH0_SB_P3 CH0_SB_P2 CH0_SB_P1 CH0_SB_P0
CH0_SB_N9 CH0_SB_N8 CH0_SB_N7 CH0_SB_N6 CH0_SB_N5 CH0_SB_N4 CH0_SB_N3 CH0_SB_N2 CH0_SB_N1 CH0_SB_N0
CK_H_FBD1 CK_H_FBD1_N
FBD_BR0_RST#
4
102
103 100
228 229
136
207 206 165 164
40 48 66 63 60 57 54 51 37 34 31 28 25 22
41 49 67 64 61 58 55 52 38 35 32 29 26 23
90 99
96 93 82 79 76 73 70
91
97 94 83 80 77 74 71
16
17
87 86 45 44
FBDIMM-1/2
PNP13 PNP12 PNP11 PNP10 PNP9 PNP8
Primarily Northbound
PNP7 PNP6 PNP5 PNP4 PNP3 PNP2 PNP1 PNP0
PNN13 PNN12 PNN11 PNN10 PNN9 PNN8 PNN7 PNN6 PNN5 PNN4 PNN3 PNN2 PNN1 PNN0
PSP9 PSP8
Primarily Southbound
PSP7 PSP6 PSP5 PSP4 PSP3 PSP2 PSP1 PSP0
PSN9 PSN8 PSN7 PSN6 PSN5 PSN4 PSN3 PSN2 PSN1 PSN0
SCKP SCKN
VID1 VID0
RESET_N
RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK
SNP13 SNP12 SNP11 SNP10
SNP9 SNP8 SNP7 SNP6 SNP5 SNP4 SNP3 SNP2 SNP1 SNP0
SNN13 SNN12 SNN11 SNN10
SNN9 SNN8 SNN7
Secondary NorthboundSecondary Southbound
SNN6 SNN5 SNN4 SNN3 SNN2 SNN1 SNN0
SSP9 SSP8 SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0
SSN9 SSN8 SSN7 SSN6 SSN5 SSN4 SSN3 SSN2 SSN1 SSN0
SCL SDA
SA2 SA1 SA0
M_TEST
RFU RFU RFU RFU RFU RFU RFU RFU
FBDIMM240
168 186 183 180 177 174 171 157 154 151 148 145 142
161 169 187 184 181 178 175 172 158 155 152 149 146 143
210 222 219 216 213 202 199 196 193 190
211 223 220 217 214 203 200 197 194 191
120 119
118 240 239
137 20 19 106 105 139 140 225 226
R_CH0_NB_P12 R_CH0_NB_P11 R_CH0_NB_P10 R_CH0_NB_P9 R_CH0_NB_P8 R_CH0_NB_P7 R_CH0_NB_P6 R_CH0_NB_P5 R_CH0_NB_P4 R_CH0_NB_P3 R_CH0_NB_P2 R_CH0_NB_P1 R_CH0_NB_P0
R_CH0_NB_N13 R_CH0_NB_N12 R_CH0_NB_N11 R_CH0_NB_N10 R_CH0_NB_N9 R_CH0_NB_N8 R_CH0_NB_N7 R_CH0_NB_N6 R_CH0_NB_N5 R_CH0_NB_N4 R_CH0_NB_N3 R_CH0_NB_N2 R_CH0_NB_N1 R_CH0_NB_N0
R_CH0_SB_P9 R_CH0_SB_P8 R_CH0_SB_P7 R_CH0_SB_P6 R_CH0_SB_P5 R_CH0_SB_P4 R_CH0_SB_P3 R_CH0_SB_P2 R_CH0_SB_P1 R_CH0_SB_P0
R_CH0_SB_N9 R_CH0_SB_N8 R_CH0_SB_N7 R_CH0_SB_N6 R_CH0_SB_N5 R_CH0_SB_N4 R_CH0_SB_N3 R_CH0_SB_N2 R_CH0_SB_N1 R_CH0_SB_N0
FBD0SCL FBD0SDA
FBD01SA2 FBD01SA1 FBD01SA0
3
R_CH0_NB_P13
160
R_CH0_SB_P[9..0] R_CH0_SB_N[9..0]
FBD01SA2 FBD01SA1 FBD01SA0
DIMM SPD SMBus Address 0XA2 AMB SMBus Address LAI SPD SMBus Address LAI IOX SMBus Address
FBD0SCL 17,23,25 FBD0SDA 17,23,25
R_CH0_NB_P[13..0] 25 R_CH0_NB_N[13..0] 25 R_CH0_SB_P[9..0] 25 R_CH0_SB_N[9..0] 25
P3V3
R1171 1K
R1177
R1176
1K
1K
0XB2 0X22 0X72
2
P1V8 P1V5
FBDIMM-2/2
231
VDD
232
VDD
233
VDD
235
VDD
236
VDD
116
VDD
115
VDD
113
VDD
112
VDD
111
VDD
109
VDD
108
VDD
127
VDD
126
VDD
125
VDD
123
VDD
122
VDD
121
VDD
7
VDD
6
VDD
5
VDD
3
VDD
2
VDD
1
VDD
234
VSS
230
VSS
227
VSS
224
VSS
221
VSS
218
VSS
215
VSS
212
VSS
209
VSS
208
VSS
205
VSS
204
VSS
201
VSS
198
VSS
195
VSS
192
VSS
189
VSS
188
VSS
185
VSS
182
VSS
179
VSS
176
VSS
173
VSS
170
VSS
167
VSS
166
VSS
163
VSS
162
VSS
159
VSS
156
VSS
153
VSS
150
VSS
114
VSS
110
VSS
104
VSS
107
VSS
101
VSS
98
VSS
95
VSS
92
VSS
DIMM12B
VCC VCC VCC VCC VCC VCC VCC VCC
VTT VTT VTT VTT
VDDSPD
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
FBDIMM240
133 132 130 129 13 12 10 9
237 135 117 15
238
89 88 85 84 81 78 75 72 69 68 65 62 59 56 53 50 47 46 43 42 39 36 33 30 147 144 141 138 134 131 128 124 27 24 21 18 14 11 8 4
F_VTT
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
FBD Channel 0 DIMM 1
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
P3V3
C3230
0.1u
Share 0.1uF Cap. Between VDDSPD Pins Of DIMM0 & DIMM1
24 90
1
of
Rev
0A
Page 25
5
4
3
2
1
FBD Channel 0 DIMM 2
DIMM13A
R_CH0_NB_P[13..0]24
D D
C C
B B
A A
R_CH0_NB_N[13..0]24
R_CH0_SB_P[9..0]24 R_CH0_SB_N[9..0]24
5
R_CH0_NB_P[13..0] R_CH0_NB_N[13..0] R_CH0_SB_P[9..0] R_CH0_SB_N[9..0]
CK_H_FBD259
CK_H_FBD2_N59
FBD_BR0_RST#23,24,26,27,28,35
R_CH0_NB_P13 R_CH0_NB_P12 R_CH0_NB_P11 R_CH0_NB_P10 R_CH0_NB_P9 R_CH0_NB_P8 R_CH0_NB_P7 R_CH0_NB_P6 R_CH0_NB_P5 R_CH0_NB_P4 R_CH0_NB_P3 R_CH0_NB_P2 R_CH0_NB_P1 R_CH0_NB_P0
R_CH0_NB_N13 R_CH0_NB_N12 R_CH0_NB_N11 R_CH0_NB_N10 R_CH0_NB_N9 R_CH0_NB_N8 R_CH0_NB_N7 R_CH0_NB_N6 R_CH0_NB_N5 R_CH0_NB_N4 R_CH0_NB_N3 R_CH0_NB_N2 R_CH0_NB_N1 R_CH0_NB_N0
R_CH0_SB_P9 R_CH0_SB_P8 R_CH0_SB_P7 R_CH0_SB_P6 R_CH0_SB_P5 R_CH0_SB_P4 R_CH0_SB_P3 R_CH0_SB_P2 R_CH0_SB_P1 R_CH0_SB_P0
R_CH0_SB_N9 R_CH0_SB_N8 R_CH0_SB_N7 R_CH0_SB_N6 R_CH0_SB_N5 R_CH0_SB_N4 R_CH0_SB_N3 R_CH0_SB_N2 R_CH0_SB_N1 R_CH0_SB_N0
CK_H_FBD2 CK_H_FBD2_N
FBD_BR0_RST#
4
102
103 100
228 229
136
207 206 165 164
40 48 66 63 60 57 54 51 37 34 31 28 25 22
41 49 67 64 61 58 55 52 38 35 32 29 26 23
90 99
96 93 82 79 76 73 70
91
97 94 83 80 77 74 71
16
17
87 86 45 44
FBDIMM-1/2
PNP13 PNP12 PNP11 PNP10 PNP9 PNP8
Primarily Northbound
PNP7 PNP6 PNP5 PNP4 PNP3 PNP2 PNP1 PNP0
PNN13 PNN12 PNN11 PNN10 PNN9 PNN8 PNN7 PNN6 PNN5 PNN4 PNN3 PNN2 PNN1 PNN0
PSP9 PSP8
Primarily Southbound
PSP7 PSP6 PSP5 PSP4 PSP3 PSP2 PSP1 PSP0
PSN9 PSN8 PSN7 PSN6 PSN5 PSN4 PSN3 PSN2 PSN1 PSN0
SCKP SCKN
VID1 VID0
RESET_N
RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK
160
SNP13
168
SNP12
186
SNP11
183
SNP10
180
SNP9
177
SNP8
174
SNP7
171
SNP6
157
SNP5
154
SNP4
151
SNP3
148
SNP2
145
SNP1
142
SNP0
161
SNN13
169
SNN12
187
SNN11
184
SNN10
181
SNN9
178
SNN8
175
SNN7
172
Secondary NorthboundSecondary Southbound
SNN6
158
SNN5
155
SNN4
152
SNN3
149
SNN2
146
SNN1
143
SNN0
210
SSP9
222
SSP8
219
SSP7
216
SSP6
213
SSP5
202
SSP4
199
SSP3
196
SSP2
193
SSP1
190
SSP0
211
SSN9
223
SSN8
220
SSN7
217
SSN6
214
SSN5
203
SSN4
200
SSN3
197
SSN2
194
SSN1
191
SSN0
FBD0SCL
120
SCL SDA
SA2 SA1 SA0
M_TEST
RFU RFU RFU RFU RFU RFU RFU RFU
FBDIMM240
119 118
240 239
137 20 19 106 105 139 140 225 226
FBD0SDA FBD02SA2
FBD02SA1 FBD02SA0
3
P3V3
R1172
R1178 1K
1K
R1179 1K
FBD02SA2 FBD02SA1 FBD02SA0
DIMM SPD SMBus Address 0XA4 AMB SMBus Address LAI SPD SMBus Address LAI IOX SMBus Address
FBD0SCL 17,23,24 FBD0SDA 17,23,24
0XB4 0X24 0X74
2
P1V8 P1V5
FBDIMM-2/2
231
VDD
232
VDD
233
VDD
235
VDD
236
VDD
116
VDD
115
VDD
113
VDD
112
VDD
111
VDD
109
VDD
108
VDD
127
VDD
126
VDD
125
VDD
123
VDD
122
VDD
121
VDD
7
VDD
6
VDD
5
VDD
3
VDD
2
VDD
1
VDD
234
VSS
230
VSS
227
VSS
224
VSS
221
VSS
218
VSS
215
VSS
212
VSS
209
VSS
208
VSS
205
VSS
204
VSS
201
VSS
198
VSS
195
VSS
192
VSS
189
VSS
188
VSS
185
VSS
182
VSS
179
VSS
176
VSS
173
VSS
170
VSS
167
VSS
166
VSS
163
VSS
162
VSS
159
VSS
156
VSS
153
VSS
150
VSS
114
VSS
110
VSS
104
VSS
107
VSS
101
VSS
98
VSS
95
VSS
92
VSS
DIMM13B
VCC VCC VCC VCC VCC VCC VCC VCC
VTT VTT VTT VTT
VDDSPD
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
FBDIMM240
133 132 130 129 13 12 10 9
237 135 117 15
238
89 88 85 84 81 78 75 72 69 68 65 62 59 56 53 50 47 46 43 42 39 36 33 30 147 144 141 138 134 131 128 124 27 24 21 18 14 11 8 4
F_VTT
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
FBD Channel 0 DIMM 2
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
P3V3
C3231
0.1u
Share 0.1uF Cap. Between VDDSPD Pins Of DIMM0 & DIMM1
25 90
1
of
Rev
0A
Page 26
5
4
3
2
1
FBD Channel 1 DIMM 0
DIMM21A
FBD_CH1_NB_P[13..0]17
D D
C C
B B
A A
FBD_CH1_NB_N[13..0]17
FBD_CH1_SB_P[9..0]17 FBD_CH1_SB_N[9..0]17
5
FBD_CH1_NB_P[13..0] FBD_CH1_NB_N[13..0] FBD_CH1_SB_P[9..0] FBD_CH1_SB_N[9..0]
CK_H_FBD359
CK_H_FBD3_N59
FBD_BR0_RST#23,24,25,27,28,35
FBD_CH1_NB_P13 FBD_CH1_NB_P12 FBD_CH1_NB_P11 FBD_CH1_NB_P10 FBD_CH1_NB_P9 FBD_CH1_NB_P8 FBD_CH1_NB_P7 FBD_CH1_NB_P6 FBD_CH1_NB_P5 FBD_CH1_NB_P4 FBD_CH1_NB_P3 FBD_CH1_NB_P2 FBD_CH1_NB_P1 FBD_CH1_NB_P0
FBD_CH1_NB_N13 FBD_CH1_NB_N12 FBD_CH1_NB_N11 FBD_CH1_NB_N10 FBD_CH1_NB_N9 FBD_CH1_NB_N8 FBD_CH1_NB_N7 FBD_CH1_NB_N6 FBD_CH1_NB_N5 FBD_CH1_NB_N4 FBD_CH1_NB_N3 FBD_CH1_NB_N2 FBD_CH1_NB_N1 FBD_CH1_NB_N0
FBD_CH1_SB_P9 FBD_CH1_SB_P8 FBD_CH1_SB_P7 FBD_CH1_SB_P6 FBD_CH1_SB_P5 FBD_CH1_SB_P4 FBD_CH1_SB_P3 FBD_CH1_SB_P2 FBD_CH1_SB_P1 FBD_CH1_SB_P0
FBD_CH1_SB_N9 FBD_CH1_SB_N8 FBD_CH1_SB_N7 FBD_CH1_SB_N6 FBD_CH1_SB_N5 FBD_CH1_SB_N4 FBD_CH1_SB_N3 FBD_CH1_SB_N2 FBD_CH1_SB_N1 FBD_CH1_SB_N0
CK_H_FBD3 CK_H_FBD3_N
FBD_BR0_RST#
4
102
103 100
228 229
136
207 206 165 164
40 48 66 63 60 57 54 51 37 34 31 28 25 22
41 49 67 64 61 58 55 52 38 35 32 29 26 23
90 99
96 93 82 79 76 73 70
91
97 94 83 80 77 74 71
16
17
87 86 45 44
FBDIMM-1/2
PNP13 PNP12 PNP11 PNP10 PNP9 PNP8
Primarily Northbound
PNP7 PNP6 PNP5 PNP4 PNP3 PNP2 PNP1 PNP0
PNN13 PNN12 PNN11 PNN10 PNN9 PNN8 PNN7 PNN6 PNN5 PNN4 PNN3 PNN2 PNN1 PNN0
PSP9 PSP8
Primarily Southbound
PSP7 PSP6 PSP5 PSP4 PSP3 PSP2 PSP1 PSP0
PSN9 PSN8 PSN7 PSN6 PSN5 PSN4 PSN3 PSN2 PSN1 PSN0
SCKP SCKN
VID1 VID0
RESET_N
RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK
SNP13 SNP12 SNP11 SNP10
SNP9 SNP8 SNP7 SNP6 SNP5 SNP4 SNP3 SNP2 SNP1 SNP0
SNN13 SNN12 SNN11 SNN10
SNN9 SNN8 SNN7
Secondary NorthboundSecondary Southbound
SNN6 SNN5 SNN4 SNN3 SNN2 SNN1 SNN0
SSP9 SSP8 SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0
SSN9 SSN8 SSN7 SSN6 SSN5 SSN4 SSN3 SSN2 SSN1 SSN0
SCL SDA
SA2 SA1 SA0
M_TEST
RFU RFU RFU RFU RFU RFU RFU RFU
FBDIMM240
168 186 183 180 177 174 171 157 154 151 148 145 142
161 169 187 184 181 178 175 172 158 155 152 149 146 143
210 222 219 216 213 202 199 196 193 190
211 223 220 217 214 203 200 197 194 191
120 119
118 240 239
137 20 19 106 105 139 140 225 226
CH1_NB_P12 CH1_NB_P11 CH1_NB_P10 CH1_NB_P9 CH1_NB_P8 CH1_NB_P7 CH1_NB_P6 CH1_NB_P5 CH1_NB_P4 CH1_NB_P3 CH1_NB_P2 CH1_NB_P1 CH1_NB_P0
CH1_NB_N13 CH1_NB_N12 CH1_NB_N11 CH1_NB_N10 CH1_NB_N9 CH1_NB_N8 CH1_NB_N7 CH1_NB_N6 CH1_NB_N5 CH1_NB_N4 CH1_NB_N3 CH1_NB_N2 CH1_NB_N1 CH1_NB_N0
CH1_SB_P9 CH1_SB_P8 CH1_SB_P7 CH1_SB_P6 CH1_SB_P5 CH1_SB_P4 CH1_SB_P3 CH1_SB_P2 CH1_SB_P1 CH1_SB_P0
CH1_SB_N9 CH1_SB_N8 CH1_SB_N7 CH1_SB_N6 CH1_SB_N5 CH1_SB_N4 CH1_SB_N3 CH1_SB_N2 CH1_SB_N1 CH1_SB_N0
FBD1SCL FBD1SDA
FBD10SA2 FBD10SA1 FBD10SA0
3
CH1_NB_P13
160
CH1_NB_P[13..0] CH1_NB_N[13..0] CH1_SB_P[9..0] CH1_SB_N[9..0]
FBD10SA2 FBD10SA1 FBD10SA0
CH1_NB_P[13..0] 27 CH1_NB_N[13..0] 27 CH1_SB_P[9..0] 27 CH1_SB_N[9..0] 27
R1164 1K
DIMM SPD SMBus Address 0XA0 AMB SMBus Address LAI SPD SMBus Address LAI IOX SMBus Address
FBD1SCL 17,27,28 FBD1SDA 17,27,28
R1165 1K
R1166 1K
0XB0 0X20 0X70
2
P1V8 P1V5
FBDIMM-2/2
231
VDD
232
VDD
233
VDD
235
VDD
236
VDD
116
VDD
115
VDD
113
VDD
112
VDD
111
VDD
109
VDD
108
VDD
127
VDD
126
VDD
125
VDD
123
VDD
122
VDD
121
VDD
7
VDD
6
VDD
5
VDD
3
VDD
2
VDD
1
VDD
234
VSS
230
VSS
227
VSS
224
VSS
221
VSS
218
VSS
215
VSS
212
VSS
209
VSS
208
VSS
205
VSS
204
VSS
201
VSS
198
VSS
195
VSS
192
VSS
189
VSS
188
VSS
185
VSS
182
VSS
179
VSS
176
VSS
173
VSS
170
VSS
167
VSS
166
VSS
163
VSS
162
VSS
159
VSS
156
VSS
153
VSS
150
VSS
114
VSS
110
VSS
104
VSS
107
VSS
101
VSS
98
VSS
95
VSS
92
VSS
DIMM21B
VCC VCC VCC VCC VCC VCC VCC VCC
VTT VTT VTT VTT
VDDSPD
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
FBDIMM240
133 132 130 129 13 12 10 9
237 135 117 15
238
89 88 85 84 81 78 75 72 69 68 65 62 59 56 53 50 47 46 43 42 39 36 33 30 147 144 141 138 134 131 128 124 27 24 21 18 14 11 8 4
F_VTT
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
FBD Channel 1 DIMM 0
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
P3V3
C3232
0.1u
Share 0.1uF Cap. Between VDDSPD Pins Of DIMM0 & DIMM1
26 90
1
of
Rev
0A
Page 27
5
4
3
2
1
FBD Channel 1 DIMM 1
DIMM22A
CH1_NB_P[13..0]26
D D
C C
B B
A A
CH1_NB_N[13..0]26
CH1_SB_P[9..0]26 CH1_SB_N[9..0]26
5
CH1_NB_P[13..0] CH1_NB_N[13..0] CH1_SB_P[9..0] CH1_SB_N[9..0]
CK_H_FBD459
CK_H_FBD4_N59
FBD_BR0_RST#23,24,25,26,28,35
CH1_NB_P13 CH1_NB_P12 CH1_NB_P11 CH1_NB_P10 CH1_NB_P9 CH1_NB_P8 CH1_NB_P7 CH1_NB_P6 CH1_NB_P5 CH1_NB_P4 CH1_NB_P3 CH1_NB_P2 CH1_NB_P1 CH1_NB_P0
CH1_NB_N13 CH1_NB_N12 CH1_NB_N11 CH1_NB_N10 CH1_NB_N9 CH1_NB_N8 CH1_NB_N7 CH1_NB_N6 CH1_NB_N5 CH1_NB_N4 CH1_NB_N3 CH1_NB_N2 CH1_NB_N1 CH1_NB_N0
CH1_SB_P9 CH1_SB_P8 CH1_SB_P7 CH1_SB_P6 CH1_SB_P5 CH1_SB_P4 CH1_SB_P3 CH1_SB_P2 CH1_SB_P1 CH1_SB_P0
CH1_SB_N9 CH1_SB_N8 CH1_SB_N7 CH1_SB_N6 CH1_SB_N5 CH1_SB_N4 CH1_SB_N3 CH1_SB_N2 CH1_SB_N1 CH1_SB_N0
CK_H_FBD4 CK_H_FBD4_N
FBD_BR0_RST#
4
102
103 100
228 229
136
207 206 165 164
40 48 66 63 60 57 54 51 37 34 31 28 25 22
41 49 67 64 61 58 55 52 38 35 32 29 26 23
90 99
96 93 82 79 76 73 70
91
97 94 83 80 77 74 71
16
17
87 86 45 44
FBDIMM-1/2
PNP13 PNP12 PNP11 PNP10 PNP9 PNP8
Primarily Northbound
PNP7 PNP6 PNP5 PNP4 PNP3 PNP2 PNP1 PNP0
PNN13 PNN12 PNN11 PNN10 PNN9 PNN8 PNN7 PNN6 PNN5 PNN4 PNN3 PNN2 PNN1 PNN0
PSP9 PSP8
Primarily Southbound
PSP7 PSP6 PSP5 PSP4 PSP3 PSP2 PSP1 PSP0
PSN9 PSN8 PSN7 PSN6 PSN5 PSN4 PSN3 PSN2 PSN1 PSN0
SCKP SCKN
VID1 VID0
RESET_N
RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK
SNP13 SNP12 SNP11 SNP10
SNP9 SNP8 SNP7 SNP6 SNP5 SNP4 SNP3 SNP2 SNP1 SNP0
SNN13 SNN12 SNN11 SNN10
SNN9 SNN8 SNN7
Secondary NorthboundSecondary Southbound
SNN6 SNN5 SNN4 SNN3 SNN2 SNN1 SNN0
SSP9 SSP8 SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0
SSN9 SSN8 SSN7 SSN6 SSN5 SSN4 SSN3 SSN2 SSN1 SSN0
SCL SDA
SA2 SA1 SA0
M_TEST
RFU RFU RFU RFU RFU RFU RFU RFU
FBDIMM240
168 186 183 180 177 174 171 157 154 151 148 145 142
161 169 187 184 181 178 175 172 158 155 152 149 146 143
210 222 219 216 213 202 199 196 193 190
211 223 220 217 214 203 200 197 194 191
120 119
118 240 239
137 20 19 106 105 139 140 225 226
R_CH1_NB_P12 R_CH1_NB_P11 R_CH1_NB_P10 R_CH1_NB_P9 R_CH1_NB_P8 R_CH1_NB_P7 R_CH1_NB_P6 R_CH1_NB_P5 R_CH1_NB_P4 R_CH1_NB_P3 R_CH1_NB_P2 R_CH1_NB_P1 R_CH1_NB_P0
R_CH1_NB_N13 R_CH1_NB_N12 R_CH1_NB_N11 R_CH1_NB_N10 R_CH1_NB_N9 R_CH1_NB_N8 R_CH1_NB_N7 R_CH1_NB_N6 R_CH1_NB_N5 R_CH1_NB_N4 R_CH1_NB_N3 R_CH1_NB_N2 R_CH1_NB_N1 R_CH1_NB_N0
R_CH1_SB_P9 R_CH1_SB_P8 R_CH1_SB_P7 R_CH1_SB_P6 R_CH1_SB_P5 R_CH1_SB_P4 R_CH1_SB_P3 R_CH1_SB_P2 R_CH1_SB_P1 R_CH1_SB_P0
R_CH1_SB_N9 R_CH1_SB_N8 R_CH1_SB_N7 R_CH1_SB_N6 R_CH1_SB_N5 R_CH1_SB_N4 R_CH1_SB_N3 R_CH1_SB_N2 R_CH1_SB_N1 R_CH1_SB_N0
FBD1SCL FBD1SDA
FBD11SA2 FBD11SA1 FBD11SA0
3
R_CH1_NB_P13
160
R_CH1_NB_P[13..0] R_CH1_NB_N[13..0] R_CH1_SB_P[9..0] R_CH1_SB_N[9..0]
FBD11SA2 FBD11SA1 FBD11SA0
R_CH1_NB_P[13..0] 28 R_CH1_NB_N[13..0] 28 R_CH1_SB_P[9..0] 28 R_CH1_SB_N[9..0] 28
P3V3
R1162 1K
DIMM SPD SMBus Address 0XA2 AMB SMBus Address LAI SPD SMBus Address LAI IOX SMBus Address
FBD1SCL 17,26,28 FBD1SDA 17,26,28
R1167 1K
R1168 1K
0XB2 0X22 0X72
2
P1V8 P1V5
FBDIMM-2/2
231
VDD
232
VDD
233
VDD
235
VDD
236
VDD
116
VDD
115
VDD
113
VDD
112
VDD
111
VDD
109
VDD
108
VDD
127
VDD
126
VDD
125
VDD
123
VDD
122
VDD
121
VDD
7
VDD
6
VDD
5
VDD
3
VDD
2
VDD
1
VDD
234
VSS
230
VSS
227
VSS
224
VSS
221
VSS
218
VSS
215
VSS
212
VSS
209
VSS
208
VSS
205
VSS
204
VSS
201
VSS
198
VSS
195
VSS
192
VSS
189
VSS
188
VSS
185
VSS
182
VSS
179
VSS
176
VSS
173
VSS
170
VSS
167
VSS
166
VSS
163
VSS
162
VSS
159
VSS
156
VSS
153
VSS
150
VSS
114
VSS
110
VSS
104
VSS
107
VSS
101
VSS
98
VSS
95
VSS
92
VSS
DIMM22B
VCC VCC VCC VCC VCC VCC VCC VCC
VTT VTT VTT VTT
VDDSPD
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
FBDIMM240
133 132 130 129 13 12 10 9
237 135 117 15
238
89 88 85 84 81 78 75 72 69 68 65 62 59 56 53 50 47 46 43 42 39 36 33 30 147 144 141 138 134 131 128 124 27 24 21 18 14 11 8 4
F_VTT
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
FBD Channel 1 DIMM 1
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
P3V3
C3233
0.1u
Share 0.1uF Cap. Between VDDSPD Pins Of DIMM0 & DIMM1
27 90
1
of
Rev
0A
Page 28
5
4
3
2
1
FBD Channel 1 DIMM 2
DIMM23A
R_CH1_NB_P[13..0]27
D D
C C
B B
A A
R_CH1_NB_N[13..0]27
R_CH1_SB_P[9..0]27 R_CH1_SB_N[9..0]27
5
R_CH1_NB_P[13..0] R_CH1_NB_N[13..0] R_CH1_SB_P[9..0] R_CH1_SB_N[9..0]
CK_H_FBD559
CK_H_FBD5_N59
FBD_BR0_RST#23,24,25,26,27,35
R_CH1_NB_P13 R_CH1_NB_P12 R_CH1_NB_P11 R_CH1_NB_P10 R_CH1_NB_P9 R_CH1_NB_P8 R_CH1_NB_P7 R_CH1_NB_P6 R_CH1_NB_P5 R_CH1_NB_P4 R_CH1_NB_P3 R_CH1_NB_P2 R_CH1_NB_P1 R_CH1_NB_P0
R_CH1_NB_N13 R_CH1_NB_N12 R_CH1_NB_N11 R_CH1_NB_N10 R_CH1_NB_N9 R_CH1_NB_N8 R_CH1_NB_N7 R_CH1_NB_N6 R_CH1_NB_N5 R_CH1_NB_N4 R_CH1_NB_N3 R_CH1_NB_N2 R_CH1_NB_N1 R_CH1_NB_N0
R_CH1_SB_P9 R_CH1_SB_P8 R_CH1_SB_P7 R_CH1_SB_P6 R_CH1_SB_P5 R_CH1_SB_P4 R_CH1_SB_P3 R_CH1_SB_P2 R_CH1_SB_P1 R_CH1_SB_P0
R_CH1_SB_N9 R_CH1_SB_N8 R_CH1_SB_N7 R_CH1_SB_N6 R_CH1_SB_N5 R_CH1_SB_N4 R_CH1_SB_N3 R_CH1_SB_N2 R_CH1_SB_N1 R_CH1_SB_N0
CK_H_FBD5 CK_H_FBD5_N
FBD_BR0_RST#
4
102
103 100
228 229
136
207 206 165 164
40 48 66 63 60 57 54 51 37 34 31 28 25 22
41 49 67 64 61 58 55 52 38 35 32 29 26 23
90 99
96 93 82 79 76 73 70
91
97 94 83 80 77 74 71
16
17
87 86 45 44
FBDIMM-1/2
PNP13 PNP12 PNP11 PNP10 PNP9 PNP8
Primarily Northbound
PNP7 PNP6 PNP5 PNP4 PNP3 PNP2 PNP1 PNP0
PNN13 PNN12 PNN11 PNN10 PNN9 PNN8 PNN7 PNN6 PNN5 PNN4 PNN3 PNN2 PNN1 PNN0
PSP9 PSP8
Primarily Southbound
PSP7 PSP6 PSP5 PSP4 PSP3 PSP2 PSP1 PSP0
PSN9 PSN8 PSN7 PSN6 PSN5 PSN4 PSN3 PSN2 PSN1 PSN0
SCKP SCKN
VID1 VID0
RESET_N
RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK
160
SNP13
168
SNP12
186
SNP11
183
SNP10
180
SNP9
177
SNP8
174
SNP7
171
SNP6
157
SNP5
154
SNP4
151
SNP3
148
SNP2
145
SNP1
142
SNP0
161
SNN13
169
SNN12
187
SNN11
184
SNN10
181
SNN9
178
SNN8
175
SNN7
172
Secondary NorthboundSecondary Southbound
SNN6
158
SNN5
155
SNN4
152
SNN3
149
SNN2
146
SNN1
143
SNN0
210
SSP9
222
SSP8
219
SSP7
216
SSP6
213
SSP5
202
SSP4
199
SSP3
196
SSP2
193
SSP1
190
SSP0
211
SSN9
223
SSN8
220
SSN7
217
SSN6
214
SSN5
203
SSN4
200
SSN3
197
SSN2
194
SSN1
191
SSN0
FBD1SCL
120
SCL SDA
SA2 SA1 SA0
M_TEST
RFU RFU RFU RFU RFU RFU RFU RFU
FBDIMM240
119 118
240 239
137 20 19 106 105 139 140 225 226
FBD1SDA FBD12SA2
FBD12SA1 FBD12SA0
3
P3V3
R1163 1K
FBD12SA2 FBD12SA1 FBD12SA0
R1169 1K
R1170 1K
DIMM SPD SMBus Address 0XA4 AMB SMBus Address LAI SPD SMBus Address LAI IOX SMBus Address
FBD1SCL 17,26,27 FBD1SDA 17,26,27
0XB4 0X24 0X74
2
P1V8 P1V5
FBDIMM-2/2
231
VDD
232
VDD
233
VDD
235
VDD
236
VDD
116
VDD
115
VDD
113
VDD
112
VDD
111
VDD
109
VDD
108
VDD
127
VDD
126
VDD
125
VDD
123
VDD
122
VDD
121
VDD
7
VDD
6
VDD
5
VDD
3
VDD
2
VDD
1
VDD
234
VSS
230
VSS
227
VSS
224
VSS
221
VSS
218
VSS
215
VSS
212
VSS
209
VSS
208
VSS
205
VSS
204
VSS
201
VSS
198
VSS
195
VSS
192
VSS
189
VSS
188
VSS
185
VSS
182
VSS
179
VSS
176
VSS
173
VSS
170
VSS
167
VSS
166
VSS
163
VSS
162
VSS
159
VSS
156
VSS
153
VSS
150
VSS
114
VSS
110
VSS
104
VSS
107
VSS
101
VSS
98
VSS
95
VSS
92
VSS
DIMM23B
VCC VCC VCC VCC VCC VCC VCC VCC
VTT VTT VTT VTT
VDDSPD
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
FBDIMM240
133 132 130 129 13 12 10 9
237 135 117 15
238
89 88 85 84 81 78 75 72 69 68 65 62 59 56 53 50 47 46 43 42 39 36 33 30 147 144 141 138 134 131 128 124 27 24 21 18 14 11 8 4
F_VTT
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
FBD Channel 1 DIMM 2
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
P3V3
C3234
0.1u
Share 0.1uF Cap. Between VDDSPD Pins Of DIMM0 & DIMM1
28 90
1
of
Rev
0A
Page 29
5
4
3
2
1
FBD Channel 2 DIMM 0
DIMM31A
FBD_CH2_NB_P[13..0]18
D D
C C
B B
A A
FBD_CH2_NB_N[13..0]18
FBD_CH2_SB_P[9..0]18 FBD_CH2_SB_N[9..0]18
5
FBD_CH2_NB_P[13..0] FBD_CH2_NB_N[13..0] CH2_NB_N[13..0] FBD_CH2_SB_P[9..0] FBD_CH2_SB_N[9..0]
CK_H_FBD659
CK_H_FBD6_N59
FBD_BR1_RST#30,31,32,33,34,35
FBD_CH2_NB_P13 FBD_CH2_NB_P12 FBD_CH2_NB_P11 FBD_CH2_NB_P10 FBD_CH2_NB_P9 FBD_CH2_NB_P8 FBD_CH2_NB_P7 FBD_CH2_NB_P6 FBD_CH2_NB_P5 FBD_CH2_NB_P4 FBD_CH2_NB_P3 FBD_CH2_NB_P2 FBD_CH2_NB_P1 FBD_CH2_NB_P0
FBD_CH2_NB_N13 FBD_CH2_NB_N12 FBD_CH2_NB_N11 FBD_CH2_NB_N10 FBD_CH2_NB_N9 FBD_CH2_NB_N8 FBD_CH2_NB_N7 FBD_CH2_NB_N6 FBD_CH2_NB_N5 FBD_CH2_NB_N4 FBD_CH2_NB_N3 FBD_CH2_NB_N2 FBD_CH2_NB_N1 FBD_CH2_NB_N0
FBD_CH2_SB_P9 FBD_CH2_SB_P8 FBD_CH2_SB_P7 FBD_CH2_SB_P6 FBD_CH2_SB_P5 FBD_CH2_SB_P4 FBD_CH2_SB_P3 FBD_CH2_SB_P2 FBD_CH2_SB_P1 FBD_CH2_SB_P0
FBD_CH2_SB_N9 FBD_CH2_SB_N8 FBD_CH2_SB_N7 FBD_CH2_SB_N6 FBD_CH2_SB_N5 FBD_CH2_SB_N4 FBD_CH2_SB_N3 FBD_CH2_SB_N2 FBD_CH2_SB_N1 FBD_CH2_SB_N0
CK_H_FBD6 CK_H_FBD6_N
FBD_BR1_RST#
4
102
103 100
228 229
136
207 206 165 164
40 48 66 63 60 57 54 51 37 34 31 28 25 22
41 49 67 64 61 58 55 52 38 35 32 29 26 23
90 99
96 93 82 79 76 73 70
91
97 94 83 80 77 74 71
16
17
87 86 45 44
FBDIMM-1/2
PNP13 PNP12 PNP11 PNP10 PNP9 PNP8
Primarily Northbound
PNP7 PNP6 PNP5 PNP4 PNP3 PNP2 PNP1 PNP0
PNN13 PNN12 PNN11 PNN10 PNN9 PNN8 PNN7 PNN6 PNN5 PNN4 PNN3 PNN2 PNN1 PNN0
PSP9 PSP8
Primarily Southbound
PSP7 PSP6 PSP5 PSP4 PSP3 PSP2 PSP1 PSP0
PSN9 PSN8 PSN7 PSN6 PSN5 PSN4 PSN3 PSN2 PSN1 PSN0
SCKP SCKN
VID1 VID0
RESET_N
RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK
SNP13 SNP12 SNP11 SNP10
SNP9 SNP8 SNP7 SNP6 SNP5 SNP4 SNP3 SNP2 SNP1 SNP0
SNN13 SNN12 SNN11 SNN10
SNN9 SNN8 SNN7
Secondary NorthboundSecondary Southbound
SNN6 SNN5 SNN4 SNN3 SNN2 SNN1 SNN0
SSP9 SSP8 SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0
SSN9 SSN8 SSN7 SSN6 SSN5 SSN4 SSN3 SSN2 SSN1 SSN0
SCL SDA
SA2 SA1 SA0
M_TEST
RFU RFU RFU RFU RFU RFU RFU RFU
FBDIMM240
168 186 183 180 177 174 171 157 154 151 148 145 142
161 169 187 184 181 178 175 172 158 155 152 149 146 143
210 222 219 216 213 202 199 196 193 190
211 223 220 217 214 203 200 197 194 191
120 119
118 240 239
137 20 19 106 105 139 140 225 226
CH2_NB_P12 CH2_NB_P11 CH2_NB_P10 CH2_NB_P9 CH2_NB_P8 CH2_NB_P7 CH2_NB_P6 CH2_NB_P5 CH2_NB_P4 CH2_NB_P3 CH2_NB_P2 CH2_NB_P1 CH2_NB_P0
CH2_NB_N13 CH2_NB_N12 CH2_NB_N11 CH2_NB_N10 CH2_NB_N9 CH2_NB_N8 CH2_NB_N7 CH2_NB_N6 CH2_NB_N5 CH2_NB_N4 CH2_NB_N3 CH2_NB_N2 CH2_NB_N1 CH2_NB_N0
CH2_SB_P9 CH2_SB_P8 CH2_SB_P7 CH2_SB_P6 CH2_SB_P5 CH2_SB_P4 CH2_SB_P3 CH2_SB_P2 CH2_SB_P1 CH2_SB_P0
CH2_SB_N9 CH2_SB_N8 CH2_SB_N7 CH2_SB_N6 CH2_SB_N5 CH2_SB_N4 CH2_SB_N3 CH2_SB_N2 CH2_SB_N1 CH2_SB_N0
FBD2SCL FBD2SDA
FBD20SA2 FBD20SA1 FBD20SA0
3
CH2_NB_P13
160
CH2_NB_P[13..0]
CH2_SB_P[9..0] CH2_SB_N[9..0]
FBD20SA2 FBD20SA1 FBD20SA0
CH2_NB_P[13..0] 30 CH2_NB_N[13..0] 30 CH2_SB_P[9..0] 30 CH2_SB_N[9..0] 30
R1150 1K
DIMM SPD SMBus Address 0XA0 AMB SMBus Address LAI SPD SMBus Address LAI IOX SMBus Address
FBD2SCL 17,18,30,31 FBD2SDA 17,18,30,31
R1151 1K
R1152 1K
0XB0 0X20 0X70
2
P1V8 P1V5
FBDIMM-2/2
231
VDD
232
VDD
233
VDD
235
VDD
236
VDD
116
VDD
115
VDD
113
VDD
112
VDD
111
VDD
109
VDD
108
VDD
127
VDD
126
VDD
125
VDD
123
VDD
122
VDD
121
VDD
7
VDD
6
VDD
5
VDD
3
VDD
2
VDD
1
VDD
234
VSS
230
VSS
227
VSS
224
VSS
221
VSS
218
VSS
215
VSS
212
VSS
209
VSS
208
VSS
205
VSS
204
VSS
201
VSS
198
VSS
195
VSS
192
VSS
189
VSS
188
VSS
185
VSS
182
VSS
179
VSS
176
VSS
173
VSS
170
VSS
167
VSS
166
VSS
163
VSS
162
VSS
159
VSS
156
VSS
153
VSS
150
VSS
114
VSS
110
VSS
104
VSS
107
VSS
101
VSS
98
VSS
95
VSS
92
VSS
DIMM31B
VCC VCC VCC VCC VCC VCC VCC VCC
VTT VTT VTT VTT
VDDSPD
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
FBDIMM240
133 132 130 129 13 12 10 9
237 135 117 15
238
89 88 85 84 81 78 75 72 69 68 65 62 59 56 53 50 47 46 43 42 39 36 33 30 147 144 141 138 134 131 128 124 27 24 21 18 14 11 8 4
F_VTT
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
FBD Channel 2 DIMM 0
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
P3V3
C3235
0.1u
Share 0.1uF Cap. Between VDDSPD Pins Of DIMM0 & DIMM1
29 90
1
of
Rev
0A
Page 30
5
4
3
2
1
FBD Channel 2 DIMM 1
DIMM32A
CH2_NB_P[13..0]29
D D
C C
B B
A A
CH2_NB_N[13..0]29
CH2_SB_P[9..0]29 CH2_SB_N[9..0]29
5
CH2_NB_P[13..0] R_CH2_NB_P[13..0] CH2_NB_N[13..0] R_CH2_NB_N[13..0] CH2_SB_P[9..0] CH2_SB_N[9..0]
CK_H_FBD759
CK_H_FBD7_N59
FBD_BR1_RST#29,31,32,33,34,35
CH2_NB_P13 CH2_NB_P12 CH2_NB_P11 CH2_NB_P10 CH2_NB_P9 CH2_NB_P8 CH2_NB_P7 CH2_NB_P6 CH2_NB_P5 CH2_NB_P4 CH2_NB_P3 CH2_NB_P2 CH2_NB_P1 CH2_NB_P0
CH2_NB_N13 CH2_NB_N12 CH2_NB_N11 CH2_NB_N10 CH2_NB_N9 CH2_NB_N8 CH2_NB_N7 CH2_NB_N6 CH2_NB_N5 CH2_NB_N4 CH2_NB_N3 CH2_NB_N2 CH2_NB_N1 CH2_NB_N0
CH2_SB_P9 CH2_SB_P8 CH2_SB_P7 CH2_SB_P6 CH2_SB_P5 CH2_SB_P4 CH2_SB_P3 CH2_SB_P2 CH2_SB_P1 CH2_SB_P0
CH2_SB_N9 CH2_SB_N8 CH2_SB_N7 CH2_SB_N6 CH2_SB_N5 CH2_SB_N4 CH2_SB_N3 CH2_SB_N2 CH2_SB_N1 CH2_SB_N0
CK_H_FBD7 CK_H_FBD7_N
FBD_BR1_RST#
4
102
103 100
228 229
136
207 206 165 164
40 48 66 63 60 57 54 51 37 34 31 28 25 22
41 49 67 64 61 58 55 52 38 35 32 29 26 23
90 99
96 93 82 79 76 73 70
91
97 94 83 80 77 74 71
16
17
87 86 45 44
FBDIMM-1/2
PNP13 PNP12 PNP11 PNP10 PNP9 PNP8
Primarily Northbound
PNP7 PNP6 PNP5 PNP4 PNP3 PNP2 PNP1 PNP0
PNN13 PNN12 PNN11 PNN10 PNN9 PNN8 PNN7 PNN6 PNN5 PNN4 PNN3 PNN2 PNN1 PNN0
PSP9 PSP8
Primarily Southbound
PSP7 PSP6 PSP5 PSP4 PSP3 PSP2 PSP1 PSP0
PSN9 PSN8 PSN7 PSN6 PSN5 PSN4 PSN3 PSN2 PSN1 PSN0
SCKP SCKN
VID1 VID0
RESET_N
RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK
SNP13 SNP12 SNP11 SNP10
SNP9 SNP8 SNP7 SNP6 SNP5 SNP4 SNP3 SNP2 SNP1 SNP0
SNN13 SNN12 SNN11 SNN10
SNN9 SNN8 SNN7
Secondary NorthboundSecondary Southbound
SNN6 SNN5 SNN4 SNN3 SNN2 SNN1 SNN0
SSP9 SSP8 SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0
SSN9 SSN8 SSN7 SSN6 SSN5 SSN4 SSN3 SSN2 SSN1 SSN0
SCL SDA
SA2 SA1 SA0
M_TEST
RFU RFU RFU RFU RFU RFU RFU RFU
FBDIMM240
168 186 183 180 177 174 171 157 154 151 148 145 142
161 169 187 184 181 178 175 172 158 155 152 149 146 143
210 222 219 216 213 202 199 196 193 190
211 223 220 217 214 203 200 197 194 191
120 119
118 240 239
137 20 19 106 105 139 140 225 226
R_CH2_NB_P12 R_CH2_NB_P11 R_CH2_NB_P10 R_CH2_NB_P9 R_CH2_NB_P8 R_CH2_NB_P7 R_CH2_NB_P6 R_CH2_NB_P5 R_CH2_NB_P4 R_CH2_NB_P3 R_CH2_NB_P2 R_CH2_NB_P1 R_CH2_NB_P0
R_CH2_NB_N13 R_CH2_NB_N12 R_CH2_NB_N11 R_CH2_NB_N10 R_CH2_NB_N9 R_CH2_NB_N8 R_CH2_NB_N7 R_CH2_NB_N6 R_CH2_NB_N5 R_CH2_NB_N4 R_CH2_NB_N3 R_CH2_NB_N2 R_CH2_NB_N1 R_CH2_NB_N0
R_CH2_SB_P9 R_CH2_SB_P8 R_CH2_SB_P7 R_CH2_SB_P6 R_CH2_SB_P5 R_CH2_SB_P4 R_CH2_SB_P3 R_CH2_SB_P2 R_CH2_SB_P1 R_CH2_SB_P0
R_CH2_SB_N9 R_CH2_SB_N8 R_CH2_SB_N7 R_CH2_SB_N6 R_CH2_SB_N5 R_CH2_SB_N4 R_CH2_SB_N3 R_CH2_SB_N2 R_CH2_SB_N1 R_CH2_SB_N0
FBD2SCL FBD2SDA
FBD21SA2 FBD21SA1 FBD21SA0
3
R_CH2_NB_P13
160
R_CH2_SB_P[9..0] R_CH2_SB_N[9..0]
FBD21SA2 FBD21SA1 FBD21SA0
DIMM SPD SMBus Address 0XA2 AMB SMBus Address LAI SPD SMBus Address LAI IOX SMBus Address
FBD2SCL 17,18,29,31 FBD2SDA 17,18,29,31
R_CH2_NB_P[13..0] 31 R_CH2_NB_N[13..0] 31 R_CH2_SB_P[9..0] 31 R_CH2_SB_N[9..0] 31
P3V3
R1148 1K
R1154
R1153
1K
1K
0XB2 0X22 0X72
2
P1V8 P1V5
FBDIMM-2/2
231
VDD
232
VDD
233
VDD
235
VDD
236
VDD
116
VDD
115
VDD
113
VDD
112
VDD
111
VDD
109
VDD
108
VDD
127
VDD
126
VDD
125
VDD
123
VDD
122
VDD
121
VDD
7
VDD
6
VDD
5
VDD
3
VDD
2
VDD
1
VDD
234
VSS
230
VSS
227
VSS
224
VSS
221
VSS
218
VSS
215
VSS
212
VSS
209
VSS
208
VSS
205
VSS
204
VSS
201
VSS
198
VSS
195
VSS
192
VSS
189
VSS
188
VSS
185
VSS
182
VSS
179
VSS
176
VSS
173
VSS
170
VSS
167
VSS
166
VSS
163
VSS
162
VSS
159
VSS
156
VSS
153
VSS
150
VSS
114
VSS
110
VSS
104
VSS
107
VSS
101
VSS
98
VSS
95
VSS
92
VSS
DIMM32B
VCC VCC VCC VCC VCC VCC VCC VCC
VTT VTT VTT VTT
VDDSPD
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
FBDIMM240
133 132 130 129 13 12 10 9
237 135 117 15
238
89 88 85 84 81 78 75 72 69 68 65 62 59 56 53 50 47 46 43 42 39 36 33 30 147 144 141 138 134 131 128 124 27 24 21 18 14 11 8 4
F_VTT
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
FBD Channel 2 DIMM 1
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
P3V3
C3236
0.1u
Share 0.1uF Cap. Between VDDSPD Pins Of DIMM0 & DIMM1
30 90
1
of
Rev
0A
Page 31
5
4
3
2
1
FBD Channel 2 DIMM 2
DIMM33A
R_CH2_NB_P[13..0]30
D D
C C
B B
A A
R_CH2_NB_N[13..0]30
R_CH2_SB_P[9..0]30 R_CH2_SB_N[9..0]30
5
R_CH2_NB_P[13..0] R_CH2_NB_N[13..0] R_CH2_SB_P[9..0] R_CH2_SB_N[9..0]
CK_H_FBD859
CK_H_FBD8_N59
FBD_BR1_RST#29,30,32,33,34,35
R_CH2_NB_P13 R_CH2_NB_P12 R_CH2_NB_P11 R_CH2_NB_P10 R_CH2_NB_P9 R_CH2_NB_P8 R_CH2_NB_P7 R_CH2_NB_P6 R_CH2_NB_P5 R_CH2_NB_P4 R_CH2_NB_P3 R_CH2_NB_P2 R_CH2_NB_P1 R_CH2_NB_P0
R_CH2_NB_N13 R_CH2_NB_N12 R_CH2_NB_N11 R_CH2_NB_N10 R_CH2_NB_N9 R_CH2_NB_N8 R_CH2_NB_N7 R_CH2_NB_N6 R_CH2_NB_N5 R_CH2_NB_N4 R_CH2_NB_N3 R_CH2_NB_N2 R_CH2_NB_N1 R_CH2_NB_N0
R_CH2_SB_P9 R_CH2_SB_P8 R_CH2_SB_P7 R_CH2_SB_P6 R_CH2_SB_P5 R_CH2_SB_P4 R_CH2_SB_P3 R_CH2_SB_P2 R_CH2_SB_P1 R_CH2_SB_P0
R_CH2_SB_N9 R_CH2_SB_N8 R_CH2_SB_N7 R_CH2_SB_N6 R_CH2_SB_N5 R_CH2_SB_N4 R_CH2_SB_N3 R_CH2_SB_N2 R_CH2_SB_N1 R_CH2_SB_N0
CK_H_FBD8 CK_H_FBD8_N
FBD_BR1_RST#
4
102
103 100
228 229
136
207 206 165 164
40 48 66 63 60 57 54 51 37 34 31 28 25 22
41 49 67 64 61 58 55 52 38 35 32 29 26 23
90 99
96 93 82 79 76 73 70
91
97 94 83 80 77 74 71
16
17
87 86 45 44
FBDIMM-1/2
PNP13 PNP12 PNP11 PNP10 PNP9 PNP8
Primarily Northbound
PNP7 PNP6 PNP5 PNP4 PNP3 PNP2 PNP1 PNP0
PNN13 PNN12 PNN11 PNN10 PNN9 PNN8 PNN7 PNN6 PNN5 PNN4 PNN3 PNN2 PNN1 PNN0
PSP9 PSP8
Primarily Southbound
PSP7 PSP6 PSP5 PSP4 PSP3 PSP2 PSP1 PSP0
PSN9 PSN8 PSN7 PSN6 PSN5 PSN4 PSN3 PSN2 PSN1 PSN0
SCKP SCKN
VID1 VID0
RESET_N
RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK
160
SNP13
168
SNP12
186
SNP11
183
SNP10
180
SNP9
177
SNP8
174
SNP7
171
SNP6
157
SNP5
154
SNP4
151
SNP3
148
SNP2
145
SNP1
142
SNP0
161
SNN13
169
SNN12
187
SNN11
184
SNN10
181
SNN9
178
SNN8
175
SNN7
172
Secondary NorthboundSecondary Southbound
SNN6
158
SNN5
155
SNN4
152
SNN3
149
SNN2
146
SNN1
143
SNN0
210
SSP9
222
SSP8
219
SSP7
216
SSP6
213
SSP5
202
SSP4
199
SSP3
196
SSP2
193
SSP1
190
SSP0
211
SSN9
223
SSN8
220
SSN7
217
SSN6
214
SSN5
203
SSN4
200
SSN3
197
SSN2
194
SSN1
191
SSN0
FBD2SCL
120
SCL SDA
SA2 SA1 SA0
M_TEST
RFU RFU RFU RFU RFU RFU RFU RFU
FBDIMM240
119 118
240 239
137 20 19 106 105 139 140 225 226
FBD2SDA FBD22SA2
FBD22SA1 FBD22SA0
3
P3V3
R1149
R1155 1K
1K
R1156 1K
FBD22SA2 FBD22SA1 FBD22SA0
DIMM SPD SMBus Address 0XA4 AMB SMBus Address LAI SPD SMBus Address LAI IOX SMBus Address
FBD2SCL 17,18,29,30 FBD2SDA 17,18,29,30
0XB4 0X24 0X74
2
P1V8 P1V5
FBDIMM-2/2
231
VDD
232
VDD
233
VDD
235
VDD
236
VDD
116
VDD
115
VDD
113
VDD
112
VDD
111
VDD
109
VDD
108
VDD
127
VDD
126
VDD
125
VDD
123
VDD
122
VDD
121
VDD
7
VDD
6
VDD
5
VDD
3
VDD
2
VDD
1
VDD
234
VSS
230
VSS
227
VSS
224
VSS
221
VSS
218
VSS
215
VSS
212
VSS
209
VSS
208
VSS
205
VSS
204
VSS
201
VSS
198
VSS
195
VSS
192
VSS
189
VSS
188
VSS
185
VSS
182
VSS
179
VSS
176
VSS
173
VSS
170
VSS
167
VSS
166
VSS
163
VSS
162
VSS
159
VSS
156
VSS
153
VSS
150
VSS
114
VSS
110
VSS
104
VSS
107
VSS
101
VSS
98
VSS
95
VSS
92
VSS
DIMM33B
VCC VCC VCC VCC VCC VCC VCC VCC
VTT VTT VTT VTT
VDDSPD
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
FBDIMM240
133 132 130 129 13 12 10 9
237 135 117 15
238
89 88 85 84 81 78 75 72 69 68 65 62 59 56 53 50 47 46 43 42 39 36 33 30 147 144 141 138 134 131 128 124 27 24 21 18 14 11 8 4
F_VTT
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
FBD Channel 2 DIMM 2
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
P3V3
C3237
0.1u
Share 0.1uF Cap. Between VDDSPD Pins Of DIMM0 & DIMM1
31 90
1
of
Rev
0A
Page 32
5
4
3
2
1
FBD Channel 3 DIMM 0
DIMM41A
FBD_CH3_NB_P[13..0]18
D D
C C
B B
A A
FBD_CH3_NB_N[13..0]18
FBD_CH3_SB_P[9..0]18 FBD_CH3_SB_N[9..0]18
5
FBD_CH3_NB_P[13..0] FBD_CH3_NB_N[13..0] FBD_CH3_SB_P[9..0] FBD_CH3_SB_N[9..0]
CK_H_FBD959
CK_H_FBD9_N59
FBD_BR1_RST#29,30,31,33,34,35
FBD_CH3_NB_P13 FBD_CH3_NB_P12 FBD_CH3_NB_P11 FBD_CH3_NB_P10 FBD_CH3_NB_P9 FBD_CH3_NB_P8 FBD_CH3_NB_P7 FBD_CH3_NB_P6 FBD_CH3_NB_P5 FBD_CH3_NB_P4 FBD_CH3_NB_P3 FBD_CH3_NB_P2 FBD_CH3_NB_P1 FBD_CH3_NB_P0
FBD_CH3_NB_N13 FBD_CH3_NB_N12 FBD_CH3_NB_N11 FBD_CH3_NB_N10 FBD_CH3_NB_N9 FBD_CH3_NB_N8 FBD_CH3_NB_N7 FBD_CH3_NB_N6 FBD_CH3_NB_N5 FBD_CH3_NB_N4 FBD_CH3_NB_N3 FBD_CH3_NB_N2 FBD_CH3_NB_N1 FBD_CH3_NB_N0
FBD_CH3_SB_P9 FBD_CH3_SB_P8 FBD_CH3_SB_P7 FBD_CH3_SB_P6 FBD_CH3_SB_P5 FBD_CH3_SB_P4 FBD_CH3_SB_P3 FBD_CH3_SB_P2 FBD_CH3_SB_P1 FBD_CH3_SB_P0
FBD_CH3_SB_N9 FBD_CH3_SB_N8 FBD_CH3_SB_N7 FBD_CH3_SB_N6 FBD_CH3_SB_N5 FBD_CH3_SB_N4 FBD_CH3_SB_N3 FBD_CH3_SB_N2 FBD_CH3_SB_N1 FBD_CH3_SB_N0
CK_H_FBD9 CK_H_FBD9_N
FBD_BR1_RST#
4
102
103 100
228 229
136
207 206 165 164
40 48 66 63 60 57 54 51 37 34 31 28 25 22
41 49 67 64 61 58 55 52 38 35 32 29 26 23
90 99
96 93 82 79 76 73 70
91
97 94 83 80 77 74 71
16
17
87 86 45 44
FBDIMM-1/2
PNP13 PNP12 PNP11 PNP10 PNP9 PNP8
Primarily Northbound
PNP7 PNP6 PNP5 PNP4 PNP3 PNP2 PNP1 PNP0
PNN13 PNN12 PNN11 PNN10 PNN9 PNN8 PNN7 PNN6 PNN5 PNN4 PNN3 PNN2 PNN1 PNN0
PSP9 PSP8
Primarily Southbound
PSP7 PSP6 PSP5 PSP4 PSP3 PSP2 PSP1 PSP0
PSN9 PSN8 PSN7 PSN6 PSN5 PSN4 PSN3 PSN2 PSN1 PSN0
SCKP SCKN
VID1 VID0
RESET_N
RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK
SNP13 SNP12 SNP11 SNP10
SNP9 SNP8 SNP7 SNP6 SNP5 SNP4 SNP3 SNP2 SNP1 SNP0
SNN13 SNN12 SNN11 SNN10
SNN9 SNN8 SNN7
Secondary NorthboundSecondary Southbound
SNN6 SNN5 SNN4 SNN3 SNN2 SNN1 SNN0
SSP9 SSP8 SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0
SSN9 SSN8 SSN7 SSN6 SSN5 SSN4 SSN3 SSN2 SSN1 SSN0
SCL SDA
SA2 SA1 SA0
M_TEST
RFU RFU RFU RFU RFU RFU RFU RFU
FBDIMM240
168 186 183 180 177 174 171 157 154 151 148 145 142
161 169 187 184 181 178 175 172 158 155 152 149 146 143
210 222 219 216 213 202 199 196 193 190
211 223 220 217 214 203 200 197 194 191
120 119
118 240 239
137 20 19 106 105 139 140 225 226
CH3_NB_P12 CH3_NB_P11 CH3_NB_P10 CH3_NB_P9 CH3_NB_P8 CH3_NB_P7 CH3_NB_P6 CH3_NB_P5 CH3_NB_P4 CH3_NB_P3 CH3_NB_P2 CH3_NB_P1 CH3_NB_P0
CH3_NB_N13 CH3_NB_N12 CH3_NB_N11 CH3_NB_N10 CH3_NB_N9 CH3_NB_N8 CH3_NB_N7 CH3_NB_N6 CH3_NB_N5 CH3_NB_N4 CH3_NB_N3 CH3_NB_N2 CH3_NB_N1 CH3_NB_N0
CH3_SB_P9 CH3_SB_P8 CH3_SB_P7 CH3_SB_P6 CH3_SB_P5 CH3_SB_P4 CH3_SB_P3 CH3_SB_P2 CH3_SB_P1 CH3_SB_P0
CH3_SB_N9 CH3_SB_N8 CH3_SB_N7 CH3_SB_N6 CH3_SB_N5 CH3_SB_N4 CH3_SB_N3 CH3_SB_N2 CH3_SB_N1 CH3_SB_N0
FBD3SCL FBD3SDA
FBD30SA2 FBD30SA1 FBD30SA0
3
CH3_NB_P13
160
CH3_NB_P[13..0] CH3_NB_N[13..0] CH3_SB_P[9..0] CH3_SB_N[9..0]
FBD30SA2 FBD30SA1 FBD30SA0
CH3_NB_P[13..0] 33 CH3_NB_N[13..0] 33 CH3_SB_P[9..0] 33 CH3_SB_N[9..0] 33
R1141 1K
DIMM SPD SMBus Address 0XA0 AMB SMBus Address LAI SPD SMBus Address LAI IOX SMBus Address
FBD3SCL 17,18,33,34 FBD3SDA 17,18,33,34
R1142 1K
R1143 1K
0XB0 0X20 0X70
2
P1V8 P1V5
FBDIMM-2/2
231
VDD
232
VDD
233
VDD
235
VDD
236
VDD
116
VDD
115
VDD
113
VDD
112
VDD
111
VDD
109
VDD
108
VDD
127
VDD
126
VDD
125
VDD
123
VDD
122
VDD
121
VDD
7
VDD
6
VDD
5
VDD
3
VDD
2
VDD
1
VDD
234
VSS
230
VSS
227
VSS
224
VSS
221
VSS
218
VSS
215
VSS
212
VSS
209
VSS
208
VSS
205
VSS
204
VSS
201
VSS
198
VSS
195
VSS
192
VSS
189
VSS
188
VSS
185
VSS
182
VSS
179
VSS
176
VSS
173
VSS
170
VSS
167
VSS
166
VSS
163
VSS
162
VSS
159
VSS
156
VSS
153
VSS
150
VSS
114
VSS
110
VSS
104
VSS
107
VSS
101
VSS
98
VSS
95
VSS
92
VSS
DIMM41B
VCC VCC VCC VCC VCC VCC VCC VCC
VTT VTT VTT VTT
VDDSPD
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
FBDIMM240
133 132 130 129 13 12 10 9
237 135 117 15
238
89 88 85 84 81 78 75 72 69 68 65 62 59 56 53 50 47 46 43 42 39 36 33 30 147 144 141 138 134 131 128 124 27 24 21 18 14 11 8 4
F_VTT
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
FBD Channel 3 DIMM 0
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
P3V3
C3238
0.1u
Share 0.1uF Cap. Between VDDSPD Pins Of DIMM0 & DIMM1
32 90
1
of
Rev
0A
Page 33
5
4
3
2
1
FBD Channel 3 DIMM 1
DIMM42A
CH3_NB_P[13..0]32
D D
C C
B B
A A
CH3_NB_N[13..0]32
CH3_SB_P[9..0]32 CH3_SB_N[9..0]32
5
CH3_NB_P[13..0] CH3_NB_N[13..0] CH3_SB_P[9..0] CH3_SB_N[9..0]
CK_H_FBD1059
CK_H_FBD10_N59
FBD_BR1_RST#29,30,31,32,34,35
CH3_NB_P13 CH3_NB_P12 CH3_NB_P11 CH3_NB_P10 CH3_NB_P9 CH3_NB_P8 CH3_NB_P7 CH3_NB_P6 CH3_NB_P5 CH3_NB_P4 CH3_NB_P3 CH3_NB_P2 CH3_NB_P1 CH3_NB_P0
CH3_NB_N13 CH3_NB_N12 CH3_NB_N11 CH3_NB_N10 CH3_NB_N9 CH3_NB_N8 CH3_NB_N7 CH3_NB_N6 CH3_NB_N5 CH3_NB_N4 CH3_NB_N3 CH3_NB_N2 CH3_NB_N1 CH3_NB_N0
CH3_SB_P9 CH3_SB_P8 CH3_SB_P7 CH3_SB_P6 CH3_SB_P5 CH3_SB_P4 CH3_SB_P3 CH3_SB_P2 CH3_SB_P1 CH3_SB_P0
CH3_SB_N9 CH3_SB_N8 CH3_SB_N7 CH3_SB_N6 CH3_SB_N5 CH3_SB_N4 CH3_SB_N3 CH3_SB_N2 CH3_SB_N1 CH3_SB_N0
CK_H_FBD10 CK_H_FBD10_N
FBD_BR1_RST#
4
102
103 100
228 229
136
207 206 165 164
40 48 66 63 60 57 54 51 37 34 31 28 25 22
41 49 67 64 61 58 55 52 38 35 32 29 26 23
90 99
96 93 82 79 76 73 70
91
97 94 83 80 77 74 71
16
17
87 86 45 44
FBDIMM-1/2
PNP13 PNP12 PNP11 PNP10 PNP9 PNP8
Primarily Northbound
PNP7 PNP6 PNP5 PNP4 PNP3 PNP2 PNP1 PNP0
PNN13 PNN12 PNN11 PNN10 PNN9 PNN8 PNN7 PNN6 PNN5 PNN4 PNN3 PNN2 PNN1 PNN0
PSP9 PSP8
Primarily Southbound
PSP7 PSP6 PSP5 PSP4 PSP3 PSP2 PSP1 PSP0
PSN9 PSN8 PSN7 PSN6 PSN5 PSN4 PSN3 PSN2 PSN1 PSN0
SCKP SCKN
VID1 VID0
RESET_N
RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK
SNP13 SNP12 SNP11 SNP10
SNP9 SNP8 SNP7 SNP6 SNP5 SNP4 SNP3 SNP2 SNP1 SNP0
SNN13 SNN12 SNN11 SNN10
SNN9 SNN8 SNN7
Secondary NorthboundSecondary Southbound
SNN6 SNN5 SNN4 SNN3 SNN2 SNN1 SNN0
SSP9 SSP8 SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0
SSN9 SSN8 SSN7 SSN6 SSN5 SSN4 SSN3 SSN2 SSN1 SSN0
SCL SDA
SA2 SA1 SA0
M_TEST
RFU RFU RFU RFU RFU RFU RFU RFU
FBDIMM240
168 186 183 180 177 174 171 157 154 151 148 145 142
161 169 187 184 181 178 175 172 158 155 152 149 146 143
210 222 219 216 213 202 199 196 193 190
211 223 220 217 214 203 200 197 194 191
120 119
118 240 239
137 20 19 106 105 139 140 225 226
R_CH3_NB_P12 R_CH3_NB_P11 R_CH3_NB_P10 R_CH3_NB_P9 R_CH3_NB_P8 R_CH3_NB_P7 R_CH3_NB_P6 R_CH3_NB_P5 R_CH3_NB_P4 R_CH3_NB_P3 R_CH3_NB_P2 R_CH3_NB_P1 R_CH3_NB_P0
R_CH3_NB_N13 R_CH3_NB_N12 R_CH3_NB_N11 R_CH3_NB_N10 R_CH3_NB_N9 R_CH3_NB_N8 R_CH3_NB_N7 R_CH3_NB_N6 R_CH3_NB_N5 R_CH3_NB_N4 R_CH3_NB_N3 R_CH3_NB_N2 R_CH3_NB_N1 R_CH3_NB_N0
R_CH3_SB_P9 R_CH3_SB_P8 R_CH3_SB_P7 R_CH3_SB_P6 R_CH3_SB_P5 R_CH3_SB_P4 R_CH3_SB_P3 R_CH3_SB_P2 R_CH3_SB_P1 R_CH3_SB_P0
R_CH3_SB_N9 R_CH3_SB_N8 R_CH3_SB_N7 R_CH3_SB_N6 R_CH3_SB_N5 R_CH3_SB_N4 R_CH3_SB_N3 R_CH3_SB_N2 R_CH3_SB_N1 R_CH3_SB_N0
FBD3SCL FBD3SDA
FBD31SA2 FBD31SA1 FBD31SA0
3
R_CH3_NB_P13
160
R_CH3_NB_P[13..0] R_CH3_NB_N[13..0] R_CH3_SB_P[9..0] R_CH3_SB_N[9..0]
FBD31SA2 FBD31SA1 FBD31SA0
R_CH3_NB_P[13..0] 34 R_CH3_NB_N[13..0] 34 R_CH3_SB_P[9..0] 34 R_CH3_SB_N[9..0] 34
P3V3
R1139 1K
DIMM SPD SMBus Address 0XA2 AMB SMBus Address LAI SPD SMBus Address LAI IOX SMBus Address
FBD3SCL 17,18,32,34 FBD3SDA 17,18,32,34
R1144 1K
R1145 1K
0XB2 0X22 0X72
2
P1V8 P1V5
FBDIMM-2/2
231
VDD
232
VDD
233
VDD
235
VDD
236
VDD
116
VDD
115
VDD
113
VDD
112
VDD
111
VDD
109
VDD
108
VDD
127
VDD
126
VDD
125
VDD
123
VDD
122
VDD
121
VDD
7
VDD
6
VDD
5
VDD
3
VDD
2
VDD
1
VDD
234
VSS
230
VSS
227
VSS
224
VSS
221
VSS
218
VSS
215
VSS
212
VSS
209
VSS
208
VSS
205
VSS
204
VSS
201
VSS
198
VSS
195
VSS
192
VSS
189
VSS
188
VSS
185
VSS
182
VSS
179
VSS
176
VSS
173
VSS
170
VSS
167
VSS
166
VSS
163
VSS
162
VSS
159
VSS
156
VSS
153
VSS
150
VSS
114
VSS
110
VSS
104
VSS
107
VSS
101
VSS
98
VSS
95
VSS
92
VSS
DIMM42B
VCC VCC VCC VCC VCC VCC VCC VCC
VTT VTT VTT VTT
VDDSPD
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
FBDIMM240
133 132 130 129 13 12 10 9
237 135 117 15
238
89 88 85 84 81 78 75 72 69 68 65 62 59 56 53 50 47 46 43 42 39 36 33 30 147 144 141 138 134 131 128 124 27 24 21 18 14 11 8 4
F_VTT
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
FBD Channel 3 DIMM 1
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
P3V3
C3239
0.1u
Share 0.1uF Cap. Between VDDSPD Pins Of DIMM0 & DIMM1
33 90
1
of
Rev
0A
Page 34
5
4
3
2
1
FBD Channel 3 DIMM 2
DIMM43A
R_CH3_NB_P[13..0]33
D D
C C
B B
A A
R_CH3_NB_N[13..0]33
R_CH3_SB_P[9..0]33 R_CH3_SB_N[9..0]33
5
R_CH3_NB_P[13..0] R_CH3_NB_N[13..0] R_CH3_SB_P[9..0] R_CH3_SB_N[9..0]
CK_H_FBD1159
CK_H_FBD11_N59
FBD_BR1_RST#29,30,31,32,33,35
R_CH3_NB_P13 R_CH3_NB_P12 R_CH3_NB_P11 R_CH3_NB_P10 R_CH3_NB_P9 R_CH3_NB_P8 R_CH3_NB_P7 R_CH3_NB_P6 R_CH3_NB_P5 R_CH3_NB_P4 R_CH3_NB_P3 R_CH3_NB_P2 R_CH3_NB_P1 R_CH3_NB_P0
R_CH3_NB_N13 R_CH3_NB_N12 R_CH3_NB_N11 R_CH3_NB_N10 R_CH3_NB_N9 R_CH3_NB_N8 R_CH3_NB_N7 R_CH3_NB_N6 R_CH3_NB_N5 R_CH3_NB_N4 R_CH3_NB_N3 R_CH3_NB_N2 R_CH3_NB_N1 R_CH3_NB_N0
R_CH3_SB_P9 R_CH3_SB_P8 R_CH3_SB_P7 R_CH3_SB_P6 R_CH3_SB_P5 R_CH3_SB_P4 R_CH3_SB_P3 R_CH3_SB_P2 R_CH3_SB_P1 R_CH3_SB_P0
R_CH3_SB_N9 R_CH3_SB_N8 R_CH3_SB_N7 R_CH3_SB_N6 R_CH3_SB_N5 R_CH3_SB_N4 R_CH3_SB_N3 R_CH3_SB_N2 R_CH3_SB_N1 R_CH3_SB_N0
CK_H_FBD11 CK_H_FBD11_N
FBD_BR1_RST#
4
102
103 100
228 229
136
207 206 165 164
40 48 66 63 60 57 54 51 37 34 31 28 25 22
41 49 67 64 61 58 55 52 38 35 32 29 26 23
90 99
96 93 82 79 76 73 70
91
97 94 83 80 77 74 71
16
17
87 86 45 44
FBDIMM-1/2
PNP13 PNP12 PNP11 PNP10 PNP9 PNP8
Primarily Northbound
PNP7 PNP6 PNP5 PNP4 PNP3 PNP2 PNP1 PNP0
PNN13 PNN12 PNN11 PNN10 PNN9 PNN8 PNN7 PNN6 PNN5 PNN4 PNN3 PNN2 PNN1 PNN0
PSP9 PSP8
Primarily Southbound
PSP7 PSP6 PSP5 PSP4 PSP3 PSP2 PSP1 PSP0
PSN9 PSN8 PSN7 PSN6 PSN5 PSN4 PSN3 PSN2 PSN1 PSN0
SCKP SCKN
VID1 VID0
RESET_N
RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK RFUCLK
160
SNP13
168
SNP12
186
SNP11
183
SNP10
180
SNP9
177
SNP8
174
SNP7
171
SNP6
157
SNP5
154
SNP4
151
SNP3
148
SNP2
145
SNP1
142
SNP0
161
SNN13
169
SNN12
187
SNN11
184
SNN10
181
SNN9
178
SNN8
175
SNN7
172
Secondary NorthboundSecondary Southbound
SNN6
158
SNN5
155
SNN4
152
SNN3
149
SNN2
146
SNN1
143
SNN0
210
SSP9
222
SSP8
219
SSP7
216
SSP6
213
SSP5
202
SSP4
199
SSP3
196
SSP2
193
SSP1
190
SSP0
211
SSN9
223
SSN8
220
SSN7
217
SSN6
214
SSN5
203
SSN4
200
SSN3
197
SSN2
194
SSN1
191
SSN0
FBD3SCL
120
SCL SDA
SA2 SA1 SA0
M_TEST
RFU RFU RFU RFU RFU RFU RFU RFU
FBDIMM240
119 118
240 239
137 20 19 106 105 139 140 225 226
FBD3SDA FBD32SA2
FBD32SA1 FBD32SA0
3
P3V3
R1140 1K
FBD32SA2 FBD32SA1 FBD32SA0
R1146 1K
R1147 1K
DIMM SPD SMBus Address 0XA4 AMB SMBus Address LAI SPD SMBus Address LAI IOX SMBus Address
FBD3SCL 17,18,32,33 FBD3SDA 17,18,32,33
0XB4 0X24 0X74
2
P1V8 P1V5
FBDIMM-2/2
231
VDD
232
VDD
233
VDD
235
VDD
236
VDD
116
VDD
115
VDD
113
VDD
112
VDD
111
VDD
109
VDD
108
VDD
127
VDD
126
VDD
125
VDD
123
VDD
122
VDD
121
VDD
7
VDD
6
VDD
5
VDD
3
VDD
2
VDD
1
VDD
234
VSS
230
VSS
227
VSS
224
VSS
221
VSS
218
VSS
215
VSS
212
VSS
209
VSS
208
VSS
205
VSS
204
VSS
201
VSS
198
VSS
195
VSS
192
VSS
189
VSS
188
VSS
185
VSS
182
VSS
179
VSS
176
VSS
173
VSS
170
VSS
167
VSS
166
VSS
163
VSS
162
VSS
159
VSS
156
VSS
153
VSS
150
VSS
114
VSS
110
VSS
104
VSS
107
VSS
101
VSS
98
VSS
95
VSS
92
VSS
DIMM43B
VCC VCC VCC VCC VCC VCC VCC VCC
VTT VTT VTT VTT
VDDSPD
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
FBDIMM240
133 132 130 129 13 12 10 9
237 135 117 15
238
89 88 85 84 81 78 75 72 69 68 65 62 59 56 53 50 47 46 43 42 39 36 33 30 147 144 141 138 134 131 128 124 27 24 21 18 14 11 8 4
F_VTT
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
FBD Channel 3 DIMM 2
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
P3V3
C3240
0.1u
Share 0.1uF Cap. Between VDDSPD Pins Of DIMM0 & DIMM1
34 90
1
of
Rev
0A
Page 35
5
FBD Reset and Decoupling
4
3
2
1
D D
SYS_PWRGD_3_3V20,37,40,50,63,77
C C
B B
FBD Branch 0 Reset CKT
R1184
1K
R1180
B
SYS_PWRGD_3_3V
FBD_RESET40
FBD_RESET
FBD Branch 1 Reset CKT
SYS_PWRGD_3_3V
R1157
4.7K
P3V3
4.7K
P3V3
R1183
4.7K
Q100 MMBT3904
E C
P1V5
P3V3
R1181
4.7K
Q99
B
MMBT3904
Q97
B
MMBT3904
E C
Q98
B
MMBT3904
E C
P3V3
R1158
4.7K
Q93
B
MMBT3904
E C
E C
Q95
B
MMBT3904
E C
P1V5
R1182 560
R3394 100K
R1159 560
R3395 100K
FBD_BR0_RST# 23,24,25,26,27,28
FBD_BR1_RST# 29,30,31,32,33,34
F_VTT
F_VTT
F_VTT
F_VTT
C895 1u
C913 1u
C897 1u
C911 1u
C898 1u
C896 1u
C900 1u
C914 1u
FBD VTT Decoupling Caps.
Channel 0
C907
C901 1u
C899 1u
C903 1u
C915 1u
C904 1u
C902 1u
C906 1u
C918 1u
C910
1u
1u
Channel 1
C905
C908
1u
1u
Channel 2
C909
C912
1u
1u
Channel 3
C921
C922
1u
1u
C916
4.7u-1206
C3159
4.7u-1206
C3165
4.7u-1206
C3171
4.7u-1206
C919
4.7u-1206
C3160
4.7u-1206
C3166
4.7u-1206
C3172
4.7u-1206
C917
4.7u-1206
C3161
4.7u-1206
C3167
4.7u-1206
C3173
4.7u-1206
C920
4.7u-1206
C3162
4.7u-1206
C3168
4.7u-1206
C3174
4.7u-1206
C3157
4.7u-1206
C3163
4.7u-1206
C3169
4.7u-1206
C3175
4.7u-1206
C3158
4.7u-1206
C3164
4.7u-1206
C3170
4.7u-1206
C3176
4.7u-1206
R1160
4.7K Q94
B
FBD_RESET
A A
5
R1161
1K
Q96
B
MMBT3904
E C
MMBT3904
E C
4
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
3
2
http://www.msi.com.tw
FBD Reset and Decoupling
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
35 90
Rev
0A
of
Micro Star Restricted Secret
Page 36
5
ESB2 PCI Express
4
3
2
1
D D
MCH_EXP0_TXN319 MCH_EXP0_TXN219 MCH_EXP0_TXN119 MCH_EXP0_TXN019
MCH_EXP0_TXP319 MCH_EXP0_TXP219 MCH_EXP0_TXP119 MCH_EXP0_TXP019 MCH_EXP0_RXP0 19
ESB_EXP0_RXN053
ESB_EXP0_RXP053
ESB_EXP1_RXN350
C C
B B
ESB_EXP1_RXN250 ESB_EXP1_RXN150 ESB_EXP1_RXN050
ESB_EXP1_RXP350 ESB_EXP1_RXP250 ESB_EXP1_RXP150 ESB_EXP1_RXP050
ESB_EXP2_RXN350 ESB_EXP2_RXN250 ESB_EXP2_RXN150 ESB_EXP2_RXN050
ESB_EXP2_RXP350 ESB_EXP2_RXP250 ESB_EXP2_RXP150 ESB_EXP2_RXP050
MCH_EXP3_TXN319 MCH_EXP3_TXN219 MCH_EXP3_TXN119 MCH_EXP3_TXN019 MCH_EXP2_TXN319 MCH_EXP2_TXN219 MCH_EXP2_TXN119 MCH_EXP2_TXN019
MCH_EXP3_TXP319 MCH_EXP3_TXP219 MCH_EXP3_TXP119 MCH_EXP3_TXP019 MCH_EXP2_TXP319 MCH_EXP2_TXP219 MCH_EXP2_TXP119 MCH_EXP2_TXP019
ESB2_100CLK_N58 ESB2_100CLK_P58 ESI_100CLK_N 58
P1V5 P3V3
MCH_EXP0_TXN3 MCH_EXP0_TXN2 MCH_EXP0_TXN1 MCH_EXP0_TXN0
MCH_EXP0_TXP3 MCH_EXP0_TXP2 MCH_EXP0_TXP1 MCH_EXP0_TXP0
ESB_EXP0_RXN0
ESB_EXP0_RXP0 ESB_EXP1_RXN3
ESB_EXP1_RXN2 ESB_EXP1_RXN1 ESB_EXP1_RXN0
ESB_EXP1_RXP3 ESB_EXP1_RXP2 ESB_EXP1_RXP1 ESB_EXP1_RXP0
ESB_EXP2_RXN3 ESB_EXP2_RXN2 ESB_EXP2_RXN1 ESB_EXP2_RXN0
ESB_EXP2_RXP3 ESB_EXP2_RXP2 ESB_EXP2_RXP1 ESB_EXP2_RXP0
MCH_EXP3_TXN3 MCH_EXP3_TXN2 MCH_EXP3_TXN1 MCH_EXP3_TXN0 MCH_EXP2_TXN3 MCH_EXP2_TXN2 MCH_EXP2_TXN1 MCH_EXP2_TXN0
MCH_EXP3_TXP3 MCH_EXP3_TXP2 MCH_EXP3_TXP1 MCH_EXP3_TXP0 MCH_EXP2_TXP3 MCH_EXP2_TXP2 MCH_EXP2_TXP1 MCH_EXP2_TXP0
ESB2_100CLK_N ESB2_100CLK_P
R563 24.9RST
R3194 5.1K-0402 R3196 5.1K-0402 R3197 5.1K-0402
Y11
Y10
AA10
AC8 AB6 AA4
AA9 AC7 AB5 AA3
U10
U11
V10
T11
W11
AJ17 AK18 AG22
J10
H8 G6 F4
J9 H7 G5 F3
M4
K6
J3
L8
M3
K5
J4
L7
W3 W5
Y7
W2 W6
Y8
P8 N6 N3 R4 U1 T5 T8
P7 N5 N2 R3 U2 T6 T9
V9
ESIRXN3 ESIRXN2 ESIRXN1 ESIRXN0
ESIRXP3 ESIRXP2 ESIRXP1 ESIRXP0
PE0RN3 PE0RN2 PE0RN1 PE0RN0
PE0RP3 PE0RP2 PE0RP1 PE0RP0
PE1RN3 PE1RN2 PE1RN1 PE1RN0
PE1RP3 PE1RP2 PE1RP1 PE1RP0
PE2RN3 PE2RN2 PE2RN1 PE2RN0
PE2RP3 PE2RP2 PE2RP1 PE2RP0
PE4RN7 PE4RN6 PE4RN5 PE4RN4 PE4RN3 PE4RN2 PE4RN1 PE4RN0
PE4RP7 PE4RP6 PE4RP5 PE4RP4 PE4RP3 PE4RP2 PE4RP1 PE4RP0
PECLKN PECLKP PEICOMPI PERCOMPO HPCLK HPDTA EXTINTR_N
ESB2 2/10
PCI-E
U39B
ESITXN3 ESITXN2 ESITXN1 ESITXN0
ESITXP3 ESITXP2 ESITXP1 ESITXP0
PE0TN3 PE0TN2 PE0TN1 PE0TN0
PE0TP3 PE0TP2 PE0TP1 PE0TP0
PE1TN3 PE1TN2 PE1TN1 PE1TN0
PE1TP3 PE1TP2 PE1TP1 PE1TP0
PE2TN3 PE2TN2 PE2TN1 PE2TN0
PE2TP3 PE2TP2 PE2TP1 PE2TP0
PE4TN7 PE4TN6 PE4TN5 PE4TN4 PE4TN3 PE4TN2 PE4TN1 PE4TN0
PE4TP7 PE4TP6 PE4TP5 PE4TP4 PE4TP3 PE4TP2 PE4TP1 PE4TP0
ESICLK100N
ESICLK100P
ESIDCAC
ESICOMPI
ESIRCOMPO
G9 J7 H5 G3
G8 J6 H4 G2
L5 K2 H1 M7
L4 K3 H2 M6
Y2 Y4 V3 W8
Y1 Y5 V4 W9
AB9 AA7 AC5 AB3
AB8 AA6 AC4 AB2
N9 R7 P5 P2 T2 U4 U7 R9
N8 R6 P4 P1 T3 U5 U8 R10
L1 M1
D27 L2 J1
ESB_EXPESI_TXN3 ESB_EXPESI_TXN2 ESB_EXPESI_TXN1 ESB_EXPESI_TXN0
ESB_EXPESI_TXP3 ESB_EXPESI_TXP2 ESB_EXPESI_TXP1 ESB_EXPESI_TXP0
ESB_E1_TXN3 ESB_E1_TXN2 ESB_E1_TXN1 ESB_E1_TXN0
ESB_E1_TXP3 ESB_E1_TXP2 ESB_E1_TXP1 ESB_E1_TXP0
ESB_E2_TXN2 ESB_E2_TXN1 ESB_E2_TXN0
ESB_E2_TXP2 ESB_E2_TXP1 ESB_E2_TXP0
ESB_EXP4_TXN7 ESB_EXP4_TXN6 ESB_EXP4_TXN5 ESB_EXP4_TXN4 ESB_EXP4_TXN3 ESB_EXP4_TXN2 ESB_EXP4_TXN1 ESB_EXP4_TXN0
ESB_EXP4_TXP7 ESB_EXP4_TXP6 ESB_EXP4_TXP5 ESB_EXP4_TXP4 ESB_EXP4_TXP3 ESB_EXP4_TXP2 ESB_EXP4_TXP1 ESB_EXP4_TXP0
ESI_100CLK_N
ESI_100CLK_P
R564 10K R565 24.9RST
C927 0.1u-0402 C928 0.1u-0402 C929 0.1u-0402 C930 0.1u-0402
C923 0.1u-0402 C924 0.1u-0402 C925 0.1u-0402 C926 0.1u-0402
C1469 0.1u
C1468 0.1u C482 0.1u
C480 0.1u C478 0.1u C476 0.1u
C481 0.1u C479 0.1u C477 0.1u C475 0.1u
C3113 0.1u C3111 0.1u C3109 0.1u C3107 0.1u
C3112 0.1u C3110 0.1u C3108 0.1u C3106 0.1u
C943 0.1u-0402 C944 0.1u-0402 C945 0.1u-0402 C946 0.1u-0402 C935 0.1u-0402 C936 0.1u-0402 C937 0.1u-0402 C938 0.1u-0402
C939 0.1u-0402 C940 0.1u-0402 C941 0.1u-0402 C942 0.1u-0402 C931 0.1u-0402 C932 0.1u-0402 C933 0.1u-0402 C934 0.1u-0402
ESI_100CLK_P 58
P1V5 P1V5
MCH_EXP0_RXN3 MCH_EXP0_RXN2 MCH_EXP0_RXN1 MCH_EXP0_RXN0
MCH_EXP0_RXP3 MCH_EXP0_RXP2 MCH_EXP0_RXP1 MCH_EXP0_RXP0
ESB_EXP0_TXN0ESB_E0_TXN0
ESB_EXP0_TXP0ESB_E0_TXP0 ESB_EXP1_TXN3
ESB_EXP1_TXN2 ESB_EXP1_TXN1 ESB_EXP1_TXN0
ESB_EXP1_TXP3 ESB_EXP1_TXP2 ESB_EXP1_TXP1 ESB_EXP1_TXP0
ESB_EXP2_TXN3ESB_E2_TXN3 ESB_EXP2_TXN2 ESB_EXP2_TXN1 ESB_EXP2_TXN0
ESB_EXP2_TXP3ESB_E2_TXP3 ESB_EXP2_TXP2 ESB_EXP2_TXP1 ESB_EXP2_TXP0
MCH_EXP3_RXN3 MCH_EXP3_RXN2 MCH_EXP3_RXN1 MCH_EXP3_RXN0 MCH_EXP2_RXN3 MCH_EXP2_RXN2 MCH_EXP2_RXN1 MCH_EXP2_RXN0
MCH_EXP3_RXP3 MCH_EXP3_RXP2 MCH_EXP3_RXP1 MCH_EXP3_RXP0 MCH_EXP2_RXP3 MCH_EXP2_RXP2 MCH_EXP2_RXP1 MCH_EXP2_RXP0
MCH_EXP0_RXN3 19 MCH_EXP0_RXN2 19 MCH_EXP0_RXN1 19 MCH_EXP0_RXN0 19
MCH_EXP0_RXP3 19 MCH_EXP0_RXP2 19 MCH_EXP0_RXP1 19
ESB_EXP0_TXN0 53
ESB_EXP0_TXP0 53 ESB_EXP1_TXN3 50
ESB_EXP1_TXN2 50 ESB_EXP1_TXN1 50 ESB_EXP1_TXN0 50
ESB_EXP1_TXP3 50 ESB_EXP1_TXP2 50 ESB_EXP1_TXP1 50 ESB_EXP1_TXP0 50
ESB_EXP2_TXN3 50 ESB_EXP2_TXN2 50 ESB_EXP2_TXN1 50 ESB_EXP2_TXN0 50
ESB_EXP2_TXP3 50 ESB_EXP2_TXP2 50 ESB_EXP2_TXP1 50 ESB_EXP2_TXP0 50
MCH_EXP3_RXN3 19 MCH_EXP3_RXN2 19 MCH_EXP3_RXN1 19 MCH_EXP3_RXN0 19 MCH_EXP2_RXN3 19 MCH_EXP2_RXN2 19 MCH_EXP2_RXN1 19 MCH_EXP2_RXN0 19
MCH_EXP3_RXP3 19 MCH_EXP3_RXP2 19 MCH_EXP3_RXP1 19 MCH_EXP3_RXP0 19 MCH_EXP2_RXP3 19 MCH_EXP2_RXP2 19 MCH_EXP2_RXP1 19 MCH_EXP2_RXP0 19
A A
5
4
ESB2
ESIDCAC
1
AC Mode
0
DC Mode (Not Support)
3
2
Title Document Number
Micro Star Restricted Secret
ESB2 PCI Express
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
36 90
1
Rev
0A
of
Page 37
5
ESB2 PCI-X Interface
D D
P3V3
R3396 X_1K R595 X_1K
R3397 X_1K R3398 X_1K R3399 X_1K R3400 1K
HPX_SLOT3
C C
B B
1 0
P3V3
NPECFG SPECFG
NPECFG
R588
10K-0402
R596
10K-0402
R597
1K-0402
R598
1K-0402
R1665 1K-0402
North PCI-E connections
1
A A
0
SPECFG
South PCI-E connections 1 0
HPX_SLOT0 HPX_SLOT1
HPX_SLOT0 HPX_SLOT1 HPX_SLOT2 HPX_SLOT3
Hot-Plug Mode
Enabled Disabled
HPX_SIC
HPX_SID
PASTRAP0
HPX_SOC
R1663 X_4.7K-0402 R1662 X_4.7K-0402
R1664
4.7K-0402
Two X4 ports One X8 port
Two X4 ports One X8 port
5
P3V3
R3188 100RST
4
PXAD63 PXAD62 PXAD61 PXAD60 PXAD59 PXAD58 PXAD57 PXAD56 PXAD55 PXAD54 PXAD53 PXAD52 PXAD51 PXAD50 PXAD49 PXAD48 PXAD47 PXAD46 PXAD45 PXAD44 PXAD43 PXAD42 PXAD41 PXAD40 PXAD39 PXAD38 PXAD37 PXAD36 PXAD35 PXAD34 PXAD33 PXAD32 PXAD31 PXAD30 PXAD29 PXAD28 PXAD27 PXAD26 PXAD25 PXAD24 PXAD23 PXAD22 PXAD21 PXAD20 PXAD19 PXAD18 PXAD17 PXAD16 PXAD15 PXAD14 PXAD13 PXAD12 PXAD11 PXAD10 PXAD9 PXAD8 PXAD7 PXAD6 PXAD5 PXAD4 PXAD3 PXAD2 PXAD1 PXAD0
HPX_SLOT3 HPX_SLOT2 HPX_SLOT1 HPX_SLOT0 HPX_SOC
HPX_SIC HPX_SID
PCIX_RCOMP
4
PXAD[63..0]50
AJ7
PXAD63
AJ5
PXAD62
AH6
PXAD61
AH5
PXAD60
AG7
PXAD59
AF7
PXAD58
AG6
PXAD57
AF5
PXAD56
AE6
PXAD55
AE5
PXAD54
AE8
PXAD53
AD9
PXAD52
AD6
PXAD51
AD7
PXAD50
AL3
PXAD49
AL2
PXAD48
AK3
PXAD47
AK4
PXAD46
AJ4
PXAD45
AJ2
PXAD44
AH3
PXAD43
AG4
PXAD42
AH2
PXAD41
AG3
PXAD40
AF2
PXAD39
AF4
PXAD38
AE3
PXAD37
AF1
PXAD36
AE2
PXAD35
AD4
PXAD34
AD3
PXAD33
AD1
PXAD32
AJ14
PXAD31
AH14
PXAD30
AG13
PXAD29
AJ13
PXAD28
AK13
PXAD27
AH12
PXAD26
AK12
PXAD25
AJ11
PXAD24
AF11
PXAD23
AJ10
PXAD22
AG10
PXAD21
AH9
PXAD20
AF10
PXAD19
AJ8
PXAD18
AH8
PXAD17
AG9
PXAD16
AK16
PXAD15
AN16
PXAD14
AL15
PXAD13
AK15
PXAD12
AM14
PXAD11
AL14
PXAD10
AN13
PXAD9
AN12
PXAD8
AL12
PXAD7
AM11
PXAD6
AL11
PXAD5
AN10
PXAD4
AM10
PXAD3
AN9
PXAD2
AL9
PXAD1
AP8
PXAD0
AT18
HPX_SLOT3 /HXPWRLED1_N
AR23
HPX_SLOT2
AR22
HPX_SLOT1 /HXPRSNT1_1_N
AR20
HPX_SLOT0 /HXMRL_2_N
AT19
HPX_SOC /HXPCIXCAP2_2
AP17
HPX_SOD /HXCLKEN_2_N
AT22
HPX_SOL /HXBUTTON2_N
AP20
HPX_SOLR /HXATNLED2_N
AN7
HPX_PWREN_1
AP18
HPX_PRST_N/HXRST1_N
AP21
HPX_RST2_N
AT21
HPX_SIC /HXPWRLED2_N
AT16
HPX_SID /HXPCIXCAP1_2
AR19
HPX_SIL_N /HXCLKEN_1_N
AC10
RCOMP
PXAD[63..0]
ESB2 1/10
PCI-X
PXREQ_N5 /HXPRSNT1_2_N PXREQ_N4 /HXPRSNT2_2_N PXREQ_N3 /HXPRSNT2_1_N
PXIRQ_N15 /HXMRL1 PXIRQ_N14 /HXPWRFLT_1_N PXIRQ_N13 /HXPWRFLT_2_N
PXIRQ_N12 /HXM66EN_2
PXIRQ_N11 /HXM66EN_1 PXIRQ_N10 /HXPCIXCAP1_1 PXIRQ_N9 /HXPCIXCAP2_1 PXIRQ_N8 /HXBUTTON_1
PXCBE_N[7..0] PXIRQ_N[6..0]
U39A
PLTRST_IN_N
PXPME_N
PXPWROK
PX133EN
PXPCIRST_N
PXPCIXCAP
PXM66EN
PXCBE_N7 PXCBE_N6 PXCBE_N5 PXCBE_N4 PXCBE_N3 PXCBE_N2 PXCBE_N1 PXCBE_N0
PXREQ_N2 PXREQ_N1 PXREQ_N0
PXGNT_N5 /HXBUSEN_1_N PXGNT_N4 /HXBUSEN_2_N PXGNT_N3 /HXPWREN_2_N
PXGNT_N2 PXGNT_N1 PXGNT_N0
PXIRQ_N7 PXIRQ_N6 PXIRQ_N5 PXIRQ_N4 PXIRQ_N3 PXIRQ_N2 PXIRQ_N1 PXIRQ_N0
PXPCLKI PXPCLKO6 PXPCLKO5 PXPCLKO4 PXPCLKO3 PXPCLKO2 PXPCLKO1 PXPCLKO0
PXREQ64_N
PXSERR_N PXSTOP_N PXTRDY_N
PXPAR
PXPAR64
PXACK64_N
PXPERR_N
PXIRDY_N
PXDEVSEL_N
PXFRAME_N
PXPLOCK_N
PASTRAP0
SPECFG
NPECFG
HPX_ATNLED_1_N
ESB2
3
PXCBE_N[7..0] 50 PXIRQ_N[6..0] 50
PLTRST_N
AJ19
PXPME_N
AP6
SYS_PWRGD_3_3V
AG30
PX133EN
AK10
PXPCIRST_N
AP5
PXPCIXCAP
AL18
PXM66EN
AC1
PXCBE_N7
AM7
PXCBE_N6
AM5
PXCBE_N5
AK7
PXCBE_N4
AL6
PXCBE_N3
AH11
PXCBE_N2
AF8
PXCBE_N1
AM16
PXCBE_N0
AM13 AF16
AN1
PXREQ_N3
AN6
PXREQ_N2
AL5 AP2
PXREQ_N0
AN3 AP3
AG16
PXGNT_N3
AG15
PXGNT_N2
AH15 AM4
PXGNT_N0
AN4 AP11
AT12 AP12
PXIRQ#12
AR13
PXIRQ#11
AR14 AT13 AP14 AT15 AR16
PXIRQ_N6
AP15
PXIRQ_N5
AN15
PXIRQ_N4
AR17
PXIRQ_N3
AP9
PXIRQ_N2
AR10
PXIRQ_N1
AR11
PXIRQ_N0
AT10
PXPCLKO_FB
AR4
PXPCLKO_FB_R
AT6 AR7 AR8
PXPCLK3_R
AR5
PXPCLK2_R
AT4 AT7
PXPCLK0_R
AT9
PXREQ64_N
AL8
PXSERR_N
AC2
PXSTOP_N
AJ1
PXTRDY_N
AM1
PXPAR
AJ16
PXPAR64
AK6
PXACK64_N
AM8
PXPERR_N
AG1
PXIRDY_N
AM2
PXDEVSEL_N
AK1
PXFRAME_N
AM3
PXPLOCK_N
AH1
PASTRAP0
AL20
SPECFG
AM19
NPECFG
AM20 AE9
3
PLTRST_N 20,63 PXPME_N 50
SYS_PWRGD_3_3V 20,35,40,50,63,77
PXPCIXCAP 50 PXM66EN 50
TP74 TP75
PXREQ_N3 50 PXREQ_N2 50
PXREQ_N0 50
TP79 TP80
PXGNT_N3 50 PXGNT_N2 50
PXGNT_N0 50
TP84 TP85 TP86
TP87 TP88 TP89 TP90
R3401 8.2K R3402 8.2K
PXREQ64_N 50 PXSERR_N 50 PXSTOP_N 50 PXTRDY_N 50 PXPAR 50 PXPAR64 50 PXACK64_N 50 PXPERR_N 50 PXIRDY_N 50 PXDEVSEL_N 50 PXFRAME_N 50 PXPLOCK_N 50
SPECFG 50
P3V3
2
PXPCIRST_N 50
2
P3V3
R584
4.7K-0402
PXPCIXCAP
R3184 X_1K-0402
PXPCLKO_FB_R
PXPCLK0_R PXPCLK0
PXPCLK2_R PXPCLK2
PXPCLK3_R PXPCLK3
PXM66EN
PXPME_N PXIRQ_N2 PXIRQ_N4 PXIRQ_N6
PXIRQ_N5 PXIRQ_N1 PXIRQ_N0 PXIRQ_N3
R3306 8.2K-0402 R3189 5.6K-0402 R3205 5.6K-0402 R3210 5.6K-0402
R594
10
R599 330
R585
10
R586 330
R3010
10
R3011 330
R3012
10
R3013 330
P3V3
R3185
3.3K
PXPCLKO_FB
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
ESB2 PCI-X Interface
MS-9192
1
R593
5.1K
C631
C632
X_103P
103P
P3V3
78 56 34 12
Last Revision Date:
Friday, April 27, 2007
Sheet
37 90
1
RN122 8P4R-5.6K
PXPCLK0 50
PXPCLK2 50
PXPCLK3 50
of
Rev
0A
Page 38
5
ESB2 PCI and BMC
D D
C C
B B
P3V3
C947
MCH_ERR_N020
A A
MCH_ERR_N0 MCH_ERR_N0_RC
5
R3445
1u
0
4
G32
F33
F34 H32 G33
J31 J30
H34
L32
L31 R34 M30 M31 U35 R30
T30
K36
J34 K32 K33
M36
L34
N35 N36
L29
M34 M33 N32 N33 R36
T35 T36
J33
N30
L35 K29
STOP_N PERR_N SERR_N FRAME_N
4
PLOCK_N ESB2_PCLK PE_WAKE#
TRDY_N IRDY_N PME_N DEVSEL_N ESB_PLTRST#
MCH_ERR_N1 REQ_N4 REQ_N3 REQ_N2 REQ_N1 REQ_N0
TP96
ESB2_PCLK58
TP97
PE_WAKE#40,50,51
PME_N50
ESB_PLTRST#63
MCH_ERR_N120
G35 G36
T29
H35
K35
M28 C34
E25 P28
N29
P31 F36 P32
A33
D35
K30 E35 L28 E34
H31
J36
ESB2 4/10
AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
CBE_N_3 CBE_N_2 CBE_N_1 CBE_N_0
STOP_N PERR_N SERR_N FRAME_N PLOCK_N PAR PCICLK PCIRST_N WAKE_N TRDY_N IRDY_N PME_N DEVSEL_N PLTRST_N
REQ_N6/GPI0 REQ_N5/GPI1 REQ_N4/GPI40 REQ_N3 REQ_N2 REQ_N1 REQ_N0
EBUS_ADV_N/EBUS_RAS_N
EBUS_OE_N/EBUS_CAS_N
3
U39D
EBUS_AD24 EBUS_AD23 EBUS_AD22 EBUS_AD21 EBUS_AD20 EBUS_AD19 EBUS_AD18 EBUS_AD17 EBUS_AD16 EBUS_AD15 EBUS_AD14 EBUS_AD13 EBUS_AD12 EBUS_AD11 EBUS_AD10
EBUS_AD9 EBUS_AD8 EBUS_AD7 EBUS_AD6 EBUS_AD5 EBUS_AD4 EBUS_AD3 EBUS_AD2 EBUS_AD1 EBUS_AD0
EBUS_ALAT/EBUS_CKE
EBUS_BE_0_N EBUS_BE_1_N EBUS_CE_1_N EBUS_CE_2_N
EBUS_CLK_1 EBUS_CLK_2
EBUS_FRST_N
EBUS_WE_N
GNT_N6/GPO16 GNT_N5/GPO17
GNT_N4/GPIO48
GNT_N3 GNT_N2 GNT_N1 GNT_N0
SERIRQ
IDEIRQ
PIRQA_N
PIRQB_N PIRQC_N PIRQD_N
PIRQE_N/GPI2 PIRQF_N/GPI3 PIRQG_N/GPI4 PIRQH_N/GPI5
ESB2
3
AK28 AJ28 AK27 AJ26 AJ25 AK25 AK24 AH23 AJ23 AL23 AJ22 AK22 AN28 AM28 AN27 AL27 AL26 AM26 AM25 AN25 AN24 AL24 AM23 AN22 AM22 AT27 AR26 AT25 AT24 AP24 AP23 AR28 AP26 AT28 AP27 AR25
D36 A32 P34 P35 B31 P29 D33
J24 B11
C31 A30 B29 C30 D32 E31 F31 E32
2.5HD_SEL
1U_2U_SEL
EBUS_CE#1
ESB_PGNT#6 ESB_PGNT#5 FRB3_N
SERIRQ IRQ14
PIRQA_N PIRQB_N PIRQC_N PIRQD_N MCH_ERR_N2 RAID_SEL
2.5HD_SEL 1U_2U_SEL
LOW 2.5HD HIGH
LOW 1U HIGH
TP94 TP95
FRB3_N 54
SERIRQ 45,53 IRQ14 67
MCH_ERR_N2 20 RAID_SEL 67
2.5HD_SEL 67 1U_2U_SEL 67
3.5HD
2U
2
PIRQC_N PIRQD_N PIRQB_N PIRQA_N REQ_N3 DEVSEL_N RAID_SEL
2.5HD_SEL
ESB_PGNT#6
LOW HIGH
1U_2U_SEL MCH_ERR_N2 MCH_ERR_N1 MCH_ERR_N0
REQ_N2 REQ_N1 REQ_N0
FRAME_N TRDY_N IRDY_N
SERR_N PLOCK_N STOP_N PERR_N
REQ_N4 IRQ14 SERIRQ
PME_N
ESB_PGNT#5 external pull-up is backup provision for booting from LPC bus
ESB2 intergrated a weak internal pull-up 20K ohms.
A16 Swap Overide Enabled Disabled (default)
R663 1K R664 1K R665 1K
R3211 8.2K-0402
ESB_PGNT#5
ESB_PGNT#6
1
78 56 34 12 78 56 34 12
R3215 2.7K-0402
R3190 2.7K-0402 R3191 2.7K-0402 R3192 2.7K-0402
12 34 56 78 12 34 56 78
R3209 2.7K R339 8.2K R341 8.2K
P3V3_AUX
P3V3
R3187 X_1K-0402
R3403 X_1K-0402
P3V3
RN121 8P4R-8.2K
RN123 8P4R-2.7K
RN125 8P4R-2.7K
RN126 8P4R-2.7K
ESB2 intergrated a weak internal pull-up 20K ohms.
EBUS_CE#1
EBUS_CE#1
LOW HIGH
Parallel Flash Not Present (default) Present
R3305 1K-0402
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
2
http://www.msi.com.tw
ESB2 PCI and BMC
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
38 90
Rev
0A
of
Page 39
5
4
3
2
1
ESB2 PATA/SATA/Serial/SMBus
PDD[15..0]67
VBAT
RTC
R548 20K
C527 1u/0805
CMOS Clear Jumper Normal (default) Clear CMOS2 - 3
Root Port Config.
C516 15P
R541 10M
C519 15P
P5V
R3154
R3131
X_0-0805
X_0-0805
21
BZ1 BUZZER
R1231
R1232 150-0805
150-0805
Q108
B
2N3904S
E C
R3172
4.7K
Q3027 2N3904S
DS
G
RTCRST_N
C528 1u/0805
4 X1 1 X4
Q3026 2N7002
SOT23SGD
R550 1K
1
2
D11 DAN202K
3
D D
P3V3_AUX
VBAT_HM
JBAT1
BAT1
1 - 2
ACZ_SDOUT/ACZ_SYNC
0 / 0
ESB2 intergrated a weak internal pull-down 20K ohms.
C C
RTC_XTAL1 RTC_XTAL2
B B
1 / 1
32.768MHz Crystal
Y2
32.768KHZ-12.5PF
P5VSB
R3130
R3129
0-0805
0-0805
Onboard Buzzer
Reboot Mode Config.
SPKR
Enabled
0
Disabled
1
ESB2 intergrated a weak internal pull-down 20K ohms.
A A
SPEAKER_BMC55
P3V3_AUX
SPEAKER_ICH
R3173
4.7K
5
P3V3
P3V3_AUX
B
R1233 X_1K
E C
INTRUSION_N50,54,65
R549 100
JBAT1 N33-1020331-H06
1 2 3
JBAT_(1-2)
N33-1020211-H06
PD_DACK#67
PD_IORDY67
P3V3
R3198 1K R3199 1K
ESB_14MHZ58
R531 10K
XDP0_TCK1_ESB20
XDP0_TDI_ESB20 XDP0_TDO_ESB20 XDP0_TMS_ESB20
XDP0_TRST#_ESB20
4
PD_DREQ67
PD_IOR#67
PD_IOW#67
PD_A267 PD_A167
PD_A067 PD_CS#167 PD_CS#367
P3V3_AUX
EECS47
EEDI47
EEDO47
EESK47
R3310
PDD15 PDD14 PDD13 PDD12 PDD11 PDD10 PDD9 PDD8 PDD7 PDD6 PDD5 PDD4 PDD3 PDD2 PDD1 PDD0 PD_DACK# PD_DREQ PD_IOR# PD_IOW#
PD_A1 PD_A0 PD_CS#1 PD_CS#3 PD_IORDY
ESB_14MHZ SPEAKER_ICH
XDP0_TCK1_ESB XDP0_TDI_ESB XDP0_TDO_ESB XDP0_TMS_ESB XDP0_TRST#_ESB
R536 10K
RTCRST_N RTC_XTAL1 RTC_XTAL2
EECS EEDI EEDO EESK
SMLINK0 SMLINK1 INTRUDER#
0
A15 G15 G14
E14
F13
E13
D12
C13
C12
D11 G12
F12 G11
E11
F10
E10
A11
A14
B13
B14
B10
A12
T32
U34
U32
U31
R33
R31
T33
B34
C33
C25
AG28
AF28 AF29 AF26
AG27
AT31
AP30 AR32 AR31 AR29
AP29 AN30
AT30
A29 B26 A27
AD36
AF35
AE35
AE36
D30 F30 C28
A8 A9
B8 B7
PDD[15..0]
DD15 DD14 DD13 DD12 DD11 DD10 DD9 DD8 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 DDACK_N DDREQ DIOR_N/DWSTB/RDMARDY_N DIOW_N/DSTOP DA2 DA1 DA0 DCS1_N DCS3_N IORDY_DRSTB/WDMRDY_N
ACZ_BIT_CLK ACZ_RST_N ACZ_SDIN2 ACZ_SDIN1 ACZ_SDIN0
ACZ_SDOUT ACZ_SYNC CLK14
SPKR INTVRMEN TCK
TDI TDO TMS TRST_N
RS232_CTS RS232_DCD RS232_DSR RS232_DTR RS232_RI RS232_RTS RS232_SIN RS232_SOUT
RTCRST_N RTCX1 RTCX2
EE_CS_N EE_DI EE_DO EE_SK
SMLINK0 SMLINK1 INTRUDER_N
ESB2 5/10
VCC
MODE
SCL SDA
MS-9192
R539 1M
R3404 X_4.7K R3405 X_4.7K R3406 X_4.7K R3407 X_4.7K R3408 X_4.7K R3409 X_4.7K R3410 X_4.7K R3411 X_4.7K R3412 X_4.7K R3413 X_4.7K
R1312 4.7K R1311 4.7K R3309 4.7K-0402
R3414 X_4.7K R3415 X_4.7K R3416 X_4.7K R3417 X_4.7K R3418 X_4.7K
R340 4.7K
R3202 1K-0402 R3200 1K-0402 R3201 1K-0402 R3203 1K-0402
P3V3_AUXP3V3_AUX
8 7 6 5
Last Revision Date:
Friday, April 27, 2007
Sheet
1
INTRUDER#
U39E
SATA5GP
SDTA
SCLK
SMBUS5 SMBUS3 SMBUS2 SMBUS1
SMBCLK SMBCLK0 SMBCLK1 SMBCLK2 SMBCLK3 SMBCLK4
SMBD0 SMBD1 SMBD2 SMBD3 SMBD4
ESB2
A18 H22 H23 L20 L19
G18 K20 K21 J22 J21
E19 G20 G21 H20 H19
C18 K17 K18 L17 L16
F18 H16 H17 J16 J15
D18 K14 K15 H14 H13
G23 G24 K23 J25
R532 24.9RST
H25
AH20 AJ20 B16 C15 F16 AL21 AH21 AN21 AK19 H29 E26 AG31 AJ32 AK33 G30 AE33 AG33 AF31 AH32 AJ34 AE32 AG34 AF32 AH33 AK34
SATA5RXN SATA5RXP SATA5TXN SATA5TXP
SATA4GP SATA4RXN SATA4RXP SATA4TXN SATA4TXP
SATA3GP SATA3RXN SATA3RXP SATA3TXN SATA3TXP
SATA2GP SATA2RXN SATA2RXPPD_A2 SATA2TXN SATA2TXP
SATA1GP SATA1RXN SATA1RXP SATA1TXN SATA1TXP
SATA0GP SATA0RXN SATA0RXP SATA0TXN SATA0TXP
SATA_100CLK_N SATA_100CLK_P SATA_LED_N
SCLK SDATA_OUT0
SDATA_OUT1 SMBUS5 SMBUS3 SMBUS2 SMBUS1 SMBDAT_ESB2 BMC_SCI_OUT_N SMBALRT2 SMBALRT3 SMBALRT4 SMBCLK_ESB2 SMBCLK0 SMBCLK1 SMBCLK2 SMBCLK3 SMBCLK4 SMBDAT0 SMBDAT1 SMBDAT2 SMBDAT3 SMBDAT4
SATA5GP/GPI13
SATA5RXN SATA5RXP SATA5TXN
SATA5TXP
SATA4GP/GPI12
SATA4RXN SATA4RXP SATA4TXN
SATA4TXP
SATA3GP/GPI31
SATA3RXN SATA3RXP SATA3TXN
SATA3TXP
SATA2GP/GPI30
SATA2RXN SATA2RXP SATA2TXN
SATA2TXP
SATA1GP/GPI29
SATA1RXN SATA1RXP SATA1TXN
SATA1TXP
SATA0GP/GPI26
SATA0RXN SATA0RXP SATA0TXN
SATA0TXP
SATACLKN SATACLKP
SATALED_N
SATARBIAS
SATARBIAS_N
SCLK/GPO20
SDATAOUT0/GPO23
SDATAOUT1/GPIO32
SMBDATA
SMBALERT_N/GPI11
SMBALRT2 SMBALRT3 SMBALRT4
3
R523 8.2K
SATA5RXN 46 SATA5RXP 46 SATA5TXN 46 SATA5TXP 46
R524 8.2K
SATA4RXN 46 SATA4RXP 46 SATA4TXN 46 SATA4TXP 46
R526 8.2K
SATA3RXN 46 SATA3RXP 46 SATA3TXN 46 SATA3TXP 46
R527 8.2K
SATA2RXN 46 SATA2RXP 46 SATA2TXN 46 SATA2TXP 46
R528 8.2K
SATA1RXN 46 SATA1RXP 46 SATA1TXN 46 SATA1TXP 46
R529 8.2K
SATA0RXN 46 SATA0RXP 46 SATA0TXN 46 SATA0TXP 46
SATA_100CLK_N 58 SATA_100CLK_P 58 SATA_LED_N 67
SATABIAS must be shorted under package and routed as single trace to resistor.
R3165 4.7K R3166 4.7K
SCLK 46 SDATA_OUT0 46
SDATA_OUT1 46
SMBDAT_ESB2 58 BMC_SCI_OUT_N 53
SMBCLK_ESB2 58
2
P3V3
P3V3
P3V3
P3V3
P3V3
P3V3
P3V3
RESREVED
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
SMBCLK0 SMBCLK1 SMBCLK2 SMBCLK3 SMBCLK4 SMBDAT0 SMBDAT1 SMBDAT2 SMBDAT3 SMBDAT4
SMBDAT_ESB2 SMBCLK_ESB2 BMC_SCI_OUT_N
SMBALRT2 SMBALRT3 SMBALRT4 SMLINK0 SMLINK1
PD_IORDY
Set SMBus address : 1100010
SMBUS2 SMBUS5 SMBUS3 SMBUS1
WHEA Circuit
R3216 X_220
U3022
1
A0
2
A1
3
A2
4
GND
X_24C02
ADDR : 0XAEh
Micro Star Restricted Secret
ESB2 PATA/SATA/Serial/SMBus
P3V3_AUX
C3201 X_0.1u
SMBCLK_ESB2 SMBDAT_ESB2
R3217 X_220
39 90
of
VBAT
P3V3
P3V3
Rev
0A
Page 40
5
4
3
2
1
ESB2 LAN/USB/FWH/MISC
P3V3
PE_WAKE# ESB_SYS_RST#R RI# BMC_PWREQ_N BMC_SMI_OUT_N
1 0
LAN Config. Enabled Disabled
LAN1_DIS# LAN0_DIS#
R3323
0
J_LANDIS_(1-2)
X_N33-1020211-H06
5
CPU_A20GATE SIO_KBRST# THRM_N FBD_RESET
FSB_FERR# THERMTRIP_N
Internal 2.5V VR Enabled Disabled
P3V3_AUXP3V3_AUX
X_N31-1030011-H06
For SE_ICOMP trace length <0.5", max trace width allowed the pins together inder BGA.
Place SK_LAN_CLK series resistor close to pin V36 to minimize stub.
R561
R560
2.2K
2.2K
R3421
R3422
X_1K
X_1K
J_LANDIS
1 2 3
P3V3_AUX
P_VTT
P3V3_AUX
R3420 X_10K
R1234 1K
R1221 10K-0402 R1377 8.2K R566 8.2K-0402 R3289 4.7K
R1222 8.2K-0402 R3419 8.2K R1378 8.2K R3207 4.7K-0402 R3208 4.7K-0402
R1241 51 R3308 1K
ESB_GPIO25
ESB_GPIO25
D D
C C
LAN_DIS#
1
B B
A A
0
LAN_DIS#_GPIO LAN_DIS#
For ESB2-E Version
FLSH_CE#
ESB_SYS_RST#9,54,67,68
R1235 1K
ESB_LAN_SERN147 ESB_LAN_SERN047 ESB_LAN_SERP147 ESB_LAN_SERP047
ESB_LAN_SETN147 ESB_LAN_SETN047 ESB_LAN_SETP147 ESB_LAN_SETP047
BIOS_PASSWORD45 BIOS_RECOVERY45
SYS_PWRGD_BUFF63,66
CPU_A20GATE55
PE_WAKE#38,50,51
CPU_VRD_PWRGD58,60,63
SYS_PWRGD_3_3V20,35,37,50,63,77
SK_LAN_CLK47
FWH_WP_N45
FBD_RESET35
RST_REQ_N54 BMC_SCI_N54
FSB_FERR#9,12
FSB_A20M#9,12
FSB_STPCLK#9,12
FSB_IGNNE#9,12
FSB_INIT#9,12,67 INIT#_3_3V45
FSB_INTR9,12
CPU_PWRGD9,12,64
FSB_SMI#9,12,54
SIO_KBRST#55
R3307 0
THERMTRIP_N61
SLP_S3_N54 SLP_S4_N54
R3212 0
PWR_BT_SSI_#54
AL30
SDP0_2
AK30
SDP0_1
AK31
SDP0_0
AP32
SDP1_2
AM31
SDP1_1
AL32
SDP1_0
AT33
SDP2_7
AR34
SDP2_6
AP35
P1V5_AUX
R558
24.9RST
R557 0
FBD_RESET LAN_DIS#_GPIO ESB_GPIO25
PLED67
FSB_FERR# SYS_PWRGD_BUFF CPU_A20GATE FSB_A20M# FSB_STPCLK# FSB_IGNNE# FSB_INIT# INIT#_3_3V FSB_INTR CPU_PWRGD
FSB_SMI# ESB2_NMI SIO_KBRST#
4
SLOAD RI#
RSMRST_ESB2# ESB_SYS_RST#R THRM_N THERMTRIP_N SLP_S3_N SLP_S4_N
SUSCLK
SLOAD46
RI#55
SUSCLK63
SDP2_5
AP33
SDP2_4
AN34
SDP2_3
AN33
SDP2_2
AN31
SDP2_1
AM32
SDP2_0
W33
SEICOMPI
V36
SER_CLK_IN
W32
SERCOMPO
W35
SERN1
V28
SERN0
W36
SERP1
V27
SERP0
Y34
SETN1
W30
SETN0
Y35
SETP1
W29
SETP0
D17
GPIO34
E16
GPIO33
B28
GPIO27
F27
GPIO25
D26
GPIO24
J28
GPIO28
A17
GPO19
B17
GPO18
G27
GPI8
E17
GPI7
G17
GPI6
A24
FERR_N
AM34
PERST_N
E22
A20GATE
A21
A20M_N
C22
STPCLK_N
A23
IGNNE_N
D23
INIT_N
E23
INIT3_3V_N
C21
INTR
F22
CPUPWRGD / GPO49
D21
CPUSLP_N
B23
SMI_N
B22
NMI
C24
RCIN_N
C16
SLOAD / GPO21
H28
SUS_STAT_N / LPCPD_N
J27
RI_N
A26
RSMRST_N
K24
SYS_RESET_N
F24
THRM_N
B32
THRMTRIP_N
D29
SLP_S3_N
E29
SLP_S4_N
G29
SLP_S5_N
AL33
PE_WAKE_N
F25
SUSCLK
K22
VRMPWRGD
F28
PWRBTN_N
B25
PWROK
ESB2 3/10
LPC
LAN
GPIO
PHY_POWER_DOWN
SDRAM_AD12/SDP3_1/LED0_1
SDRAM_BA0/SDP3_2/LED0_2 SDRAM_BA1/SDP3_3/LED0_3
SDRAM_A9/SDP3_5/LED1_1 SDRAM_A10/SDP3_6/LED1_2 SDRAM_A11/SDP3_7/LED1_3
3
FWH0/LFRAME_N
USB
LAN_PWR_GOOD
U39C
FLBSD1
FLBSD0 FLBSINTEX1 FLBSINTEX0
FLSH_CE_N
FLSH_SCK
FLSH_SI
FLSH_SO
FWH3/LAD3 FWH2/LAD2 FWH1/LAD1 FWH0/LAD0
LDRQ_N1/GPI41
LDRQ_N0
CLK48
USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P
USBRBIAS
USBRBIAS_N
OC_N_7/GPI15 OC_N_6/GPI14 OC_N_5/GPI10
OC_N_4/GPI9
0C_N_3
0C_N_2
0C_N_1
0C_N_0 LAN1_DIS_N
LAN0_DIS_N
EEPRTDIS_N
PHYRST_N
SDP3_0/LED0_0
SDP3_4/LED1_0
LINK_0 LINK_1
ESB2
AK36 AL35 AM35 AL36
AJ35 AH35 AH36 AG36
D20 C19 B19 B20 A20 F21 E20
H11 C9
C10 D8 D9 E7 E8 C6 C7 A5 A6 B4 B5 C3 C4 D2 D3 J12 J13
F7
USB_OC#4
F6
BMC_PWREQ_N
F1
BMC_SMI_OUT_N
E4 E1 E2 D6 D5
AM29 AL29
AE27 AA36
AB36
AG25 AH29 AJ31 AJ29 AH24 AH27 AH30 AH26 AB35 AC35 AN36
FLBSD1 FLBSD0 FLBSINTEX1 FLBINTEX0
FLSH_CE#
LFRAME# LAD3 LAD2 LAD1 LAD0
CK_48M_ESB USBP0N
USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P
R559 22.6RST
USB_OC#2 USB_OC#0 LAN1_DIS#
LAN0_DIS#
R562 X_1K
ESB_LINK0 ESB_LINK1 LAN_RSMRST#
R551 10K-0402 R552 10K-0402 R553 10K-0402 R554 10K-0402
R3186 10K-0402
R3362 33 R3363 33
P3V3_AUX
R569
10K
P3V3_AUX
LFRAME# 45,53,67 LAD3 45,53,67 LAD2 45,53,67 LAD1 45,53,67 LAD0 45,53,67
TP102 TP93
CK_48M_ESB 58 USBP0N 53
USBP0P 53 USBP1N 53 USBP1P 53 USBP2N 46 USBP2P 46 USBP3N 46 USBP3P 46 USBP4N 68 USBP4P 68 USBP5N 68 USBP5P 68 USBP6N 67 USBP6P 67 USBP7N 67 USBP7P 67
USB_DISCON 53 USB_OC#4 68 BMC_PWREQ_N 54 BMC_SMI_OUT_N 53
USB_OC#2 46 USB_OC#0 67
LAN_DIS#
R570 10K
ESB_LINK0 47 ESB_LINK1 47
2
ESB2_NMI
BMC_NMI54
NMI To CPU Ckt
P5V
P_VTT
R3168
2.7K R3171
B
4.7K
P3V3_AUX
R3195 10K
R3193 X_4.7K
Power Well Isolation Between RTC And Standby 3.3V Place As Close To Pin A26 As Possible
RSMRST#47,57,63
LAN_RSMRST#
C565 X_103P
E C
P3V3_AUX
R3170
4.7K
B
RSMRST#
R572
0
R3354
Q3015 MMBT3904
R3206 X_10K
B
Q3018 X_MMBT3904
E C
X_0
R3169 10K
G
Q3014 MMBT3904
E C
Q68 2N3906S
1
2 1
2
3
D13 1PS226_SOT23
3
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
ESB2 LAN/USB/FWH/MISC
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
DS
Q3024 2N7002
SOT23SGD
RSMRST_ESB2#
D12 1PS226_SOT23
R583
2.2K
40 90
1
FSB_NMI 9,12
R576 100K
Rev
0A
of
Page 41
5
4
3
2
1
ESB2 Power/GND Part1
D D
U39H
VCC15_9 VCC15_8 VCC15_7 VCC15_6 VCC15_5 VCC15_4 VCC15_3 VCC15_2 VCC15_1 VCC15_0
VCC33_16 VCC33_15 VCC33_14 VCC33_13 VCC33_12 VCC33_11 VCC33_10
VCC33_9 VCC33_8 VCC33_7 VCC33_6 VCC33_5 VCC33_4 VCC33_3 VCC33_2 VCC33_1 VCC33_0
VCCARX_5 VCCARX_4 VCCARX_3 VCCARX_2 VCCARX_1 VCCARX_0
VCCATX_5 VCCATX_4 VCCATX_3 VCCATX_2 VCCATX_1 VCCATX_0
VCC_AUX1_5_7 VCC_AUX1_5_6 VCC_AUX1_5_5 VCC_AUX1_5_4 VCC_AUX1_5_3 VCC_AUX1_5_2 VCC_AUX1_5_1 VCC_AUX1_5_0
VCCSE_6 VCCSE_5 VCCSE_4 VCCSE_3 VCCSE_2 VCCSE_1 VCCSE_0
ESB2
AB7 AB10 AB11 AB12 AC6 AC12 AD11 AD12 AE12 AG12
AE15 AE17 AE18 AF17 AG17 AH13 AK11 AK17 AM9 AM12 AM15 AP10 AP13 AP16 AT11 AT14 AT17
A16 B18 D16 F15 K16 M16
F17 F20 G19 H18 L18 M18
Y21 Y23 AA22 AB21 AB23 AC22 AD21 AD23
W24 W26 Y24 Y25 Y27 Y30 Y33
ESB2 STRAPS
ESB_STRAP_7 ESB_STRAP_6 ESB_STRAP_5 ESB_STRAP_4
ESB_STRAP_3 ESB_STRAP_2
C C
B B
ESB_STRAP_1
Reserved for ESB2 A0 Stepping Gilgal LAN 62.5MHz
ESB_STRAP_0
R534 10K-0402 R540 0-0402 R542 0-0402 R543 0 R544 X_4.7K-0402 R545 4.7K-0402 R546 X_4.7K
R3364 1K
R547 10K
R3371 X_1K
R537 4.7K
P3V3 P1V5_AUX P1V5
P3V3
P3V3_AUX
P3V3_AUX
P3V3_AUX
R3423 330
ESB_STRAP_7 ESB_STRAP_6 ESB_STRAP_5 ESB_STRAP_4 ESB_STRAP_3 ESB_STRAP_2 ESB_STRAP_1 ESB_STRAP_0
TP73 TP72 TP71
AD34
D15 F35
L22 M10 M12 M15 M21 M23 M24
P10
P11
P24
R28
U25
V25
AD25 AE13 AE23 AF14 AF18 AF22 AF23 AL17
AM17 AD31
U26
U28
E28
F19
AF21 AF20
K27
AK21
AD28
AE30 AE26
R1
NOCONN NOCONN NOCONN NOCONN NOCONN NOCONN NOCONN NOCONN NOCONN NOCONN NOCONN NOCONN NOCONN NOCONN NOCONN NOCONN NOCONN NOCONN NOCONN NOCONN NOCONN NOCONN NOCONN NOCONN NOCONN NOCONN
ESB2_TEST2 ESB2_TEST1 ESB2_TEST0
TP0
STRAP_7 STRAP_6 STRAP_5 STRAP_4 STRAP_3 STRAP_2 STRAP_1 STRAP_0
ESB2 6/10
U39F
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
RESERVED
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
ESB2
AC29 AD27 AD30 AD33 AE29 AF19 AG18 AG19 AG21 AH17 AH18 AN18 AK9
AN19 AA33 Y29 AB33 Y31 AB30 AC32 AB32 AA31 AA30 Y32 AA34 AC25 AC31 Y28 AC34 AA27 AB27 AB29 AC26 AC28 Y26 W27 AA28 AB26 AF34
ESB_STRAP_8
R525
0
W14 W16 W18 W20 W22
AA14 AA16 AA18 AA20 AB13 AB15 AB17
AB19 AC14 AC16 AC18 AC20 AD13 AD15 AD17 AD19
N14 N16 N18 N20 N22 P13 P15 P17 P19 P21 P23 R14 R16 R18 R20 R22 T13 T15 T17 T19 T21 T23 U14 U16 U18 U20 U22 V13 V15 V17 V19 V21 V23
Y13 Y15 Y17 Y19
VCC_57 VCC_56 VCC_55 VCC_54 VCC_53 VCC_52 VCC_51 VCC_50 VCC_49 VCC_48 VCC_47 VCC_46 VCC_45 VCC_44 VCC_43 VCC_42 VCC_41 VCC_40 VCC_39 VCC_38 VCC_37 VCC_36 VCC_35 VCC_34 VCC_33 VCC_32 VCC_31 VCC_30 VCC_29 VCC_28 VCC_27 VCC_26 VCC_25 VCC_24 VCC_23 VCC_22 VCC_21 VCC_20 VCC_19 VCC_18 VCC_17 VCC_16 VCC_15 VCC_14 VCC_13 VCC_12 VCC_11 VCC_10 VCC_9 VCC_8 VCC_7 VCC_6 VCC_5 VCC_4 VCC_3 VCC_2 VCC_1 VCC_0
ESB2 8/10
P1V5P1V5
P3V3
P1V5
P1V5
P1V5_AUX
P1V5_AUX
A A
Title Document Number
5
4
3
2
Micro Star Restricted Secret
ESB2 Power/GND Part1
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
41 90
1
Rev
0A
of
Page 42
5
4
3
2
1
ESB2 Power/GND Part2
P3V3_AUX
U39G
VCCPSUS8 VCCPSUS_7 VCCPSUS_6 VCCPSUS_5 VCCPSUS_4 VCCPSUS_3 VCCPSUS_2 VCCPSUS_1 VCCPSUS_0
VCCPUSB_4 VCCPUSB_3 VCCPUSB_2 VCCPUSB_1 VCCPUSB_0
VCCUSBCORE_4 VCCUSBCORE_3 VCCUSBCORE_2 VCCUSBCORE_1 VCCUSBCORE_0
VCCAUBG
VSSAUBG
VCCBGESI VSSBGESI
VCCBGPE
VSSBGPE
VCCA3_3 VSSA3_3
VCCASATABG VSSASATABG
VCCAPE VSSAPE
VCCAUPLL
VCCAPLL1_5 VSSAPLL1_5
VREFPCI VCC5REF2 VCC5REF1
VCC5REFSUS
VCCAESI
VCCAP3 VCCAP1
VCCAPLL VCCP25IDE VCCP25PCI
VCCPRTC VCCSATA VCCSUS1 VCCSUS2
VCCUSB
ESB2
D34 F32 H30 K25 K26 K28 L25 L26 M25
A4 B3 C5 E6 G7
D1 G4 J8 K8 K9
K12 K11
L11 L10
V1 AA1
V30 V31
J18 J19
ESB_VCCA_EXP
V7
ESB_VSSA_EXP
V6
ESB_VCCAUPLL
F9 V33
V34 AC11
D14 U29
VCC5VREFSUS
E5 M9
ESB_VCCAPCI3
AD10
ESB_VCCAPCI1
AE11 G26 N11 T27 C27 H26 M27 N27 H10
4
P1V5
AU_VCCBG AU_VSSBG
ESI_VCCBG ESI_VSSBG
PE_VCCBG PE_VSSBG
ESB_VCCA3_3
ESB_VSSA3_3
SATA_VCCBG SATA_VSSBG
VCCAUPLL1_5
VSSAUPLL1_5
VREFPCI VCC5VREF
ESB_VCCAESI
ESB_VCCAPLL ESB_VCCPIDE ESB_VCCPPCI
VBAT P1V5 P1V5_AUX
P3V3_AUX
P5V
P3V3_AUX
P1V5_AUX
B24 C23 D24
N12 P12
T12 U12 V11
Y12
A13 C14 E12 H15 K13
L13 L14
K31
L33
N24 N26 N31 P25 P26 P27 P33 P36 R25 R27 R29 T24 T26
M2 N4
N7
P9
R2 R5
T7
U3
V5
W7
Y3 Y9
VSS2_7 VSS2_6 VSS2_5 VSS2_4 VSS2_3 VSS2_2 VSS2_1 VSS2_0
VCCAUX3_3_15 VCCAUX3_3_14 VCCAUX3_3_13 VCCAUX3_3_12 VCCAUX3_3_11 VCCAUX3_3_10 VCCAUX3_3_9 VCCAUX3_3_8 VCCAUX3_3_7 VCCAUX3_3_6 VCCAUX3_3_5 VCCAUX3_3_4 VCCAUX3_3_3 VCCAUX3_3_2 VCCAUX3_3_1 VCCAUX3_3_0
VCCPCPU_2 VCCPCPU_1 VCCPCPU_0
VCCPE_20 VCCPE_19 VCCPE_18 VCCPE_17 VCCPE_16 VCCPE_15 VCCPE_14 VCCPE_13 VCCPE_12 VCCPE_11 VCCPE_10 VCCPE_9 VCCPE_8 VCCPE_7 VCCPE_6 VCCPE_5 VCCPE_4 VCCPE_3 VCCPE_2 VCCPE_1 VCCPE_0
VCCP_IDE_5 VCCP_IDE_4 VCCP_IDE_3 VCCP_IDE_2 VCCP_IDE_1 VCCP_IDE_0 VCCP_IDE_6 VCCP_IDE_7
VCCPPCI_16 VCCPPCI_15 VCCPPCI_14 VCCPPCI_13 VCCPPCI_12 VCCPPCI_11 VCCPPCI_10 VCCPPCI_9 VCCPPCI_8 VCCPPCI_7 VCCPPCI_6 VCCPPCI_5 VCCPPCI_4 VCCPPCI_3 VCCPPCI_2 VCCPPCI_1 VCCPPCI_0
ESB2 7/10
AA25 AA35
D D
P3V3_AUX
P_VTT
C C
P1V5
B B
P3V3
P3V3
A A
5
AB24 AB25 AB31 AC33 AD29 AD35
AE24
AF25
AF27 AG24 AG29 AH25 AH31
AJ27 AK29 AK32 AM30 AM33 AN35 AP31 AR33
AT29
M11
W12
AA12
M13
M29 M35
P3V3
P3V3
P1V5
C1067 1u
R765
0.499RST
R766
0.499RST
R772
220
R752
0.499RST
R769
0.499RST
R764
0.499RST
R762
0.499RST
L26
4.7uH-0805-30mA
R767
0
L27
4.7uH-0805-30mA
R768
0
P2V5_REF1
1
U49
LM431AIM3/Vf=2.5V
3 2
0 ohm and 22u need close
L19
4.7uH-0805-30mA
R754
0
L28
4.7uH-0805-30mA
R771
0
L25
4.7uH-0805-30mA
L23
4.7uH-0805-30mA
3
R773
0.499RST
C1057 22u-1206
C1059 22u-1206
L30
4.7uH-0805-30mA
C1040 22u-1206
C1061 22u-1206
ESB_VCCA_EXP
C1055 22u-1206
ESB_VSSA_EXP
ESB_VCCAUPLL
C1051 22u-1206
AU_VCCBG
C1058 103P
AU_VSSBG
ESI_VCCBG
C1060 103P
ESI_VSSBG
ESB_VCCA3_3
C1041 103P
ESB_VSSA3_3
SATA_VCCBG
C1062 103P
SATA_VSSBG
C1056 103P
C1052 103P
C1065 22u-1206
R774 0
PE_VCCBG
C1066 103P
PE_VSSBG
ESB_VCCPIDE ESB_VCCPPCI
P1V5_AUX
2
P1V5
P3V3_AUX
P1V5
P1V5
P1V5
P1V5
C1068 103P
R755
0.499RST
R760
150RST
A C
1N4148
A C
1N4148
R757
0.499RST
R770
0.499RST
R763
0.499RST
R759
0.499RST
L20
4.7uH-0805-30mA
R761 150RST
D14
D15
VCC5VREFSUS
4.7uH-0805-30mA
4.7uH-0805-30mA
4.7uH-0805-30mA
4.7uH-0805-30mA
C1069 103P
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
VCCAUPLL1_5
C1043
C1042
103P
22u-1206
VSSAUPLL1_5
VREFPCI
C1050 1u
C1044 1u
C1047 1u
C1045 22u-1206
C1063 22u-0805
C1053 22u-1206
C1048 22u-1206
R756
10
R758
10
ESB_VCCAESI
C1046 103P
ESB_VCCAPCI3
C1064 103P
ESB_VCCAPCI1
C1054 103P
ESB_VCCAPLL
C1049 103P
P5VP3V3
P5VSB
VCC5VREF
L21
L29
L24
L22
Micro Star Restricted Secret
ESB2 Power/GND Part2
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
42 90
of
Rev
0A
Page 43
5
4
3
2
1
ESB2 Power/GND Part3
U39I
A3
VSS
A7
VSS
A10
VSS
A19
VSS
D D
C C
B B
A A
A22 A25 A28 A31 A34
B12 B15 B21 B27 B30 B33 B35
C11 C17 C20 C26 C29 C32 C35 C36
D10 D13 D19 D22 D25 D28 D31
E15 E18 E21 E24 E27 E30 E33 E36
F11 F14 F23 F26 F29
G10 G13 G16 G22 G25 G28 G31 G34
H12 H21 H24 H27 H33 H36
VSS VSS VSS VSS VSS
B2
VSS
B6
VSS
B9
VSS VSS VSS VSS VSS VSS VSS VSS
C1
VSS
C2
VSS
C8
VSS VSS VSS VSS VSS VSS VSS VSS VSS
D4
VSS
D7
VSS VSS VSS VSS VSS VSS VSS VSS
E3
VSS
E9
VSS VSS VSS VSS VSS VSS VSS VSS VSS
F2
VSS
F5
VSS
F8
VSS VSS VSS VSS VSS VSS
G1
VSS VSS VSS VSS VSS VSS VSS VSS VSS
H3
VSS
H6
VSS
H9
VSS VSS VSS VSS VSS VSS VSS
J2
VSS
J5
VSS
VSS
VSS
VSS
VSS
J11
J14
J17
J20
5
VSS
VSS
VSS
VSS
J23
J26
J29
J32
ESB2 9/10
VSS
VSSK1VSSK4VSSK7VSS
VSS
VSS
VSS
J35
K10
K19
K34
V35
V32
VSS
V29
VSS
V26
VSS
V24
VSS
V22
VSS
V20
VSS
V18
VSS
V16
VSS
V14
VSS
V12
VSSV2VSSV8VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
ESB2
4
L3 L6 L9 L12 L15 L21 L23 L24 L27 L30 L36 M5 M8 M14 M17 M19 M20 M22 M26 M32 N1 N10 N13 N15 N17 N19 N21 N23 N25 N28 N34 P3 P6 P14 P16 P18 P20 P22 P30 R8 R11 R12 R13 R15 R17 R19 R21 R23 R24 R26 R32 R35 T1 T4 T10 T14 T16 T18 T20 T22 T25 T28 T31 T34 U6 U9 U13 U15 U17 U19 U21 U23 U24 U27 U30 U33 U36
W10 W13 W15 W17 W19 W21 W23 W25 W28 W31 W34
Y14 Y16 Y18 Y20 Y22
Y36 AA2 AA5 AA8
AA11 AA13 AA15 AA17 AA19 AA21 AA23 AA24 AA26 AA29 AA32
AB1 AB4
AB14 AB16 AB18 AB20 AB22 AB28 AB34
AC3 AC9
AC13 AC15 AC17 AC19 AC21 AC23 AC24 AC27 AC30 AC36
AD2 AD5 AD8
AD14 AD16 AD18 AD20 AD22 AD24 AD26 AD32
AE1 AE4 AE7
AE10 AE14 AE16 AE19 AE20 AE21 AE22
W1
VSS
W4
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Y6
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AT34
VSS
VSS
VSS
VSS
VSS
VSS
AT8
AT20
AT23
AT26
AT32
VSS
VSS
VSS
VSS
VSS
AT3
AT5
AR27
AR30
AR35
3
ESB2 10/10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AR2
AR3
AR6
AR9
AP36
AR12
AR15
AR18
AR21
AR24
VSS
AP34
VSS
AP28
VSS
AP25
VSS
AP22
VSS
AP19
AP7
VSS
AP4
VSS
AP1
VSS
U39J
AG5
VSS
AG2
VSS
AF36
VSS
AF33
VSS
AF30
VSS
AF24
VSS
AF15
VSS
AF13
VSS
AF12
VSS
AF9
VSS
AF6
VSS
AF3
VSS
AE34
VSS
AE31
VSS
AE28
VSS
AE25
VSS
AG8
VSS
AG11
VSS
AG14
VSS
AG20
VSS
AG23
VSS
AG26
VSS
AG32
VSS
AG35
VSS
AH4
VSS
AH7
VSS
AH10
VSS
AH16
VSS
AH19
VSS
AH22
VSS
AH28
VSS
AH34
VSS
AJ3
VSS
AJ6
VSS
AJ9
VSS
AJ12
VSS
AJ15
VSS
AJ18
VSS
AJ21
VSS
AJ24
VSS
AJ30
VSS
AJ33
VSS
AJ36
VSS
AK2
VSS
AK5
VSS
AK8
VSS
AK14
VSS
AK20
VSS
AK23
VSS
AK26
VSS
AK35
VSS
AL1
VSS
AL4
VSS
AL7
VSS
AL10
VSS
AL13
VSS
AL16
VSS
AL19
VSS
AL22
VSS
AL25
VSS
AL28
VSS
AL31
VSS
AL34
VSS
AM6
VSS
AM18
VSS
AM21
VSS
AM24
VSS
AM27
VSS
AM36
VSS
AN2
VSS
AN5
VSS
AN8
VSS
AN11
VSS
AN14
VSS
AN17
VSS
AN20
VSS
VSS
VSS
VSS
VSS
ESB2
AN23
AN26
AN29
AN32
2
Title Document Number
Micro Star Restricted Secret
ESB2 Power/GND Part3
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
43 90
1
Rev
0A
of
Page 44
5
ESB2 Decoupling Cap.
4
3
2
1
D D
C C
ESB2 1.5V Decoupling Caps.
P1V5
C597 1u
C619 1u
C575 1u
C599 1u
C621 1u
C577 1u
C601 1u
C623 1u
C583 1u
C605 1u
C625 1u
C604 1u
C607 1u
C596 1u
C606 1u
P1V5
P1V5
C593 1u
C615 1u
C521 1u
C595 1u
C617 1u
C523 1u
C609 1u
C598 1u
C608 1u
C611 1u
C600 1u
C613 1u
C517 1u
ESB2 1.5V AUX Decoupling Caps.
P1V5_AUX
C584
C576 1u
P1V5_AUX
C520 1u
C578 1u
C522 1u
C580 1u
C582 1u
C586
1u
C588
1u
1u
C590
4.7u-1206
C592
4.7u-1206
3.3V AUX Decoupling Caps.
P3V3_AUX
C498
C496 1u
C500
1u
C502
1u
1u
P5VSB
C515 1u
C504 1u
C506 1u
C508 1u
C510
4.7u-1206
C512
4.7u-1206
ESB2 3.3V Decoupling Caps.
P1V5
P3V3
C589
C525
B B
4.7u-1206
C526
4.7u-1206
4.7u-1206
C591
4.7u-1206
C627
4.7u-1206
C629
4.7u-1206 C495 1u
C497 1u
C499 1u
C501 1u
C503 1u
C505 1u
C507 1u
C509
4.7u-1206
C511
4.7u-1206
P3V3
C614
C616
1u
1u
A A
5
4
C618 1u
C620 1u
C622 1u
3
C624 1u
C626 1u
C628
4.7u-1206
C630
4.7u-1206
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
2
http://www.msi.com.tw
ESB2 Decoupling Cap.
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
44 90
Rev
0A
of
Micro Star Restricted Secret
Page 45
5
4
3
2
1
Firmware Hub
FGPI2
SAS function
High
SAS SATALow
D D
PLTRST_BUFF1#53,63,67 FWH_PCLK 58
FGPI2_MODE46
P3V3
C C
BIOS_RECOVERY40
R3150 1K
J_RECOVERY
N31-1030011-H06
R3151
8.2K
C662
0.1u
3 2 1
J_RECOVERY
FWH_WP_N40
J_RECOVERY_1-2
N33-1020331-H06
1-2 2-3
P3V3
B B
TPM_DISABLE54
A A
5
R1411
4.7K_0402
R1409
4.7K_0402 R1413 X_0
Q35
B
2N3904S
E C
R38 X_8.2K R40 0 R3148 X_8.2K R3149 X_8.2K
LAD040,53,67 LAD140,53,67 LAD240,53,67
BIOS Recovery Normal Recover
R1415 0
P3V3
B
E C
4
R1410
4.7K_0402 R1414 X_0
Q41 2N3904S
PLTRST_BUFF1#
R37
4.7K
IDE_PRI_CBLSNS FGPI2 PCI1_GPI1 PCI1_GPI0
R43 470 R45 8.2K R46 8.2K R47 8.2K R48 8.2K
P3V3 P3V3
P3V3P3V3
1 2
R680 X_4.7K
PP
R687 X_4.7K
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16
P3V3
R1412
X_0
VPP RST# FGPI3 FGPI2 FGPI1 FGPI0 WP# TBL# ID3 ID2 ID1 ID0 FWH0 FWH1 FWH2 GND
U98
53
74AHC1G08
4
R679
4.7K
R667 X_4.7K
BADDR
P3V3
FWH1
VCC
CLK
FGPI4
IC(VIL)
GNDA
VCCA
GND VCC
INIT#
FWH4
RFU RFU RFU RFU RFU
FWH3
PLCC-32
SERIRQ38,53 TPM_PCLK58
P3V3
3
P3V3 P3V3
FGPI4
IDE_PRI_CBLSNS67
P3V3
R666
4.7K
6 19
24 10
5 18
25 11 4
14 13
12
NC
3
P3V3_AUX
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
LAD0 LAD1 LAD2 LAD3 LFRAME#
TPMRST#
R623 4.7K R707 4.7K
R708 33R
TPM_PCLK
R700 4.7K
R1247 4.7K
FGPI4
INIT#_3_3V
TP1 TP2 TP3 TP4 TP5
BADDR
PP
C26
C27
0.1u
0.1u
R39 8.2K R41 8.2K
26 23 20 17 22
16 28 15 27
21
9 8 7
2 1
C28
0.1u
INIT#_3_3V 40 LFRAME# 40,53,67
LAD3 40,53,67
BIOS_PASSWORD40
TPM module
U59
LAD0 LAD1 LAD2 LAD3 LFRAME#
LRESET# LPCPD# CLKRUN# SERIRQ
LCLK TESTBI/BADD
TESTI PP
GPIO2 NC#1
SLB9635TT1.2-RH
VDD#24 VDD#10
GND#25 GND#11
GND#4 XTALO
XTALI/32KIN
GPIO
VDD
VSB
GND
NC#3
Addresses: PIN 9 pull up to Vcc3 = 4Eh/4Fh Addresses: PIN 9 pull down to GND = 2Eh/2Fh
2
IDE_PRI_CBLSNS
FGPI2
P3V3
C649
0.1u
INIT#_3_3V
R3152 1K
R3153
8.2K
Y7
PCI1_GPI1 PCI1_GPI0
J_PASSWORD
3 2 1
N31-1030011-H06
C651 1u
Title Document Number
PCI1_GPI150 PCI1_GPI050
P3V3
R3424 X_10K
32.768KHz-12.5pF-20PPM
C650
0.1u
C1242 15p
R1246 10M
C1243 15p
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
R3374 X_1K R3345 X_1K R3346 10K R3347 X_1K R3348 X_1K
J_PASSWORD_1-2
N33-1020331-H06
J_PASSWORD
1-2 2-3
P3V3
C652
0.1u
BIOS Password Normal Clear
Micro Star Restricted Secret
Firmware Hub/TPM
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
45 90
1
Rev
0A
of
Page 46
5
4
3
2
1
SATA/USB Connectors
SATA Connectors
D D
SATA0RXP SATA0RXPR
SATA0RXP39 SATA0RXN39
SATA1RXP39 SATA1RXN39 SATA1TXN 39
FGPI2_MODE45
SDATA_OUT039
SATA2RXN39 SATA3RXP39
SATA3RXN39 SATA3TXN 39
C C
B B
P3V3
X_4.7K
R52
0
R3366
SB5
SLOAD SCLK
SATA4TXP39 SATA4TXN39
SATA4RXN39
SATA4RXP39
SATA5TXP39 SATA5TXN39
SATA5RXN39
SATA5RXP39
C1617 103P-0402 C1615 103P-0402 C1613103P-0402
C1616 103P-0402 C1614 103P-0402
SDATA_OUT0
SATA2RXN SATA3RXP
SATA3RXN
C1609 103P-0402 C1607 103P-0402
C1608 103P-0402 C1606 103P-0402
J1
1 2 3 4 5 7
N31-2040131-H06
SATA4TXP SATA4TXN
SATA4RXN SATA4RXP
SATA5TXP SATA5TXN
SATA5RXN SATA5RXP
R3365 0
6 8
SATA0RXNR SATA0TXNR SATA1RXPRSATA1RXP SATA1TXPSATA1TXPR
SATA1RXNR SATA1TXNRSATA1RXN
SB5
SATA2RXPR SATA2RXNR SATA2TXNR
SATA3RXPR SATA3RXNR
SDATA_OUT1
C1618 103P-0402 C1620 103P-0402
C1622 103P-0402 C1624 103P-0402
C1619 103P-0402 C1621 103P-0402
C1623 103P-0402 C1625 103P-0402
A1 A2 A3 A4 A5 A6 A7 A8
A9 A10 A11 A12 A13 A14 A15 A16 A17 A18
19
20
21
SATA4TXPR SATA4TXNR
SATA4RXNR SATA4RXPR
SATA5TXPR SATA5TXNR
SATA5RXNR SATA5RXPR
U1
GND Rx0+ Rx0­GND Rx1+ Rx1­GND SB7 SB3 SB4 SB5 GND Rx2+ Rx2­GND Rx3+ Rx3­GND
19 20 21
MINISAS
GND Tx0+
Tx0­GND Tx1+
Tx1­GND
SB0
SB1
SB2
SB6 GND Tx2+
Tx2­GND Tx3+
Tx3­GND
22 23 24
1 2 3 4 5 6 7
1 2 3 4 5 6 7
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18
22 23 24
SATA1
GND HT+ HT­GND HR­HR+ GND
SATA-blue
SATA2
GND HT+ HT­GND HR­HR+ GND
SATA-blue
SATA0TXPR
SATA2TXPR
SATA3TXPR
SATA3TXNR
SATA0TXP
C1611103P-0402
SATA0TXNSATA0RXN
C1610103P-0402
SATA1TXN
C1612103P-0402
C1603103P-0402 C1605103P-0402
C1602103P-0402 C1604103P-0402
SCLK
SLOAD
SATA2TXPSATA2RXP SATA2TXN
SATA3TXP SATA3TXN
R33690 R33670
SATA0TXP 39
SATA0TXN 39
SATA1TXP 39
SCLK 39
SLOAD 40
SATA2TXP 39SATA2RXP39
SATA2TXN 39
SATA3TXP 39
SDATA_OUT139
SDATA_OUT1 SDATA_OUT0 SLOAD SCLK
R42 4.7K R44 4.7K R49 4.7K R50 4.7K
Rear USB Connectors
RN43
0-8P4R
BN1
USB2P USB2N
USB3N
F3000 2A6V
P5V
R3015
5.1K
R3014
2.7K
USB_OC#240
USB_OC#2
USBPWR23
12
+
EC3000 1000u-6.3V
C3002
0.1u
12
+
EC3002 1000u-6.3V
8 7 6 5
X_90_COMM
P3V3
12 34 56 78
1 2 3 4
6 1 5
6 1 5
USBP2P USBP2N USBP3PUSB3P USBP3N
USB3003
USB3004
USB_D4
USB_D4
USBP2P 40 USBP2N 40 USBP3P 40 USBP3N 40
USB2P
3 4
USB2N
2
USB3P
3 4
USB3N
2
A A
Title Document Number
5
4
3
2
Micro Star Restricted Secret
SATA/USB Connectors
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
46 90
1
Rev
0A
of
Page 47
5
LAN PHY Gilgal
D D
C C
RSMRST#40,57,63
LAN_A_MDIP[3..0]48 LAN_A_MDIN[3..0]48 LAN_B_MDIP[3..0]48 LAN_B_MDIN[3..0]48
R825
0
Place caps close to Gilgal
B B
ESB_LAN_SERN040 ESB_LAN_SERP040 ESB_LAN_SERN140 ESB_LAN_SERP140
C1077 103P R791 X_0 C1083 103P C1084 103P C1085 103P
Place caps close to ESB2
ESB_LAN_SETN040 ESB_LAN_SETP040 ESB_LAN_SETN140 ESB_LAN_SETP140
C1086 0.1u C1087 0.1u C1088 0.1u C1089 0.1u
LAN_A_MDIP[3..0] LAN_A_MDIN[3..0] LAN_B_MDIP[3..0] LAN_B_MDIN[3..0]
PHY_RSM_RST#
C1090 X_103P
GILGAL_LAN_SETN0 GILGAL_LAN_SETP0 GILGAL_LAN_SETN1 GILGAL_LAN_SETP1
GILGAL_LAN_SERN0 GILGAL_LAN_SERP0 GILGAL_LAN_SERN1 GILGAL_LAN_SERP1
TP36
TP19
4
LAN_A_MDIP3 LAN_A_MDIP2 LAN_A_MDIP1 LAN_A_MDIP0
LAN_A_MDIN3 LAN_A_MDIN2 LAN_A_MDIN1 LAN_A_MDIN0
LAN_B_MDIP3 LAN_B_MDIP2 LAN_B_MDIP1 LAN_B_MDIP0
LAN_B_MDIN3 LAN_B_MDIN2 LAN_B_MDIN1 LAN_B_MDIN0
MDC MDIO_ADD3 MDIO_ADD2 MDIO_ADD1 MDIO_ADD0
LAN_PD_TCK LAN_PU_TDI LAN_PU_TMS LAN_TEST_JTAG
PHY_REF PHY_PWRDOWN PHY_RST# PHY_RSM_RST#
PHY_MODE_SEL
GILGAL_LAN_SETN0 GILGAL_LAN_SETP0 GILGAL_LAN_SERP0 GILGAL_LAN_SERN0
GILGAL_LAN_SERN1 GILGAL_LAN_SERP1 GILGAL_LAN_SETP1 GILGAL_LAN_SETN1
P1V8LAN
P3V3_AUX
36
MDIA_PLUS3
33
MDIA_PLUS2
31
MDIA_PLUS1
27
MDIA_PLUS0
37
MDIA_MINUS3
34
MDIA_MINUS2
32
MDIA_MINUS1
28
MDIA_MINUS0
39
MDIB_PLUS3
42
MDIB_PLUS2
44
MDIB_PLUS1
48
MDIB_PLUS0
38
MDIB_MINUS3
41
MDIB_MINUS2
43
MDIB_MINUS1
47
MDIB_MINUS0
76
MDIO
77
MDC
19
MDIO_ADD3
18
MDIO_ADD2
79
MDIO_ADD1
78
MDIO_ADD0
99
JTAG_TDO
100
JTAG_TCK
1
JTAG_TDI
3
JTAG_TMS
95
TEST_JTAG
50
PHY_REF
80
PHY_SLEEP
81
PHY_RESET_N
83
PHY_PWR_GOOD
82
MODE_SEL
91
TXA_MINUS
90
TXA_PLUS
93
RXA_PLUS
94
RXA_MINUS
84
RXB_MINUS
85
RXB_PLUS
88
TXB_PLUS
87
TXB_MINUS
46
AVDD6
45
AVDD5
40
AVDD4
35
AVDD3
30
AVDD2
29
AVDD1
92
AVDDF1
86
AVDDF0
51
AVDDR1
24
AVDDR0
3
RESERVED14 RESERVED13 RESERVED12 RESERVED11 RESERVED10
RESERVED9 RESERVED8 RESERVED7 RESERVED6 RESERVED5 RESERVED4 RESERVED3 RESERVED2 RESERVED1 RESERVED0
PHY_CLK_OUT
XTAL1 XTAL2
CTRL_12 CTRL_18
LEDA_RX_ACTIVITY
LEDA_TX_ACTIVITY
LEDA_DUPLEX
LEDA_SPEED_1000
LEDA_SPEED_100
LEDA_ACTIVITY
LEDA_LINKUP
LINK_A
LEDB_RX_ACTIVITY
LEDB_TX_ACTIVITY
LEDB_DUPLEX
LEDB_SPEED_1000
LEDB_SPEED_100
LEDB_ACTIVITY
LEDB_LINKUP
LINK_B
DVDD7 DVDD6 DVDD5 DVDD4 DVDD3 DVDD2 DVDD1
DVDD0 VDDO4 VDDO3 VDDO2 VDDO1 VDDO0
VSS
GND
TQFL100_82563EB
U50
98 53 52 49 26 17 15 14 13 10 9 8 6 5
Place PHY_CLK_OUT series
4
termination close to Gilgal pin.
96 21
20 23
25
66 67 68 70 71 72 73 65
55 56 57 58 61 62 63 54
74 69 64 59 16 12 7 2 97 75 60 22 11
89 101
R778 40.2RST
PHY_CTRL12 PHY_CTRL18
R788 X_1K
LANA_1000# LANA_100# LANA_ACT# LANA_LINKUP# LAN_STRAP0
R792 X_1K
LANB_1000# LANB_100# LANB_ACT# LANB_LINKUP# LAN_STRAP1
TP37 TP78
TP83 TP100
P1V2LAN
P3V3_AUX
2
SK_LAN_CLK 40
Y4
PHY_CTRL12 49 PHY_CTRL18 49
LANA_1000# 48 LANA_100# 48 LANA_ACT# 48,49 LANA_LINKUP# 48,49
LANB_1000# 48 LANB_100# 48 LANB_ACT# 48,49 LANB_LINKUP# 48,49
Depop 10K ohms pull-ups when populating 0 ohm series resistors
C1070
27P
R790 X_0
25MHZ
P3V3_AUX
R3426 10K
P3V3_AUX
R3427 10K
EECS39 EEDO39
12
C1071 27P
ESB_LINK0 40
ESB_LINK1 40
P3V3_AUX
EECS EEDO EEWP#
P3V3_AUX
R815 3.3K R814 3.3K R813 3.3K R812 10K
R3425 3.3K R818 3.3K R819 3.3K R820 3.3K R821 3.3K R816 3.3K R822 4.99KST R823 10K R817 1K
LAN_STRAP0 LAN_STRAP1
LAN_TEST_JTAG
LAN_PU_TMS LAN_PU_TDI PHY_RST#
MDC MDIO_ADD3 MDIO_ADD2 MDIO_ADD1 MDIO_ADD0 LAN_PD_TCK PHY_REF
PHY_PWRDOWN
PHY_MODE_SEL
Ra
Ra Rb Rc
POP DEPOP POP
DEPOP
N/A N/A
LAN EEPROM
HOLD#
SCK
EECS EEDO EEWP# EEHOLD#
SI
P3V3_AUX
8 7 6 5
R3290 100K R3291 X_10K R1625 3.3K R1626 3.3K
U101
CS#1VCC
2
SO
3
WP#
4
GND
AT25256A
DEPOPPOPPOP
R797 10K
1
P3V3_AUX
EEHOLD# EESK EEDI
R789
Rb
X_10K
R793
Rc
10K
SK_LAN_CLK
62.5MHz (default) 25MHz Disable
EESK 39 EEDI 39
A A
Title Document Number
5
4
3
2
Micro Star Restricted Secret
LAN PHY Gilgal
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
47 90
Rev
0A
of
Page 48
5
4
3
2
1
LAN Connectors
D D
P1V8LAN
T3001
TCT1
MCT1
TD1+
MX1+
TD1-
MX1-
TCT2
MCT2
TD2+
MX2+
TD2-
MX2-
TCT3
MCT3
TD3+
MX3+
TD3-
MX3-
TCT4
MCT4
TD4+
MX4+
TD4-12MX4-
H5007
24
A_MDIN3
23
A_MDIP3
22 21
A_MDIN2
20
A_MDIP2
19 18
A_MDIN1
17
A_MDIP1
16 15
A_MDIN0
14
A_MDIP0
13
R3025 75RST
R3026 75RST
R3027 75RST
R3028 75RST
C3023
102P
C3022
0.1u
1 2 3 4 5 6 7 8
9 10 11
LAN_A_MDIN3 LAN_A_MDIP3
LAN_A_MDIN2 LAN_A_MDIP2
LAN_A_MDIN1 LAN_A_MDIP1
LAN_A_MDIN0 LAN_A_MDIP0
R3044
C C
R3042
49.9RST
C3100
0.1u
49.9RST
R3038
49.9RST
C3098
0.1u
R3040
49.9RST
R3034
49.9RST
C3096
0.1u
R3036
49.9RST
R3030
49.9RST
C3094
0.1u
R3032
49.9RST
C3016
0.1u
C3018
0.1u
C3021
0.1u
CHSGND
LAN1
13
1 2 3 4 5 6 7 8
14
AMP/108-57136
C3019
100P
C3024
1500P
C3015 120P
R3023 330
R3024 330
C3017 120P
11 12
9 10
C3014 120P
C3020 120P
LANA_LINKUP# LANA_ACT#
LANA_1000# LANA_100#
LANA_LINKUP# 47,49 LANA_ACT# 47,49
LANA_1000# 47 LANA_100# 47
470p-->120p Avoid LED Error
Place RC Termination Close to Gilgal
P1V8LAN
CHSGND
LAN2
13
1 2 3 4 5 6 7 8
14
AMP/108-57136
C3009
100P
C3013
1500P
C3004 120P
R3016 330
R3017 330
C3006 120P
11 12
9 10
C3003 120P
C3008 120P
LANB_LINKUP# LANB_ACT#
LANB_1000# LANB_100#
LANB_LINKUP# 47,49 LANB_ACT# 47,49
LANB_1000# 47 LANB_100# 47
470p-->120p Avoid LED Error
T3000
TCT1
MCT1
TD1+
MX1+
TD1-
MX1-
TCT2
MCT2
TD2+
MX2+
TD2-
MX2-
TCT3
MCT3
TD3+
MX3+
TD3-
MX3-
TCT4
MCT4
TD4+
MX4+
TD4-12MX4-
H5007
24
B_MDIN3
23
B_MDIP3
22 21
B_MDIN2
20
B_MDIP2
19 18
B_MDIN1
17
B_MDIP1
16 15
B_MDIN0
14
B_MDIP0
13
R3018
R3019
R3020
75RST
75RST
75RST
R3021 75RST
C3012
102P
C3011
0.1u
1
2
3
4
5
6
7
8
9 10 11
LAN_B_MDIN3 LAN_B_MDIP3
LAN_B_MDIN2 LAN_B_MDIP2
LAN_B_MDIN1
B B
LAN_B_MDIP1 LAN_B_MDIN0
LAN_B_MDIP0
R3043
49.9RST
C3101
0.1u
R3045
49.9RST
R3039
49.9RST
C3099
0.1u
R3041
49.9RST
R3035
49.9RST
C3097
0.1u
R3037
49.9RST
R3031
49.9RST
C3095
0.1u
R3033
49.9RST
C3005
0.1u
C3007
0.1u
C3010
0.1u
Place RC Termination Close to Gilgal
LAN_A_MDIP[3..0]47
A A
5
4
LAN_A_MDIN[3..0]47 LAN_B_MDIP[3..0]47 LAN_B_MDIN[3..0]47
LAN_A_MDIP[3..0] LAN_A_MDIN[3..0] LAN_B_MDIP[3..0] LAN_B_MDIN[3..0]
3
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
2
http://www.msi.com.tw
LAN Connectors
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
48 90
Rev
0A
of
Micro Star Restricted Secret
Page 49
5
4
LAN Voltage Regulator and Decoupling.
3
2
1
1R-1206
1
R794
1R-1206
R776
P3V3_AUX
P3V3_AUX
32
1
Q69
4
PNP-BCP69-S-SOT223
R777 1R-1206
32
Q70
4
PNP-BCP69-S-SOT223
R795 1R-1206
C3186 470p
C3178 470p
P1V8LAN
C3187 470p
C791
4.7u-1206
P1V2LAN
C3179 470p
C783
4.7u-1206
C3180
0.1u
C3188 470p
C3181
0.1u
C399
0.1u
C3189 470p
C400
0.1u
C3182
0.1u
C3190
0.1u
C3183
0.1u
C3191
0.1u
C3184
4.7u-1206
C3192
0.1u
C3193
0.1u
C3185
4.7u-1206
TC3004 X_100u/16V
C3194
4.7u-1206
C3195
4.7u-1206
TC3005 X_100u/16V
P3V3_AUX
R3046 1K
147
LANA_LINKUP#47,48
LANA_ACT#47,48
LANB_LINKUP#47,48
LANA_LINKUP#
LANA_ACT#
LANB_LINKUP#
1 2
P3V3_AUX
R3047 100
147
5 6
P3V3_AUX
R3048 1K
147
11 10
U3002A 74LVC07
U3002C 74LVC07
U3002E 74LVC07
LANA_ACT_C 67
LANA_ACT_A 67
LANB_ACT_C 67
D D
PHY_CTRL1247
C C
PHY_CTRL1847
B B
PHY_CTRL12
PHY_CTRL18
P3V3_AUX
R3049 100
2
147
13 12
U3002F 74LVC07
LANB_ACT_A 67
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
LAN Voltage Regulator and Decoupling
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
49 90
of
Rev
0A
Power Sequencing Provisiona
P1V2LAN
P1V8LAN
A A
5
P1V2LAN
D3016
A C
1N5817S
D3017
A C
1N5817S
D3018
A C
1N5817S
P3V3_AUX
P3V3_AUX
P1V8LAN
4
3
LANB_ACT#47,48
LANB_ACT#
Page 50
5
4
3
2
1
280 Pin PCI-X and PCI-E Slot
P-12V
P5V
B10 B11
B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49
B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70
B1 B2 B3 B4 B5 B6 B7 B8 B9
PXIRQ_N6
D D
PXPCLK337
PXREQ_N337
PXPCLK237
PXREQ_N237
PXPCLK037
PXREQ_N037
C C
PXIRDY_N37
PXDEVSEL_N37
PXPCIXCAP37 PXPLOCK_N37
PXPERR_N37 PXSERR_N37
PXM66EN37
B B
PXACK64_N37
PXIRQ_N1 PXIRQ_N3
PXAD31 PXAD29
PXAD27 PXAD25
PXCBE_N3 PXAD23
PXAD21 PXAD19
PXAD17 PXCBE_N2
PXIRDY_N PXDEVSEL_N
PXPCIXCAP PXPLOCK_N PXPERR_N
PXSERR_N PXCBE_N1
PXAD14 PXAD12
PXAD10 PXM66EN
PXAD8 PXAD7
PXAD5 PXAD3
PXAD1 PXACK64_N
PXCBE_N6 PXCBE_N4
PXAD63 PXAD61
PXAD59 PXAD57
P3V3
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49
B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70
PCI1A
PCIX+PCIE
A10 A11
A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49
A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70
P12V
P5V
A1
A1
A2
A2
A3
A3
A4
A4
A5
A5
A6
A6
A7
A7
A8
A8
A9
A9
A10 A11
A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49
A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70
P3V3
PXIRQ_N5 TDI
PXIRQ_N0 PXIRQ_N2
PXPCIRST_N_PCI1
PCI1_PME# PXAD30
PXAD28 PXAD26
PXAD24 PXIDSEL
PXAD22 PXAD20
PXAD18 PXAD16
PXFRAME_N PXTRDY_N PXSTOP_N
PXPAR PXAD15
PXAD13 PXAD11
PXAD9
PXCBE_N0 PXAD6
PXAD4 PXAD2
PXAD0 PXREQ64_N
PXCBE_N7 PXCBE_N5
PXPAR64 PXAD62
PXAD60 PXAD58
R521 4.7K
PXGNT_N3 37 PXGNT_N2 37
P3V3_AUX
PXGNT_N0 37
R3213 X_0 R3214 X_0 R3221 0
R1310 X_100 R1313 100
PXFRAME_N 37 PXTRDY_N 37 PXSTOP_N 37 SMBCLK_PCI 51,54
SMBDAT_PCI 51,54 PXPAR 37
PXREQ64_N 37
PXPAR64 37
P3V3
PE_WAKE# PME_N
PXAD24 PXAD19
PXPME_N 37
PME_N 38
SMBCLK_PCI51,54 SMBDAT_PCI51,54
PE_WAKE#38,40,51
ESB_EXP1_TXP036 ESB_EXP1_TXN036
ESB_EXP1_TXP136 ESB_EXP1_TXN136
ESB_EXP1_TXP236 ESB_EXP1_TXN236
ESB_EXP1_TXP336 ESB_EXP1_TXN336
ESB_EXP2_TXP036 ESB_EXP2_TXN036
ESB_EXP2_TXP136 ESB_EXP2_TXN136
ESB_EXP2_TXP236 ESB_EXP2_TXN236
ESB_EXP2_TXP336 ESB_EXP2_TXN336
INTRUSION_N39,54,65
PXAD55 PXAD53
PXAD51 PXAD49
PXAD47 PXAD45
PXAD43 PXAD41
PXAD39 PXAD37
PXAD35 PXAD33
P3V3_AUX
PE_WAKE#
P3V3
P12V
B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82 B83 B84 B85 B86 B87 B88 B89 B90 B91 B92 B93 B94 B95 B96 B97 B98
B99 B100 B101 B102 B103 B104 B105 B106 B107 B108 B109 B110 B111 B112 B113 B114 B115 B116 B117 B118 B119 B120 B121 B122 B123 B124 B125 B126 B127 B128 B129 B130 B131 B132 B133 B134 B135 B136 B137 B138 B139 B140
B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82 B83 B84 B85 B86 B87 B88 B89 B90 B91 B92 B93 B94 B95 B96 B97 B98 B99 B100 B101 B102 B103 B104 B105 B106 B107 B108 B109 B110 B111 B112 B113 B114 B115 B116 B117 B118 B119 B120 B121 B122 B123 B124 B125 B126 B127 B128 B129 B130 B131 B132 B133 B134 B135 B136 B137 B138 B139 B140
PCI1B
A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84 A85 A86 A87 A88 A89 A90 A91 A92 A93 A94 A95 A96 A97 A98
A99 A100 A101 A102 A103 A104 A105 A106 A107 A108 A109 A110 A111 A112 A113 A114 A115 A116 A117 A118 A119 A120 A121 A122 A123 A124 A125 A126 A127 A128 A129 A130 A131 A132 A133 A134 A135 A136 A137 A138 A139 A140
PCIX+PCIE
A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84 A85 A86 A87 A88 A89 A90 A91 A92 A93 A94 A95 A96 A97 A98 A99 A100 A101 A102 A103 A104 A105 A106 A107 A108 A109 A110 A111 A112 A113 A114 A115 A116 A117 A118 A119 A120 A121 A122 A123 A124 A125 A126 A127 A128 A129 A130 A131 A132 A133 A134 A135 A136 A137 A138 A139 A140
P3V3
P12V
PXAD56 PXAD54
PXAD52 PXAD50
PXAD48 PXAD46
PXAD44 PXAD42
PXAD40 PXAD38
PXAD36 PXAD34
PXAD32
SYS_PWRGD_3_3V
PCI1_GPI1
PCI1_GPI0 0 1 01
PCI1_GPI1 45 PCI1_GPI0 45
SPECFG 37 PCI1_100CLK_P1 60
PCI1_100CLK_N1 60
PCIE_RST# 51,63
PCI1_100CLK_P0 60 PCI1_100CLK_N0 60
ESB_EXP1_RXP0 36 ESB_EXP1_RXN0 36
ESB_EXP1_RXP1 36 ESB_EXP1_RXN1 36
ESB_EXP1_RXP2 36 ESB_EXP1_RXN2 36
ESB_EXP1_RXP3 36 ESB_EXP1_RXN3 36
ESB_EXP2_RXP0 36 ESB_EXP2_RXN0 36
ESB_EXP2_RXP1 36 ESB_EXP2_RXN1 36
ESB_EXP2_RXP2 36 ESB_EXP2_RXN2 36
ESB_EXP2_RXP3 36 ESB_EXP2_RXN3 36
RAISER
0
No PCI
0
1 PCI 2 PCI 3 PCI
11
R1670 0
P3V3
U104
VCC
PXPCIRST_N37
A A
5
4
3
SYS_PWRGD_3_3V20,35,37,40,63,77
SYS_PWRGD_3_3V
1 2 3
GND
X_74LVC1G08
2
5 4
PXPCIRST_N_PCI1
R1671 10K
PXIRQ_N[6..0] PXAD[63..0] PXCBE_N[7..0]
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
PXIRQ_N[6..0] 37 PXAD[63..0] 37 PXCBE_N[7..0] 37
280 Pin PCI-X and PCI-E Slot
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
of
50 90
Rev
0A
Page 51
5
4
3
2
1
PCI Express X8 Slots
D D
PCIE1
PCI-E 8PORT
B10 B11
B12 B13 B14 B15 B16 B17 B18
B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32
B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49
B1 B2 B3 B4 B5 B6 B7 B8 B9
12V 12V RSVD GND SMCLK SMDATA GND
3.3V JTAG1
3.3VAUX WAKE_#
RSVD GND PETP0 PETN0 GND PRSNT2_# GND
PETP1 PETN1 GND GND PETP2 PETN2 GND GND PETP3 PETN3 GND RSVD PRSNT2_# GND
PETP4 PETN4 GND GND PETP5 PETN5 GND GND PETP6 PETN6 GND GND PETP7 PETN7 GND PRSNT2_# GND
PCI-E 8PORT
PRSNT1_#
P12V
SMBCLK_PCI50,54 SMBDAT_PCI50,54
P3V3
P3V3_AUX
PE_WAKE#38,40,50
MCH_EXP4_TXP019
C C
B B
MCH_EXP4_TXN019
MCH_EXP4_TXP119 MCH_EXP4_TXN119
MCH_EXP4_TXP219 MCH_EXP4_TXN219
MCH_EXP4_TXP319 MCH_EXP4_TXN319
MCH_EXP5_TXP019 MCH_EXP5_TXN019
MCH_EXP5_TXP119 MCH_EXP5_TXN119
MCH_EXP5_TXP219 MCH_EXP5_TXN219
MCH_EXP5_TXP319 MCH_EXP5_TXN319
PE_WAKE#
MCH_EXP4_TXN0
MCH_EXP4_TXP1 MCH_EXP4_TXN1
MCH_EXP4_TXP2 MCH_EXP4_TXN2
MCH_EXP4_TXP3 MCH_EXP4_TXN3
MCH_EXP5_TXP0 MCH_EXP5_TXN0
MCH_EXP5_TXP1 MCH_EXP5_TXN1
MCH_EXP5_TXP2 MCH_EXP5_TXN2
MCH_EXP5_TXP3 MCH_EXP5_TXN3
12V 12V
GND JTAG2 JTAG3 JTAG4 JTAG5
3.3V
3.3V
PERST#
GND
REFCLK+
REFCLK-
GND
PERP0 PERN0
GND
RSVD
GND
PERP1 PERN1
GND
GND
PERP2 PERN2
GND
GND
PERP3 PERN3
GND
RSVD
RSVD
GND
PERP4 PERN4
GND
GND
PERP5 PERN5
GND
GND
PERP6 PERN6
GND
GND
PERP7 PERN7
GND
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
A12 A13 A14 A15 A16 A17 A18
A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32
A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49
P12V
P3V3
PCIE_RST#
PCIE1_100CLK_P0 PCIE1_100CLK_N0MCH_EXP4_TXP0
MCH_EXP4_RXP0 MCH_EXP4_RXN0
MCH_EXP4_RXP1 MCH_EXP4_RXN1
MCH_EXP4_RXP2 MCH_EXP4_RXN2
MCH_EXP4_RXP3 MCH_EXP4_RXN3
MCH_EXP5_RXP0 MCH_EXP5_RXN0
MCH_EXP5_RXP1 MCH_EXP5_RXN1
MCH_EXP5_RXP2 MCH_EXP5_RXN2
MCH_EXP5_RXP3 MCH_EXP5_RXN3
PEWIDTH_0 19
PCIE_RST# 50,63
PCIE1_100CLK_P0 60 PCIE1_100CLK_N0 60
MCH_EXP4_RXP0 19 MCH_EXP4_RXN0 19
MCH_EXP4_RXP1 19 MCH_EXP4_RXN1 19
MCH_EXP4_RXP2 19 MCH_EXP4_RXN2 19
MCH_EXP4_RXP3 19 MCH_EXP4_RXN3 19
MCH_EXP5_RXP0 19 MCH_EXP5_RXN0 19
MCH_EXP5_RXP1 19 MCH_EXP5_RXN1 19
MCH_EXP5_RXP2 19 MCH_EXP5_RXN2 19
MCH_EXP5_RXP3 19 MCH_EXP5_RXN3 19
P12V
SMBCLK_PCI SMBDAT_PCI
P3V3
P3V3_AUX
PE_WAKE#
MCH_EXP6_TXP019 MCH_EXP6_TXN019
MCH_EXP6_TXP119 MCH_EXP6_TXN119
MCH_EXP6_TXP219 MCH_EXP6_TXN219
MCH_EXP6_TXP319 MCH_EXP6_TXN319
MCH_EXP7_TXP019 MCH_EXP7_TXN019
MCH_EXP7_TXP119 MCH_EXP7_TXN119
MCH_EXP7_TXP219 MCH_EXP7_TXN219
MCH_EXP7_TXP319 MCH_EXP7_TXN319
MCH_EXP6_TXP0 MCH_EXP6_TXN0
MCH_EXP6_TXP1 MCH_EXP6_TXN1
MCH_EXP6_TXP2 MCH_EXP6_TXN2
MCH_EXP6_TXP3 MCH_EXP6_TXN3
MCH_EXP7_TXP0 MCH_EXP7_TXN0
MCH_EXP7_TXP1 MCH_EXP7_TXN1
MCH_EXP7_TXP2 MCH_EXP7_TXN2
MCH_EXP7_TXP3 MCH_EXP7_TXN3
B10 B11
B12 B13 B14 B15 B16 B17 B18
B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32
B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49
B1 B2 B3 B4 B5 B6 B7 B8 B9
PCIE2
PCI-E 8PORT
PCI-E 8PORT
12V 12V RSVD GND SMCLK SMDATA GND
3.3V JTAG1
3.3VAUX WAKE_#
RSVD GND PETP0 PETN0 GND PRSNT2_# GND
PETP1 PETN1 GND GND PETP2 PETN2 GND GND PETP3 PETN3 GND RSVD PRSNT2_# GND
PETP4 PETN4 GND GND PETP5 PETN5 GND GND PETP6 PETN6 GND GND PETP7 PETN7 GND PRSNT2_# GND
PRSNT1_#
12V 12V
GND JTAG2 JTAG3 JTAG4 JTAG5
3.3V
3.3V
PERST#
GND
REFCLK+
REFCLK-
GND
PERP0 PERN0
GND
RSVD
GND
PERP1 PERN1
GND
GND
PERP2 PERN2
GND
GND
PERP3 PERN3
GND
RSVD
RSVD
GND
PERP4 PERN4
GND
GND
PERP5 PERN5
GND
GND
PERP6 PERN6
GND
GND
PERP7 PERN7
GND
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
A12 A13 A14 A15 A16 A17 A18
A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32
A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49
P12V
P3V3
PCIE_RST#
PCIE2_100CLK_P0 PCIE2_100CLK_N0
MCH_EXP6_RXP0 MCH_EXP6_RXN0
MCH_EXP6_RXP1 MCH_EXP6_RXN1
MCH_EXP6_RXP2 MCH_EXP6_RXN2
MCH_EXP6_RXP3 MCH_EXP6_RXN3
MCH_EXP7_RXP0 MCH_EXP7_RXN0
MCH_EXP7_RXP1 MCH_EXP7_RXN1
MCH_EXP7_RXP2 MCH_EXP7_RXN2
MCH_EXP7_RXP3 MCH_EXP7_RXN3
PCIE1_100CLK_P1 60 PCIE1_100CLK_N1 60
PCIE_RST# 50,63
PCIE2_100CLK_P0 60 PCIE2_100CLK_N0 60
MCH_EXP6_RXP0 19 MCH_EXP6_RXN0 19
MCH_EXP6_RXP1 19 MCH_EXP6_RXN1 19
MCH_EXP6_RXP2 19 MCH_EXP6_RXN2 19
MCH_EXP6_RXP3 19 MCH_EXP6_RXN3 19
MCH_EXP7_RXP0 19 MCH_EXP7_RXN0 19
MCH_EXP7_RXP1 19 MCH_EXP7_RXN1 19
MCH_EXP7_RXP2 19 MCH_EXP7_RXN2 19
MCH_EXP7_RXP3 19 MCH_EXP7_RXN3 19
A A
Title Document Number
5
4
3
2
Micro Star Restricted Secret
PCI Express x8 Slots
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
51 90
1
Rev
0A
of
Page 52
5
4
3
2
1
PCI Decoupling Cap.
D D
PCI 3.3V Decoupling Caps.
P3V3
EC31 1000u-6.3V
C3143
0.1u
12
C3138
0.1u
+
EC3007 1000u-6.3V
C3139
0.1u
12
+
EC3008 1000u-6.3V
C3140
0.1u
C3141
0.1u
C3132
0.1u
C3142
0.1u
C3133
0.1u
C3144
0.1u
C3134
0.1u
C3145
0.1u
C3135
0.1u
C3146
0.1u
C3136
0.1u
C3137
0.1u
12
+
EC3011 1000u-6.3V
12
+
P3V3
C C
PCI 5V Decoupling Caps.
P5V
EC3009 1000u-6.3V
12
+
EC3010 1000u-6.3V
C3147
0.1u
C3148
0.1u
12
+
C3149
0.1u
C3150
0.1u
C3151
0.1u
PCI 12V Decoupling Caps.
P12V
EC3012 330u/16V
12
+
EC3013 330u/16V
12
+
EC3014 330u/16V
C654
0.1u
12
+
C655
0.1u
C656
0.1u
C657
0.1u
C658
0.1u
SAS 3.3V Decoupling Caps.
PCI 3.3V AUX Decoupling Caps.
P3V3
P3V3_AUX
B B
12
+
EC3015 1000u-6.3V
C3152
0.1u
C3153
0.1u
C3154
0.1u
C3155
0.1u
C3156
0.1u
P3V3
C695
0.1u
C698
0.1u
C700
0.1u
C703
0.1u
C705
0.1u
C708
0.1u
C710
0.1u
C713
0.1u
C715
0.1u
C718
0.1u
C720
0.1u
C723
0.1u
C725 10u-1206
C728 10u-1206
A A
Title Document Number
5
4
3
2
Micro Star Restricted Secret
PCI Decoupling Cap.
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
52 90
1
Rev
0A
of
Page 53
5
U54A
SIO_PCLK LFRAME# SERIRQ
R1416 X_0_0402
C473 X_10p
AA13 AA16 AA15
AB17
AA17
AB14 AB15
J21 J22
L21 L22
D22
E20 E21
H17
F16
G18
Y18 Y13
U13 U15 U14 U16
Y17
V15 W17 W14
W12 W15
Y14
Y15
V13
U12
U1 P3 R3 N3 P6
A15
A14
B11
A11
R20
PCIE_CLKN PCIE_CLKP
PCIE_RXN PCIE_RXP
SIO_LRESET_N SIO_LPCCLK SIO_LFRAME_N SIO_SERIRQ SIO_SCI_N SIO_SMI_N
MA_0 MA_1 MA_2 MA_3 MA_4 MA_5 MA_6 MA_7 MA_8 MA_9 MA_10 MA_11 MA_12 MA_13
BNK_1 BNK_0
RAS_N CS_N CAS_N WE_N CKE
CLKP CLKN
MAC0_REF_CLK MAC0_RX_DV MAC0_RX_ER MAC0_RXD_0 MAC0_RXD_1
GFX_DDC_SDA GFX_DDC_SDC
GFX_VREF
RSET
USBCLK
PILOT2
P3V3
PILOT_100CLK_N60
PILOT_100CLK_P60
ESB_EXP0_TXN036
PLTRST_BUFF1#45,63,67
D D
P3V3_AUX
R1114 4.7K_0402 R1321 4.7K_0402 R1115 X_4.7K_0402
C C
P3V3_AUX
3
LM385M3-1.2
P3V3_AUX P3V3_AUX
R1501
4.7K
1
B B
BMC_SMI_OUT_N BMC_SCI_OUT_N
R1545 1K
Q119
1
+
3
2
-
OE GND2OUT+
USBP0N USBP0P USBP1N USBP1P
R1543
OSC2
VDD
48MHZ
X_15K
BMC_SCI_OUT_N39 BMC_SMI_OUT_N40
SERIRQ
ETH_REFCLK57 ETH_RXDV57 ETH_RXER57 ETH_RXD057 ETH_RXD157
R1542
4 3
DDC_SDA54 DDC_SDC54
X_15K
LFRAME#40,45,67
C1465
0.1u
SIO_PCLK58 SERIRQ38,45
R1532
R1497
15K
R603 0
DDR2_MA0 DDR2_MA1 DDR2_MA2 DDR2_MA3 DDR2_MA4 DDR2_MA5 DDR2_MA6 DDR2_MA7 DDR2_MA8 DDR2_MA9 DDR2_MA10 DDR2_MA11 DDR2_MA12 DDR2_MA13
DDR2_BNK1 DDR2_BNK0
DDR2_RAS_N DDR2_CS_N DDR2_CAS_N DDR2_WE_N DDR2_CKE
DDR2_CLKP DDR2_CLKN
ETH_REFCLK ETH_RXDV ETH_RXER ETH_RXD0 ETH_RXD1
DDC_SDA DDC_SDC
DAC_VREF
R1546 2.21KST
C3025
0.1u
33
R1533
15K
USB (1.1)
USB (2.0)
C3472 10uF
PCI EXPRESS
PCIE_TXN PCIE_TXP
SIO LPC
SIO_LAD_0 SIO_LAD_1 SIO_LAD_2 SIO_LAD_3
DDR2
DQSN_0 DQSP_0
DM_0 DQ_0 DQ_1 DQ_2 DQ_3 DQ_4 DQ_5 DQ_6 DQ_7 DQ_8
DQ_9 DQ_10 DQ_11 DQ_12 DQ_13 DQ_14 DQ_15
DM_1
DQSN_1 DQSP_1
DDR_COMP_PD
DDR_VREF
ODT
RMII
MAC_MDC
MAC_MDIO
MAC0_TX_EN MAC0_TXD_0 MAC0_TXD_1
GFX_VSYNC GFX_HSYNC
RGB
GFX_RED
GFX_GREEN
GFX_BLUE
IORET_CUR_BLUE
IORET_CUR_GREEN
IORET_CUR_RED
USB0_D_N USB0_D_P
USB0_DISCON
USB1_D_N
USB1_RSDM
USB1_RPU USB1_D_P
USB1_RSDP
CK_48M_PILOT 58
C3430
C3431
0.1u
0.1u
G21 G22
G19 F20 F19 H18
AB10 AB11 AA11 W11 AB12 AA12 V11 U11 W10 U10 V9 W8 Y9 AA8 Y6 U9 Y7 U8 V7 W7 AB6 AB7
W16
Y10 Y11
AB5 AA5
P5 P2 R2
A16 F14
B13 C12 C13
F13 E12 D13
N18 N17 T22
M17 N20
L18 M18 M19
Place Resistors Close to PILOT
P3V3_AUX
R3435 X_4.7K
2 1
B
P5VSB
P5VSB
53
U126 7S14_SOT23-5
R3434 X_1K
Q3035 X_MMBT3904
E C
4
P3V3_AUX
R3322
USB_DISCON
A A
1K
5
R3321 1K
DS
Q3032 BSS138
G
SOT23SGD
USBP0P
4
PILOT_EXP0_TXN0 PILOT_EXP0_TXP0
USB_DISCON
USB7_RSDM
USB7_RSDP
LAD0 LAD1 LAD2 LAD3
DDR2_DQSN0 DDR2_DQSP0 DDR2_DM0 DDR2_DQ0 DDR2_DQ1 DDR2_DQ2 DDR2_DQ3 DDR2_DQ4 DDR2_DQ5 DDR2_DQ6 DDR2_DQ7 DDR2_DQ8 DDR2_DQ9 DDR2_DQ10 DDR2_DQ11 DDR2_DQ12 DDR2_DQ13 DDR2_DQ14 DDR2_DQ15 DDR2_DM1 DDR2_DQSN1 DDR2_DQSP1
R775 150RST
DDR2_VREF DDR2_ODT
ETH_MDC ETH_MDIO
ETH_TXEN
R834 20 R835 20
VSY HSY
RED GREEN BLUE
R1527 24 R1528 24
C1515 0.1u C1494 0.1u
LAD0 40,45,67 LAD1 40,45,67 LAD2 40,45,67 LAD3 40,45,67
ETH_TXD0 ETH_TXD1
R831 39.2RST_0402 R827 1.5K_0402 R826 39.2RST_0402
Place Resistors Close to PILOT
C3432 X_0.1u
P5V
B1
CP1
MONSCL RVSYNC_N RHSYNC_N MONSDA
4
X_80ohm-700mA
X_COPPER
ESB_EXP0_RXN0 36 ESB_EXP0_RXP0 36ESB_EXP0_TXP036
P1V8_AUX
C62 0.1u
ETH_MDC 57 ETH_MDIO 57
ETH_TXEN 54,57 ETH_TXD0 54,57 ETH_TXD1 54,57
USBP0N
USBP0N 40
USBP0P
USBP0P 40 USB_DISCON 40
USBP1N
USBP1N 40
USBP1P
USBP1P 40
F3003 X_1.1A6V
VGA Connector
16
15 10 14
9
13
8
12
7
11
6
VGA1 N51-15F0471-F02
5 4 3 2 1
17
HSY
VSY
CRT_BLUE CRT_GREEN CRT_RED
R844
4.7K
R852
4.7K
1 2 3
1 2 3
U3048
GND
NC7S08
U3049
GND
NC7S08
Place resistor close to DDR
P1V8_AUX
VCC
5 4
VCC
5 4
R3218
75RST
GREEN
R3219 75RST
BLUE
R3220 75RST
3
3
DDR2_CLKP
DDR2_CLKN
P5VP3V3
R845
2.2K
P5VP3V3
R853
2.2K
FB28
80_600mA
P5V
P5V
C1093 22P
C1096 22P
C1098 22P
R824 200
C64
0.1u
C63
0.1u
D19 1PS226_SOT23
2
3
D21 1PS226_SOT23
2
3
P5V
FB7
30ohm-600mA
P5V
FB8
30ohm-600mA
P5V
FB9
30ohm-600mA
32M x 16 DDR2
DDR2_MA0 DDR2_MA1 DDR2_MA2 DDR2_MA3 DDR2_MA4 DDR2_MA5 DDR2_MA6 DDR2_MA7 DDR2_MA8 DDR2_MA9 DDR2_DQ9 DDR2_MA10 DDR2_MA11 DDR2_MA12
DDR2_BNK0 DDR2_BNK1
DDR2_CKE DDR2_RAS_N
DDR2_CAS_N DDR2_WE_N DDR2_CS_N
DDR2_ODT
DDR2_DM0 DDR2_DM1
DDR2_DQSP0 DDR2_DQSN0
DDR2_DQSP1 DDR2_DQSN1
DDR2_VDDL
C401 22u-1206
1
R846
RHSYNC_N
100RST
1
R855
RVSYNC_N
100RST
D16 1PS226_SOT23
1
2
3
CRT_REDRED
C1094 15P
D17 1PS226_SOT23
1
2
3
CRT_GREEN
C1097 15P
D18 1PS226_SOT23
1
2
3
CRT_BLUE
C1099 15P
U82
M8
A0
M3
A1
M7
A2
N2
A3
N8
A4
N3
A5
N7
A6
P2
A7
P8
A8
P3
A9
M2
A10
P7
A11
R2
A12
L2
BA0
L3
BA1
J8
CK
K8
CK#
K2
CKE
K7
RAS#
L7
CAS#
K3
WE#
L8
CS#
L1
RFU1
R3
RFU2
R7
RFU3
R8
RFU4
K9
ODT
A2
NC1
E2
NC2
F3
LDM
B3
UDM
F7
LDQS
E8
LDQS#/NU
B7
UDQS
A8
UDSQS#/NU
J2
VREF
J1
VDDL
J7
VSSDL
DDR2_84FBGA_x16
P5V P5V
DLL pwr
R77 1K-0402
1.8V
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
VDD1 VDD2 VDD3 VDD4 VDD5
VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9
VDDQ10
VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9
VSSQ10
VSS1 VSS2 VSS3 VSS4 VSS5
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9
R78 1K-0402
G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9
A1 E1 J9 M9 R1
A9 C1 C3 C7 C9 E9 G1 G3 G7 G9
A7 B2 B8 D2 D8 E7 F2 F8 H2 H8
A3 E3 J3 N1 P9
MONSDA
MONSCL
2
P3V3_AUX
2
DDR2_DQ0 DDR2_DQ1 DDR2_DQ2 DDR2_DQ3 DDR2_DQ4 DDR2_DQ5 DDR2_DQ6 DDR2_DQ7 DDR2_DQ8
DDR2_DQ10 DDR2_DQ11 DDR2_DQ12 DDR2_DQ13 DDR2_DQ14 DDR2_DQ15
P1V8_AUX
PILOT DDR2 VTT Power
P1V8_AUX
U9
9 8 7 6 5
W83310DS_SOIC8
MONSDA 54
MONSCL 54
NC VREF2 ENABLE VCNTL BOOT_SEL
GND
VREF1
VOUT
1
VIN
2 3 4
DDR2 TERMINATION ADDR/CMD PLACE CLOSE TO DDR CHIP
DDR2_VTT
RN20
C402
0.1u 8P4R-47
RN21
C403
0.1u 8P4R-47
RN22
C404
0.1u 8P4R-47
RN23
C405
0.1u 8P4R-47
RN24
C406
0.1u 8P4R-47
RN25
C407
0.1u 8P4R-47
DDR2_VTTDDR2_VREF
P1V8_AUX
R709 1KST_0402
+
R710
EC2
1KST_0402
100u-16V
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
DDR2_VTT
DDR2_VREF
Micro Star Restricted Secret
PILOT2 PCI-E/LPC/VAG/DDR2
1
DDR2_CAS_N
12
DDR2_MA9
34
DDR2_MA12
56
DDR2_MA7
78
DDR2_CS_N
12
DDR2_MA2
34
DDR2_MA0
56
DDR2_MA6
78
DDR2_BNK0
12
DDR2_BNK1
34
DDR2_CKE
56
DDR2_WE_N
78
DDR2_MA5
12
DDR2_MA3
34
DDR2_MA10
56
DDR2_MA1
78
DDR2_MA4
12
DDR2_MA8
34
DDR2_MA11
56
DDR2_MA13
78
12 34
DDR2_RAS_N
56
DDR2_ODT
78
C408 22u-1206
12
+
EC9 1000u-6.3V
MS-9192
Last Revision Date:
Wednesday, May 02, 2007
Sheet
1
of
53 90
Rev
0A
Page 54
5
J_BMC_SEL
R3430 10K
1
BMC_SEL_N
2
R3431 51
3
N31-1030011-H06
J_BMC_SEL_1-1 N33-1020331-H06
D D
SGPIO_CLK SGPIO_LOAD SGPIO_DIN SGPIO_DOUT
LM285M3-2.5
P3V3_AUX
R3146X_1K R3294X_1K
R31335.6K R31345.6K R31355.6K R31365.6K R32225.6K R32235.6K R32245.6K R32255.6K R32855.6K R32865.6K R32875.6K R32885.6K
AIN_P5V
R3295X_1K R3296X_1K
C1455 47P
C C
P3V3_AUX
B B
A A
P3V3_AUX
PS_ALERT_N68 FSB0_TTL_IERR#62 FSB1_TTL_IERR#62
ESB_SYS_RST#9,40,67,68
THERM_PRE_SET#61
SYS_RESET_N63
J3004
1
1
2
2
3
3
4
4
5
5
X_MOLEX-0520
P3V3_AUX
+
Q120
3
3
-
SMBDAT_IPMB68 SMBCLK_IPMB68
SMBDAT_PCI50,51 SMBCLK_PCI50,51 SMBDAT_HM65,66 SMBCLK_HM65,66
SGPIO_DIN67
SGPIO_CLK SGPIO_LOAD SGPIO_DOUT SGPIO_DIN
SMBCLK_PCI SMBDAT_PCI SMBCLK_HM SMBDAT_HM SMBCLK_PS SMBDAT_PS SMBCLK_IPMB SMBDAT_IPMB SMBCLK_FBD SMBDAT_FBD SMBCLK_BF SMBDAT_BF
VSB_PWRGD_PILOT55,57
PS_PWROK_BUF58,68,75
SLP_S3_N40 SLP_S4_N40
BMC_PWREQ_N40
INTRUSION_N39,50,65
R1526
5.1KST
AIN_P12V
R1531
3.57KST
P1V8_AUX P1V8 P_VTT
C3223 47P
5
BMC_SEL_N
R1137 0_0402 R1136 X_0_0402
FAN_SELECT
NMI_BTN_N68
ID_BTN_N68
BMC_SMI_IN_N
BMC_NMI40
FRB3_PILOT_N SPI_WE# FORCE_MODE_N SPI_RST#
AIN_P3V3_AUX
P1V8_AUX
AIN_P12V AIN_P5V AIN_P3V3
R4150
AVREFP
1
C1589
0.1u
2
SMBDAT_IPMB SMBDAT_PS SMBCLK_IPMB SMBDAT_PCI SMBCLK_PCI SMBDAT_HM SMBCLK_HM
SGPIO_DIN
ARM_LFRAME# ARM_LAD1#
R1226 X_4.7K_0402
BMC_BT_SPI_DI
BMC_BKUP_SPI_DI
R3292 0
R3314 X_0
R1683 1M
VBAT
R1688 X_1M
P3V3_AUX
P12V
R1525
5.1KST
AIN_P3V3
C1454
R1530
47P
1.05KST
C3276
C3277
47P
47P
N5 N6
T3
U5
P4
U2
T5 U3 R4
W5
V1
V2
V5 R5 U4
AA3 A10
F11
R16794.7K
D11
R16804.7K
A9
E11
B9 C9
D10
A6
B6 D8
J6
B1 H3 H4
E1 C1
C21
C4 H6
E2 G3
Y21
AA22
E4
V21
B19 B18 F15
F5
P3V3 P3V3_AUXP5V
C1458 47P
U54B
GPIO
GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15
ANALOG
AVIN_0 AVIN_1
VOLTAGE
AVIN_2
MONITOR
AVIN_3 AVIN_4 AVIN_5 AVIN_6
ADC_AVREFP1 TEMP_AVREFP1
THERMAL SENSOR
ADC_AVREFN TEMP_AVREFN2
UART4_TXD/SDA_0 UART4_RXD/SDC_0 SDA_1
I2C BUSES
SDC_1 SDA_2 SDC_2
SGPIO_DIN
SERIAL GPIO
KBDCLK KBDATA
ARM LPC ROM
BMCLPC_LCLKG5BMCLPC_LAD_0 BMCLPC_LFRAMEn BMCLPC_LRESETn
SPI INTERFACE A
BMCBOOT_SPIDI
SPI INTERFACE B
BMCBKUP_SPIDI VSB_PWRGD
VDD_PWRGOOD
ACPI POWER CNTL
SIO_SLPS3n SIO_SLPS5n SIO_PWRREQn
CHASIn
MISC
PILOT2
R1534
5.1KST
R1537
8.06KST
4
JTAGM_TCK/GPIO_16 JTAGM_TMS/GPIO_17 JTAGM_TDO/GPIO_18
JTAGM_TDI/GPIO_19 HSTSPI_DIN/GPIO_20 HSTSPI_DO/GPIO_21
HSTSPI_CLK/GPIO_22 HSTSPI_CSn/GPIO_23 MAC1_TXEN/GPIO_24 MAC1_TXD1/GPIO_25 MAC1_TXD0/GPIO_26 MAC1_RXD1/GPIO_27 MAC1_RXD0/GPIO_28 MAC1_RXDV/GPIO_29 MAC1_RXER/GPIO_30
MAC1_REFCLK/GPIO_31
AVIN_7 AVIN_8
AVIN_9 AVIN_10 AVIN_11
AVIN_BAT_15
TEMPIN_0_N TEMPIN_0_P
TEMPIN_1_N TEMPIN_1_P
TEMPIN_2_N TEMPIN_2_P
SDA_3 SDC_3 SDA_4 SDC_4 SDA_5 SDC_5
SGPIO_CLK
SGPIO_DOUT
SGPIO_LD
KB/MS
MOUSECLK
MOUSEDATA
BMCLPC_LAD_1 BMCLPC_LAD_2 BMCLPC_LAD_3
BMCBOOT_SPICLK BMCBOOT_SPICSn
BMCBOOT_SPIDO
BMCBKUP_SPICLK BMCBKUP_SPICSn
BMCBKUP_SPIDO
POWER GOODS
SIO_ONCTLn
SIO_PWRTINn
SIO_PWRBTOUTn
SIO_WATCHDOG
ICMB_TX_EN
BMC_WATCHDOG
P5VSB
R3316
5.1KST
AIN_P3V3_AUXAIN_P5VSB
R3318
3.57KST
C3222 47P
AIN_P-12V
3
12
D32 X_BAT54S
4
V3 W2 R6 V4 W3 T6 Y1 Y2 AA1 AA2 AB2 U6 V6 AA4 AB3 Y4
B10 A8 E10 C10 A7 B8
D9 B5
C5 E8
E7 A2
J5 F1 J4 H5 K5 J3
E16 C19 C18
B3 B2
F4 F3 G6 F2
AB20 AA20 AB21
W20 Y22 Y20
D20 C16 C15
D21 B14 C14
C1459 47P
C1453 X_47P-0402
RN36
1 2 3 4 5 6 7 8
8P4R-0
AIN_P5VSB
R1521 4.7K
R3358 499RST
R3359 499RST
R3361 499RST
SMBCLK_PS SMBDAT_BF SMBCLK_BF SMBDAT_FBD SMBCLK_FBD
SGPIO_CLK SGPIO_DOUT SGPIO_LOAD
R_MSCLKR_KBCLK R_MSDATAR_KBDATA
ARM_LAD0# ARM_LAD2#
ARM_LAD3# BMC_BT_SPI_CLK
BMC_BT_SPI_CS# BMC_BT_SPI_DO
BMC_BKUP_SPI_CLK BMC_BKUP_SPI_CS# BMC_BKUP_SPI_DO
ICM_TX_EN# BMC_WDO
R1535
5.1KST
R1538
8.06KST
P-12V
R1524 X_21.82K-0402
R1529 X_5K-0402
P3V3
BMC_SCI_N 40 RST_REQ_N 40 SYS_ID_LED_N 67 THERMTRIP0_N 61 THERMTRIP1_N 61 SYSRDY_LED 67 SYS_FLT_LED 67 COOL_FLT_LED 67 TPM_DISABLE 45
CPU0_SKTOCC# 9,62,63,65 CPU1_SKTOCC# 12,63,65 CPU0_DISABLE_N 9,65 CPU1_DISABLE_N 12,65
P1V5 P_VTT P1V8
AIN_P5VSB 65
SMBDAT_PS 67,68 SMBCLK_PS 67,68 SMBDAT_BF 20 SMBCLK_BF 20 SMBDAT_FBD 17 SMBCLK_FBD 17
SGPIO_CLK 67 SGPIO_DOUT 67 SGPIO_LOAD 67
ONCTL# 68 PWR_BT_IN# 67,68 PWR_BT_SSI_# 40
VBAT_HM
Pull Down Unused AIN
J_FANSEL
J_FRB3
2 - 3
J_FORCE_MODE 1 - 2 Normal (default)
FSB_SMI#9,12,40
DDC_SDA53 DDC_SDC53
PS_PWRGD_N55,63,68
3
D S
2N7002
SOT23SGD
1-2 2-3
P12V
G
Q65
R1408
1K_0402
C972
0.1u_0402
FAN Select None Option Fan Full Fan
Normal (default)1 - 2 Disable
P3V3_AUX
P3V3_AUX
Q12
G1
G1
S1
S1
G2
G2
S2
S2
NTZD3154N
R1406
49.9KST_0402
R1407
84.5KST_0402
R3429 1K
FAN_SELECT
FRB3_N38
D1
D1
D2
D2
FRB3_PILOT_N
FORCE_MODE_N
R3274 1K
P3V3_AUX
J_FANSEL1
N31-1030011-H06
R3428
8.2K
R3324 10K-0402
R3275 X_8.2K
FORCE MODE2 - 3
ESB2 to PILOT SMI# CKT
P3V3_AUX
P3V3_AUX
R3174
4.7K
R3176
B
4.7K
Isolation Ckt
R_MSCLK R_MSDATA R_KBCLK R_KBDATA DDC_SDA DDC_SDC
U88
2
1A1
4
1A2
6
1A3
8
1A4
11
2A1
13
2A2
15
2A3
17
2A4
1
1OEn
19
2OEn
SN74CB3Q3244
R_MSCLK R_MSDATA R_KBCLK R_KBDATA
DDC_SDA MONSDA DDC_SDC
3
Q3017 MMBT3904
E C
18
1B1
16
1B2
14
1B3
12
1B4
9
2B1
7
2B2
5
2B3
3
2B4
20
VCC
10
GND
R843 4.7K_0402 R830 4.7K_0402 R829 4.7K_0402 R828 4.7K_0402 R92 4.7K_0402 R91 4.7K_0402
B
MONSCL
P3V3_AUX
R977
4.7K_0402
3 2 1
J_FRB3
1 2 3
N31-1030011-H06
J_FORCEMODE
3 2 1
N31-1030011-H06
R3175
4.7K
BMC_SMI_IN_N
Q3016 MMBT3904
E C
MSCLK MSDATA KBCLK KBDATA
R1223 49.9KST_0402 R1202 49.9KST_0402 R1204 49.9KST_0402 R1205 49.9KST_0402 R1213 X_49.9KST_0402 R1203 49.9KST_0402 R1185 49.9KST_0402 R1197 X_49.9KST_0402 R1217 49.9KST_0402 R1227 X_49.9KST_0402 R1249 49.9KST_0402 R1192 49.9KST_0402 R1253 49.9KST_0402 R1284 49.9KST_0402 R1282 X_49.9KST_0402 R1280 49.9KST_0402 R1250 49.9KST_0402 R1283 49.9KST_0402
J_FANSEL_1-2 N33-1020211-H06
J_FRB3_1-2 N33-1020331-H06
J_FORCEMODE_1-2
N33-1020331-H06
MONSDA 53 MONSCL 53
2
P3V3_AUX
P3V3_AUX P3V3_AUX
KBDATA MSDATA KBCLK MSCLK
2
PILOT2 STRAPS
P3V3_AUX
ARM_LFRAME# ARM_LAD0# ARM_LAD1# ARM_LAD2# ARM_LAD3# BMC_WDO BMC_BKUP_SPI_DO ICM_TX_EN# BMC_BKUP_SPI_CLK RSVD3 ETH_TXD0 BMC_BT_SPI_DO BMC_BT_SPI_CLK U2SOUT RSVD1 RSVD2 ETH_TXD1 ETH_TXEN
RSVD3 RSVD1 RSVD2 ETH_TXD0 ETH_TXD1 ETH_TXEN U2SOUT
R1109 X_2.7K_0402 R1191 X_2.7K_0402 R1215 X_2.7K_0402 R1225 X_2.7K_0402 R1186 2.7K_0402 R1198 X_2.7K_0402 R1190 X_2.7K_0402 R1224 2.7K_0402 R1220 X_2.7K_0402 R1228 2.7K_0402 R1110 X_2.7K_0402 R1193 X_2.7K_0402 R1189 X_2.7K_0402 R1285 X_2.7K_0402 R1230 2.7K_0402 R1229 X_2.7K_0402 R1112 X_2.7K_0402 R1113 X_2.7K_0402
RSVD3 55 RSVD1 55 RSVD2 55 ETH_TXD0 53,57 ETH_TXD1 53,57 ETH_TXEN 53,57 U2SOUT 55
BMC BOOT SPI FLASH (8 to 8Mbytes)
P3V3_AUX
1K-0402
C958
0.1u_0402
R1324 1K-0402
BMC_BT_SPI_CS# BMC_BT_SPI_DI
BMC BACKUP SPI FLASH
BMC_BKUP_SPI_CLK SPI_RST#
BMC_BKUP_SPI_CS#
R1325 1K-0402 R1326 1K-0402
R1323
U92
1
HOLDn
2
VCC
3
NC1
4
NC2
5
NC3
6
NC4
7
CSn/Sn SO/Q8WPn
SPI_SOCKET
U14
1
D
2
C
3
RST#
4
S#
M45PE80-VMW6TG
VCC
VSS
CLK/C
W#
16 15
SI/D
14
NC8
13
NC7
12
NC6
11
NC5
10
GND
9
BMC_BKUP_SPI_DIBMC_BKUP_SPI_DO
8
Q
5 6 7
PS2 KB/MS Connector
RN113
4.7K-8P4R
1 2
3 4
5 6
7 8
B3 120ohm-500mA B4 120ohm-500mA B5 120ohm-500mA B6 120ohm-500mA
C3122 180P
Title Document Number
C3123
C3124
180P
180P
Micro Star Restricted Secret
PILOT2 BMC Modules/Straps
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
STRAP0=0 STRAP1=0 STRAP2=0 STRAP3=0 STRAP4=1 STRAP5=0 STRAP6=0 STRAP7=1 STRAP8=0 STRAP9=1 STRAP10=0 STRAP11=0 STRAP12=0 STRAP13=0 STRAP14=1 STRAP15=0 STRAP16=0 STRAP17=0
BMC_BT_SPI_CLK BMC_BT_SPI_DO
P3V3_AUX
R1307 1K-0402
SPI_WE#
SPI_WE#
C960
0.1u_0402
C1576
0.1u KBMS1 YMD12P-1
1 2 5 6
C3125 180P
MS-9192
1
M25P64-VMF6TP
P3V3_AUX
5V_KB
4
3
KB
789
Last Revision Date:
Friday, April 27, 2007
Sheet
54 90
1
XU60
BIOS
F3004
1.1A6V
B2 80ohm-0805-5A
of
P5V
Rev
0A
Page 55
5
4
3
2
1
123456
C1244 22u-1206
P3V3_AUX
B
Isolation Ckt
R_PWM2 R_PWM3 R_PWM4
L41
JP1
2 4 6 8
10 12 14 16 18 20
HEADER 10X2
CONA_RI CONB_RI
P3V3_AUX
R265
X_8.2K
Q26
E C
2N3904S
2
U93
2 4 6 8
11 13 15 17
1
19
SN74CB3Q3244
P1V2_AUX
18 20
R951 0
1A1 1A2 1A3 1A4
2A1 2A2 2A3 2A4
1OEn 2OEn
VCC GND
18
1B1
16
1B2
14
1B3
12
1B4
9
2B1
7
2B2
5
2B3
3
2B4
20 10
RN32
8P4R-1K
PWM2 PWM3 PWM4
P3V3_AUX
C971
0.1u_0402
P3V3_AUX P3V3
R3332 1K
D S
R3454 1K
D S
Multi-ICE Header
P3V3_AUX
112
VSB_PWRGD
334 556 778
PROC_TCK
9910 111112 131314
HDR_nRESET# VSB_PWRGD
151516
17
17
19
19
RI# 40
P3V3_AUX
C1600
0.1u
R1685 33 R1686 X_0
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
R1684 X_1K
123456
78
PWM2 56 PWM3 56 PWM4 56
P12V
R1619 1K
R3455
G
1K
Q89 2N7002
SOT23SGD
P12V
R1620 0
G
Q90 2N7002
SOT23SGD
123456
P3V3P3V3_AUX
78
R1687 1K
SIO_KBRST#KBDRST
R3456 1K
CPU_A20GATEKBDGA20
RN9 1K-8P4R
PROC_TDI PROC_TMS PROC_TCK
PROC_TDO
SIO_KBRST# 40
CPU_A20GATE 40
VSB_PWRGD 57
Micro Star Restricted Secret
PILOT2 UART/OSC
MS-9192
Last Revision Date:
Wednesday, May 02, 2007
Sheet
55 90
1
Rev
0A
of
U54C
RSVD1 RSVD2 RSVD3
E5 F6 D3 E3
K6
G1
H2 H1 J2 J1 K3 L6
M2 M6
N1 T1
P1 M4 M3
R1
A20 A19 E14
B7
C7
F7
C6
D6
A4
A5
D7
A13 E13 A12 F12
P18 T18 V20 U18 R19
C17 B21
V22 B16 P20
W21
R17 R18
C1489 0.1u
C1492 0.1u
CONB_DCD CONB_DSR CONB_RXD CONB_RTS CONB_TXD CONB_CTS CONB_DTR CONB_RI
8P4C-180P
BMC_FAN_TACH0 BMC_FAN_TACH1 BMC_FAN_TACH2 BMC_FAN_TACH3
UART0_CTSn UART0_DCDn UART0_DSRn UART0_DTRn UART0_RIn UART0_RTSn UART0_RXD UART0_TXD
U2CTSn/FANTACH4 U2DCDn/FANTACH5 U2DSRn/FANTACH6 U2DTRn/PWM2 U2RIn/FANTACH7 U2RTSn/PWM3 UART2_RXD UART2_TXD
PASSTHRUIN_0 PASSTHRUIN_1 PASSTHRUIN_2
TEMP_AVDD_1 TEMP_AVDD_2 TEMP_AVDD_3 TEMP_AVDD_4 TEMP_AVDD_5 TEMP_AVDD_6 TEMP_AVDD_7 TEMP_AVDD_8 DAC_AVDD1 DAC_AVDD2 DAC_AVDD3 DAC_AVDD4
MFG_TCK MFG_TDI MFG_TDO MFG_TMS MFG_TRST
MFG_TAP_EN TEST_BUS_EN
RSVD0 RSVD1 RSVD2 RSVD3
XT1_1 XT1_2
PILOT2
PRTB_DTR PRTB_RTS PRTB_TXD
PRTB_DCD PRTB_RXD PRTB_DSR PRTB_CTS PRTB_RI
CN1
FANTACH167 FANTACH267 FANTACH367 FANTACH467
PRTA_CTS PRTA_DCD PRTA_DSR PRTA_DTR
R3360 4.7K
P_TEMP_AVDD
P_DACVDD
C950 103P_0402
VSB_PWRGD_PILOT
R1330 1K-0402 R1331 1K-0402
R1329 1K-0402
R1618 0
12
C1457 33P
R1309 X_0
C1488
0.1u
4
PRTA_RI PRTA_RTS PRTA_RXD PRTA_TXD
R_PWM3 R_PWM4
U2SIN U2SOUT
TP9 TP10 TP11
PROC_TCK PROC_TDI PROC_TDO PROC_TMS
PILOT_XTALI PILOT_XTALO
R1549 2.7K R1550 2.7K
D D
FANTACH567 FANTACH667 FANTACH767
FANTACH867
U2SOUT54
C951 103P_0402
P3V3_AUX
RSVD154 RSVD254 RSVD354
Y5
25MHZ
C1456 33P
P3V3_AUX P3V3_AUXP3V3 P3V3
R1314 0
C955 22u-1206
C948 22u-1206
7 8
5 6
T1OUT T2OUT T3OUT
MAX3243CAI
3 4
1 2
J3001
1 2
X_YJ102
C957
0.1u_0402
C953
0.1u_0402
U95
V+
V-
R1IN R2IN R3IN R4IN R5IN
VCC GND
1 6 2 7 3 8 4 9 5
C954
0.1u_0402
C949
0.1u_0402
C1485 0.1u
27
C1486 0.1u
3
9 10 11
4 5 6 7 8
26 25
COM1
1011
N51-09M0181-F02
CONA_DTR CONA_RTS CONA_TXD
CONA_DCD CONA_RXD CONA_DSR CONA_CTS CONA_RI
C956 103P_0402
C952
0.1u_0402
VSB_PWRGD_PILOT54,57
U2SIN U2SOUT
For Debug
P3V3_AUX
L40
4.7uH-0805-30mA
P3V3_AUX
L39
4.7uH-0805-30mA
C C
COM A COM B
C1484 0.1u
C1487 0.1u
B B
P3V3_AUX P3V3_AUX
R1547 2.7K R1548 2.7K
A A
PRTA_INVLD PRTB_INVLD
CONA_DCD CONA_DSR CONA_RXD CONA_RTS CONA_TXD CONA_CTS CONA_DTR CONA_RI
PRTA_DTR PRTA_RTS PRTA_TXD
PRTA_DCD PRTA_RXD PRTA_DSR PRTA_CTS PRTA_RI
5
28
C1+
24
C1-
1
C2+
2
C2-
14
T1IN
13
T2IN
12
T3IN
20
R2OUTB
19
R1OUT
18
R2OUT
17
R3OUT
16
R4OUT
15
R5OUT
21
INVALID#
22
FORCEOFF#
23
FORCEON
7 8
5 6
CPN1 8P4C-180P
3 4
1 2
CPN2 8P4C-180P
7 8
5 6
UART 0&1
ANALOG POWER
28 24
1 2
14 13 12
20 19 18 17 16 15
21 22 23
7 8
3 4
1 2
FAN CONTROL
BMC_PWM0 BMC_PWM1
UART1_CTSn UART1_DCDn UART1_DSRn
UART1_DTRn
UART1_RIn
UART1_RTSn
UART1_RXD UART1_TXD
U3RXD/KBDRSTn
U3TXD/KBGA20
UART 2&3
PASSTHRUOUT_0 PASSTHRUOUT_1 PASSTHRUOUT_2
PIX_PLL_VDD
ADC_VDD
SYS_PLL_VDD
MFG_TMODE_0 MFG_TMODE_1
MFG_SMC
MFG_TMC MFG_TMC1 MFG_TMC2
TAPRSTN
PECI
PECI_VTT
PECI_N
C1+ C1-
C2+ C2-
T1IN T2IN T3IN
R2OUTB R1OUT R2OUT R3OUT R4OUT R5OUT
INVALID# FORCEOFF# FORCEON
MAX3243CAI
CN2 8P4C-180P
5 6
3 4
1 2
SPEAKER_BMC
C2
R_PWM2
D2
PRTB_CTS
L5
PRTB_DCD
L3
PRTB_DSR
K1
PRTB_DTR
M5
PRTB_RI
L4
PRTB_RTS
M1
PRTB_RXD
L2
PRTB_TXD
L1
KBDRST
B20
KBDGA20
F17
D14 A18 A17
PIXEL_AVDD
T20
P_ADC_VDD
C8
P_PLLVDD
U20
R1327 1K-0402
E19
R1328 1K-0402
D18
R1335 1K-0402
E17
R1332 1K-0402
D16
R1336 X_1K-0402
G17
R1337 X_1K-0402
E18
TAP_TRSTN
E15
T17 V19
U96
C1490 0.1u
27
V+
C1491 0.1u
3
V-
CONB_DTR
9
T1OUT T2OUT T3OUT
R1IN R2IN R3IN R4IN R5IN
GND
CONB_DCD 67 CONB_DSR 67 CONB_RXD 67 CONB_RTS 67 CONB_TXD 67 CONB_CTS 67 CONB_DTR 67 CONB_RI 67
CONB_RTS
10
CONB_TXD
11
CONB_DCD
4
CONB_RXD
5
CONB_DSR
6
CONB_CTS
7
CONB_RI
8
26
VCC
25
Serial Port DCD (IN) Data Carrier Detect SIN (IN) Received Data SOUT(OUT) Transmitted Data DTR (OUT) Data Terminal Ready DSR (IN) Data Set Ready RTS (OUT) Request To Send CTS (IN) Clear To Send RI (IN) Ring Indicator
3
SPEAKER_BMC 39
TP6 TP7 TP8
R1300 4.7K_0402
R1405 0_0402 R1103 0_0402 R1308 X_4.7K_0402
C966
0.1u_0402
C962 103P_0402
C961
0.1u_0402
C959
0.1u_0402
P3V3_AUX
P1V2_AUX
RSVD_PECI 11,14,66
P1V2_AUX
Provide Pull Up if PECI not used
R1316
R1319
0
X_0
C1493
0.1u
SPEAKER_BMC
PS_PWRGD_N54,63,68
4.7uH-0805-30mA
C537 22u-1206
4.7uH-0805-30mA
C965 22u-1206
C964
0.1u_0402
1N4148S
P3V3_AUX P3V3_AUX
78
RN31
8P4R-1K
P1V2_AUX
L42
P3V3_AUX
L43
4.7uH-0805-30mA
C963 103P_0402
R928 0 R957 0
AC
AC
D26
D20
1N4148S
R51
4.7K
R63
C65
2.7K
0.1u
Page 56
5
P1V2_AUX
D D
VBAT_HM VBAT
R1389
R1111
0
X_0
C C
B B
P3V3_AUX
P1V2_AUX
P1V2_AUX
FB29
80_600mA
FB30
80_600mA
G16 H16 K16
L16 N16 P16
T16
L15 G14 M14
T14
L13 G12 H12 K12 M12 P12
T12
J11
L11 N11 R11
T11 G10 M10
L9 T9 G8
M8
H7
J7
L7 N7 R7 T7
D5
J20 K19 K20
F22
F21
C968
0.1u_0402
C969
0.1u_0402
U54E
VDD12_1 VDD12_2 VDD12_3 VDD12_4 VDD12_5 VDD12_6 VDD12_7 VDD12_8 VDD12_9 VDD12_10 VDD12_11 VDD12_12 VDD12_13 VDD12_14 VDD12_15 VDD12_16 VDD12_17 VDD12_18 VDD12_19 VDD12_20 VDD12_21 VDD12_22 VDD12_23 VDD12_24 VDD12_25 VDD12_26 VDD12_27 VDD12_28 VDD12_29 VDD12_30 VDD12_31 VDD12_32 VDD12_33 VDD12_34 VDD12_35
BATVDD3
PCIE_VDD1 PCIE_VDD2 PCIE_VDD3 PCIE_VDD4 PCIE_VDD5
PILOT2
C967 103P_0402
C970 103P_0402
DDR_VDD1 DDR_VDD2 DRR_VDD3 DDR_VDD4 DDR_VDD5 DDR_VDD6 DDR_VDD7 DDR_VDD8
DDR_VDD9 DDR_VDD10 DDR_VDD11 DDR_VDD12
DAC_DVDD
VDD33_1 VDD33_2 VDD33_3 VDD33_4 VDD33_5 VDD33_6 VDD33_7 VDD33_8
VDD33_9 VDD33_10 VDD33_11 VDD33_12 VDD33_13 VDD33_14 VDD33_15 VDD33_16 VDD33_17 VDD33_18 VDD33_19
USB1_AVDD USB1_PVDD
USB1_VD331 USB1_VD332
USB1_GND1 USB1_GND2
USB1_RREF
USB1_COM USB1_PVSS USB1_AVSS
C653 22u-1206
C659 22u-1206
USB_AVDD
USB_PLLVDD
W18 Y16 V14 Y12 V10 Y8 W6 AB9 AA7 AB18 AB13 AA9
D12
U22 P21 AA21 C20 T19 Y19 F18 D17 P17 U17 B15 Y5 G4 N4 C3 Y3 K2 T2 B22
K17 P19 N21
M20 P22
N22 L17 R21
R22 L19
P1V8_AUX
P1V2_AUX
P3V3_AUX
USB_AVDD USB_PLLVDD
P3V3_AUX
USB_RREF
4
R1404
1.6KST_0402
W22
AB22
W19
AA19
3
U54D
A22
GND_1
AB1
GND_2
C22
GND_3
E22
GND_4 GND_5 GND_6
A21
GND_7
T21
GND_8
D19
GND_9
N19
GND_10 GND_11 GND_12
V18
GND_13
B17
GND_14
J16
GND_15
M16
GND_16
R16
GND_17
D15
GND_18
G15
GND_19
H15
GND_20
J15
GND_21
K15
GND_22
M15
GND_23
N15
GND_24
P15
GND_25
R15
GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67
GND_DDR_1 GND_DDR_2 GND_DDR_3 GND_DDR_4 GND_DDR_5 GND_DDR_6 GND_DDR_7 GND_DDR_8
GND_DDR_9 GND_DDR_10 GND_DDR_11 GND_DDR_12 GND_DDR_13
SYS_PLLGND PCIE_PLL_GND TEMP_AGND_1 TEMP_AGND_2 TEMP_AGND_3 TEMP_AGND_4 TEMP_AGND_5
PCIE_GND10 PCIE_GND11 PCIE_GND12 PCIE_GND13 PCIE_GND14
T15
H14
J14
K14
L14 N14 P14 R14 G13 H13
J13 K13 M13 N13 P13 R13
T13
J12
L12 N12 R12 G11 H11 K11 M11 P11 H10
J10 K10
L10 N10 P10 R10
T10
G9
H9
J9
K9
M9
N9 P9
PILOT2
GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90 GND_91
ADC_AGND
BATGND DAC_AGND DAC_DGND
PCIE_GND1 PCIE_GND2 PCIE_GND3 PCIE_GND4 PCIE_GND5 PCIE_GND6 PCIE_GND7 PCIE_GND8 PCIE_GND9
R9 H8 J8 K8 L8 N8 P8 R8 T8 G7 K7 M7 P7 U7 D4 K4 T4 W4 AB4 G2 N2 A1 D1 W1
AB19 AA18 W13 V17 V16 AB16 AA14 V12 W9 AA10 AA6 V8 AB8
U19 U21 E9 F8 B4 A3 F9
F10 E6 C11 B12
H20 H19 J19 J18 K22 M22 K21 M21 L20 K18 J17 H22 H21 G20
PILOT 1.2V AUX Decoupling Caps.
P1V2_AUX
C1500
P1V2_AUX
C1499 1u
C1504
0.1u
1u
C1505
0.1u
C1501 1u
C1507
0.1u
C1502 1u
C1510
0.1u
C1503 1u
C1511
0.1u
PILOT 1.8V AUX Decoupling Caps.
P1V8_AUX
C1527
C1528
C1532 1u
C1526
0.1u
0.1u
C1529
0.1u
0.1u
PILOT 3.3V AUX Decoupling Caps.
P3V3_AUX
P3V3_AUX
C1534
0.1u
C1552
0.1u
C1535
0.1u
C1553
0.1u
C1536
0.1u
C1554
0.1u
C1537
0.1u
C1555
0.1u
C1541
0.1u
C1556
0.1u
C1506 1u
C1512
0.1u
C1530
0.1u
C1542
0.1u
C1557
0.1u
2
C1518 1u
C1516
0.1u
C1533
0.1u
C1543
0.1u
C1538 1u
C1519 1u
C1523
0.1u
C1531 22u-1206
C1546
0.1u
C1539 1u
C1513 103P
C1524
0.1u
C1547
0.1u
C1540 1u
C1514 103P
C1525
0.1u
C1548
0.1u
C1544 22u-1206
C1508 22u-1206
C1495
0.1u
C1549
0.1u
C1545 22u-1206
C1496
0.1u
C1550
0.1u
C1509 22u-1206
C1497
0.1u
C1551
0.1u
C1498
0.1u
1
P3V3
P3V3_AUX
R3464 1K
U77
VCC
1 2 3
GND
74LVC126
5 4
R1622
X_0
PWM2
A A
PWM255
5
FPWM_CPU
P3V3
R3459 1K
FPWM_CPU 67
P3V3
P3V3_AUX
R3465 1K
U85
VCC
1 2 3
GND
74LVC126
5 4
R1623
X_0
PWM3
PWM355
4
FPWM_PWR
P3V3
R3460 1K
FPWM_PWR 67
3
P3V3
P3V3_AUX
R3466 1K
U94
VCC
1 2 3
GND
74LVC126
R1624
X_0
5
FPWM_MEM
4
PWM4
PWM455
2
P3V3
R3461 1K
FPWM_MEM 67
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
PILOT2 POWER
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
of
56 90
Rev
0A
Page 57
5
4
3
2
1
BCMDVDD
P3V3_AUX
C422
0.1u
ETH_MDIO ETH_MDC
ETH_TXD1 ETH_TXD0 ETH_TXEN ETH_TXCLKR
ETH_RXER ETH_RXCLKR
ETH_RXD0 ETH_RXD1
R1320 X_4.7K_0402 R1396 X_4.7K_0402 R1397 X_4.7K_0402 R1398 X_4.7K_0402 R1399 4.7K_0402 R1400 X_4.7K_0402 R1401 4.7K_0402
BCMAVDD
R832 0
R602 33
R601 33 R833 X_0
C425
0.1u
P3V3_AUX
C485 103P
ETH_RXDV
ETH_TXCLK
ETH_RXCLK ETH_RXDV
P3V3_AUX
C427
0.1u
MAC1_TDP MAC1_TDN
MAC1_RDP MAC1_RDN
C424
C817
0.1u
0.1u
ETH_MDIO 53 ETH_MDC 53
ETH_RXDV 53
ETH_TXD1 53,54 ETH_TXD0 53,54 ETH_TXEN 53,54
ETH_RXER 53
ETH_RXD0 53 ETH_RXD1 53
P3V3_AUX
R849 1K
C409
0.1u
BCMAVDD
ETH_MDIO ETH_MDC
R1553
49.9RST
OSC3
2 1
50MHz_OSC
R1554
49.9RST
P3V3_AUX
R1558 1K
4 3
R1551
49.9RST
R1559 1K
P3V3_AUX
P3V3_AUX
R1552
49.9RST
C1568
C1569
0.1u
0.1u
C486
0.1u
P3V3_AUX
R851
33
FB10 80_600mA
TD+ TDC TD-
RD+ RD­RDC
TX+
CMT
RX+ RXC
TF2
16 15 14
TX-
11 9
RX-
10
1 2 3
6 8 7
1:1-TX
78
RN112
75-8P4R
RMII Reference Clock
C538
0.1u
1 2 6 4
U29
CLKIN OE VCC3 GND
CDCV304
1Y0 1Y1 1Y2 1Y3
50_CLKIN
LAN3TXP LAN3TXN LAN3RXP
LAN3RXN
123456
CHS1GND
R857 33
3
R854 33
5
R858 X_33
7
R856 X_33
8
MATCH LENGTHS
C3216
102P
14
8 7 6 5 4 3 2 1
13
ETH_REFCLK PHY_REFCLK ETH_TXCLK ETH_RXCLK
LAN3
SPEED
10
O
G
9
12 11
LINK/ACT
AMP/108-57136
ETH_REFCLK 53
P1_SPD# P2_SPD#
R1555 300
R1556 X_300
R1572 300
P1_ACT# P1_LNK#
R1030 X_0
P3V3_AUX
64
RDAC
VSB_PWRGD
C1570 X_0.1u
JTAG-EN
4
REF_CLK
5
XTALO
6
XTALI
7
XTALGND
9
RESET#
10
PHYAD0/FDX_LED#
11
PHYAD1/COL_LED#
12
PHYAD2/ACT_LED#
13
PHYAD3/PAUSE
14
PHYAD4
15
TESTEN
16
LOW_PWR
17
ENERGY_DET
18
MII_EN
19
SD-
21
SD+
37
F100/TCK
38
ANEN/TRST#
39
FDX
23
RDAC
24
BIASGND
29
AGND1
32
AGND2
40
DGND1
45
DGND2
54
DGND3
63
DGND4
33
RCVLED#/ACTLED#/TDO
34
XMTLED#/INTR#/FDXLED#
35
LINKLED#/TDI
36
SPDLED#/TMS
R1322 X_200_0402 R1390 200_0402 R1392 X_200_0402 R1391 200_0402 R1393 X_200_0402 R1394 X_200_0402 R1395 X_200_0402
D D
P3V3_AUX
C C
C1566 X_18P
X_25MHZ
C3217
0.1u
Y6
C1567
PHY_REFCLK
12
X_18P
C3218
0.1u
R837 0
XTALO XTALI
R836 0
VSB_PWRGD
ETH_TESTEN ETH_LOWPWR ETH_ENERGY ETH_MII_EN
ETH_TCK ETH_TRST# ETH_FDX
R501
1.27KST
P1_ACT# P1_LNK#
P1_SPD#
RSMRST#40,47,63
B B
R1029
X_0
DVDD1 DVDD2
OVDD1 OVDD2
OVDD3/NC
AVDD1 AVDD2
BIASVDD REGDVDD REGAVDD
MDIO
MDC
CRS/CRS_DV
TXD3 TXD2 TXD1 TXD0 TXEN
TXER RXER RXDV
RXD0 RXD1 RXD2 RXD3
BCM5221KPT
TD+
RD+
COL
TXC
RXC
U97
TD-
RD-
2 55
1 46 8
28 27 22 3 20
31 30
26 25
41 42 61 62
60 59 58 57 56 53 52
51 50 49 48 47 44 43
ETH_TESTEN ETH_LOWPWR ETH_ENERGY ETH_MII_EN ETH_TCK ETH_TRST# ETH_FDX
P3V3_AUX
P3V3_AUX
R711 1K-0402
DS
Q47 2N7002
G
SOT23SGD
147
U3010E
11 10
74LVC14A_SOIC14
R1339
54.9KST-0402
VSB_PWRGD_PILOT 54,55
J7
1 2
X_N31-1020011-H06
P3V3_AUX
R726 10K_0402
R725
330_0402
P3V3_AUX
C487 X_1u
U123
3
RESET
MR
4
GND
VCC
MAX6315US29D3+T
2 1
P3V3_AUX
R1338 1K-0402
A A
U119
GND2VCC
X_ADM809TART_SOT23-3
5
4
RESET
P3V3_AUX
3
1
VSB_PWRGD
VSB_PWRGD 55
3
Title Document Number
2
Micro Star Restricted Secret
PILOT2 LAN
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
MS-9192
Last Revision Date:
Wednesday, May 02, 2007
Sheet
57 90
of
1
Rev
0A
Page 58
5
Clocks CK410B
4
3
2
1
D D
P3V3
C C
B B
FB1
80ohm-0805-5A CB4
0.1u
P3V3
80ohm-0805-5A
CPU_VRD_PWRGD40,60,63
CB5
0.1u
FB2
SMBDAT_MAIN59,60,64,69,74 SMBCLK_MAIN59,60,64,69,74
C430 10u-0805
C436
0.1u
CPU_BSEL059,62 CPU_BSEL162 CPU_BSEL262
C431 102P
C437
0.1u
VCC3VA
C444 10u-0805
SMBDAT_MAIN SMBCLK_MAIN
VCC3VA
C432
0.1u
C438 102P
R449 10K
R458 1K
R465 1K
C433
0.1u
C439
0.1u
C443
0.1u
R3436 0 R3437 0
CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
C434 102P
C440
0.1u
R392
10
C445 102P
C435
0.1u
C441
0.1u
C442
0.1u
C446
0.1u
CLK_GD#
Q67 MMBT3904
1K Pull Down Added to Counter
CK410B
1
VDDPCI
8
VDDPCI
2
GNDPCI
7
GNDPCI
38
VDDCPU
44
VDDCPU
47
VDDCPU
41
GNDCPU
15
VDDSRC
25
VDDSRC
28
VDDSRC
20
GNDSRC
12
VDD48
14
GND48
53
VDDREF
50
GNDREF
35
VDDA
34
GNDA
30
SDATA
29
SCLK
31
VTT_PWRGD#/PD
48
FS_A
49
FS_B/TEST_MODE
56
FS_C/TEST_SEL
U37
R355 33
PCICLK0 PCICLK1 PCICLK2 PCICLK3
48MHZ
REF0 REF1
IREF
X1
X2
46 45 43 42 40 39 37 36
16 17
19 18 21 22 24 23 26 27
9 10 11 3 4 5 6
13 55
54 52
51
R417 475RST
33
R357 33 R359 33 R361 33 R363 33 R365 33 R367 33 R369 33
R372 33 R374 33 R376 33 R378 33 R381 33 R384 33 R387 33 R389 33 R393 33 R395 33
R3157 33 R400 33 R402 33 R404 33 R3467 33 R3145 33 R410 33
R413 10 R414 10
R415 33
Y1 14M-32pf-HC49S-D
CPUCLK_0_P CPUCLK_0_N CPUCLK_1_P CPUCLK_1_N CPUCLK_2_P CPUCLK_2_N CPUCLK_3_P CPUCLK_3_N
SRCCLK_0_P SRCCLK_0_N SRCCLK_1_P SRCCLK_1_N SRCCLK_2_P SRCCLK_2_N SRCCLK_3_P SRCCLK_3_N SRCCLK_4_P SRCCLK_4_N
PCICLK_F0 PCICLK_F1 PCICLK_F2
CK410B/ICS932S401
SMBus Voltage Translation
P3V3
CK_H_MCH CK_H_MCH_N CK_H_P0 CK_H_P0_N CK_H_P1 CK_H_P1_N CK_H_FBD CK_H_FBD_N
SRC_100CLK_P SRC_100CLK_N ESB2_100CLK_P ESB2_100CLK_N ESI_100CLK_P ESI_100CLK_N SATA_100CLK_P SATA_100CLK_N MCH_100CLK_P MCH_100CLK_N
XDP0_33MHZ_CLK ESB2_PCLK SIO_PCLK FWH_PCLK TPM_PCLK DEBUG_33MHZ_CLK PLD_33MHZ_CLK
CK_48M_ESB CK_48M_PILOT
ESB_14MHZ
33PC453
33PC454
P3V3
CK_H_MCH 15 CK_H_MCH_N 15 CK_H_P0 9 CK_H_P0_N 9 CK_H_P1 12 CK_H_P1_N 12 CK_H_FBD 59 CK_H_FBD_N 59
SRC_100CLK_P 60 SRC_100CLK_N 60 ESB2_100CLK_P 36 ESB2_100CLK_N 36 ESI_100CLK_P 36 ESI_100CLK_N 36 SATA_100CLK_P 39 SATA_100CLK_N 39 MCH_100CLK_P 19 MCH_100CLK_N 19
XDP0_33MHZ_CLK 64 ESB2_PCLK 38 SIO_PCLK 53 FWH_PCLK 45
TPM_PCLK 45
DEBUG_33MHZ_CLK 67 PLD_33MHZ_CLK 63
CK_48M_ESB 40
CK_48M_PILOT 53
ESB_14MHZ 39
BSEL2 BSEL0BSEL1
0
0 0
1
0
110
Freq.
133MHz
1
166MHz
1
266MHz
00
333MHz
001
RESVD
CK_H_MCH CK_H_MCH_N CK_H_P0 CK_H_P0_N CK_H_P1 CK_H_P1_N CK_H_FBD CK_H_FBD_N SRC_100CLK_P SRC_100CLK_N MCH_100CLK_P MCH_100CLK_N ESI_100CLK_P ESI_100CLK_N ESB2_100CLK_P ESB2_100CLK_N SATA_100CLK_P SATA_100CLK_N
ESB2_PCLK SIO_PCLK FWH_PCLK XDP0_33MHZ_CLK PLD_33MHZ_CLK DEBUG_33MHZ_CLK CK_48M_ESB
ESB_14MHZ
R478 49.9RST R480 49.9RST R482 49.9RST R484 49.9RST R486 49.9RST R488 49.9RST R490 49.9RST R492 49.9RST R504 49.9RST R505 49.9RST R483 49.9RST R485 49.9RST R487 49.9RST R489 49.9RST R491 49.9RST R493 49.9RST R494 49.9RST R496 49.9RST
X_10PC461 X_10PC462 X_10PC463 X_10PC3121 X_10PC470 X_10PC471 X_10PC472
10PC474
Any EPLD Glitches At power Up
R3128
R3126
5.1K
U3016
1
NC
VCC
SMBCLK_ESB239
A A
5
SMBDAT_ESB239
4
2 3
PCA9515
SCL0
SCL1
SDA0
SDA1
GND4EN
5.1K
8 7 6 5
SMBCLK_MAINSMBCLK_ESB2 SMBDAT_MAINSMBDAT_ESB2
PS_PWROK_BUF 54,68,75
Micro Star Restricted Secret
R3127
5.1K
3
2
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
Clocks CK410B
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
58 90
of
Rev
0A
Page 59
5
4
3
2
1
Clock DB1900
D D
DB1900
U36
CB6
0.1u
CK_H_FBD0 CK_H_FBD0_N CK_H_FBD1 CK_H_FBD1_N CK_H_FBD2 CK_H_FBD2_N CK_H_FBD3 CK_H_FBD3_N CK_H_FBD4 CK_H_FBD4_N CK_H_FBD5 CK_H_FBD5_N CK_H_FBD6 CK_H_FBD6_N CK_H_FBD7 CK_H_FBD7_N CK_H_FBD8 CK_H_FBD8_N CK_H_FBD9 CK_H_FBD9_N CK_H_FBD10 CK_H_FBD10_N CK_H_FBD11 CK_H_FBD11_N
FBD01CLKP FBD01CLKN FBD23CLKP FBD23CLKN XDP0_BCLK_P XDP0_BCLK_N
FB4
80ohm-0805-5A C452
10u-0805
CK_H_FBD0 23 CK_H_FBD0_N 23 CK_H_FBD1 24 CK_H_FBD1_N 24 CK_H_FBD2 25 CK_H_FBD2_N 25 CK_H_FBD3 26 CK_H_FBD3_N 26 CK_H_FBD4 27 CK_H_FBD4_N 27 CK_H_FBD5 28 CK_H_FBD5_N 28 CK_H_FBD6 29 CK_H_FBD6_N 29 CK_H_FBD7 30 CK_H_FBD7_N 30 CK_H_FBD8 31 CK_H_FBD8_N 31 CK_H_FBD9 32 CK_H_FBD9_N 32 CK_H_FBD10 33 CK_H_FBD10_N 33 CK_H_FBD11 34 CK_H_FBD11_N 34
FBD01CLKP 17 FBD01CLKN 17 FBD23CLKP 18 FBD23CLKN 18 XDP0_BCLK_P 64 XDP0_BCLK_N 64
P3V3
CB7
0.1u
CK_H_FBD0 CK_H_FBD0_N CK_H_FBD1 CK_H_FBD1_N CK_H_FBD2 CK_H_FBD2_N CK_H_FBD3 CK_H_FBD3_N CK_H_FBD4 CK_H_FBD4_N CK_H_FBD5 CK_H_FBD5_N CK_H_FBD6 CK_H_FBD6_N CK_H_FBD7 CK_H_FBD7_N CK_H_FBD8 CK_H_FBD8_N CK_H_FBD9 CK_H_FBD9_N CK_H_FBD10 CK_H_FBD10_N CK_H_FBD11 CK_H_FBD11_N FBD01CLKP FBD01CLKN FBD23CLKP FBD23CLKN XDP0_BCLK_P XDP0_BCLK_N
DIF_18 DIF_18#
R418 49.9RST R419 49.9RST R420 49.9RST R421 49.9RST R422 49.9RST R423 49.9RST R424 49.9RST R426 49.9RST R428 49.9RST R429 49.9RST R432 49.9RST R434 49.9RST R436 49.9RST R437 49.9RST R438 49.9RST R439 49.9RST R440 49.9RST R441 49.9RST R443 49.9RST R446 49.9RST R448 49.9RST R451 49.9RST R453 49.9RST R456 49.9RST R457 49.9RST R460 49.9RST R462 49.9RST R463 49.9RST R3381 49.9RST R3382 49.9RST
C455 0.1u C456 0.1u
R343 1K
R352 1K
P3V3_M
C C
P3V3
B B
CK_H_FBD58
CK_H_FBD_N58
SMBCLK_MAIN58,60,64,69,74 SMBDAT_MAIN58,60,64,69,74
P3V3_M
CPU_BSEL058,62
FB3
80ohm-0805-5A C447
0.1u
CK_H_FBD CK_H_FBD_N
SMBCLK_MAIN SMBDAT_MAIN
CPU_BSEL0
P3V3_M
C448 10u-0805
R3438 0 R3439 0
R379 1K R382 1K R385 1K
R390 X_10K
C450
C449
0.1u
0.1u
R391
4.7K-0402
C451
0.1u
18
OE_01234#
21
OE_5#
24
OE_6#
29
OE_7#
32
OE_8#
37
OE_9#
40
OE_10#
43
OE_11#
48
OE_12#
51
OE_13#
54
OE_14#
57
OE_15#
60
OE_16#
69
OE_17_18#
70
CLK_IN
71
CLK_IN#
19
SMBCLK
20
SMBDAT
35
SMB_A0
36
SMB_A1
72
SMB_A2_PLLBYP#
4
HIGH_BW#
5
FS_A_410
11
VDD
27
VDD
47
VDD
63
VDD
10
GND
28
GND
46
GND
64
GND
73
GND
VDDA/PD#
DIF_0
DIF_0#
DIF_1
DIF_1#
DIF_2
DIF_2#
DIF_3
DIF_3#
DIF_4
DIF_4#
DIF_5
DIF_5#
DIF_6
DIF_6#
DIF_7
DIF_7#
DIF_8
DIF_8#
DIF_9 DIF_9# DIF_10
DIF_10#
DIF_11
DIF_11#
DIF_12
DIF_12#
DIF_13
DIF_13#
DIF_14
DIF_14#
DIF_15
DIF_15#
DIF_16
DIF_16#
DIF_17
DIF_17#
DIF_18
DIF_18#
GNDA
IREF
DB1900
6 7 8 9 12 13 14 15 16 17 22 23 25 26 30 31 33 34 38 39 41 42 44 45 49 50 52 53 55 56 58 59 61 62 65 66 67 68
3 2 1
DIF_18 DIF_18#
R416 475RST
R344 33 R345 33 R346 33 R347 33 R348 33 R349 33 R350 33 R351 33 R353 33 R354 33 R356 33 R358 33 R360 33 R362 33 R364 33 R366 33 R368 33 R370 33 R371 33 R373 33 R375 33 R377 33 R380 33 R383 33
R407 33 R409 33 R411 33 R412 33 R386 33 R388 33
A A
Title Document Number
5
4
3
2
Micro Star Restricted Secret
Clock DB1900
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
59 90
1
Rev
0A
of
Page 60
5
4
3
2
1
Clock DB800
D D
DB800
U38
R442 10K R444 10K
R450 475RST
R454 1K
R3442 1K
C458 10u-0805
VCC3_SRCLK
C466
0.1u
SRC_100CLK_P SRC_100CLK_N
R430 1K R435 1K
DB800PWDN
C459
0.1u
C467
0.1u
SRC_100CLK_P58 SRC_100CLK_N58
VCC3_SRCLK
SMBCLK_MAIN58,59,64,69,74 SMBDAT_MAIN58,59,64,69,74
CPU_VRD_PWRGD40,58,63
C C
B B
P3V3
SMBCLK_MAIN SMBDAT_MAIN
CPU_VRD_PWRGD
P3V3
80ohm-0805-5A C464
0.1u
VCC3_SRCLK
VCC3_SRCLK VCC3_SRCLK
VCC3_SRCLK
FB5
80ohm-0805-5A C457
0.1u
FB6
R3440 0 R3441 0
R1387 0
C465 10u-0805
C468
0.1u
4
SRC_IN_P
5
SRC_IN_N
1
SRC_DIV2_N
22
PLL
23
SCL
24
SDA
26
PWRDWN_N
27
SRC_STOP_N
28
HIGH_BW_N
45
LOCK
46
IREF
44
OE_7
36
OE_6
35
OE_5
43
OE_4
7
OE_3
15
OE_2
14
OE_1
6
OE_0
48
VDD_A
39
VDD4
31
VDD3
19
VDD2
11
VDD1
2
VDD0
DIF_7_P DIF_7_N
DIF_6_P DIF_6_N
DIF_5_P DIF_5_N
DIF_4_P DIF_4_N
DIF_3_P DIF_3_N
DIF_2_P DIF_2_N
DIF_1_P DIF_1_N
DIF_0_P DIF_0_N
VSS_A
VSS5 VSS4 VSS3 VSS2 VSS1 VSS0
DB800
42 41
38 37
34 33
30 29
20 21
16 17
12 13
8 9
47 40 32 25 18 10 3
R425 33 R427 33
R431 33 R433 33
R1540 33 R1541 33
R452 33 R455 33
R459 33 R461 33
R464 33 R466 33
PCIE1_100CLK_P1 PCIE1_100CLK_N1
PCIE1_100CLK_P0 PCIE1_100CLK_N0
PILOT_100CLK_P PILOT_100CLK_N
PCIE2_100CLK_P0 PCIE2_100CLK_N0
PCI1_100CLK_P0 PCI1_100CLK_N0
PCI1_100CLK_P1 PCI1_100CLK_N1
PCIE1_100CLK_P1 51 PCIE1_100CLK_N1 51
PCIE1_100CLK_P0 51 PCIE1_100CLK_N0 51
PILOT_100CLK_P 53 PILOT_100CLK_N 53
PCIE2_100CLK_P0 51 PCIE2_100CLK_N0 51
PCI1_100CLK_P0 50 PCI1_100CLK_N0 50
PCI1_100CLK_P1 50 PCI1_100CLK_N1 50
PCIE1_100CLK_P1 PCIE1_100CLK_N1 PCIE1_100CLK_P0 PCIE1_100CLK_N0 PILOT_100CLK_P PILOT_100CLK_N PCIE2_100CLK_P0 PCIE2_100CLK_N0 PCI1_100CLK_P0 PCI1_100CLK_N0 PCI1_100CLK_P1 PCI1_100CLK_N1
R3052 49.9RST R3053 49.9RST R3054 49.9RST R3055 49.9RST R479 49.9RST R481 49.9RST R3050 49.9RST R3051 49.9RST R3058 49.9RST R3059 49.9RST R3056 49.9RST R3057 49.9RST
A A
Title Document Number
5
4
3
2
Micro Star Restricted Secret
Clock DB800
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
60 90
1
Rev
0A
of
Page 61
5
4
3
2
1
Thermtrip Ckt
D D
C3251
0.1u
P3V3_AUX
R3182 10K
C3221
0.1u
R3179
4.7K
U3031
1
C1_#
2
D1
3
CK1
4
S1_#
5
Q1
6
Q1_# GND7Q2_#
74LCX74MX
VCC
C2_#
CK2
S2_#
SWITCH
R3181
Q3021
4.7K
R3183
B
E C
4.7K
FSB1_THERMTRIP_N 12
14 13 12
D2
11 10 9
Q2
8
P3V3_AUX
THERM_PRE_SET# THERMTRIP1_N
R3312 10K-0402
G
Q3029 2N7002
SOT23SGD
DS
MMBT3904
SWITCH77
P3V3 P3V3
THERM_PRE_SET#
R3178
4.7K
C C
FSB0_THERMTRIP_N9
R3180
4.7K
Q3019
B
MMBT3904
E C
D S
Q3028 2N7002
SOT23SGD
G
THERMTRIP0_N
R3311 10K-0402
THERMTRIP0_N, THERMTRIP1_N 1: NORMAL
0: THERMALTRIP ASSERT
THERMTRIP0_N54 THERMTRIP1_N54
THERM_PRE_SET#54
B B
THERMTRIP0_N THERMTRIP1_N THERM_PRE_SET#
DS
Q3030 2N7002
G
SOT23SGD
THERMTRIP_N 40
Q3031 2N7002
SOT23SGD
DS
G
A A
Title Document Number
5
4
3
2
Micro Star Restricted Secret
Thermtrip Ckt
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
61 90
1
Rev
0A
of
Page 62
5
4
3
2
1
CPU BSEL Level Translation
P_VTT
P3V3
D D
GTL+ to TTL Translator
U16
FSB0_BSEL09 PLD_CPU0_BSEL0 63 FSB0_BSEL19 FSB0_BSEL29
FSB0_GTL_IERR#9
C C
FSB1_BSEL012 FSB1_BSEL112 FSB1_BSEL212
FSB1_GTL_IERR#12
B B
FSB0_BSEL0 FSB0_BSEL1 PLD_CPU0_BSEL1# FSB0_BSEL2
P_VTT
P_VTT
R1264
49.9RST
R1265 100RST
R1248
49.9RST
R1255 100RST
C1408 1u
FSB1_BSEL0 FSB1_BSEL1 FSB1_BSEL2
C1406 1u
R1263
1K
R1254
1K
2
A0
3
A1
5
A2
6
A3
1
DIR
4
GTLREF
DIR
A
L B = A
Inputs
2
A0
3
A1
5
A2
6
A3
1
DIR
4
GTLREF
VCC3
GND1 GND2 GND3
GTL2005
B
U86
VCC3
GND1 GND2 GND3
GTL2005
13
B0
12
B1
10
B2
9
B3
14
7 8 11
13
B0
12
B1
10
B2
9
B3
14
7 8 11
R1259 1K R1260 1K R1261 1K R1262 1K
PLD_CPU0_BSEL2 63 FSB0_TTL_IERR# 54
P3V3
C1405
0.1u
PLD_CPU0_BSEL1#
R1279
1K
G
For EPLD Reversed CPU0_BSEL1
P3V3
R1256 1K R1257 1K R1252 1K R1258 1K
PLD_CPU1_BSEL0 63 PLD_CPU1_BSEL1 63 PLD_CPU1_BSEL2 63 FSB1_TTL_IERR# 54
P3V3
C1407
0.1u
CPU0_SKTOCC#9,54,63,65
P3V3
R1278 1K
DS
Q40 2N7002
SOT23SGD
PLD_CPU0_BSEL1 63
R3443
0
CPU_BSEL058,59
P_VTT
CPU_BSEL158
P_VTT
CPU_BSEL258
P3V3
R1214
4.7K
DS
Q30 2N7002
G
SOT23SGD
R1363 1K
CPU_BSEL0
R1364 1K
CPU_BSEL1
R1365 1K
CPU_BSEL2
CPU0_SKTOCC FSB1_BSEL1 CPU_BSEL1 CPU0_SKTOCC# FSB0_BSEL1 CPU_BSEL1
CPU0_SKTOCC# FSB0_BSEL2 CPU_BSEL2
CPU0_SKTOCC
FSB1_BSEL2 CPU_BSEL2
P1V5
P1V5
P1V5
R1130 1K
R1129 1K
R1366 470
R1132 1K
R1131 1K
R1367 470
R1134 1K
R1133 1K
R1368 470
1 2 3 4 5 6 7
1 2 3 4 5 6 7
B
B
B
U89
1OE
VCC 1A 1B 2OE 2A 2B GND
SN74CBTLV3125
U90
1OE
VCC 1A 1B 2OE 2A 2B GND
SN74CBTLV3125
4OE
3OE
4OE
3OE
E C
E C
E C
4A 4B
3A 3B
4A 4B
3A 3B
B
Q112 MMBT3904
B
Q114 MMBT3904
B
Q116 MMBT3904
14 13 12 11 10 9 8
14 13 12 11 10 9 8
Q111 MMBT3904
E C
Q113 MMBT3904
E C
Q115 MMBT3904
E C
P3V3
CPU0_SKTOCC# FSB0_BSEL0 CPU_BSEL0 CPU0_SKTOCC FSB1_BSEL0 CPU_BSEL0
P3V3
MCH_SEL0 15
MCH_SEL1 15
MCH_SEL2 15
OE#
Function
L A = B
XH
A A
Title Document Number
5
4
3
2
Micro Star Restricted Secret
CPU BSEL Level Translation
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
62 90
1
Rev
0A
of
Page 63
5
EPLD and RSMRST#
R1343 1K
R1358 X_1K
B
R1344 1K
R1357 X_1K
P3V3P3V3P3V3
P3V3
3 37 55
30 29 28
39 42 38 36 35 33 27 25 24 22 20 19 17 16 11 15 10
9 59
58 52 51 47 46 40 34 32
21 41 54
R1101 10K
VTT_PWRGD_3_3V
Q85 MMBT3904
E C
XC9536XL_C
VCCINT1 VCCINT2 VCCIO
TCK TMS TDI
IO117 IO116 IO115 IO114 IO113 IO112 IO111 IO110 IO19 IO18 IO17 IO16 IO15/GCK3 IO14/GCK2 IO13 IO12/GCK1 IO11 IO10
NC NC NC NC NC NC NC NC NC
GND2 GND1 GND0
PLD_VTT_PWRGD_3_3V
D D
EPLD_TCK EPLD_TMS
CPU1_SKTOCC#12,54,65
VRM1_PWRGD71
VRD0_EN69
VRM0_PWRGD69
PLD_CPU0_BSEL262 PLD_CPU0_BSEL162 PLD_CPU0_BSEL062 PLD_CPU1_BSEL262 PLD_CPU1_BSEL162 PLD_CPU1_BSEL062
SUSCLK40
IDE_RSTDRV#67
C C
B B
PLD_33MHZ_CLK58
PLTRST_N20,37
P_VTT_PWRGD76
P1_MS_ID0R
R1356 1K
R1099
1.6K
R1359
R1360
1K
1K
P3V3 P_VTT
R1100 10K
Q84
B
MMBT3904
E C
TDO
IO217 IO216 IO215 IO214 IO213 IO212 IO211 IO210
IO29 IO28 IO27 IO26
GSR/IO25
GTS2/IO24
IO23
GTS1/IO22
IO21 IO20
NC NC NC NC NC NC NC NC NC
XC9536XL_C
U83
4
53 49
43 44 45 48 50 56 57 60 61 62 63 64 2 6 5 7 8
26 31 23 18 14 13 12 4 1
P3V3 P3V3P3V3
R1375 10K
SYS_PWRGD#
EPLD_DEBUG1
SYS_PWRGD_BUFF1#
EPLD_DEBUG2
R1201
B
1.6K
R1346
R1347
10K
10K
R1656
R1658
X_1K
X_1K
PLTRST_BUFF2# SYS_PWRGD_BUFF
R1199 330
Q104 MMBT3904
E C
P3V3
B
R3444 X_10K
R1659 1K
P_VTT
R1200 X_150
Q105 MMBT3904
E C
R1657
R1617
1K
10K
R1361 0 R1362 X_0
P3V3
P3V3P3V3 P3V3
3
EPLD_TDOEPLD_TDI VTT_PWRGD_3_3V
P1_MS_ID1R P0_MS_ID0R
P0_MS_ID1R PLD_VTT_PWRGD_3_3V
PLD_SYS_PWRGD PLTRST_BUFF2#
R1281
R1654
20K
1K
R1402 1K
VTT_PWRGD 10,13
R1403 X_620
FSB0_VIDSEL9,69 FSB1_VIDSEL12,71
R1655 1K
PCIE_RST# 50,51
FSB0_VIDSEL FSB1_VIDSEL
CPU0_SKTOCC# 9,54,62,65VRD1_EN71
MCH_FSB_SLWCTRL# 16
SYS_PWRGD_BUFF 40,66
ESB_PLTRST# 38 PLTRST_BUFF1# 45,53,67
PS_PWRGD_N 54,55,68 CPU_VRD_PWRGD 40,58,60
SYS_RESET_N54
2
P3V3
R3177
4.7K
G
1 2
U3021
1 2 3
GND
74LVC1G08
P3V3
DS
P3V3
VCC
R920
10K
SOT23SGD
Q48 2N7002
5
U131
4
74LVC1G32GV
3
P0_MS_ID0R P0_MS_ID1R
P1_MS_ID0R P1_MS_ID1R
P3V3
5 4
R1341 1K
R1349 1K
P3V3
5
U130
1 2
NC7S86_SC70
CPU0_SKTOCC# CPU1_SKTOCC#
R3352 0
PLD_SYS_PWRGDG SYS_PWRGD_3_3V
4
3
P3V3
5
1 2
74LVC1G32GV
3
PLD_SYS_PWRGD
P3V3P3V3
R1342 1K
R1345 0 R1348 0
P3V3P3V3
R1350 1K
U132
4
R1351 0 R1352 0
1
P3V3
U129
53
1 2
74AHC1G08
R868 X_0_0402
P0_MS_ID0 9 P0_MS_ID1 9
P1_MS_ID0 12 P1_MS_ID1 12
SYS_PWRGD_3_3V 20,35,37,40,50,77
PLD_SYS_PWRGDG
4
P3V3
J6
1
P3V3_AUX
A A
C3126
0.1u
R3158 22K
C3127 1u
RSMRST# CKT
P3V3_AUX
147
U91C
5 6
74LVC14A_SOIC14
5
P3V3_AUX
147
U91D
9 8
74LVC14A_SOIC14
C3243 X_103P
R3162 10K
RSMRST# 40,47,57
4
2 3 4 5 6
X_H1X6_black
R1353 1K
R1354 1K
R1355 1K
EPLD_TCK EPLD_TDO EPLD_TDI EPLD_TMS
3
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
2
http://www.msi.com.tw
EPLD and RSMRST#
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
63 90
Rev
0A
of
Page 64
5
4
3
2
1
Extended Debug Port
D D
P_VTT P_VTT
U84
1
VSS
FSB1_BPM_N512,16 FSB1_BPM_N412,16
FSB1_BPM_N312 FSB1_BPM_N212
FSB1_BPM_N112 FSB1_BPM_N012
FSB1_BPMB_N312
C C
B B
FSB1_BPMB_N212 FSB1_BPMB_N114
FSB1_BPMB_N014
CPU_PWRGD9,12,40
XDP0_33MHZ_CLK58
P3V3
R1242 330RST
R1243 330RST
XDP0_TCK120 XDP0_TCK09,12
SMBDAT_MAIN SMBCLK_MAIN
SMBDAT_MAIN58,59,60,69,74 SMBCLK_MAIN58,59,60,69,74
R1376 0
C1404
0.1u
XDP0_CLKREF
R3448 X_0 R3449 X_0
CPU1 Isolation Jumper
Place jumper on pins 2 & 3 To isolate CPU1 from scan chain
Place jumper on pins 1,2 and 3,4 To include CPU1 in the scan chain
3
BPM5#
5
BPM4#
7
VSS
9
BPM3#
11
BPM2#
13
VSS
15
BPM1#
17
BPM0#
19
VSS
21
BPM5#1
23
BPM4#1
25
VSS
27
BPM3#1
29
BPM2#1
31
VSS
33
BPM1#1
35
BPM0#1
37
VSS
39
PWRGD
41
NC
43
VTT
45
NC
47
NC
49
VSS
51
SDA
53
SCL
55
TCK1
57
TCK0
59
VSS
RESET_IN#
RESET_OUT#
CPU0 Isolation Jumper
Place jumper on pins 2 & 3 To isolate CPU0 from scan chain
Place jumper on pins 1,2 and 3,4 To include CPU0 in the scan chain
A A
5
4
VSS
VSS
VSS
VSS
VSS
VSS
VSS ITP_CLKP ITP_CLKN
VTT
VSS
TDO
TRST#
TMS
VSS
XDP
2 4
NC
6
NC
8 10
NC
12
NC
14 16
NC
18
NC
20 22
NC
24
NC
26 28
NC
30
NC
32 34
NC
36
NC
38 40 42 44
FSB1_RESET_N_R
46 48 50 52 54 56
TDI
58 60
P_VTTP_VTT
R1236 51
J4
1
YJ104
J5
YJ104
2 3 4
1 2 3 4
XDP0_TDO_MAIN
XDP0_TDI_MAIN_JMP
XDP0_TDI_MAIN
FSB0_BPM_N5 9,15 FSB0_BPM_N4 9,15
FSB0_BPM_N3 9 FSB0_BPM_N2 9
FSB0_BPM_N1 9 FSB0_BPM_N0 9
FSB0_BPMB_N3 9 FSB0_BPMB_N2 9
FSB0_BPMB_N1 11 FSB0_BPMB_N0 11
XDP0_BCLK_P 59
R695 1K
XDP0_TDO_MAIN XDP0_TDI_MAIN
Place R1236 and R1237 within 1" 0f CPU0 and CPU1.
R1237 51
XDP0_BCLK_N 59 FSB1_RESET_N 12,16
CPU_DBR_RST# 9,12
XDP0_TRST# 9,12,20 XDP0_TMS_MAIN 9,12,20
XDP0_TDI_FSB1 12 XDP0_TDO_MAIN 20
XDP0_TDO_FSB1 12
XDP0_TDI_FSB0 9 XDP0_TDI_MAIN 20
XDP0_TDO_FSB0 9
3
N33-1020351-H06
N33-1020351-H06
Place pull-up resistors close to CPU.
R1238 51
P_VTT
R1240 51 R1239 51 R3344 51
J4_(1-2)
J5_(1-2)
J4_(3-4)
N33-1020351-H06
J5_(3-4)
N33-1020351-H06
2
XDP0_TMS_MAIN
XDP0_TCK1 XDP0_TCK0 XDP0_TRST#
Place resistors atend of each clock chain.
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
Extended Debug Port
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
64 90
of
Rev
0A
Page 65
5
Hardware monitor
RN37
CPU1_DISABLE_N12,54 CPU0_DISABLE_N9,54
D D
C C
B B
A A
CPU1_SKTOCC#12,54,63 CPU0_SKTOCC#9,54,62,63
CPU0_SKTOCC# CPU1_SKTOCC# CPU0_DISABLE_N CPU1_DISABLE_N
5
1 2 3 4 5 6 7 8
X_8P4R-0
1 2 3 4 5 6 7 8
X_8P4R-0
P3V3_AUX
P3V3_AUX
CPU1_DISABLE_N_ADT CPU0_DISABLE_N_ADT CPU1_SKTOCC#_ADT CPU0_SKTOCC#_ADT
RN38
CPU0_SKTOCC#_PCA CPU1_SKTOCC#_PCA CPU0_DISABLE_N_PCA CPU1_DISABLE_N_PCA
R3140 X_4.7K R3141 0
ADDR pull high >> SMB 2.0 pull low >> 0X58H NC >> 0X5CH
R3143 X_4.7K R3144 X_0
FANTACH967 FANTACH1067 SMBCLK_HM54,66 SMBDAT_HM54,66
HWM_RST#
P0THERMDA9 P0THERMDC9
FANTACH1367 FANTACH1467
HWM_RST#
P1THERMDA12 P1THERMDC12
CPU0_SKTOCC#_ADT CPU1_SKTOCC#_ADT
SMBCLK_HM SMBDAT_HM HM_ADD0
R1333 X_0_0402
P0THERMDA P0THERMDC
HM_ADD0
SMBCLK_HM SMBDAT_HM HM_ADD1
R1334 X_0_0402
P1THERMDA P1THERMDC
HM_ADD1
4
CPU0_SKTOCC#_PCA CPU1_SKTOCC#_PCA CPU0_DISABLE_N_PCA CPU1_DISABLE_N_PCA
P3V3_AUX
1
TACH1/GPIO1/VID1
2
TACH2/GPIO2/VID2
3
TACH3/GPIO3/VID3
4
TACH4/GPIO4/VID4
5
VCC
6
GND
7
12V1/TACH5
8
12V2/TACH6
9
SCL
10
SDA
11
ADD
12
ALERT#
13
PWM4/3.3V
14
RESET#
15
D1+/2.5V/1.8V
16
D-/SCSI_Term1
P0THERMDA P0THERMDA2
C3114 X_100P
P0THERMDC
P3V3_AUX
1
TACH1/GPIO1/VID1
2
TACH2/GPIO2/VID2
3
TACH3/GPIO3/VID3
4
TACH4/GPIO4/VID4
5
VCC
6
GND
7
12V1/TACH5
8
12V2/TACH6
9
SCL
10
SDA
11
ADD
12
ALERT#
13
PWM4/3.3V
14
RESET#
15
D1+/2.5V/1.8V
16
D-/SCSI_Term1
P1THERMDA P1THERMDA2
C3116 X_100P
4
U2
1 2 3 4 5 6 7 8
9 10 11 12
PCA9555
PWM2/GPIO6/VID6 PWM1/GPIO5/VID5
THERM2#/1.5V/GPIO8
THERM1#/1.5V/GPIO7/VID7
VR_HOT2/1.2V/VBATT
VR_HOT1/1.2V/3.3V Vccp2/1.5V/1.8V/2.5V Vccp1/1.5V/1.8V/2.5V
GND
33
C3115 X_100P
P0THERMDC2
PWM2/GPIO6/VID6 PWM1/GPIO5/VID5
THERM2#/1.5V/GPIO8
THERM1#/1.5V/GPIO7/VID7
VR_HOT2/1.2V/VBATT
VR_HOT1/1.2V/3.3V Vccp2/1.5V/1.8V/2.5V Vccp1/1.5V/1.8V/2.5V
GND
33
C3117 X_100P
P1THERMDC2P1THERMDC
INT# A1 A2 I/O0_0 I/O0_1
I/O1_7
I/O0_2
I/O1_6
I/O0_3
I/O1_5
I/O0_4
I/O1_4
I/O0_5
I/O1_3
I/O0_6
I/O1_2
I/O0_7
I/O1_1
GND
I/O1_0
PWM3
FAN2MAX#/CI
TACH8/+12V3
TACH7/+5V
D3-/SCSI_Term2
D3+/1.25V/0.9V
ADT7462
PWM3
FAN2MAX#/CI
TACH8/+12V3
TACH7/+5V
D3-/SCSI_Term2
D3+/1.25V/0.9V
ADT7462
VCC
SDA SCL
A0
U3014
D2+
U3015
D2+
24 23 22 21 20 19 18 17 16 15 14 13
D2-
SYS_DN0
SYS_DP0
D2-
SYS_DN1
SYS_DP1
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
3
SMBDAT_HM SMBCLK_HM
R3204 0 R3139 1K
SYS_DN0
SYS_DP0 P0THERMDC2 P0THERMDA2
FANTACH16
SYS_DN1
SYS_DP1
P1THERMDC2 P1THERMDA2
3
P3V3_AUX
CPU1_DISABLE_N_ADT CPU0_DISABLE_N_ADT
FSB0_PROCHOT#
VBAT_HM P3VSB
AIN_P5VSB 54
VCORE0
FANTACH12 67 FANTACH11 67
P0THERMDC2 9 P0THERMDA2 9
C3224 102P
R3463 R3142 1K
C3225 102P
Q3033 2N3906S
0
FSB1_PROCHOT#
P3V3_AUX P1V5 VCORE1
FANTACH15 67 FANTACH16 67
P1THERMDC2 12 P1THERMDA2 12
Q3034 2N3906S
P3V3_AUXP3V3_AUX
R1091 1K
FSB0_PROCHOT# 9
R1092 1K
FSB1_PROCHOT# 12 INTRUSION_N 39,50,54
2
P3V3_AUX
SMBCLK_HM SMBDAT_HM
FAN_F1_N67 FAN_F2_N67
U3017
1
SCL
2
SDA
3
A0
4
A1
5
A2
6
I/O0
7
I/O1 GND8I/O2
PCA9557
VCC
RESET
I/O7 I/O6 I/O5 I/O4 I/O3
16 15 14 13 12 11 10 9
P3V3_AUX
R3167
4.7K
1
FAN_F8_N 67 FAN_F7_N 67 FAN_F6_N 67 FAN_F5_N 67 FAN_F4_N 67 FAN_F3_N 67
SMBUS ADDR: 0X30
P3V3_AUX
VCC
RESET
I/O7 I/O6 I/O5 I/O4 I/O3
P3V3_AUX
16 15 14 13 12 11 10 9
FAN_F16_N 67 FAN_F15_N 67 FAN_F14_N 67 FAN_F13_N 67 FAN_F12_N 67 FAN_F11_N 67
R6 10K
SMBCLK_HM SMBDAT_HM
FAN_F9_N67
FAN_F10_N67
U3018
1
SCL
2
SDA
3
A0
4
A1
5
A2
6
I/O0
7
I/O1 GND8I/O2
PCA9557
SMBUS ADDR: 0X32
FRU EEPROM
P3V3_AUX P3V3_AUX
R3268 220
U3023
1
A0
2
A1
3
A2
4
GND
24C02
VCC
MODE
SCL SDA
8 7 6 5
SMBUS ADDR: 0XAE
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
2
http://www.msi.com.tw
Hardware monitor
SMBCLK_HM SMBDAT_HM
R3269 220
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
C3211
0.1u
65 90
Rev
0A
of
Page 66
5
4
3
2
1
PECI Poller
P3V3
U120
C460
D D
PECIPIN4 PECIPIN12
P3V3
P3V3 P3V3 P3V3
C484 X_0.1u
U122
1
NC
C C
SMBCLK_HM54,65 SMBDAT_HM54,65
SMBCLK_HM SMBDAT_HM
2 3
PCA9515
VCC
SCL0
SCL1
SDA0
SDA1
GND4EN
SMBus Voltage Translation
R1315
5.1K
8 7 6 5
SMBCLK_PECI SMBDAT_PECI
R1306
0
SMBCLK_PECI67 SMBDAT_PECI67
SYS_PWRGD_BUFF
R1318
R1317
5.1K
5.1K
SMBCLK_PECI SMBDAT_PECI
SYS_PWRGD_BUFF 40,63
PECI Circuit 1
RN46
B
PECI_IO PECI_OUT PECI_IN
P3V3
Q3036 X_MMBT3904
E C
R474 X_10K
R475 X_10K
P_VTT
C3279 X_22u-1206
4
PECI_IO_OP2 PECIPIN4 PECIPIN12
B B
A A
P3V3
R472 X_10K
R473 X_10K
P3V3
3
+
2
-
U125A
4 8
X_TLV2362IDR_SOIC8
1 2 3 4 5 6 7 8
X_0-8P4R
1
RESERVED
5
X_0.1u
PECI_IO_OP2
16
VDD
1
A,I,M,P0[7]
2
A,I,M,P0[5]
3
A,I,M,P0[3]
4
A,I,M,P0[1]
5
SMP
7
M,I2C_SCL,P1[1]
P_VTT
R500
X_4.22KST
P1[0],I2C_SDA,M
VSS
VSS
6
8
R495 X_20.5KST-0402
R497 X_20.5KST-0402
P0[6],A,I,M P0[4],A,I,M P0[2],A,I,M P0[0],A,I,M
P1[4],EXTCLK,M
P1[2],M
X_CY8C21234
P3V3
5
+
6
-
4 8
R498
X_20.5KST-0402
X_MMBT3904
15 14 13 12 11
PECIPIN10
10 9
C483 X_0.1u
PECI_IN
7
U125B X_TLV2362IDR_SOIC8
P_VTT
R499 X_1.21KST
Q3037
B
E C
3
R477
X_10K
R467 X_10K
C3278 X_22u-1206
R476 X_10K
C469 X_0.1u
PECI_OUT
P3V3
5
Vcc
4
Control
X_HD74LV1G66ACME_SC70-5
P_VTT
U121
IN/OUT OUT/IN
Gnd
1 2 3
PECI_IO
R1305
X_0
PECI Trace IMPEDANCE 50 ohms+/-15% Width 4 mils, Spacing 10 mils, Microstrip, <15"
PECI Circuit 2
PECIPIN4 PECIPIN12 PECI_LO_COMP PECI_IO_COMP PECIPIN10
PECI_LO_COMP
PECI_IO_COMP
PECI_HI_COMP
2
RN44
1 2 3 4 5 6 7 8
X_0-8P4R
P_VTT
R471 X_54.9KST
R469 X_10K
R468 X_10K
R470 X_64.9KST
Title Document Number
PECI_HI_COMP PECI_IO
PECI_OUT
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
RSVD_PECI 11,14,55
R1299 X_330
Micro Star Restricted Secret
PECI Poller
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
66 90
of
Rev
0A
Page 67
5
4
3
2
1
Back Panel Connector
LPC Debug Port
D D
Avoid CD-ROM can't detect
P5V
R3474
4.7K
PD_IOW#39
SGPIO_DIN54 SGPIO_DOUT54
ESB_SYS_RST#9,40,54,68
R3112
X_4.7K R3119
PD_IOR#39
PD_DREQ39
PD_DACK#39
IRQ1438
PD_IORDY39
PD_A139 PD_A039
PD_CS#139
FANTACH355 FANTACH1165 FANTACH1265 FANTACH1365
RAID_SEL38
2.5HD_SEL38
FANTACH1465 FANTACH1565
FANTACH1665
PWR_BT_IN#54,68
DUMP_SSI68
ID_F_N68
FAN_F9_N65
FAN_F10_N65
1K
R3111 100
LANA_ACT_A49 LANA_ACT_C49SMBDAT_PS54,68
1U_2U_SEL38 LANB_ACT_A49 LANB_ACT_C49
1U_2U_SEL
IDE_PRI_CBLSNS
ID_LED_A
C C
B B
A A
IDE_RSTDRV#63
GPO of BMC
SYSRDY_LED54
R975 X_0
SMBDAT_PECI66
SMBCLK_PS54,68
SMBCLK_PECI66
R978 0 R976 X_0 R964 0
P3V3
P5VSB
5
Back Panel Connector
U3000
1
101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139
1
3
3
5
5
7
7 9910 111112 131314 151516 171718 191920 212122 232324 252526 272728 292930 313132 333334 353536 373738 393940 414142 434344 454546 474748 494950 515152 535354 555556 575758 595960 616162 636364 656566 676768 696970 717172 737374 757576 777778 797980 818182 838384 858586 878788 898990 919192 939394 959596 979798 9999100 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139
102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140
140pIN
PDD[15..0]
4
PDD7 PDD6 PDD5 PDD4 PDD3 PDD2 PDD1 PDD0
SGPIO_DIN SGPIO_DOUT
FDD_OC_N
HDD_LED_C
STATE_LED_1 STATE_LED_2
ID_LED_A ID_LED_C
POWER_LED_N
1U_2U_SEL
R337
10K-0402
2
2
4
4
6
6
8
8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140
PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15
IDE_PRI_CBLSNS
SGPIO_CLK SGPIO_LOAD
USB_FDD_P USB_FDD_N
PDD[15..0] 39
USB_FDD_N USB_FDD_P
USB_TYPE_N68 USB_TYPE_P68
IDE_PRI_CBLSNS 45 PD_A2 39 PD_CS#3 39
CONB_DCD 55 CONB_TXD 55 CONB_RTS 55 CONB_RI 55 CONB_RXD 55 CONB_DTR 55 CONB_DSR 55 CONB_CTS 55
FAN_F11_N 65 FAN_F12_N 65 FAN_F13_N 65 SGPIO_CLK 54 SGPIO_LOAD 54
FAN_F14_N 65
FAN_F15_N 65 FAN_F16_N 65
FANTACH6 55 FANTACH5 55
FPWM_CPU 56 FANTACH2 55 FPWM_PWR 56 FANTACH1 55 FPWM_MEM 56 FANTACH4 55
FANTACH8 55 FANTACH7 55
FANTACH9 65 FANTACH10 65 FAN_F3_N 65 FAN_F6_N 65 FAN_F5_N 65 FAN_F2_N 65 FAN_F1_N 65 FAN_F4_N 65 FAN_F8_N 65 FAN_F7_N 65
HDD_LED_C
GPO of BMC
3
P3V3
RAID_SEL
P3V3
P3V3
PLED40
R3468 X_1K
01Normal
R3120 10K
BN3
8 7 6 5
R3302 4.7K-0402
1 2 3 4
X_90_COMM RN42
12 34 56 78
0-8P4R
JP2
1 2 3
X_N31-1030011-H06
JP2_1-2 X_N33-1020331-H06
SW-Raid
D3002
3
BAT54A-S-SOT23
G
R3147
0
SATA_LED_N
POWER_LED_N
DS
Q3025 2N7002
SOT23SGD
USB_OC#0FDD_OC_N
GPO of BMC
SYS_ID_LED_N54
2 1
SATA_LED_N 39
LAD040,45,53 LAD140,45,53 LAD240,45,53 LAD340,45,53
USBP6N 40 USBP6P 40 USBP7N 40 USBP7P 40
USB_OC#0 40
FSB_INIT#9,12,40
2
J3002
1 3 5 7 9
R3278
B
4.7K
P5VSB
R3159
0
G
GPO of BMC
COOL_FLT_LED54
SYS_FLT_LED54
P3V3
R3276
4.7K
Q3023 MMBT3904
E C
R3118 330
D3003 LED
ID_LED_C
Q3011 X_2N7002
SOT23SGD
2 4 6
8 10 12
2 4
FSB_TTL_INIT#
6 8 10 12
P3V3
B
1 2 3
R3277
4.7K
E C
U3030
GND
7432
1 3 5 7 9
D2X6-BK
21
DS
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
PLTRST_BUFF1# 45,53,63 LFRAME# 40,45,53
DEBUG_33MHZ_CLK 58
Q3022 MMBT3904
P5VSB
R3121 330
12
D3015 LED
P3V3_AUX
VCC
5
STATE_LED_1
4
Back Panel Connector
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
67 90
of
Rev
0A
Page 68
5
Power Connector and NMI
D D
C C
P5VSB P3V3 P-12V P12V
C3081
C3082
0.1u
C3086
0.1u
R1090
4.7K
P3V3_AUX
C3083
0.1u
P3V3_AUX
B
0.1u
P5V P12V_CPU1 P12V_CPU0
C3085
0.1u
P3V3_AUX
R1088
4.7K
ONCTL#54
C3088
0.1u
C3084
0.1u
R1085
4.7K
Q81 MMBT3904
E C
P12V_CPU0
P12V_CPU1
P5VSB
R1086
4.7K
Q80
B
MMBT3904
E C
NMI Button
P3V3_AUX
5
R3099
147
1 2
C3091 103P
U3010A
74LVC14A_SOIC14
DUMP_SSI 67
4.7K
From Front Side
P3V3_AUX P3V3_AUX
R3103
4.7K
C3093 103P
147
U3010C
5 6
74LVC14A_SOIC14
ID_F_N 67
From Front Side
JNMI1
2 3
B B
41
PUSH BUTTON
System REAR Side
JID3000
2 3
41
A A
PUSH BUTTON
System REAR Side
Power Connector
P12V
P3V3
P5VSB
PS_PWROK
PS_ON#
C21
0.1u
P3V3_AUXP3V3_AUX
147
U3010B
3 4
74LVC14A_SOIC14
147
U3010D
9 8
74LVC14A_SOIC14
4
JPWR1
1
12V3
GND
2
12V3
GND
3
12V2
GND
4
12V2
5
12V1
6
12V1
GND
7
3.3V
GND
8
3.3V
-12V
9
GND
3.3V
10
5VSB
GND
11
PWOK
GND
12
PSON
GND
POWERCONN
NMI_BTN_N 54
GPI of BMC
ID_BTN_N 54
4
3
JFAN4
3
P12V P12V P12VP12V
2 1
(BH1X3B_white )
13 14 15 16
5V 5V
P5V
17
P5V
18 19 20
P-12V
21
P3V3
22 23 24
PS_PWROK
P5V
USB_OC#440
P5V
R1216 1K
C1381 103P
JFAN3
3 2 1
(BH1X3B_white )
F3001 2A6V
R3094 2.7K
R3095
5.1K
P3V3_AUX
147
U91E
11 10
74LVC14A_SOIC14
Front USB Header
JFAN2
3 2 1
(BH1X3B_white )
USBPWR45
12
+
EC3001 1000u-6.3V
P3V3_AUX
147
U91F
13 12
74LVC14A_SOIC14
PS_PWRGD_N 54,55,63
USB4N
C3087
0.1u
PS_PWROK_BUF 54,58,75
JFAN1
(BH1X3B_white )
3 2 1
JUSB3001
1 3 5 7
CON10B-9
2
USB4N USB4P USB5P USB5N
2
USB5N
4
USB5PUSB4P
6 8
10
RN45
0-8P4R BN2
8 7 6 5
X_90_COMM
1
12 34 56 78
1 2 3 4
USBP4N 40 USBP4P 40 USBP5P 40 USBP5N 40
Internal USB Connector For TYPE
USB_TYPE_N67 USB_TYPE_P67
USBPWR45
JUSB3002
1 2 3 4
BH1X4
Power Button
Power SMBUS Connector
C3212 22P
P5VSB
R3271
5.6K
C3213 22P
PS_ALERT_N
P3V3_AUX
R3272
5.6K
PS_ALERT_N
P3V3
R3132 1K
J3003
1
1
2
2
3
3
4
4
5
5
MOLEX-0520
PS_ALERT_N 54
P3V3_AUX
P3V3_AUX
R3270
U3024
1
NC
VCC
SMBCLK_PS54,67 SMBDAT_PS54,67
2
SCL0
3
SDA0 GND4EN
PCA9515
SCL1 SDA1
5.6K
8 7 6 5
IPMB Connector
P3V3_AUX
VCC
SCL1
SDA1
P3V3_AUX
U3025
1
NC
SMBCLK_IPMB54 SMBDAT_IPMB54
2 3
PCA9515
SCL0
SDA0
GND4EN
R3273
5.6K
8 7 6 5
P5VSB
R3350
R3349
5.6K
5.6K
C3215
C3214
22P
22P
3
J_IPMB
3 2 1
N32-1030321-M06
P3V3_AUX
R3098
JPBT3000
2 1
YJ102
1K
PWR_BT# PWR_BT_IN#
C3090 1u
Reset Button
P3V3_AUX
R3100
JRST3000
2 1
YJ102
1K
RST_BT#
C3092 1u
2
147
U3011A
1 2
74LVC14A_SOIC14
147
U3011C
5 6
74LVC14A_SOIC14
P3V3_AUXP3V3_AUX
147
U3011B
3 4
74LVC14A_SOIC14
R1379 X_0
PWR_BT# RST_BT#
R1388 X_0
P3V3_AUXP3V3_AUX
147
U3011D
9 8
74LVC14A_SOIC14
ESB_SYS_RST#
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
Power Connector and NMI
R3101 20K
PWR_BT_IN# ESB_SYS_RST#
R3102 20K
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
PWR_BT_IN# 54,67
ESB_SYS_RST# 9,40,54,67
68 90
1
of
Rev
0A
Page 69
5
4
3
2
1
CPU0 VREG1 VT1115M
P0VID[6..0]
D D
VCORE_EN High(>1.24V) VRM Enable
R941 249RST
C1223 680P
C1240 X_103P
R946 X_10K
C1241 X_103P
FSB0_VIDSEL
5
C C
B B
A A
FSB0_VIDSEL9,63
R944 499RST
R947 649RST
VRD0_EN63
R1667 1K
R1673 620
R3137
1K
VRD0_EN P0VID7 P0VID6 P0VID5 P0VID4 P0VID3 P0VID2 P0VID1 P0VID0
10u-0805C1202
P0OVP+ P0OVP­P0OVP_OUT
6800pC1205
VCC0_SENSE VSS0_SENSE
P0VR_HOT P0VR_FAN P0FAULTB
P5V
B
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
R1668 1K
Q39 MMBT3904
E C
OE VID<7> VID<6> VID<5> VID<4> VID<3> VID<2> VID<1> VID<0> VDD GND OVP+ OVP­OVP_out Vnom+ Vnom­sense+ sense­Vamp_out1 Vamp_in Vamp_out2 Vr_Hot Vr_Fan FaultB
VDD
EXT_REF
R_sel<7> R_sel<6> R_sel<5> R_sel<4>
GND
R_ref R_sel<3> R_sel<2>
Pwrgd R_freq Vin_ov Vin_uv
Load_Current
R_sel<1>
Ides_n Ides_p
R_sel<0>
DBO
sphase
GND
VT1115M
49
G
4
U57
SC SD
DBI
G
DS
Q102 2N7002
SOT23SGD
36 47 46 45 44 43 42 41 40 39 38 37 48 35 34 33 32 31 30 29 28 27 26 25
DS
R981
11.3KST
G
P0VID[6..0] 9
P3V3P3V3
SMBCLK_1115 SMBDAT_1115
P0R_SEL7 P0R_SEL6 P0R_SEL5 P0R_SEL4
P0R_REF P0R_SEL3 P0R_SEL2
P0R_FREQ P0VIN_OV P0VIN_UV
P0R_SEL1
P0R_SEL0
R1187
2.61KST
Q101 2N7002
SOT23SGD
P0R_SEL2
P5V
R1669
4.7K
DS
Q103 2N7002
SOT23SGD
SMBCLK_1115 71 SMBDAT_1115 71
R948 X_0 R949 X_0
VRM0_PWRGD 63
R938 10K R939 0
R940 0 R942 0
R943 0
R1188
39.2KST
P0IDES_N P0IDES_P
P0DBI P0DBO P0SPHASE
P0R_SEL3
SMBCLK_MAIN 58,59,60,64,74 SMBDAT_MAIN 58,59,60,64,74
P0IDES_N 80 P0IDES_P 80
P0DBI 70 P0DBO 70 P0SPHASE 70
For 5 Phases condition:
IF VIDSEL=0 , R_SEL3=3.74K , VR10 IF VIDSEL=1 , R_SEL3=69.8K , VR11
For 6 Phases condition:
IF VIDSEL=0 , R_SEL3=2.43K , VR10 IF VIDSEL=1 , R_SEL3=39.2K , VR11
IF VIDSEL=0 , R_SEL2=11.3K , VR10 IF VIDSEL=1 , R_SEL2=340 , VR11
R980
P0R_SEL2
340RST
DS
Q106 2N7002
G
SOT23SGD
VCORE0
R933 0 R929 0
R934 0 R930 0R945 0
3
P0OVP+ VCC0_SENSE
P0OVP­VSS0_SENSE
P0VR_HOT
P12V_CPU0 P12V_CPU0
R931 100KST
P0VIN_OV
R935
C1203
10.7KST
103P
VCC0_SENSE 9
VSS0_SENSE 9
P3V3
R1209 1K
R1211
4.7K
P0VIN_UV
P3V3 P3V3
P_VTT
B
2
R932
63.4KST
R936
C1204
10KST
103P
R591
R590
2.2K
2.2K
SMBDAT_1115 SMBCLK_1115
For Volterra Debug
R1210
4.7K
Q107 MMBT3904
E C
P3V3
J11
1 2 3 4
N31-1040011-H06
FSB0_FORCEPR# 9
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
VRD0_EN
P0VID0 P0VID1 P0VID2 P0VID3 P0VID4 P0VID5 P0VID6 P0VID7
P0R_SEL7 P0R_SEL6 P0R_SEL5 P0R_SEL4 P0R_SEL1 P0R_SEL0 P0R_FREQ P0R_REF
R3446 X_10K
R955 510 R956 510 R958 510 R959 510 R960 510 R961 510 R962 510 R963 510
R965 5.9KST R966 1.02KST R973 340RST R974 3.74KST R982 340RST R983 340RST R984 26.1KST R985 11KST
Master Reported Faults
P0FAULTB P0OVP_OUT P0VR_FAN P0VR_HOT
CPU0 VREG1 VT1115M
VCORE0
MS-9192
R950 10K R952 10K R953 10K R954 10K
R937
100
Last Revision Date:
Friday, April 27, 2007
Sheet
1
P3V3
P_VTT
P3V3P3V3
69 90
of
Rev
0A
Page 70
5
P0DB4 P0DB2
CPU0 VREG2
P0S1DBI80
P0S1DBO80
P0SPHASE
D D
C C
B B
A A
P0S1PHASE80
P3V3 P3V3
C1265 1u
P0S5PHASE80
P3V3 P3V3
C1289 1u
5
C1266 1u
1uC1253
1uC1256 10u-1206C1259 10u-1206C1262
P0S5DBI80
P0S5DBO80
P0SPHASE
C1290
1u
1uC1274
1uC1277
1uC1280 10u-1206C1283 10u-1206C1286
P0S1DBI P0S1DBO
R995 1K
P0S1PHASE
P12V_CPU0
P0DBO P0DB6P0DB6
P0DBO69
P0S5DBI P0S5DBO
R1010 1K
P0S5PHASE
P12V_CPU0
R3226
X_0
R3229
0
H2H1G2D1C2
A5
VSS
A7
VSS
A9
VSS
B5
VSS
B7
VSS
B9
VSS
C5
VSS
C7
VSS
C9
VSS
D5
VSS
D7
VSS
D9
VSS
E5
VSS
E7
VSS
E9
VSS
F5
VSS
F7
VSS
F9
VSS
B3
VDDH
C3
VDDH
D3
VDDH
E3
VDDH
F3
VDDH
P3V3
R3235
X_0
R3238
0
H2
A5
VSS
A7
VSS
A9
VSS
B5
VSS
B7
VSS
B9
VSS
C5
VSS
C7
VSS
C9
VSS
D5
VSS
D7
VSS
D9
VSS
E5 D4
VSS
E7
VSS
E9
VSS
F5
VSS
F7
VSS
F9
VSS
B3
VDDH
C3
VDDH
D3
VDDH
E3
VDDH
F3
VDDH
P3V3
R3230
0
DBI
DBO
SPHASE
VCC
VDD
VDD
A2B2A1E2F1
R3239
0
H1
G2E6C2
DBI
DBO
SPHASE
VDD
VCC
VDD
A1
A2
B2
D1
P0DB3
IDESP
IDESN
IDESP
IDESN
B1
FAULTB
GND
B1
FAULTB
GND
E2
4
P0IDES_P P0IDES_N P0S1_FAULTB
A3
VX
BST
VX VX
VX VX VX
VX VX VX
VX VX VX
VX VX VX
VX VX VX
GND
P0IDES_P P0IDES_N P0S5_FAULTB
P0S5BST P0S4BST P0S3BST
A3
VX
BST
VX VX
VX VX VX
VX VX VX
VX VX VX
VX VX VX
VX VX VX
GND
F1
P0S1_FAULTB 80
P0S2DBI80
C1247
1u
C1271
1u
A4 A6 A8
B4 B6 B8
C4 C6 C8
D4 D6 D8
E4 E6 E8
F4 F6 F8
A4 A6 A8
B4 B6 B8
C4 C6 C8
D6 D8
E4 E8 F4
F6 F8
4
P0S2DBO80
P0SPHASE
P0S2PHASE80
P0VX3
P0VX3 80 P0VX2 80 P0VX1 80
P3V3 P3V3
C1268
C1267
1u
1u
1uC1251 1uC1254
1uC1257 10u-1206C1260 10u-1206C1263
P0S5_FAULTB 80 P0S5BST 80 P0S4BST 80 P0S3BST 80
P0VX6
P0S4PHASE80
P3V3 P3V3
C1291 1u
P0S4DBI80
P0S4DBO80
P0SPHASE
C1292
1u
1uC1275
1uC1278
1uC1281 10u-1206C1284 10u-1206C1287
P0DB3 P0DBI
P0S2DBI P0S2DBO
R996 1K
P0S2PHASE
P12V_CPU0
P0S4DBI P0S4DBO
R1011 1K
P0S4PHASE
P12V_CPU0
R3227
X_0
0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VDDH VDDH VDDH VDDH VDDH
0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VDDH VDDH VDDH VDDH VDDH
H2
SPHASE
R3236
X_0
H2
SPHASE
R3232
A2
R3241
A2
0
H1
DBO
VDD
VCC
B2
0
H1
DBO
VDD
VCC
B2
R3231
A5 A7 A9 B5 B7 B9 C5 C7 C9 D5 D7 D9 E5 D4 E7 E9 F5 F7 F9
B3 C3 D3 E3 F3
P3V3
R3240
A5 A7 A9 B5 B7 B9 C5 C7 C9 D5 D7 D9 E5 D4 E7 E9 F5 F7 F9
B3 C3 D3 E3 F3
P3V3
G2E6C2
D1
DBI
IDESP
VDD
A1
G2E6C2
D1
DBI
IDESP
VDD
A1
P0IDES_P P0IDES_N P0S2_FAULTB
B1
A3
BST
IDESN
FAULTB
GND
GND
E2
F1
P0DB5
P0IDES_P P0IDES_N P0S4_FAULTB
B1
A3
BST
IDESN
FAULTB
GND
GND
E2
F1
3
P0DB2
R3233
0
P0S6DBI P0S6DBO
R997 1K
P0S6PHASE
A5
VSS
A7
VSS
A9
VSS
B5
VSS
B7
VSS
B9
VSS
C5
VSS
C7
VSS
C9
VSS
D5
VSS
D7
VSS
D9
VSS
E5 D4
VSS
E7
VSS
E9
VSS
F5
VSS
F7
VSS
F9
VSS
B3
VDDH
C3
VDDH
D3
VDDH
E3
VDDH
F3
VDDH
P3V3
P0DB5
R3242
0
P0S3DBI P0S3DBO
R1012 1K
P0S3PHASE
A5
VSS
A7
VSS
A9
VSS
B5
VSS
B7
VSS
B9
VSS
C5
VSS
C7
VSS
C9
VSS
D5
VSS
D7
VSS
D9
VSS
E5 D4
VSS
E7
VSS
E9
VSS
F5
VSS
F7
VSS
F9
VSS
B3
VDDH
C3
VDDH
D3
VDDH
E3
VDDH
F3
VDDH
P3V3
C1248
1u
C1272
1u
A4 A6 A8
B4 B6 B8
C4 C6 C8
D6 D8
E4 E8 F4
F6 F8
A4 A6 A8
B4 B6 B8
C4 C6 C8
D6 D8
E4 E8 F4
F6 F8
P0S2_FAULTB 80 P0S2BST 80P0S1BST 80
P0SPHASE69
P0VX2
P3V3 P3V3
C1269 1u
P0S4_FAULTB 80
P0VX5
P3V3 P3V3
C1293 1u
P0S6DBI80
P0S6DBO80
P0SPHASE
P0S6PHASE80
C1270 1u
P12V_CPU0
1uC12521uC1250 1uC1255
1uC1258 10u-1206C1261 10u-1206C1264
P0S3DBI80
P0S3DBO80
P0SPHASE
P0S3PHASE80
C1294
1u
P12V_CPU0
1uC1276
1uC1279
1uC1282 10u-1206C1285 10u-1206C1288
P0S2BSTP0S1BST
VX VX VX
VX VX VX
VX VX VX
VX VX VX
VX VX VX
VX VX VX
VX VX VX
VX VX VX
VX VX VX
VX VX VX
VX VX VX
VX VX VX
3
R3228
X_0
H2
SPHASE
R3237
X_0
H2
SPHASE
R3234
A2
R3243
A2
VCC
VCC
0
H1
B2
0
H1
B2
2
G2E6C2
DBI
DBO
VDD
VDD
A1
G2E6C2
DBI
DBO
VDD
VDD
A1
2
D1
D1
IDESP
IDESN
P0DB4
IDESP
IDESN
P0IDES_P P0IDES_N P0S6_FAULTB
P0S6BST
B1
A3
BST
FAULTB
GND
GND
E2
F1
P0IDES_P P0IDES_N P0S3_FAULTB
B1
A3
BST
FAULTB
GND
GND
E2
F1
P0DBI 69
C1249
1u
A4
VX
A6
VX
A8
VX
B4
VX
B6
VX
B8
VX
C4
VX
C6
VX
C8
VX VX
D6
VX
D8
VX
E4
VX VX
E8
VX
F4
VX
F6
VX
F8
VX
C1273
1u
A4
VX
A6
VX
A8
VX
B4
VX
B6
VX
B8
VX
C4
VX
C6
VX
C8
VX VX
D6
VX
D8
VX
E4
VX VX
E8
VX
F4
VX
F6
VX
F8
VX
P0IDES_P 69,80 P0IDES_N 69,80 P0S6_FAULTB 80 P0S6BST 80
P0VX1
P0S3_FAULTB 80
P0VX4
P0VX4 80P0VX5 80P0VX6 80
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
1
P0VX1
1
50nH
2 3
50nH
4 5
50nH
6
L31 INDUCTOR_3_PHASE_6pin
1
50nH
2 3
50nH
4 5
50nH
6
L32 INDUCTOR_3_PHASE_6pin
P0VX2
P0VX3
P0VX4
P0VX5
P0VX6
VCORE0
VCORE0
VCORE0
VCORE0
VCORE0
VCORE0
Slave Faults
P0S1_FAULTB P0S2_FAULTB P0S3_FAULTB P0S4_FAULTB P0S5_FAULTB P0S6_FAULTB
CPU0 VREG2 VT1115S
R967 10K R968 10K R969 10K R970 10K R971 10K R972 10K
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
P3V3
70 90
of
Rev
0A
Page 71
5
4
3
2
1
CPU1 VREG1 VT1115M
P1VID[6..0]
D D
VCORE_EN High(>1.24V) VRM Enable
R289 249RST
C380 680P
C C
B B
FSB1_VIDSEL12,63
A A
C397 X_103P
R294 X_10K
C398 X_103P
FSB1_VIDSEL
5
R292 499RST
R295 649RST
VRD1_EN63
P3V3
R1650 1K
R1674 620
R3138
1K
VRD1_EN P1VID7 P1VID6 P1VID5 P1VID4 P1VID3 P1VID2 P1VID1 P1VID0
10u-0805C359
P1OVP+ P1OVP­P1OVP_OUT
6800pC362
VCC1_SENSE VSS1_SENSE
P1VR_HOT P1VR_FAN P1FAULTB
B
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
P5V
R1651 1K
Q133 MMBT3904
E C
1 2 3 4 5 6 7 8 9
OE VID<7> VID<6> VID<5> VID<4> VID<3> VID<2> VID<1> VID<0> VDD GND OVP+ OVP­OVP_out Vnom+ Vnom­sense+ sense­Vamp_out1 Vamp_in Vamp_out2 Vr_Hot Vr_Fan FaultB
VDD
EXT_REF
R_sel<7> R_sel<6> R_sel<5> R_sel<4>
GND
R_ref R_sel<3> R_sel<2>
Pwrgd R_freq Vin_ov Vin_uv
Load_Current
R_sel<1>
Ides_n Ides_p
R_sel<0>
DBO
sphase
GND
VT1115M
49
G
4
DBI
SC SD
U35
G
DS
P3V3P3V3
36 47 46 45
P1R_SEL7
44
P1R_SEL6
43
P1R_SEL5
42
P1R_SEL4
41 40
P1R_REF
39
P1R_SEL3
38
P1R_SEL2
37 48
P1R_FREQ
35
P1VIN_OV
34
P1VIN_UV
33 32
P1R_SEL1
31 30 29
P1R_SEL0
28 27 26 25
DS
11.3KST
Q121 2N7002
SOT23SGD
G
P1VID[6..0] 12
R286 10K R287 0
R288 0 R290 0
R291 0 R293 0
R1649
2.61KST
Q132 2N7002
SOT23SGD
R987
P5V
R1672
4.7K
DS
Q122 2N7002
SOT23SGD
SMBCLK_1115 69 SMBDAT_1115 69
VRM1_PWRGD 63
P1R_SEL3
R1652
39.2KST
P1IDES_N P1IDES_P
P1DBI P1DBO P1SPHASE
P1IDES_N 81 P1IDES_P 81
P1DBI 72 P1DBO 72 P1SPHASE 72
For 5 Phases condition:
IF VIDSEL=0 , R_SEL3=3.74K , VR10 IF VIDSEL=1 , R_SEL3=69.8K , VR11
For 6 Phases condition:
IF VIDSEL=0 , R_SEL3=2.43K , VR10 IF VIDSEL=1 , R_SEL3=39.2K , VR11
P1R_SEL2
IF VIDSEL=0 , R_SEL2=11.3K , VR10 IF VIDSEL=1 , R_SEL2=340 , VR11
R986
P1R_SEL2
340RST
DS
Q123 2N7002
G
SOT23SGD
P1VIN_OV
3
P12V_CPU1 P12V_CPU1
R279 100KST
P1VIN_UV
R283
C360
10.7KST
103P
VCORE1
R281 0 R277 0
R282 0 R278 0
P1OVP+ VCC1_SENSE
P1OVP­VSS1_SENSE
P1VR_HOT
VCC1_SENSE 12
VSS1_SENSE 12
P3V3
R1125 1K
R1127
4.7K
C361 103P
B
R280
63.4KST
R284 10KST
P_VTT
R1126
4.7K
E C
2
Q92 MMBT3904
FSB1_FORCEPR# 12
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
VRD1_EN
P1VID0 P1VID1 P1VID2 P1VID3 P1VID4 P1VID5 P1VID6 P1VID7
R3447 X_10K
R303 510 R304 510 R306 510 R307 510 R308 510 R309 510 R310 510 R311 510
Configuration Resistors
P1R_SEL7 P1R_SEL6 P1R_SEL5 P1R_SEL4 P1R_SEL1 P1R_SEL0 P1R_FREQ P1R_REF
R313 5.9KST R314 1.02KST R321 340RST R322 3.74KST R330 340RST R331 1.02KST R332 26.1KST R333 11KST
Master Reported Faults
P1FAULTB P1OVP_OUT P1VR_FAN P1VR_HOT
R298 10K R300 10K R301 10K R302 10K
VCORE1
R285
100
Micro Star Restricted Secret
CPU1 VREG1 VT1115M
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
P3V3
P_VTT
P3V3
71 90
of
Rev
0A
Page 72
5
P1DB4 P1DB2
CPU1 VREG2
P12V_CPU1
P1DBO71
P12V_CPU1
P1S1DBI P1S1DBO
R256 1K
P1S1PHASE
P1DBO
P1S5DBI P1S5DBO
R271 1K
P1S5PHASE
P1S1DBI81 P1S1DBO81
P1SPHASE
D D
C C
B B
A A
P1S1PHASE81
P3V3 P3V3
C329 1u
P1S5PHASE81
P3V3 P3V3
C353 1u
5
C330 1u
1uC314 1uC317
1uC320 10u-1206C323 10u-1206C326
P1S5DBI81 P1S5DBO81
P1SPHASE
C354
1u
1uC338
1uC341
1uC344 10u-1206C347 10u-1206C350
R3244
X_0
R3247
0
H2
A5
VSS
A7
VSS
A9
VSS
B5
VSS
B7
VSS
B9
VSS
C5
VSS
C7
VSS
C9
VSS
D5
VSS
D7
VSS
D9
VSS
E5 D4
VSS
E7
VSS
E9
VSS
F5
VSS
F7
VSS
F9
VSS
B3
VDDH
C3
VDDH
D3
VDDH
E3
VDDH
F3
VDDH
P3V3
R3253
X_0
R3256
0
H2
A5
VSS
A7
VSS
A9
VSS
B5
VSS
B7
VSS
B9
VSS
C5
VSS
C7
VSS
C9
VSS
D5
VSS
D7
VSS
D9
VSS
E5 D4
VSS
E7
VSS
E9
VSS
F5
VSS
F7
VSS
F9
VSS
B3
VDDH
C3
VDDH
D3
VDDH
E3
VDDH
F3
VDDH
P3V3
SPHASE
SPHASE
R3248
A2
R3257
A2
VCC
VCC
0
H1
DBO
VDD
B2
0
H1
DBO
VDD
B2
G2E6C2
D1
DBI
IDESP
VDD
A1
G2E6C2
D1
DBI
IDESP
VDD
A1
P1DB3
B1
IDESN
E2
P1DB6
B1
IDESN
E2
FAULTB
GND
FAULTB
GND
4
R257 1K
P12V_CPU1
R272 1K
P12V_CPU1
P1DB3
P1S2DBI P1S2DBO
P1S2PHASE
P1DB6
P1S4DBI P1S4DBO
P1S4PHASE
P1IDES_P P1IDES_N P1S1_FAULTB
A3
VX
BST
VX VX
VX VX VX
VX VX VX
VX VX VX
VX VX VX
VX VX VX
GND
F1
P1IDES_N P1S5_FAULTB
P1S5BST P1S4BST P1S3BST
A3
VX
BST
VX VX
VX VX VX
VX VX VX
VX VX VX
VX VX VX
VX VX VX
GND
F1
P1S1_FAULTB 81 P1S2_FAULTB 81
P1S2DBI81
C311
C335
1u
A4 A6 A8
B4 B6 B8
C4 C6 C8
D6 D8
E4 E8 F4
F6 F8
1u
A4 A6 A8
B4 B6 B8
C4 C6 C8
D6 D8
E4 E8 F4
F6 F8
4
P1S2DBO81
P1SPHASE
P1S2PHASE81
P1VX3
P1VX3 81 P1VX2 81 P1VX1 81
P3V3 P3V3
C331
C332
1u
1u
1uC315 1uC318
1uC321 10u-1206C324 10u-1206C327
P1S5BST 81 P1S4BST 81 P1S3BST 81
P1S4DBI81 P1S4DBO81
P1SPHASE
P1S4PHASE81
P1VX6
P3V3 P3V3
C355
C356
1u
1u
1uC339
1uC342
1uC345 10u-1206C348 10u-1206C351
R3245
X_0
0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VDDH VDDH VDDH VDDH VDDH
0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VDDH VDDH VDDH VDDH VDDH
H2
SPHASE
R3254
X_0
H2
SPHASE
R3250
A2
R3259
A2
0
H1
DBO
VDD
VCC
B2
0
H1
DBO
VCC
VDD
B2
R3249
A5 A7 A9 B5 B7 B9 C5 C7 C9 D5 D7 D9 E5 D4 E7 E9 F5 F7 F9
B3 C3 D3 E3 F3
P3V3
R3258
A5 A7 A9 B5 B7 B9 C5 C7 C9 D5 D7 D9 E5 D4 E7 E9 F5 F7 F9
B3 C3 D3 E3 F3
P3V3
G2E6C2
D1
DBI
IDESP
VDD
A1
G2E6C2
D1
DBI
IDESP
VDD
A1
P1IDES_P P1IDES_N P1S2_FAULTB
B1
A3
BST
IDESN
FAULTB
GND
GND
E2
F1
P1DB5
P1IDES_P P1IDES_N P1S4_FAULTB
B1
A3
BST
IDESN
FAULTB
GND
GND
E2
F1
3
P1DB2
R3251
P1S2BSTP1S1BST
C312
VX VX VX
VX VX VX
VX VX VX
VX VX VX
VX VX VX
VX VX VX
C336
VX VX VX
VX VX VX
VX VX VX
VX VX VX
VX VX VX
VX VX VX
3
P1S2BST 81P1S1BST 81
P1SPHASE71
1u
A4 A6 A8
B4 B6 B8
P1VX2
C4 C6 C8
D6 D8
E4 E8 F4
F6 F8
1u
A4 A6 A8
B4 B6 B8
P1VX5
C4 C6 C8
D6 D8
E4 E8 F4
F6 F8
P1S6PHASE81
P3V3 P3V3
C333 1u
P1S3PHASE81
P3V3 P3V3
C357 1u
P1S6DBI81 P1S6DBO81
P1SPHASE
C334 1u
P12V_CPU1
1uC316 1uC319
1uC322 10u-1206C325 10u-1206C328
P1S3DBI81 P1S3DBO81
P1SPHASE
C358
1u
P12V_CPU1
1uC340
1uC343
1uC346 10u-1206C349 10u-1206C352
0
P1S6DBI P1S6DBO
R258 1K
P1S6PHASE
A5
VSS
A7
VSS
A9
VSS
B5
VSS
B7
VSS
B9
VSS
C5
VSS
C7
VSS
C9
VSS
D5
VSS
D7
VSS
D9
VSS
E5 D4
VSS
E7
VSS
E9
VSS
F5
VSS
F7
VSS
F9
VSS
B3
VDDH
C3
VDDH
D3
VDDH
E3
VDDH
F3
VDDH
P3V3
P1DB5
R3260
0
P1S3DBI P1S3DBO
R273 1K
P1S3PHASE
A5
VSS
A7
VSS
A9
VSS
B5
VSS
B7
VSS
B9
VSS
C5
VSS
C7
VSS
C9
VSS
D5
VSS
D7
VSS
D9
VSS
E5 D4
VSS
E7
VSS
E9
VSS
F5
VSS
F7
VSS
F9
VSS
B3
VDDH
C3
VDDH
D3
VDDH
E3
VDDH
F3
VDDH
P3V3
R3246
X_0
H2
SPHASE
R3255
X_0
H2
SPHASE
R3252
A2
R3261
A2
VCC
VCC
0
H1
B2
0
H1
B2
2
G2E6C2
DBI
DBO
VDD
VDD
A1
G2E6C2
DBI
DBO
VDD
VDD
A1
2
D1
D1
P1DBI
IDESP
IDESN
P1DB4
IDESP
IDESN
P1IDES_P P1IDES_N P1S6_FAULTB
P1S6BST
B1
A3
VX
BST
VX
FAULTB
VX VX
VX VX
VX VX VX
VX VX VX
VX VX VX
VX VX VX
GND
GND
E2
F1
P1IDES_PP1IDES_P P1IDES_N P1S3_FAULTB
B1
A3
VX
BST
VX
FAULTB
VX VX
VX VX
VX VX VX
VX VX VX
VX VX VX
VX VX VX
GND
GND
E2
F1
P1DBI 71
P1IDES_P 71,81 P1IDES_N 71,81 P1S6_FAULTB 81 P1S6BST 81
C313
1u
A4 A6 A8
B4 B6 B8
P1VX1
C4 C6 C8
D6 D8
E4 E8 F4
F6 F8
P1S3_FAULTB 81P1S4_FAULTB 81P1S5_FAULTB 81
C337
1u
A4 A6 A8
B4 B6 B8
P1VX4
C4 C6 C8
D6 D8
E4 E8 F4
F6 F8
L5 INDUCTOR_3_PHASE_6pin
L6 INDUCTOR_3_PHASE_6pin
P1VX4 81P1VX5 81P1VX6 81
P1S1_FAULTB P1S2_FAULTB P1S3_FAULTB P1S4_FAULTB P1S5_FAULTB P1S6_FAULTB
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
CPU1 VREG2 VT1115S
P1VX1
1
50nH
2
P1VX2
3
50nH
4
P1VX3
5
50nH
6
P1VX4
1
50nH
2
P1VX5
3
50nH
4
P1VX6
5
50nH
6
Slave Faults
MS-9192
1
VCORE1
VCORE1
VCORE1
VCORE1
VCORE1
VCORE1
R315 10K R316 10K R317 10K R318 10K R319 10K R320 10K
Last Revision Date:
Friday, April 27, 2007
Sheet
72 90
1
P3V3
Rev
0A
of
Page 73
5
VCORE Decoupling Cap.
4
3
2
1
VCORE0
D D
C1206 10u-1206
VCORE0
C1220 10u-1206
VCORE0
C C
C1235 10u-1206
VCORE0
C3283 10u-0805
VCORE0
B B
C3297 10u-0805
VCORE0 BULK Decoupling Caps. VCORE1 BULK Decoupling Caps.
C1207 10u-1206
C1221 10u-1206
C1236 10u-1206
C3284 10u-0805
C3298 10u-0805
C1208 10u-1206
C1222 10u-1206
C1237 10u-1206
C3285 10u-0805
C3301 10u-0805
C1209 10u-1206
C1224 10u-1206
C1238 10u-1206
C3286 10u-0805
C3302 10u-0805
C1210 10u-1206
C1225 10u-1206
C1239 10u-1206
C3287 10u-0805
C3304 10u-0805
C1211 10u-1206
C1226 10u-1206
C1418 10u-1206
C3288 10u-0805
C3305 10u-0805
C1212 10u-1206
C1227 10u-1206
C1419 10u-1206
C3289 10u-0805
C3309 10u-0805
C1213 10u-1206
C1228 10u-1206
C1420 10u-1206
C3290 10u-0805
C3306 10u-0805
C1214 10u-1206
C1229 10u-1206
C1421 10u-1206
C3291 10u-0805
C3308 10u-0805
C1215 10u-1206
C1230 10u-1206
C1422 10u-1206
C3292 10u-0805
C3307 10u-0805
C1216 10u-1206
C1231 10u-1206
C1423 10u-1206
C3293 10u-0805
C3315 10u-0805
C1217 10u-1206
C1232 10u-1206
C1424 10u-1206
C3294 10u-0805
C3317 10u-0805
C1218 10u-1206
C1233 10u-1206
C3281 10u-0805
C3295 10u-0805
C3318 10u-0805
C1219 10u-1206
C1234 10u-1206
C3282 10u-0805
C3296 10u-0805
C3322 10u-0805
VCORE1
VCORE1
VCORE1
VCORE1
VCORE1
C363 10u-1206
C377 10u-1206
C392 10u-1206
C3328 10u-0805
C3350 10u-0805
C364 10u-1206
C378 10u-1206
C393 10u-1206
C3330 10u-0805
C3354 10u-0805
C365 10u-1206
C379 10u-1206
C394 10u-1206
C3331 10u-0805
C3351 10u-0805
C366 10u-1206
C381 10u-1206
C395 10u-1206
C3332 10u-0805
C3353 10u-0805
C367 10u-1206
C382 10u-1206
C396 10u-1206
C3333 10u-0805
C3352 10u-0805
C368 10u-1206
C383 10u-1206
C1411 10u-1206
C3334 10u-0805
C3355 10u-0805
C369 10u-1206
C384 10u-1206
C1412 10u-1206
C3342 10u-0805
C3356 10u-0805
C370 10u-1206
C385 10u-1206
C1413 10u-1206
C3343 10u-0805
C3357 10u-0805
C371 10u-1206
C386 10u-1206
C1414 10u-1206
C3344 10u-0805
C43
0.1u
C372 10u-1206
C387 10u-1206
C1415 10u-1206
C3345 10u-0805
C44
0.1u
C373 10u-1206
C388 10u-1206
C1416 10u-1206
C3346 10u-0805
C45
0.1u
C374 10u-1206
C389 10u-1206
C1417 10u-1206
C3347 10u-0805
C46
0.1u
C375 10u-1206
C390 10u-1206
C3329 10u-0805
C3348 10u-0805
C47
0.1u
C376 10u-1206
C391 10u-1206
C3326 10u-0805
C3349 10u-0805
C48
0.1u
VCORE0
C3321
C3319
10u-0805
10u-0805
VCORE0
C33
C34
0.1u
A A
0.1u
C3320 10u-0805
C35
0.1u
5
C3323 10u-0805
C36
0.1u
C3324 10u-0805
C37
0.1u
C3325 10u-0805
C38
0.1u
C22
0.1u
C3247 103P
C23
0.1u
C3248 103P
C24
0.1u
C39
0.22u
4
C25
0.1u
C40
0.22u
C29
0.1u
C41
0.22u
C30
0.1u
C31
0.1u
C32
0.1u
VCORE1
3
C49
0.1u
C50
0.1u
C51
0.1u
C52
0.1u
C53
0.1u
C54
0.1u
C42
0.1u
C56
0.1u
C3249 103P
C3250 103P
C55
0.22u
C57
0.22u
C58
0.22u
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
2
http://www.msi.com.tw
VCORE Decoupling Cap.
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
1
73 90
Rev
0A
of
Page 74
5
4
3
2
1
FBD 1.8V VREG
SMBCLK_MAIN58,59,60,64,69 SMBDAT_MAIN 58,59,60,64,69
P_VTTOEN76
P1V5_PWRGD75
RN3
10u-1206C170 10u-1206C173
C177 1u
1uC161 1uC164 1uC167
1 2 3 4 5 6 7 8
C129 X_103P
P1V8S1PHASE
P12V
0-8P4R
R197 X_249RST
C128 X_680P
R203 1KST
C130 153P
P1V8S1DBI
R218 1K
D D
C C
P1V8S1DBI82
P1V8S1DBO82
P1V8SPHASE P1V8SPHASE
P1V8S1PHASE82
B B
P3V3 P3V3
C176 1u
A A
R1128 X_0 R1124 0 R3156 0
R200 499RST
R204
2.2KST
R209
R212
0
A5
VSS
A7
VSS
A9
VSS
B5
VSS
B7
VSS
B9
VSS
C5
VSS
C7
VSS
C9
VSS
D5
VSS
D7
VSS
D9
VSS
E5 D4
VSS
E7
VSS
E9
VSS
F5
VSS
F7
VSS
F9
VSS
B3
VDDH
C3
VDDH
D3
VDDH
E3
VDDH
F3
VDDH
P3V3
5
H2
X_0
SPHASE
R213
A2
VCC
0
H1
DBO
VDD
B2
P1V8DB3
G2E6C2
D1
DBI
IDESP
VDD
A1
IDESN
P3V3
SMBCLK_1105 SMBDAT_1105 P1V8_PWRGD P1V8OEN P1V8VID5 P1V8VID4 P1V8VID3 P1V8VID2 P1V8VID1 P1V8VID0
10u-0805C126 6800PC127
P1V8SENSE+ P1V8SENSE-
P1V8_FAULT
P1V8VIN_OV
P1V8IDES_P P1V8IDES_N
P1V8S1BST
C158
B1
A3
VX
BST
VX
FAULTB
VX VX
VX VX
VX VX VX
VX VX VX
VX VX VX
VX VX VX
GND
GND
E2
F1
1u
A4 A6 A8
B4 B6 B8
C4 C6 C8
D6 D8
E4 E8 F4
F6 F8
1
SC
2
Pwrgd
3
OEN
4
VID<5>
5
VID<4>
6
VID<3>
7
VID<2>
8
VID<1>
9
VID<0>
10
VDD
11
GND
12
Vnom+
13
Vnom-
14
sense+
15
sense-
16
Vamp_out1
17
Vamp_in
18
Vamp_out2
19
FaultB#
P12V
R205 100KST
R207
C133
10.7KST
103P
P1V8S_FAULT1 82 P1V8S1BST 82
P1V8S2DBI82
P1V8S2DBO82
P1V8S2PHASE82
P1V8VX3
P1V8VX3 82 P1V8VX2 82 P1V8VX1 82
P3V3 P3V3
C178 1u
P1V8VIN_UV
C179 1u
P12V
1uC162 1uC165
1uC168 10u-1206C171 10u-1206C174
4
R_sel<6> R_sel<5> R_sel<4>
R_ref R_sel<3> R_sel<2>
R_freq Vin_ov
Vin_uv
R_sel<1>
Ides_n Ides_p
R_sel<0>
sphase
VT1105M
P1V8S2PHASE
P3V3
U23
38
SD
37
GND
VDD
DBO
DBI
C134 103P
P1V8S2DBI
R219 1K
P1V8SEL6
36
P1V8SEL5
35
P1V8SEL4
34
P1V8REF
33
P1V8SEL3
32
P1V8SEL2
31
P1V8FREQ
30 29
P1V8VIN_OV
28
P1V8VIN_UV
27
P1V8SEL1
26
P1V8IDESNR
25
P1V8IDESPR P1V8IDES_P
24
P1V8SEL0
23 22 21 20
P12V
R206
63.4KST
R208 10KST
R3262
R3264
0
A5
VSS
A7
VSS
A9
VSS
B5
VSS
B7
VSS
B9
VSS
C5
VSS
C7
VSS
C9
VSS
D5
VSS
D7
VSS
D9
VSS
E5 D4
VSS
E7
VSS
E9
VSS
F5
VSS
F7
VSS
F9
VSS
B3
VDDH
C3
VDDH
D3
VDDH
E3
VDDH
F3
VDDH
P3V3
H2
X_0
R3265
SPHASE
C1072 1u
0
H1
G2E6C2
D1
DBI
DBO
VCC
VDD
VDD
A1
A2
B2
R1135 X_0
R189 0 R190 0
R199 0 R201 0 R202 0
P1V8
P1V8DB2 P1V8DBIP1V8DBO P1V8DB3
P1V8IDES_P P1V8IDES_N P1V8S_FAULT2P1V8S_FAULT1
P1V8S2BST
B1
A3
BST
IDESP
IDESN
FAULTB
GND
GND
E2
F1
R1301 0
R1302 0
C159
1u
A4
VX
A6
VX
A8
VX
B4
VX
B6
VX
B8
VX
C4
VX
C6
VX
C8
VX VX
D6
VX
D8
VX
E4
VX VX
E8
VX
F4
VX
F6
VX
F8
VX
P1V8IDES_N
P1V8DBI P1V8DBO P1V8SPHASE
P1V8SENSE+
P1V8SENSE-
P1V8S_FAULT2 82 P1V8S2BST 82
P1V8S3PHASE82
P1V8VX2
P3V3 P3V3
C180 1u
C1073 1u
P1V8S3DBI82
P1V8S3DBO82
P1V8SPHASE
C181 1u
1uC163 1uC166
1uC169 10u-1206C172 10u-1206C175
3
P1V8VID5 P1V8VID0 P1V8OEN
C67 0.1u
C66 0.1u
P12V
P3V3 P3V3 P3V3
R175
R174
10K
X_10K
R193
R192
X_0
0
P1V8DB2
P1V8S3DBI P1V8S3DBOP1V8S1DBO P1V8S2DBO
R220 1K
P1V8S3PHASE
R3263
X_0
R3266
A5 A7 A9 B5 B7 B9 C5 C7 C9 D5 D7 D9 E5 D4 E7 E9 F5 F7 F9
B3 C3 D3 E3 F3
P3V3
0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VDDH VDDH VDDH VDDH VDDH
H2
SPHASE
R3267
A2
0
H1
DBO
VCC
VDD
B2
R176 10K
R194 X_0
G2E6C2
D1
DBI
IDESP
VDD
A1
SMBDAT_110575 SMBCLK_110575
P1V8IDES_P P1V8IDES_N P1V8S_FAULT3
P1V8S3BST
C160
B1
A3
VX
BST
VX
IDESN
FAULTB
VX VX
VX VX
VX VX VX
VX VX VX
VX VX VX
VX VX VX
GND
GND
E2
F1
1u
A4 A6 A8
B4 B6 B8
C4 C6 C8
D6 D8
E4 E8 F4
F6 F8
P1V8IDES_P 82 P1V8IDES_N 82 P1V8S_FAULT3 82 P1V8S3BST 82
P1V8VX1
2
P1V8VX1
1
50nH
2
P1V8VX2
3
50nH
4
P1V8VX3
5
50nH
6
L4 INDUCTOR_3_PHASE_6pin
P3V3 P3V3
R600
R592
2.2K
2.2K
SMBDAT_1105 SMBCLK_1105
For Volterra Debug
1.8V BULK Decoupling Caps.
P1V8
P1V8
P1V8
P1V8
C155
C154
22u-1206
22u-1206
P12V
12
+
EC24 270u-16V
P1V8
P1V8
P1V8
P3V3
J12
1 2 3 4
N31-1040011-H06
C131
C132
22u-1206
22u-1206
C140
C141
22u-1206
22u-1206
C148
C147 22u-1206
22u-1206
C157
C156 22u-1206
22u-1206
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
Master Reported Faults
P1V8S_FAULT1 P1V8S_FAULT2 P1V8S_FAULT3 P1V8_FAULT P1V8_PWRGD
Configuration Resistors
P1V8SEL6 P1V8SEL5 P1V8SEL4 P1V8REF P1V8SEL3 P1V8SEL2 P1V8FREQ P1V8SEL1 P1V8SEL0
C135
C136
22u-1206
22u-1206
C143
C142
22u-1206
22u-1206
C149
C150
22u-1206
22u-1206
C182 22u-1206
FBD 1.8V VREG
MS-9192
Last Revision Date:
Sheet
R182 10K R181 10K R180 10K R179 10K R178 10K
R183 1.02KST R184 340RST R185 16.9KST R186 11KST R187 5.9KST R188 23.7KST R191 26.1KST R196 6.49KST R198 13KST
C137 22u-1206
C144 22u-1206
C151 22u-1206
C59
C183 22u-1206
0.1u
Friday, April 27, 2007
74 90
1
C138 22u-1206
C145 22u-1206
C152 22u-1206
C60
0.1u
of
P3V3
C139 22u-1206
C146 22u-1206
C153 22u-1206
C61
0.1u
Rev
0A
Page 75
5
4
3
2
1
FBD 1.5V VREG
SMBCLK_110574 SMBDAT_1105 74 P1V5_PWRGD74
D D
C C
P1V5S1PHASE83
B B
P3V3 P3V3
C237 1u
A A
PS_PWROK_BUF54,58,68
R217 X_249RST
C241 X_680P
R230 1KST
C229 X_103P
C221 153P
P1V5S1DBI83
P1V5S1DBO83
P1V5SPHASE P1V5SPHASE
C192 1u
1uC228 1uC207
1uC212 10u-1206C219 10u-1206C200
P1V5S1DBI
R239 1K
P1V5S1PHASE
P12V
P3V3
5
R252 0
R211 499RST
R225
2.8KST
R226
R216
0
A5
VSS
A7
VSS
A9
VSS
B5
VSS
B7
VSS
B9
VSS
C5
VSS
C7
VSS
C9
VSS
D5
VSS
D7
VSS
D9
VSS
E5 D4
VSS
E7
VSS
E9
VSS
F5
VSS
F7
VSS
F9
VSS
B3
VDDH
C3
VDDH
D3
VDDH
E3
VDDH
F3
VDDH
H2
X_0
SPHASE
R238
A2
VCC
0
H1
DBO
VDD
B2
P1V5DB3
G2E6C2
D1
DBI
IDESP
VDD
A1
IDESN
P3V3
SMBCLK_1105 SMBDAT_1105 P1V5PWRGD P1V5OEN P1V5VID5 P1V5VID4 P1V5VID3 P1V5VID2 P1V5VID1 P1V5VID0
10u-0805C222 6800PC213
P1V5SENSE+ P1V5SENSE-
P1V5_FAULT
P1V5VIN_OV
P1V5IDES_P P1V5IDES_N
P1V5S1BST
C220
B1
A3
VX
BST
VX
FAULTB
VX VX
VX VX
VX VX VX
VX VX VX
VX VX VX
VX VX VX
GND
GND
E2
F1
C218 103P
1u
A4 A6 A8
B4 B6 B8
C4 C6 C8
D6 D8
E4 E8 F4
F6 F8
1
SC
2
Pwrgd
3
OEN
4
VID<5>
5
VID<4>
6
VID<3>
7
VID<2>
8
VID<1>
9
VID<0>
10
VDD
11
GND
12
Vnom+
13
Vnom-
14
sense+
15
sense-
16
Vamp_out1
17
Vamp_in
18
Vamp_out2
19
FaultB#
P12V
R227 100KST
R233
10.7KST
P1V5S_FAULT1 83 P1V5S1BST 83
P1V5S2PHASE83
P1V5VX3
P3V3 P3V3
C235 1u
R_sel<6> R_sel<5> R_sel<4>
R_ref R_sel<3> R_sel<2>
R_freq Vin_ov
Vin_uv
R_sel<1>
Ides_n Ides_p
R_sel<0>
sphase
VT1105M
P1V5VIN_UV
C201 103P
P1V5S2DBI83
P1V5S2DBO83
P1V5S2PHASE
P1V5VX3 83 P1V5VX2 83
C187 1u
P12V
1uC226 1uC203
1uC209 10u-1206C215 10u-1206C196
4
P3V3
U40
38
SD
37
GND
VDD
DBO
DBI
P12V
P1V5S2DBI
R232 1K
P1V5SEL6
36
P1V5SEL5
35
P1V5SEL4
34
P1V5REF
33
P1V5SEL3
32
P1V5SEL2
31
P1V5FREQ
30 29
P1V5VIN_OV
28
P1V5VIN_UV
27
P1V5SEL1
26
P1V5IDESNR
25
P1V5IDESPR P1V5IDES_P
24
P1V5SEL0
23 22 21 20
P1V5
R251
63.4KST
R215 10KST
R3293
A5 A7 A9 B5 B7 B9 C5 C7 C9 D5 D7 D9 E5 D4 E7 E9 F5 F7 F9
B3 C3 D3 E3 F3
P3V3
0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VDDH VDDH VDDH VDDH VDDH
R3379
X_0
H2
SPHASE
C1075 1u
R3452
A2
0
H1
G2E6C2
D1
DBI
DBO
VCC
VDD
VDD
A1
B2
R248 0 R235 0
R245 0 R237 0 R224 0
R1303 0
R1304 0
P1V5DB2 P1V5DBIP1V5DBO P1V5DB3
B1
IDESP
IDESN
FAULTB
GND
E2
P1V5IDES_P P1V5IDES_N P1V5S_FAULT2P1V5S_FAULT1
P1V5S2BST
C217
1u
A3
A4
VX
BST
A6
VX
A8
VX
B4
VX
B6
VX
B8
VX
C4
VX
C6
VX
C8
VX VX
D6
VX
D8
VX
E4
VX VX
E8
VX
F4
VX
F6
VX
F8
VX
GND
F1
P1V5IDES_N
P1V5DBI P1V5DBO P1V5SPHASE
P1V5SENSE+
C1074 1u
P1V5SENSE-
P1V5S_FAULT2 83 P1V5S2BST 83
P1V5S3PHASE83
P1V5VX2
P3V3 P3V3
C189 1u
L7 INDUCTOR_3_PHASE_6pin
C69 0.1u
C68 0.1u
P1V5S3DBI83
P1V5S3DBO83
P1V5SPHASE
C197 1u
P12V
1uC234 1uC211
1uC216 10u-1206C225 10u-1206C206
3
P1V5VX1
1
50nH
2 3
50nH
4 5
50nH
6
R243 1K
P1V5S3PHASE
P1V5
P1V5VX2
P1V5
P1V5VX3
P1V5
P1V5DB2
P1V5S3DBI P1V5S3DBOP1V5S1DBO P1V5S2DBO
R3451
X_0
0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VDDH VDDH VDDH VDDH VDDH
H2
SPHASE
R3453
A2
0
H1
DBO
VCC
VDD
B2
R3377
A5 A7 A9 B5 B7 B9 C5 C7 C9 D5 D7 D9 E5 D4 E7 E9 F5 F7 F9
B3 C3 D3 E3 F3
P3V3
R255 X_10K R259 0 R260 0R253 0 R261 X_0 R262 X_0 R263 0 R264 X_0
Master Reported Faults
P1V5S_FAULT1 P1V5S_FAULT2 P1V5S_FAULT3 P1V5_FAULT P1V5PWRGD
P1V5IDES_P P1V5IDES_N P1V5S_FAULT3
P1V5S3BST
C227
1u
B1
A3
G2E6C2
D1
IDESN
A4
VX
BST
A6
VX
A8
FAULTB
VX
B4
VX
B6
VX
B8
VX
C4
VX
C6
VX
C8
VX VX
D6
VX
D8
VX
E4
VX VX
E8
VX
F4
VX
F6
VX
F8
VX
GND
GND
E2
F1
DBI
IDESP
VDD
A1
P1V5OEN P1V5VID5 P1V5VID4 P1V5VID3 P1V5VID2 P1V5VID1 P1V5VID0
R241 10K R228 10K R222 10K R249 10K R210 X_10K
P1V5IDES_P 83 P1V5IDES_N 83 P1V5S_FAULT3 83 P1V5S3BST 83
P1V5VX1
P1V5VX1 83
P12V
12
+
EC25 270u-16V
2
R177 10K R223 X_10K R236 X_10K R244 10K R246 10K R250 X_10K R254 10K
P3V3
P1V5
P1V5
P1V5
P1V5
P1V5
P3V3
Configuration Resistors
P1V5SEL6 P1V5SEL5 P1V5SEL4 P1V5REF P1V5SEL3 P1V5SEL2 P1V5FREQ P1V5SEL1 P1V5SEL0
R240 1.02KST R231 340RST R195 31.6KST R247 11KST R242 5.9KST R234 23.7KST R214 26.1KST R221 6.49KST R229 14KST
1.5V BULK Decoupling Caps.
C3033
C3030
22u-0805
22u-0805
C513
C610
22u-0805
22u-0805
C612
C587
22u-0805
22u-0805
C3068
C3067
22u-1206
22u-1206
C3202
C3244
22u-1206
22u-1206
Micro Star Restricted Secret
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
C3034 22u-0805
C514 22u-0805
C602 22u-0805
C3069 22u-1206
C3245 22u-1206
C3035 22u-0805
C594 22u-0805
C579 22u-0805
C3197 22u-1206
C3246 22u-1206
FBD 1.5V VREG
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
C3053 22u-0805
C581 22u-0805
C3063 22u-1206
C3198 22u-1206
C3252 22u-1206
1
C3056 22u-0805
C518 22u-0805
C3064 22u-1206
C3199 22u-1206
P1V5 P1V5
12
+
EC22 820u-4V
75 90
of
C585 22u-0805
C524 22u-0805
C3066 22u-1206
C3200 22u-1206
12
+
EC23 820u-4V
Rev
0A
Page 76
5
4
3
2
1
FSB VTT 1.2V / FBD VTT 0.9V
P1V8
D D
C C
B B
P_VTT
C3205 10u-1206
IF VTT_SEL=1, Vo=1.2V IF VTT_SEL=0, Vo=1.1V
P5V
R3475
R3477 1K_0402
P5V
DS
R3478
A A
VTT_SEL10,13 Title
VTT_SEL
1K_0402
R3479 X_1K_0402
Q3040 2N7002_B
G
47KST
DS
Q3038
G
FDN337N
R3125 33-0805
C3118 10u-1206
P_VTT_PWRGD63
P_VTTOEN74
R3476
43.2KST
DS
Q3039
G
FDN337N
C3206
0.1u
R3062 10K
C3119
0.1u
FSB VTT 1.2V VREG
P5V
A1
VDD
A2
VDD
A3
VDD
R3060 10
C3120
0.1u
R3064 10KST R3065 30KST
C1
VDD
C2
VDD
C3
VDD
E1
VDD
E2
VDD
E3
VDD
G1
VDD
G2
VDD
G3
VDD
H1
AVDD
J1
STAT
K1
EN
K7
IMAX
K6
IRIPL
J7
BIAS
A4
GND
A5
GND
A6
GND
A7
GND
C4
GND
C5
GND
C6
GND
C7
GND
E4
GND
E5
GND
E6
GND
E7
GND
G4
GND
G5
GND
G6
GND
G7
GND
U3003
VFB
VDES
PGIN
VREF
AGND AGND AGND
VT225
B1
VX
B2
VX
B3
VX
B4
VX
B5
VX
B6
VX
B7
VX
D1
VX
D2
VX
D3
VX
D4
VX
D5
VX
D6
VX
D7
VX
F1
VX
F2
VX
F3
VX
F4
VX
F5
VX
F6
VX
F7
VX
K4 K3
K5 K2
H5 H6 H7
CHOK3000
200nH
R3075
42.2KST
Support Harpertown
&
Wolfdale
CPU
5
4
3
P_VTT
R3071 100KST C3042
100P
R3123
1.1KST R3160
20RST
C3027 22u-1206
C3039 22u-1206
C3043 102P
R126
0_0402
FBD VTT 0.9V VREG
C661
R3122
1.1KST
C3028 22u-1206
C3040 22u-1206
C3044 103P
C3102
0.1u
F_VTT
X_102P_0402
C3029 22u-1206
C3103 22u-1206
C3105 220P
X_102P_0402
C660
R3124
220
R3072
10K
2
P12V
3
+
2
-
U3036A LM358MX_SOIC8
4 8
R129 0_0402
P12V
5
+
6
-
U3036B LM358MX_SOIC8
4 8
C3038 22u-1206
C3104 22u-1206
P_VTT_SENSE+
P_VTT_SENSE-
X_0_0402
1
7
X_0_0402
C3031 22u-1206
C3036 22u-1206
R782
C3196
0.1u
F_VTT
R130
C3032 22u-1206
R3378
R3380
0
0
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
P1V8
C3177
0.1u
Q9
1 2 3 4 5
STS8DNF3LL_SO8
8 7 6
C3203
0.1u
F_VTT
12
+
EC3004 820u-4V
Micro Star Restricted Secret
FSB VTT 1.2V / FBD VTT 0.9V
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
76 90
1
of
12
+
EC3005 820u-4V
Rev
0A
Page 77
5
4
3
2
1
Standby/MISC VREG
P3V3_AUX
D D
C C
P5VSB P3VSB
12
+
EC14 270u-16V
3VSB VREG
3
VIN
C77 1u
SYS_PWRGD_3_3V20,35,37,40,50,63
VOUT VOUT
GND
LM1085-3.3
1
U18
2 4
P5VSB
R1096
4.7K
DS
Q83 2N7002
G
SOT23SGD
C78 1u
12
+
EC13 1000u-6.3V
P-MOS
1
S
2
S
3
S
R1098
8.2K
4
G
P3V3
G
SWITCH61
P12V
R1097 2KST
DS
Q82 2N7002
G
SOT23SGD
U78
D D D D
FDS4463
U79 ICEU603AL
D S
P3V3_AUX
8 7 6 5
12
+
EC15 1000u-6.3V
P1V2_AUX
C3074
0.1u
P3V3_AUX
1.5V AUX VREG
B B
P3V3_AUX
C1366 103P
U80
ADJ
L1084D-TO252
2
3
VIN1VOUT
Vout = 1.25*(Rup+Rdown)/(Rup)
R1102 499RST
R1104 100RST
C1367 103P
C1368 1u
P1V5_AUX
12
+
EC16 1000u-6.3V
R879
200RST
P1V8_AUX
C1245 22u-1206
EC21 22u-1206
C410
0.1u
12
+
C3073 10u-0805
EC20 1000u-6.3V
12
+
EC17 820u-4V
C3072 10u-0805
12
+
EC18 820u-4V
1.8V AUX VREG
3
C3075 10u-0805
Vout = 1.25*(1+Rdown/Rup)
C603
+
10u-0805
U3008
VIN
OUT
VOUT
ADJ/GND
X_RC1117S_SOT223
P3V3_AUX
12
EC4 560u/4V
2 4
1
P3V3_AUX
C3078 103P
R447 51RST
R3088
4.7K
P3V3_AUX
R3087
4.7K
C79
0.1u
R659 10RST
1.2V AUX VREG
U3007
1
EN
2
VIN
3
VO ADJ4GND
GND GND GND
SC1565
8 7 6 5
Vout = 1.20*(Rup+Rdown)/(Rdoown)
R3108 220RST
P1V8_AUX
C3077
1
EN
2
VIN
3
VO ADJ4GND
C3076 X_0.1u
U3009
GND GND GND
SC1565
8 7 6 5
X_10u-0805
R3090 X_220RST
R3091 X_100RST
Vout = 1.20*(Rup+Rdown)/(Rdoown)
12
+
EC19 X_820u-4V
A A
5
4
3
R445 100RST
Title Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
2
http://www.msi.com.tw
Standby/MISC VREG
MS-9192
Last Revision Date:
Wednesday, May 02, 2007
Sheet
1
77 90
Rev
0A
of
Micro Star Restricted Secret
Page 78
5
4
Impedance Test and Mouting Hole
3
2
1
D D
C C
B B
Impedance Test Port: Differential-85ohm
TL5
1
L1_D85ohm_P
2
X_YJ102 TL6
1
L1_D85ohm_N
2
X_YJ102
Layer 1, Differential Pair, Width=6mil, Space=6mil
Impedance Test Port: Differential-100ohm
TL9
1
L1_D100ohm_P
2
X_YJ102 TL10
1
L1_D100ohm_N
2
X_YJ102
Layer 1, Differential Pair, Width=4mil, Space=6mil
Impedance Test Port: Signal-50ohm
TL1
1
L1_S50ohm_6 L6_S50ohm_4.5
2
Layer 1--6 mil
X_YJ102
TL2
1 2
X_YJ102
50 ohm(6mil)
L3_S50ohm_4.5
Layer 3--4.5 mil
50 ohm(4.5mil)
TL7
1
L3_D85ohm_P
2
X_YJ102 TL8
1
L3_D85ohm_N
2
X_YJ102
Layer 3, Differential Pair, Width=5mil, Space=6.5mil
TL11
1
L3_D100ohm_P
2
X_YJ102 TL12
1
L3_D100ohm_N
2
X_YJ102
Layer 3, Differential Pair, Width=4mil, Space=9mil
TL3
1 2
Layer 6--4.5 mil
X_YJ102
TL4
X_YJ102
50 ohm(4.5mil)
1
L8_S50ohm_6
2
Layer 8--6 mil
50 ohm(6mil)
Optics Orientation Holes
FM1
NOPOP
FM19
FM2 FM9
FM3
FM4
FM5
NOPOP NOPOP NOPOP NOPOP NOPOP NOPOP NOPOP NOPOP
FM20
FM25
FM22
FM23
FM6
FM21
FM7
FM17
FM8
FM24 FM26
NOPOP NOPOP NOPOP NOPOP NOPOP NOPOP NOPOP NOPOP NOPOP NOPOP
12
FM10 X_FM
12
12
FM11 X_FM
FM12 X_FM
12
12
FM13 X_FM
FM14 X_FM
12
12
FM15
FM16
X_FM
X_FM
NOPOP NOPOP NOPOP NOPOP NOPOP NOPOP NOPOP
FM18
NOPOP
FM27
Mouting Holes
MH2
H1 H2 H3 H4 H5 H6 H7 H8 H9
X_MH
MH7
H1 H2 H3 H4 H5 H6 H7 H8 H9
X_MH
MH1
1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8 9
H1 H2 H3 H4 H5 H6 H7 H8 H9
X_MH
MH8
H1 H2 H3 H4 H5 H6 H7 H8 H9
X_MH
MH10
1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8 9
H1 H2 H3 H4 H5 H6 H7 H8 H9
X_MH
MH4
H1 H2 H3 H4 H5 H6 H7 H8 H9
X_MH
MH6
1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8 9
H1 H2 H3 H4 H5 H6 H7 H8 H9
X_MH
MH12
H1 H2 H3 H4 H5 H6 H7 H8 H9
X_MH
MH5
1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8 9
H1 H2 H3 H4 H5 H6 H7 H8 H9
X_MH
MH11
H1 H2 H3 H4 H5 H6 H7 H8 H9
X_MH
1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8 9
H3000
1
1
X_Hole_157
H3001
1
1
X_Hole_157
MH13 E2B-95H4010-A89
A A
Title Document Number
5
4
3
2
Micro Star Restricted Secret
Impedance Test and Mouting Hole
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
78 90
1
Rev
0A
of
Page 79
5
Manual Parts
4
3
2
1
XX3
XX4
H3001_X1
Mylar
PCB1
MS-9192-0A
FWH1_X1
BIOS
SST-1024K*8-33MHz-PLCC32
BAT1_X1
D D
1 2
HS1 MCH Heatsink
1 2
HS4 VRD0 Heatsink
C C
1 2
HS7 P1V5 Heatsink
B B
1 2
HS2 ESB2 Heatsink
1 2
HS5 VRD1 Heatsink
1 2
HS6 P1V8 Heatsink
BAT-B-CR2032-P-3V-220mAh
CPU0-S
XX1
XX2
Retention-Socket771
+
BATTERY
-
XX3
XX4
U900
TQFL100_82563EB
U98_X1
S29AL032D90
CPU1-S
XX1
XX2
Retention-Socket771
H3000_X1
Mylar
ROM
Un-used Gate
P3V3_AUX
147
U3010F
13 12
74LVC14A_SOIC14
A A
Title Document Number
5
4
3
2
Micro Star Restricted Secret
Manual Parts
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
79 90
1
Rev
0A
of
Page 80
5
4
3
2
1
CPU0 VREG2 Option Parts
D D
P0IDES_P
P0S1DBI70
P0S1DBO70
P0S1PHASE70
C C
B B
P12V_CPU0
P0S5DBI70
P0S5DBO70
P0S5PHASE70
P12V_CPU0
P0S1DBI P0S1PHASE
H2
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH
H1
SPHASE
H2
H1
SPHASE
A5 A7 B5 B7 C5 C7 D5 D7 E5 E7 F5 F7 B3 C3 D3 E3 F3
P0S5DBI P0S5DBO P0S5PHASE P0S4BSTP0S4PHASE
A5 A7 B5 B7 C5 C7 D5 D7 E5 E7 F5 F7 B3 C3 D3 E3 F3
P0IDES_N P0S1_FAULTBP0S1DBO P0S1BST
G2
B1
A3
D1
C2
U102
A4
VX
BST
IDESN
FAULTB
GND GND VDD VDD VCC
VT1135S
P0IDES_P P0IDES_N P0S5_FAULTB P0S5BST
B1
A3
BST
IDESN
FAULTB
GND GND VDD VDD VCC
VT1135S
VX VX VX VX VX VX VX VX VX VX VX
U106
VX VX VX VX VX VX VX VX VX VX VX VX
A6 B4 B6 C4 C6
P0VX3
D4 D6 E4 E6 F4
P3V3 P3V3 F6 F1 E2 A1 B2 A2
P0S5_FAULTB 70 P0S5BST 70 P0S4BST 70 P0S3BST 70
A4 A6 B4 B6 C4 C6
P0VX6 P0VX5 P0VX4
D4 D6 E4 E6 F4 F6 F1 E2 A1 B2 A2
P0VX6 70 P0VX5 70 P0VX4 70
P3V3
DBI
DBO
IDESP
G2
D1
C2
DBI
DBO
IDESP
P0S2DBI70
P0S2DBO70P0S1_FAULTB 70
P0S2PHASE70
P12V_CPU0
P0S4DBI70
P0S4DBO70
P0S4PHASE70
P12V_CPU0
P0S2DBI P0S2DBO P0S2_FAULTB P0S2PHASE P0S6BSTP0S6PHASE
H2
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH
H1
SPHASE
H2
H1
SPHASE
A5 A7 B5 B7 C5 C7 D5 D7 E5 E7 F5 F7 B3 C3 D3 E3 F3
P0S4DBI P0S4DBO P0S4_FAULTB
A5 A7 B5 B7 C5 C7 D5 D7 E5 E7 F5 F7 B3 C3 D3 E3 F3
P0IDES_P P0IDES_N
P0S2BST
G2
B1
A3
D1
C2
U103
A4
VX
IDESN
FAULTB
VT1135S
B1
IDESN
FAULTB
VT1135S
BST
VX VX VX VX VX VX VX VX VX VX
VX GND GND VDD VDD VCC
P0IDES_P P0IDES_N
A3
U107
VX BST
VX
VX
VX
VX
VX
VX
VX
VX
VX
VX
VX GND GND VDD VDD VCC
A6 B4 B6 C4 C6
P0VX2 P0VX1
D4 D6 E4 E6 F4 F6 F1 E2 A1 B2 A2
A4 A6 B4 B6 C4 C6 D4 D6 E4 E6 F4
P3V3 F6 F1 E2 A1 B2 A2
DBI
DBO
IDESP
G2
D1
C2
DBI
DBO
IDESP
P0S6DBO70
P0S6PHASE70
P12V_CPU0
P0S3DBI70
P0S3DBO70
P0S3PHASE70
P12V_CPU0
P0S6DBI P0S6DBO P0S6_FAULTB
H2
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH
H1
SPHASE
H2
H1
DBO
SPHASE
A5 A7 B5 B7 C5 C7 D5 D7 E5 E7 F5 F7 B3 C3 D3 E3 F3
P0S3DBI P0S3DBO P0S3PHASE
A5 A7 B5 B7 C5 C7 D5 D7 E5 E7 F5 F7 B3 C3 D3 E3 F3
P0IDES_P P0IDES_N
G2
B1
A3
D1
C2
U105
VX
DBI
BST
DBI
IDESP
D1
IDESP
C2
IDESN
IDESN
FAULTB
VT1135S
B1
A3
FAULTB
VT1135S
VX VX VX VX VX VX VX VX VX VX
VX GND GND
VDD VDD VCC
P0IDES_P P0IDES_N P0S3_FAULTB P0S3BST
U108
VX
BST
VX VX VX VX VX VX VX VX VX VX
VX GND GND VDD VDD VCC
DBO
G2
A4 A6 B4 B6 C4 C6 D4 D6 E4 E6 F4 F6 F1 E2 A1 B2 A2
A4 A6 B4 B6 C4 C6 D4 D6 E4 E6 F4 F6 F1 E2 A1 B2 A2
P0IDES_P 69 P0IDES_N 69P0S6DBI70 P0S6_FAULTB 70P0S2_FAULTB 70 P0S6BST 70P0S2BST 70P0S1BST 70
P3V3
P0S3_FAULTB 70P0S4_FAULTB 70
P3V3
P0VX1 70P0VX2 70P0VX3 70
A A
Title Document Number
5
4
3
2
Micro Star Restricted Secret
CPU0 VREG2 VT1135S Option Parts
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
80 90
1
Rev
0A
of
Page 81
5
4
3
2
1
CPU1 VREG2 Option Parts
D D
P1S1DBI72 P1S1DBO72
P1S1PHASE72
C C
P1S5DBI72 P1S5DBO72
P1S5PHASE72
B B
P12V_CPU1 P12V_CPU1 P12V_CPU1
P1S1DBI P1S1DBO
A5 A7 B5 B7 C5 C7 D5 D7 E5 E7
F5
F7 B3 C3 D3 E3
F3
P1S5DBI P1S5DBO
A5 A7 B5 B7 C5 C7 D5 D7 E5 E7
F5
F7 B3 C3 D3 E3
F3
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH
H2
H1
SPHASE
H2
H1
SPHASE
P1IDES_P P1S1_FAULTB
P1S1BSTP1S1PHASE
G2
B1
A3
D1
C2
U112
VX
DBI
BST
G2
DBI
IDESP
D1
IDESP
IDESN
C2
IDESN
FAULTB
VT1135S
B1
A3
FAULTB
VT1135S
VX VX VX VX VX VX VX VX VX VX
VX GND GND VDD VDD VCC
P1IDES_P P1IDES_N P1S5_FAULTB P1S5BSTP1S5PHASE
U113
VX
BST
VX
VX
VX
VX
VX
VX
VX
VX
VX
VX
VX GND GND VDD VDD VCC
DBO
DBO
P1S1_FAULTB 72 P1S2_FAULTB 72
A4 A6 B4 B6 C4 C6
P1VX3 P1VX2
D4 D6 E4 E6 F4
P3V3 F6 F1 E2 A1 B2 A2
P1S5BST 72 P1S4BST 72 P1S3BST 72
A4 A6 B4 B6 C4 C6
P1VX6
D4 D6 E4 E6 F4 F6 F1 E2 A1 B2 A2
P1VX6 72 P1VX5 72 P1VX4 72
P3V3 P3V3
P1S2DBI72 P1S2DBO72
P1S2PHASE72
P12V_CPU1P12V_CPU1
P1S4DBI72 P1S4DBO72
P1S4PHASE72
P1S2DBIP1IDES_N P1S2DBO P1S2_FAULTB
H2
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH
H2
H1
SPHASE
H1
SPHASE
A5 A7 B5 B7 C5 C7 D5 D7 E5 E7 F5 F7 B3 C3 D3 E3 F3
P1S4DBI P1S4DBO P1S4_FAULTB
A5 A7 B5 B7 C5 C7 D5 D7 E5 E7 F5 F7 B3 C3 D3 E3 F3
P1IDES_P P1IDES_N
P1S2BSTP1S2PHASE
G2
B1
A3
D1
C2
U110
A4
VX
IDESN
FAULTB
VT1135S
BST
VX VX VX VX VX VX VX VX VX VX
VX GND GND
VDD VDD VCC
P1IDES_P P1IDES_N
A6 B4 B6 C4 C6 D4 D6 E4 E6 F4
P3V3 P3V3 F6 F1 E2 A1 B2 A2
DBI
DBO
IDESP
P1S4BSTP1S4PHASE
G2
B1
A3
D1
C2
U114
A4
VX
DBI
DBO
IDESP
IDESN
FAULTB
VT1135S
BST
GND GND
VDD VDD VCC
A6
VX
B4
VX
B6
VX
C4
VX
C6
VX VX VX VX VX VX VX
P1VX5
D4 D6 E4 E6 F4 F6 F1 E2 A1 B2 A2
P1S6DBI72 P1S6DBO72
P1S6PHASE72
P12V_CPU1
P1S3DBI72 P1S3DBO72
P1S3PHASE72
P1S6DBI
P1S6DBO P1S6_FAULTB
G2
H2
D1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH
H1
DBI
DBO
SPHASE
G2
H2
D1
H1
DBI
DBO
SPHASE
A5 A7 B5 B7 C5 C7 D5 D7 E5 E7
F5
F7 B3 C3 D3 E3
F3
P1S3DBI P1S3DBO P1S3_FAULTB
A5 A7 B5 B7 C5 C7 D5 D7 E5 E7
F5
F7 B3 C3 D3 E3
F3
IDESP
IDESP
C2
IDESN
C2
IDESN
B1
A3
BST
FAULTB
GND GND
VDD VDD VCC
VT1135S
B1
A3
BST
FAULTB
GND GND
VDD VDD VCC
VT1135S
P1IDES_P
P1IDES_N
U111
A4
VX
A6
VX
B4
VX
B6
VX
C4
VX
C6
VX
D4
VX
D6
VX
E4
VX
E6
VX
F4
VX
F6
VX
F1 E2 A1 B2 A2
P1IDES_P P1IDES_N
P1S3BSTP1S3PHASE
U109
A4
VX
A6
VX
B4
VX
B6
VX
C4
VX
C6
VX
D4
VX
D6
VX
E4
VX
E6
VX
F4
VX
F6
VX
F1 E2 A1 B2 A2
P1S6BSTP1S6PHASE
P1IDES_P 71 P1IDES_N 71 P1S6_FAULTB 72 P1S6BST 72P1S2BST 72P1S1BST 72
P1VX1
P1S3_FAULTB 72P1S4_FAULTB 72P1S5_FAULTB 72
P1VX4
P3V3
P1VX1 72P1VX2 72P1VX3 72
A A
Title Document Number
5
4
3
2
Micro Star Restricted Secret
CPU1 VREG2 VT1135S Option Parts
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
81 90
1
Rev
0A
of
Page 82
5
4
3
2
1
FBD 1.8V VREG Option Parts
D D
P1V8S1DBI74
P1V8S1DBO74
P1V8S1PHASE74
C C
P12V P12V P12V
B B
P1V8S1DBI P1V8S1DBO
A5 A7 B5 B7 C5 C7 D5 D7 E5 E7 F5 F7 B3 C3 D3 E3 F3
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH
H2
H1
SPHASE
P1V8IDES_P P1V8S_FAULT1 P1V8S2DBO P1V8S_FAULT2
P1V8S1BSTP1V8S1PHASE
G2
B1
A3
D1
C2
U117
VX
DBI
BST
IDESP
IDESN
FAULTB
VX VX VX VX VX VX VX VX VX VX
VX GND GND
VDD VDD VCC
VT1135S
DBO
P1V8S_FAULT1 74 P1V8S1BST 74
A4 A6 B4 B6 C4 C6 D4 D6 E4 E6 F4
P3V3 P3V3 P3V3 F6 F1 E2 A1 B2 A2
P1V8S2DBI74
P1V8S2DBO74
P1V8S2PHASE74
P1V8S2DBI
A5 A7 B5 B7 C5 C7 D5 D7 E5 E7 F5 F7 B3 C3 D3 E3 F3
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH
H2
H1
SPHASE
P1V8IDES_P
P1V8S3DBO74
P1V8S3PHASE74
A4 A6 B4 B6 C4 C6 D4 D6 E4 E6 F4 F6 F1 E2 A1 B2 A2
P1V8S_FAULT2 74 P1V8S2BST 74
P1V8VX2 P1V8VX1P1V8VX3
P1V8S2BSTP1V8S2PHASE
G2
B1
A3
D1
C2
U115
VX
DBI
BST
IDESP
IDESN
VX VX
FAULTB
VX VX VX VX VX VX VX VX
VX GND GND
VDD VDD VCC
VT1135S
DBO
P1V8S3DBIP1V8IDES_N P1V8IDES_N P1V8S3DBO P1V8S_FAULT3
H2
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH
H1
SPHASE
A5 A7 B5
B7 C5 C7 D5 D7
E5
E7
F5
F7
B3 C3 D3
E3
F3
P1V8IDES_P P1V8IDES_N
P1V8S3BSTP1V8S3PHASE
G2
B1
A3
D1
C2
U116
VX
DBI
BST
IDESP
IDESN
FAULTB
VT1135S
GND GND VDD VDD VCC
VX VX VX VX VX VX VX VX VX VX VX
DBO
A4 A6 B4 B6 C4 C6 D4 D6 E4 E6 F4 F6 F1 E2 A1 B2 A2
P1V8IDES_P 74 P1V8IDES_N 74P1V8S3DBI74 P1V8S_FAULT3 74 P1V8S3BST 74
P1V8VX1 74P1V8VX2 74P1V8VX3 74
A A
Title Document Number
5
4
3
2
Micro Star Restricted Secret
FBD 1.8V VREG VT1135S Option Parts
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
82 90
1
Rev
0A
of
Page 83
5
4
3
2
1
FBD 1.5V VREG Option
D D
P1V5IDES_P
P1V5S1DBI75
P1V5S1DBO75
P1V5S1PHASE75
C C
P12V P12V
B B
P1V5S1DBO
A5 A7 B5 B7 C5 C7 D5 D7 E5 E7 F5 F7 B3 C3 D3 E3 F3
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH
H2
H1
SPHASE
P1V5IDES_NP1V5S1DBI P1V5S_FAULT1 P1V5S2DBO P1V5S_FAULT2 P1V5S1BSTP1V5S1PHASE
G2
B1
A3
D1
C2
U128
VX
DBI
BST
IDESP
IDESN
FAULTB
VT1135S
GND GND VDD VDD VCC
VX VX VX VX VX VX VX VX VX VX VX
DBO
P1V5S_FAULT1 75 P1V5S1BST 75
A4 A6 B4 B6 C4 C6
P1V5VX3 P1V5VX2
D4 D6 E4 E6 F4
P3V3 P3V3 P3V3 F6 F1 E2 A1 B2 A2
P1V5S2DBI75
P1V5S2DBO75
P1V5S2PHASE75
P1V5S2DBI P1V5IDES_N
H2
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH
H1
SPHASE
A5 A7 B5 B7 C5 C7 D5 D7 E5 E7 F5 F7 B3 C3 D3 E3 F3
P1V5IDES_P
P1V5S3DBO75
P1V5S3PHASE75
P12V
A4 A6 B4 B6 C4 C6 D4 D6 E4 E6 F4 F6 F1 E2 A1 B2 A2
P1V5S_FAULT2 75 P1V5S2BST 75
P1V5S2BSTP1V5S2PHASE
G2
B1
A3
D1
C2
U118
VX
DBI
BST
IDESP
IDESN
FAULTB
VT1135S
GND GND VDD VDD VCC
VX VX VX VX VX VX VX VX VX VX VX
DBO
P1V5S3DBI P1V5S3DBO P1V5S_FAULT3
H2
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDH VDDH VDDH VDDH VDDH
H1
SPHASE
A5 A7 B5 B7 C5 C7 D5 D7 E5 E7 F5 F7 B3 C3 D3 E3 F3
P1V5IDES_P P1V5IDES_N
P1V5S3BSTP1V5S3PHASE
G2
B1
A3
D1
C2
U127
VX
DBI
BST
IDESP
IDESN
FAULTB
VT1135S
GND GND
VDD VDD VCC
VX VX VX VX VX VX VX VX VX VX VX
DBO
A4 A6 B4 B6 C4 C6 D4 D6 E4 E6 F4 F6 F1 E2 A1 B2 A2
P1V5IDES_P 75 P1V5IDES_N 75P1V5S3DBI75 P1V5S_FAULT3 75 P1V5S3BST 75
P1V5VX1
P1V5VX1 75P1V5VX2 75P1V5VX3 75
A A
Title Document Number
5
4
3
2
Micro Star Restricted Secret
FBD 1.5V VREG Option
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
83 90
1
Rev
0A
of
Page 84
1
GPIO Maping
PIN NAME USAGEDURING RESET# S3 / S5 NOTE
GPI_0 GPI_1 GPI_2 GPI_3 GPI_4 GPI_5 GPI_6 GPI_7 GPI_8 GPI_9 GPI_10 GPI_11 GPI_12 GPI_13 GPI_14 GPI_15 GPO_16 GPO_17 GPO_18 GPO_19 GPO_20 GPO_21 GPIO_22
A A
GPO_23 GPIO_24
ESB2
GPIO_25 GPI_26 GPIO_27 GPIO_28 GPI_29 GPI_30 GPI_31 GPIO_32 GPIO_33 GPIO_34 GPIO_35 GPIO_36 GPIO_37 GPIO_38 GPIO_39 GPI_40 GPI_41 GPIO_42 GPIO_43 GPIO_44 GPIO_45 GPIO_46 GPIO_47 GPO_48 GPO_49
POWER WELL
V5REF V5REF V5REF V5REF V5REF V5REF VCC3.3 VCC3.3 VCCSus3.3 VCCSus3.3 VCCSus3.3 VCCSus3.3 VCC3.3 VCC3.3 VCCSus3.3 VCCSus3.3 VCC3.3 VCC3.3 VCC3.3 VCC3.3 VCC3.3 VCC3.3 N/A VCC3.3 VCCSus3.3 VCCSus3.3 VCC3.3 VCCSus3.3 VCCSus3.3 VCC3.3 VCC3.3 VCC3.3 VCC3.3 VCC3.3 VCC3.3 N/A N/A N/A N/A N/A V5REF VCC3.3 N/A N/A N/A N/A N/A N/A VCC3.3 V_CPU_IO
MUXED WITH REQ#6 REQ#5 PIRQ#E PIRQ#F PIRQ#G PIRQ#H N/A N/A N/A OC#4 OC#5 SMBALERT# SATAGP4 SATAGP5 OC#6 OC#7 GNT#6 GNT#5 N/A N/A SCLK SLOAD N/A SDATAOUT0 N/A N/A SATAGP0 N/A N/A SATAGP1 SATAGP2 SATAGP3 SDATAOUT1 N/A N/A N/A N/A N/A N/A N/A REQ#4 LDRQ#1 N/A N/A N/A N/A N/A N/A GNT#4 CPUPWRGD
PCI Master PCI Master High-Z High-Z High-Z High-Z DependOn Input DependOn Input DependOn Input External Pull-up External Pull-up External Pull-up DependOn Input DependOn Input External Pull-up External Pull-up High-Z High-Z High High Undriven Undriven N/A Undriven High High DependOn Input High High DependOn Input DependOn Input DependOn Input Undriven High High N/A N/A N/A N/A N/A PCI Master LPC Device N/A N/A N/A N/A N/A N/A High High-Z
Low Low Low Low Low Low Off Off Off Driven Driven Driven Driven Driven Driven Driven Off Off Off Off Off Off N/A Off Defined Defined Driven Defined Defined Driven Driven Driven Off Off Off N/A N/A N/A N/A N/A Low Low N/A N/A N/A N/A N/A N/A Off Off
MCH_ERR_N0 MCH_ERR_N1 MCH_ERR_N2 Un-used
2.5HD_SEL 1U_2U_SEL BIOS_RECOVERY BIOS_PASSWORD BMC_SCI_N BMC_SMI_OUT_N BMC_PWREQ_N BMC_SCI_OUT_N Un-used Un-used Un-used USB_DISCON Un-used Un-used Un-used RST_REQ SCLK SLOAD N/A SDATAOUT0 ESB_SATA_GPI Un-used Un-used LAN_DIS#_GPIO PLED Un-used Un-used Un-used SDATAOUT1 FBD_RESET FWH_WP_N N/A N/A N/A N/A N/A IDE_PRI_CBLSNS Un-used N/A N/A N/A N/A N/A N/A FRB3 CPU_PWRGD
PIN NAME
GPI_0 GPI_1 GPI_2
FWH
GPI_3 GPI_4
PIN NAME
GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 GIPO_16
PILOT 2
GIPO_17 GIPO_18 GIPO_19 GIPO_20 GIPO_21 GIPO_22 GIPO_23 GIPO_24 GIPO_25 GIPO_26 GIPO_27 GIPO_28 GIPO_29 GIPO_30 GIPO_31
POWER WELL
VCC3.3 VCC3.3 VCC3.3 VCC3.3 VCC3.3
POWER WELL
Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume
MUXED WITH N/A N/A N/A N/A N/A
MUXED WITH N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A BB_TXD0 BB_TXD1 BB_TXD2 BB_TXD3 BB_TXEN BB_TXER BB_TXCLK BB_CRS BB_COL BB_RXD0 BB_RXD1 BB_RXD2 BB_RXD3 BB_RXDV BB_RXER BB_RXCLK
PCI-X IRQ Routing Table
SAS1068 PCI_X Slot1 PCI_X Slot2
INT#A INT#B INT#C INT#D IDSEL
IRQ#/GNT#
1
IRQ#4
AD19 1
IRQ#0 IRQ#1 ZCR_INT# IRQ#3 AD21 (ZCR)
23
IRQ#1 IRQ#2 IRQ#3 IRQ#0
Undriven Undriven Undriven Undriven Undriven
USAGEDURING RESET# S3 / S5 NOTE
PCI1_GPI0Off Off Off Off Off
PCI1_GPI1
SAS Identified
Un-used
Un-used
USAGEDURING RESET# S3 / S5 NOTE Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined Defined
BMC_SEL_N
FSB0_TTL_IERR#
FSB1_TTL_IERR#
FAN_SELECT
Un-used
NMI_BTN_N
ID_BTN_N
BMC_SMI_IN_N
ESB_SYS_RST#
THERM_PRE_SET#
SYS_RESET_N
BMC_NMI
FRB3_PILOT_N
SPI_WE#
FORCE_MODE_N
SPI_HOLD#
BMC_SCI_N
RST_REQ_N
SYS_ID_LED_N
THERMTRIP0_N
THERMTRIP1_N
SYSRDY_LED
SYS_FLT_LED
COOL_FLT_LED
Un-used
Un-used
Un-used
Un-used
CPU0_SKTOCC#
CPU1_SKTOCC#
CPU0_DISABLE_N
CPU1_DISABLE_N
Title Document Number
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
Micro Star Restricted Secret
GPIO Maping
MS-9192
Last Revision Date:
Sheet
Friday, April 27, 2007
84
of
Rev
0A
90
Page 85
Reset and Power Good PLD Logic
PS_PWRGD5PS_PWRGD_N
CPU_SKTOCC044CPU_SKTOCC_N0
CPU_SKTOCC139CPU_SKTOCC_N1
15PLD_33MHZ_CLK PLD_33MHZ_CLK
45FSB0_MS_ID0
CPU_MSID_OK_N0
FSB1_MS_ID0
FSB0_MS_ID1 FSB1_MS_ID1
CPU0_BSEL0 CPU1_BSEL0
CPU0_BSEL1 CPU1_BSEL1
CPU0_BSEL2 CPU1_BSEL2
42
48
CPU_MSID_OK_N1
43
22 17
24 19
25 20
CPU0_BSEL_tmp1
CPU_SKTOCC0 PS_PWRGD
CPU_SKTOCC0 CPU_SKTOCC1
CPU_MSIDS_OK
CPU_BSEL_OK_N0
CPU_BSEL_OK_N1
CPU_BSEL_OK_N2
PMUX
CPU_SKTOCC0 CPU_SKTOCC1
PLD_VTT_PWRGD_3_3V_LOC PS_PWRGD
VR_ENABLE_MSID
PMUX
CPU_BSELS_OK
VR_ENABLE_BSEL
1
CPU_SKTOCC0
VR_ENABLE
2ms
CPU_SKTOCC1
PS_PWRGD
VR_ENABLE_DELAYED
PS_PWRGD
VR_SYS_ENABLE0
VR_SYS_ENABLE1
3538VR_SYS_ENABLE0
VR_SYS_ENABLE1
CPU_VRD_PWRGD0
A A
CPU_VRD_PWRGD1
VTT_PWRGD_3_3V 49
ESB_PLTRST_N 64
33
CPU_SKTOCC1
36
PS_PWRGD
PLD_33MHZ_CLK
PS_PWRGD
CPU_VRD_PWRGD_TMP
PS_PWRGD
PS_PWRGD
SincPLTCLK SincToCLK
120ms
PS_PWRGD
PLD_33MHZ_CLK
PS_PWRGD
PLD_VTT_PWRGD_3_3V_TMP
SincSYSCLK SincToCLK
CPU_VRD_PWRGD_OK_LOC
7
GOSHEN_DELAYED
300ms
CPU_VRD_PWRGD_TMP
VTT_PWRGD_3_3V_DELAYED PLD_VTT_PWRGD_3_3V
2ms
PLTRST_TMP
PS_PWRGD
SYSPWR_TMP
1
SYS_PWRGD_BUFFCPU_VRD_PWRGD_TMP
Tristate Buffer (open drain)
SYS_PWRGD_N
SYS_PWRGD_BUFF1_N
SYS_PWRGD_BUFF2
IDE_RSTDRV_N
61
50
9
2
62
11
57
6
60
CPU_VRD_PWRGD_OK
SYS_PWRGD_BUFFPS_PWRGD
PLTRST_N
PLTRST_BUFF1_N
PLTRST_BUFF2_N
IDE_RSTDRV_N
SYS_PWRGD_N
SYS_PWRGD_BUFF1_N
SYS_PWRGD_BUFF2
Title Document Number
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
Micro Star Restricted Secret
Reset and Power Good PLD Logic
MS-9192
Last Revision Date:
Sheet
Friday, April 27, 2007
of
85 90
Rev
0A
Page 86
1
Power On/Off Sequence
Power on Sequence
G3 G3 To S5 S3 To S0S4 S0 StateSystem State
Power SW#
CPU_SKTOCC#
ESB_SLP_S4#
ESB_SLP_S3#
PS_ON#
+12V1~+12V4
PWRGD_12V
VCC3.3
PWRGD_3.3V
VCC5
PWRGD_PS
P1V5_ESB2
PWRGD1_P1V5
A A
P1V5
PWRGD2_P1V5
P1V8
PWRGD_P1V8
P_VTT
VTT_PWRGD_3.3V
VTT_PWRGD
VRD_EN
VCORE
VRD_PWRGD
CPU_VRD_PWRGD
SYS_PWRGD_3V3
CPU_PWRGD
SYS_PWRGD_BUFF
SYS_PWRGD_BUF1
SYS_PWRGD_BUF2
When PWRBTN# is pressed.
Processor is present. ESB_SLP_S5# inactive to ESB_SLP_S4#
ESB_SLP_S4# inactive to ESB_SLP_S3#
A logical AND gate CPU_SKTOCC# and ESB_SLP_S3# from CPU and ESB2.
0.1msec-20msec after PS_ON# is asserted
Delay 100msec-500msec after 12V power is OK.
Power enable from PWRGD_12V
When VCC3.3 power is OK
Power enable from PWRGD_3.3V
P1v5_ESB2 power enable when VCC5 power is OK.
Power enable from PWRGD_PS
P1V5 power enable when ESB_P1V5 power is OK
Power enable from PWRGD1_P1V5
P1V8 power enable when P1V5 power is OK
Power enable from PWRGD2_P1V5
PVTT power enable when P1V8 power is OK
Power enable from PWRGD_P1V8 Voltage level compared P_VTT is 1.2V or 1.1V when
P_VTT power is OK CPLD delay 2msec after PWRGD_PS and
VTT_PWRGD_3.3V asserted CPLD delay 2msec after PWRGD_PS and
PLD_VTT_PWRGD asserted
Power enable from VRD_EN VCORE power OK. Need 1-500msec
VCORE to VRD_PWRGD assertion time. A logical OR gate VRD0_PWRGD and VRD1_PWRGD
from CPLD CPLD delay 120msec after CPU_VRD_PWRGD asserted
ESB2 core and PCICLK been stable for at least 99msec A logical AND gate of SYS_PWRGD_3V3 and
VRD_PWRGD from ESB2
CPLD delay 120msec after CPU_VRD_PWRGD asserted
A buffered copy of SYS_PWRGD_3V3 from CPLD
A buffered copy of SYS_PWRGD_3V3 from CPLD
Power off Sequence
Power SW#
FSB_STPCLK#
SUS_STAT#
PCI_PLTRST#
PCI_RESET#
ESB_SLP_S3#
ESB_SLP_S4#
ESB_SLP_S5#
PS_ON#
PWRGD_12V
PWRGD_PS
PWRGD1_P1V5
PWRGD2_P1V5
PWRGD_P1V8
VTT_PWRGD_3.3V
VTT_PWRGD
VRD_PWRGD
CPU_VRD_PWRGD
SYS_PWRGD_3V3
CPU_PWRGD
1
S0 S0 To S3 S3 S4 S0 StateSystem State
When PWRBTN# is pressed for more than 4 sec this will cause an unconditional transation (power button override) to the S5 state
Asserted by ESB2 in response to hardware or software events. When processor samples STPCLK# asserted, it responds by syopping its internal clock.
Needs 2 RTCCLK for DMI message to SUS_STAT# active Needs 7-17 RTCCLK for SUS_STAT# to PCI_PLTRST#
and PCI_RESET# active Needs 1-2 RTCCLK for PCI_PLTRST# and PCI_RESET#
to ESB_SLP_S3# active
Needs 1-2 RTCCLK for ESB_SLP_S3# to ESB_SLP_S4#
Needs 1-2 RTCCLK for ESB_SLP_S4# to ESB_SLP_S5# When ESB_SLP_S4# is active
When +12V1, +12V2, +12V3, +12V4 power down
When VCC3.3 and VCC5 power down
When P1V5_ESB2 power down
When P1V5 power down
When P1V8 power down Voltage level compared P_VTT is 1.2V or 1.1V when
P_VTT power down
When VTT_PWRGD_3.3V inactive
When VRD_EN inactive
When VCORE power down
When CPU_VRD_PWRGD inactive A logical AND gate of SYS_PWRGD_3V3 and VRD_PWRD
from ESB2
Title Document Number
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw
Micro Star Restricted Secret
Power On/Off Sequence
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
86
Rev
0A
90
of
Page 87
1
System Reset Sequence
Reset Sequence
G3 G3 To S5 S4 S0 StateSystem State
ESB_SLP_S5#
ESB_SLP_S4#
ESB_SLP_S3#
CPU_VRD_PWRGD
SYS_PWRGD_3V3
PCI_PLTRST#
PLTRST#
PCI_RESET#
PCIX_RESET#
IDE_RESDREV#
A A
ACZ_RST#
PLT_BUFF1#
PLTRST_STRAP#
FSB_RESET#
FBD_RESET_GPO
FBD_BR_RST#
ESB_SYS_RST#
S3 To S0S3
A maximum 110msec of after RSM_RST# inactive to SUSCLK running, ESB_SLP_S5# inactive
ESB_SLP_S5# inactive to ESB_SLP_S4# Needs 1-2 RTCCLK (32us-64us) of after
ESB_SLP_S4# inactive to ESB_SLP_S3#
A logical OR gate of VRD_PWRGD from CPLD CPLD delay 120msec after CPU_VRD_PWRGD
asserted (ESB2 core power and PCICLK have been stable for at least 99ms)
The ESB2 Asserts PCI_PLTRST# during power up and when software initates a hard reset sequence through the reset control register ( I/O register CF9H). PCI_PLTRST# inactive a minimum of 1 ms after both SYS_PWRGD and CPU_VRD_PWRGD are active.
RESET# from CPLD (minimum of 1msec after both SYS_PWRGD_3V3 and VRD_PWRGD driven high)
A logic OR gate of the primary PCI_PLTRST# and the state of secondary bus reset bit of bridge control register (D30:F0:3EH, bit 6)
When PLTRST# and bridge contrl register asserted
A buffered copy of PCI_RESET#
When PLTRST# and bridge contrl register asserted
A buffered copy of PLT_TRST#from CPLD
A buffered copy of PLT_BUFF# After P_VTT and BCLK[1:0] stable, reset pulse
width 1msec - 10 msec during processor PWRGD_3V3 asserted
Signal from ESB2 GPO A logical NAND gate of SYS_PWRGD_3V3 and
FBD_RESET_GPO This pin forces an internal reset after being
debounced, when system reset button is pressed
Title Document Number
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
1
http://www.msi.com.tw
Micro Star Restricted Secret
System Reset Sequence
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
87
Rev
0A
90
of
Page 88
1
Revision History I
Revision History (Changes from Rev 0B)
Desciption
Changed the index.1 4 Changed the FBD VTT power block from the +5V source to +12V3 source. 6
Added PECI SMBus block diagram.
Changed Vcore0 sense serial damping R1273, R1274, R1275, and R1276 from 10ohms to 0ohm.
9
Stuffed FSB0_BSEL[2..0] pull-up resistors R3384, R3385, and R3386 510ohms.
Added PECI support.
11
Changed Vcore1 sense serial damping R1269, R1270, R1271, and R1272 from 10ohms to 0ohm.
12
Stuffed FSB1_BSEL[2..0] pull-up resistors R3388, R3389, and R3390 510ohms.
Added PECI support.
14 20
Reserved MCH_ERR_N[2..0] pull-up resistors R660, R661, and R662 1Kohms to P3V3.
Stuffed R3384 0ohm for XDP.
Stuffed R627 1Kohms for B-stepping Blackford MCH.
38
Added MCH_ERR_N0 RC delay circuit for Blackford MCH SMI# errata.
Separated MCH_ERR_N[2..0] and 1U-2U_SEL pull-up Rpack to resistors.
Separated IDE_PRI_CBLSNS pull-up resistor to R3209 2.7Kohms and no stuffed.
Moved IDE_PRI_CBLSNS pull-down resistor R337 to page74.
Changed pull-up resistor R3419 from ESB_SYS_RST# to ESB_SYS_RST#R.
40 44
Removed C603.
Reserved FGPI4 pull-up resistor R3374 1Kohms.
45
Stuffed SATA SGPIO serial resistors R3365, R3367, R3369, R3366, R3368, and R3370 0ohm for
46
front panel LED.
Added EC3002 1000uF/6.3V for rear USB connector 5V.
Changed AC coupling capacitors C1086, C1087, C1088, and C1089 from 0.01uF to 0.1uF.
47
A A
Changed LAN EEPROM EECS pull-up resistor R3290 from 10Kohms to 100Kohms, and no-stuffed
EEDO pull-up R3291.
Stuffed the power sequencing diode D3016, D3017, and D3018.
49
Swapped MOE0# and MOE1# signals name.
53
Changed R1392, R1393, and R3428, and R3429 from 2.7Kohms to 1Kohms.
Stuffed strapping pin MAD29 pull-up resistor R1401 4.7Kohms for SAS SGPIO enabled.
Resreved SAS EEPROM 24C64 U92 and its glued components.
Changed FB35 and FB36 from 330ohms/100MHz to 1Kohms/100MHz.
54
Modified OSC1 relatived circuit, shorted FB3000, R3002 and R3003, and changed R1466 from
55
10Kohms to 4.7Kohms.
Swapped MOE0# and MOE1# signals name.
56
Modified dual flashrom FLASHCS# circuit, used jumper JSASRAID1 setting RAID or no-RAID
supported.
No-stuffed R824 and R3432 for TST_RST#.
Changed the capacitor C1456 value for XTALI to 12pF. Changed capacitor C1457 value for XTALO
60
to 8pF. Also added series 0ohm resistor R1618 to XTALO pin.
Changed USB_DISCON pull-up resistor R3322 from 1Kohms to 300ohms and serial resitor R3435
from 100ohms to 4.7Kohms.
Removed VR0_HOT_BMC and VR1_HOT_BMC, and added GPIO27 for PILOT flashrom chip selected.
SheetSheet
Added 2 pin header J3001 for UART3 pins U3SIN and U3SOUT. This is used for debug.
61
Added 2 MOSFET Q89 and Q90 to KBDRST# and A20GATE for PILOT current leakage issue. Changed R1526, R1525, R1534, R3316, R3319, and R1535 from 5Kohms to 5.1Kohms 1%. Removed 2.5V_AUX voltage sense circuit and added pull down resistor R1521 4.7Kohms. Added P_VTT, P1V8, and P1V8_AUX voltage sense pin decoupling cap. C3277, C3276, and C3223 47pF. Stuffed PILOT strapping pin SF_AD9 pull-up R1698 1Kohms for UART3 disabled.63 Connected the PILOT JTAG TRST pin of Pilot to VSB_PWRGD signal. Modified the chip selected glued circuit.
64
Added Broadcom BCM5241 supported.
Modified the LAN3 connector pin out connection. 65 Added CPU_VRD_PWRGD pull-down resistor R465 1Kohms. 66
Modified the U36 OE_15# and OE_16# connected to R343. 69 Changed R1371 and R1374 from 100ohms to 4.7Kohms.
Changed R3443 from 1Kohms to 0ohm and Q30 from 3904 translator to 7002 NMOS.
Changed CPU_BSEL[2..0] pull-up resistors R1363, R1364, R1365 from 10Kohms to 1Kohms.
Changed R1366, R1367, and R1368 from 100ohms to 470ohms. 72 Added ADT7462 P1V5 voltage monitor at U3015 pin24. 73
Added PECI circuit supported. 74 Removed R3445.
Changed J3002 footprint for foolproof.
Changed R3111 value from 1Kohms to 300ohms for STATE LED.
Added R3159 0ohm to change polarity of SYS_ID_LED. 76 Removed R976 and R979.
Changed RSEL1 strap resistor R982 from 3.74Kohms to 340ohms 1% for offset function.
Changed R47 from 634ohms to 649ohms 1% for troop.
Added RSEL2 strap pin circuit for VR10 and VR11. 78 Removed R324 and R327.
Changed RSEL1 strap resistor R330 from 3.74Kohms to 340ohms 1% for offset function.
Changed R295 from 634ohms to 649ohms 1% for troop.
Added RSEL2 strap pin circuit for VR10 and VR11.
80
Added 45 10uF/0805 ceramic decoupling caps for per vcore.
Correctted VT1135/VT1115 signals DBI and DBO mis-connection.
81
Changed R203 from 845ohms to 374ohms 1% and C130 from 183pF to 473pF for compensation.
Changed RSEL4 strap resistor R185 from 3.74Kohms to 31.6Kohms 1%.
82 Changed FBD VTT 1.5 circuit. 84 Removed 2.5V AUX regulator circuit.
Added one OSCON cap. 270uF/16V for U18 P5VSB input.
Removed TC2.
Changed TC1 and TC3 from 100uF/16V to EC15 and EC16 1000uF/6.3V.
Changed TC3002 from 100uF/16 to EC19 OSCON 820uF/4V.
Modified P1V2_AUX circuit.
89 Correctted VT1135/VT1115 signals DBI and DBO mis-connection. 90 Added VT1135S option for FBD VTT1.5V.
Desciption
Title Document Number
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
1
http://www.msi.com.tw
Micro Star Restricted Secret
HISTORY I
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
88
Rev
0A
90
of
Page 89
Revision History II
1
Revision History (Changes from Rev 0C)
Sheet
Changed THERMTRIP_N pull-up R3308 from 51 ohms to 1 Kohms.40
63 Swapped U124 pin 4 and pin 6 for power on.
Added C3251 0.1uF and changed R3182 from 4.7Kohms to 10Kohms.
68
Added 7414 for power button and reset button de-bounce.75
84
Added U3009 regulator for 1.8V_AUX for PILOT power sequency requirement.
Desciption
Revision History (Changes from Rev 1.0)
Sheet
9
Swapped signals P0_LL_ID0 and P0_LL_ID1. Unstuffed R703 and R704. Changed Land#G4 from signal H_TESTHI9 to FSB0_BPMB_N2 for Clovertown. Changed Land#G3 from signal H_TESTHI8 to FSB0_BPMB_N3 for Clovertown. Changed Land#C9 from reserved pin to FSB0_BPMB_N1 and added pull up resistor R745 51 ohms
11
Desciption
for Clovertown.
Revision History (Changes from Rev 0D)
Sheet
Modified the power block diagram for SAS P1V2.4
5
Modified the clock block diagram for PILOT 48MHz. Added signal PXIRQ_N6 connection to 280 pin connector, and pull up R3210.
37
Renamed LAN connectors reference from JLAN3001, JLAN3000 to LAN1 and LAN2.48
50
Connected PCI-X slot PME pin to ESB2 PME_N for wake up function. Connected PXIRQ_N6 to 280 pin slot pin B2.
Added U76 for SAS1068 new ZCR spec. Connected signal PXAD19 to PCI1 pin A24 (IDSEL) for SAS1068 new ZCR spec.
53 Changed jumper JSASRAID2 to 3 pin jumper.
Connected signal PXAD21 to SAS1068 IDSEL pin for new ZCR spec. Changed R1392 and R1393 from 1K to 4.7Kohms to match with LSI Stanley's refefence schematics. Changed R3428 and R3429 from 1K to 2.7Kohms to match with LSI Stanley's refefence schematics.
A A
54 Removed FB3001.
Connected signal SYS_PWRGD_3_3V_1 to SAS TST_RST#.
56
Added P1V2 linear regulator circuit for SAS.
57 58 Stuffed C1093, C1096, C1098 22pF for EMI. 59 Stuffed CN1 and CN2 180pF for EMI.
Added 48MHz OSC for PILOT USBCLK.
60
Connected BCM5241 U123 pin8 RDAC to BCM5221 U97 pin23.
64
Modified PILOT LAN connector LED circuit for BCM5241. Reserved R3146 for PILOT 48MHz clock.
65
Desciption
Changed Land#G1 from GND pin to FSB0_BPMB_N0 and added pull up resistor R746 51 ohms for Clovertown. Swapped signals P1_LL_ID0 and P1_LL_ID1.
12
Unstuffed R655 and R656. Changed Land#G4 from signal FSB1_TESTHI9 to FSB1_BPMB_N2 for Clovertown. Changed Land#G3 from signal FSB1_TESTHI8 to FSB1_BPMB_N3 for Clovertown.
14
Changed Land#C9 from reserved pin to FSB1_BPMB_N1 and added pull up resistor R747 51 ohms for Clovertown. Changed Land#G1 from GND pin to FSB1_BPMB_N0 and added pull up resistor R748 51 ohms for Clovertown.
61 Added buffer 74LVC126 U77, U85, and U94 for signals FPWM_CPU, FPWM_PWR, and FPWM_ MEM.
Added pull up resistors R1523, R1536, and R1539 4.7K ohms to P3V3_AUX for signals PWM2, PWM3, and PWM4. Added pull up resistors R3459, R3460, and R3461 1K ohms to P3V3 for signals FPWM_CPU, FPWM_PWR, and FPWM_MEM.
63
Added R1573 0 ohm to U81 pin G2 to signal SF_AD19 for 1Mb*16 SRAM.
70 Stuffed R1345, R1348, R1351, and R1352 0 ohm.
Added R1403 620 ohms to GND for signal VTT_PWRGD. 71 Modified U84 XDP port connection for Clovertown. 72 Connected signal FSB0_PROCHOT# and FSB1_PROCHOT# to U3014 pin28 and U3015 pin28.
Changed signal FSB0_VIDSEL pull up voltage from P_VTT to P3V3.
76 78
Changed signal FSB1_VIDSEL pull up voltage from P_VTT to P3V3. 81 Changed R204 from 2.8K oms to 2.2K ohms.
70 Reserved signal VTT_PWRGD pull up R1402 1Kohms to P3V3.
Added signal SYS_PWRGD_3_3V_1 circuit for SAS TST_RST#. Changed C3224 and C3225 value from 103pF to 102pF for ADT7462 remote temperature sensor
72
properly.
73 Connected SYS_PWRGD_BUFF to U122 PCA9515 EN pin.
Changed JUSB3002 from 5 pin box-header to 4 pin box-header.
75
Stuffed R1209 1Kohms.
76 77 Removed the CSP VT1115S. 79 Removed the CSP VT1115S. 81 Added EC24 OSCON 270uF/16V for P12V bulk cap.
Added C59, C60, and C61 0.1uF/0602 for P1V8 decoupling. Removed the CSP VT1115S.
82 Added EC25 OSCON 270uF/16V for P12V bulk cap.
Added EC22, EC23 OSCON 820uF/4V for P1V5 bulk cap. Removed the CSP VT1115S.
83 Modified FBD VTT 0.9V F_VTT linear regulator circuit to meet Intel spec.
Added C3031, C3032, and C3036 22uF/1206 for P_VTT decoupling.
Title Document Number
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
1
http://www.msi.com.tw
Micro Star Restricted Secret
HISTORY II
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
89
Rev
0A
90
of
Page 90
Reserved Page
1
A A
Title Document Number
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
1
http://www.msi.com.tw
Micro Star Restricted Secret
Reserved Page
MS-9192
Last Revision Date:
Friday, April 27, 2007
Sheet
90
Rev
0A
90
of
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