MSI MS-7702 Schematics rev1.0

1

Cover Sheet BLOCK DIAGRAM

Clock Distribution PWRGD&RESET Map GPIO/MSIC TABLE VRM Intersil 6328 3+1 PHASE AMD FM1

DDR3 DIMM CH-A

DDR3 DIMM CH-B DDR REF POWER AND CAPS EMI Reserved

AMD HUDSON D2/3

A A

SWITCH/HDMI CONN.

TRAVIS & VGA CONN. SATA//eSATA/PS2/ FAN LAN RTL8111E/81105E SUPER I/O NCT66776F ACPI UPI & SYS POWER FCH CORE & DDR POWER Azalia CODEC ALC892/662 USB 2.0/3.0CONN. USB POWER/DISCHARGE

1 2 3 Power Deliver Chart 4 5 6 7 8 ~ 11 12 13 14 15 16~20 21 22 23 24 25 26 27 28 29 30

(MS-7702L2 Ver:1.0)

CPU:

AMD FM1(Llano uPGA FAMILIES)

System Chipset:

AMD - Hudson D3/D2

On Board Chipset:

CLOCK GEN --FCH internal clock gen LPC Super I/O --NCT6776F LAN-Realtek 8111E/8105E

Azalia CODEC - Realtek ALC892/662/888/

Main Memory:

DDR III * 4 (max 32G)

Expansion Slots:

PCI Express X16 Slot * 1 PCI Express X1 Slot * 3 PCI Express X1 Slot *1 for front USB3.0

VRM

Controller - Intersil 6328 3+1 Phase

mATX: 244mm * 244mm

FUSION

PCI EXPRESS X16 SLOT PCIE X1 SLOTs ATX & Front Panel Auto BOM Manual MINI PCIE CONN,

31 32 33 34 35

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FUSION BLOCK DIAGRAM

D D

VGA CONNECTOR

22

VGA

HUDSON D3

18

VGA MAIN LINK

HDMI CON

PCIE GFX x16

C C

PCIE INTERFACE

10/100/Giga bit ETHERNET 8105EL/8111EL

B B

24

PCIE INTERFACE

DP 1

DP0

21

PCIE x16

30

USB REAR

/HDR

USB REAR

29

Only D3 support USB3.0

USB 2.0

USB 3.0

FM1

8~11

UMI

HUDSON D3/D2

DDRIII 1333~1866

AZALIA

SERIAL ATA 3.0

CHA

CHB

UNBUFFERED DDRIII DIMM1 2

UNBUFFERED DDRIII DIMM3 4

ALC662/888/892

i-SATA [4:1]

23

e-SATA 5

23

12

13

28

CPU CORE POWER NB CORE POWERACPI CONTROLLER Intersil ISL6323 Intersil ISL6612A

PCIE x1 SLOT1,2,3

7

31

16~20

SPI Bus

SPI ROM 16M

18

26

CPU VDDP Power CPU VDDR Power CPU VDDA Power DUAL POWER

A A

DDR3 DRAM POWER FCH CORE POWER

ATX CON

5

26

27

32

4

SUPER I/O NCT66776F

KBD MOUSE

3

SERIAL PORT

23 25

25

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Power Deliver Chart

2.5V Shunt Regulator

VRM SW

D D

ATX P/S WITH 1A STBY CURRENT

5V

5VSB

+/-5%

C C

3.3V +/-5%

12V +/-5%

-12V +/-5%

CPU PW 12V +/-5%

5VDIMM Linear REGULATOR

VCC5_SB FET REGULATOR

VCC3_WAKE Linear REGULATOR

1.5V VDD SW REGULATOR

1.1V VCCP SW REGULATOR

VCC3_SB SW REGULATOR

VCC5_SB

REGUALTOR

VDDA25 (S0, S1)

VCCP (S0, S1) / VCC_NB (S0, S1)

1.2V VDDR REGULATOR

1.2V VDDP REGULATOR

0.75V VTT_DDR REGULATOR

CPU_VDDR (S0, S1)

CPU_VDDP (S0, S1)

VCC_DDR (S0, S1, S3)

DDRIII DIMM X4

VDD MEM VTT_DDR

NB_VCC1P1 (S0, S1)

VCC3 (S0, S1)

VCC3_SB (S0, S1, S3, S5)

1.1V_SB Linear REGULATOR

+1.1VDUAL(S0,S1,S3,S5)

15A 2 A

OPTION

0R

AMD FM1 CPU

VDDA

2.5V(1.8~2.7V) VDDCORE

0.8-2V VDDNBCORE

1.2V CPU_VDDR

1.2V

CPU_VDDP

1.2V

DDR3 MEM I/F 1.5V VCC_DDR

0.8~2.3V TBD A

HUDSON 2/3

VDDPL_11_DAC

VDDAN_11_ML

VDDCR_11

VDDAN_11_SATA

VDDAN_11_CLK

VDDAN_11_PCIE

VDDIO_33_PCIGP 3.3V (S0, S1) VDDPL_33_*_RUN

VDDPL_33_*_ALW

VDDIO_33_GBE_S

VDDAN_33_USB_S

VDDXL_33_S

VDDIO_33_S

VDDCR/AN_11_SUSB_S

VDDCR/AN_11_USB_S

VDDCR_11_GBE_S

VDDCR_11_S

100 mA 500 mA 700 mA 400 mA 900 mA

300 mA 320 mA

34 mA 1 mA 130 mA 6 mA 30 mA

500 mA 52 mA 100 mA

100 mA

0.5A 120A

20A

5A

20 mA

B B

VCC3 (S0, S1)

+5VA Linear REGULATOR

SVCC Linear REGULATOR

SVCC(S0,S3)

+5VA (S0, S1)

AUDIO CODEC

3.3V CORE

5V ANALOG

0.1A

SUPER I/O

+3.3V (S0, S1)

VCC3_WAKE (S0, S1, S3, S5)

+3.3VDUAL (S3)

0.01A

VCC3_WAKE (S0, S1, S3, S5)

A A

5

COM Port

-12V

0.1A

X1 PCIE per

3.3V 12V

3.3Vaux

3.0A

0.5A

0.1A

4

X16 PCIE per

3.3V 12V

3.3VDual

3.0A

5.5A

0.3A

USB X6 FR

VDD 5VDual

3.8A

USB X4 RL 2XPS/2

5VDual

VDD

0.5A

5VDual

2.0A

3

ENTHENET

3.3V 1.05V

70mA

300mA

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INTERNAL CLOCK MODE

D D

CH A CH B

DIMM1

DIMM2

DIMM3

DIMM4

AMD HUDSON-D3/D2

MEM_MA_CLK_H0/L0

MEM_MA_CLK_H3/L3

MEM_MA_CLK_H2/L2

C C

MEM_MA_CLK_H1/L1

AMD

FM1 APU

B B

MEM_MB_CLK_H0/L0

MEM_MB_CLK_H3/L3

MEM_MB_CLK_H1/L1

MEM_MB_CLK_H2/L2

APU_CLKP/N

DISP_CLKP/N

FCH_APU_CLKP

FCH_DISP_CLKP 100MHZ (NO SPREAD)

USBCLK

14M_25M_48M_OSC

25M_X2

SATA_X1

25M_X1

25MHZ RTC CLOCK

FOR SATA DNI

25M Hz

32K_X1

SATA_X2

32.768K Hz

PCICLK0

PCICLK2

PCICLK3

PCICLK4

LPCCLK0 LPCCLK1

RTCCLK

AZ_BITCLK

SPI_CLK

FCH_GFX_CLKP/N

FCH_GPP_CLK0P/N

FCH_GPP_CLK1P/N

FCH_GPP_CLK2P/N

FCH_GPP_CLK3P/N

FCH_GPP_CLK4P/N

32K_X2

PCICLK1

33MHZ

PCI_CLK4

PCI_CLK3PCI_CLK2

33MHZ

LPC_CLK0

LPCCLK1

33MHZ

AZ_BIT_CLK

24MHZ

SPI_CLK

xxHZ

PE16_GXF_CLK/PE16_GXF_CLK#

100MHZ

PE1_GPP_CLK0/PE1_GPP_CLK0#

100MHZ

PE1_GPP_CLK1/PE1_GPP_CLK1#

100MHZ

PE1_GPP_CLK2/PE1_GPP_CLK2#

100MHZ

PE_LAN_CLK/PE_LAN_CLK#

100MHZ

SIO NCT6776F

STRAPS SETTING,

UNUSED CLOCKS

STRAPS SETTING,

RESERVE TP

HD AUDIO

SPI ROM & HEADER

PCIE GFX SLOT (FM1, 16 LANES)

PCIE GPP SLOT1 (HUDSON-D3, 1 LANE)

PCIE GPP SLOT2 (HUDSON-D3, 1 LANE)

PCIE GPP SLOT3(HUDSON-D3, 1 LANE)

PCIE LAN (FM1, 1 LANE)

reserve LAN_CLKREQ#

PCIEX16 SLOT

PCIE X1 SLOT

PCIE LAN

PCIE LAN RTL8111E

25M Hz

A A

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FM1

PWROK(Pin AG11)

4

PWRGD MAP

3

2

1

POWER ON SEQUENCE

HUDSON D3/D2

APU_PG(Pin E26)

D D

PWR_BTN#(Pin J4)

SLP_S3#(Pin T3)

SLP_S5#(Pin W2)

APU_PWRGD

FCH_PWRGDPWR_GD(Pin N7)

NCT 6776F

SLP_S5#

SLP_S5#(Pin 84)

SUSB#(Pin 64)SLP_S3#

PSOUT# (Pin 60)PSOUT#

ATX_POWER

U16

NCP1587

VRM U5

ISL6328CR

VDDPWRGD(Pin 34)

U32

NCP1587

U41

*

PS_ON#

FCH_PWRGD

CPU_VDD

VRM_PWRGD

U30

NCP102

Pin16

ATX_PWROK U23 (UP7501) 5VDIMM

Pin8

F_PANEL1PSIN#

VCC_DDR

CPU_VDDP CPU_VDDR

NB_VCC1P1

*

U54 (UP7704) VDDA_25

MEANS OPTION

PSON# (Pin 63)

PSIN# (Pin 61)

C C

ATX_PWROK

SLP_S5#

ATX_PWROK APU_FM1R1 VCC_DDR

VRM_PWRGD

B B

ATX_PWROK NB_VCC1P1 FP_RST# SLP_S3#

D41

CPU_VDDP_VDDR_EN

NBCORE_EN

D40

DDR_EN

VCORE_EN

APU_PWRGD

FCH_PWRGD_R

EN(Pin 25)

PWROK(Pin 35)

RESET MAP

FM1

RESET_L(Pin AJ13)

HUDSON D3/D2

CLK GEN

Reserve TP Reserve TP

PCIE_RST#(Pin AE2)

A_RST#(Pin AD5)Super IO

PCIE_RST2#(Pin AB6) PCIRST#(Pin AB5)

5

PCIE 16X slot PCIE 1X slot 1 PCIE 1X slot 2 PCIE LAN

A A

LPC debug

ICS-9VRS4818

APU_RST#(Pin F26)

SYS_RESET#(Pin U4)

FP_RST#

APU_RST#

RESET#(Pin 12)RESET_IN#(Pin 70)

F_PANEL

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PWRGD/RESET MAP

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DDR DIMM Config.

SIO NCT6776F GPIO Config

D D

50 GP60 VSB

78 GP36 VSB SIO_VDUAL_EN

GPIO Power Rail Function descriptionPin

GP4638 VSB SIO_WAKE

YLW_LED/GP4539 VSB

GRN_LED/GP4440 VSB PWR_LED

GP6742 VSB

GP6544

GP6445 VSB

GP6347 VSB

GP6248 VSB

GP6149 VSB

VSB

SUS_LED

USB_EN

MB_ID0

MB_ID1

MB_ID2

COM_GPIO2

CHASSIS_ID1

CHASSIS_ID2

Comment

OD

GPI

reserved

DEVICE

DIMM 1

10100000B

CH-A

10100010B A4H

CH-A MEM_MA_CLK_H3/L3

DIMM 3

10100001B

CH-B

DIMM 4

10100011B A6H

CH-B

CLOCKADDRESS

MEM_MA_CLK_H1/L1

A0H

MEM_MA_CLK_H2/L2

MEM_MA_CLK_H0/L0DIMM 2

MEM_MB_CLK_H1/L1

A2H

MEM_MB_CLK_H2/L2

MEM_MB_CLK_H0/L0 MEM_MB_CLK_H3/L3

SMBus TABLE

FCH HUDSON D3/D2GPIO Config

AJ3

C C

B B

AD22 SATA_ACT#/GPIO67 SATA_LED#:SATA Channel Active

M6

V3 SPI_CLK/GPIO162 SPI Clock

V6 SPI_DI/GPIO164 SPI Data In

V5 SPI_DO/GPIO163 SPI Data Output

T6 SPI_CS1#/GPIO165 SPI Chip Select1#

Y6 SPI_HOLD#/GEVENT9# SPI HOLD#. Assert low to hold the SPI transaction.

J7 USB_OC1#/TDI/GEVENT13# OC#1:USB2.0 port 4,5

P5 USB_OC2#/TCK/GEVENT14#

P5 USB_OC3#/

P6 USB_OC4#/IR_RX0/

T1 OC#5:USB2.0 port 2,3

R8 OC#6:USB2.0 port 0,1

M7 OC#7:USB 3.0 port 2,USB 2.0 port12BLINK/USB_OC7#/

pin Name Function description

AD0/GPIO0 CLEAR_CMOS

IR_LED#/LLB#/GPIO184 MINI_PWRONJ2

TEMPIN3/TALERT#/ GPIO174

ROM_RST#/SPI_WP#/GPIO161V1 SPI write protect (active low)

USB_OC0#/SPI_TPM_CS#/ TRST#/GEVENT12#

AC_PRES/TDO/GEVENT15#

GEVENT16# USB_OC5#/IR_TX0/ GEVENT17# USB_OC6#/IR_TX1/ GEVENT6#

GEVENT18#

GPIO[171::173];GPIO[175::182]; GPIO[193::194]

FCH_TALERT#:Thermal Alert. The FCH can be programmed to generate an SMI, SCI, or IRQ13 through GPE, or generate an SMI without GPE in response to the signal’s assertion.

OC#0:USB 3.0 port 3,USB 2.0 port 13T8

OC#2:USB2.0 port 8,9

OC#3:USB 3.0 port 0,USB 2.0 port 10

OC#4:USB 3.0 port 1,USB 2.0 port 11

Configure as one of the following: 10-kΩ 5% pull-up resistor to +3.3V_S5. 10-kΩ 5% pull-down resistor.

SOURCE

DP0_AUXP_C /DP0_AUXN_C

APU

DP1_AUXP_C /DP1_AUXN_C

SCLK0/SDATA0

FCH

SCLK1/SDATA1 LAN,PCIE SLOTs,MINI_PCIE

SCLK3/SDATA3 TP

RESET TABLE

SOURCE

PCIE_RST# PCIe 16X,1X,LAN,MINI_PCIE

FCH

FRONT PANEL

A_RST# SIO,LPC debug PCIE_RST2# RESERVE TP LDT_RST# APU AZ_RST# AZALIA CODEC DDR3_RST# NC FC_RST# DEBUG BUS ROM_RST# NC FP_RST# FCH,CLOCK GEN

LINKED DEVICESINGLE NAME

HDMI

Hudson D2/3 DP to VGA translator

DIMMs,CLOCK GEN ,SIO

LINKED DEVICESINGLE NAME

A A

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GPIO/MSIC TABLE

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ISL6328/6612A 3+1 Phase

D D

VRM_PWRGD27

COREFB+_R

VCCP

COREFB+10

COREFB-10

C C

CPU_VDDNB

NBCOREFB+10

B B

VRM_PWRGD_R

ATX_PWROK25,26,27,33

APU_FM1R110

VCORE_EN_R25,27

A A

Soft-Start Ramp Rate: TBD mV/us

OCP ~ 160A Work F=230Khz

VCC5

R5 10KR0402R510KR0402

C16

C1500p50X0402

R22

47.5R1%0402

R13 100R0402R13 100R0402 R14 0R0402R14 0R0402

R23 0R0402R23 0R0402 R24 100R0402R24 100R0402

C110

20.5KR1%0402

R95

R95 X_47.5R1%0402

X_47.5R1%0402

R96 1.37KR1%0402-HFR96 1.37KR1%0402-HF R88 100R0402R88 100R0402 R89 0R0402R89 0R0402

VCC5_ISL6328

VCC5_ISL6328 VCC5_ISL6328 VCC5_ISL6328

VCCP

R75

R75 X_1KR0402

X_1KR0402

R76 X_10KR0402R76 X_10KR0402

D11 S-RB751V-40_SOD323-RHD11 S-RB751V-40_SOD323-RH

D10 S-RB751V-40_SOD323-RHD10 S-RB751V-40_SOD323-RH

VCORE_EN_R

VRM_PWRGD_R

C100 X_C0.1u16Y0402C100 X_C0.1u16Y0402

VRM_PWROK

C102 X_C0.1u16Y0402C102 X_C0.1u16Y0402

VCORE_EN

C45 C2.2u6.3X50402C45 C2.2u6.3X50402

0.98V Threshold

VCORE_EN

0.95V Threshold

VRM_PWROK

APU_SVD10 APU_SVC10

R10

X_2.15KR1%0402

R12

2.37KR1%0402

C17

C17 C2200p50X0402

C2200p50X0402

R21

R21 301R1%0402

301R1%0402

R41R41 R2 0R0402R2 0R0402

C46 C150P50N0402C46 C150P50N0402

R11

4.99KR1%0402

C47 C0.01U16X0402C47 C0.01U16X0402

VRM_PWRGD_R

C31

C6800P50X0402

APU_PWRGD10,16

C18 X_C0.1u16Y0402C18 X_C0.1u16Y0402

C32

C32 X_C0.1u16Y0402

X_C0.1u16Y0402

R127

34KR1%0402

C99 X_C680p50XC99 X_C680p50X

R107

6.04KR1%0402

C93

C220p50N0402

C85 X_C0.1u16Y0402C85 X_C0.1u16Y0402 R140

R60 0R0402R60 0R0402

R20 X_100R0402R20 X_100R0402 R73 X_100R0402R73 X_100R0402 R77 X_100R0402R77 X_100R0402 U25

C73

C0.015u16X0402

R53

107KR1%0402-RH

C108

C0.022u50X

Disable APD

R72

10KR1%0402

R70

25.5KR1%0402-RH

C48

C48 X_C0.1u16Y0402

X_C0.1u16Y0402

NBCOREFB+_R

C44

X_C1500p50X0402

R78

20KR1%0402

VCC5_ISL6328

U5

25

EN

35

PWROK

OD

34

VDDPWRGD

6

SVD

5

SVC

VCORE_COMP

17

R19

X_35.7KR1%0402

C66

C0.1U25X

16

15

14

13

19

18

10

1 2

3 8

9 4

COMP FB

FB_PSI

VSEN

RGND

COMP_NB FB_NB

VSEN_NB APD APA

FS OFS DRPCTRL

OCP

VCORE_FB

VRM_PSI

COREFB+_R

COREFB-_R

VDDNB_COMP

VDDNB_COMP VDDNB_FBNBCOREFB+_R

VRM_APD VRM_APA

VRM_FS ISEN_NB_R VRM_OFS VRM_DRPCTRL

VRM_OCP

VCC5

VRM_PWRGD

DS

C68

Q8

G

X_C0.1u16Y0402

X_N-2N7002_SOT23Q8X_N-2N7002_SOT23

+12VINVCC5

R74

G

+12VIN

R74 10KR0402

10KR0402

DS

Q13

Q13 N-2N7002_SOT23

N-2N7002_SOT23

DS

G

CHOKE7

CH-1.1u35A1.7m-RH

R81

10.7KR1%0402

Q14

Q14 N-2N7002_SOT23

N-2N7002_SOT23

1 2

+

C334

C10u16Y1206

C340

X_C0.01u25X0402

12

2

1

5

B

ATX_12V

12V

GND GND

PWR-2X2M_natural-RH

5

CE

Q7

4

3

R69

R69 X_10KR0402

X_10KR0402

X_N-SST3904_SOT23Q7X_N-SST3904_SOT23

VCC5

BOTTOM PAD CONNECT TO GND Through 8 VIAs

Make sure +12VIN connector plug in

+

12

EC25

CD270u16SO-RH-2

4

7

VCC

GND

ISL6328CRU5ISL6328CR

49

EC17

CD270u16SO-RH-2

4

R80

2.2R0805

BOOT_NB UGATE_NB PHASE_NB LGATE_NB

ISEN_NB+

ISEN_NB-

+

12

C106

C106 C0.1u10X0402

C0.1u10X0402

PVCC

GVOT

BOOT1 UGATE1 PHASE1 LGATE1

BOOT2 UGATE2 PHASE2 LGATE2

PWM3 PWM4

ISEN1+

ISEN1-

ISEN2+

ISEN2-

ISEN3+

ISEN3-

ISEN4+

ISEN4-

TCOMP1 TCOMP2

R92

R92 1KR0402

1KR0402

EC5

CD270u16SO-RH-2

42 29

31 32 33 30

27 26 24 28

37 36

20 21

22 23

44 43

46 45

40 39 38 41

48 47

11 12

C92

C92 C2.2U6.3X0603

C2.2U6.3X0603

+

12

+12VIN VCC5

C70 C2.2u25X1206-HF-1C70 C2.2u25X1206-HF-1

BOOT1 BOOT1_R

R82

2.2R1%0805

BOOT2 BOOT2_R

R68

2.2R1%0805

PWM3

R52 249R1%0402R52 249R1%0402

PHASE11_R

PHASE11

R28

4.02KR1%0402

ISEN2_R ISEN2

R50 249R1%0402R50 249R1%0402

PHASE22_R

PHASE22

R27

4.02KR1%0402

ISEN3_R

R111 237R1%0402R111 237R1%0402

PHASE33_R

PHASE33

R140

4.02KR1%0402

Disable PWM4

VCC5

NB_BOOT NB_BOOT_R

R110

2.2R1%0805

R113 180R1%0402R113 180R1%0402

PHASE_NB_R

PHASE_NBA

R116

12.1KR1%0402

R55 2.8KR1%0402R55 2.8KR1%0402

R66 1.5KR1%0402R66 1.5KR1%0402

R54

C59

C22p50N0402

19.6KR1%0402

VCORE_EN

VIN

C315

EC11

C0.1u16Y0402

CD270u16SO-RH-2

R131

2.2R0805

C87

C87 C0.1U25X

C0.1U25X

C62

C62 C0.1U25X

C0.1U25X

R51 X_0R0402R51 X_0R0402 C21 C0.22U16XC21 C0.22U16X

R49 X_0R0402R49 X_0R0402 C33 C0.22U16XC33 C0.22U16X

R137 X_0R0402R137 X_0R0402 C118 C0.22U16XC118 C0.22U16X

C104

C104 C0.1U25X

C0.1U25X

R112 X_0R0402R112 X_0R0402 C107 C0.1U25XC107 C0.1U25X

R120

X_2.2R0805

C105

C105 C1U16X5

C1U16X5

UGATE1

PHASE1 LGATE1

UGATE2

PHASE2 LGATE2

ISEN1ISEN1_R

C35 C0.1U25XC35 C0.1U25X

ISEN3

UGATE_NB

PHASE_NB LGATE_NB

ISEN_NB

Close PHASE1

RT1

Output Choke

10KRT1%

Vcore side

R56

16.2KR1%0402

C34

C119

C0.1U25X

C109

C109 C0.1U25X

C0.1U25X

3

2

1

VIN

C148

C288

C1U16X5

C10u16Y1206

CHOKE2 CH-0.36u55A0.46m-HFCHOKE2 CH-0.36u55A0.46m-HF

1 2

12

CP9CP9

PHASE11 ISEN1

C168

C163

C1U16X5

C10u16Y1206

CHOKE4 CH-0.36u55A0.46m-HFCHOKE4 CH-0.36u55A0.46m-HF

1 2

12

CP11CP11

PHASE22 ISEN2

C232

C225

C1U16X5

C10u16Y1206

CHOKE6 CH-0.36u55A0.46m-HFCHOKE6 CH-0.36u55A0.46m-HF

1 2

12

CP13CP13

PHASE33 ISEN3

VCORE output 80A OCP:160A

12

C144

CP10CP10

C10u6.3X50805

Place close to CHOKE

12

C184

CP12CP12

C10u6.3X50805

Place close to CHOKE

12

C253

CP14CP14

C10u6.3X50805

Place close to CHOKE

VCCP

+

12

+

12

EC10

EC23

CD820u2.5SO-RH-3

VCCP

+

12

EC22

EC16

CD820u2.5SO-RH-3

VCCP

+

12

+

12

EC15

EC9

CD820u2.5SO-RH-3

CPU_VDDNB

+12VIN

R326

2.2R0805

R1 0R0805R1 0R0805 C338

C338 C1U25X0805

C1U25X0805

VCCP

+

12

+

12

EC26

CD820u2.5SO-RH-3

EC74

CD820u2.5SO-RH-3

C1

C1 X_C1U25X0805

X_C1U25X0805

+

12

+

12

EC73

CD820u2.5SO-RH-3

+

12

+

12

EC78

C470u2.5pSO-RH

U25

6

VCC

UGATE

7

BOOT

PVCC

PHASE

4

GND

3

PWM

LGATE

ISL6612ACBZT_SOIC8-RH

UGATE1

PHASE1

LGATE1

bottom side

EC77

C470u2.5pSO-RH

UGATE2 UGATE2_R

PHASE2

Top side

EC79

LGATE2

C470u2.5pSO-RH

UGATE3 UGATE3_R

1

BOOT3

2

R297

2.2R1%0805

8

PHASE3

LGATE3PWM3

5

R198 1R0805R198 1R0805 R212 10KR0402R212 10KR0402

R199 0R0805R199 0R0805

R261 1R0805R261 1R0805 R265 10KR0402R265 10KR0402

R259 0R0805R259 0R0805

R296 1R0805R296 1R0805 C328

C328

R272 10KR0402R272 10KR0402

C0.1U25X

R320 0R0805R320 0R0805

UGATE1_R

LGATE1_R

LGATE2_R

LGATE3_R

Q21

Q25

D

G

S

N-P0903BD

X_N-P0903BD

Q26

Q20

R152

D

G

S

N-P0603BD

R152

D

G

2.2R1206

S

C126

C126 C1000P50X0402

C1000P50X0402

N-P0603BD

VIN

Q37

Q32

D

G

S

N-P0903BD

X_N-P0903BD

Q31

Q38

D

G

S

N-P0603BD

R226

D

G

2.2R1206

S

C174

C174 C1000P50X0402

C1000P50X0402

N-P0603BD

VIN

Q41

Q44

D

G

S

N-P0903BD

X_N-P0903BD

R270

Q42

Q45

D

G

S

N-P0603BD

2.2R1206

G

S

C246

C246 C1000P50X0402

C1000P50X0402

N-P0603BD

VIN

C95

C125

C10u16Y1206

C1U16X5

Q17

D

LGATE_NB_R

G

D

S

N-P0903BD

Q15

D

S

N-P0603BD

CHOKE1 CH-0.36u55A0.46m-HFCHOKE1 CH-0.36u55A0.46m-HF

1 2

R58

Q16

D

2.2R1206

G

S

C53

C53 C1000P50X0402

C1000P50X0402

N-P0603BD

PHASE_NBA ISEN_NB

Title

Size Document Number Rev

Date: Sheet

12

CP7CP7

ISL6328/6612A 3+1 Phase

C

FUSION 1.0

UGATE_NB

PHASE_NB

LGATE_NB

TP1TP1

TP2TP2

3

VCC5_ISL6328 VIN

R136 1R0805R136 1R0805 R126 10KR0402R126 10KR0402

R91 0R0805R91 0R0805

UGATE_NB_R

2

NB_CORE output 20A OCP:32A

CPU_VDDNB

+

12

C123

CP8CP8

C10u6.3X50805

Place close to CHOKE

MICRO-START INT'L CO.,LTD.

1

12

EC7

EC6

CD820u2.5SO-RH-3

735Saturday, August 13, 2011

of

CD820u2.5SO-RH-3

5

4

3

2

1

FM1 PCIE I/F

mach@CRB PCIE AC Capacitors:75nF to 200nF

D D

P_GFX_RXP0

GFX_RX0P31 GFX_RX0N31 GFX_RX1P31 GFX_RX1N31 GFX_RX2P31 GFX_RX2N31 GFX_RX3P31 GFX_RX3N31 GFX_RX4P31 GFX_RX4N31 GFX_RX5P31 GFX_RX5N31 GFX_RX6P31 GFX_RX6N31 GFX_RX7P31 GFX_RX7N31 GFX_RX8P31 GFX_RX8N31

C C

B B

VCC_VDDP_B

GFX_RX9P31 GFX_RX9N31 GFX_RX10P31 GFX_RX10N31 GFX_RX11P31 GFX_RX11N31 GFX_RX12P31 GFX_RX12N31 GFX_RX13P31 GFX_RX13N31 GFX_RX14P31 GFX_RX14N31 GFX_RX15P31 GFX_RX15N31

LAN_RXC_P24 LAN_RXC_N24

UMI_RX0P16 UMI_RX0N16 UMI_RX1P16 UMI_RX1N16 UMI_RX2P16 UMI_RX2N16 UMI_RX3P16 UMI_RX3N16

R252 196R1%R252 196R1%

Layout: Place within 1.5'' of APU

LAN_RXC_P LAN_RXC_N

APU_P_ZVDDP

AF8

AF9 AE7 AE8 AD5 AD6 AD8 AD9 AC7 AC8 AB5 AB6 AB8 AB9 AA7 AA8

AH5 AH6 AH8 AH9 AG7 AG8

AF5

AF6

AL5

AL4

AK3

AK2

AJ2

AJ1

AJ4

AJ5

Y5 Y6 Y8

Y9 W7 W8

V5

V6

V8

V9

U7

U8

T5

T6

T8

T9

J7

P_GFX_RXN0 P_GFX_RXP1 P_GFX_RXN1 P_GFX_RXP2 P_GFX_RXN2 P_GFX_RXP3 P_GFX_RXN3 P_GFX_RXP4 P_GFX_RXN4 P_GFX_RXP5 P_GFX_RXN5 P_GFX_RXP6 P_GFX_RXN6 P_GFX_RXP7 P_GFX_RXN7 P_GFX_RXP8 P_GFX_RXN8 P_GFX_RXP9 P_GFX_RXN9 P_GFX_RXP10 P_GFX_RXN10 P_GFX_RXP11 P_GFX_RXN11 P_GFX_RXP12 P_GFX_RXN12 P_GFX_RXP13 P_GFX_RXN13 P_GFX_RXP14 P_GFX_RXN14 P_GFX_RXP15 P_GFX_RXN15

P_GPP_RXP0 P_GPP_RXN0 P_GPP_RXP1 P_GPP_RXN1 P_GPP_RXP2 P_GPP_RXN2 P_GPP_RXP3 P_GPP_RXN3

P_UMI_RXP0 P_UMI_RXN0 P_UMI_RXP1 P_UMI_RXN1 P_UMI_RXP2 P_UMI_RXN2 P_UMI_RXP3 P_UMI_RXN3

P_ZVDDP

PCI EXPRESS

U100H

GPP GRAPHICS

UMI_LINK

P_GFX_TXP0 P_GFX_TXN0 P_GFX_TXP1 P_GFX_TXN1 P_GFX_TXP2 P_GFX_TXN2 P_GFX_TXP3 P_GFX_TXN3 P_GFX_TXP4 P_GFX_TXN4 P_GFX_TXP5 P_GFX_TXN5 P_GFX_TXP6 P_GFX_TXN6 P_GFX_TXP7 P_GFX_TXN7 P_GFX_TXP8 P_GFX_TXN8 P_GFX_TXP9

P_GFX_TXN9 P_GFX_TXP10 P_GFX_TXN10 P_GFX_TXP11 P_GFX_TXN11 P_GFX_TXP12 P_GFX_TXN12 P_GFX_TXP13 P_GFX_TXN13 P_GFX_TXP14 P_GFX_TXN14 P_GFX_TXP15 P_GFX_TXN15

P_GPP_TXP0

P_GPP_TXN0

P_GPP_TXP1

P_GPP_TXN1

P_GPP_TXP2

P_GPP_TXN2

P_GPP_TXP3

P_GPP_TXN3

P_UMI_TXP0 P_UMI_TXN0 P_UMI_TXP1 P_UMI_TXN1 P_UMI_TXP2 P_UMI_TXN2 P_UMI_TXP3 P_UMI_TXN3

P_ZVSS

<APU>

Layout: PLACE CAPS WITH APU < 1 INCH ROUTE ALL PCIE AS 85OHM +/-10%

AE2 AE1 AE4 AE5 AD2 AD3 AC2 AC1 AC4 AC5 AB2 AB3 AA2 AA1 AA4 AA5 Y2 Y3 W2 W1 W4 W5 V2 V3 U2 U1 U4 U5 T2 T3 R2 R1

AH2 AH3 AG2 AG1 AG4 AG5 AF2 AF3

UMI_TX0P_APU

AK8

UMI_TX0N_APU

AK9

UMI_TX1P_APU

AL7

UMI_TX1N_APU

AL8

UMI_TX2P_APU

AK5

UMI_TX2N_APU

AK6

UMI_TX3P_APU

AJ7

UMI_TX3N_APU

AJ8

APU_P_ZVSS

J6

GFX_TXP0 GFX_TXN0 GFX_TXP1 GFX_TXN1 GFX_TXP2 GFX_TXN2 GFX_TXP3 GFX_TXN3 GFX_TXP4 GFX_TXN4 GFX_TXP5 GFX_TXN5 GFX_TXP6 GFX_TXN6 GFX_TXP7 GFX_TXN7 GFX_TXP8 GFX_TXN8 GFX_TXP9 GFX_TXN9 GFX_TXP10 GFX_TXN10 GFX_TXP11 GFX_TXN11 GFX_TXP12 GFX_TXN12 GFX_TXP13 GFX_TXN13 GFX_TXP14 GFX_TXN14 GFX_TXP15 GFX_TXN15

LAN_TXP LAN_TXN

C423 C0.1u10X0402C423 C0.1u10X0402 C422 C0.1u10X0402C422 C0.1u10X0402 C420 C0.1u10X0402C420 C0.1u10X0402 C421 C0.1u10X0402C421 C0.1u10X0402 C418 C0.1u10X0402C418 C0.1u10X0402 C419 C0.1u10X0402C419 C0.1u10X0402 C417 C0.1u10X0402C417 C0.1u10X0402 C416 C0.1u10X0402C416 C0.1u10X0402 C414 C0.1u10X0402C414 C0.1u10X0402 C415 C0.1u10X0402C415 C0.1u10X0402 C412 C0.1u10X0402C412 C0.1u10X0402 C413 C0.1u10X0402C413 C0.1u10X0402 C411 C0.1u10X0402C411 C0.1u10X0402 C410 C0.1u10X0402C410 C0.1u10X0402 C409 C0.1u10X0402C409 C0.1u10X0402 C408 C0.1u10X0402C408 C0.1u10X0402 C406 C0.1u10X0402C406 C0.1u10X0402 C407 C0.1u10X0402C407 C0.1u10X0402 C405 C0.1u10X0402C405 C0.1u10X0402 C404 C0.1u10X0402C404 C0.1u10X0402 C402 C0.1u10X0402C402 C0.1u10X0402 C403 C0.1u10X0402C403 C0.1u10X0402 C400 C0.1u10X0402C400 C0.1u10X0402 C401 C0.1u10X0402C401 C0.1u10X0402 C399 C0.1u10X0402C399 C0.1u10X0402 C398 C0.1u10X0402C398 C0.1u10X0402 C396 C0.1u10X0402C396 C0.1u10X0402 C397 C0.1u10X0402C397 C0.1u10X0402 C394 C0.1u10X0402C394 C0.1u10X0402 C395 C0.1u10X0402C395 C0.1u10X0402 C393 C0.1u10X0402C393 C0.1u10X0402 C392 C0.1u10X0402C392 C0.1u10X0402

C799 C0.1u10X0402C799 C0.1u10X0402 C800 C0.1u10X0402C800 C0.1u10X0402

C318 C0.1u10X0402C318 C0.1u10X0402 C319 C0.1u10X0402C319 C0.1u10X0402 C304 C0.1u10X0402C304 C0.1u10X0402 C305 C0.1u10X0402C305 C0.1u10X0402 C302 C0.1u10X0402C302 C0.1u10X0402 C303 C0.1u10X0402C303 C0.1u10X0402 C316 C0.1u10X0402C316 C0.1u10X0402 C317 C0.1u10X0402C317 C0.1u10X0402

R253 196R1%R253 196R1%

Layout: Place within 1.5'' of APU

GFX_TXC_0P 31 GFX_TXC_0N 31 GFX_TXC_1P 31 GFX_TXC_1N 31 GFX_TXC_2P 31 GFX_TXC_2N 31 GFX_TXC_3P 31 GFX_TXC_3N 31 GFX_TXC_4P 31 GFX_TXC_4N 31 GFX_TXC_5P 31 GFX_TXC_5N 31 GFX_TXC_6P 31 GFX_TXC_6N 31 GFX_TXC_7P 31 GFX_TXC_7N 31 GFX_TXC_8P 31 GFX_TXC_8N 31 GFX_TXC_9P 31 GFX_TXC_9N 31 GFX_TXC_10P 31 GFX_TXC_10N 31 GFX_TXC_11P 31 GFX_TXC_11N 31 GFX_TXC_12P 31 GFX_TXC_12N 31 GFX_TXC_13P 31 GFX_TXC_13N 31 GFX_TXC_14P 31 GFX_TXC_14N 31 GFX_TXC_15P 31 GFX_TXC_15N 31

LAN_TXC_P 24 LAN_TXC_N 24

UMI_TX0P 16 UMI_TX0N 16 UMI_TX1P 16 UMI_TX1N 16 UMI_TX2P 16 UMI_TX2N 16 UMI_TX3P 16 UMI_TX3N 16

A A

MICRO-START INT'L CO.,LTD.

Title

FM1 PCIE I/F

Size Document Number Rev

B

Date: Sheet

5

4

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

FUSION 1.0

835Wednesday, August 17, 2011

of

1

of

5

4

3

2

1

FM1DDR3 I/F

MEM_MA_DQS_L[7..0]12 MEM_MA_DQS_H[7..0]12

MEM_MA_DM[7..0]12

D D

MEM_MA_ADD0 MEM_MA_ADD1 MEM_MA_ADD2 MEM_MA_ADD3 MEM_MA_ADD4 MEM_MA_ADD5 MEM_MA_ADD6 MEM_MA_ADD7 MEM_MA_ADD8 MEM_MA_ADD9 MEM_MA_ADD10 MEM_MA_ADD11 MEM_MA_ADD12 MEM_MA_ADD13

MEM_MA_ADD[15..0]12

MEM_MA_BANK012 MEM_MA_BANK112 MEM_MA_BANK212

C C

mach@CLOCK assignment can be changed

MEM_MA_CLK_H012 MEM_MA_CLK_L012 MEM_MA_CLK_H112 MEM_MA_CLK_L112 MEM_MA_CLK_H212 MEM_MA_CLK_L212 MEM_MA_CLK_H312 MEM_MA_CLK_L312

MEM_MA_CKE012 MEM_MA_CKE112

MEM_MA0_ODT012 MEM_MA0_ODT112 MEM_MA1_ODT012 MEM_MA1_ODT112

MEM_MA0_CS_L012 MEM_MA0_CS_L112 MEM_MA1_CS_L012

B B

MEM_MA1_CS_L112 MEM_MA_RAS_L12

MEM_MA_CAS_L12 MEM_MA_WE_L12

MEM_MA_RESET#12 MEM_MA_HOT#12

APU_M_VREF

VCC_DDR

MEM_MA_ADD14 MEM_MA_ADD15

MEM_MA_BANK0 MEM_MA_BANK1 MEM_MA_BANK2

MEM_MA_DM0 MEM_MA_DM1 MEM_MA_DM2 MEM_MA_DM3 MEM_MA_DM4 MEM_MA_DM5 MEM_MA_DM6 MEM_MA_DM7

MEM_MA_DQS_H0 MEM_MA_DQS_L0 MEM_MA_DQS_H1 MEM_MA_DQS_L1 MEM_MA_DQS_H2 MEM_MA_DQS_L2 MEM_MA_DQS_H3 MEM_MA_DQS_L3 MEM_MA_DQS_H4 MEM_MA_DQS_L4 MEM_MA_DQS_H5 MEM_MA_DQS_L5 MEM_MA_DQS_H6 MEM_MA_DQS_L6 MEM_MA_DQS_H7 MEM_MA_DQS_L7

MEM_MA_CLK_H0 MEM_MA_CLK_L0 MEM_MA_CLK_H1 MEM_MA_CLK_L1 MEM_MA_CLK_H2 MEM_MA_CLK_L2 MEM_MA_CLK_H3 MEM_MA_CLK_L3

MEM_MA_CKE0 MEM_MA_CKE1

MEM_MA0_ODT0 MEM_MA0_ODT1 MEM_MA1_ODT0 MEM_MA1_ODT1

MEM_MA0_CS_L0 MEM_MA0_CS_L1 MEM_MA1_CS_L0 MEM_MA1_CS_L1

MEM_MA_RAS_L MEM_MA_CAS_L MEM_MA_WE_L

MEM_MA_RESET# MEM_MA_HOT#

R254 39.2R1%0402R254 39.2R1%0402

Layout: Place within 1.5'' of APU

APU_M_ZVDDIO

AE25 AG21

AE28 AE29 AG24 AG25

AE16 AD16

AA24 AC27 AA25 AC26

AB26 AB25

W26

AF29

AF17

AF20 AF21

W23

W25

MA_ADD0

V27

MA_ADD1

P27

MA_ADD2

R25

MA_ADD3

P26

MA_ADD4

R24

MA_ADD5

P24

MA_ADD6

P23

MA_ADD7

N26

MA_ADD8

N23

MA_ADD9

M25

MA_ADD10

V24

MA_ADD11

N25

MA_ADD12

M24

MA_ADD13

Y23

MA_ADD14

L27

MA_ADD15

L24

MA_BANK0 MA_BANK1

V25

MA_BANK2

L26

MA_DM0

H12

MA_DM1

E17

MA_DM2

H21

MA_DM3

F25

MA_DM4 MA_DM5 MA_DM6 MA_DM7 MA_DM8

G29

MA_DQS_H0

G13

MA_DQS_L0

F13

MA_DQS_H1

H17

MA_DQS_L1

G17

MA_DQS_H2

F21

MA_DQS_L2

E21

MA_DQS_H3

G26

MA_DQS_L3

G25

MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7 MA_DQS_H8

F30

MA_DQS_L8

E30

MA_CLK_H0

U27

MA_CLK_L0

U26

MA_CLK_H1

T23

MA_CLK_L1

U23

MA_CLK_H2

T25

MA_CLK_L2

T26

MA_CLK_H3

R27

MA_CLK_L3

R28

MA_CKE0

L23

MA_CKE1

K26

MA0_ODT0 MA0_ODT1 MA1_ODT0 MA1_ODT1

MA0_CS_L0

Y27

MA0_CS_L1 MA1_CS_L0 MA1_CS_L1

MA_RAS_L MA_CAS_L

Y24

MA_WE_L

Y26

MA_RESET_L

J25

MA_EVENT_L

U24

M_VREF

K22

M_ZVDDIO

J24

MEMORY CHANNEL A

U100A

E12 F12 H14 E15 G11 H11 E14 G14

F16 G16 H18 F19 F15 H15 E18 F18

G20 H20 E23 G23 G19 E20 F22 G22

F24 H24 E27 F27 H23 E24 E26 H26

AD30 AF30 AG27 AF27 AD31 AE31 AG28 AD28

AF26 AD25 AF23 AE23 AD27 AE26 AF24 AD24

AG22 AD21 AE19 AG19 AD22 AE22 AE20 AD19

AG18 AE17 AF15 AG15 AD18 AF18 AG16 AD15

F28 E29 G31 H30 H27 G28 F31 H29

MEM_MA_DATA0 MEM_MA_DATA1 MEM_MA_DATA2 MEM_MA_DATA3 MEM_MA_DATA4 MEM_MA_DATA5 MEM_MA_DATA6 MEM_MA_DATA7

MEM_MA_DATA8 MEM_MA_DATA9 MEM_MA_DATA10 MEM_MA_DATA11 MEM_MA_DATA12 MEM_MA_DATA13 MEM_MA_DATA14 MEM_MA_DATA15

MEM_MA_DATA16 MEM_MA_DATA17 MEM_MA_DATA18 MEM_MA_DATA19 MEM_MA_DATA20 MEM_MA_DATA21 MEM_MA_DATA22 MEM_MA_DATA23

MEM_MA_DATA24 MEM_MA_DATA25 MEM_MA_DATA26 MEM_MA_DATA27 MEM_MA_DATA28 MEM_MA_DATA29 MEM_MA_DATA30 MEM_MA_DATA31

MEM_MA_DATA32 MEM_MA_DATA33 MEM_MA_DATA34 MEM_MA_DATA35 MEM_MA_DATA36 MEM_MA_DATA37 MEM_MA_DATA38 MEM_MA_DATA39

MEM_MA_DATA40 MEM_MA_DATA41 MEM_MA_DATA42 MEM_MA_DATA43 MEM_MA_DATA44 MEM_MA_DATA45 MEM_MA_DATA46 MEM_MA_DATA47

MEM_MA_DATA48 MEM_MA_DATA49 MEM_MA_DATA50 MEM_MA_DATA51 MEM_MA_DATA52 MEM_MA_DATA53 MEM_MA_DATA54 MEM_MA_DATA55

MEM_MA_DATA56 MEM_MA_DATA57 MEM_MA_DATA58 MEM_MA_DATA59 MEM_MA_DATA60 MEM_MA_DATA61 MEM_MA_DATA62 MEM_MA_DATA63

MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7

MA_DATA8

MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15

MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23

MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31

MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39

MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47

MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55

MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63

MA_CHECK0 MA_CHECK1 MA_CHECK2 MA_CHECK3 MA_CHECK4 MA_CHECK5 MA_CHECK6 MA_CHECK7

<APU>

MEM_MA_DATA[63..0] 12

MEM_MB_ADD[15..0]13

MEM_MB_BANK013 MEM_MB_BANK113 MEM_MB_BANK213

MEM_MB_CLK_H013 MEM_MB_CLK_L013 MEM_MB_CLK_H113 MEM_MB_CLK_L113 MEM_MB_CLK_H213 MEM_MB_CLK_L213 MEM_MB_CLK_H313 MEM_MB_CLK_L313

MEM_MB_CKE013 MEM_MB_CKE113

MEM_MB0_ODT013 MEM_MB0_ODT113 MEM_MB1_ODT013 MEM_MB1_ODT113

MEM_MB0_CS_L013 MEM_MB0_CS_L113 MEM_MB1_CS_L013 MEM_MB1_CS_L113

MEM_MB_RAS_L13 MEM_MB_CAS_L13 MEM_MB_WE_L13

MEM_MB_RESET#13 MEM_MB_HOT#13

MEM_MB_BANK0 MEM_MB_BANK1 MEM_MB_BANK2

MEM_MB_DQS_H0 MEM_MB_DQS_L0 MEM_MB_DQS_H1 MEM_MB_DQS_L1 MEM_MB_DQS_H2 MEM_MB_DQS_L2 MEM_MB_DQS_H3 MEM_MB_DQS_L3 MEM_MB_DQS_H4 MEM_MB_DQS_L4 MEM_MB_DQS_H5 MEM_MB_DQS_L5 MEM_MB_DQS_H6 MEM_MB_DQS_L6 MEM_MB_DQS_H7 MEM_MB_DQS_L7

MEM_MB_CLK_H0 MEM_MB_CLK_L0 MEM_MB_CLK_H1 MEM_MB_CLK_L1 MEM_MB_CLK_H2 MEM_MB_CLK_L2 MEM_MB_CLK_H3 MEM_MB_CLK_L3

MEM_MB_CKE0 MEM_MB_CKE1

MEM_MB0_ODT0 MEM_MB0_ODT1 MEM_MB1_ODT0 MEM_MB1_ODT1

MEM_MB0_CS_L0 MEM_MB0_CS_L1 MEM_MB1_CS_L0 MEM_MB1_CS_L1

MEM_MB_RAS_L MEM_MB_CAS_L MEM_MB_WE_L

MEM_MB_RESET# MEM_MB_HOT#

MEM_MB_ADD0 MEM_MB_ADD1 MEM_MB_ADD2 MEM_MB_ADD3 MEM_MB_ADD4 MEM_MB_ADD5 MEM_MB_ADD6 MEM_MB_ADD7 MEM_MB_ADD8 MEM_MB_ADD9 MEM_MB_ADD10 MEM_MB_ADD11 MEM_MB_ADD12 MEM_MB_ADD13 MEM_MB_ADD14 MEM_MB_ADD15

MEM_MB_DM0 MEM_MB_DM1 MEM_MB_DM2 MEM_MB_DM3 MEM_MB_DM4 MEM_MB_DM5 MEM_MB_DM6 MEM_MB_DM7

MEM_MB_DQS_L[7..0]13 MEM_MB_DQS_H[7..0]13

MEM_MB_DM[7..0]13

U100B

AB28

AL29 AH25 AK21 AJ17

AJ29 AH29 AK25 AL25 AJ20 AJ21 AL16 AL17

AA30 AC30 AA31 AC29

AB29 AB31

AA27 AA28

U100B

MEMORY CHANNEL B

MB_ADD0

V31

MB_ADD1

N28

MB_ADD2

P29

MB_ADD3

N29

MB_ADD4

N31

MB_ADD5

M30

MB_ADD6

M31

MB_ADD7

M28

MB_ADD8

M27

MB_ADD9

L30

MB_ADD10

W31

MB_ADD11

L29

MB_ADD12

K28

MB_ADD13 MB_ADD14

K31

MB_ADD15

J31

MB_BANK0

W29

MB_BANK1

V30

MB_BANK2

K29

MB_DM0

B12

MB_DM1

D16

MB_DM2

B20

MB_DM3

A25

MB_DM4 MB_DM5 MB_DM6 MB_DM7 MB_DM8

D29

MB_DQS_H0

D13

MB_DQS_L0

C13

MB_DQS_H1

A17

MB_DQS_L1

B17

MB_DQS_H2

B21

MB_DQS_L2

C21

MB_DQS_H3

D25

MB_DQS_L3

C25

MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7 MB_DQS_H8

B29

MB_DQS_L8

A29

MB_CLK_H0

U30

MB_CLK_L0

U29

MB_CLK_H1

T29

MB_CLK_L1

T28

MB_CLK_H2

R31

MB_CLK_L2

T31

MB_CLK_H3

P30

MB_CLK_L3

R30

MB_CKE0

J30

MB_CKE1

J28

MB0_ODT0 MB0_ODT1 MB1_ODT0 MB1_ODT1

MB0_CS_L0

Y29

MB0_CS_L1 MB1_CS_L0

Y30

MB1_CS_L1

MB_RAS_L

W28

MB_CAS_L MB_WE_L

MB_RESET_L

J27

MB_EVENT_L

V28

MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7

MB_DATA8

MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15

MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23

MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31

MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39

MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47

MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55

MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63

MB_CHECK0 MB_CHECK1 MB_CHECK2 MB_CHECK3 MB_CHECK4 MB_CHECK5 MB_CHECK6 MB_CHECK7

MEM_MB_DATA0

D11

MEM_MB_DATA1

C12

MEM_MB_DATA2

A14

MEM_MB_DATA3

B14

MEM_MB_DATA4

B11

MEM_MB_DATA5

A11

MEM_MB_DATA6

A13

MEM_MB_DATA7

D14

MEM_MB_DATA8

A16

MEM_MB_DATA9

C16

MEM_MB_DATA10

B18

MEM_MB_DATA11

A19

MEM_MB_DATA12

C15

MEM_MB_DATA13

B15

MEM_MB_DATA14

D17

MEM_MB_DATA15

C18

MEM_MB_DATA16

D20

MEM_MB_DATA17

A20

MEM_MB_DATA18

D22

MEM_MB_DATA19

D23

MEM_MB_DATA20

C19

MEM_MB_DATA21

D19

MEM_MB_DATA22

A22

MEM_MB_DATA23

C22

MEM_MB_DATA24

C24

MEM_MB_DATA25

B24

MEM_MB_DATA26

B26

MEM_MB_DATA27

C27

MEM_MB_DATA28

A23

MEM_MB_DATA29

B23

MEM_MB_DATA30

D26

MEM_MB_DATA31

A26

MEM_MB_DATA32

AJ30

MEM_MB_DATA33

AK30

MEM_MB_DATA34

AH28

MEM_MB_DATA35

AJ27

MEM_MB_DATA36

AG30

MEM_MB_DATA37

AH31

MEM_MB_DATA38

AK28

MEM_MB_DATA39

AL28

MEM_MB_DATA40

AJ26

MEM_MB_DATA41

AH26

MEM_MB_DATA42

AH23

MEM_MB_DATA43

AJ23

MEM_MB_DATA44

AK27

MEM_MB_DATA45

AL26

MEM_MB_DATA46

AJ24

MEM_MB_DATA47

AK24

MEM_MB_DATA48

AK22

MEM_MB_DATA49

AH22

MEM_MB_DATA50

AL19

MEM_MB_DATA51

AK19

MEM_MB_DATA52

AL23

MEM_MB_DATA53

AL22

MEM_MB_DATA54

AH20

MEM_MB_DATA55

AL20

MEM_MB_DATA56

AJ18

MEM_MB_DATA57

AH17

MEM_MB_DATA58

AJ15

MEM_MB_DATA59

AK15

MEM_MB_DATA60

AH19

MEM_MB_DATA61

AK18

MEM_MB_DATA62

AK16

MEM_MB_DATA63

AH16 A28

D28 C30 D31 B27 C28 B30 C31

<APU>

MEM_MB_DATA[63..0] 13

VCC_DDR

R196

1KR1%

A A

5

R201

1KR1%

C170

C1000P50X0402

APU_M_VREF

C679

C0.1u10X0402

C156

Layout: Place within 1.0'' of APU

C1000P50X0402

4

VCC_DDR

R275 1KR0402R275 1KR0402 R274 1KR0402R274 1KR0402

3

MEM_MA_HOT# MEM_MB_HOT#

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

C

Date: Sheet

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

FM1 DDR3 I/F

FUSION 1.0

1

935Wednesday, August 17, 2011

of

5

FM1 DISPLAY I/F

Note: Several vias on the DP0 interface violate the minimum distance rules for via to via spacing between diff pairs. These violations have been reviewed and approved on an individual basis, and pose no significant singal integrity issues for this implementation since the route lengths are under the maximum allowed spec, and the via distance violations are not severe.

DP0_TX0P21 DP0_TX0N21

mach@DP0 for HDMI

D D

mach@DP1 for CRT

APU_SIC

C337

X_C10p50N0402

Layout: Place within 1.5'' of APU

APU_RST# APU_PWRGD

C C

C335

C299

C180p50N0402

DP0_TX1P21 DP0_TX1N21

DP0_TX2P21 DP0_TX2N21

DP0_TX3P21 DP0_TX3N21

DP1_TX0P18 DP1_TX0N18

DP1_TX1P18 DP1_TX1N18

DP1_TX2P18 DP1_TX2N18

DP1_TX3P18 DP1_TX3N18

APU_PROCHOT#16

APU_RST#16

APU_PWRGD7,16

APU_CLK16 APU_CLK#16

DISP_CLK16 DISP_CLK#16

APU_SIC25 APU_SID25

C230 C0.1u10X0402C230 C0.1u10X0402 C235 C0.1u10X0402C235 C0.1u10X0402

C226 C0.1u10X0402C226 C0.1u10X0402 C220 C0.1u10X0402C220 C0.1u10X0402

C213 C0.1u10X0402C213 C0.1u10X0402 C209 C0.1u10X0402C209 C0.1u10X0402

C210 C0.1u10X0402C210 C0.1u10X0402 C214 C0.1u10X0402C214 C0.1u10X0402

C255 C0.1u10X0402C255 C0.1u10X0402 C259 C0.1u10X0402C259 C0.1u10X0402

C248 C0.1u10X0402C248 C0.1u10X0402 C252 C0.1u10X0402C252 C0.1u10X0402

C244 C0.1u10X0402C244 C0.1u10X0402 C238 C0.1u10X0402C238 C0.1u10X0402

C240 C0.1u10X0402C240 C0.1u10X0402 C236 C0.1u10X0402C236 C0.1u10X0402

APU_SIC

R316 10R0402R316 10R0402

APU_SID

APU_RST# APU_PWRGD

APU_PROCHOT# APU_THERMTRIP# APU_ALERT#

VCC_DDR VCC3_SB

R304

R305

TP9TP9

NBCOREFB+7

VDDIOFB+27

COREFB+

COREFB+7

TP10TP10

COREFB-7

APU_THERMTRIP#

2

10KR0402

61

Q49A

NN-CMKT3904_SOT363-6-RH

10KR0402

FCH_THERMTRIP# 17

VCC3_SBVCC_DDR

R302

R303

APU_ALERT#

B B

Q49B

NN-CMKT3904_SOT363-6-RH

5

10KR0402

34

FCH_TALERT# 18

PULL UP

VCC_DDR

R307 1KR0402R307 1KR0402 R317 1KR0402R317 1KR0402

R288 300R0402R288 300R0402 R310 300R0402R310 300R0402

R289 300R0402R289 300R0402 R287 1KR0402R287 1KR0402 R290 1KR0402R290 1KR0402

R318 1KR0402R318 1KR0402

VCC5_SB

R301 10KR0402R301 10KR0402

A A

APU_SIC_R APU_SID

APU_RST# APU_PWRGD

APU_PROCHOT# APU_ALERT# APU_THERMTRIP#

FCH_DMA_ACTIVE#

APU_FM1R1

To overide VID:remove R520,R521 Stuff R82 to enter FIX mode

4

ROUTE PCIE AS 85OHM +/-10% PLACE CAPS WITH APU < 1 INCH

Trace length within 10"

ANALOG/DISPLAY/MISC

AL12

AK12 AH12

AG12

AF10 AG10

AJ13

AG11

AL14 AK14 AD10

AF13

ANALOG/DISPLAY/MISC

DP0_TXP0

M2

DP0_TXN0

M3

DP0_TXP1

L2

DP0_TXN1

L1

DP0_TXP2

L4

DP0_TXN2

L5

DP0_TXP3

K2

DP0_TXN3

K3

DP1_TXP0

R4

DP1_TXN0

R5

DP1_TXP1

P2

DP1_TXN1

P3

DP1_TXP2

N2

DP1_TXN2

N1

DP1_TXP3

N4

DP1_TXN3

N5

CLKIN_H CLKIN_L

DISP_CLKIN_H DISP_CLKIN_L

SVC

A8

SVD

B8

SIC SID

RESET_L PWROK

PROCHOT_L THERMTRIP_L ALERT_L

TDI

E9

TDO

G10

TCK

E8

TMS

D8

TRST_L

F10

DBRDY

D7

DBREQ_L

F8

RSVD_1

E11

RSVD_2

H9

RSVD_3

K23

RSVD_4

K25

RSVD_5

VDDP_SENSE

B5

VDDNB_SENSE

A6

VDDIO_SENSE

B6

VDD_SENSE

C7

VDDR_SENSE

A5

VSS_SENSE

C6

DP0_TX0P_APU DP0_TX0N_APU

DP0_TX1P_APU DP0_TX1N_APU

DP0_TX2P_APU DP0_TX2N_APU

DP0_TX3P_APU DP0_TX3N_APU

DP1_TX0P_APU DP1_TX0N_APU

DP1_TX1P_APU DP1_TX1N_APU

DP1_TX2P_APU DP1_TX2N_APU

DP1_TX3P_APU DP1_TX3N_APU

APU_SVC_R APU_SVD_R

APU_SIC_R

CPU_TDI CPU_TDO CPU_TCK CPU_TMS CPU_TRST_L CPU_DBRDY CPU_DBREQ_L

VDDP_SENSE

VDDR_SENSE

VID OVERRIDE CIRCUIT

APU_SVC_R APU_SVD_R APU_PWRGD

SVC SVD 0

0 001 1 11

BOOT Voltage

Pre-PWROK metel VID V_FIX MODE

1.1

1.0

0.9

0.8

1.4

1.2

1.0

0.8

3

U100C

DISPLAY PORT 0

DISPLAY PORT MISC.

DISPLAY PORT 1

CLK

CTRL SER.

TEST

JTAG

SENSE RSVD

TEST2, TEST3, TEST6, TEST10, TEST23, TEST28_H TEST28_L, and any RSVD pins have no connections. TEST4, TEST5, TEST[17:14], TEST25_H/L,TEST30_H/L, and TEST32_H/L have onboard test points.

DP_AUX_ZVSS

J9

APU_BLON

DP_BLON

G9

APU_DIGON

DP_DIGON

G7

APU_BLPWM

DP_VARY_BL

H8

DP0_AUXP

K6

DP0_AUXN

K8

DP1_AUXP

L7

DP1_AUXN

L8

DP2_AUXP

R7

DP2_AUXN

R8

DP3_AUXP

P8

DP3_AUXN

P9

DP4_AUXP

N7

DP4_AUXN

N8

DP5_AUXP

M8

DP5_AUXN

M9

DP0_HPD

K9

DP1_HPD

K5

DP2_HPD

P5

DP3_HPD

P6

DP4_HPD

M5

DP5_HPD

M6

THERMDA

AH14

THERMDC

AG14

TEST2

AB23

TEST3

AC24

TEST6

AG13

TEST9

D10

TEST10

C10

TEST12

F6

TEST14

D9

TEST15

C9

TEST16

B9

TEST17

A9

TEST18

E4

TEST19

F5

TEST20

D4

TEST21

D5

TEST22

E5

TEST23

F7

TEST24

E6

TEST25_H

AE11

TEST25_L

AD11

TEST28_H

G5

TEST28_L

G6

TEST30_H

AD14

TEST30_L

AE14

TEST31

AG31

TEST32_H

AE13

TEST32_L

AD13

TEST35

A7

FM1R1

AC12

DMAACTIVE_L

AF11

<APU>

mach@FM1R1 used to control VRM_EN(D66)??? FM1R1 = OPEN ON PKG. IF LOW, KEEP PWR OFF!

R207 150R1%0402R207 150R1%0402

DP0

DP1

DP2_HPD DP3_HPD DP4_HPD DP5_HPD

APU_TEST4 APU_TEST5 APU_TEST2 APU_TEST3 APU_TEST6 APU_TEST9 APU_TEST10 APU_TEST12 APU_TEST14 APU_TEST15 APU_TEST16 APU_TEST17 APU_TEST18 APU_TEST19 APU_TEST20 APU_TEST21 APU_TEST22 APU_TEST23 APU_TEST24 APU_TEST25_H APU_TEST25_L APU_TEST28_H APU_TEST28_L APU_TEST30_H APU_TEST30_L APU_TEST31 APU_TEST32_H APU_TEST32L APU_TEST35

APU_FM1R1 FCH_DMA_ACTIVE#

Layout: Place within 1.5'' of APU

DP0_AUXP_C 21 DP0_AUXN_C 21

DP1_AUXP_C 18 DP1_AUXN_C 18

DP0_TX0,TX1,TX2 and TX3 DP0_AUX0 and DP0_HPD

DP1_TX0,TX1,TX2 and TX3 DP1_AUX0 and DP1_HPD

R266 100KR0402R266 100KR0402 R267 100KR0402R267 100KR0402 R262 100KR0402R262 100KR0402 R260 100KR0402R260 100KR0402

TP39TP39 TP45TP45 TP40TP40 TP41TP41 TP44TP44

R210 0R0402R210 0R0402

TP33TP33

R192 1KR0402R192 1KR0402

R203 1KR0402R203 1KR0402 R189 1KR0402R189 1KR0402 R191 1KR0402R191 1KR0402 R205 1KR0402R205 1KR0402 R190 1KR0402R190 1KR0402

TP36TP36

R204 1KR0402R204 1KR0402 R319 511R1%0402R319 511R1%0402

R311 511R1%0402R311 511R1%0402 TP38TP38 TP37TP37

R308 X_39.2R1%0402R308 X_39.2R1%0402

R300 X_39.2R1%0402R300 X_39.2R1%0402

R280 39.2R1%0402R280 39.2R1%0402 TP42TP42 TP43TP43

R206 X_300R0402R206 X_300R0402

R193 300R0402R193 300R0402

APU_FM1R1 7

FCH_DMA_ACTIVE# 16

MACH@??? DP2 to PCIE16X conn?

DP0_HPD_HDMI_C 21 DP1_HPD_VGA_C 18

CPU_VDDP

VCC_DDR

Sabine HDMI Design Guidance HDMI enable strapping: TEST35 PU TO VCC_DDR thru 300R

VCC_DDR

R185

R186

1KR0402

R209 0R0402R209 0R0402 R208 0R0402R208 0R0402

R309

R195

X_220R0402

R194

X_220R0402

APU_SVC 7 APU_SVD 7

2

CPU_TRST_L

HDT+ Connector

VCC_DDR

J2

1

CPU_VDDIO

3

GND

5

GND

7

R658 X_0R0402R658 X_0R0402 R659 X_10KR0402R659 X_10KR0402 R660 X_10KR0402R660 X_10KR0402 R661 X_10KR0402R661 X_10KR0402

GND CPU_TRST_L9CPU_PWROK_BUF CPU_DBRDY311CPU_RST_L_BUF CPU_DBRDY213CPU_DBRDY0 CPU_DBRDY115CPU_DBREQ_L

17

GND CPU_VDDIO19CPU_PLLTEST1

X_H2X10SM-1.27PITCH_BLUE-RH

VCC3 VCC3

R9

2

X_10KR0402R9X_10KR0402

APU_PWROK_BUFAPU_PWRGD APU_LDT_RST_BUF

61

Q83A

X_NN-CMKT3904_SOT363-6-RH

VCC_DDRVCC_DDR

Layout: Place close to HDT header

R653 1KR0402R653 1KR0402 R651 1KR0402R651 1KR0402 R652 1KR0402R652 1KR0402 R657 1KR0402R657 1KR0402 R654 300R0402R654 300R0402

SCAN Conn,

APU_TEST18 APU_TEST19 APU_TEST21 APU_TEST22 APU_TEST12 APU_TEST24 APU_TEST20

WARM RESET

APU_RST#

GPU DEBUG

APU_TEST14 APU_TEST15 APU_TEST16 APU_TEST17 APU_BLON APU_DIGON APU_BLPWM DP1_HPD_VGA_C

CPU_TCK

CPU_TMS

CPU_TDI

CPU_TDO

CPU_PLLTEST0

APU_RST#

TP8TP8 TP7TP7 TP32TP32

2 4 6 8

APU_PWROK_BUF

10

APU_LDT_RST_BUF

12 14 16 18 20

5

R83

Q83B

X_0R0402

X_NN-CMKT3904_SOT363-6-RH

CPU_TDI CPU_TCK CPU_TMS CPU_TRST_L CPU_DBREQ_L

TP46TP46 TP64TP64 TP65TP65 TP67TP67 TP68TP68 TP69TP69 TP70TP70

TP71TP71

TP72TP72 TP73TP73 TP74TP74 TP75TP75 TP76TP76 TP77TP77 TP78TP78 TP79TP79

1

CPU_TCK CPU_TMS CPU_TDI CPU_TDO

CPU_DBRDY

CPU_DBREQ_L

APU_TEST19 APU_TEST18

R42

X_10KR0402

34

NBCOREFB+ VDDIOFB+ COREFB+

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

C

Date: Sheet

5

4

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

FM1 DISPLAY/MSIC

FUSION 1.0

1

10 35Wednesday, August 17, 2011

of

5

BOTTOM SIDE DECOUPLING

VCCP

C697,C700,C705,C710 change to ASM-5010

D D

C700

C22u6.3X1206

C697

C22u6.3X1206

C705

C22u6.3X1206

C710

C22u6.3X1206

C682

C47u6.3X1206

C704

VCCP VCCP

C694

C712

VCCP

C715

C C

C715

C702

C689

C47u4X50805-RH

C22u6.3X50805-RH

C47u4X50805-RH

C709

C708

C47u4X50805-RH

C22u6.3X50805-RH

VCCP VCCP

C716

C0.22U16X

C693

C0.01u25X

C711

C0.01u25X

C714

CPU_VDDNB

C789

C796

C47u6.3X1206

C790

C795

C47u6.3X1206

C789

C47u6.3X1206

C794

C47u6.3X1206

C792

C47u6.3X1206

VCC_DDR

B B

C695

CPU_VDDR

C298

A A

VCCP

C260

C180p50N0402

C681

C685

C22u6.3X1206

C314

C4.7u6.3X5

C273

C180p50N0402

C685

C22u6.3X1206

C332

C4.7u6.3X5

C268

X_C180p50N0402

5

C22u6.3X1206

C0.22U16X

C690

C22u6.3X1206

Layout: Place close to Pins AH11,AJ11,AK11,AL11

C324

C22u6.3X1206

C180p50N0402

C223

C10u6.3X50805

C330

C0.22U16X

C216

X_C180p50N0402

C698

C4.7u6.3X5

CPU_VDDP

C263

X_C180p50N0402

C696

C699

C47u6.3X1206

C684

C713

C22u6.3X50805-RH

C680

C0.01u25X

C797

C816

C47u6.3X1206

C272

C706

C703

C4.7u6.3X5

Layout: Place close to Pins AH10,AJ10,AK10,AL10

C296

C310

C10u6.3X50805

C323

C10u6.3X50805

C687

C47u4X50805-RH

C718

C180p50N0402

C814

C47u6.3X1206

C4.7u6.3X5

C47u6.3X1206

C707

C47u4X50805-RH

C719

C791

C270

C0.22U16X

C329

C0.22U16X

C692

C47u6.3X1206

C701

C688

C180p50N0402

C815

C47u6.3X1206

C221

C0.22U16X

C326

C1000P50X0402

C683

C47u6.3X1206

C22u6.3X50805-RH

C180p50N0402

C47u6.3X1206

EMC Caps On Bottom side

C162

C202

X_C180p50N0402

C191

X_C180p50N0402

C166

X_C180p50N0402

C798

C47u6.3X1206

C784

C180p50N0402

C331

C1000P50X0402

C211

X_C180p50N0402

4

VCCP VCCP

C785

C180p50N0402

C154

C150

X_C180p50N0402

4

U100D

VDD

M12

VDD

P12

VDD

H10

VDD

H6

VDD

U19

VDD

J11

VDD

J13

VDD

J15

VDD

J17

VDD

J19

VDD

J21

VDD

J5

VDD

K10

VDD

K12

VDD

K14

VDD

K16

VDD

K18

VDD

K20

VDD

K4

VDD

L11

VDD

W19

VDD

L15

VDD

L17

VDD

N19

VDD

L21

VDD

L3

VDD

L6

VDD

M1

VDD

M10

VDD

W13

VDD

M16

VDD

M18

VDD

M20

VDD

U21

VDD

M4

VDD

M7

VDD

N11

VDD

N21

VDD

P1

VDD

P10

VDD

P20

VDD

R11

VDD

R21

VDD

R3

VDD

R6

VDD

T1

VDD

T10

VDD

T12

VDD

T20

VDD

T4

VDD

T7

U100E

VDDIO

J26

VDDIO

J29

VDDIO

K24

VDDIO

K27

VDDIO

K30

VDDIO

L25

VDDIO

L28

VDDIO

L31

VDDIO

M23

VDDIO

M26

VDDIO

M29

VDDIO

N24

VDDIO

N27

VDDIO

N30

VDDIO

P22

VDDIO

P25

VDDIO

P28

VDDIO

P31

VDDIO

R23

VDDIO

R26

VDDIO

R29

VDDIO

T22

VDDIO

T24

VDDIO

T27

VDDIO

T30

VDDIO

U25

VDDIO

U28

VDDIO

U31

VDDIO

V22

VDDIO

V23

VDDIO

V26

VDDIO

V29

VDDIO

W24

VDDIO

W27

VDDIO

W30

VDDIO

Y22

VDDIO

Y25

VDDIO

Y28

VDDIO

Y31

VDDIO

AA23

VDDIO

AA26

VDDIO

AA29

VDDIO

AB22

VDDIO

AB24

VDDIO

AB27

VDDIO

AB30

VDDIO

AC23

VDDIO

AC25

VDDIO

AC28

VDDIO

AC31

VDDIO

M22

C197

X_C180p50N0402

C149

X_C180p50N0402

POWER

3

VDD

U11

VDD

U13

VDD

V1

VDD

V10

VDD

V12

VDD

V20

VDD

W11

VDD

W21

VDD

W3

VDD

W6

VDD

Y1

VDD

Y10

VDD

Y12

VDD

Y14

VDD

Y16

VDD

Y18

VDD

Y20

VDD

Y4

VDD

Y7

VDD

AA11

VDD

AA13

VDD

AA15

VDD

AA17

VDD

AA19

VDD

AA21

VDD

AB1

VDD

AB10

VDD

R13

VDD

AB14

VDD

AB16

VDD

AB18

VDD

R19

VDD

AC11

VDD

AC13

VDD

AC15

VDD

AC17

VDD

AC19

VDD

AC21

VDD

AC3

VDD

AC6

VDD

AD1

VDD

AD4

VDD

AD7

VDD

AF1

VDD

AG3

VDD

AG6

VDD

AH1

VDD

AH4

VDD

AH7

VDD

AK4

VDD

AK7

<APU>

TOTLE POWER PINS

416 2

VALUE/SIZE/ MATERIAL

22U/1206/X5R 10U/0805/X5R

4.7U/0805/X5R

0.22U/0603/X5R

0.1U/0603/X5R

0.01U/0603/X5R

3.3 nF/0603/X5R 1 nF/0603/X5R 1 nF/0603/X5R 180 pF/0603/X5R

VDDA25VCC_DDR

VDDA

C277

VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB

VDDNB VDDNB_CAP_1 VDDNB_CAP_2

VDDP_A_1 VDDP_A_2 VDDP_A_3 VDDP_A_4

VDDP_B_1 VDDP_B_2 VDDP_B_3 VDDP_B_4

<APU>

AD12

VDDA

AE12 A3

A4 B3 B4 C1 C2 C3 C4 C5 D1 D2 D3 E1 E2 E3 F1 F2 F3 F4 M14 N13

AH10 AJ10 AK10 AL10

VDDR

AH11

VDDR

AJ11

VDDR

AK11

VDDR

AL11 J1

J2 J3 J4

VDDR

H1

VDDR

H2

VDDR

H3

VDDR

H4

CPU_VDDNB

C180p50N0402

C181

TP18TP18

CPU_VDDNB

VDDNB = 0.8V (Variable)

Layout: Place close to Pins M14,M13 inside the backplate cavity openning

VDDNB_CAP

C686 C22u6.3X1206C686 C22u6.3X1206 C691 C22u6.3X1206C691 C22u6.3X1206

CPU_VDDP

CPU_VDDR

VCC_VDDP_B

CPU_VDDR_B

VDDR = 1.2V VDDPCIE = 1.2V ONLY ONE SIDE OF VDDPCIE & VDDR MUST CONNECTED ON THE PCB.CONNECTING BOTH SIDES IS ACCEPTABLE BUT NOT REQUIRED. BOTH SIDES MUST BE DECOUPLED.

VCC_VDDP_B CPU_VDDR_B

C204

C180p50N0402

3

FM1 DECOUPLING CAPS

VSS

VDD

VDDNB

VDDIO

19

102

226

11

/

7

/

3

/

2

/

/ /

4

/

/ /

31

Place across each VDDIO-GND plane seam

VCC_DDR

C357

C0.22U16X

Layout: Place caps within 0.6'' of APU

Layout: Place close to Pins H1,H2,H3,H4

C189

CPU_VDDP CPU_VDDR

C281

C203

C180p50N0402

51

2

4 1

2 1

4

2

2+2

/

/ 2+2

C371

C758

C0.22U16X

C180p50N0402

C306

C312

C0.22U16X

C4.7u6.3X5

Layout: Place close to Pins J1,J2,J3,J4

C200

C198

C4.7u6.3X5

C10u6.3X50805

C185

C186

C4.7u6.3X5

C10u6.3X50805

C308

C194

C180p50N0402

VDDP

COMB

8

/

2+1(B)

2 2 / / / // 4 2+2

C757

C180p50N0402

FB5

30L3A-40_0805-RH

C717

C3300p50X0402

VCC_VDDP_B

C196

C199

C0.22U16X

C1000P50X0402

CPU_VDDR_B

C187

C4.7u6.3X5

C0.22U16X

VDDP and VDDR support two separate power planes with single regulator

2

4

NEAR

//1

2 2 / / / / / /

SPLIT

4

FAR

/ / 2 2 / / / / / /

VDDA

Mvref

1

/

/ /

1

/

1 /

/

1

1 / /

/

VDDR

COMB

SPLIT

8

1 2+2 2+2 / /

/ // 2

CPU_VDDNB

C169

C180

C169

C164

C0.22U16X

C180p50N0402

VDDA_25VDDA25

C195

C1000P50X0402

C188

C0.22U16X

C321

C180p50N0402

2

1

U100F

VSS

VSS_1

A10

VSS_2

A12

VSS_3

A15

VSS_4

A18

VSS_5

A21

VSS_6

A24

VSS_7

A27

VSS_8

AL9

VSS_9

B10

VSS_10

B13

VSS_11

B16

VSS_12

B19

VSS_13

B22

VSS_14

B25

VSS_15

B28

VSS_16

B7

VSS_17

C11

VSS_18

C14

VSS_19

C17

VSS_20

C20

VSS_21

C23

VSS_22

C26

VSS_23

C29

VSS_24

C8

VSS_25

D12

VSS_26

D15

VSS_27

D18

VSS_28

D21

VSS_29

D24

VSS_30

D27

VSS_31

D30

VSS_32

D6

VSS_33

E10

VSS_34

E13

VSS_35

E16

VSS_36

E19

VSS_37

E22

VSS_38

E25

VSS_39

E28

VSS_40

E31

VSS_41

E7

VSS_42

F11

VSS_43

F14

VSS_44

F17

VSS_45

F20

VSS_46

F23

VSS_47

F26

VSS_48

F29

VSS_49

F9

VSS_50

G1

VSS_51

G12

VSS_52

G15

VSS_53

G18

VSS_54

G2

VSS_55

G21

VSS_56

G24

VSS_57

G27

VSS_58

G3

U100G

VSS

T11

VSS

T21

VSS

U10

VSS

U12

VSS

U20

VSS

U22

VSS

U3

VSS

U6

VSS

U9

VSS

V11

VSS

V21

VSS

V4

VSS

V7

VSS

W10

VSS

W12

VSS

W20

VSS

W22

VSS

W9

VSS

Y11

VSS

Y13

VSS

Y15

VSS

Y17

VSS

Y19

VSS

Y21

VSS

AA10

VSS

AA14

VSS

AA16

VSS

AA18

VSS

AA22

VSS

AA3

VSS

AA6

VSS

AA9

VSS

AB11

VSS

AB13

VSS

AB15

VSS

AB17

VSS

AB19

VSS

AB21

VSS

AB4

VSS

AB7

VSS

AC10

VSS

AC14

VSS

AC16

VSS

AC18

VSS

AC20

VSS

AC22

VSS

AC9

VSS

AD17

VSS

AD20

VSS

AD23

VSS

AD26

VSS

AD29

VSS

AE10

VSS

AE15

VSS

AE18

VSS

AE21

VSS

AE24

VSS

AE27

Title

FM1 POWER&DECOUPLING

Size Document Number Rev

C

Date: Sheet

VSS_59

G30

VSS_60

G4

VSS_61

G8

VSS_62

H13

VSS_63

H16

VSS_64

H19

VSS_65

H22

VSS_66

H25

VSS_67

H28

VSS_68

H31

VSS_69

H5

VSS_70

H7

VSS_71

J10

VSS_72

J12

VSS_73

J14

VSS_74

J16

VSS_75

J18

VSS_76

J20

VSS_77

J22

VSS_78

J23

VSS_79

J8

VSS_80

K1

VSS_81

K11

VSS_82

V13

VSS_83

K15

VSS_84

K17

VSS_85

V19

VSS_86

K21

VSS_87

K7

VSS_88

L10

VSS_89

L12

VSS_90

L14

VSS_91

L16

VSS_92

L18

VSS_93

L20

VSS_94

L22

VSS_95

L9

VSS_96

M11

VSS_97

M13

VSS_98

M15

VSS_99

M17

VSS_100

M21

VSS_101

N10

VSS_102

N12

VSS_103

N20

VSS_104

N22

VSS_105

N3

VSS_106

N6

VSS_107

N9

VSS_108

P11

VSS_109

P21

VSS_110

P4

VSS_111

P7

VSS_112

R10

VSS_113

R12

VSS_114

R20

VSS_115

R22

VSS_116

R9

<APU>

VSS

AE3

VSS

AE30

VSS

AE6

VSS

AE9

VSS

AF12

VSS

AF14

VSS

AF16

VSS

AF19

VSS

AF22

VSS

AF25

VSS

AF28

VSS

AF31

VSS

AF4

VSS

AF7

VSS

AG17

VSS

AG20

VSS

AG23

VSS

AG26

VSS

AG29

VSS

AG9

VSS

AH13

VSS

AH15

VSS

AH18

VSS

AH21

VSS

AH24

VSS

AH27

VSS

AH30

VSS

AJ12

VSS

AJ14

VSS

AJ16

VSS

AJ19

VSS

AJ22

VSS

AJ25

VSS

AJ28

VSS

AJ3

VSS

AJ31

VSS

AJ6

VSS

AJ9

VSS

AK13

VSS

AK17

VSS

AK20

VSS

AK23

VSS

AK26

VSS

AK29

VSS

AL13

VSS

AL15

VSS

AL18

VSS

AL21

VSS

AL24

VSS

AL27

VSS

AL3

VSS

AL6

VSS

M19

VSS

P13

VSS

P19

VSS

T13

VSS

T19

<APU>

MICRO-START INT'L CO.,LTD.

FUSION 1.0

1

11 35Wednesday, August 17, 2011

of

5

VCC_DDR VCC3

MEM_MA_DQS_H[7..0]9 MEM_MA_DQS_L[7..0]9

MEM_MA_DATA[63..0]9

D D

C C

B B

MEM_MA_DATA0 MEM_MA_DATA1 MEM_MA_DATA2 MEM_MA_DATA3 MEM_MA_DATA4 MEM_MA_DATA5 MEM_MA_DATA6 MEM_MA_DATA7 MEM_MA_DATA8 MEM_MA_DATA9 MEM_MA_DATA10 MEM_MA_DATA11 MEM_MA_DATA12 MEM_MA_DATA13 MEM_MA_DATA14 MEM_MA_DATA15 MEM_MA_DATA16 MEM_MA_DATA17 MEM_MA_DATA18 MEM_MA_DATA19 MEM_MA_DATA20 MEM_MA_DATA21 MEM_MA_DATA22 MEM_MA_DATA23 MEM_MA_DATA24 MEM_MA_DATA25 MEM_MA_DATA26 MEM_MA_DATA27 MEM_MA_DATA28 MEM_MA_DATA29 MEM_MA_DATA30 MEM_MA_DATA31 MEM_MA_DATA32 MEM_MA_DATA33 MEM_MA_DATA34 MEM_MA_DATA35 MEM_MA_DATA36 MEM_MA_DATA37 MEM_MA_DATA38 MEM_MA_DATA39 MEM_MA_DATA40 MEM_MA_DATA41 MEM_MA_DATA42 MEM_MA_DATA43 MEM_MA_DATA44 MEM_MA_DATA45 MEM_MA_DATA46 MEM_MA_DATA47 MEM_MA_DATA48 MEM_MA_DATA49 MEM_MA_DATA50 MEM_MA_DATA51 MEM_MA_DATA52 MEM_MA_DATA53 MEM_MA_DATA54 MEM_MA_DATA55 MEM_MA_DATA56 MEM_MA_DATA57 MEM_MA_DATA58 MEM_MA_DATA59 MEM_MA_DATA60 MEM_MA_DATA61 MEM_MA_DATA62 MEM_MA_DATA63

122 123 128 129

131 132 137 138

140 141 146 147

149 150 155 156

200 201 206 207

209 210 215 216

100 105 106 218 219 224 225 108 109 114 115 227 228 233 234

101 104

3 4 9

10

12 13 18 19

21 22 27 28

30 31 36 37

81 82 87 88

90 91 96 97

99

2 5

8 11 14 17 20 23 26 29 32 35 38 41 44 47 80 83 86 89 92 95 98

DIMM1

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

54

VDD51VDD

VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD

VSS

107

110

113

116

119

121

170

173

176

179

182

VDD

DDR3

VSS

124

127

VSS

130

133

136

139

142

145

148

151

154

DIMM1(CHANNEL-A A0) SM ADDRESS=A0

VTT_DDR

120

183

VDD

VSS

157

240

186

189

191

194

197

236

VTT

VDD

VSS

160

VTT

VDD

VDDSPD

VSS

163

166

199

202

205

208

211

214

217

4

MEM_MA_HOT#

79

48

187

198

68

53

167

RSVD

FREE1

FREE249FREE3

NC/TEST4

NC/PAR_IN

NC/ERR_OUT

DM0/DQS9

NC/DQS9# DM1/DQS10 NC/DQS10# DM2/DQS11 NC/DQS11# DM3/DQS12 NC/DQS12# DM4/DQS13 NC/DQS13# DM5/DQS14 NC/DQS14# DM6/DQS15 NC/DQS15# DM7/DQS16 NC/DQS16# DM8/DQS17 NC/DQS17#

CK1#(NU)

VSS

220

223

226

229

232

235

239

A0 A1

FREE4

A2 A3 A4 A5 A6 A7 A8 A9

A10/AP

A11 A12 A13 A14 A15

CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7

DQS0

DQS0#

DQS1

DQS1#

DQS2

DQS2#

DQS3

DQS3#

DQS4

DQS4#

DQS5

DQS5#

DQS6

DQS6#

DQS7

DQS7#

DQS8

DQS8#

ODT0 ODT1 CKE0 CKE1 CS0# CS1#

BA0 BA1 BA2

WE# RAS# CAS#

RESET#

CK0

CK0#

CK1(NU)

VREFDQ VREFCA

SCL SDA SA1 SA0

MEC1

MEC2

MEC3

DDRIII-240P_Blue-RH

MEC1

MEC2

MEC3

188 181 61 180 59 58 178 56 177 175 70 55 174 196 172 171

39 40 45 46 158 159 164 165

7 6 16 15 25 24 34 33 85 84 94 93 103 102 112 111 43 42

125 126 134 135 143 144 152 153 203 204 212 213 221 222 230 231 161 162

195 77 50 169 193 76 71 190 52

73 192 74 168

184 185 63 64

1 67 118 238 237 117

MEM_MA_ADD0 MEM_MA_ADD1 MEM_MA_ADD2 MEM_MA_ADD3 MEM_MA_ADD4 MEM_MA_ADD5 MEM_MA_ADD6 MEM_MA_ADD7 MEM_MA_ADD8 MEM_MA_ADD9 MEM_MA_ADD10 MEM_MA_ADD11 MEM_MA_ADD12 MEM_MA_ADD13 MEM_MA_ADD14 MEM_MA_ADD15

MEM_MA_DQS_H0 MEM_MA_DQS_L0 MEM_MA_DQS_H1 MEM_MA_DQS_L1 MEM_MA_DQS_H2 MEM_MA_DQS_L2 MEM_MA_DQS_H3 MEM_MA_DQS_L3 MEM_MA_DQS_H4 MEM_MA_DQS_L4 MEM_MA_DQS_H5 MEM_MA_DQS_L5 MEM_MA_DQS_H6 MEM_MA_DQS_L6 MEM_MA_DQS_H7 MEM_MA_DQS_L7

MEM_MA_DM0 MEM_MA_DM1 MEM_MA_DM2 MEM_MA_DM3 MEM_MA_DM4 MEM_MA_DM5 MEM_MA_DM6 MEM_MA_DM7

MEM_MA0_ODT0 MEM_MA0_ODT1 MEM_MA_CKE0 MEM_MA_CKE1 MEM_MA0_CS_L0 MEM_MA0_CS_L1 MEM_MA_BANK0 MEM_MA_BANK1 MEM_MA_BANK2

MEM_MA_WE_L MEM_MA_RAS_L MEM_MA_CAS_L MEM_MA_RESET#

MEM_MA_CLK_H1 MEM_MA_CLK_L1 MEM_MA_CLK_H2 MEM_MA_CLK_L2

MEM_VREF_DQ_A MEM_VREF_CA MEM_SCLK MEM_SDATA

MEM_MA_HOT# 9

MEM_MA_ADD[15..0] 9

MEM_MA_DM[7..0] 9

MEM_MA0_ODT0 9 MEM_MA0_ODT1 9 MEM_MA_CKE0 9 MEM_MA_CKE1 9 MEM_MA0_CS_L0 9 MEM_MA0_CS_L1 9 MEM_MA_BANK0 9 MEM_MA_BANK1 9 MEM_MA_BANK2 9

MEM_MA_WE_L 9 MEM_MA_RAS_L 9 MEM_MA_CAS_L 9 MEM_MA_RESET# 9

MEM_MA_CLK_H1 9 MEM_MA_CLK_L1 9 MEM_MA_CLK_H2 9 MEM_MA_CLK_L2 9

MEM_VREF_CA

C97

C97 C0.1U25X

C0.1U25X

3

VCC_DDR VCC3

54

DIMM2

MEM_MA_DATA0 MEM_MA_DATA1 MEM_MA_DATA2 MEM_MA_DATA3 MEM_MA_DATA4 MEM_MA_DATA5 MEM_MA_DATA6 MEM_MA_DATA7 MEM_MA_DATA8 MEM_MA_DATA9 MEM_MA_DATA10 MEM_MA_DATA11 MEM_MA_DATA12 MEM_MA_DATA13 MEM_MA_DATA14 MEM_MA_DATA15 MEM_MA_DATA16 MEM_MA_DATA17 MEM_MA_DATA18 MEM_MA_DATA19 MEM_MA_DATA20 MEM_MA_DATA21 MEM_MA_DATA22 MEM_MA_DATA23 MEM_MA_DATA24 MEM_MA_DATA25 MEM_MA_DATA26 MEM_MA_DATA27 MEM_MA_DATA28 MEM_MA_DATA29 MEM_MA_DATA30 MEM_MA_DATA31 MEM_MA_DATA32 MEM_MA_DATA33 MEM_MA_DATA34 MEM_MA_DATA35 MEM_MA_DATA36 MEM_MA_DATA37 MEM_MA_DATA38 MEM_MA_DATA39 MEM_MA_DATA40 MEM_MA_DATA41 MEM_MA_DATA42 MEM_MA_DATA43 MEM_MA_DATA44 MEM_MA_DATA45 MEM_MA_DATA46 MEM_MA_DATA47 MEM_MA_DATA48 MEM_MA_DATA49 MEM_MA_DATA50 MEM_MA_DATA51 MEM_MA_DATA52 MEM_MA_DATA53 MEM_MA_DATA54 MEM_MA_DATA55 MEM_MA_DATA56 MEM_MA_DATA57 MEM_MA_DATA58 MEM_MA_DATA59 MEM_MA_DATA60 MEM_MA_DATA61 MEM_MA_DATA62 MEM_MA_DATA63

MEM_VREF_DQ_A MEM_VREF_DQ_A

C101

C1000P50X0402

C101

C1000P50X0402

DIMM2

3

DQ0

VDD51VDD

4

DQ1

9

DQ2

10

DQ3

122

DQ4

123

DQ5

128

DQ6

129

DQ7

12

DQ8

13

DQ9

18

DQ10

19

DQ11

131

DQ12

132

DQ13

137

DQ14

138

DQ15

21

DQ16

22

DQ17

27

DQ18

28

DQ19

140

DQ20

141

DQ21

146

DQ22

147

DQ23

30

DQ24

31

DQ25

36

DQ26

37

DQ27

149

DQ28

150

DQ29

155

DQ30

156

DQ31

81

DQ32

82

DQ33

87

DQ34

88

DQ35

200

DQ36

201

DQ37

206

DQ38

207

DQ39

90

DQ40

91

DQ41

96

DQ42

97

DQ43

209

DQ44

210

DQ45

215

DQ46

216

DQ47

99

DQ48

100

DQ49

105

DQ50

106

DQ51

218

DQ52

219

DQ53

224

DQ54

225

DQ55

108

DQ56

109

DQ57

114

DQ58

115

DQ59

227

DQ60

228

DQ61

233

DQ62

234

DQ63

2

VSS

5

VSS

8

VSS

11

VSS

14

VSS

17

VSS

20

VSS

23

VSS

26

VSS

29

VSS

32

VSS

35

VSS

38

VSS

41

VSS

44

VSS

47

VSS

80

VSS

83

VSS

86

VSS

89

VSS

92

VSS

95

VSS

98

VSS

101

VSS

104

VSS

107

110

113

116

170

VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD

VSS

119

121

124

127

130

133

136

139

142

DIMM2(CHANNEL-A A1) SM ADDRESS=A4

173

176

179

182

183

VDD

DDR3

VSS

145

148

151

154

157

2

VTT_DDR

120

186

160

240

189

191

194

197

VDD

VSS

163

166

199

202

205

236

VDDSPD

VSS

208

211

79

68

53

167

VTT

RSVD

NC/TEST4

NC/PAR_IN

NC/ERR_OUT

VSS

214

217

220

223

226

229

232

48

187

FREE1

FREE249FREE3

A10/AP

DM0/DQS9

NC/DQS9# DM1/DQS10 NC/DQS10# DM2/DQS11 NC/DQS11# DM3/DQS12 NC/DQS12# DM4/DQS13 NC/DQS13# DM5/DQS14 NC/DQS14# DM6/DQS15 NC/DQS15# DM7/DQS16 NC/DQS16# DM8/DQS17 NC/DQS17#

RESET#

CK1(NU)

CK1#(NU)

VREFDQ VREFCA

VSS

MEC1

235

239

MEC1

198

188

A0

181

A1

FREE4

61

A2

180

A3

59

A4

58

A5

178

A6

56

A7

177

A8

175

A9

70 55

A11

174

A12

196

A13

172

A14

171

A15

39

CB0

40

CB1

45

CB2

46

CB3

158

CB4

159

CB5

164

CB6

165

CB7

7

DQS0

6

DQS0#

16

DQS1

15

DQS1#

25

DQS2

24

DQS2#

34

DQS3

33

DQS3#

85

DQS4

84

DQS4#

94

DQS5

93

DQS5#

103

DQS6

102

DQS6#

112

DQS7

111

DQS7#

43

DQS8

42

DQS8#

125 126 134 135 143 144 152 153 203 204 212 213 221 222 230 231 161 162

195

ODT0

77

ODT1

50

CKE0

169

CKE1

193

CS0#

76

CS1#

71

BA0

190

BA1

52

BA2

73

WE#

192

RAS#

74

CAS#

168 184

CK0

185

CK0#

63 64

1 67 118

SCL

238

SDA

237

SA1

117

SA0

MEC2

MEC3

DDRIII-240P_Green-RH

MEC2

MEC3

MEM_MA_HOT#

MEM_MA_ADD0 MEM_MA_ADD1 MEM_MA_ADD2 MEM_MA_ADD3 MEM_MA_ADD4 MEM_MA_ADD5 MEM_MA_ADD6 MEM_MA_ADD7 MEM_MA_ADD8 MEM_MA_ADD9 MEM_MA_ADD10 MEM_MA_ADD11 MEM_MA_ADD12 MEM_MA_ADD13 MEM_MA_ADD14 MEM_MA_ADD15

MEM_MA_DQS_H0 MEM_MA_DQS_L0 MEM_MA_DQS_H1 MEM_MA_DQS_L1 MEM_MA_DQS_H2 MEM_MA_DQS_L2 MEM_MA_DQS_H3 MEM_MA_DQS_L3 MEM_MA_DQS_H4 MEM_MA_DQS_L4 MEM_MA_DQS_H5 MEM_MA_DQS_L5 MEM_MA_DQS_H6 MEM_MA_DQS_L6 MEM_MA_DQS_H7 MEM_MA_DQS_L7

MEM_MA_DM0 MEM_MA_DM1 MEM_MA_DM2 MEM_MA_DM3 MEM_MA_DM4 MEM_MA_DM5 MEM_MA_DM6 MEM_MA_DM7

MEM_MA1_ODT0 MEM_MA1_ODT1 MEM_MA_CKE0 MEM_MA_CKE1 MEM_MA1_CS_L0 MEM_MA1_CS_L1 MEM_MA_BANK0 MEM_MA_BANK1 MEM_MA_BANK2

MEM_MA_WE_L MEM_MA_RAS_L MEM_MA_CAS_L MEM_MA_RESET#

MEM_MA_CLK_H0 MEM_MA_CLK_L0 MEM_MA_CLK_H3 MEM_MA_CLK_L3

MEM_VREF_DQ_A MEM_VREF_CA MEM_SCLK MEM_SDATA

VCC3

MEM_MA1_ODT0 9 MEM_MA1_ODT1 9 MEM_MA_CKE0 9 MEM_MA_CKE1 9 MEM_MA1_CS_L0 9 MEM_MA1_CS_L1 9 MEM_MA_BANK0 9 MEM_MA_BANK1 9 MEM_MA_BANK2 9

MEM_MA_WE_L 9 MEM_MA_RAS_L 9 MEM_MA_CAS_L 9

MEM_MA_CLK_H0 9 MEM_MA_CLK_L0 9 MEM_MA_CLK_H3 9 MEM_MA_CLK_L3 9

MEM_VREF_CA

1

C79

C1000P50X0402

C79

C1000P50X0402

C80

C80 C0.1U25Y

C0.1U25Y

MEM_SCLK13 MEM_SDATA13

A A

Vref-DQ : Reference voltage for DQ0–DQ63, CB0–CB7 and PAR_IN. When in single ended mode used for DQS0–DQS7. Vref-CA : Reference voltage for A0-A15, BA0–BA2, RAS#, CAS#, WE#, S0#, S01#, CKE0, CKE1, ODT0 and ODT1.

RESET#(Output) : A synchronously forces all registered output LOW when RESET# is LOW. This signal can be used during power up to ensure that CKE is LOW and DQs are High-Z.

5

4

MEM_SCLK MEM_SDATA

R352R352 R349R349

SCLK0 14,17,25 SDATA0 14,17,25

3

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

DDR CH-A

FUSION 1.0

1

12 35Tuesday, May 03, 2011

of

5

4

3

2

1

VCC_DDR VCC3

MEM_MB_DQS_H[7..0]9 MEM_MB_DQS_L[7..0]9

MEM_MB_DATA[63..0]9 MEM_MB_ADD[15..0] 9

D D

C C

B B

MEM_MB_DATA0 MEM_MB_DATA1 MEM_MB_DATA2 MEM_MB_DATA3 MEM_MB_DATA4 MEM_MB_DATA5 MEM_MB_DATA6 MEM_MB_DATA7 MEM_MB_DATA8 MEM_MB_DATA9 MEM_MB_DATA10 MEM_MB_DATA11 MEM_MB_DATA12 MEM_MB_DATA13 MEM_MB_DATA14 MEM_MB_DATA15 MEM_MB_DATA16 MEM_MB_DATA17 MEM_MB_DATA18 MEM_MB_DATA19 MEM_MB_DATA20 MEM_MB_DATA21 MEM_MB_DATA22 MEM_MB_DATA23 MEM_MB_DATA24 MEM_MB_DATA25 MEM_MB_DATA26 MEM_MB_DATA27 MEM_MB_DATA28 MEM_MB_DATA29 MEM_MB_DATA30 MEM_MB_DATA31 MEM_MB_DATA32 MEM_MB_DATA33 MEM_MB_DATA34 MEM_MB_DATA35 MEM_MB_DATA36 MEM_MB_DATA37 MEM_MB_DATA38 MEM_MB_DATA39 MEM_MB_DATA40 MEM_MB_DATA41 MEM_MB_DATA42 MEM_MB_DATA43 MEM_MB_DATA44 MEM_MB_DATA45 MEM_MB_DATA46 MEM_MB_DATA47 MEM_MB_DATA48 MEM_MB_DATA49 MEM_MB_DATA50 MEM_MB_DATA51 MEM_MB_DATA52 MEM_MB_DATA53 MEM_MB_DATA54 MEM_MB_DATA55 MEM_MB_DATA56 MEM_MB_DATA57 MEM_MB_DATA58 MEM_MB_DATA59 MEM_MB_DATA60 MEM_MB_DATA61 MEM_MB_DATA62 MEM_MB_DATA63

122 123 128 129

131 132 137 138

140 141 146 147

149 150 155 156

200 201 206 207

209 210 215 216

100 105 106 218 219 224 225 108 109 114 115 227 228 233 234

101 104

3 4 9

10

12 13 18 19

21 22 27 28

30 31 36 37

81 82 87 88

90 91 96 97

99

2 5

8 11 14 17 20 23 26 29 32 35 38 41 44 47 80 83 86 89 92 95 98

DIMM3

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

54

VDD51VDD

VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD

VSS

107

110

113

116

119

121

170

VSS

124

127

130

133

136

139

142

DIMM3(CHANNEL-B B0) SM ADDRESS=A2

173

176

179

182

VDD

DDR3

VSS

145

148

151

154

VTT_DDR

120

183

186

VDD

VSS

157

160

240

189

191

194

197

VDD

VSS

163

166

199

202

205

VSS

236

VDDSPD

VSS

208

79

48

68

53

167

VTT

RSVD

FREE1

FREE249FREE3

NC/TEST4

NC/PAR_IN

NC/ERR_OUT

DM0/DQS9

NC/DQS9# DM1/DQS10 NC/DQS10# DM2/DQS11 NC/DQS11# DM3/DQS12 NC/DQS12# DM4/DQS13 NC/DQS13# DM5/DQS14 NC/DQS14# DM6/DQS15 NC/DQS15# DM7/DQS16 NC/DQS16# DM8/DQS17 NC/DQS17#

CK1#(NU)

VSS

211

VSS

214

217

220

223

226

229

232

235

239

187

198

A0 A1

FREE4

A2 A3 A4 A5 A6 A7 A8 A9

A10/AP

A11 A12 A13 A14 A15

CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7

DQS0

DQS0#

DQS1

DQS1#

DQS2

DQS2#

DQS3

DQS3#

DQS4

DQS4#

DQS5

DQS5#

DQS6

DQS6#

DQS7

DQS7#

DQS8

DQS8#

ODT0 ODT1 CKE0 CKE1

CS0# CS1#

BA0 BA1 BA2

WE# RAS# CAS#

RESET#

CK0

CK0#

CK1(NU)

VREFDQ VREFCA

SCL

SDA

SA1 SA0

MEC1

MEC2

MEC3

DDRIII-240P_Blue-RH

MEC1

MEC2

MEC3

188 181 61 180 59 58 178 56 177 175 70 55 174 196 172 171

39 40 45 46 158 159 164 165

7 6 16 15 25 24 34 33 85 84 94 93 103 102 112 111 43 42

125 126 134 135 143 144 152 153 203 204 212 213 221 222 230 231 161 162

195 77 50 169 193 76 71 190 52

73 192 74 168

184 185 63 64

1 67 118 238 237 117

MEM_MB_HOT#

MEM_MB_ADD0 MEM_MB_ADD1 MEM_MB_ADD2 MEM_MB_ADD3 MEM_MB_ADD4 MEM_MB_ADD5 MEM_MB_ADD6 MEM_MB_ADD7 MEM_MB_ADD8 MEM_MB_ADD9 MEM_MB_ADD10 MEM_MB_ADD11 MEM_MB_ADD12 MEM_MB_ADD13 MEM_MB_ADD14 MEM_MB_ADD15

MEM_MB_DQS_H0 MEM_MB_DQS_L0 MEM_MB_DQS_H1 MEM_MB_DQS_L1 MEM_MB_DQS_H2 MEM_MB_DQS_L2 MEM_MB_DQS_H3 MEM_MB_DQS_L3 MEM_MB_DQS_H4 MEM_MB_DQS_L4 MEM_MB_DQS_H5 MEM_MB_DQS_L5 MEM_MB_DQS_H6 MEM_MB_DQS_L6 MEM_MB_DQS_H7 MEM_MB_DQS_L7

MEM_MB_DM0 MEM_MB_DM1 MEM_MB_DM2 MEM_MB_DM3 MEM_MB_DM4 MEM_MB_DM5 MEM_MB_DM6 MEM_MB_DM7

MEM_MB0_ODT0 MEM_MB0_ODT1 MEM_MB_CKE0 MEM_MB_CKE1 MEM_MB0_CS_L0 MEM_MB0_CS_L1 MEM_MB_BANK0 MEM_MB_BANK1 MEM_MB_BANK2

MEM_MB_WE_L MEM_MB_RAS_L MEM_MB_CAS_L MEM_MB_RESET#

MEM_MB_CLK_H1 MEM_MB_CLK_L1 MEM_MB_CLK_H2 MEM_MB_CLK_L2

MEM_VREF_DQ_B MEM_VREF_CA MEM_SCLK MEM_SDATA

VCC3

MEM_MB_HOT# 9

MEM_MB_DM[7..0] 9

MEM_MB0_ODT0 9 MEM_MB0_ODT1 9 MEM_MB_CKE0 9 MEM_MB_CKE1 9 MEM_MB0_CS_L0 9 MEM_MB0_CS_L1 9 MEM_MB_BANK0 9 MEM_MB_BANK1 9 MEM_MB_BANK2 9

MEM_MB_WE_L 9 MEM_MB_RAS_L 9 MEM_MB_CAS_L 9 MEM_MB_RESET# 9

MEM_MB_CLK_H1 9 MEM_MB_CLK_L1 9 MEM_MB_CLK_H2 9 MEM_MB_CLK_L2 9

MEM_VREF_CA

MEM_SCLK 12 MEM_SDATA 12

MEM_VREF_DQ_B

C88

C88 C0.1U25Y

C0.1U25Y

C98

C1000P50X0402

C98

C1000P50X0402

MEM_MB_DATA0 MEM_MB_DATA1 MEM_MB_DATA2 MEM_MB_DATA3 MEM_MB_DATA4 MEM_MB_DATA5 MEM_MB_DATA6 MEM_MB_DATA7 MEM_MB_DATA8 MEM_MB_DATA9 MEM_MB_DATA10 MEM_MB_DATA11 MEM_MB_DATA12 MEM_MB_DATA13 MEM_MB_DATA14 MEM_MB_DATA15 MEM_MB_DATA16 MEM_MB_DATA17 MEM_MB_DATA18 MEM_MB_DATA19 MEM_MB_DATA20 MEM_MB_DATA21 MEM_MB_DATA22 MEM_MB_DATA23 MEM_MB_DATA24 MEM_MB_DATA25 MEM_MB_DATA26 MEM_MB_DATA27 MEM_MB_DATA28 MEM_MB_DATA29 MEM_MB_DATA30 MEM_MB_DATA31 MEM_MB_DATA32 MEM_MB_DATA33 MEM_MB_DATA34 MEM_MB_DATA35 MEM_MB_DATA36 MEM_MB_DATA37 MEM_MB_DATA38 MEM_MB_DATA39 MEM_MB_DATA40 MEM_MB_DATA41 MEM_MB_DATA42 MEM_MB_DATA43 MEM_MB_DATA44 MEM_MB_DATA45 MEM_MB_DATA46 MEM_MB_DATA47 MEM_MB_DATA48 MEM_MB_DATA49 MEM_MB_DATA50 MEM_MB_DATA51 MEM_MB_DATA52 MEM_MB_DATA53 MEM_MB_DATA54 MEM_MB_DATA55 MEM_MB_DATA56 MEM_MB_DATA57 MEM_MB_DATA58 MEM_MB_DATA59 MEM_MB_DATA60 MEM_MB_DATA61 MEM_MB_DATA62 MEM_MB_DATA63

VCC_DDR VCC3

54

DIMM4

3

DQ0

VDD51VDD

VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD

4

DQ1

9

DQ2

10

DQ3

122

DQ4

123

DQ5

128

DQ6

129

DQ7

12

DQ8

13

DQ9

18

DQ10

19

DQ11

131

DQ12

132

DQ13

137

DQ14

138

DQ15

21

DQ16

22

DQ17

27

DQ18

28

DQ19

140

DQ20

141

DQ21

146

DQ22

147

DQ23

30

DQ24

31

DQ25

36

DQ26

37

DQ27

149

DQ28

150

DQ29

155

DQ30

156

DQ31

81

DQ32

82

DQ33

87

DQ34

88

DQ35

200

DQ36

201

DQ37

206

DQ38

207

DQ39

90

DQ40

91

DQ41

96

DQ42

97

DQ43

209

DQ44

210

DQ45

215

DQ46

216

DQ47

99

DQ48

100

DQ49

105

DQ50

106

DQ51

218

DQ52

219

DQ53

224

DQ54

225

DQ55

108

DQ56

109

DQ57

114

DQ58

115

DQ59

227

DQ60

228

DQ61

233

DQ62

234

DQ63

2

VSS

5

VSS

8

VSS

11

VSS

14

VSS

17

VSS

20

VSS

23

VSS

26

VSS

29

VSS

32

VSS

35

VSS

38

VSS

41

VSS

44

VSS

47

VSS

80

VSS

83

VSS

86

VSS

89

VSS

92

VSS

95

VSS

98

VSS

101

VSS

104

VSS

107

110

113

VSS

116

119

121

124

127

130

133

136

139

170

173

176

179

182

VDD

DDR3

VSS

142

145

148

151

154

DIMM4(CHANNEL-B B1) SM ADDRESS=A6

VTT_DDR

120

183

186

VDD

VSS

157

160

240

189

191

194

197

VDD

VSS

163

166

199

202

205

VSS

236

VDDSPD

VSS

208

211

79

48

68

53

167

VTT

RSVD

FREE1

FREE249FREE3

NC/TEST4

NC/PAR_IN

NC/ERR_OUT

DM0/DQS9

NC/DQS9# DM1/DQS10 NC/DQS10# DM2/DQS11 NC/DQS11# DM3/DQS12 NC/DQS12# DM4/DQS13 NC/DQS13# DM5/DQS14 NC/DQS14# DM6/DQS15 NC/DQS15# DM7/DQS16 NC/DQS16# DM8/DQS17 NC/DQS17#

CK1#(NU)

VSS

214

217

220

223

226

229

232

235

239

187

198

A0 A1

FREE4

A2 A3 A4 A5 A6 A7 A8 A9

A10/AP

A11 A12 A13 A14 A15

CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7

DQS0

DQS0#

DQS1

DQS1#

DQS2

DQS2#

DQS3

DQS3#

DQS4

DQS4#

DQS5

DQS5#

DQS6

DQS6#

DQS7

DQS7#

DQS8

DQS8#

ODT0 ODT1 CKE0 CKE1 CS0# CS1#

BA0 BA1 BA2

WE# RAS# CAS#

RESET#

CK0

CK0#

CK1(NU)

VREFDQ VREFCA

SCL SDA SA1 SA0

MEC1

MEC2

MEC3

DDRIII-240P_Green-RH

MEC1

MEC2

MEC3

188 181 61 180 59 58 178 56 177 175 70 55 174 196 172 171

39 40 45 46 158 159 164 165

7 6 16 15 25 24 34 33 85 84 94 93 103 102 112 111 43 42

125 126 134 135 143 144 152 153 203 204 212 213 221 222 230 231 161 162

195 77 50 169 193 76 71 190 52

73 192 74 168

184 185 63 64

1 67 118 238 237 117

MEM_MB_HOT#

MEM_MB_ADD0 MEM_MB_ADD1 MEM_MB_ADD2 MEM_MB_ADD3 MEM_MB_ADD4 MEM_MB_ADD5 MEM_MB_ADD6 MEM_MB_ADD7 MEM_MB_ADD8 MEM_MB_ADD9 MEM_MB_ADD10 MEM_MB_ADD11 MEM_MB_ADD12 MEM_MB_ADD13 MEM_MB_ADD14 MEM_MB_ADD15

MEM_MB_DQS_H0 MEM_MB_DQS_L0 MEM_MB_DQS_H1 MEM_MB_DQS_L1 MEM_MB_DQS_H2 MEM_MB_DQS_L2 MEM_MB_DQS_H3 MEM_MB_DQS_L3 MEM_MB_DQS_H4 MEM_MB_DQS_L4 MEM_MB_DQS_H5 MEM_MB_DQS_L5 MEM_MB_DQS_H6 MEM_MB_DQS_L6 MEM_MB_DQS_H7 MEM_MB_DQS_L7

MEM_MB_DM0 MEM_MB_DM1 MEM_MB_DM2 MEM_MB_DM3 MEM_MB_DM4 MEM_MB_DM5 MEM_MB_DM6 MEM_MB_DM7

MEM_MB1_ODT0 MEM_MB1_ODT1 MEM_MB_CKE0 MEM_MB_CKE1 MEM_MB1_CS_L0 MEM_MB1_CS_L1 MEM_MB_BANK0 MEM_MB_BANK1 MEM_MB_BANK2

MEM_MB_WE_L MEM_MB_RAS_L MEM_MB_CAS_L MEM_MB_RESET#

MEM_MB_CLK_H0 MEM_MB_CLK_L0 MEM_MB_CLK_H3 MEM_MB_CLK_L3

MEM_VREF_DQ_B MEM_VREF_CA MEM_SCLK MEM_SDATA

VCC3

MEM_MB1_ODT0 9 MEM_MB1_ODT1 9 MEM_MB_CKE0 9 MEM_MB_CKE1 9 MEM_MB1_CS_L0 9 MEM_MB1_CS_L1 9 MEM_MB_BANK0 9 MEM_MB_BANK1 9 MEM_MB_BANK2 9

MEM_MB_WE_L 9 MEM_MB_RAS_L 9 MEM_MB_CAS_L 9

MEM_MB_CLK_H0 9 MEM_MB_CLK_L0 9 MEM_MB_CLK_H3 9 MEM_MB_CLK_L3 9

MEM_VREF_CA

MEM_VREF_DQ_B

C121

C121 C0.1U25Y

C0.1U25Y

C124

C1000P50X0402

C124

C1000P50X0402

A A

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

Custom

Date: Sheet

5

4

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

DDR CH-B

FUSION 1.0

1

13 35Tuesday, May 03, 2011

of

A

DDR REF POWER & CAPS

VCC_DDR

B

C

D

E

De-coupling Caps For DIMMs

C242

X_C0.1u16Y0402

VTT_DDR

C759

X_C4.7u6.3X5

C760

X_C4.7u6.3X5

C376

C376 C1U10Y

C1U10Y

C377

C377 C1U10Y

C1U10Y

R182

VCC_DDR

R182

1KR1%

R181

1KR1%

R292

1KR1%

R333

1KR1%

R321

1KR1%

R325

1KR1%

C285

C133

C751

X_C0.1u10X0402

C282

C131

X_C1000P50X0402

C753

X_C1000P50X0402

C761

MEM_VREF_DQ_A

MEM_VREF_DQ_B

MEM_VREF_CA

C786

VCC3

C437

C0.1u16Y0402

C233

C233 C1U10Y

C1U10Y

C217

C217 C1U10Y

C1U10Y

C205

C205 C1U10Y

C1U10Y

C278

C278 C1U10Y

C1U10Y

C243

C243 C1U10Y

C1U10Y

C254

C254 C1U10Y

C1U10Y

C295

C295 C1U10Y

C1U10Y

C261

C261 C1U10Y

C1U10Y

VCC_DDRVCC_DDR

C292

C0.1u16Y0402

4 4

3 3

2 2

C0.1u10X0402

C1000P50X0402

VOLTAGE CONSOLE

0x28:RH=9.1K,RL=3K;Bit7=0

5VDIMM 5VDIMM

1 1

R687 X_3KR1%0402R687 X_3KR1%0402

R686

X_9.1KR1%0402

SCLK012,17,25 SDATA012,17,25

A

C803 X_C0.1u10X0402C803 X_C0.1u10X0402

R432R432 R422R422

U62

1

VCC

2

ADD_SEL

5

SCL

4

SDA

3

GND

X_NCT3931U-2_SOT23-8-HF

Option PN I34-6262B09-U33

OUT1 OUT2 OUT3

8 7 6

Bit7=0 OUT1=10uA OUT2=10uA OUT3=10uA

MEM_VREF_DQ_A MEM_VREF_DQ_B

B

MICRO-START INT'L CO.,LTD.

Title

DDR REF POWER & CAPS

Size Document Number Rev

B

Date: Sheet

C

D

Date: Sheet

MICRO-START INT'L CO.,LTD.

FUSION 1.0

14 35Friday, April 29, 2011

of

E

of

5

4

3

2

1

D D

C C

B B

EMI Reserved

VCC5

C2 C0.1u16Y0402C2 C0.1u16Y0402 C4 C0.1u16Y0402C4 C0.1u16Y0402 C6 X_C0.1u16Y0402C6 X_C0.1u16Y0402 C8 X_C0.1u16Y0402C8 X_C0.1u16Y0402 C10 C0.1u16Y0402C10 C0.1u16Y0402 C13 X_C0.1u16Y0402C13 X_C0.1u16Y0402 C23 C0.1u16Y0402C23 C0.1u16Y0402

VCC5 VCC3

C36 X_C0.1u16Y0402C36 X_C0.1u16Y0402

VCC3_SB

C49 C0.1u16Y0402C49 C0.1u16Y0402 C55 X_C0.1u16Y0402C55 X_C0.1u16Y0402 C63 C0.1u16Y0402C63 C0.1u16Y0402 C69 X_C0.1u16Y0402C69 X_C0.1u16Y0402

-12V

C94 C0.1u16Y0402C94 C0.1u16Y0402 C103 X_C0.1u16Y0402C103 X_C0.1u16Y0402

VCC5

C115 C10u16Y1206C115 C10u16Y1206 C145 C10u16Y1206C145 C10u16Y1206

C301 X_C10u6.3X50805C301 X_C10u6.3X50805 C311 X_C10u6.3X50805C311 X_C10u6.3X50805

C756 X_C4.7u6.3X5C756 X_C4.7u6.3X5 C788 X_C4.7u6.3X5C788 X_C4.7u6.3X5

VCC3

C3 C0.1u16Y0402C3 C0.1u16Y0402 C5 C0.1u16Y0402C5 C0.1u16Y0402 C7 X_C0.1u16Y0402C7 X_C0.1u16Y0402 C9 X_C0.1u16Y0402C9 X_C0.1u16Y0402 C11 X_C0.1u16Y0402C11 X_C0.1u16Y0402 C14 X_C0.1u16Y0402C14 X_C0.1u16Y0402 C24 X_C0.1u16Y0402C24 X_C0.1u16Y0402 C29 X_C0.1u16Y0402C29 X_C0.1u16Y0402 C37 X_C0.1u16Y0402C37 X_C0.1u16Y0402 C41 X_C0.1u16Y0402C41 X_C0.1u16Y0402 C50 X_C0.1u16Y0402C50 X_C0.1u16Y0402 C57 X_C0.1u16Y0402C57 X_C0.1u16Y0402 C64 X_C0.1u16Y0402C64 X_C0.1u16Y0402 C71 X_C0.1u16Y0402C71 X_C0.1u16Y0402 C74 X_C0.1u16Y0402C74 X_C0.1u16Y0402

VCC5_SB

C81 X_C0.1u16Y0402C81 X_C0.1u16Y0402 C89 X_C0.1u16Y0402C89 X_C0.1u16Y0402 C15 X_C0.1u16Y0402C15 X_C0.1u16Y0402 C25 X_C0.1u16Y0402C25 X_C0.1u16Y0402 C30 X_C0.1u16Y0402C30 X_C0.1u16Y0402 C38 X_C0.1u16Y0402C38 X_C0.1u16Y0402 C42 X_C0.1u16Y0402C42 X_C0.1u16Y0402

+12V

C51 C0.1u16Y0402C51 C0.1u16Y0402 C58 X_C0.1u16Y0402C58 X_C0.1u16Y0402 C65 X_C0.1u16Y0402C65 X_C0.1u16Y0402 C72 X_C0.1u16Y0402C72 X_C0.1u16Y0402 C75 X_C0.1u16Y0402C75 X_C0.1u16Y0402 C82 X_C0.1u16Y0402C82 X_C0.1u16Y0402 C90 X_C0.1u16Y0402C90 X_C0.1u16Y0402

VCC3

C313 X_C10u6.3X50805C313 X_C10u6.3X50805

VCCP

C773 C0.1u16Y0402C773 C0.1u16Y0402 C772 C0.1u16Y0402C772 C0.1u16Y0402 C769 X_C0.1u16Y0402C769 X_C0.1u16Y0402 C766 X_C0.1u16Y0402C766 X_C0.1u16Y0402 C771 C0.1u16Y0402C771 C0.1u16Y0402 C78 X_C0.1u16Y0402C78 X_C0.1u16Y0402 C767 X_C0.1u16Y0402C767 X_C0.1u16Y0402 C768 X_C0.1u16Y0402C768 X_C0.1u16Y0402 C752 X_C0.1u16Y0402C752 X_C0.1u16Y0402 C765 X_C0.1u16Y0402C765 X_C0.1u16Y0402 C770 X_C0.1u16Y0402C770 X_C0.1u16Y0402 C776 C0.1u16Y0402C776 C0.1u16Y0402 C774 C0.1u16Y0402C774 C0.1u16Y0402 C775 C0.1u16Y0402C775 C0.1u16Y0402 C777 C0.1u16Y0402C777 C0.1u16Y0402

C780 X_C0.1u16Y0402C780 X_C0.1u16Y0402 C778 X_C0.1u16Y0402C778 X_C0.1u16Y0402 C779 C0.1u16Y0402C779 C0.1u16Y0402 C781 X_C0.1u16Y0402C781 X_C0.1u16Y0402

VCC_DDR

C349

X_C0.1u16Y0402

C348

X_C0.1u16Y0402

C549

X_C0.1u16Y0402

C369

X_C0.1u16Y0402

A A

MICRO-START INT'L CO.,LTD.

Title

EMI Reserved

Size Document Number Rev

Custom

Date: Sheet

5

4

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

FUSION 1.0

1

of

15 35Friday, April 29, 2011

5

4

3

2

1

HUDSON PCIE/PCI/APU/LPC/CLK

U600E

A_RST# for LPC device; PCIE_RST# for APU PCIE device; PCIE_RST#2 FCH PCIE device

FCH_PCIE_RST#_R

D D

FCH_A_RST#_R

R527 33R0402R527 33R0402

R526 33R0402R526 33R0402

C585

C1000P50X0402

A_RST#

C584

X_C150p25N0402

PCIE_RST# 24,31,32

To PCIEX16,X1,LAN

A_RST# 25

To SIO,LPC debug

UMI_RX0P8 UMI_RX0N8 UMI_RX1P8 UMI_RX1N8 UMI_RX2P8 UMI_RX2N8 UMI_RX3P8 UMI_RX3N8

UMI_TX0P8 UMI_TX0N8 UMI_TX1P8 UMI_TX1N8 UMI_TX2P8 UMI_TX2N8 UMI_TX3P8 UMI_TX3N8

FCH_VDD11_RUN

GPP_TXC_0P32 GPP_TXC_0N32 GPP_TXC_1P32 GPP_TXC_1N32 GPP_TXC_2P32 GPP_TXC_2N32

C C

DISP_CLK10

For external clock generator mode: 100-MHz reference clock for the FCH. Spreadcapable. For internal clock generator mode: Not used. Left unconnected. The function is selected by the pin strap “CLKGEN” (pin LPCCLK1).

B B

C610 X_C10p50N0402C610 X_C10p50N0402

SIO_48M_CLK

DISP_CLK#10

Fusion Mode:100Mhz Non-Fusion Mode:200Mhz

APU_CLK10 APU_CLK#10

PE16_GXF_CLK31 PE16_GXF_CLK#31

PE1_GPP_CLK032 PE1_GPP_CLK0#32

PE1_GPP_CLK132 PE1_GPP_CLK1#32

PE1_GPP_CLK232 PE1_GPP_CLK2#32

PE_LAN_CLK24 PE_LAN_CLK#24

SIO_48M_CLK25

FCH_VDD11_RUN

MACH@bios porting to 48M clock output

C468 C0.1u10X0402C468 C0.1u10X0402 C469 C0.1u10X0402C469 C0.1u10X0402 C467 C0.1u10X0402C467 C0.1u10X0402 C466 C0.1u10X0402C466 C0.1u10X0402 C464 C0.1u10X0402C464 C0.1u10X0402 C465 C0.1u10X0402C465 C0.1u10X0402 C462 C0.1u10X0402C462 C0.1u10X0402 C463 C0.1u10X0402C463 C0.1u10X0402

R386 590R1%0402R386 590R1%0402

Layout: Place within 1 inch

R451 2KR1%0402R451 2KR1%0402

R380 0R0402R380 0R0402 R379 0R0402R379 0R0402

INT

R412 0R0402R412 0R0402 R405 0R0402R405 0R0402

R423 0R0402R423 0R0402 R417 0R0402R417 0R0402

R461 0R0402R461 0R0402 R462 0R0402R462 0R0402

R463 0R0402R463 0R0402 R464 0R0402R464 0R0402

R465 0R0402R465 0R0402 R466 0R0402R466 0R0402

R443 0R0402R443 0R0402 R437 0R0402R437 0R0402

MACH@???DG:Leave NC if not used; CRB reserve 49.9R to GND

R460 22R0402R460 22R0402

C487 C22p50N0402-RHC487 C22p50N0402-RH

Y2

Y2 25MHZ18P_D-4

25MHZ18P_D-4

C451 C22p50N0402-RHC451 C22p50N0402-RH

1 2

Layout:Place x'tal within 1.5 inch of FCH

FCH_25M_X120 FCH_25M_X220

R387 2KR1%0402R387 2KR1%0402

C473 C0.1u10X0402C473 C0.1u10X0402 C474 C0.1u10X0402C474 C0.1u10X0402 C533 C0.1u10X0402C533 C0.1u10X0402 C534 C0.1u10X0402C534 C0.1u10X0402 C614 C0.1u10X0402C614 C0.1u10X0402 C615 C0.1u10X0402C615 C0.1u10X0402

GPP_RX0P32 GPP_RX0N32 GPP_RX1P32 GPP_RX1N32 GPP_RX2P32 GPP_RX2N32

FCH_DISP_CLKP_R FCH_DISP_CLKN_R

FCH_APU_CLKP_R FCH_APU_CLKN_R

FCH_GFX_CLKP_R FCH_GFX_CLKN_R

FCH_GPP_CLK0P_R FCH_GPP_CLK0N_R

FCH_GPP_CLK1P_R FCH_GPP_CLK1N_R

FCH_GPP_CLK2P_R FCH_GPP_CLK2N_R

FCH_GPP_CLK3P_R FCH_GPP_CLK3N_R

FCH_48M

R408

R408 1MR

1MR

FCH_25M_X1 FCH_25M_X2

FCH_PCIE_RST#_R FCH_A_RST#_R

UMI_RX0P_FCH UMI_RX0N_FCH UMI_RX1P_FCH UMI_RX1N_FCH UMI_RX2P_FCH UMI_RX2N_FCH UMI_RX3P_FCH UMI_RX3N_FCH

PCIE_CALRP PCIE_CALRN

GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N

CLK_CALRN

FCH_25M_X1

FCH_25M_X2

AE30 AE32 AD33 AD31 AD28 AD29 AC30 AC32

AB33 AB31 AB28 AB29

AF29 AF31

AB26 AB27 AA24 AA23

AA27 AA26

AE2

AD5

Y33 Y31 Y28 Y29

V33

V31 W30 W32

W27

V27

V26 W26 W24 W23

F27

G30

G28

R26

T26

H33

H31

T24

T23

J30

K29

H27

H28

J27

K26

F33

F31

E33

E31

M23

M24

M27

M26

N25

N26

R23

R24

N27

R27

J26

C31

C33

PCIE_RST# A_RST#

UMI_TX0P UMI_TX0N UMI_TX1P UMI_TX1N UMI_TX2P UMI_TX2N UMI_TX3P UMI_TX3N

UMI_RX0P UMI_RX0N UMI_RX1P UMI_RX1N UMI_RX2P UMI_RX2N UMI_RX3P UMI_RX3N

PCIE_CALRP PCIE_CALRN

GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N

GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N

CLK_CALRN

PCIE_RCLKP PCIE_RCLKN

DISP_CLKP DISP_CLKN

DISP2_CLKP DISP2_CLKN

APU_CLKP APU_CLKN

SLT_GFX_CLKP SLT_GFX_CLKN

GPP_CLK0P GPP_CLK0N

GPP_CLK1P GPP_CLK1N

GPP_CLK2P GPP_CLK2N

GPP_CLK3P GPP_CLK3N

GPP_CLK4P GPP_CLK4N

GPP_CLK5P GPP_CLK5N

GPP_CLK6P GPP_CLK6N

GPP_CLK7P GPP_CLK7N

GPP_CLK8P GPP_CLK8N

14M_25M_48M_OSC

25M_X1

25M_X2

HUDSON-2

U600E

Part 1 of 5

PCI CLKS

PCI EXPRESS INTERFACES

PCI INTERFACE

CLOCK GENERATOR

APU

S5 PLUS

?

PCICLK4/14M_OSC/GPO39

REQ2#/CLK_REQ8#/GPIO41 REQ3#/CLK_REQ5#/GPIO42

GNT2#/SD_LED/GPO45

GNT3#/CLK_REQ7#/GPIO46

LPC

LDRQ1#/CLK_REQ6#/GPIO49

INTRUDER_ALERT#

PCICLK0 PCICLK1/GPO36 PCICLK2/GPO37 PCICLK3/GPO38

PCIRST#

AD0/GPIO0 AD1/GPIO1 AD2/GPIO2 AD3/GPIO3 AD4/GPIO4 AD5/GPIO5 AD6/GPIO6 AD7/GPIO7 AD8/GPIO8

AD9/GPIO9 AD10/GPIO10 AD11/GPIO11 AD12/GPIO12 AD13/GPIO13 AD14/GPIO14 AD15/GPIO15 AD16/GPIO16 AD17/GPIO17 AD18/GPIO18 AD19/GPIO19 AD20/GPIO20 AD21/GPIO21 AD22/GPIO22 AD23/GPIO23 AD24/GPIO24 AD25/GPIO25 AD26/GPIO26 AD27/GPIO27 AD28/GPIO28 AD29/GPIO29 AD30/GPIO30 AD31/GPIO31

DEVSEL#

REQ1#/GPIO40

GNT1#/GPO44

CLKRUN#

INTE#/GPIO32 INTF#/GPIO33 INTG#/GPIO34 INTH#/GPIO35

LPCCLK0 LPCCLK1

LFRAME#

SERIRQ/GPIO48

DMA_ACTIVE#

PROCHOT#

LDT_STP#

APU_RST#

S5_CORE_EN

VDDBT_RTC_G

FRAME#

LDRQ0#

APU_PG

32K_X1

32K_X2

RTCCLK

AF3 AF1 AF5 AG2 AF6

AB5

AJ3 AL5 AG4 AL6 AH3 AJ5 AL1 AN5 AN6 AJ1 AL8 AL3 AM7 AJ6 AK7 AN8 AG9 AM11 AJ10 AL12 AK11 AN12 AG12 AE12 AC12 AE13 AF13 AH13 AH14 AD15 AC15 AE16

CBE0#

AN3

CBE1#

AJ8

CBE2#

AN10

CBE3#

AD12 AG10 AK9

IRDY#

AL10

TRDY#

AF10

PAR

AE10

STOP#

AH1

PERR#

AM9

SERR#

AH8

REQ0#

AG15 AG13 AF15 AM17

GNT0#

AD16 AD13 AD21 AK17 AD19

LOCK#

AH9 AF18

AE18 AC16 AD18

B25 D25

LAD0

D27

LAD1

C28

LAD2

A26

LAD3

A29 A31 B27 AE27 AE19

G25 E28 E26 G26 F26

G2 G4 H7

F1 F3 E6

Layout:Place x'tal within 1.5 inch of FCH

FCH_32K_X1

A A

FCH_32K_X2

12

4

3

Y5

32.768KHZ12.5P_D-1

R519 20MRR519 20MR

C573

C18p50N

mach@CRB use 22pF

5

4

3

C18p50N

PLACE THESE COMPONENTS CLOSE TO U600, AND USE GROUND GUARD FOR 32K_X1 AND 32K_X2

C574

C18p50N

Layout: Place close to FCH

PCI_CLK_SIO_R PCI_CLK_SIO

R529 33R0402R529 33R0402

PCI_CLK2_R

PCIRST#

R551 22R0402R551 22R0402

PCI_CLK_DEBUG

TP66TP66

CLR_CMOS

If PCI not implemented: Provide test points or other means to allowaccess for debug purposes. use these balls for alternate GPIO/GPO functions or leave unconnected.

AD23

AD23 20

AD24

AD24 20

AD25

AD25 20

AD26

AD26 20

AD27

AD27 20

PREQ3#

PREQ3# 20

PGNT#3

PGNT#3 20

LPC_CLK0

LPC_CLK0 20

LPC_CLK1

LPC_CLK1 20 LPC_AD[3..0] 25

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# LPC_DRQ#0

SERIRQ

APU_PG_R

R447 0R0402R447 0R0402

APU_RST#_R

R450 0R0402R450 0R0402

FCH_32K_X1 FCH_32K_X2 S5_CORE_EN

TP63TP63

RTC_CLK VBAT_FCH

Layout: Place close to pin B1 ASAP 0603 size and X5R for CMOS issue

LPC_AD[3..0]

LPC_FRAME# 25

LPC_DRQ#0 25

SERIRQ 25

FCH_DMA_ACTIVE# 10 APU_PROCHOT# 10

APU_PWRGD 7,10 APU_RST# 10

This signal is for enabling the standby power when S5 plus logic is enabled

RTC_CLK 20

C550

C546

C546 C0.1U25X

C0.1U25X

C550

C1u10X7R

2

PCI_CLK_SIO 25 PCI_CLK1 20 PCI_CLK_DEBUG 25 PCI_CLK3 20 PCI_CLK4 20

PCI_CLK_SIO PCI_CLK_DEBUG

C565 X_C10p50N0402C565 X_C10p50N0402 C598 X_C10p50N0402C598 X_C10p50N0402

CLEAR CMOS

VCC3

R534

R534 10KR0402

10KR0402

CLR_CMOS

Note: LDT_PG, LDT_STP# & LDT_RST# are OD and require a PU to the APU I/O rail. They are also in the S5 domain to prevent glitching at power up.

VBAT

R533 510R0402R533 510R0402

Title

Size Document Number Rev

C

Date: Sheet

1 2 3

H1X3M_RED-RH

CMOS CLEAR JUMPER CLR_COMS Clear CMOS

Normal

1 - 2 2 - 3 Clear CMOS

SERIRQ

R418 X_10KR0402R418 X_10KR0402

Layout: VBAT route 20mils

BAT1

BAT2P_BLACK-RH

MICRO-START INT'L CO.,LTD.

HUDSON PCIE/PCI/APU/LPC/CLK

FUSION 1.0

1

CLR_CMOS_X1

JUMP1X2A_RED-RH

6.0

16 35Tuesday, August 16, 2011

VCC3

of

5

4

3

2

1

HUDSON ACPI/USB/AZ/GPIO

mach@???DS require external PU;

VCC3_SB

DG/CRB W/O PU resister

R525 X_10KR0402R525 X_10KR0402 R521 X_10KR0402R521 X_10KR0402

VCC3_SB

D D

C C

R568 10KR0402R568 10KR0402

Layout:Place close to FCH ASAP

FCH_PWRGD

VCC3

mach@DG???PU to VCC3 rail and leave unconnected

R429 300R0402R429 300R0402

VCC3_SB

R566 X_22KR0402R566 X_22KR0402

VCC3

R384 2.2KR0402R384 2.2KR0402 R385 2.2KR0402R385 2.2KR0402

VCC3_SB

R544 2.2KR0402R544 2.2KR0402 R543 2.2KR0402R543 2.2KR0402

VCC3_SB

RN14 8P4R-10KR0402RN14 8P4R-10KR0402

1 3 5 7

RN13 8P4R-10KR0402RN13 8P4R-10KR0402

1 3 5 7

AZ_SDOUT28 AZ_BIT_CLK28

AZ_SYNC28 AZ_RST#28

AZ_SDIN

B B

R550 may stuff 15pF cap for EMI

AZ_BIT_CLK AZ_SDIN

SLP_S3# SLP_S5#

FCH_WAKE#

C595 X_C1000P50X0402C595 X_C1000P50X0402

WD_PWRGD

FCH_RSMRST#

C559

C559 C1000P50X0402

C1000P50X0402

SCLK0 SDATA0

SCLK1 SDATA1

OC#1

2 4

OC#7

6

OC#6

8

OC#2

2 4

OC#0

6

OC#5

8

Layout: Place close to FCH

R547 33R0402R547 33R0402 R662 33R0402R662 33R0402 R663 33R0402R663 33R0402 R664 33R0402R664 33R0402

C562 15p50N0402C562 15p50N0402

R550 X_10KR0402R550 X_10KR0402 R554 X_10KR0402R554 X_10KR0402

SLP_S3#25,26,27 SLP_S5#25,26,27,30 PSOUT#25

FCH_PWRGD25,27

A20GATE25

Inte-grated PU

Rise time ≤ 50-ms +3.3V_S5 voltage rails ramp up at least 10-ms before RSMRST# is deasserted

S0 POWER DOMAIN

ROUTE TO DIMMs,SIO

S5 POWER DOMAIN

ROUTE TO LAN,PCIE,Mini_PCIE

KBRST#25 IO_PME#25 LPC_SMI#25

FP_RST#25,27,33

PE_WAKE#24,25,31,32

FCH_THERMTRIP#10

IO_RSMRST#25

RSRMT# should be asserted when system power is being applied for the first time. RSMRST# should be deasserted sometime after S5 power is up, and should stay deasserted until system power is removed.

SPKR33 SCLK012,14,25 SDATA012,14,25 SCLK131,32 SDATA131,32

SPI_HOLD#_R18

USB Overcurrent Implemented: Connect to overcurrent signal from USB connector (note that these are programmable and can be flexibly assigned as needed). Configure for a

3.3-V swing (i.e. not 5-V) and use low-pass filter to prevent glitches during plug/unplug events. If USB ports are not powered in S4/S5 states and the FCH’s internal pullups are enabled, provide a diode between the FCH and overcurrent circuit (cathode towards the FCH) to prevent leakage from the FCH internal pullups in S4/S5 states.

AZ_SDATA_OUT_R AZ_BITCLK_R AZ_SYNC_R AZ_RST_R

mach@verify the ports being used

Inte-grated PU

AZ_SDIN28

MACH@ RESERVE TP

R556 15R0402R556 15R0402 R584 15R0402R584 15R0402

SCLK0 SDATA0 SCLK1 SDATA1

PCIE_RST2#

RI#

SLP_S3#_R

SLP_S5#_R PSOUT# FCH_PWRGD

FCH_TEST0 FCH_TEST1 FCH_TEST2

FCH_WAKE#

WD_PWRGD FCH_RSMRST#

TP59TP59

SLP_S3# SLP_S5#

FCH_TEST020 FCH_TEST120 FCH_TEST220

R541 X_0R0402R541 X_0R0402

R567 0R0402R567 0R0402

TP47TP47

SPI_HOLD#_R

OC#730 OC#630 OC#530 OC#430 OC#320,30 OC#220,30 OC#120,30

OC#0

OC#020,30

AZ_BITCLK_R AZ_SDATA_OUT_R

AZ_SDIN AZ_SYNC_R AZ_RST_R

TP35TP35 TP34TP34

KBC Not Implemented: Use for alternate available function or leave not connected.

FOR GPIO[226:209] KBC Not Implemented: Use for alternate available function or leave not connected.

PCIE_RST2#/GEVENT4#

AB6

RI#/GEVENT22#

R2

SPI_CS3#/GBE_STAT1/GEVENT21#

W7

SLP_S3#

T3

SLP_S5#

W2

PWR_BTN#

J4

PWR_GOOD

N7

TEST0

T9

TEST1/TMS

T10

TEST2

V9

GA20IN/GEVENT0#

AE22

KBRST#/GEVENT1#

AG19

PME#/GEVENT3#

R9

LPC_SMI#/GEVENT23#

C26

LPC_PD#/GEVENT5#

T5

SYS_RESET#/GEVENT19#

U4

WAKE#/GEVENT8#

K1

IR_RX1/GEVENT20#

V7

THRMTRIP#/SMBALERT#/GEVENT2#

R10

WD_PWRGD

AF19

RSMRST#

U2

CLK_REQ4#/SATA_IS0#/GPIO64

AG24

CLK_REQ3#/SATA_IS1#/GPIO63

AE24

SMARTVOLT1/SATA_IS2#/GPIO50

AE26

CLK_REQ0#/SATA_IS3#/GPIO60

AF22

SATA_IS4#/FANOUT3/GPIO55

AH17

SATA_IS5#/FANIN3/GPIO59

AG18

SPKR/GPIO66

AF24

SCL0/GPIO43

AD26

SDA0/GPIO47

AD25

SCL1/GPIO227

T7

SDA1/GPIO228

R7

CLK_REQ2#/FANIN4/GPIO62

AG25

CLK_REQ1#/FANOUT4/GPIO61

AG22

IR_LED#/LLB#/GPIO184

J2

SMARTVOLT2/SHUTDOWN#/GPIO51

AG26

DDR3_RST#/GEVENT7#/VGA_PD

V8

GBE_LED0/GPIO183

W8

SPI_HOLD#/GBE_LED1/GEVENT9#

Y6

GBE_LED2/GEVENT10#

V10

GBE_STAT0/GEVENT11#

AA8

CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#

AF25

BLINK/USB_OC7#/GEVENT18#

M7

USB_OC6#/IR_TX1/GEVENT6#

R8

USB_OC5#/IR_TX0/GEVENT17#

T1

USB_OC4#/IR_RX0/GEVENT16#

P6

USB_OC3#/AC_PRES/TDO/GEVENT15#

F5

USB_OC2#/TCK/GEVENT14#

P5

USB_OC1#/TDI/GEVENT13#

J7

USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12#

T8

AZ_BITCLK

AB3

AZ_SDOUT

AB1

AZ_SDIN0/GPIO167

AA2

AZ_SDIN1/GPIO168

Y5

AZ_SDIN2/GPIO169

Y3

AZ_SDIN3/GPIO170

Y1

AZ_SYNC

AD6

AZ_RST#

AE4

PS2_DAT/SDA4/GPIO187

K19

PS2_CLK/CEC/SCL4/GPIO188

J19

SPI_CS2#/GBE_STAT2/GPIO166

J21

PS2KB_DAT/GPIO189

D21

PS2KB_CLK/GPIO190

C20

PS2M_DAT/GPIO191

D23

PS2M_CLK/GPIO192

C22

KSO_0/GPIO209

F21

KSO_1/GPIO210

E20

KSO_2/GPIO211

F20

KSO_3/GPIO212

A22

KSO_4/GPIO213

E18

KSO_5/GPIO214

A20

KSO_6/GPIO215

J18

KSO_7/GPIO216

H18

KSO_8/GPIO217

G18

KSO_9/GPIO218

B21

KSO_10/GPIO219

K18

KSO_11/GPIO220

D19

KSO_12/GPIO221

A18

KSO_13/GPIO222

C18

KSO_14/XDB0/GPIO223

B19

KSO_15/XDB1/GPIO224

B17

KSO_16/XDB2/GPIO225

A24

KSO_17/XDB3/GPIO226

D17

HUDSON-2

Part 4 of 5

U600A

HD AUDIO

EMBEDDED CTRL

USB MISCUSB 1.1

ACPI / WAKE UP EVENTS

USB 2.0

GPIO

USB OC

USB 3.0

EC_PWM0/EC_TIMER0/GPIO197 EC_PWM1/EC_TIMER1/GPIO198

EC_PWM2/EC_TIMER2/WOL_EN/GPIO199

EC_PWM3/EC_TIMER3/GPIO200

USBCLK/14M_25M_48M_OSC

USB_RCOMP

USB_FSD1P/GPIO186

USB_FSD1N

USB_FSD0P/GPIO185

USB_FSD0N

USB_HSD13P USB_HSD13N

USB_HSD12P USB_HSD12N

USB_HSD11P USB_HSD11N

USB_HSD10P USB_HSD10N

USB_HSD9P USB_HSD9N

USB_HSD8P USB_HSD8N

USB_HSD7P USB_HSD7N

USB_HSD6P USB_HSD6N

USB_HSD5P USB_HSD5N

USB_HSD4P USB_HSD4N

USB_HSD3P USB_HSD3N

USB_HSD2P USB_HSD2N

USB_HSD1P USB_HSD1N

USB_HSD0P USB_HSD0N

USBSS_CALRP USBSS_CALRN

USB_SS_TX3P USB_SS_TX3N

USB_SS_RX3P USB_SS_RX3N

USB_SS_TX2P USB_SS_TX2N

USB_SS_RX2P USB_SS_RX2N

USB_SS_TX1P USB_SS_TX1N

USB_SS_RX1P USB_SS_RX1N

USB_SS_TX0P USB_SS_TX0N

USB_SS_RX0P USB_SS_RX0N

SCL2/GPIO193

SDA2/GPIO194 SCL3_LV/GPIO195 SDA3_LV/GPIO196

KSI_0/GPIO201 KSI_1/GPIO202 KSI_2/GPIO203 KSI_3/GPIO204 KSI_4/GPIO205 KSI_5/GPIO206 KSI_6/GPIO207 KSI_7/GPIO208

14M_25M_48M_OSC

G8

USB_RCOMP

B9 H1

H3 H6

H5 H10

G10 K10

J12 G12

F12 K12

K13 B11

D11 E10

F10 C10

A10 H9

G9 A8

C8 F8

E8 C6

A6 C5

A5 C1

C3 E1

E3 C16

A16 A14

C14 C12

A12 D15

B15 E14

F14 F15

G15 H13

G13 J16

H16 J15

K15

H19 G19 G22 G21 E22 H22 J22 H21

K21 K22 F22 F24 E24 B23 C24 F18

R491 11.8KR1%0402R491 11.8KR1%0402

Layout: Place within 1'' of FCH

USB13+ 29 USB13- 29

USB12+ 29 USB12- 29

USB11+ 29 USB11- 29

USB10+ 29 USB10- 29

USB9+ 29 USB9- 29

USB8+ 29 USB8- 29

USB5+ 29 USB5- 29

USB4+ 29 USB4- 29

USB3+ 29 USB3- 29

USB2+ 29 USB2- 29

USB1+ 29 USB1- 29

USB0+ 29 USB0- 29

USBSS_CALRP

R483 1KR1%0402R483 1KR1%0402

USBSS_CALRN

R484 1KR1%0402R484 1KR1%0402

SCLK3 SDATA3

TP81TP81 TP82TP82

FOR GPIO[208:197] KBC Not Implemented: Use for alternate available function or leave not connected.

TP80TP80

mach@Rerouting the USB pairs follow layout

USB11 FRONT PANEL USB10 FRONT PANEL USB9 FRONT PANEL USB8 FRONT PANEL USB7 FRONT PANEL USB6 FRONT PANEL

USB3 USB2 BOTTOM USB2 USB2 TOP USB1 LAN USB BOTTOM USB0 LAN USB TOP

FCH_VDD_11_SSUSB_S

USB_SS_TX3P 29 USB_SS_TX3N 29

USB_SS_RX3P 29 USB_SS_RX3N 29

USB_SS_TX2P 29 USB_SS_TX2N 29

USB_SS_RX2P 29 USB_SS_RX2N 29

USB_SS_TX1P 29 USB_SS_TX1N 29

USB_SS_RX1P 29 USB_SS_RX1N 29

USB_SS_TX0P 29 USB_SS_TX0N 29

USB_SS_RX0P 29 USB_SS_RX0N 29

FOR Pin H19,G19 Use as GPIO or configure as one of the following: 10-kΩ 5% pull-up resistor to +3.3V_S5. 10-kΩ 5% pull-down resistor.

FCH_GPIO199 20

?

Wake On Modem Header

A A

5

4

N_RI25

N_RI RI#

+12VActive Low

R578 10KR0402R578 10KR0402

R577

R577 10KR0402

10KR0402

INT 10k PU

HighNormal -12V

B

C621

C621 X_C1U16X5

X_C1U16X5

RI#RI#

CE

Q68

C620

C620 X_C1000P50X0402

X_C1000P50X0402

Title

N-SST3904_SOT23

3

2

Title

Size Document Number Rev

C

Date: Sheet

MICRO-START INT'L CO.,LTD.

HUDSON ACPI/USB/AZ/GPIO

FUSION 1.0

1

17 35Thursday, September 15, 2011

of

5

4

3

2

1

HUDSON SATA/VGA/SPI/HWM

D D

SATA[3::0]Route to iSATA GEN III 6.0 Gbit/S

SATA[5::4]Route to e-SATA

C C

GEN II 3.0 Gbit/S

FCH_VDD11_RUN

External Clock Generator Mode: Connect to 25.000-MHz XTAL or connect SATA_X1/X2 balls to 100MHz differential clock from external clock generator. Integrated Clock Mode: Leave unconnected.

B B

LAYOUT: ROUTE SATA TX DIFF PAIR @ 100 OHM+/-10% RX DIFF PAIR @ 90 OHM+/-10%

TP83TP83

TP84TP84

SATA_TX0+ SATA_TX0-

SATA_RX0SATA_RX0+

SATA_TX1+ SATA_TX1-

SATA_RX1SATA_RX1+

SATA_TX2+ SATA_TX2-

SATA_RX2SATA_RX2+

SATA_TX3+ SATA_TX3-

SATA_RX3SATA_RX3+

SATA_TX4+ SATA_TX4-

SATA_RX4SATA_RX4+

SATA_LED#

FCH_SATA_X1

FCH_SATA_X2

SATA_TX0+23 SATA_TX0-23

SATA_RX0-23 SATA_RX0+23

SATA_TX1+23 SATA_TX1-23

SATA_RX1-23 SATA_RX1+23

SATA_TX2+23 SATA_TX2-23

SATA_RX2-23 SATA_RX2+23

SATA_TX3+23 SATA_TX3-23

SATA_RX3-23 SATA_RX3+23

SATA_TX4+23 SATA_TX4-23

SATA_RX4-23 SATA_RX4+23

Layout: Place within 1'' of FCH

R388 1KR1%0402R388 1KR1%0402 R389 1KR1%0402R389 1KR1%0402

SATA_LED#33

FANOUT020

PIN K3,K5,K6: Use as GPIO182 or configure as one of the following: 10-kΩ 5% pull-up resistor to +3.3V_S5. 10-kΩ 5% pull-down resistor.

FCH_TALERT#10

FCH_TALERT#

SATA_CALRP SATA_CALRN

AK19 AM19

AL20

AN20 AN22

AL22

AH20

AJ20 AJ22

AH22 AM23

AK23 AH24

AJ24

AN24

AL24 AL26

AN26

AJ26

AH26 AN29

AL28

AK27 AM27

AL29

AN31

AL31 AL33

AH33 AH31

AJ33 AJ31

AF28 AF27

AD22

AF21

AG21

AH16 AM15

AJ16

AK15 AN16

AL16

K6 K5 K3 M6

SATA_TX0P SATA_TX0N

SATA_RX0N SATA_RX0P

SATA_TX1P SATA_TX1N

SATA_RX1N SATA_RX1P

SATA_TX2P SATA_TX2N

SATA_RX2N SATA_RX2P

SATA_TX3P SATA_TX3N

SATA_RX3N SATA_RX3P

SATA_TX4P SATA_TX4N

SATA_RX4N SATA_RX4P

SATA_TX5P SATA_TX5N

SATA_RX5N SATA_RX5P

NC6 NC7

NC8 NC9

NC10 NC11

NC12 NC13

SATA_CALRP SATA_CALRN

SATA_ACT#/GPIO67

SATA_X1

SATA_X2

FANOUT0/GPIO52 FANOUT1/GPIO53 FANOUT2/GPIO54

FANIN0/GPIO56 FANIN1/GPIO57 FANIN2/GPIO58

TEMPIN0/GPIO171 TEMPIN1/GPIO172 TEMPIN2/GPIO173 TEMPIN3/TALERT#/GPIO174

HUDSON-2

?

SERIAL ATA

HW MONITOR

U600B

Part 2 of 5

SD CARD

SPI ROM

VGA DAC

VGA MAINLINK

GBE LAN

SD_CLK/SCLK_2/GPIO73

SD_CMD/SLOAD_2/GPIO74

SD_DATA0/SDATI_2/GPIO77

SD_DATA1/SDATO_2/GPIO78

ROM_RST#/SPI_WP#/GPIO161

VGA_DDC_SDA/GPO70

VGA_DDC_SCL/GPO71

ML_VGA_HPD/GPIO229

VIN2/SDATI_1/GPIO177

VIN3/SDATO_1/GPIO178

VIN4/SLOAD_1/GPIO179

VIN5/SCLK_1/GPIO180

VIN6/GBE_STAT3/GPIO181

VIN7/GBE_LED3/GPIO182

SD_CD#/GPIO75

SD_WP/GPIO76

SD_DATA2/GPIO79 SD_DATA3/GPIO80

GBE_COL GBE_CRS

GBE_MDCK

GBE_MDIO

GBE_RXCLK

GBE_RXD3 GBE_RXD2 GBE_RXD1 GBE_RXD0

GBE_RXCTL/RXDV

GBE_RXERR

GBE_TXCLK

GBE_TXD3 GBE_TXD2 GBE_TXD1 GBE_TXD0

GBE_TXCTL/TXEN

GBE_PHY_PD

GBE_PHY_RST#

GBE_PHY_INTR

SPI_DI/GPIO164 SPI_DO/GPIO163

SPI_CLK/GPIO162

SPI_CS1#/GPIO165

VGA_RED

VGA_GREEN

VGA_BLUE

VGA_HSYNC/GPO68 VGA_VSYNC/GPO69

VGA_DAC_RSET

AUX_VGA_CH_P AUX_VGA_CH_N

AUXCAL

ML_VGA_L0P ML_VGA_L0N ML_VGA_L1P ML_VGA_L1N ML_VGA_L2P ML_VGA_L2N ML_VGA_L3P ML_VGA_L3N

VIN0/GPIO175 VIN1/GPIO176

AL14 AN14 AJ12 AH12 AK13 AM13 AH15 AJ14

GBE_COL

AC4

GBE_CRS

AD3 AD9

GBE_MDIO

W10 AB8 AH7 AF7 AE7 AD7 AG8

GBE_RXERR

AD1 AB7 AF9 AG6 AE8 AD8 AB9 AC2 AA7

GBE_PHY_INTR

W9

V6 V5 V3 T6 V1

L30 L32 M29

M28 N30

M33 N32

K31 V28

V29 U28 T31

T33 T29 T28 R32 R30 P29 P28

C29 N2

M3 L2 N4 P1 P3 M1 M5

NC1

AG16

NC2

AH10

NC3

A28

NC4

G27

NC5

L4

Layout:For SPI Trace length within 4''

SPI_DATAIN SPI_DATAOUT_R SPI_CLK_R SPI_CS#_R SPI_WP#_R

HUDSON_VGA_R

R402 150R1%0402R402 150R1%0402

HUDSON_VGA_G

R401 150R1%0402R401 150R1%0402

HUDSON_VGA_B

R403 150R1%0402R403 150R1%0402

Layout: R within 1''

DAC_RSET AUX_VGA_CH_P

AUX_VGA_CH_N AUXCAL

R383 100R1%0402R383 100R1%0402

ML_VGA_HPD

PIN N2,M3,L2,N4,P1,P3,M1,M5 Use as GPIO182 or configure as one of the following: 10-kΩ 5% pull-up resistor to +3.3V_S5. 10-kΩ 5% pull-down resistor.

R587 0R0402R587 0R0402 R588 0R0402R588 0R0402 R573 0R0402R573 0R0402

R400 715R1%0402R400 715R1%0402

SPI_CLK

SPI_DATAOUT SPI_CLK SPI_CS#

HUDSON_VGA_R 22 HUDSON_VGA_G 22 HUDSON_VGA_B 22

HUDSON_VGA_HSYNC 22 HUDSON_VGA_VSYNC 22

HUDSON_VGA_SDAT 22 HUDSON_VGA_SCLK 22

FCH_VDD11_RUN

DP1_TX0P 10 DP1_TX0N 10 DP1_TX1P 10 DP1_TX1N 10 DP1_TX2P 10 DP1_TX2N 10 DP1_TX3P 10 DP1_TX3N 10

C628

X_C10p50N0402

VCC3_SB VCC3_ROM

D52

B140-13-F_SMA-RH

SPI_CS# SPI_WP#_R

MACH@Reserve 0R serial resisters for SI overshoot/undershoot debug

GBE NOT ENABLED

VCC3_SB

R563 10KR0402R563 10KR0402

1

2

3

4

5

6

7

8

RN8 8P4R-10KR0402RN8 8P4R-10KR0402

SPI ROM & DEBUG HEADER

+

EC57 CD10u16EL5

1 2

C639 C0.1u16Y0402C639 C0.1u16Y0402

R570

R580

1KR0402

R572 0R0402R572 0R0402 R571 X_0R0402R571 X_0R0402

10KR0402

SPI_DATAIN_R SPI_WP# SPI_CLK

SPI_HOLD#

SPI_CS# SPI_HOLD#

VGA HPD

VCC3

R431

R431 X_10KR0402

X_10KR0402

ML_VGA_HPD

R430 10KR0402R430 10KR0402

GBE_MDIO GBE_COL

GBE_CRS GBE_RXERR GBE_PHY_INTR

16M

U38

1

CS#

2

SO/SIO1

3

WP#

4

GND

MX25L1606EM2I-12G-HF

R600 X_0R0402R600 X_0R0402

VCC3_ROM

SPI_DEBUG1

1 2 3 4 5 7 8 9

X_H2X5[10]M-2PITCH_BLACK-RH-2

B

Q59

N-SST3904_SOT23

VCC

HOLD#

SCLK

SI/SIO0

SPI_DATAOUTSPI_DATAIN

6

VCC_DDR

CE

VCC3_ROMVCC3_ROM

8 7 6 5

SPI_CLK

R441

R441 1KR0402

1KR0402

R601

R601 10KR0402

10KR0402

SPI_HOLD#SPI_DATAIN SPI_DATAOUT

SPI_HOLD#_R 17

DP1_HPD_VGA_C 10

R409 100KR0402R409 100KR0402

AUX_VGA_CH_P AUX_VGA_CH_N

R407 100KR0402R407 100KR0402

A A

5

4

3

2

C441 C0.1u10X0402C441 C0.1u10X0402 C442 C0.1u10X0402C442 C0.1u10X0402

VCC3

DP1_AUXP_C 10 DP1_AUXN_C 10

R436

R435

1.8KR0402

Title

Size Document Number Rev

Date: Sheet

HUDSON_VGA_R HUDSON_VGA_G HUDSON_VGA_B

MICRO-START INT'L CO.,LTD.

HUDSON SATA/VGA/SPI/HWM

C

FUSION 1.0

C764 X_C10p50N0402C764 X_C10p50N0402 C763 X_C10p50N0402C763 X_C10p50N0402 C762 X_C10p50N0402C762 X_C10p50N0402

1

18 35Thursday, August 18, 2011

of

5

4

3

2

1

HUDSON POWER&DECOUPLING

Connected directly to the power plane with

U600C

4

HUDSON-2

?

U600C

Part 3 of 5

PCI/GPIO I/O

CLKGEN I/O

PCI EXPRESS

MAIN LINK

GBE LAN

SERIAL ATA

USB

USB SS

POWER

VCC3

L29 220L200mA-300-RHL29 220L200mA-300-RH

CORE S0

3.3V_S5 I/O

VDDCR_11_1 VDDCR_11_2 VDDCR_11_3 VDDCR_11_4 VDDCR_11_5 VDDCR_11_6 VDDCR_11_7 VDDCR_11_8 VDDCR_11_9

VDDAN_11_CLK_1 VDDAN_11_CLK_2 VDDAN_11_CLK_3 VDDAN_11_CLK_4 VDDAN_11_CLK_5 VDDAN_11_CLK_6 VDDAN_11_CLK_7 VDDAN_11_CLK_8

VDDAN_11_PCIE_1 VDDAN_11_PCIE_2 VDDAN_11_PCIE_3 VDDAN_11_PCIE_4 VDDAN_11_PCIE_5 VDDAN_11_PCIE_6 VDDAN_11_PCIE_7 VDDAN_11_PCIE_8

VDDAN_11_SATA_1 VDDAN_11_SATA_4 VDDAN_11_SATA_2 VDDAN_11_SATA_3 VDDAN_11_SATA_5 VDDAN_11_SATA_6 VDDAN_11_SATA_7 VDDAN_11_SATA_8 VDDAN_11_SATA_9

VDDAN_11_SATA_10

VDDIO_33_S_1 VDDIO_33_S_2 VDDIO_33_S_3 VDDIO_33_S_4 VDDIO_33_S_5 VDDIO_33_S_6 VDDIO_33_S_7 VDDIO_33_S_8

VDDXL_33_S

VDDCR_11_S_1 VDDCR_11_S_2

VDDPL_11_SYS_S

VDDAN_33_HWM_S

VDDIO_AZ_S

L31

220L2A-50

VCC3

D D

mach@???if VGA translater is not used, power rails tied to GND. (VDDPL_33_DAC,VDDPL_33_ML,VDDAN_33_DAC)

mach@Internally generated 1.8V supply for the RGB outputs???

C C

+1.1VDUAL

+1.1VDUAL_D3

R482 0R0805R482 0R0805

Hudson-2 design:Tie to GND (preferred) VDDPL_33_SSUSB_S VDDAN_11_SSUSB_S_[5:1] VDDCR_11_SSUSB_S_[4:1]

B B

LAYOUT: ROUTE THE POWER TRACES 15MILS WIDTH AT LEAST PLACE THE DECOUPING CAPS CLOSE TO FCH ASAP PLACE FB<=1" ,CAPS <=0.2"

VCC3

VDDPL_3.3V FCH_VDDPL_33_MLDAC

L32 220L200mA-300-RHL32 220L200mA-300-RH

C501

C2.2u6.3X50402

VCC3_SB

mach@ CRB DNI???

FCH_VDDPL_33_USB_S VDDPL_3.3V_PCIE

L44 220L200mA-300-RHL44 220L200mA-300-RH

C541

C540

A A

C540

C2.2u6.3X50402

C1u6.3X50402-HF

5

+3.3V_FCH_R

R488 0R0805R488 0R0805

FCH_VDD11_RUN

mach@???GbE MAC is not enalbed, power rails tied to GND. (VDDIO_33_GBE_S,VDDIO_GBE_S,VDDCR_11_GBE_S)

VCC3_SB AVDD33_USB

L46

220L2A-50

L42 220L2A-50L42 220L2A-50

FCH_VDD_11_SSUSB_S

C746

C536

C538

C10u6.3X50805

C2.2u6.3X50402

C530

C526

C1u6.3X50402-HF

C22u6.3X50805-RH

VDDPL_3.3V

FCH_VDDPL_33_MLDAC

FCH_VDDAN_33_DAC_R

FCH_VDDPL_33_SSUSB_S

FCH_VDDPL_33_USB_S

VDDPL_3.3V_PCIE VDDPL_3.3V_SATA

L60

220L200mA-300-RH

C545

AVDD11_USB

C548

C10u6.3X50805

C537

C733

C731

C0.1u10X0402

C1u6.3X50402-HF

VCC3

L30 220L200mA-300-RHL30 220L200mA-300-RH

VCC3

L26 220L200mA-300-RHL26 220L200mA-300-RH

C458 X_C2.2u6.3X50402C458 X_C2.2u6.3X50402

C22u6.3X50805-RH

C0.1u10X0402

C735

C1u6.3X50402-HF

VDDPL_11_DAC FCH_VDD11_RUN

C747

C2.2u6.3X50402

60mils

C740

C1u6.3X50402-HF

20mils

C547

C2.2u6.3X50402

C730

C0.1u10X0402

C732

C1u6.3X50402-HF

15mils 15mils

C738

C1u6.3X50402-HF

C736

C0.1u10X0402

C734

C0.1u10X0402

VDDIO_33_PCIGP_1

AB17

102 mA

VDDIO_33_PCIGP_2

AB18

C741

C737

Pankor

C741

C1u6.3X50402-HF

470 mA

C0.1u10X0402

C484

C452

VDDIO_33_PCIGP_3

AE9

VDDIO_33_PCIGP_4

AD10

VDDIO_33_PCIGP_5

AG7

VDDIO_33_PCIGP_6

AC13

VDDIO_33_PCIGP_7

AB12

VDDIO_33_PCIGP_8

AB13

VDDIO_33_PCIGP_9

AB14

VDDIO_33_PCIGP_10

AB16

VDDPL_33_SYS

H24

47 mA

VDDPL_33_DAC

V22

20 mA

VDDPL_33_ML

U22

12 mA

VDDAN_33_DAC

T22

30 mA

VDDPL_33_SSUSB_S

L18

11 mA

VDDPL_33_USB_S

D7

14 mA

VDDPL_33_PCIE

AH29

11 mA

VDDPL_33_SATA

AG28

12 mA

LDO_CAPLDO_CAP

LDO_CAP

M31

VDDPL_11_DAC

V21

7 mA

VDDAN_11_ML_1

Y22

226 mA

VDDAN_11_ML_2

V23

VDDAN_11_ML_3

V24

VDDAN_11_ML_4

V25

VDDIO_33_GBE_S

AB10

VDDCR_11_GBE_S_1

AB11

VDDCR_11_GBE_S_2

AA11

VDDIO_GBE_S_1

AA9

VDDIO_GBE_S_2

AA10

VDDAN_33_USB_S_1

G7

VDDAN_33_USB_S_2

H8

VDDAN_33_USB_S_3

J8

VDDAN_33_USB_S_4

K8

VDDAN_33_USB_S_5

K9

VDDAN_33_USB_S_6

M9

VDDAN_33_USB_S_7

M10

VDDAN_33_USB_S_8

N9

VDDAN_33_USB_S_9

N10

VDDAN_33_USB_S_10

M12

VDDAN_33_USB_S_11

N12

VDDAN_33_USB_S_12

M11

VDDAN_11_USB_S_1

U12

140 mA

VDDAN_11_USB_S_2

U13

VDDCR_11_USB_S_1

T12

42 mA

VDDCR_11_USB_S_2

T13

VDDAN_11_SSUSB_S_1

P16

282 mA

VDDAN_11_SSUSB_S_2

M14

VDDAN_11_SSUSB_S_3

N14

VDDAN_11_SSUSB_S_4

P13

VDDAN_11_SSUSB_S_5

P14

VDDCR_11_SSUSB_S_1

N16

424 mA

VDDCR_11_SSUSB_S_2

N17

VDDCR_11_SSUSB_S_3

P17

VDDCR_11_SSUSB_S_4

M17

C483

C0.1u10X0402

C2.2u6.3X50402

For low current PLL, analog and IO power rails, a minimum trace width of 15 mils must be used, even if the formula above shows that a thinner trace is acceptable. The 15 mil minimum trace width is required to minimize noise coupling; if necessary, thinner trace can be used but not for more than 300 mils of trace length

It is recommended that each power supply or regulator

C2.2u6.3X50402

on the motherboard be located within 3.0" of its respective load to minimize voltage drop and potential noise issues. To calculate the minimum power delivery trace width, use the formula: Vdroop = I*R, where R=ρ*L/A (ρ = resistivity of material, L = trace length, A = trace cross-sectional area). Vdroop must be < 2.5% of the nominal power rail voltage under maximum current conditions

width ≥ 100 mils with area fill under the FCH.

T14

1414 mA

T17 T20 U16 U18 V14 V17 V20 Y17

H26 J25 K24 L22 M22 N21 N22 P22

AB24 Y21 AE25 AD24 AB23 AA22 AF26 AG27

AA21 Y20 AB21 AB22 AC22 AC21 AA20 AA18 AB20 AC19

N18 L19 M18 V12 V13 Y12 Y13 W11

G24

N20 M20

J24

M8

AA4

340 mA

1088 mA

1337 mA

59 mA

5 mA

272 mA

70 mA

5 mA

26 mA

C727

C1u6.3X50402-HF

C460

C2.2u6.3X50402

C476

C1u6.3X50402-HF

C729

C1u6.3X50402-HF

C543

15mils

C1u6.3X50402-HF

20mils

VDDAN_3.3V_HWM

20mils

FCH_VDDAN_33_DAC_R

C493

C494

C0.1u10X0402

C2.2u6.3X50402

VDDPL_3.3V_SATA

C478

C2.2u6.3X50402

FCH_VDD11_RUN

C438

C447

C2.2u6.3X50402

C22u6.3X50805-RH

C754

C1u6.3X50402-HF

C455

C1u6.3X50402-HF

C728

C1u6.3X50402-HF

+3.3VALW_R

20mils

C739

C447

VDDAN_11_CLK

C22u6.3X50805-RH

C448

C22u6.3X50805-RH

C449

C1u6.3X50402-HF

C723

C1u6.3X50402-HF

C544

C477

C1u6.3X50402-HF

C459

C1u6.3X50402-HF

R499 0RR499 0R

C720

C755

C724

C456

C726

VDDXL_3.3V

C1u6.3X50402-HF

VDDCR_1.1V

C1u6.3X50402-HF

VDDPL_1.1V

VDDIO_AZ

R565 0RR565 0R

C599

C597

X_C0.1u10X0402

C1u6.3X50402-HF

VCC3_SB

L37 220L200mA-300-RHL37 220L200mA-300-RH

R381 4.7KR0402R381 4.7KR0402

+12V

FCH_VDD11_RUN

C495

C496

C0.1u10X0402

C2.2u6.3X50402

VDDPL_11_SYS_S Leakage Patch

3

NB_VCC1P1

R390 0R0805R390 0R0805 R397 0R0805R397 0R0805

FCH_VDD11_RUN

C721

C722

C1u6.3X50402-HF

VCC3_SB

FCH_VDDPL_33_SSUSB_S

C521

Pankor

C2.2u6.3X50402

G

S

D

Q35

N-AO3400_SOT23-RH

L55 X_220L200mA-300-RHL55 X_220L200mA-300-RH

Pankor

Power Rails Hudson D3 Hudson D2

NB_VCC1P1

VDDCR_11_[9:1]

VDDAN_11_CLK_[8:1]

VDDAN_11_PCIE_[8:1]

VDDAN_11_SATA_[10:1]

VDDAN_11_ML_[4:1]

VDDPL_11_DAC

VCC3

VDDIO_33_PCIGP_[10:1]

VDDPL_33_SYS

VDDPL_33_DAC

VDDPL_33_ML

VDDPL_33_PCIE

VDDPL_33_SATA

VDDAN_33_DAC

VCC3_SB

VDDIO_33_S_[8:1]

VDDIO_AZ_S

VDDXL_33_S

VDDAN_33_HWM_S

VDDIO_GBE_S[2:1]

VDDIO_33_GBE_S

VDDPL_33_USB_S

VDDAN_33_USB_S_[12:1]

VDDPL_33_SSUSB_S

+1.1VDUAL

VDDCR_11_S_[2:1]

VDDCR_11_GBE_S[2:1]

VDDPL_11_SYS_S

VDDAN_11_USB_S_[2:1]

VDDCR_11_USB_S_[2:1]

VDDAN_11_SSUSB_S_[5:1]

VDDCR_11_SSUSB_S_[4:1]

VCC3_SB

L33 220L200mA-300-RHL33 220L200mA-300-RH

FCH_VDD11_RUN

VDDAN_11_CLK

+1.1VDUAL

VDDPL_11_SYS_S should be tied

C497

to +1.1V_S5 rail if Wake on LAN or USB 3.0 Wake (Hudson-D3 only) is supported; otherwise, it can be tied to +1.1V_S0 rail.

C2.2u6.3X50402

Stuff Q35,L35 for Hudson D3 Stuff L55,L54 for Hudson D2

max

4412 mA

1120 mA 1414 mA

340 mA 1088 mA 1337 mA 226 mA

7 mA

max

102 mA 47 mA 20 mA 12 mA 11 mA 12 mA 30 mA

max

59 mA 26 mA 5 mA 12 mA 145 mA 2 mA 14 mA 470 mA

11 mA 0 mA

max

1293 mA 272 mA 63 mA 70 mA 140 mA 42 mA

282 mA 424 mA

L54 X_220L200mA-300-RHL54 X_220L200mA-300-RH

Pankor

L35 220L200mA-300-RHL35 220L200mA-300-RH

2

319 mA

659 mA

GND

0 mA 0 mA

C506

VDDXL_3.3V

C2.2u6.3X50402

VDDPL_1.1V

C515

C2.2u6.3X50402

U600D

Part 5 of 5

GROUND

C725

C2.2u6.3X50402

C583

C2.2u6.3X50402

C518

C1u6.3X50402-HF

VDDAN_3.3V_HWM

C564

C0.1u10X0402

1

U600D

VSSPL_DAC VSSAN_DAC

VSSANQ_DAC

VSSIO_DAC

VDDCR_1.1V

VSS

T25

VSS

T27

VSS

U6

VSS

U14

VSS

U17

VSS

U20

VSS

U21

VSS

U30

VSS

U32

VSS

V11

VSS

V16

VSS

V18

VSS

W4

VSS

W6

VSS

W25

VSS

W28

VSS

Y14

VSS

Y16

VSS

Y18

VSS

AA6

VSS

AA12

VSS

AA13

VSS

AA14

VSS

AA16

VSS

AA17

VSS

AA25

VSS

AA28

VSS

AA30

VSS

AA32

VSS

AB25

VSS

AC6

VSS

AC18

VSS

AC28

VSS

AD27

VSS

AE6

VSS

AE15

VSS

AE21

VSS

AE28

VSS

AF8

VSS

AF12

VSS

AF16

VSS

AF33

VSS

AG30

VSS

AG32

VSS

AH5

VSS

AH11

VSS

AH18

VSS

AH19

VSS

AH21

VSS

AH23

VSS

AH25

VSS

AH27

VSS

AJ18

VSS

AJ28

VSS

AJ29

VSS

AK21

VSS

AK25

VSS

AL18

VSS

AM21

VSS

AM25

VSS

AN1

VSS

AN18

VSS

AN28

VSS

AN33 T21

L28 K33 N28

EFUSE

R6

19 35Tuesday, August 16, 2011

of

HUDSON-2

VSS

A3

VSS

A33

VSS

B7

VSS

B13

VSS

D9

VSS

D13

VSS

E5

VSS

E12

VSS

E16

VSS

E29

VSS

F7

VSS

F9

VSS

F11

VSS

F13

VSS

F16

VSS

F17

VSS

F19

VSS

F23

VSS

F25

VSS

F29

VSS

G6

VSS

G16

VSS

G32

VSS

H12

VSS

H15

VSS

H29

VSS

J6

VSS

J9

VSS

J10

VSS

J13

VSS

J28

VSS

J32

VSS

K7

VSS

K16

VSS

K27

VSS

K28

VSS

L6

VSS

L12

VSS

L13

VSS

L15

VSS

L16

VSS

L21

VSS

M13

VSS

M16

VSS

M21

VSS

M25

VSS

N6

VSS

N11

VSS

N13

VSS

N23

VSS

N24

VSS

P12

VSS

P18

VSS

P20

VSS

P21

VSS

P31

VSS

P33

VSS

R4

VSS

R11

VSS

R25

VSS

R28

VSS

T11

VSS

T16

VSS

T18

VSSAN_HWM

N8

VSSXL

K25

VSSPL_SYS

H25

?

Layout: VSSPL_SYS;VSSAN_HWM CONNECT TO GND WITH A SEPREATED VIA

+1.1VDUAL

R474 0RR474 0R

VCC3_SB

L47 220L200mA-300-RHL47 220L200mA-300-RH

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

C

Date: Sheet

MICRO-START INT'L CO.,LTD.

HUDSON POWER&DECOUPLING

FUSION 1.0

5

4

3

2

1

FCH REQUIRED STRAPS

D D

C C

RTC_CLK16 PCI_CLK116 PCI_CLK316 PCI_CLK416 LPC_CLK016 LPC_CLK116

FCH_GPIO19917

MACH@All power must be removed after changing S5_PLUS_MODE strap value.

RTCCLK

PULL HIGH

PULL LOW

S5 PLUS MODE DISABLED

DEFAULT

S5 PLUS MODE ENABLED

VCC3_SB

R540

R540 10KR0402

10KR0402

PCI_CLK1

ALLOW PCIE GEN2

DEFAULT

FORCE PCIE GEN1

PCI_CLK3

USE DEBUG STRAPS

IGNORE DEBUG STRAPS

DEFAULT

FCH DEBUG STRAPS

Provided test point access for lab use. FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]

TP25TP25 TP50TP50

B B

TP51TP51 TP53TP53 TP52TP52

PCI_AD27 PCI_AD23

PULL HIGH PULL DOWN

USE PCI PLL

DEFAULT

BYPASS PCI PLL

FCH PCIE EEPROM STRAPS

A A

5

TP22TP22 TP23TP23

AD27 AD26 FCH_25M_X1 AD25 AD24 AD23

PCI_AD26

RESERVED

Normal REFCLK Termination

Inverted REFCLK Termination

PREQ3# PGNT#3

4

AD27 16 AD26 16 AD25 16 AD24 16 AD23 16

PCI_AD25 PCI_AD24

USE DEFAULT

DEFAULT DEFAULT

PCIE STRAPS

USE EEPROM PCIE STRAPS

PREQ3# 16 PGNT#3 16

R546

R546 10KR0402

10KR0402

R545

R545 X_10KR0402

X_10KR0402

DISABLE PCI MEM BOOT

DEFAULT

ENABLE PCI MEM BOOT

VCC3 VCC3_SB VCC3_SBVCC3_SBVCC3

R549

R549 X_10KR0402

X_10KR0402

R548

R548 10KR0402

10KR0402

PCI_CLK4

Reserved

Required setting for intergrated CLOCk MODE

DEFAULT

R448

R448 X_10KR0402

X_10KR0402

R564

R564 10KR0402

10KR0402

TP54TP54 TP56TP56 TP60TP60 TP62TP62 TP61TP61

3

R449

R449 10KR0402

10KR0402

LPC_CLK0

EC ENABLED

EC DISABLED

DEFAULT

FCH ICE DEBUG /JTAG TEST PINS

LPC_CLK1

INTERNAL CLOCK GEN ENABLED

INTERNAL CLOCK GEN DISABLED

FCH_TEST1 OC#0 OC#1 OC#2 OC#3

R444

R444 10KR0402

10KR0402

R445

R445 X_10KR0402

X_10KR0402

DEFAULT

FCH_JTAG_TMS FCH_JTAG_TRST# FCH_JTAG_TDI FCH_JTAG_TCK FCH_JTAG_TDO

R471

R471 X_2.2KR0402

X_2.2KR0402

R472

2.2KR0402

GPIO199

LPC ROM

SPI ROM

DEFAULT

TP24TP24

TP17TP17 TP15TP15

TP55TP55 TP58TP58

VCC3_SB

OC#0 17,30 OC#1 17,30 OC#2 17,30 OC#3 17,30

FCH XOR CHAIN TEST

FCH_25M_X2

FCH_TEST0 FCH_TEST2

R586 X_2.2KR0402R586 X_2.2KR0402

2

FANOUT0 18

FCH_25M_X1 16 FCH_25M_X2 16

FCH_TEST0 17 FCH_TEST2 17

1

2

XOR_TEST

X_H1X2M_BLACK-RH

Title

Size Document Number Rev

B

Date: Sheet

FCH XOR CHAIN OUTPUT

FCH XOR CHAIN REF CLOCK

TEST1 TEST0TEST2

0 1 X Enable test mode

FCH_TEST1 17

MICRO-START INT'L CO.,LTD.

HUDSON STRAPS

FUSION 1.0

Description

XOR_TEST_X1

SHORTING PLUG

X_JUMP1X2A_RED-RH

6.0

20 35Friday, April 29, 2011

1

of

5

4

3

2

1

HDMI CONN,

DP CONOFIGERATION TABLE

INTERFACE

DP

D D

VCC5

C224

C224 C0.1u16Y0402

C0.1u16Y0402

R236 604R1%0402R236 604R1%0402 R233 604R1%0402R233 604R1%0402

R239 604R1%0402R239 604R1%0402 R243 604R1%0402R243 604R1%0402

HDMI_IMPEDANCE

R227 604R1%0402R227 604R1%0402 R231 604R1%0402R231 604R1%0402

R246 604R1%0402R246 604R1%0402 R251 604R1%0402R251 604R1%0402

DS

Q39

G

N-2N7002_SOT23

DP0_TX2P DP0_TX2N

DP0_TX1P DP0_TX1N

DP0_TX0P DP0_TX0N

DP0_TX3P DP0_TX3N

DP0_TX0P10 DP0_TX0N10

DP0_TX1P10 DP0_TX1N10

DP0_TX2P10 DP0_TX2N10

DP0_TX3P10 DP0_TX3N10

VDD_VGA_HDMI

HDMI

R235 X_0RR235 X_0R R232 X_0RR232 X_0R

R238 X_0RR238 X_0R R242 X_0RR242 X_0R

R229 X_0RR229 X_0R R225 X_0RR225 X_0R

R245 X_0RR245 X_0R R250 X_0RR250 X_0R

C454

C192

C0.1u16Y0402

X_C10u10Y0805

DP PORT OF FM1

DP0_TX2P_HDMI DP0_TX2N_HDMI

DP0_TX1P_HDMI DP0_TX1N_HDMI

DP0_TX0P_HDMI DP0_TX0N_HDMI

DP0_TXCP_HDMI DP0_TXCN_HDMI

DP0_HDMI_CLK DP0_HDMI_DATA

DP0_HPD_HDMI

Ch 2Ch 1Ch 0ChannelClock

0123

HDMI_USBB

1

D2+

2

D2 Shield

3

D2-

4

D1+

5

D1 Shield

6

D1-

7

D0+

8

D0 Shield

9

D0-

10

CK+

11

CK Shield

12

CK-

13

CE Remote

14

NC

15

DDC CLK

16

DDC DATA

17

GND

18

+5V HP DET19X4

HDMI_USBX2-RH-3

MEC1

X1

X2

MEC1

X3

X4

C C

U53

R255

2.2KR0402

U53

1 2

4 5

C251

X_C0.1u16Y0402

DP0_HDMI_CLK

DP0_HDMI_DATA

3

B

R257

2.2KR0402

10

NC

9

NC

7

NC

6

NC

X_ESD-PDY050003-2510-RH

8

VCC_DDR

CE

Q40

Q40 N-SST3904_SOT23

N-SST3904_SOT23

R269

R269 1KR0402

1KR0402

DP0_TXCN_HDMI DP0_TXCP_HDMI

DP0_TX1N_HDMI DP0_TX1P_HDMI

DP0_HPD_HDMI_C 10

U52

DP0_TX2P_HDMI DP0_TX2N_HDMI

DP0_TX0P_HDMI DP0_TX0N_HDMI

B B

A A

U52

1 2

4 5

3

DP0_HDMI_CLK

DP0_HDMI_DATA

DP0_AUXP_C10

DP0_AUXN_C10

VDD_VGA_HDMI

DP0_TX2P_HDMI

10

NC

DP0_TX2N_HDMI

9

NC

DP0_TX0P_HDMI

7

NC

DP0_TX0N_HDMI

6

NC

X_ESD-PDY050003-2510-RH

8

VCC5

5

261

C231 C0.1u16Y0402C231 C0.1u16Y0402

DP0_AUXP_C

DP0_AUXN_C

R256 10KR0402R256 10KR0402 C206 C0.1u16Y0402C206 C0.1u16Y0402

C237 X_C0.1u16Y0402C237 X_C0.1u16Y0402

DP0_HPD_HDMI

4

U21

X_CMD ( CM1293A-04SO )

3

VCC_DDR

U19 PCA9509DP_TSSOP8-RHU19 PCA9509DP_TSSOP8-RH

2

A1

3

A2

DP0_HDMI_EN

VDD_VGA_HDMI

C227 C0.1u16Y0402C227 C0.1u16Y0402

1

8

7

B1

VCCA

VCCB

6

B2

GND4EN

5

DP0_TXCN_HDMI DP0_TXCP_HDMI

DP0_TX1N_HDMI DP0_TX1P_HDMI

DP0_HPD_HDMI

VDD_VGA_HDMI VDD_VGA_HDMI

R268 10KR0402R268 10KR0402

R183

R183 100KR0402

100KR0402

DP0_TX2P DP0_TX0P_HDMI DP0_TX1N_HDMI DP0_TX2N DP0_TX0N_HDMI

DP0_TX0P DP0_TX2P_HDMI DP0_TX0N DP0_TX2N_HDMI

L12-9008054-M09/L12-9008044-T34/L12-9008054-M09

L12

3

2

4

1

CMC-L12-9008104-RH

L13

3

2

4

1

CMC-L12-9008104-RH

DP0_TX0P_HDMI DP0_TX1N_HDMI

R228

X_180R0402-RH

DP0_TX0N_HDMI

DP0_TX2P_HDMI

DP0_TX2N_HDMI

X_180R0402-RH

R234

X_180R0402-RH

DP0_TX1N DP0_TX1P

DP0_TX3N DP0_TX3P

L14

3 4

CMC-L12-9008104-RH

L15

3 4

CMC-L12-9008104-RH

DP0_TX1P_HDMI

DP0_TXCN_HDMI

DP0_TXCP_HDMI

2

DP0_TX1P_HDMI

1

DP0_TXCN_HDMI

2

DP0_TXCP_HDMI

1

R241

X_180R0402-RH

R249

X_180R0402-RH

VCC5 VCC5

C222

X_C0.1u16Y0402

C271

X_C0.1u16Y0402

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

C

Date: Sheet

5

4

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

SWITCH&DP/HDMI CONN.

FUSION 1.0

1

21 35Friday, April 29, 2011

of

8

7

6

5

4

3

2

1

VGA CONNECTOR

D D

R932-R934 CLOSE TO CRT CONNECTOR, THE TRACE IMPEDANCE BETWEEN NB AND 150OHM RESISTOR SHOULD BE 37OHM+/-15%, THE TRACE IMPEDANCE BETWEEN THE 2 150OHM

RESISTOR SHOULD BE 50 OHM +/-15%, THE IMPEDANCE BETWEEN THE 2ND RESISTOR

TO THE CONNECTOR SHOULD BE 75OHM+/-15%

R258 4.7KR0402R258 4.7KR0402

+12V

G

S

D

VCC5

C C

D

Q34

N-APM2308AC-TRL_SOT23-3-RH

FS1

1 2

F-MICROSMD110

VDD_VGA_HDMI

C201

C10u10Y0805

C207

C0.1u16Y0402

HUDSON_VGA_R18

HUDSON_VGA_G18

mach@The value of L,C refer to demo board,maybe adjusted for test

R276

R276 150R1%0402

150R1%0402

R273

R273 150R1%0402

150R1%0402

HUDSON_VGA_B18

R271

R281

R279

4.7KR0402

HUDSON_VGA_SDAT18

HUDSON_VGA_SCLK18

R278R278

R282R282

DDCDATA_5V

DDCCLK_5V

R271 150R1%0402

150R1%0402

Layout:PLACE L 90 DEGREE FROM EACH OTHER

L20

10n300mA

C276

C1p50N0402-RH

L19

10n300mA

C264

C1p50N0402-RH

L16

10n300mA

C258

C1p50N0402-RH

VGA_R

VGA_G

VGA_B

L210RL21

0R

C275

X_C3.3p50N0402

L180RL18

0R

C267

X_C3.3p50N0402

L170RL17

0R

C257

X_C3.3p50N0402

CLOSE TO VGA Connector

C274

C1p50N0402-RH

C266

C1p50N0402-RH

C256

C1p50N0402-RH

VDD_VGA_HDMI VDD_VGA_HDMI VCC5 VCC5

VCC5

C269 C0.1u16Y0402C269 C0.1u16Y0402

D21

BAV99-7-F_SOT23-LF

Y

VCC5

C262 C0.1u16Y0402C262 C0.1u16Y0402

D20

BAV99-7-F_SOT23-LF

Y

VCC5

C249 C0.1u16Y0402C249 C0.1u16Y0402

D19

BAV99-7-F_SOT23-LF

Y

X

Z

X

Z

X

Z

VDD_VGA_HDMI

PLACE ESD PROTECTION DIODES

1. CLOSE TO CONNECTOR PINS

2. DIRECTLY ON SIGNAL TRACES

3. +5V & GND TRACE TO DIODE SHOULDBE LESS THAN 100MILS AND 20MILS WIDE

4. THE ESD DIODE SHOULD BE THE FIRST DEVICE FROM CONNECTOR

BAV99

Y

D24

C284

Z

X

C0.1u16Y0402

DDCCLK_CONN VSYNC_CONN HSYNC_CONN DDCDATA_CONN

C241

C0.1u16Y0402

3

Y

D18

BAV99

Z

X

C250

X_C100P50N0402

Y

D23

C0.1u16Y0402

4

D23

BAV99

Z

X

C297

VCC5

C228 C0.1u16Y0402C228 C0.1u16Y0402

53

1

HUDSON_VGA_VSYNC18

B B

HUDSON_VGA_HSYNC18

A A

8

2

U18

VCC5

53

1 2

U18

C239 C0.1u16Y0402C239 C0.1u16Y0402

U20

AHCT1G126GV_SOT23-5-RH

7

4

VSYNC_5V

C219

C219 X_C100P50N0402

X_C100P50N0402

HSYNC_5V

C234

C234 X_C100P50N0402

X_C100P50N0402

6

DDCCLK_5V

R283 33R0402R283 33R0402

VSYNC_5V

R263 27R0402R263 27R0402

HSYNC_5V

R264 27R0402R264 27R0402

DDCDATA_5V

R277 33R0402R277 33R0402

5

C279

Y

D17

BAV99

C283

D17

C218

Z

C229

X

C0.1u16Y0402

15 14 13 12 11

VGA

DSUB-VGAF_BLUE-RH-2

DSUB-VGAF_BLUE-RH-2 5 10 4 9 3 8 2 7 1 6

C208

C208 C0.1u16Y0402

C0.1u16Y0402

BLUE_CONN GREEN_CONN RED_CONN

16 17

X_C100P50N0402

X_C18P50N0402

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

C

Date: Sheet

2

MICRO-START INT'L CO.,LTD.

TRAVIS & VGA CONN.

FUSION 1.0

22 35Friday, April 29, 2011

1

of

5

iSATA CONNECTOR

Multiple eSATA function

SATA_TX0+

C586 C0.01U16X0402C586 C0.01U16X0402

SATA_TX0+18

SATA_TX0-

SATA_TX0-18

SATA_RX0-

SATA_RX0-18

SATA_RX0+ ST_RX0

SATA_RX0+18

D D

SATA_TX1+

SATA_TX1+18

SATA_TX1-

SATA_TX1-18

SATA_RX1-18

SATA_RX1+

SATA_RX1+18 SATA_RX3+18

1 2

C590 C0.01U16X0402C590 C0.01U16X0402

1 2

C604 C0.01U16X0402C604 C0.01U16X0402

1 2

C609 C0.01U16X0402C609 C0.01U16X0402

1 2

C510 C0.01U16X0402C510 C0.01U16X0402

1 2

C516 C0.01U16X0402C516 C0.01U16X0402

1 2

C519 C0.01U16X0402C519 C0.01U16X0402

1 2

C522 C0.01U16X0402C522 C0.01U16X0402

1 2

Layout:For Gen 3.0,trace length within 3''

SATA1

GND

9

GND

TX+

1 2

TX-

ST_TX#0 ST_RX#0

ST_TX1 ST_TX#1

ST_RX#1SATA_RX1-

TX-

3

GND GND

4

RX-

5 6 7

GND

8

SATA7PM_RED-P

SATA2

GND

9

GND

1 2

TX-

3

GND GND

4

RX-

5 6 7

GND

8

SATA7PM_RED-P

RX+

TX+

RX+

eSATA Conn. WO re-driver

Layout:For onboard eSATA conn. without redriver IC,trace length within 6''

eSATA

ST_TX4 ST_TX#4

ST_RX#4 ST_RX4

ST_TX4 ST_TX#4

ST_RX#4 ST_RX4

eSATA

GND

9

GND

TX+

1 2

TX-

3

GND GND

4

RX-

5

RX+

6 7

GND

8

SATA7PM_BLACK-P

C C

C527 C0.01U16X0402C527 C0.01U16X0402

SATA_TX4+18

SATA_TX4-18 SATA_RX4-18

SATA_RX4+18

B B

A A

C524 C0.01U16X0402C524 C0.01U16X0402 C517 C0.01U16X0402C517 C0.01U16X0402

C512 C0.01U16X0402C512 C0.01U16X0402

ST_TX4 ST_TX#4

ST_RX#4 ST_RX4

5

1 2 1 2

U33

1 2

4 5

3

10

NC

9

NC

7

NC

6

NC

X_ESD-PDY050003-2510-RH

8

4

SATA3

9

GND

SATA_TX2+

C588 C0.01U16X0402C588 C0.01U16X0402

SATA_TX2+18 SATA_TX2-18

SATA_RX2-18 SATA_RX2+18

SATA_TX3+18

SATA_RX3-18

SATA_TX2SATA_RX2-

SATA_RX2+

SATA_TX3+ SATA_TX3-

SATA_TX3-18

SATA_RX3SATA_RX3+

1 2

C592 C0.01U16X0402C592 C0.01U16X0402

1 2

C601 C0.01U16X0402C601 C0.01U16X0402

1 2

C608 C0.01U16X0402C608 C0.01U16X0402

1 2

C507 C0.01U16X0402C507 C0.01U16X0402

1 2

C513 C0.01U16X0402C513 C0.01U16X0402

1 2

C520 C0.01U16X0402C520 C0.01U16X0402

1 2

C523 C0.01U16X0402C523 C0.01U16X0402

1 2

ST_TX2ST_TX0 ST_TX#2

ST_RX#2 ST_RX2

ST_TX3 ST_TX#3

ST_RX#3 ST_RX3ST_RX1

1 2 3

GND GND

4 5 6 7 8

SATA7PM_RED-P

SATA4

9

GND

1 2 3

GND GND

4 5 6 7 8

SATA7PM_RED-P

3

PS2 KEYBOARD & MOUSE CONNECTOR

GND

TX+

TX-

RX-

RX+

GND

TX+

TX-

RX-

RX+

GND

SVCC2

1 2

3 4

5 6

MSDATA

MSDATA25

MSCLK

MSCLK25

KBDATA

KBDATA25

KBCLK

KBCLK25

RN1

RN1 8P4R-2.2KR

8P4R-2.2KR

7 8

R57 33R0402R57 33R0402 R71 33R0402R71 33R0402

R43 33R0402R43 33R0402 R67 33R0402R67 33R0402

2

KBCLK_L MSCLK_L

MSDATA_R

FB2 300L250mA-380_0402-RHFB2 300L250mA-380_0402-RH

MSCLK_R

FB4 300L250mA-380_0402-RHFB4 300L250mA-380_0402-RH

KBDATA_R

FB1 300L250mA-380_0402-RHFB1 300L250mA-380_0402-RH

KBCLK_R

FB3 300L250mA-380_0402-RHFB3 300L250mA-380_0402-RH

SVCC2

52

6 1

C56 X_C0.1u16Y0402C56 X_C0.1u16Y0402

U27

KBDATA_L

4

MSDATA_L

3

CMD ( CM1293A-04SO )

C22

C0.1u16Y0402

MSDATA_L MSCLK_L

KBDATA_L KBCLK_L

C60

C60 C180P50N0402

C180P50N0402

C40

C40 C180P50N0402

C180P50N0402

C67

C67 C180P50N0402

C180P50N0402

C52

C52 C180P50N0402

C180P50N0402

R35

R35 X_1KR1%0402

X_1KR1%0402

7

8 11 12

1

2

5

6

131415

1

16

17

10

KB_MS

9

MS

CONN-MiniDIN2X12P-RH

4

3

KB

PWM FAN CONTROL

VCC3

VCC5

VCC3

R669

R40

D

G

S

VCC5

R396

4.7KR0402

D

Q55

G

N-2N7002_SOT23

S

R40

4.7KR0402

4.7KR0402 X_4.7KR0402

X_4.7KR0402

Q60

Q60 N-2N7002_SOT23

N-2N7002_SOT23

VCC3

R329

X_4.7KR0402

G

C365

R16 100R0402R16 100R0402

+12V

DS

Q80

R332 100R0402R332 100R0402

R372

R372 0R1206

0R1206

VCC5

R48

CPUFAN_PWM25

CPUFAN_PWM

VCC5

R331

4.7KR0402

SYSFAN_PWM25

SYSFAN_PWM

4.7KR0402

VCC5

R668

4.7KR0402

D

4.7KR0402

D

Q52

G

N-2N7002_SOT23

S

VCC5

R395

4.7KR0402

D

Q48

G

S

N-2N7002_SOT23

+12V

R617

U63A

X_8.2KR0402

3

+

PWRFAN_PWM25

R414 X_15K/4R414 X_15K/4

+

2

-

4 8

X_8.2KR0402

1

X_LM358D_SOIC8

R419 X_0R0805R419 X_0R0805

R420 X_10KR1%0402R420 X_10KR1%0402

R416

X_2KR1%0402

+12V

U63B

5

+

7

6

-

X_LM358D_SOIC8

4 8

4

X_2KR1%0402

3

X_C0.1u16Y0402

X_P-P06P03LDG_TO252-RH

VCC5

CPUFAN_PWM1 SYSFAN_PWM1

2

D1

X_1N4148W-FD1X_1N4148W-F

VCC3

D26

D25

X_1N4148W-F

C12 X_C0.1u16Y0402C12 X_C0.1u16Y0402 C352 X_C0.1u16Y0402C352 X_C0.1u16Y0402

+12V

D2

D4 1N4148W-F_SOD123-RHD4 1N4148W-F_SOD123-RH R39 4.7KR0402R39 4.7KR0402

CPUFAN_PWM1

X_1N4148W-FD2X_1N4148W-F

+

12

EC2

EC2 CD100u16EL5-RH

CD100u16EL5-RH

SYSTEM FAN

+12V

D27 1N4148W-F_SOD123-RHD27 1N4148W-F_SOD123-RH R342 4.7KR0402R342 4.7KR0402

SYSFAN_PWM1

X_1N4148W-F

C356

C356 C0.1u16Y0402

C0.1u16Y0402

+

12

EC30

EC30 CD100u16EL5-RH

CD100u16EL5-RH

+12V

D45 1N4148W-F_SOD123-RHD45 1N4148W-F_SOD123-RH R506 4.7KR0402R506 4.7KR0402

+

12

D70

EC50

EC50 CD100u16EL5-RH

CD100u16EL5-RH

X_1N4148W-F

CPU FAN

C39

C39 C0.1u16Y0402

C0.1u16Y0402

POWER FAN

0 to +3 V amplitude fan

4 3 2 1

R524 100R0402R524 100R0402

R502

R502 10KR0402

10KR0402

1

tachometer input.

CPUFAN_TAC 25

R37

R37 10KR0402

10KR0402

SYSFAN_TAC 25

R344

R344 10KR0402

10KR0402

PWRFAN_TAC 25

23 35Wednesday, August 17, 2011

of

R38 27KR0402R38 27KR0402

CPU_FAN

BH1X4B_brown-RH

R343 27KR0402R343 27KR0402

SYS_FAN

BH1X4B_white-RH

R501 27KR0402R501 27KR0402

PWR_FAN

3 2 1

BH1X3B-FR_WHITE-RH

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

C

Date: Sheet

MICRO-START INT'L CO.,LTD.

SATA//eSATA/PS2/ FAN

FUSION 1.0

5

RTL8111E/8105E

LAN_EESK/LED1_R

R6660RR666 0R

VDD33

VDD10

R345 2.49KST/4R345 2.49KST/4

D D

VDD10

VDD33

C C

U901

LAN

RTL8105E

RTL8105E-VC-GR

R507 place close to pin 46 as possible

ROUTE 100 OHM DIFF

TR_D0+ TR_D0-

TR_D1+ TR_D1-

TR_D2+ TR_D2-

TR_D3+ TR_D3-

RTL8111E-VB-GR

1 2 3 4 5 6 7 8

9 10 11 12

U28

MDIP0 MDIN0 AVDD10 MDIP1 MDIN1 AVDD10(NC) MDIP2(NC) MDIN2(NC) AVDD10(NC) MDIP3(NC) MDIN3(NC) AVDD33(NC)

47

AVDD3348AVDD33

DVDD10

13

VDD10

CLK_LAN2

RSET

46

45

RSET

AVDD10

SMBCLK(NC)14SMBDATA(NC)15CLKREQB

16

LAN_SDATA

CLK_LANI

LAN_LED0_LINK100#

39

40

41

43

42

LED0

AVDD33

DVDD33

CKXTAL244CKXTAL1

DVDD10(NC)

HSIP17HSIN18REFCLK_P19REFCLK_N20EVDD1021HSOP22HSON

EVDD10

LAN_EESK/LED1

LAN_GPO

37

38

GPO/SMBALERT

24

23

3.3v Power on rise time : 1~100ms.

MAX: 163mA

VCC3_WAKE

L24 X_220L2A-50-RHL24 X_220L2A-50-RH

CP4CP4

B B

width>60mil

REGOUT_VDD10

CH-4.7u0.85A170mS-HF

CHOKE12 close to Pin 36 within 0.2''

C763,C868 close to CHOKE12 within 0.2''

A A

C342

CHOKE8

1 2

8105E POWER Consumption

10 M Idle/TxRx

100 M Idle/TxRx

S0 ALDPS Giga Idle/TxRx

27 39 42 47 48 12

C529

X_C22u6.3X1206

C10u6.3X50805

C381

C351

C0.1u16Y0402

C10u6.3X50805

5

C345

C361

C354

C743

C0.1u16Y0402

C360

C0.1u16Y0402

3.3V mW

14/75

43/66

3.2

46/248

142/218

C359

C0.1u16Y0402

29 45 41 6 9313

C744

C0.1u16Y0402

11

C364

C368

C0.1u16Y0402

Place close to pin 31,37,40

LAN_LED0_LINK100# LAN_EESK/LED1 LAN_EEDO/LED3

LED1/EESK

GND

C0.1u16Y0402

36

REGOUT

35

VDDREG

34

VDDREG

33

ENSWREG

LED3/EEDO

LANWAKEB

ISOLATEB

LAN_RXN LAN_RXP

8105E: unstuff

8111E: stuff

C380

C0.1u16Y0402

LAN_EEDI

32

EEDI

LAN_EEDO/LED3

31

LAN_EECS

30

EECS

29

DVDD10

28 27

DVDD33

LAN_ISOLATE#

26

PCIE_RST#

25

PERSTB

49

GND

Pin49: 9 via from top layer to GND layer and make the via at the center of IC.

C384 C0.1u10X0402C384 C0.1u10X0402 C383 C0.1u10X0402C383 C0.1u10X0402

VDD33

C370

C358

C366

C0.1u16Y0402

8111E POWER Consumption

10 M Idle/TxRx

100 M Idle/TxRx

ALDPS

4

C353 X_C1000P50X0402C353 X_C1000P50X0402 C362 X_C1000P50X0402C362 X_C1000P50X0402 C367 X_C1000P50X0402C367 X_C1000P50X0402

REGOUT_VDD10

VDD33 VDD33

R347 10KR0402R347 10KR0402 R667 0RR667 0R R350 10KR0402R350 10KR0402

VDD10 VDD33

C378

X_C680p50N0402

PE_LAN_CLK# PE_LAN_CLK

VDD10

8105E: unstuff

8111E: stuff

C0.1u16Y0402

4

AVDD33_REG

PE_WAKE# 17,25,31,32

LAN_RXC_N 8 LAN_RXC_P 8 PE_LAN_CLK# 16 PE_LAN_CLK 16 LAN_TXC_N 8 LAN_TXC_P 8

VDD33

VDD10

CLK_LAN2

CLK_LANI

VDD33

ENSWREG:3.3V-Enable SW

LAN_EEDO/LED3_R

MACH@Reserve PU at FCH side

PCIE_RST# 16,31,32

width>40mil WITHIN 0.2'' OF PIN 34,35

C346

C4.7u6.3X5

WITHIN 0.2'' OF PIN21

R361 0RR361 0R

C385

3.3V mW

12/66

31/444102/145

135/163 452/538

40/218

13

C375

C0.1u16Y0402

C1u10X7R

VDD33

EVDD10

C382

R330

R330 X_1MR

X_1MR

C0.1u16Y0402

1 2

LAN_ISOLATE#

3

C341 C27p50N0402-RHC341 C27p50N0402-RH

Y1

Y1 25MHZ18P_D-4

25MHZ18P_D-4

C347 C27p50N0402-RHC347 C27p50N0402-RH

VCC3

R359

R359 1KR0402

1KR0402

R358

R358 15K/4

15K/4

N58-22F0431-U30(10/100)

3

2

USE Efuse/BIOS PATCH WITHOUT ASF FUNCTION

LAN_EECS LAN_EESK/LED1_R LAN_EEDI LAN_EEDO/LED3_R

U60

TR_D2+ TR_D2-

TR_D3+ TR_D3-

U60

1 2

4 5

3

LED3_ACT LED0_LINK100# LED1_LINK1000#

The center-tap of transformer must be tied together

and connect to GND with 0.01 u cap.

R291

R291 0R0402

0R0402

8111E: stuff

8105E: unstuff

N58-22F0851-F02/N58-22F0851-I60 30u

N58-22F0951-I60

Link

Active

1000 Green

100

10

19

20

21

22

Green

2

TR_D2+

10

NC

TR_D2-

9

NC

TR_D3+

7

NC

TR_D3-

6

NC

X_ESD-PDY050003-2510-RH

8

12

D65

D64

ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH

8111E: unstuff

8105E: stuff

R428 X_0R0402R428 X_0R0402

N58-22F0431-U30

Link

Yellow Blinking

Active

Orange

100

Green

10

None

19

Orange

20

21

Yellow

22

12

C320

C320 X_C0.01U16X0402

X_C0.01U16X0402

1 2

8111E: unstuff

8105E: stuff

10/100-LanGiga-Lan

Green

VDD33

D66

LAN_LED0_LINK100#

LAN_EESK/LED1_R

VDD33

Yellow Blinking

None

Yellow

1

U49

1

CS

VCC

2

SK

DC

3

DI

ORG

4

DO

GND

X_HT93LC46-8 SOP-A-RH

AVL PN:M33-93C46F3-S10

R341 1KR0402R341 1KR0402

R433 X_1KR0402R433 X_1KR0402 R360 10KR0402R360 10KR0402

8111E: stuff

8105E: unstuff

LAN_CONN_TCT LAN-CONN_RCT/GND

LAN_GPO

LAN_SDATA

TR_D0+ TR_D0-

TR_D1+ TR_D1-

VDD33_R LAN_CONN_TCT LAN-CONN_RCT/GND

8111E: 220R

8105E: 510R

R348 220RR348 220R

R616 75RR616 75R

8111E: 220R

8105E: unstuff

R340 220RR340 220R

R425 X_510RR425 X_510R

8111E: unstuff

8105E: 510R

only support LED0+LED1/LED1+LED3 dual color LED combinations when using EEPROM

Title

LAN-RTL8111E/8105E.

Size Document Number Rev

C

Date: Sheet

VDD33

8 7 6 5

1 2

4 5

TR_D3TR_D2TR_D1TR_D0-

TR_D3+ TR_D2+ TR_D1+ TR_D0+

FUSION 1.0

C372

X_C0.1u16Y0402

GPO: 1: Link up 0: Link down

U61

3

TP11TP11

TP12TP12

TP16TP16

TP13TP13 TP14TP14

TR_D0+

10

NC

TR_D0-

9

NC

TR_D1+

7

NC

TR_D1-

6

NC

X_ESD-PDY050003-2510-RH

8

12

D67

D68

4-

TD-

3-

2-

1-

PWR

GND

4+

TD+

3+

2+

1+

LED0_LINK100#

LED1_LINK1000#

1

169

12

D69

VDD33

20 22

VDD10

VDD33

PCIE_RST# PE_LAN_CLK

PE_LAN_CLK#

12

ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH

LED3_ACTLAN_EEDO/LED3_R

9 10 11 12 13 14 15 16 17 18

MICRO-START INT'L CO.,LTD.

R477

R477 75R

75R

VDD33_R

21

USB_LANB

USB_LANB RJ45_USBX2_TX-RH-3

RJ45_USBX2_TX-RH-3

19

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5

SERIRQ16

IO_PME#17

R166 4.7KR0402R166 4.7KR0402

C147

C4.7u6.3X5

R220 4.7KR0402R220 4.7KR0402

R164 0R0402R164 0R0402 R165 0R0402R165 0R0402

R167 0R0402R167 0R0402

D13 1N4148WD13 1N4148W

C127 X_C1u10XC127 X_C1u10X

PSOUT# IO_RSMRST#

SIO_48M_CLK PCI_CLK_SIO

A_RST#

A_RST# PCI_CLK_SIO SERIRQ LPC_DRQ#0 LPC_FRAME# IO_PME# SIO_48M_CLK LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

SIO_AVCC SIO_VREF SIO_HWM_AGND

THERMDA_CPU EXT_SYS_TEMP VR_TEMP_DA

VIN_VDIMM VIN_CPUCORE

SIO_TSI_CLK SIO_TSI_DAT

SKTOCC# CASE_OPEN0 CASE_OPEN1

SIO_SMI#

VBAT_IO

U9

26

LRESET#

17

PCICLK

19

SERIRQ

18

LDRQ#

25

LFRAME#

OD

65

PME#

15

IOCLK

23

LAD[0]

22

LAD[1]

21

LAD[2]

20

LAD[3]

116

CTSB#/GP17/VIDI7

117

DSRB#/GP16/VIDI6

118

RTSB#/GP15/VIDI5

119

DTRB#/GP14/VIDI4

120

SINB/GP13/VIDI3

121

SOUTB/GP12/VIDI2

122

DCDB#/GP11/VIDI1

123

RIB#/GTP10/VIDI0

106

AVCC(3.3V)

108

VREF

112

CPUD-(AGND)

110

CPU_TIN

111

SYS_TIN

109

AUXTIN/VIN3

103

VIN2

104

VLDT/VIN1

105

VDIMM/VIN0

107

CPUVCORE

114

VTT

113

TSI_CLK/GPA0

115

TSI_DAT/PECI

124

CPU_FANIN

125

CPU_FANOUT

126

SYS_FANIN

127

SYS_FANOUT

3

AUX_FANIN0/INDEX#

98

AUX_FANOUT0/GP27

102

SKTOCC#/GP90

100

CASEOPEN0#

72

CASEOPEN1#

78

RSTOUT1#/GP36

79

RSTOUT0#/GP35

37

RSTCONO#/GP47

OD

128

SMI#/OVT#

82

PWROK/GP32

83

RESETCON#/OVT#/GP31

84

SLP_S5#/GP30

64

SLP_S3#/GP51

OD

60

PSOUT#/GP54

61

PSIN#/GP53

63

PSON#/GP52/AMD_PSON#

80

ATXPGD/GP34

OD

101

RSMRST#/GP91

88

SLP_SUS_FETVIDO5/GP75

89

SLP_SUS#/VIDO4/GP74

90

SUSWARN#/VIDO3/GP73

91

SUSACK#VIDO2/GP72

92

5VDUALVIDO1/GP71

93

SUSWARN#/VIDO0/GP70

99

VBAT

94

VSS

16

VSS

NCT6776F-RH

NCT6776F

AUXFANIN1/GP01/MOA#

AUXFANIN2/GP02/DSA#

TRAK0#/PRIMARY_HD#

DSKCHG#/SECONDARY_HD#

CIRRX/GP24/IRRX1

GP25/CIRTX1/IRTX1/(AMDPWR_EN)

GRN_LED/GP44/BUSY

YLW_LED/GP45/PE

CIRRXWB/SLCT/GP46

MSDA/SDA/GP42/SLIN#/BEEP

MSCL/SCL/GP41/INIT# VID_RST#/GP57/ERR#

ALERTI#/SLP_SUS#/GP56/AFD#

ALERTO#/GP55/CIRTX3/STB#

SLP_S5#_LATCH/GP40/(TEST MODE1)

(LPT_EN)/SOUTA/GP85

(24M_48M_SEL)/DTRA#/GP83

(2E_4E_SEL)/RTSA#/GP82

VCLKO/SUSWARN_5VDUAL

3VSBSW#/(TESTMODE2)

VRM_EN/SUSWARN

SLP_SUS_FET/RSTOUT2#/GP37

DEEP_S5/3VSBSW

VLDT_EN/VIDO7/GP77

VCORE_EN/VIDO6/GP76

CPUPWRGD/GP33

C122 15p50N0402C122 15p50N0402 C120 C22p50N0402C120 C22p50N0402

C43 X_C0.1u16Y0402C43 X_C0.1u16Y0402

A_RST#16

D D

VCC3

L7 600L500mA-300_0805L7 600L500mA-300_0805

C146

SIO_HWM_AGND

SHORT PIN 86,104

SIO_VLDT_EN VIN_VDDP/VDDR

0 to +3 V amplitude fan tachometer input.

C C

Fan speed control: CPU_FAN,SYS FAN use PWM duty-cycle signal ; PWR_FAN use DC mode

CASEOPEN NOT USED

T=180 ms RSMRST# refers to V3A only when first plug in power cord. T=120 ms One bit to enable 3.3VSB(pin 97) monitor. Powered by VRTC,RSMRST# refers to V3A

VBAT

VCC3_SB

R158 1KR0402R158 1KR0402

16 mil

R3 1KR1%0402R3 1KR1%0402 R4 4.7KR0402R4 4.7KR0402

B B

PCI_CLK_SIO16

LPC_FRAME#16 SIO_48M_CLK16

C138

C0.1u10X0402

C10u6.3X50805

L8

600L500mA-300_0805

R176 0R0402R176 0R0402

APU_SIC10 APU_SID10

CPUFAN_TAC23

CPUFAN_PWM23

SYSFAN_TAC23

SYSFAN_PWM23

PWRFAN_TAC23

PWRFAN_PWM23

SIO_VDUAL_EN26

LPC_SMI#17

FP_RST#17,27,33 SLP_S5#17,26,27,30 SLP_S3#17,26,27

PSOUT#17

ATX_PSON#33

ATX_PWROK7,26,27,33

IO_RSMRST#17

LPC_DRQ#016

LPC_AD[3..0]16

SIO_AVCC

R7 10KR0402R7 10KR0402 R153 1KR0402R153 1KR0402 R156 1KR0402R156 1KR0402

PSIN#33

SUPER I/O STRAPPING RESISTOR

FCH HAS INTE-GRATED PU RESISTER

VCC3_SB

R79 X_4.7KR0402R79 X_4.7KR0402

A A

VCC3

R124 X_10KR0402R124 X_10KR0402 R125 X_10KR0402R125 X_10KR0402 R168 X_10KR0402R168 X_10KR0402

50% fan output duty by default while power-on @NCT6776F

IO_PME#

A20GATE KBRST# LPC_SMI#

5

VCC3

VCC3_ALW

R108 1KR0402R108 1KR0402 R109 X_1KR0402R109 X_1KR0402

R99 1KR0402R99 1KR0402 R114 X_1KR0402R114 X_1KR0402

R93 1KR0402R93 1KR0402 R59 1KR0402R59 1KR0402

R98 1KR0402R98 1KR0402

R90 1KR0402R90 1KR0402 R144 X_1KR0402R144 X_1KR0402

R145 1KR0402R145 1KR0402

RTSA#

DTRA#

SOUTA

TEST_MODE1

TEST_MODE2

DSW_ROUTING

AMDPWR_EN

MACH@???

4

DRVDEN0/GP00

STEP#/HD_LED#

LED_A/GP60/PD0 LED_B/GP61/PD1 LED_C/GP62/PD2 LED_D/GP63/PD3 LED_E/GP64/PD4 LED_F/GP65/PD5 LED_G/GP66/PD6

DGH#/GP67/PD7

DGL#/GP43/ACK#

GP92/SDA/MSDA

GP93/SCL/MSCL

VDIOO/SUSACK#

VDIOI(DSW_EN)

PCHVSB_DETECT

Power On Strapping Options

2

R155 4.7KR0402R155 4.7KR0402

4

R163 4.7KR0402R163 4.7KR0402

5 6

DIR#/CIRTX2

7 8

WD#/GP03

9

WE#/GP04

10 11

WP#/GP05

12

RDATA#/GP06

13

HEAD#/GP07

14

SIO_GP24

95 96

50 49 48 47 45 44 43 42 41 40 39 38

51 52 53 54 55 62

36

RIA#/GP87

35

DCDA#/GP86

34 33

SINA/GP84

32 31 30

DSRA#/GP81

29

CTSA#/GP80

27

GA20M

28

KBRST#

59

KDAT/GP20

58

KCLK/GP21

57

MDAT/GP22

56

MCLK/GP23

76 75

66 67 68

VCLK/5VDUAL

69 71 74 77 73

BKFD_CUT

70 97

86 87 81

24

3VCC

1

3VCC

85

3VSB

46

3VSB

Symbol

GPIO / RTSA# (2E_4E_SEL) GP64 / DTRA# (24_48_SEL)

(LPT_EN) TEST_MODE1

TEST_MODE2 71 10Eable TEST MODE

DSW_ROUTING AMDPWR_EN

4

R230 4.7KR0402R230 4.7KR0402

AMDPWR_EN

CHASSIS_ID2 CHASSIS_ID1 COM_GPIO2

MB_ID1 MB_ID0

USB_EN

SIO_WAKE

TEST_MODE1

RIA# DCDA#

SOUTA

SINA

DTRA# RTSA#

DSRA# CTSA#

A20GATE KBRST# KBDATA KBCLK MSDATA MSCLK

SIO_SDATA0

R128R128

SIO_SCLK0

R122R122

DSW_ROUTING TEST_MODE2

DEEP_S5 PCHVSB_DETECT

SIO_VLDT_EN SIO_VCORE_EN SIO_FCH_PWRGD

C135 C10u6.3X50805C135 C10u6.3X50805 C134 C0.1u10X0402C134 C0.1u10X0402 C280 C0.1u10X0402C280 C0.1u10X0402

C54 C10u6.3X50805C54 C10u6.3X50805 C117 C0.1u10X0402C117 C0.1u10X0402 C130 C0.1u10X0402C130 C0.1u10X0402

MB_ID0 MB_ID1

value

1

I/O Configuration Address :4E

31

I/O Configuration Address :2E

0

48M Clock Source

32

1

24M Clock Source

0 1

34GPIO / SOUTA

Enable LPT

0

Disable LPT Eable TEST MODE

1

62

Disable TEST MODE

0

Disable TEST MODE DSW ROUTING TO PIN 66,67,68,69,74,77

3VSB

VCC3

69

DSW ROUTING TO PIN 88,89,90,91,92,93

1 Active K8 power on sequence

Inactive K8 power on sequence

96

0

and will be VINX and VRD11.1 function

USB_EN 30

PWR_LED SUS_LED

Wake up event

SIO_WAKE SIO_GP24

A20GATE 17 KBRST# 17 KBDATA 23 KBCLK 23 MSDATA 23 MSCLK 23

R105 0R0402R105 0R0402

R346 4.7KR0402R346 4.7KR0402

TinianPangkor

1

0

COM_GPIO2

USB_EN

PWR_LED 33 SUS_LED 33

R175 0R0402R175 0R0402 R247 X_0R0402R247 X_0R0402

SINA DSRA# DCDA# CTSA# RIA#

SDATA0 12,14,17

SCLK0 12,14,17

SYS5VSB_OFF 26

VCC3

VCC3_ALW

MB_ID0

MB_ID1

Description

R61 10KR0402R61 10KR0402

R65 4.7KR0402R65 4.7KR0402

R353 10KR0402R353 10KR0402

Stuff When COM Port unstuff

R94 X_4.7KR0402R94 X_4.7KR0402 R118 X_4.7KR0402R118 X_4.7KR0402 R87 X_4.7KR0402R87 X_4.7KR0402 R119 X_4.7KR0402R119 X_4.7KR0402 R86 X_4.7KR0402R86 X_4.7KR0402

R64 X_10KR0402R64 X_10KR0402 R47 10KR0402R47 10KR0402

R63 X_10KR0402R63 X_10KR0402 R46 X_10KR0402R46 X_10KR0402

Low

5VDIMM

VCC3_ALW

3

VCC3

PE_WAKE# 17,24,31,32

VCC3

VCC3_SB

VCC3

3

SERIAL PORT 1

VCC5

C653

C0.1u16Y0402

Close to COM PORT header

NRTSA NDSRA# NCTSA# NRIA

NDCDA# NSOUTA NSINA NDTRA

COM_GPIO2

NRIA NCTSA# NDSRA# NSINA NDCDA#

RTSA# DTRA# SOUTA

C662 C330p50XC662 C330p50X C659 C330p50XC659 C330p50X C664 C330p50XC664 C330p50X C666 C330p50XC666 C330p50X

C660 C330p50XC660 C330p50X C663 C330p50XC663 C330p50X C661 C330p50XC661 C330p50X C665 C330p50XC665 C330p50X

C674 C0.1u16Y0402C674 C0.1u16Y0402

TEMP SENSOR

External Thermistor Mode

External Thermal diode Mode Current mode

CHASSIS_ID1

CHASSIS_ID2

THERMDA_CPU

SIO_HWM_AGND

VR_TEMP_DA

SIO_HWM_AGND VR_TEMP_DC

External Thermal diode Mode Current mode

EXT_SYS_TEMP

R184 10KR0402R184 10KR0402 R187 X_10KR0402R187 X_10KR0402

R188 10KR0402R188 10KR0402 R197 X_10KR0402R197 X_10KR0402

CHASSIS_ID1

C153 X_C0.1u16Y0402C153 X_C0.1u16Y0402

CHASSIS_ID2

C161 X_C0.1u16Y0402C161 X_C0.1u16Y0402

U48

20

2 3 4 7 9

16 15 13 11

C137

C2200p50X0402

CP2 X_CPCP2 X_CP

CP3 X_CPCP3 X_CP L9

L9 X_120L600mA-250

X_120L600mA-250

VCC RA1 RA2 RA3 RA4 RA5

DA1 DA2 DA3 GND

GD75232_SSOP20

SIO_VREF

C140

X_C2200p50X0402

CP1 X_CPCP1 X_CP

C142 C2200p50X0402C142 C2200p50X0402 THER_HD

THER_HD

1 2 3

H2X3[4]M_BLACK-RH

2

1

VDD

19

RY1

18

RY2

17

RY3

14

RY4

12

RY5

5

DY1

6

DY2

8

DY3

10

VSS

NDCDA# NSINA NRTSA NSOUTA NDTRA

NRIA

S-BAT54C_SOT23

C139

C2200p50X0402

65

SIO_HWM_AGND

VCC3

CHASSIS TYPE

DEFAULT

25L 17L 13L 10L

2

C652 C0.1u50YC652 C0.1u50Y

+12COM_1 RIA# CTSA#

D51 BAS32L_LL34D51 BAS32L_LL34

DSRA# SINA DCDA#

NRTSA NDTRA NSOUTA

D62 BAS32L_LL34D62 BAS32L_LL34

-12COM_1

C677 C0.1u50YC677 C0.1u50Y

COM1 HEADER

COM1

1 2 3 4

6

5 7 8 9 10

12

H2X6[11]M_GREEN-RH

X

D54

Z

Y

R162

X_10KR1%0402

Place Within APU

RT2

solder side area

X_10KRT1%

SIO_VREF

Place close to VRM MOSFET

CE

B

Q22

Q22 N-SST3904_SOT23

N-SST3904_SOT23

SIO_HWM_AGND

CHASSIS_ID2

CHASSIS_ID1

C750 X_C0.1u16Y0402C750 X_C0.1u16Y0402 C805 X_C0.1u16Y0402C805 X_C0.1u16Y0402

1

00

NDSRA# NCTSA#

NRIA COM_GPIO2

CHASSIS_ID2CHASSIS_ID1

11 0 10

+12V

-12V

N_RI 17

R438

X_10KR1%0402

RT3

X_10KRT1%

1

LPC Debug

LPC_DEBUG1

PCI_CLK_DEBUG16

1 2

A_RST#

3 5

LPC_AD1 LPC_AD2

9

LPC_AD3

11

LPC_FRAME#

13

BH2X7[10]-2PITCH_BLACK-RH-1

SIO AMD POWER SEQUENCE

VCC3

R142 X_10KR0402R142 X_10KR0402 R139 X_10KR0402R139 X_10KR0402 R134 X_10KR0402R134 X_10KR0402

The timing delay between each step is 10~15 mS

PIN 84 SLP_S5#

PIN 64 SLP_S3#

PIN 63 PSON#

DESCRETE VDIMM_EN CIRCUIT

PIN 105 VDIMM_IN

PIN 87 VCORE_EN

SIO_VCORE_EN

PIN 107 VCORE_IN

PIN 86 VLDT_EN

SIO_VLDT_EN

PIN 104 VLDT_IN

PIN 81 FCH_PWRGD

SIO_FCH_PWRGD

SIO_PWRGD INCLUDES TRADITIONAL VCC3 POWER READY CONDITION

Voltage Divider

9 voltage sensors (including VCC, AVCC, VSB, VBAT)

VCCP

VCC_DDR

Title

SUPER I/O NCT6776F

Size Document Number Rev

Custom

Date: Sheet

SIO_VCORE_EN SIO_VLDT_EN SIO_FCH_PWRGD

R141 X_0R0402R141 X_0R0402

R138 X_10KR0402R138 X_10KR0402

R135 X_0R0402R135 X_0R0402

VIN 0~2.048V

R178 X_10KR1%0402R178 X_10KR1%0402

R177 X_10KR1%0402R177 X_10KR1%0402

TP6TP6 TP30TP30 TP31TP31 TP3TP3 TP5TP5

FUSION 1.0

R354 4.7KR0402R354 4.7KR0402

R355 4.7KR0402R355 4.7KR0402

A_RST#

MICRO-START INT'L CO.,LTD.

1

VCC3

4

LPC_ID0LPC_AD0

6 87

12 14

VCORE_EN_R 7,27

CPU_VDDP_VDDR_EN 27

FCH_PWRGD 17,27

VBAT_IO

+12COM_1

-12COM_1

SIO_48M_CLK

VIN_CPUCORE

SIO_HWM_AGND

VIN_VDIMM

SIO_HWM_AGND

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R44

R44 10KR0402

10KR0402

VCC5

5

VCC5_SB Power Switch

+

12

EC55

.CD1000U6.3EL11.5

ATX_5VSB

Option for Normal State

R514

249KR1%

R531

10KR0805

Soft Start

R552 X_0R1206R552 X_0R1206 R553 X_0R1206R553 X_0R1206

12

+

EC54

CD10u16EL5

Tune 5VSB inrush current to 2A from 4A

Layout: Place close to UP7706 pin3 ASAP

D D

SYS5VSB_OFF25

High--------Q20 OFF Low---------Q20 ON

S0,S1,S3

Q62

DS

P-P06P03LCG_SOT89-3-RH

G

C566

C566 C1U16X5

C1U16X5

EC67:Prevent 5VSB viberation

if there is no viberation on VCC5_SB, place EC67 at ATX_5VSB side

EC75 prevent ATX_5VSB inrush current over 2A

4

Trace Width 80mils.

VCC5_SB

12

+

EC56

EC56 .CD1000U6.3EL11.5

.CD1000U6.3EL11.5

VDUAL_EN

ATX_5VSB

R535 0R0402R535 0R0402

R522 X_0R0402R522 X_0R0402

12

+

EC52

.CD1000U6.3EL11.5

ATX_5VSB

C571

C10u10Y0805

R538 10RR538 10R

VCC3_WAKE_ENVCC3_WAKE_EN

3

VCC3_WAKE POWER

4

U35

1

POK

2

EN

VCTRL

3

VIN

5

VREF

GND8GND

C557 C1U10YC557 C1U10Y

6

VOUT

7

FB

UP0104PSU8_PSOP8-HF

9

S0,S1,S3,S5

C539

C0.015u16X0402

R495

R495 10KR1%0402

10KR1%0402

R503

3.09KR1%0402-RH

VCC3_WAKE

C475

C10u10Y0805

2

+

12

EC46

CD470u6.3SO-RH

ATX_5VSB

C558

C10u10Y0805

Pd=( Vin - Vout] * Imax = (5 - 2.5) V * 0.2 Amp = 0.5 W

VCC3_ALW POWER

U37

U37 UP0111AMA5-00_SOT23-5-HF

UP0111AMA5-00_SOT23-5-HF

1

C0.1u16Y0402

VIN

3

EN

C555

mach@Stuff when turn off VCC3_WAKE on S5 state

VOUT

FB

GND

4

2

0.8 V

1

S0,S1,S3,S5,DEEP_S5

5

C556

C0.1u16Y0402

R512

3.16KR1%0402

R2

R513

1KR1%0402

R1

VCC3_ALW

C568

C563

C10u10Y0805

C22u6.3X1206

Vo=0.8*(R1+R2)/R1

5VSBDRV1 5VDRV1

5VDIMM FOR DDR

5VSBDRV1

7

5VDRV1

8

+12V

5VDIMM_5V

D

Q50

G

S

X_N-2N7002_SOT23

C782 X_C0.1u16Y0402C782 X_C0.1u16Y0402

U54

UP0105PSW8_PSOP8-HF

6

VOUT

7

FB

0.8 V

9

PD=1.9 W

ATX_5VSB

C212 C18000p16X0402C212 C18000p16X0402

R284

C294

C0.022u50X

1.5KR-RH

R286

200KR0402

R285

56KR1%0402

Layout:Route 50 mils AND 500 mils LONG (USE 2x25 mil TRACES TO EXIT BALL FIELD)

2.5V@0.75 A

R351

C373

2.1KR1%0402

R2

X_C0.1u16Y0402

R356

Vo=0.8*(R1+R2)/R1

R356

1KR1%0402

R1

R293 510R0402R293 510R0402

C C

VCC5

R294 10KR0402R294 10KR0402

ATX_PWROK7,25,27,33

SLP_S3#17,25,27

ATX_5VSB

CRB: MODE Low support S0/S3 Hi support S0/S3/S5

SLP_S5#17,25,27,30

R299 X_4.7KR0402R299 X_4.7KR0402

5VDIMM_5V

C309 X_C0.1u16Y0402C309 X_C0.1u16Y0402

U23

S3#55VSB_DRV

6

S5#

MODE

4

MODE

R295

0R0402

R298 10R0402R298 10R0402 C325 X_C0.1u16Y0402C325 X_C0.1u16Y0402

1

2

5VSB

5VCC

5VCC_DRV

GND

3

UP7501M8_SOT23-8-RH

For special PSU sequence

VCC3

B B

R323

X_1KR0402

R322

X_4.7KR0402

ATX_5VSB

D

G

S

Q51

X_N-2N7002_SOT23

R306

X_47KR1%0402-RH

C333

X_C0.1u16Y0402

CPU VDDA_25 POWER

VCC5_SB

R557 10RR557 10R

ATX_PWROK7,25,27,33

A A

R362 10KR0402R362 10KR0402

VCC3

C389

C10u10Y0805

4

1

POK

CNTL

2

EN

3

C390

X_C0.1u16Y0402

5

VIN

5

NC

GND8GND

Pd=( Vin - Vout] * Imax = (3.3 - 2.5) V * 0.75Amp = 0.6 W

ATX_5VSB

G

VCC5

D S

D

S

5VSBDRV1 30 5VDRV1 30

Q47

Q47 P06P03LCG_SOT89

P06P03LCG_SOT89

Q46

N-45N02_TO252-RH

5VDRV1_EN 30

VDDA_25

C374

X_C10u10Y0805

4

5VDIMM

+

12

EC29

EC29 CD100u16EL5-RH

CD100u16EL5-RH

C247

X_C0.1u16Y0402

L:S5 H:S0,S1,S3

VDUAL_EN

VCC3_SB

VCC5_SB

VCC3_SB

12

+

VCC3_SB

12

+

EC71

EC72

VCC3_SB

R594

X_0R0402

VCC3_SB_EN

R595 0R0402R595 0R0402

C630

C10u10Y0805

VCC5_SB

R496 10RR496 10R

VCC3_SB_POK

R523 X_0R0402R523 X_0R0402 R485 0R0402R485 0R0402

C525

C10u10Y0805

Pd=( Vin - Vout] * Imax = (3.3 - 1.1) V * TBD Amp

X_CD100u16EL5-RH

VCC5_SB

R500 X_10RR500 X_10R

VCC3_SB_POK

R530 X_0R0402R530 X_0R0402 R490 X_0R0402R490 X_0R0402

C553

X_C10u10Y0805

Pd=( Vin - Vout] * Imax = (3.3 - 1.1) V * TBD Amp

X_CD100u16EL5-RH

VCC3_SB POWER

VCC5_SB

R596 10RR596 10R

R413

X_10KR0402

VCC3_SB_POK

4

U40

1

POK

2

EN

VCTRL

3

VIN

5

VREF

GND8GND

1.1VDUAL POWER

C542 X_C0.1u16Y0402C542 X_C0.1u16Y0402

4

U55 UP0104PSU8_PSOP8-HFU55 UP0104PSU8_PSOP8-HF

1

POK

2

EN

3

VIN

5

VREF

U56 X_UP0104PSU8_PSOP8-HFU56 X_UP0104PSU8_PSOP8-HF

1

POK

2

EN

3

VIN

5

VREF

VCTRL

GND8GND

9

4

VCTRL

GND8GND

9

3

VOUT

6

7

FB

0.8 V

PD=1.9W

C552 X_C0.1u16Y0402C552 X_C0.1u16Y0402

6

7

FB

0.8 V

PD=1.9W

For option

R674 0R0805R674 0R0805

C625 C1U10YC625 C1U10Y

6

VOUT

7

FB

UP0104PSU8_PSOP8-HF

9

1.V@1.3A----D3

S0,S1,S3

0.6A----D2

C783

C0.015u16X0402

Vo=0.8*(R1+R2)/R1

C787

X_C0.015u16X0402

Vo=0.8*(R1+R2)/R1

+1.1VDUAL+1.1VDUAL_D3

S0,S1,S3

C594

C0.015u16X0402

R2

R1

R2

R1

R555

R555 10KR1%0402

10KR1%0402

R559

3.09KR1%0402-RH

R489

R489 1KR1%0402

1KR1%0402

R479

2.61KR1%0402

R528

R528 X_1KR1%0402

X_1KR1%0402

R492

X_2.61KR1%0402

C528

C10u10Y0805

C569

X_C10u10Y0805

VCC3_SB

+

12

EC53

C616

C10u10Y0805

+1.1VDUAL

+

12

EC47

+1.1VDUAL_D3

+

12

EC66

.CD1000U6.3EL11.5

CD100u16EL5-RH

X_CD100u16EL5-RH

2

0.75V@2A

H:S5 L:S0,S1,S3

SYS5VSB_OFF25

SIO GPIO L:VCC3_WAKE on@ S5 H:VCC3_WAKE off@S5

SIO_VDUAL_EN25

SIO_VDUAL_EN SYS5VSB_OFF

VTT_DDR POWER

VCC_DDRVTT_DDR

C339 X_C0.1u16Y0402C339 X_C0.1u16Y0402

R327

+

12

EC28

.CD1000U6.3EL11.5

R327 1KR1%0402

1KR1%0402

R328

1KR1%0402

C343

C0.1u16Y0402

U26

1

VIN

2

GND

3

REFIN

4

VOUT

9

GND

UP0109PSW8_PSOP8-HF

VCNTL

8

NC3

7

NC2

6 5

NC1

DUAL POWER CONTROL

ATX_5VSB

R629

R629 X_4.7KR0402

X_4.7KR0402

R382 4.7KR0402R382 4.7KR0402

R670 X_0R0402R670 X_0R0402 R411 X_4.7KR0402R411 X_4.7KR0402

B

R630

X_4.7KR0402

VCC5 VCC3

12

+

EC19

.CD1000U6.3EL11.5

Title

ACPI UPI & SYS POWER

Size Document Number Rev

Custom

FUSION 1.0

Date: Sheet

ATX_5VSB

R623

R623 20KR1%0402

20KR1%0402

VDUAL_EN

VDUAL_EN=NAND (SYS5VSB_OFF . SIO_VDUAL_EN)

DS

C640

Q76

G

N-2N7002_SOT23

X_C0.1u16Y0402

CE

Q36

R665

X_0R0402

N-SST3904_SOT23

U64

1

INB

2

INA

GND3OUTY

12

+

EC65

CD1000U6.3EL11.5

MICRO-START INT'L CO.,LTD.

VCC3

5

VCC

R671 X_0R0402R671 X_0R0402

4

X_TC7SH00FU_SSOP5-RH

+

12

+

12

EC33

.CD1000U6.3EL11.5

1

EC45

X_.CD1000U6.3EL11.5

26 35Friday, April 29, 2011

VCC3

VCC5

VDUAL_EN

of

C350

C1U10Y

R649

R649 X_4.7KR0402

X_4.7KR0402

5

POWER EN & PWRGD LOGIC CIRCUIT

VCC5_SB 5VDIMM

R174 4.7KR0402R174 4.7KR0402

R202 4.7KR0402R202 4.7KR0402

B

CE

Q24

N-SST3904_SOT23

Q28

N-SST3904_SOT23

D D

SLP_S5#17,25,26,30

VCC5_SB

VCC_DDR

R26

4.7KR0402

R25

R25 X_4.7KR0402

X_4.7KR0402

C C

OD,10KR PU TO 5V

VRM_PWRGD7

B B

NB_VCC1P1

R628 8.2KR0402R628 8.2KR0402

VRM_PWRGD CPU_VDDP_VDDR_EN

VRM_PWRGD

SLP_S3#17,25,26

ATX_PWROK7,25,26,33

FP_RST#17,25,33

VCC5_SB

4.7KR0402

R589

R560

R560 X_10KR0402

X_10KR0402

R30

4.7KR0402

CE

B

Q2

Q2 N-SST3904_SOT23

N-SST3904_SOT23

C27

C4.7u6.3X5

D41

S-RB751V-40_SOD323-RH

D40

S-RB751V-40_SOD323-RH

D9 S-RB751V-40_SOD323-RHD9 S-RB751V-40_SOD323-RH D8 S-RB751V-40_SOD323-RHD8 S-RB751V-40_SOD323-RH D7 S-RB751V-40_SOD323-RHD7 S-RB751V-40_SOD323-RH

SYS_PWRGD

CE

B

Q67

Q67 N-SST3904_SOT23

N-SST3904_SOT23

C600

C600 C1U10Y

C1U10Y

G

CE

B

R29

R29 10KR0402

10KR0402

VCORE_EN_R

DS

Q1

Q1 N-2N7002_SOT23

N-2N7002_SOT23

NBCORE_ENVRM_PWRGDVRM_PWRGD

DS

Q27

G

N-2N7002_SOT23

R173 4.7KR0402R173 4.7KR0402

VCC3_SB

R585

R585 10KR0402

10KR0402

DS

Q69

G

N-2N7002_SOT23

TO VCORE_EN CONTROL

VCORE_EN_R 7,25

C19

C0.1u16Y0402

CPU_VDDP_VDDR_EN 25

FCH_PWRGD_R

ATX_PWROK 7,25,26,33

DDR_EN

C171

X_C0.1u16Y0402

4

DDR III 1.5V POWER

C172 C0.1u10X0402C172 C0.1u10X0402

C176 C1000P50X0402C176 C1000P50X0402

CPU_VDD POWER

C491 C0.1u10X0402C491 C0.1u10X0402

C486 C470P50X0402C486 C470P50X0402

+12V

S-BAT54C_SOT23

5VDIMM

R215 2KR1%0402R215 2KR1%0402

1.2V@15A

R421 3.09KR1%0402-RHR421 3.09KR1%0402-RH

CPU_VDDP_VDDR_EN

1.5V@22A

X

D16

Y

DDR_EN

7

DDR_FB

6

0.8 V

R222

1.1KR1%0402

7

6

0.8 V

R427

2KR1%0402

Z

U16

COMP/DIS

FB

U32

COMP/DIS

FB

3

+12V

S-BAT54C_SOT23

R240

2.2R0805

C183 C1U25X0805C183 C1U25X0805

5

DDR_BOOT

1

BST

DDR_HG

2

VCC

TG

DDR_PHASE

8

PHASE

DDR_LG

4

BG

GND

NCP1587DR2G_SOIC8-RH

3

C173 X_C0.01U16X0402C173 X_C0.01U16X0402

R216 976R1%0402R216 976R1%0402

+12V

R426

2.2R0805

C489 C1U25X0805C489 C1U25X0805

5

CPU_VDD_BOOT

1

BST

CPU_VDD_HG

2

VCC

TG

CPU_VDD_PHASE

8

PHASE

CPU_VDD_LGCPU_VDD_FB

4

BG

GND

NCP1587DR2G_SOIC8-RH

3

C492 X_C0.01U16X0402C492 X_C0.01U16X0402

R424 1KR1%0402R424 1KR1%0402

2

X

D15

Z

Q33

R219

R219 1R0805

1R0805

Q33

D

G

S

N-P0903BD

R218

R218 10KR1%0402

10KR1%0402

Q30

D

G

S

N-P0603BD

G

Y

R244 1R0805R244 1R0805

R237

R237 10KR1%0402

10KR1%0402

DDR_HG_R

C175C0.22u25X-HFC175C0.22u25X-HF

R213 X_1KR1%0402R213 X_1KR1%0402

VDDIOFB+10

R224 0R0402R224 0R0402

+12V

S-BAT54C_SOT23

D42

X

R415 1R0805R415 1R0805

R371

12.7KR1%0402

Y

Z

C482C0.22u25X-HFC482C0.22u25X-HF

CPU_VDD_HG_R

R369

R369 1R0805

1R0805

Q54

D

G

S

N-P0903BD

R367

R367 10KR1%0402

10KR1%0402

Q53

D

G

S

N-P0603BD

R434 X_1KR1%0402R434 X_1KR1%0402

VDDR&VDDP IS COMBINED BY DEFAULT VDDP_PWMONLY FOR NORMAL OPERATION(VDDR/VDDP COMBINED MODE) VDDR_PWMIS FOR DEBUG/OC MODE (SEPERATE VDDR/VDDP)

5VDIMM_IN

C245

C215

+

12

EC14

C10u10X50805

X_C0.1u16Y0402

Q29

D

S

N-P0603BD

X_C0.1u16Y0402

CHOKE3 CH-1.1u35A1.7m-RHCHOKE3 CH-1.1u35A1.7m-RH

1 2

R200

2.2R0805

C155

C155 C2200p50X0402

C2200p50X0402

CD470u6.3SO-RH

R223 56R0402R223 56R0402

C440

C391

+

12

EC40

C10u10X50805

X_C0.1u16Y0402

CHOKE10 CH-1.1u35A1.7m-RHCHOKE10 CH-1.1u35A1.7m-RH

CPU_VDDP POWER

CD470u6.3SO-RH

1 2

R368

2.2R0805

C429

C429 C2200p50X0402

C2200p50X0402

VDDP and VDDR support two separate power planes with single regulator

1.2 V@5A

CPU_VDD CPU_VDDP CPU_VDDRCPU_VDD

R337 0R0805R337 0R0805 R336 0R0805R336 0R0805

+

12

EC13

CD470u6.3SO-RH

+

12

EC35

CD470u6.3SO-RH

CHOKE5

CH-1.2u15A3.0m-RH

1 2

C193

C1u10X7R

CHOKE9

CH-1.2u15A3.0m-RH

1 2

C480

C1u10X7R

1

5VDIMM

C265

X_C0.1u16Y0402

+

12

+

12

EC18

EC20

CD1800u6.3EL20-RH-2

VCC3

C379

X_C0.1u16Y0402

CPU_VDD output 15A OCP:26A

CPU_VDD

+

12

+

12

EC32

EC31

.CD1000U6.3EL11.5

CPU_VDDR POWER

R339 0R0805R339 0R0805 R338 0R0805R338 0R0805

VCC_DDR output 22A OCP:38A

VCC_DDR

+

12

+

12

EC24

EC12

CD1800u6.3EL20-RH-2

+

12

EC38

.CD1000U6.3EL11.5

1.2 V@5A

NB_VCC1P1 POWER

A A

FCH_PWRGD_R

C618 X_C0.1u16Y0402C618 X_C0.1u16Y0402

53

U41

VCC

1

A

Y

2

B

GND

X_AHCT1G126GV_SOT23-5-RH

4

R592 33R0402R592 33R0402

5

VCC3_SB

Rise time ≤ 50-ms. Fall time ≤ 1-ms Deasserted at least 80-ns before VDDCR_11 drops below 5% of its nominal value

FCH_PWRGD

FCH_PWRGD 17,25

NBCORE_EN

4

VCC3

R376

R376 10KR0402

10KR0402

C431

X_C0.1u16Y0402

1.1V@5A

1 2

0.8 V

R375

2.55KR1%0402

U30

EN

VCC DRV

GND FB3SOFT-S

NCP102SNT1G_TSOP6-RH

3

+12V

6 5

NB_VCC1P1_SS

4

C430

C430 C1U16X5

C1U16X5

C433

1 2

C0.01U16X0402

R370 100R1%R370 100R1%

R373

R373 10KR1%0402

10KR1%0402

C434

C434 C100P50N0402

C100P50N0402

C20 X_C1500p50X0402C20 X_C1500p50X0402

NB_VCC1P1_DRV_RNB_VCC1P1_DRV

C432 C0.022u50XC432 C0.022u50X

R374 1KR1%0402R374 1KR1%0402

CPU_VDD

EC39 .CD1000U6.3EL11.5

Q57

D

G

S

N-45N02_TO252-RH

Pd=33 W@Tc=100 °C

+

1 2

C439 C10u10Y0805C439 C10u10Y0805

2

C450

X_C10u10X50805

NB_VCC1P1

+

12

EC37

.CD1000U6.3EL11.5

+

12

EC36

.CD1000U6.3EL11.5

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

Custom

Date: Sheet

MICRO-START INT'L CO.,LTD.

FCH CORE & DDR Power

FUSION 1.0

1

27 35Friday, April 29, 2011

of

5

Audio Codec ALC892 (Co-Lay 662/888S)

Default is ALC892

JD resistors should be placed as close as possible to the sense pin of CODEC.

HP_SNS

R591 39.2KR1%0402R591 39.2KR1%0402

MIC_SNS

R590 20KR1%0402R590 20KR1%0402

CEN_JD

D D

FRONT-JD

R532 5.1KR1%0402R532 5.1KR1%0402

LINE1-JD

R517 10KR1%0402R517 10KR1%0402

MIC1-JD

R537 20KR1%0402R537 20KR1%0402

SURR_JD

R542 39.2KR1%0402R542 39.2KR1%0402

ALC888S/892:stuff ALC662: NC

VCC3

C C

ALC892 ALC888S-VC ALC662-VD

Pin 3

REGREF GPIO0

GPIO1 GPIO1

Pin 4

ALC662-VC

GPIO1

DVSS

Front Audio Jack

MIC2-VREFO

LINE2-VREFO

B B

MIC_IN-R

C575 C4.7u10X50805-HFC575 C4.7u10X50805-HF

MIC_IN-L

C576 C4.7u10X50805-HFC576 C4.7u10X50805-HF

+

HP_OUT-R HP_OUT-L

+

EC48 CD100u16EL5-RH

1 2

+

EC49 CD100u16EL5-RH

1 2

SIDESURR_JD

C626

C10u10X50805

FPAUD_PRESENCE#

REGREF

GPIO1

D58

S-BAT54A_SOT23

Z

D57

X_S-BAT54A_SOT23

SIDESURR_L SIDESURR_R

C624

C0.1u10X0402

R582 10KR1%0402R582 10KR1%0402 R581 5.1KR1%0402R581 5.1KR1%0402

ALC888S/892:stuff ALC662: NC

45 46 47 48

Sense_A

13

HP_OUT-L

14

HP_OUT-R

15

MIC_IN-L

16

MIC_IN-R

17 18 19

20

C591

C0.1u10X0402

R575 X_0R0402R575 X_0R0402 R574 X_0R0402R574 X_0R0402

ALC662-VC:stuff ALC888S/892/662-VD:NC

Y X

MIC_R_1

HP_R_1 HP_L_1

R515

R515 1KR0402

1KR0402 R516

R516 1KR0402

1KR0402 R507

R507 75R0402

75R0402 R508

R508 75R0402

75R0402

D60

D60 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH

D59

D59 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH

D61

D61 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH

Sense_B

FRONT-L

34

35

33

U39

NC

Sense B

FRONT-L

SIDE-L SIDE-R SPDIFI/EAPD SPDIFO

Sense A LINE2-L LINE2-R MIC2-L MIC2-R CD-L CD-GND

CD-R

DVDD11GPOI0/DMIC-CLK2GPIO1/DMIC-DATA3DVSS14SDATA-OUT5BCLK6DVSS27SDATA-IN8DVDD-IO9SYNC10RESET#11PCBEEP

R641 4.7KR0402R641 4.7KR0402 R643 4.7KR0402R643 4.7KR0402

R645 X_4.7KR0402R645 X_4.7KR0402 R647 X_4.7KR0402R647 X_4.7KR0402

12

D63

D63 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH

Audio Power

ALC662/888S: stuff ALC892/662-VD: unstuff

Trace Width 40mils.

D46 X_1N4148W-F_SOD123-RHD46 X_1N4148W-F_SOD123-RH

+12V

A A

R518 X_10R0805R518 X_10R0805

EC51

X_CD100u16EL5-RH

+

12

X_C0.1u16Y0402

5

U36

VIN3VOUT

C587

GND

X_L78L05N_TO92-3

2

Reference resistor for Jack Detection(close to the codec)

Spilt by DGND

AVDD5

C0.1u10X0402

C0.1u10X0402 C634

C634

FRONT-R

SURR_L

SURR_R

CENO

LFE

R597 20KR1%0402R597 20KR1%0402

36

37

FRONT-R

REALTEK

AL892/662

12

44

39

40

42

41

43

38

LFE

JDREF

AVSS2

AVDD2

SURR-L

SURR-R

CENTER

PIN37-VREFO

MIC1-VREFO-L

LINE1-VREFO

LINE2-VREFO

MIC1-VREFO-R

AZ_SDIN_R

REGREF

FPAUD_PRESENCE#

R569 0R0402R569 0R0402

ALC662-VC:NC ALC892/888S/662-VD:stuff

1/16W, 2.5V, max:25mA

F_AUDIO

3

MIC_R

5

MIC_L

7

HP_R HP_L

11 13

H2X7[14]M_ORANGE-RH

R642

R648

X_22KR0402

22KR0402

R644

R646

X_22KR0402

22KR0402

Analog Area Digital Area

Digital Area Analog Area

1

Analog Area Digital Area

21

MIC1-L

22

MIC1-R

23

LINE1-L

24

LINE1-R

25

AVDD1

26

AVSS1

27

VREF

28 29 30

MIC2-VREFO

31 32

ALC892-CG,A2

12

R561 22R0402R561 22R0402

C607

291

HP_SNS

4

MIC_SNS

6 8 10 12

FPAUD_PRESENCE#

3.3V Level GPIO Codec GPIO1

VCC5_SB

Pd=( Vin - Vout] * Imax = (12 - 5 ) V * 0.1Amp = 0.7 W SPEC:PD(max) to 25°C = 625 mW

4

Layout Follow Route

PIN.36

PIN.46

PIN.47

PIN.1 PIN.12

MIC1-IN-L MIC1-IN-R

LINE1-IN-L LINE1-IN-R

C605 C0.1u10X0402C605 C0.1u10X0402

C622 C10u10X50805C622 C10u10X50805

LDOVDD

C602

15p50N0402

C22p50N0402

D44

X_B140-13-F_SMA-RH

AVDD5_R

C551

MIC1-VREFO-L

MIC2-VREFO LINE2-VREFO

MIC1-VREFO-R

C589

15p50N0402

VCC3

C0.1u10X0402

4

PIN.25

AVDD5

AZ_RST#

C582

C270P50N0402

X_JUMPER-1X2A_GREEN-RH-1

Short Pin3 & Pin5

R579

R579 10KR0402

10KR0402

C617

C617 X_C0.1u16Y0402

X_C0.1u16Y0402

R511 X_0RR511 X_0R

X5R

C554

ALC 662/888S/892 : stuff

C10u10X50805

PIN.24PIN.37

PIN.13PIN.48

Analog Area Digital Area

AZ_RST# 17 AZ_SYNC 17 AZ_SDIN 17 AZ_BIT_CLK 17 AZ_SDOUT 17

F_AUDIO_X1

AVDD5

3

Rear Phone Jack 3 IN 1

LIN_IN

AUDIOD

1 2 1 2 1 2

C745

C745 C10u10X50805

C10u10X50805

AUDIOD

63 62 64 61 R5

AUDIOE

53 52 54 51

AUDIOF

43 42 44 41

CP15CP15 CP6CP6 CP16CP16

C632

C632 C10u10X50805

C10u10X50805

C627

C627 C10u10X50805

C10u10X50805

JACK-AUDIOX6F-RH

G3

LIN_OUT

JACK-AUDIOX6F-RH

MIC1

JACK-AUDIOX6F-RH

G4

X_CD10u16EL5

+

EC42

1 2

LINE1-IN-L

C801

C4.7u10X50805-HF

C4.7u10X50805-HF C4.7u10X50805-HF

C4.7u10X50805-HF

LINE1-IN-R

C793

+

EC44

1 2

X_CD10u16EL5

ALC888S/892: 4.7uX5R,1KR,22KR reserved ALC662: 10u EL,75R,22KR stuffed

EC69

EC69 CD100u16EL5-RH

CD100u16EL5-RH

+

1 2

+

1 2

EC70

EC70 CD100u16EL5-RH

CD100u16EL5-RH

MIC1-VREFO-L MIC1-VREFO-R

X_CD10u16EL5

+

EC41

1 2

C561

C4.7u10X50805-HF

C4.7u10X50805-HF C4.7u10X50805-HF

C4.7u10X50805-HF

C560

+

EC43

1 2

X_CD10u16EL5

ALC888S/892: 4.7uX5R,1KR,22KR reserved ALC662: 10u EL,75R,22KR stuffed

In order to meet Vista Premium requirement, ALC892/888S:MLCC input cap MUST use X5R dielectric material and 10V DC rated voltage. ALC662:10uF DIP caps and 22K pull-down resistors

6.0

(A) CEN/BAS

(B) SURR

(C) SIDESURR

VCC5_SB

5.1V

1KR0402

M_INR_0MIC1-IN-R

L_INL_1

R481

R481 1KR0402

1KR0402

L_INR_1

R476

R487

R487 75R0402

75R0402

R494

R494 75R0402

75R0402

R498 2.2KR0402R498 2.2KR0402 R505 2.2KR0402R505 2.2KR0402

1KR0402

1KR0402 R510

R510 1KR0402

1KR0402 R509

R509

1*3 N54-13F0331-K06

F_L_1

M_INL_1

M_INR_1

L_INL_0

L_INR_0

F_R_0FRONT-R F_R_1 F_R_2

2*3 N54-26F0091-K06

120L600mA-250

120L600mA-250 L38

L38 120L600mA-250

120L600mA-250 L36

L36

R475

R475 X_22KR0402

X_22KR0402 R480

R480 X_22KR0402

X_22KR0402

D35

D35 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH D34

D34 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH

120L600mA-250

120L600mA-250 L39

L39 120L600mA-250

120L600mA-250 L41

L41

R493

R493 22KR0402

22KR0402 R486

R486 22KR0402

22KR0402

120L600mA-250

120L600mA-250 L45

L45 120L600mA-250

120L600mA-250 L43

L43

R504

R504 X_22KR0402

X_22KR0402 R497

R497 X_22KR0402

X_22KR0402

LIN_IN (D)

LIN_OUT (E)

MIC1 (F)

ALC892 PART

ALC662-VC/88S:NC ALC892/662-VD:stuff

Digital Area

Analog Area

21

L40

D43

60n900mA_0805-RH-2

MMSZ5231BT1G-RH

AVDD5_R LDOVDD

R576 0RR576 0R

PIN 29:Reference for integrated regulator

3

PIN 3:Reference for integrated regulator; 10uF capacitor to digital ground

LINE1-JD L_INL_2

L_INR_2

12

FRONT-JD

F_L_2FRONT-L F_L_0

12

D39

D39 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH D33

D33 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH

MIC1-JD

M_INL_2M_INL_0MIC1-IN-L

M_INR_2

12

D32

D32 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH D29

D29 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH

Tied at one point only under the codec or near the codec

C631 C0.1u16Y0402C631 C0.1u16Y0402 C514 C1000P50X0402C514 C1000P50X0402 C675 C1000P50X0402C675 C1000P50X0402 C567 C1000P50X0402C567 C1000P50X0402

PIN25,38 Layout:place close to Pin 25,38 ASAP

AVDD5

Layout:place close to Pin 3 ASAP

REGREF

2

Rear Phone Jack 6 IN 1

12

CEN_JD

LFE_2

12

SURR_JD

SURR_R_2

12

SIDESURR_JD

12

120L600mA-250

CENO_1

SURR_L_1

SURR_R_1

SIDESURR_L_1

SIDESURR_R_1

120L600mA-250 L57

L57 120L600mA-250

120L600mA-250 L56

L56

R621

R621 22KR0402

22KR0402 R626

R626 22KR0402

22KR0402

D28

D28 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH D38

D38 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH

120L600mA-250

120L600mA-250 L59

L59 120L600mA-250

120L600mA-250 L58

L58

R631

R631 22KR0402

22KR0402 R634

R634 22KR0402

22KR0402

D37

D37 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH D36

D36 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH

120L600mA-250

120L600mA-250 L48

L48 120L600mA-250

120L600mA-250 L49

L49

R603

R603 22KR0402

22KR0402 R598

R598 22KR0402

22KR0402

D30

D30 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH D31

D31 ESD-VPORT0603102MV05-RH

ESD-VPORT0603102MV05-RH

75R0402

+

CENO CENO_0 CENO_2

SURR_L SURR_L_2SURR_L_0

SURR_R SURR_R_0

SIDESURR_L SIDESURR_L_2SIDESURR_L_0

SIDESURR_R SIDESURR_R_0 SIDESURR_R_2

+

EC58 CD10u16EL5

1 2

+

EC59 CD10u16EL5

1 2

+

EC62 CD10u16EL5

1 2

+

EC63 CD10u16EL5

1 2

+

EC60 CD10u16EL5

1 2

+

EC64 CD10u16EL5

1 2

ALC888S/892:stuff ALC662: NC

75R0402 R627

R627 75R0402

75R0402

LFE_0LFE LFE_1

R622

75R0402

75R0402 R635

R635 75R0402

75R0402 R632

R632

75R0402

75R0402 R599

R599 75R0402

75R0402 R604

R604

EMI

For EMI Placement close to Codec chip

LINE1-IN-R

C577 X_C100P50N0402C577 X_C100P50N0402

LINE1-IN-L

C578 X_C100P50N0402C578 X_C100P50N0402

FRONT-R

C633 X_C100P50N0402C633 X_C100P50N0402

FRONT-L

C629 X_C100P50N0402C629 X_C100P50N0402

MIC1-IN-RMIC_L_1

C579 X_C100P50N0402C579 X_C100P50N0402

MIC1-IN-L

C580 X_C100P50N0402C580 X_C100P50N0402

SURR_R

C636 X_C100P50N0402C636 X_C100P50N0402

SURR_L

C635 X_C100P50N0402C635 X_C100P50N0402

LFE

C637 X_C100P50N0402C637 X_C100P50N0402

CENO

C638 X_C100P50N0402C638 X_C100P50N0402

Sense_B

C623 X_C0.1u16Y0402C623 X_C0.1u16Y0402

ALC892 ALC888S-VC ALC662-VD

AVDD(5V)

45.8mA 61mA

11mA 41mA

2

ALC662-VC

41.5mA

23.4mADVDD(3.3V)

40.5mA

10.8mA

TP29TP29

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

Custom

Date: Sheet

MICRO-START INT'L CO.,LTD.

ALC892/662

FUSION 1.0

1

CEN/BAS

AUDIOA

33 32 34 31 L5

JACK-AUDIOX6F-RH

G6

SURR

AUDIOB

JACK-AUDIOX6F-RH

23 22 24 21

G7

G8

SIDESURR

AUDIOC

13 12 14 11

JACK-AUDIOX6F-RH

G5

AVDD5

28 35Saturday, August 13, 2011

of

1

of

E

NEAR USB CONNECTOR

4 4

3 3

SVCC2

U12

U12 CMD ( CM1293A-04SO )

CMD ( CM1293A-04SO )

52

SBD8-

614

SBD8+

USB9USB9+ USB8USB8+

SBD4SBD4+

USB5+ USB5- SBD5USB4+ USB4-

3

R169 0RR169 0R R160 0RR160 0R R179 0RR179 0R R171 0RR171 0R

SVCC1

U24

U24 CMD ( CM1293A-04SO )

CMD ( CM1293A-04SO )

52

614

3

SBD5+

R313 0RR313 0R R312 0RR312 0R C812

SBD4+

R315 0RR315 0R

SBD4-

R314 0RR314 0R

REAR PANEL USB CONNECTOR

SBD9SBD9+

SBD9SBD9+ SBD8SBD8+

SBD5+ SBD5-

L3

USB9-17 USB9+17

USB8-17 USB8+17

USB4-17 USB4+17

USB5-17 USB5+17

4

X_CMC-L12-9008014-RH

L5

4

X_CMC-L12-9008014-RH

L22

4

X_CMC-L12-9008014-RH

L23

4

X_CMC-L12-9008014-RH

231

USB 2.0 trace length REAR side within 18''; FRONT side within 6''

SBD9SBD9+

SBD8SBD8+

SBD4SBD4+

SBD5SBD5+

FRONT USB PIN HEADER

SVCC6

U42

U42 CMD ( CM1293A-04SO )

CMD ( CM1293A-04SO )

52

SBD0+ SBD0-

USB1+

2 2

USB1USB0+

SBD2+ SBD2- SBD3-

USB3+ USB3USB2+ USB2-

1 1

614

R608 0RR608 0R R609 0RR609 0R R610 0RR610 0R R611 0RR611 0R

SVCC5

614

R612 0RR612 0R R613 0RR613 0R R614 0RR614 0R R615 0RR615 0R

SBD1+ SBD1-

3

SBD1+ SBD1SBD0+ SBD0-USB0-

U43

U43 CMD ( CM1293A-04SO )

CMD ( CM1293A-04SO )

52

SBD3+

3

SBD3+ SBD3SBD2+ SBD2-

USB1-17

USB1+17

USB0-17

USB0+17

USB3-17

USB3+17

USB2-17

USB2+17

E

L50

231

4

X_CMC-L12-9008014-RH

L51

231

4

X_CMC-L12-9008014-RH

L52

231

4

X_CMC-L12-9008014-RH

L53

231

4

X_CMC-L12-9008014-RH

SBD1SBD1+

SBD0SBD0+

SBD3SBD3+

SBD2- SBD3-SBD3SBD2+

SBD2SBD2+

SBD9SBD9+

SBD8SBD8+

SBD5SBD5+

SBD4SBD4+

SVCC6

SVCC5

C808

C807

C806

X_C5.6p50N0402

C812

C811

C810

X_C5.6p50N0402

1 2 3 4 5 7 8 9 10

H2X6[11]M_YELLOW-RH

1 2 3 4 5 7 8 9 10

H2X6[11]M_YELLOW-RH

D

SVCC2

C809

X_C5.6p50N0402

SVCC1

C813

X_C5.6p50N0402

F_USB1

F_USB2

D

C157 X_C0.1u16Y0402C157 X_C0.1u16Y0402

HDMI_USBA

U1

VCC

U2

USB2-

U3

USB2+

U4

GND

U5

VCC

U6

USB1-

U7

USB1+

U8

GND

HDMI_USBX2-RH-3

X_C5.6p50N0402

X_C0.1u16Y0402

X_C0.1u16Y0402 C290

C290 USB_LANA

USB_LANA

5

PWR

6

USB-

7

USB+

UP

8

GND

1

PWR

2

USB-

3

USB+

4

DOWN

GND

RJ45_USBX2_TX-RH-3

X_C5.6p50N0402

6

12

6

12

UP

DOWN

C136 C0.1u10X0402C136 C0.1u10X0402 C143 C0.1u10X0402C143 C0.1u10X0402

C128 C0.1u10X0402C128 C0.1u10X0402 C129 C0.1u10X0402C129 C0.1u10X0402

SBD12+SBD13+

SBD12SBD12+ SBD13SBD13+

C

USB_SS_TX2P_R USB_SS_TX2N_R

USB_SS_RX2N_R USB_SS_RX2P_R

USB_SS_TX2P_CUSB_SS_TX2P USB_SS_TX2P_R

USB_SS_TX3P_R USB_SS_TX3N_R

USB_SS_RX3N_R USB_SS_RX3P_R

USB_SS_TX3P_CUSB_SS_TX3P USB_SS_TX3P_R

USB12+17 USB12-17

USB13-17

USB13+17

F_USB_30

B18

RSVD

B17

RSVD

B16

RSVD

B15

VBUS

B14

VBUS

B13

GND

B12

GND

B11

GND

B10

STDA SSRX-

B9

STDA SSRX+

B8

GND

B7

STDA SSTX-

B6

STDA SSTX+

B5

GND

B4

D+

B3

D-

B2

GND

B1

RSVD

SLOT-PCI36P_WHITE-2PITCH-RH-10

C

USB_SS_RX2N_R USB_SS_RX2P_R USB_SS_RX2P_R

USB_SS_RX3N_R USB_SS_RX3P_R

L4 X_CMC-L12-9008054-RHL4 X_CMC-L12-9008054-RH

231

4

231

4

L6 X_CMC-L12-9008054-RHL6 X_CMC-L12-9008054-RH

USB_SS_TX3N_R USB_SS_TX3P_R USB_SS_TX3P_R

USB_SS_TX2N_R USB_SS_TX2P_R

L1 X_CMC-L12-9008054-RHL1 X_CMC-L12-9008054-RH

231

4

231

4

L2 X_CMC-L12-9008054-RHL2 X_CMC-L12-9008054-RH

4

X_CMC-L12-9008014-RH

4

X_CMC-L12-9008014-RH

X2

A18

RSVD

SVCC7SVCC8

A17

RSVD

A16

RSVD

A15

VBUS

A14

VBUS

A13

GND

A12

GND

X1

A11

GND

A10 A9 A8

GND

A7

STDA SSTX-

A6 A5

GND

A4

D+

A3

D-

A2

GND

A1

RSVD

L10

L11

USB_SS_RX2N_RUSB_SS_RX2N

U34

1 2

4 5

U57

1 2

4 5

231

USB_SS_RX3N_R USB_SS_RX3P_R

USB_SS_TX3N_R USB_SS_TX3P_R

SBD13+ SBD13-

NC

NC NC

NC

NC NC

NC

ESD-IP4284CZ10-TB-RH

3

8

NC

NC NC

NC

NC NC

NC

ESD-IP4284CZ10-TB-RH

3

8

SBD12+ SBD12-

SBD13SBD13+

10 9

7 6

10 9

7 6

USB_SS_RX2N_R

USB_SS_RX3N_R USB_SS_RX3P_R

USB_SS_TX3N_R

USB_SS_TX2N_R USB_SS_TX2P_R

USB 3.0 trace length Front pin header within 3.5''

USB_SS_TX2P_C

R161 0RR161 0R

USB_SS_TX2N_C

R170 0RR170 0R

USB_SS_RX2N

R180 0RR180 0R

USB_SS_RX2P

R172 0RR172 0R

20

GND

21

GND

23

GND

24

GND

25

GND

26

GND

27

GND

28

GND

29

GND

30

GND

SBD1SBD1+

SBD3+

USB_SS_TX2P17

USB_SS_TX2N USB_SS_TX2N_C USB_SS_TX2N_R

USB_SS_TX2N17

USB_SS_RX2P17

USB_SS_RX2N17

USB_SS_TX3P17

USB_SS_TX3N17

USB_SS_RX3P17

USB_SS_RX3N17

SBD13- SBD12-

USB12USB12+ USB13USB13+

USB_SS_RX2P USB_SS_RX2P_R

USB_SS_TX3P_C

R149 0RR149 0R

USB_SS_TX3N_C

R154 0RR154 0R

USB_SS_RX3N

R159 0RR159 0R

USB_SS_RX3P

R157 0RR157 0R

USB_SS_TX3N USB_SS_TX3N_RUSB_SS_TX3N_C

USB_SS_RX3P USB_SS_RX3P_R USB_SS_RX3N USB_SS_RX3N_R

SVCC7

U14

U14 CMD ( CM1293A-04SO )

CMD ( CM1293A-04SO )

52

614

3

R214 0RR214 0R R211 0RR211 0R R221 0RR221 0R R217 0RR217 0R

USB_SS_RX2N_R USB_SS_RX2P_R

USB_SS_TX2N_R USB_SS_TX2P_R

SBD12+ SBD12-

B

USB 3.0 trace length Rear connector within 8''

USB_SS_TX0P_C USB_SS_TX0N_C

USB_SS_RX0N USB_SS_RX0P

USB_SS_TX0P

USB_SS_TX0P17

USB_SS_TX0N

USB_SS_TX0N17

USB_SS_RX0P17

USB_SS_RX0N17

USB_SS_TX1P_C USB_SS_TX1N_C

USB_SS_RX1N USB_SS_RX1P

USB_SS_TX1P

USB_SS_TX1P17

USB_SS_TX1N

USB_SS_TX1N17

USB_SS_RX1P17

USB_SS_RX1N17

SVCC4

USB10USB10+ USB11USB11+

USB_SS_TX0P_R USB_SS_TX0N_R

USB_SS_RX0P_R USB_SS_RX0N_R

SBD11+ SBD11-

SBD10+ SBD10-

52

614

R398 0RR398 0R R404 0RR404 0R R399 0RR399 0R R406 0RR406 0R

SBD10SBD10+

C826

SBD10SBD10+

B

A

U59

USB_SS_TX0P_R

R248 0RR248 0R

USB_SS_TX0N_R

R377 0RR377 0R

USB_SS_RX0N_R

R378 0RR378 0R

USB_SS_RX0P_R

R357 0RR357 0R

USB_SS_TX1P_R USB_SS_TX1N_R

USB_SS_RX1N_R USB_SS_RX1P_R

SBD10SBD10+ SBD11SBD11+

USBA

9

SSTX2+

1

VBUS2

8

SSTX2-

2

D2-

4

GND

3

D2+

6

SSRX2+

7

GND_D

5

SSRX2-

USBAX2M_BLUE-RH

AVL:N53-18M0041-I60 N53-18M0021-F02

X_C5.6p50N0402

USB_SS_TX0P_C USB_SS_TX0N_C

USB_SS_TX1P_C USB_SS_TX1N_C

19

GND

20

C190 C0.1u10X0402C190 C0.1u10X0402 C443 C0.1u10X0402C443 C0.1u10X0402

USB_SS_RX0P USB_SS_RX0P_R

R150 0RR150 0R R392 0RR392 0R

R394 0RR394 0R R393 0RR393 0R

C160 C0.1u10X0402C160 C0.1u10X0402 C182 C0.1u10X0402C182 C0.1u10X0402

USB_SS_RX1P USB_SS_RX1P_R

U15

U15 CMD ( CM1293A-04SO )

CMD ( CM1293A-04SO )

SBD11SBD11+

3

SVCC3

C827

C829

C828

X_C5.6p50N0402

USB10+17 USB10-17

USB11+17

USB11-17

USB_SS_TX1P_R USB_SS_TX1N_R

USB_SS_TX0P_R USB_SS_TX0N_R

L62 X_CMC-L12-9008054-RHL62 X_CMC-L12-9008054-RH

4

L61 X_CMC-L12-9008054-RHL61 X_CMC-L12-9008054-RH

L27 X_CMC-L12-9008054-RHL27 X_CMC-L12-9008054-RH

4

L25 X_CMC-L12-9008054-RHL25 X_CMC-L12-9008054-RH

U59

1 2

4 5

3

USB_SS_TX0P_R

231

USB_SS_TX0N_R

231

USB_SS_RX0N_RUSB_SS_RX0N

U58

USB_SS_RX0P_R USB_SS_RX0N_R

USB_SS_RX1P_R USB_SS_RX1N_R USB_SS_RX1N_R

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

U58

1 2

4 5

3

USB_SS_TX1P_R

231

USB_SS_TX1N_R

231

USB_SS_RX1N_RUSB_SS_RX1N

L34

231

4

X_CMC-L12-9008014-RH

L28

231

4

X_CMC-L12-9008014-RH

USB_SS_TX1P_R USB_SS_TX1N_R

USB_SS_RX1P_R USB_SS_RX1N_R

Custom

SVCC4

SBD11SBD11+

USB

USBAX2M_BLUE-RH

MICRO-START INT'L CO.,LTD.

USB POWER/CONNECTORS

FUSION 1.0

A

USB_SS_TX1P_R

10

NC

USB_SS_TX1N_R

9

NC

USB_SS_TX0P_R

7

NC

USB_SS_TX0N_R

6

NC

X_ESD-IP4284CZ10-TB-RH

8

USB_SS_RX0P_R

10

NC

USB_SS_RX0N_R

9

NC

USB_SS_RX1P_R

7

NC

6

NC

X_ESD-IP4284CZ10-TB-RH

8

SBD10+ SBD10-

SBD11+ SBD11-

USBB

18

SSTX2+

10

VBUS2

17

SSTX2-

11

D2-

13

GND

12

D2+

15

SSRX2+

16

GND_D

14

SSRX2-

USBAX2M_BLUE-RH

21

GND

22

of

29 35Thursday, September 15, 2011

8

7

6

5

4

3

2

1

USB 2.0 0.5A pert port

VCC5

Place close to UP7533 pin1

C167

C646

C654

C648

VCC5

ATX_5VSB

1

2

U22

D D

5VDRV1_EN26

OC#117,20

USB_EN25

VCC5

5VDRV1_EN26

OC#517

USB_EN25

C C

5 6

4

EC61

12

+

X_.CD1000U6.3EL11.5

5 6

4

U22

S3# OC#

EN

U47

S3# OC#

EN

VOUT1

5VSB

5VCC

VOUT2

GND

UP7536AMA8_SOT23-8-HF

3

1

2

VOUT1

5VSB

5VCC

VOUT2

GND

UP7536AMA8_SOT23-8-HF

3

ATX_5VSB

SVCC1

7

8

C291

EC21

+

12

C0.1u16Y0402

.CD1000U6.3EL11.5

SVCC5

7

EC68

C645

8

C645

+

12

C0.1u16Y0402

.CD1000U6.3EL11.5

USB 3.0 0.9A pert port

ATX_5VSB

C488

C18000p16X0402

5VSBDRV126

5VDRV126

G2

G1

Q64

Q64 NP-P2003ND5G_TO252-5-RH

NP-P2003ND5G_TO252-5-RH

S2

D

S1

+5VUSB_FRONT1

C593

C593 X_10u10Y8

X_10u10Y8

+5VUSB_FRONT1

VCC5

B B

+5VUSB_FRONT1

60 mils

OC#317,20

+5VUSB_FRONT1

60 mils

OC#417

VCC5

5VDRV1_EN26

OC#217,20

USB_EN25

VCC5

5VDRV1_EN26

OC#617

USB_EN25

FS5

FS5 F-SMD1812P150TF-RH

F-SMD1812P150TF-RH

C983

C0.1U25Y0402-RH

FS6

FS6 F-SMD1812P150TF-RH

F-SMD1812P150TF-RH

U13

5

S3#

6

OC#

4

EN

U46

5

S3#

6

OC#

4

EN

R536

5.1KR

R456

10KR0402

R562

5.1KR

R457

C984

10KR0402

C0.1U25Y0402-RH

1

2

VOUT1

5VSB

5VCC

VOUT2

GND

UP7536AMA8_SOT23-8-HF

3

1

2

VOUT1

5VSB

5VCC

VOUT2

GND

UP7536AMA8_SOT23-8-HF

3

R439

R439 1KR0402

1KR0402

R440

R440 1KR0402

1KR0402

ATX_5VSB

7

8

ATX_5VSB

7

8

EC3

+

12

SVCC2

C165

EC8

+

12

C0.1u16Y0402

.CD1000U6.3EL11.5

ATX_5VSB

X_C0.1u16Y0402

C658

X_C0.1u16Y0402

SVCC1 SVCC5 SVCC6SVCC2 SVCC4 SVCC7

SVCC6

C289

EC67

C644

+

12

C0.1u16Y0402

.CD1000U6.3EL11.5

C289

C0.1u16Y0402

For EMI Placement close to ESD doide power pin.

USB power discharge circuit

R605 10KR0402R605 10KR0402

ATX_5VSB

R606 8.2KR0402R606 8.2KR0402

SVCC3

C84

C0.1u16Y0402

.CD1000U6.3EL11.5

SVCC4

EC4

C113

+

C0.1u16Y0402

.CD1000U6.3EL11.5

SLP_S5#17,25,26,27

X_C0.1u16Y0402

SVCC1

SVCC2

SVCC3

C642

1 3 5 7

N-2N7002_SOT23

1 3 5 7

N-2N7002_SOT23

1 3 5 7

X_N-2N7002_SOT23

C648

X_C0.1u16Y0402

Place close to UP7533 pin2

C158

C77

C286

X_C0.1u16Y0402

C151

C453

C0.1u16Y0402

SVCC_DIS

C641

Q71

C

X_C0.1u16Y0402

B

E

NPN-MMBT2222A-7

RN5

2 4 6 8

D

Q43

8P4R-270R

G

S

RN4

2 4 6 8

D

8P4R-270R

Q23

G

S

RN2

2 4 6 8

D

X_8P4R-270R

Q18

G

S

C293

C91

X_C0.1u16Y0402

C112

X_C0.1u16Y0402

C804

C114

X_C0.1u16Y0402

C656

C802

C655

X_C0.1u16Y0402

C669

C672

C742

C0.1u16Y0402

RN3

1

2

3

4

5

6

7

8

D

Q19

8P4R-270R

G

S

N-2N7002_SOT23

RN16

1

2

3

4

5

6

7

8

D

8P4R-270R

Q72

G

S

N-2N7002_SOT23

RN15

1

2

3

4

5

6

7

8

D

Q70

8P4R-270R

G

S

N-2N7002_SOT23

RN17

1

2

3

4

5

6

7

8

D

8P4R-270R

Q77

G

S

N-2N7002_SOT23

RN18

1

2

3

4

5

6

7

8

8P4R-270R

D

Q79

G

S

N-2N7002_SOT23

VCC5

ATX_5VSB

1

2

U7

5VDRV1_EN26

5

S3#

6

OC#017,20

USB_EN25

OC#

VOUT1

5VSB

5VCC

EN

VOUT2

GND

UP7536AMA8_SOT23-8-HF

3

4

SVCC7

7

EC75

C86

8

C86

+

12

C0.1u16Y0402

.CD1000U6.3EL11.5

VCC5

A A

5VDRV1_EN26

OC#717

USB_EN25

U10

5

S3#

6

OC#

4

EN

2

1

5VSB

5VCC

GND

UP7536AMA8_SOT23-8-HF

3

VOUT1

VOUT2

ATX_5VSB

7

8

SVCC8

C445

EC76

+

12

C0.1u16Y0402

.CD1000U6.3EL11.5

Lenovo Consumer MB common spec V0 2: Must reserve ESD protection diode on USB front header 5V_Dual power.

SVCC4 SVCC5 SVCC6SVCC1 SVCC2

12

SVCC4

SVCC5

12

D22

D12

D14

X_ESD-SFI0603ML080C-LF-RH

Use low-pass filter to prevent glitches duringplug/unplug events.

OC#0

C111 C0.1u16Y0402C111 C0.1u16Y0402

OC#1

C96 C0.1u16Y0402C96 C0.1u16Y0402

OC#2

C116 C0.1u16Y0402C116 C0.1u16Y0402

OC#5

C603 C0.1u16Y0402C603 C0.1u16Y0402

OC#6

C748 C0.1u16Y0402C748 C0.1u16Y0402

OC#7

C749 C0.1u16Y0402C749 C0.1u16Y0402

SVCC6

SVCC7

SVCC8

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

MICRO-START INT'L CO.,LTD.

USB POWER/DISCHARGE

FUSION 1.0

SVCC7

12

D48

D56

D49

X_ESD-SFI0603ML080C-LF-RH

of

30 35Thursday, September 15, 2011

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

PCI Express Slot x16

VCC3

R364 X_4.7KR0402R364 X_4.7KR0402 R365 X_4.7KR0402R365 X_4.7KR0402 R363 X_4.7KR0402R363 X_4.7KR0402

D D

C C

B B

A A

R366 X_4.7KR0402R366 X_4.7KR0402

GFX_TXC_15P8

GFX_TXC_15N8

GFX_TXC_14P8

GFX_TXC_14N8

GFX_TXC_13P8

GFX_TXC_13N8

GFX_TXC_12P8

GFX_TXC_12N8

GFX_TXC_11P8

GFX_TXC_11N8

GFX_TXC_10P8

GFX_TXC_10N8

GFX_TXC_9P8 GFX_TXC_9N8

GFX_TXC_8P8 GFX_TXC_8N8

GFX_TXC_7P8 GFX_TXC_7N8

GFX_TXC_6P8 GFX_TXC_6N8

GFX_TXC_5P8 GFX_TXC_5N8

GFX_TXC_4P8 GFX_TXC_4N8

GFX_TXC_3P8 GFX_TXC_3N8

GFX_TXC_2P8 GFX_TXC_2N8

GFX_TXC_1P8 GFX_TXC_1N8

GFX_TXC_0P8 GFX_TXC_0N8

PE_JTAG_TDI PE_JTAG_TMS PE_JTAG_TCK PE_JTAG_TRST#

PE_WAKE#17,24,25,32

GFX_TXC_15P GFX_TXC_15N

GFX_TXC_14P GFX_TXC_14N

GFX_TXC_13P GFX_TXC_13N

GFX_TXC_12P GFX_TXC_12N

GFX_TXC_11P GFX_TXC_11N

GFX_TXC_10P GFX_TXC_10N

GFX_TXC_9P GFX_TXC_9N

GFX_TXC_8P GFX_TXC_8N

GFX_TXC_7P GFX_TXC_7N

GFX_TXC_6P GFX_TXC_6N

GFX_TXC_5P GFX_TXC_5N

GFX_TXC_4P GFX_TXC_4N

GFX_TXC_3P GFX_TXC_3N

GFX_TXC_2P GFX_TXC_2N

GFX_TXC_1P GFX_TXC_1N

GFX_TXC_0P GFX_TXC_0N

SCLK117,32 SDATA117,32

VCC3

VCC3_WAKE

SCLK1

SDATA1

PE_JTAG_TRST#

PE_WAKE#

PCI EXPRESS x16 Slot

+12V

PCIE16X

X2

B1

12V#B1

B2

12V#B2

B3

RSVD#B3

B4

GND#B4

B5

SMCLK

B6

SMDAT

B7

GND#B7

B8

3.3V#B8

B9

JTAG1

B10

3.3VAUX

B11

WAKE#

B12

RSVD#B12

B13

GND#B13

B14

HSOP0

B15

HSON0

B16

GND#B16

B17

PRSNT2#

B18

GND#B18

B19

HSOP1

B20

HSON1

B21

GND#B21

B22

GND#B22

B23

HSOP2

B24

HSON2

B25

GND#B25

B26

GND#B26

B27

HSOP3

B28

HSON3

B29

GND#B29

B30

RSVD#B30

B31

PRSNT2##B31

B32

GND#B32

B33

HSOP4

B34

HSON4

B35

GND#B35

B36

GND#B36

B37

HSOP5

B38

HSON5

B39

GND#B39

B40

GND#B40

B41

HSOP6

B42

HSON6

B43

GND#B43

B44

GND#B44

B45

HSOP7

B46

HSON7

B47

GND#B47

B48

PRSNT2##B48

B49

GND#B49

B50

HSOP8

B51

HSON8

B52

GND#B52

B53

GND#B53

B54

HSOP9

B55

HSON9

B56

GND#B56

B57

GND#B57

B58

HSOP10

B59

HSON10

B60

GND#B60

B61

GND#B61

B62

HSOP11

B63

HSON11

B64

GND#B64

B65

GND#B65

B66

HSOP12

B67

HSON12

B68

GND#B68

B69

GND#B69

B70

HSOP13

B71

HSON13

B72

GND#B72

B73

GND#B73

B74

HSOP14

B75

HSON14

B76

GND#B76

B77

GND#B77

B78

HSOP15

B79

HSON15

B80

GND#B80

B81

PRSNT2##B81

B82

RSVD#B82

X1

SLOT-PCI164P_BLACK-2PITCH-RH-21

PRSNT1#

12V#A3

GND JTAG2 JTAG3 JTAG4 JTAG5

3.3V#A10 PWRGD

GND#A12 REFCLK+

REFCLK-

GND#A15

HSIP0 HSIN0

GND#A18

RSVD

GND#A20

HSIP1

HSIN1 GND#A23 GND#A24

HSIP2

HSIN2 GND#A27 GND#A28

HSIP3

HSIN3 GND#A31

RSVD#A32

RSVD#A33

GND#A34

HSIP4

HSIN4 GND#A37 GND#A38

HSIP5

HSIN5 GND#A41 GND#A42

HSIP6

HSIN6 GND#A45 GND#A46

HSIP7

HSIN7 GND#A49

RSVD#A50

GND#A51

HSIP8

HSIN8 GND#A54 GND#A55

HSIP9

HSIN9 GND#A58 GND#A59

HSIP10

HSIN10 GND#A62 GND#A63

HSIP11

HSIN11 GND#A66 GND#A67

HSIP12

HSIN12 GND#A70 GND#A71

HSIP13

HSIN13 GND#A74 GND#A75

HSIP14

HSIN14 GND#A78 GND#A79

HSIP15

HSIN15 GND#A82

3.3V

+12V

A1 A2

12V

A3 A4 A5 A6 A7 A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18

A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32

A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49

A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82

PE_JTAG_TCK PE_JTAG_TDI

PE_JTAG_TMS

PCIE_RST#

PE16_GXF_CLK PE16_GXF_CLK#

GFX_RX15P GFX_RX15N

GFX_RX14P GFX_RX14N

GFX_RX13P GFX_RX13N

GFX_RX12P GFX_RX12N

GFX_RX11P GFX_RX11N

GFX_RX10P GFX_RX10N

GFX_RX9P GFX_RX9N

GFX_RX8P GFX_RX8N

GFX_RX7P GFX_RX7N

GFX_RX6P GFX_RX6N

GFX_RX5P GFX_RX5N

GFX_RX4P GFX_RX4N

GFX_RX3P GFX_RX3N

GFX_RX2P GFX_RX2N

GFX_RX1P GFX_RX1N

GFX_RX0P GFX_RX0N

VCC3

From Clock Gen

PE16_GXF_CLK 16 PE16_GXF_CLK# 16

GFX_RX15P 8 GFX_RX15N 8

GFX_RX14P 8 GFX_RX14N 8

GFX_RX13P 8 GFX_RX13N 8

GFX_RX12P 8 GFX_RX12N 8

GFX_RX11P 8 GFX_RX11N 8

GFX_RX10P 8 GFX_RX10N 8

GFX_RX9P 8 GFX_RX9N 8

GFX_RX8P 8 GFX_RX8N 8

GFX_RX7P 8 GFX_RX7N 8

GFX_RX6P 8 GFX_RX6N 8

GFX_RX5P 8 GFX_RX5N 8

GFX_RX4P 8 GFX_RX4N 8

GFX_RX3P 8 GFX_RX3N 8

GFX_RX2P 8 GFX_RX2N 8

GFX_RX1P 8 GFX_RX1N 8

GFX_RX0P 8 GFX_RX0N 8

PCIE_RST# 16,24,32

PCIE_RST#

C428 X_C0.1u16Y0402C428 X_C0.1u16Y0402

+

12

EC34

CD470u16EL11.5-RH

Placement Close To PCIE16_X1

+12V

C427

C424

C425

C0.1u16Y0402

C424

X_C0.1u16Y0402

C0.1u16Y0402

C426

X_C0.1u16Y0402

VCC3_WAKEVCC3+12V

C436

C435

C0.1u16Y0402

X_C0.1u16Y0402

MICRO-START INT'L CO.,LTD.

Title

PCI EXPRESS X16

Size Document Number Rev

Custom

Date: Sheet

8

7

6

5

4

3

Date: Sheet

2

MICRO-START INT'L CO.,LTD.

FUSION 1.0

of

31 35Friday, April 29, 2011

1

8

D D

7

6

5

4

3

2

1

PCI EXPRESS X1 Slot-1 PCI EXPRESS X1 Slot-3

VCC3_WAKE

SCLK1

SCLK117,31

SDATA1

SDATA117,31

PE_WAKE#17,24,25,31

GPP_TXC_0P16

C C

GPP_TXC_0N16

PE_WAKE# PCIE_RST#

+12V +12V

PCIE1X_1

VCC3

PCIE1X_1

B1

12V

B2

12V#B2

B3

RSVD

B4

GND

B5

SMCLK

B6

SMDATA

B7

GND#B7

B8

3.3V

B9

JTAG1

B10

3.3VAUX

B11

WAKE_#

B12

RSVD#B12

B13

GND#B13

B14

HSOP0+

B15

HSOP0-

B16

GND#B16

B17

PRSNT2_#

B18

GND#B18

SLOT-PCI36_BLACK-2PITCH-RH-4

PRSNT1_#

12V#A2 12V#A3

GND#A4

JTAG2 JTAG3 JTAG4 JTAG5

3.3V#A9

3.3V#A10 PWRGD

GND#A12 REFCLK+

REFCLK-

GND#A15

HSIP0+

HSIP0-

GND#A18

X1

X2

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 X1

A12 A13 A14 A15 A16 A17 A18 X2

VCC3

PCIE_RST#

PCIE_RST# 16,24,31

PE1_GPP_CLK0 16 PE1_GPP_CLK0# 16

GPP_RX0P 16 GPP_RX0N 16

GPP_TXC_2P16 GPP_TXC_2N16

SCLK1 SDATA1

PE_WAKE#

VCC3_WAKE

+12V +12V

PCIE1X_3

VCC3

PCIE1X_3

B1

12V

B2

12V#B2

B3

RSVD

B4

GND

B5

SMCLK

B6

SMDATA

B7

GND#B7

B8

3.3V

B9

JTAG1

B10

3.3VAUX

B11

WAKE_#

B12

RSVD#B12

B13

GND#B13

B14

HSOP0+

B15

HSOP0-

B16

GND#B16

B17

PRSNT2_#

B18

GND#B18

SLOT-PCI36_BLACK-2PITCH-RH-4

PRSNT1_#

12V#A2 12V#A3

GND#A4

JTAG2 JTAG3 JTAG4 JTAG5

3.3V#A9

3.3V#A10 PWRGD

GND#A12 REFCLK+

REFCLK-

GND#A15

HSIP0+

HSIP0-

GND#A18

X1

X2

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 X1

A12 A13 A14 A15 A16 A17 A18 X2

VCC3

PE1_GPP_CLK2 16 PE1_GPP_CLK2# 16

GPP_RX2P 16 GPP_RX2N 16

+12V

PCI EXPRESS X1 Slot-2

SCLK1 SDATA1

PE_WAKE#

VCC3_WAKE

B B

GPP_TXC_1P16 GPP_TXC_1N16

A A

8

+12V +12V

PCIE1X_2

VCC3

7

PCIE1X_2

B1

12V

B2

12V#B2

B3

RSVD

B4

GND

B5

SMCLK

B6

SMDATA

B7

GND#B7

B8

3.3V

B9

JTAG1

B10

3.3VAUX

B11

WAKE_#

B12

RSVD#B12

B13

GND#B13

B14

HSOP0+

B15

HSOP0-

B16

GND#B16

B17

PRSNT2_#

B18

GND#B18

SLOT-PCI36_BLACK-2PITCH-RH-4

PRSNT1_#

12V#A2 12V#A3

GND#A4

JTAG2 JTAG3 JTAG4 JTAG5

3.3V#A9

3.3V#A10 PWRGD

GND#A12 REFCLK+

REFCLK-

GND#A15

HSIP0+

HSIP0-

GND#A18

X1

X2

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 X1

A12 A13 A14 A15 A16 A17 A18 X2

6

VCC3

PCIE_RST# PCIE_RST#

PE1_GPP_CLK1 16 PE1_GPP_CLK1# 16

GPP_RX1P 16 GPP_RX1N 16

5

VCC3

C472 X_C0.1u16Y0402C472 X_C0.1u16Y0402

VCC3_WAKE

4

C479

C470

C581

C0.1u16Y0402

C503

C471

C613

Place close to Pin A3,B3

C535

C572

X_C0.1u16Y0402

C532

C505

X_C0.1u16Y0402

C531

X_C0.1u16Y0402

3

C651

C619

X_C0.1u16Y0402

C612

C611

X_C0.1u16Y0402

MICRO-START INT'L CO.,LTD.

Title

PCIE X1 SLOTs

Size Document Number Rev

Custom

Date: Sheet

2

MICRO-START INT'L CO.,LTD.

FUSION 1.0

of

32 35Friday, April 29, 2011

1

8

7

6

5

4

3

2

1

ATX CONNECTOR

C0.1u16Y0402

ATX_5VSB

VCC3

R335

R334

R334 0R0402

0R0402

R335

10KR0402

D D

ATX_PSON#25

D71

1N4148W

X_C1000P50X0402

-12V

C0.1u16Y0402

VCC5

C0.1u16Y0402

C C

For EMI

SLED#

C670

C670 C0.1u16Y0402

C0.1u16Y0402

5VDIMM

B B

LED_SB

C673

C673 C0.1u16Y0402

C0.1u16Y0402

R492,R473 Pmax=(5*5)/300=0.083W Pspec=0.1W

VCC5

R636 330RR636 330R

YELLOW

Green

R638 330RR638 330R

C0.1u16Y0402 C363

C355

C388

C344

C363

25

3.3V

25

3.3V GND

GND

GND POK

5VSB

+12V +12V

1 2 3 4

5V

5 6

5V

7 8 9 10 11 12

13

3.3V

14

-12V

15

GND

16

P_ON

17

GND

18

GND

19

GND

20

-5V

21

5V

22

5V

23

5V GND243.3V

ATX_POWER

ATX_POWER PWRCONN24P_WHITE-1

PWRCONN24P_WHITE-1

LENOVO Front Panel Connector

F_PANEL

SLED# SUSLED PWRLED LED_SB PWRSW+ PWRSW-

R639

R639 300R

300R

1

HDD+

3

GNDL

5

SLED2

7

PLED1

9

PWSW+

11

PWSW-

NC7

H2X7[13]_black-2.6mm-RH

HDD-

SPK+

GND

NC2

SPK-

RESET

GNDR

2 4 6 8 10 12 14

C307

C0.1u16Y0402

C387

C387 C0.1u16Y0402

C0.1u16Y0402

HDD-

C671

C671 C0.1u16Y0402

C0.1u16Y0402

FP_RST#

C667

C667 C0.1u16Y0402

C0.1u16Y0402

C386

C386 C0.1u16Y0402

C0.1u16Y0402

C287

C287 C0.1u16Y0402

C0.1u16Y0402

C327

C327 C0.1u16Y0402

C0.1u16Y0402

Z

VCC5

SPK1

VCC3

VCC5

ATX_5VSB +12V

VCC3

D55

S-BAT54A_SOT23

Y X

C657

C4.7u6.3X5

R324

R324 10KR0402

10KR0402

ATX_PWROK 7,25,26,27

C336

C336 C1000P50X0402

C1000P50X0402

R637 X_4.7KR0402R637 X_4.7KR0402

SATA_LED#

Active by South Bridge

VCC3_SB

R640

4.7KR0402

VCC_DDR

VCC3_SB

Y

VCC5_SB

R520 X_1KR0402R520 X_1KR0402

X_C0.1u16Y0402

VCC3

SATA_LED# 18

BAV99

D53

X

Z

R558 X_1KR0402R558 X_1KR0402

C570

FP_RST# 17,25,27

VCC3

B

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

D

G

S

CE

Q61

Q61 X_N-SST3904_SOT23

X_N-SST3904_SOT23

RN9

RN9 X_8P4R-10R

X_8P4R-10R

RN12

RN12 X_8P4R-10R

X_8P4R-10R

Q65

Q65 X_N-2N7002_SOT23

X_N-2N7002_SOT23

VCCP

POWER LED

C0.1u16Y0402

power LED definition

VCC5_SB

R391 X_1KR0402R391 X_1KR0402

X_C0.1u16Y0402

SUSLED

CE

C647

PWRLED

CE

C650

R410 X_1KR0402R410 X_1KR0402

B

C444

5VDIMM

R607 X_300RR607 X_300R R624 X_4.7KR0402R624 X_4.7KR0402

B

Q74

Q74 X_N-SST3904_SOT23

X_N-SST3904_SOT23

5VDIMM

R593 300RR593 300R R602 4.7KR0402R602 4.7KR0402

B

Q73

Q73 N-SST3904_SOT23

N-SST3904_SOT23

VCC5

1 3 5 7 1 3 5 7

CE

Q56

Q56 X_N-SST3904_SOT23

X_N-SST3904_SOT23

SUS_LED

PWR_LED

2

RN6

4

X_8P4R-10R

6 8 2

RN7

4

X_8P4R-10R

6 8

D

Q58

G

S

X_N-2N7002_SOT23

SUS_LED 25

PWR_LED 25

VCC5

D47

D47 BAS32L_LL34

BAS32L_LL34

RN11

1

Q63

7

3 5 7

2 4 6 8

8P4R-150R

C606

C606 C0.1u16Y0402

C0.1u16Y0402

BUZZER

A A

R539 1KR0402R539 1KR0402

SPKR17

8

C

B

E

NPN-MMBT2222A-7

SPK1

VCC5

1 2

BZ1

BUZZER-RH

6

POWER BUTTON

ATX_5VSB ATX_5VSB

BAV99

D50

PWRSW+

5

Y

C668

C668 C0.1u16Y0402

C0.1u16Y0402

X

Z

R633 100R0402R633 100R0402

12

4

R625

8.2KR0402

PSIN# 25

C649

C649 C0.01U16X0402

C0.01U16X0402

MICRO-START INT'L CO.,LTD.

Title

ATX & FRONT PANEL

Size Document Number Rev

B

Date: Sheet

3

Date: Sheet

MICRO-START INT'L CO.,LTD.

FUSION 1.0

2

33 35Friday, April 29, 2011

of

1

8

7

6

5

4

3

2

1

981

X_MH001

4

2 3

Pangkor

U902

HUDSON

HUDSON D2

D2

HUDSON D2

U909

ALC662

ALC662-VC1-GR

U910

AUDIO JACK

AUDIO 1X3

U912

75R

R11-0750012-W08

R11-0750012-W08 U913

U913

0R

R11-0000012-W08

MH3

7 6

5

N54-13F0211-S42

981

2 3

X_MH001

4

HEAT SINK

U14_X1

XX1

D D

XX2

FCH_HEATSINK

HDMI_Logo

HDMI Logo

Y01-RHDMI03-000

Rubber2

Rubber1

PCB

rubber1/2

MANUAL PART

C C

AVL: D06-0100161-F52 D06-0100101-K26

BAT1_X1

BAT-CR2032-RH

PCB1

P30-077020C-E36

GBM ( PF0-0770210-G37 )

B B

USB_LAN

USB_LAN CONN

CONN

RJ45_USBX2

RJ45_USBX2 AUDIO

AUDIO

AUDIO JACK

AUDIO 2X3

HDMI_USB

HDMI

HDMI USB

USB

HDMI_USBX2

6KV Giga 15u N58-22F1261-I60

2*3 N54-26F0091-K06

10/100M

1*3 N54-13F0331-K06 N54-13F0211-S42

MH1

7 6

5

981

X_MH001

4

MH2

2 3

7 6

5

Optics Orientation Holes

FM3

X_FM120

FM5

X_FM120

FM8

A A

X_FM120

FM4

X_FM120

8

FM2

X_FM120

FM6

X_FM120

FM1

X_FM120

FM7

X_FM120

Simulation

X_JS1

SIM2

X_JS1

SIM1

X_PIN1*2

X_JS2

X_PIN1*2

7

VCC5

6

MH4

7 6

MH8

7 6

5

981

X_MH001

4

981

X_MH001

4

5

2 3

MH5

7 6

MH7

7 6

5

981

X_MH001

4

981

X_MH001

4

2 3

4

7 6

MH6

5

981

X_MH001

4

2 3

MICRO-START INT'L CO.,LTD.

Title

Auto BOM Mnaual

Size Document Number Rev

B

Date: Sheet

3

Date: Sheet

MICRO-START INT'L CO.,LTD.

FUSION 1.0

2

34 35Tuesday, August 16, 2011

of

1

5

110105

1,ATX_PSON# (R335) PU to ATX_VSB and reserve D71

2,C99 change to 680pF; C16,C44 change to 1500pF for bom

3,SP1,SP2 change to 5010

4,R27,R28,R116,R140 change to 0402 footprint

5,Reserve R560

6,Stuff R193 and Reserve R206.Sabine HDMI Design Guidance HDMI enable strapping:TEST35 PU TO VCC_DDR thru 300R

1101216

D D

7, remove MINI_PCIE

8, PCIEX1 change PN to N11-0360241-L06 , N11-0360251-F02 , N11-0360051-K06(15u)

8, C299,C335=180pF,C559=1000pF,R592=33R;R529=33R,C122=15pF,C120=22pF Add C300=180pF,R556,R584=22R; unstuff C584,R665

9, Remove Q66,R583;Reserve U55.Co-lay D3

1101222 10,F_USB_30 modify to N11-0360201-F02(white)

11,C771, C774, C775, C776, C777, C779 add 104pF/0402 capacitor (for EMI)

12,U34

、

U57、U58、U59 add D0G-05A0500-N47(for EMI)

13,Add Q35,L54,L55 to fix VDDPL_11_SYS_S leakage issue

14,Remove R523,and route RTC_CLK away from 32K to fix RTC clk too fast issue

15,Reserve C20 for Linear power soft start(RC)

16,D23,D24 PU change to VDD_VGA_HDMI

17,EC46 change to 470u OS-con(To meet Lenovo TV card)

18,R391 change to VCCP

19,Remove Y4 (SATA_25) and reserve TP only

20,D43 change to D01-0523500-O05 ( MMSZ5235BT1G )

21,CHOKE8 change to L04-47A7760-T04

22,PCIE16X change to PN11-1640781-F02(SLOT_PCIEXP164_4) (AVL:N11-1640761-L06)

C C

23,Add EC77(C71-471022E-S03),outpout caps change to C71-8210271-N07 C697,C700,C705,C710 change to ASM-5010

24,Add Q36,Reserve U64 for VDUAL_EN control

25,Reserve R413,R523,R530 for POS adjusting

26,C536,C548,C529,C391,C245,C193,C391,C480 change to X7R or X5R

27,Audio codec (U39) change to PN:B05-LC89214-R09 (ALC892-CG)

110303 28, U600 change to PN:B01-2180745-A08(D3), B01-2180755-A08(D2)

29, Add VRM power solution

30,Reserve R438,RT3

110307

31,Add C448,C313

32,KB_MS footprint change to PS_12P

110311

33,R628 change to 8.2KR; C45=2.2uF,C94 NC(fix SI pos fail)

34,R237=10KR,R371=12.7KR (Fix ocp)

35,C276,C258,C264,C266,C274,C256=1pF; L17,L18,L21=0R;C257,C267,C275 NC,C229,C250 NC(Tune VGA)

36,R324 change to 10KR(ATX_PWROK step risk issue)

B B

110326

36,update VRM power solution

110418 Modify ESATA (SPEC : eSATA) , SYS_FAN1 (SPEC : SYS_FAN) , PWR_FAN1 (SPEC : PWR_FAN) , SEN_HEADER (THER_HD) , USB1 (USB)

change COM2 ref to COM1 Add C10 C22 0.1uF for BOM Add EC65 1000UF for BOM Remove U58 U59 for BOM

110420 Change BAT1 to N91-01F0201-L06

4

3

2

1

A A

MICRO-START INT'L CO.,LTD.

HISTORY

FUSION 1.0

1

36 35Friday, April 29, 2011

of

1013

Title

Size Document Number Rev

Custom

Date: Sheet

5

4

3

2

Date: Sheet

MSI MS-7702 Schematics rev1.0

Specifications and Main Features

Frequently Asked Questions

User Manual