MSI MS-7389L2 Schematics
1
VL390 FOR uBTX
Cover Sheet
BLOCK DIAGRAM
1
2
CPU:
AMD AM3
3GPIO Configuration
Clock Distribution
Power Deliver Chart
VRM Intersil 6323 3 Phase
AMD Socket AM3
DDR III DIMM 1 & 2 & 3 & 4
Clock Gen SLG8LP625
AMD - RS780
AMD - SB710
A A
DVI / VGA Connector
SATA/KB/ FAN Control
LAN-Realtek 8111CP
LPC I/O ITE8720
ACPI UPI & SYS POWER
Core Power & DDR Power
Azalia CODEC ALC662/888
USB CONNECTORS
PCI EXPRESS X16 & X 1 SLOT
4
5
6
7 ~ 9
10 ~ 11
12
13 ~ 16
17 ~ 21
22
23
24
25
26
27
28
29
30
System Chipset:
AMD - RS780(North Bridge)
AMD - SB710 (South Bridge)
On Board Chipset:
BIOS - SPI
Azalia CODEC - Realtek ALC662(Default)/888
LPC Super I/O -- ITE8720
CLOCK GEN --SLG8LP625
LAN-Realtek 8111CP
TMP - INFINEON/SLB9635T
Main Memory:
DDR III * 4
Expansion Slots:
PCI Express X16 Slot * 1
PCI Express X1 Slot * 1
PCI 2.3 Slot * 2
PCI Slot 1&2
TMP
ATX & Front Panel
Auto BOM Manual
History
History
31
32
33
34
35
36
Intersil PWM:
Controller - Intersil 6323 3 Phase
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
COVER SHEET
COVER SHEET
COVER SHEET
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
1
Date: Sheet
MICRO-START INT'L CO.,LTD.
VL390 0A
VL390 0A
VL390 0A
of
of
of
137Tuesday, September 09, 2008
137Tuesday, September 09, 2008
137Tuesday, September 09, 2008
5
4
3
2
1
Project RS-780 BLOCK DIAGRAM
DDRIII 800~1333
D D
AMD AM3
AM3 SOCKET
7,8,9
OUT
16x16 2.6GHZ(HT3)HyperTransport LINK
IN
128bit
DDRIII 800~1333
128bit
UNBUFFERED
DDRIII DIMM1
UNBUFFERED
DDRIII DIMM2
DDRIII FIRST LOGICAL DIMM DDRIII SECOND LOGICAL DIMM
10
10
UNBUFFERED
DDRIII DIMM3
UNBUFFERED
DDRIII DIMM4
11
11
Display Port
ATI NB - RS780
HyperTransport LINK0 CPU I/F
1 16X PCIE VIDEO I/F
USB 2.0
1 4X PCIE I/F WITH SB
2 1X PCIE I/F
A-LINK
4X PCIE
ATI SB - SB710
USB2.0 (12)
SATA2 (4 PORTS)
AC97 2.3
HD AUDIO 1.0
ACPI 1.1
SPI I/F
PCI/PCI BRIDGE
ASF
17,18,19,20,21
ITE SIO
IT8720
13,14,15,16
LPC BUS
26
AZALIA
SERIAL ATA 2.0
SPI Bus
HD AUDIO HDR
AZALIA CODEC
SATA#0 SATA#1
SPI ROM 8M
TPM
33
29
29
SATA#2 SATA#3
24
24 24 24
19
PCIE GFX x16
C C
4X1 PCIE INTERFACE
Gbit ETHERNET
30
IEEE-1394
23
8039/8056
/8071/8075
USB-4USB-5
30 30 30 30 30
HDR HDR HDR HDR
PCIE x1 SLOT1,2
USB-1USB-2USB-3
USB-7USB-8USB-9
31
USB-0
REARREARREARREARREARREAR
USB-6
PCIE x16
3125
30303030
B B
PCI BUS
ACPI CONTROLLER
UPi
CPU CORE POWER
NB CORE POWER
Intersil ISL6323
Intersil ISL6612A
PCI SLOT
6
30
27
CPU VLDT Power
CPU VDDR Power
CPU VDDA Power
DUAL POWER
A A
NB & SB POWER
27
DDR3 DRAM POWER
RS780 CORE POWER
ATX CON
5
28
FLOPPY
KBD
MOUSE
26
34
4
3
SERIAL
PORT
24 26
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
BLOCK Diagram
BLOCK Diagram
BLOCK Diagram
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
VL390 0A
VL390 0A
VL390 0A
237Tuesday, September 09, 2008
237Tuesday, September 09, 2008
237Tuesday, September 09, 2008
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1
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5
4
3
2
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SB700/710 GPIO Config
GPIO Name Type Function description Pin
CLK_REQ0#/SATA_IS3#/GPIO0
SMARTVOLT/SATA_IS2#/GPIO4
D D
C C
B B
CLK_REQ3#/SATA_IS1#/GPIO6
DDC1_SDA/GPIO8
DDC1_SCL/GPIO9
SATA_IS0#/GPIO10
SPI_DO/GPIO11
BMREQ#/REQ5#/GPIO68
LAN_RST#/GPIO13
ROM_RST#/GPIO14
SPI_HOLD#/GPIO31 SPI_HOLD_L
SPI_CS#/GPIO32 SPI_CS#
CLK_REQ1#/GPIO39 Not connected (internal pull-down).
CLK_REQ2#/GPIO40
PCICLK5/GPIO41 Terminated with a strapping resistor
AZ_SDIN0/GPIO42 SDATA_IN_R
AZ_SDIN1/GPIO43 Not connected (internal pull-down)
AZ_SDIN2/GPIO44
AZ_SDIN3/GPIO46
GPIO[49:48]/ FANOUT[2:1]]
GPIO[52:50]/ FANIN[2:0]
GPIO[60:53]/ VIN[7:0]
GPIO[63:61]/ TEMPIN[2:0]
GPIO64/ TALERT#/ TEMPIN3
GPIO65/ BMREQ#/ REQ5#
GPIO66/ LLB#
GPIO67/ SATA_ACT#
GPIO68/ LDRQ1#/ GNT5#
GPIO[71:70]/ REQ[4:3]#
GPIO[73:72]/ GNT[4:3]#
GPOC0#/ SCL0
GPOC1#/ SDA0
GPOC2#/ SCL1
GPOC3#/ SDA1 SDATA1
USB_OC[5:0]#/GPM[5:0]#
SYS_RESET#/GPM7#
AZ_DOCK_RST#/GPM8#
SLP_S2/GPM9#
NOTE1
Configured for one of these options:
"10-k? 5% pull-up resistor to +3.3V_S0.
"10-k? 5% pull-down resistor.
"Configured GPIO to output mode.
"Configured for internal pull-up or pull-down resistor.
3.3V Not connected(internal pull-down)
SPKRSPKR/GPIO2
Not connected (internal PU to +3.3V_S0)FANOUT0/GPIO3
CPU_PRESENT#:CPU present detect
R377 10KR to GNDSHUTDOWN#/GPIO5
Note1
Note1
Note1
Note1
SPI_DATAOUT
SPI_DATAIN
Reserve TP
Not connected (defaults to output driven low)
Not connectedGPIO[30:15]/IDE_D[15:0]
Not connected (internal pull-down)
Not connected (internal pull-down)
Not connected (internal pull-down)
SPI_CLKSPI_CLK/GPIO47
Not connected (internal pull-up to +3.3V_S0)
Note1
Note1
Note1
TALERT#
Note1
LC_SENSE
SATA_LED#
Reserve TP54
Not connected (internal pull-up to +3.3V_S0)
Not connected (defaults to output HIGH).
SCLK
SDATA
SCLK1
OC#[6::1]
FP_RST#
Not connected (internal pull-up to +3.3V_S5).
GFX16_PCIERST#
SIO IT8720 GPIO Config
GPIO Name Type Function description Pin
VDIMM_STR_EN / PCIRST3#/GP10
SMARTVOLT/SATA_IS2#/GPIO4
CLK_REQ3#/SATA_IS1#/GPIO6
DDC1_SDA/GPIO8
DDC1_SCL/GPIO9
SATA_IS0#/GPIO10
SPI_DO/GPIO11
BMREQ#/REQ5#/GPIO68
LAN_RST#/GPIO13
ROM_RST#/GPIO14
SPI_HOLD#/GPIO31 SPI_HOLD_L
SPI_CS#/GPIO32 SPI_CS#
CLK_REQ1#/GPIO39 Not connected (internal pull-down).
CLK_REQ2#/GPIO40
PCICLK5/GPIO41 Terminated with a strapping resistor
AZ_SDIN0/GPIO42 SDATA_IN_R
AZ_SDIN1/GPIO43 Not connected (internal pull-down)
AZ_SDIN2/GPIO44
AZ_SDIN3/GPIO46
GPIO[49:48]/ FANOUT[2:1]]
GPIO[52:50]/ FANIN[2:0]
GPIO[60:53]/ VIN[7:0]
GPIO[63:61]/ TEMPIN[2:0]
GPIO64/ TALERT#/ TEMPIN3
GPIO65/ BMREQ#/ REQ5#
GPIO66/ LLB#
GPIO67/ SATA_ACT#
GPIO68/ LDRQ1#/ GNT5#
GPIO[71:70]/ REQ[4:3]#
GPIO[73:72]/ GNT[4:3]#
GPOC0#/ SCL0
GPOC1#/ SDA0
GPOC2#/ SCL1
GPOC3#/ SDA1 SDATA1
USB_OC[5:0]#/GPM[5:0]#
SYS_RESET#/GPM7#
AZ_DOCK_RST#/GPM8#
SLP_S2/GPM9#
3.3V Not connected(internal pull-down)
SPKRSPKR/GPIO2
Not connected (internal PU to +3.3V_S0)FANOUT0/GPIO3
CPU_PRESENT#:CPU present detect
R377 10KR to GNDSHUTDOWN#/GPIO5
Note1
Note1
Note1
Note1
SPI_DATAOUT
SPI_DATAIN
Reserve TP
Not connected (defaults to output driven low)
Not connectedGPIO[30:15]/IDE_D[15:0]
Not connected (internal pull-down)
Not connected (internal pull-down)
Not connected (internal pull-down)
SPI_CLKSPI_CLK/GPIO47
Not connected (internal pull-up to +3.3V_S0)
Note1
Note1
Note1
TALERT#
Note1
LC_SENSE
SATA_LED#
Reserve TP54
Not connected (internal pull-up to +3.3V_S0)
Not connected (defaults to output HIGH).
SCLK
SDATA
SCLK1
OC#[6::1]
FP_RST#
Not connected (internal pull-up to +3.3V_S5).
GFX16_PCIERST#
A A
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
GPIO Configuration
GPIO Configuration
GPIO Configuration
VL390 0A
VL390 0A
VL390 0A
1
337Tuesday, September 09, 2008
337Tuesday, September 09, 2008
337Tuesday, September 09, 2008
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5
4
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1
DIMM3 DIMM4
D D
DIMM1 DIMM2
2 PAIR MEM CLK
2 PAIR MEM CLK
AM3 CPU
AM3SOCKET
C C
B B
2 PAIR MEM CLK
2 PAIR MEM CLK
1 PAIR CPU CLK
200MHZ
HT REFCLK
100MHz DIFF(RX780/RS780)
EXTERNAL
CLK GEN.
Y1
NB-OSCIN
14.318MHZ
NB ALINK PCIE CLK
100MHZ
SB ALINK PCIE CLK
100MHZ
NB GFX PCIE CLK
100MHZ
PCIE GFX CLK
100MHZ
PCIE GPP CLK
100MHZ
PCIE GPP CLK
100MHZ
PCIE GPP CLK
100MHZ
PCIE GPP CLK
100MHZ
USB CLK
48MHZ
SIO CLK
48MHZ
AMD NB
RS780/RS740
PCIE GFX SLOT 1 - 16 LANES
PCIE GPP SLOT 1 - 1 LANE
PCIE GPP SLOT 2 - 1 LANES
PCIE GBE
PCIE IEEE1394
25MHZ
OSC
INPUT
24.576MHZ
OSC INPUT
25MHz
LAN
Y2
Y4
24.576MHz
1394
CPU_HT_CLK
NB_HT_CLK
25M_48M_66M_OSC
AMD SB
SB700
NB_DISP_CLK
GPP_CLK3
PCIE_RCLK/
NB_LNK_CLK
SLT_GFX_CLK
GPP_CLK0
GPP_CLK1
GPP_CLK2
USB_CLK
Y3
PCI CLK0
33MHZ
PCI CLK1
33MHZ
PCI CLK2
33MHZ
PCI CLK3
33MHZ
PCI CLK4
33MHZ
PCI CLK5
33MHZ
LPC_CLK0
33MHZ
LPC CLK1
33MHZ
SB_BITCLK
48MHZ
Y5
32.768KHz
PCI SLOT 0 33MHz
SUPER IO IT8720
TPM 33MHz
HD AUDIO
ALC 662/888
Y6
14.318MHz
25MHz SATA
14.31818MHz
A A
5
External clock mode
Internal clock mode
4
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Clock Distribution Chart
Clock Distribution Chart
Clock Distribution Chart
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
3
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
VL390 0A
VL390 0A
VL390 0A
437Tuesday, September 09, 2008
437Tuesday, September 09, 2008
437Tuesday, September 09, 2008
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of
1
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5
Power Deliver Chart
4
3
2
1
2.5V Shunt
Regulator
VRM SW
REGUALTOR
D D
ATX P/S WITH 1A STBY CURRENT
5V
5VSB
+/-5%
+/-5%
3.3V
+/-5%
12V
+/-5%
-12V
+/-5%
CPU
PW
12V
+/-5%
5VDIMM Linear
REGULATOR
1.8V VDD SW
REGULATOR
1.8V VCC Linear
REGULATOR
VDDA25 (S0, S1)
VCCP (S0, S1) / VCC_NB (S0, S1)
0.9V VTT_DDR
REGULATOR
1.1V VCC Linear
REGULATOR
1.2V VCC Linear
REGULATOR
VCC_DDR (S0, S1, S3)
VTT_DDR (S0, S1, S3)
DDRII DIMMX4
VDD MEM
12A
VTT_DDR
2A
NB_VCC1P1 (S0, S1)
VCC_1V2 (S0, S1)
+1.8V_S0 (S0, S1)
C C
AMD AM2r2 CPU
VDDA 2.5V 0.2A
VDDCORE
0.8-1.55V
DDR2 MEM I/F
VDD MEM 1.8V
VTT MEM 0.9V
VLDT 1.2V
NB RS780
VDDHT/RX 1.1V
VDDHTTX 1.2V
VDDPCIE 1.1V
NB CORE VDDC
1.1V
VDDA18PCIE 1.8V
PLLs 1.8V
VDD18/VDD18_MEM
1.8V
VDD_MEM 1.8V/1.5V
AVDD 3.3V
110A
10A
2A
0.5A
1.2A
0.5A
2A
7A
0.9A
0.1A
0.01A
0.5A
0.135A
SB700
VCC3_SB Linear
REGULATOR
VCC3_SB (S0, S1, S3, S5)
1.2V_SB Linear
REGULATOR
+1.2VSB (S0, S1)
VCC3_SB (S0, S1, S3, S5)
VCC3 (S0, S1)
+5VA Linear
B B
5VDUAL Linear
REGULATOR
REGULATOR
+5VA (S0, S1)
VCC3_SB (S0, S1, S3, S5)
X4 PCI-E
ATA I/O
ATA PLL
PCI-E PVDD
SB CORE
CLOCK
1.2V S5 PW
3.3V S5 PW
USB CORE I/O
3.3V I/O
AUDIO CODEC
3.3V CORE
5V ANALOG
+3.3VDUAL (S3)
+3.3V (S0, S1)
+5V (S0, S1)
0.8A
0.5A
0.01A
80mA
0.6A
0.22A
0.01A
0.2A
0.45A
0.1A
0.1A
SUPER I/O
0.01A
0.01A
0.1A
5.0A
7.6A
0.5A
0.1A
X1 PCIE per
3.3V
12V
3.3Vaux
PCI Slot (per slot)
A A
5
5V
3.3V
12V
3.3VDual
-12V
0.375A
3.0A
0.5A
0.1A
4
X16 PCIE per
3.3V
12V
3.3VDual
3.0A
5.5A
0.1A
USB X4 FR
VDD
5VDual
2.0A
USB X6 RL 2XPS/2
VDD
5VDual
3.0A
3
5VDual
0.5A
ENTHENET
3.3V (S3)
3.3V (S0, S1)
0.1A
0.5A
IEEE-1394 x1
3.3V (S0, S1)
12V (S0, S1) 1.1A
0.1A
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet
Date: Sheet
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
Power Deliver Chart
Power Deliver Chart
Power Deliver Chart
VL390 0A
VL390 0A
VL390 0A
1
537Tuesday, September 09, 2008
537Tuesday, September 09, 2008
537Tuesday, September 09, 2008
of
of
of
5
4
3
2
1
Intersil 6323 3 Phase
+12VIN
Make sure +12vin
connect plug in
R38
B
R63
R63
10KR0402
10KR0402
X_C680P50X0402
X_C680P50X0402
R59
R59
C8
C8
R4
R4
C24
C24
X_C0.1U16Y0402
X_C0.1U16Y0402
R38
10KR0402
10KR0402
CE
1KR0402
1KR0402
Q97
Q97
N-MMBT3904
N-MMBT3904
R206 X_0R0402R206 X_0R0402
C42
C42
C40
C40
X_C0.1U16Y0402
X_C0.1U16Y0402
C38
C38
X_C0.1U16Y0402
X_C0.1U16Y0402
1.2KR1%0402
1.2KR1%0402
R34
R34
R17
R17
1.3KR1%0402
1.3KR1%0402
C30
C30
C587 C0.1U10X0402C587 C0.1U10X0402
R37 56KR1%0402R37 56KR1%0402
R19 59KR1%0402R19 59KR1%0402
R28
R28
X_10KR0402
X_10KR0402
R36
R36
0.85V Threshold
VRM_PWROK
TP8TP8
TP9TP9
TP10TP10
R69
R69
1.2KR1%0402
1.2KR1%0402
C44 C10P50N0402C44 C10P50N0402
ISEN_NB_A
R53 0R0402R53 0R0402
R54 X_0R0402R54 X_0R0402
C0.01U16X0402
C0.01U16X0402
1 2
C7 C33P50N0402C7 C33P50N0402
C19 C0.01U16X0402C19 C0.01U16X0402
COREFB+
COREFB-
R16
R16
4.99KR1%0402
4.99KR1%0402
VRM_SET
VCC5
120KR1%0402
120KR1%0402
C20 C0.1U16Y0402C20 C0.1U16Y0402
VR_VID5
VR_VID4
VR_FIXEN
C0.01U16X0402
C0.01U16X0402
1 2
C48
C48
C23
C23
12
C0.1U16Y0402
C0.1U16Y0402
C22
C22
OFS
R47
R47
X_100KR0402
X_100KR0402
R45
R45
R39
R39
2.2R0805
2.2R0805
7X7 QFN
U1
U1
24
EN
37
VDDPWRGD
34
PWROK
9
VID5
8
VID4
7
VID3/SVC
6
VID2/SVD
5
VID1/SEL
4
VID0/VFIXEN
48
COMP_NB
1
FB_NB
2
VSEN_NB
3
RGND_NB
18
COMP
17
FB
15
RCOMP
13
VSEN
12
RGND
19
APA
16
RESET
14
OFS
11
FS
BOTTOM PAD
CONNECT TO GND
Through 8 VIAs
VCC5
C32
C32
C4.7U10Y0805
C4.7U10Y0805
10
PVCC1_2
VCC
BOOT1
UGATE1
PHASE1
LGATE1
ISEN1+
ISEN1-
BOOT2
UGATE2
PHASE2
LGATE2
ISEN2+
ISEN2-
PWM3
ISEN3+
ISEN3-
PWM4
ISEN4+
ISEN4-
PVCC_NB
BOOT_NB
UGATE_NB
PHASE_NB
LGATE_NB
ISEN_NB
GND
49
ISL6323CRZ_QFN48-RH
ISL6323CRZ_QFN48-RH
+12VIN
R51
R51
2.2R0805
2.2R0805
C35
C35
C1U16X5
C1U16X5
29
R52 2.2R1%0805R52 2.2R1%0805
31
U_G1
32
PHASE1
33
L_G1
30
20
ISEN1-
21
PHASE11
R46 2.2R1%0805R46 2.2R1%0805
27
U_G2
26
PHASE2
25
L_G2
28
ISEN2+
22
ISEN2-
23
PHASE22
PWM3
35
ISEN3+
44
ISEN3-
43
PHASE33
36
Disable PWM4 Use 3phase
46
45
VCC5
R70 2.2R1%0805R70 2.2R1%0805
42
C52 C1U25X0805C52 C1U25X0805
R68
R68
40
2.2R1%0805
2.2R1%0805
UGATE_NB
39
PHASE_NB
38
LGATE_NB
41
47
PHASE_NB_A ISEN_NB_A
R62
R62
5.6KR1%0402
5.6KR1%0402
LDT_PWRGD7,17
C41 C0.1U25XC41 C0.1U25X
R33 200R1%0402R33 200R1%0402
R32
R32
4.32KR1%0402
4.32KR1%0402
C27 C0.1U25XC27 C0.1U25X
R31 150R1%0402R31 150R1%0402
R30
R30
4.32KR1%0402
4.32KR1%0402
R65 0R0402R65 0R0402
R64
R64
4.32KR1%0402
4.32KR1%0402
C51 C0.1U25XC51 C0.1U25X
R75 X_6.2KR1%0402R75 X_6.2KR1%0402
C53
C53
C0.1U16Y0402
C0.1U16Y0402
C5
C5
C0.1U16Y0402
C0.1U16Y0402
C3
C3
C0.1U16Y0402
C0.1U16Y0402
C54
C54
C0.1U16Y0402
C0.1U16Y0402
+12VIN
ISEN1ISEN1+
ISEN2
ISEN3
C6
C4
C55
C55
C0.1U16Y0402C6C0.1U16Y0402
C0.1U16Y0402C4C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
VCC5_SB
R637
R637
10KR0402
10KR0402
VCORE_EN#
VCORE_EN#26
D D
R636 10KR0402R636 10KR0402
VCC5
VRM_GD26
NB_PWRGD15,26
VID3_SVC7
VID2_SVD7
VID1_SEL7
CPU_VDDNB
R58
R58
100R0402
100R0402
V_NB7
X_C0.1U16Y0402
X_C0.1U16Y0402
C C
V_GND7
R50
R50
100R0402
100R0402
COREFB+7
100R0402R5100R0402
COREFB-7
100R0402
100R0402
R5
R42
R42
C39
C39
VCCP
R57
R57
X_470R1%0402
X_470R1%0402
360R1%0402
360R1%0402
X_470R1%0402
X_470R1%0402
R18
R18
X_C1000P50X0402
X_C1000P50X0402
560R1%0402-RH
560R1%0402-RH
C26
C26
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
VCC5
VCC5
B B
R584
R584
4.7KR0402
4.7KR0402
B
CE
Q100
Q100
N-MMBT3904
N-MMBT3904
VCC3VCC_DDR
+12VIN
R191
R191
2.2R0805
2.2R0805
C271
C271
C1U25X0805
C1U25X0805
PWM3
R580
R580
10KR0402
10KR0402
VRM_PWROKLDT_PWRGD
U11
U11
6
VCC
7
PVCC
4
GND
3
PWM
ISL6612ACBZT_SOIC8-RH
ISL6612ACBZT_SOIC8-RH
UGATE
BOOT
PHASE
LGATE
U_G1
PHASE1
L_G1
U_G2
PHASE2
L_G2
1
2
R186
R186
2.2R1%0805
2.2R1%0805
8
5
R137 1R0805R137 1R0805
R151 1R0805R151 1R0805
U_G3
PHASE3
L_G3
R136
R136
10KR0402
10KR0402
N-NTD4806NT4G_DPAK3-RH
N-NTD4806NT4G_DPAK3-RH
R152
R152
10KR0402
10KR0402
N-NTD4806NT4G_DPAK3-RH
N-NTD4806NT4G_DPAK3-RH
R176 1R0805R176 1R0805
C260
C260
C0.1U25X
C0.1U25X
N-NTD4806NT4G_DPAK3-RH
N-NTD4806NT4G_DPAK3-RH
Q16
Q16
Q21
Q21
R175
R175
10KR0402
10KR0402
Q28
Q28
G
G
G
G
G
G
G
G
G
G
G
G
VIN
C101
C101
C1U16X5
C1U16X5
D
D
S
S
Q14
Q14
N-NTD4809NT4G_DPAK3-RH
N-NTD4809NT4G_DPAK3-RH
Q17
N-NTD4806NT4G_DPAK3-RH
Q17
N-NTD4806NT4G_DPAK3-RH
D
D
D
D
G
G
S
S
S
S
VIN
C140
C140
C1U16X5
C1U16X5
D
D
S
S
Q20
Q20
N-NTD4809NT4G_DPAK3-RH
N-NTD4809NT4G_DPAK3-RH
Q22
N-NTD4806NT4G_DPAK3-RH
Q22
N-NTD4806NT4G_DPAK3-RH
D
D
D
D
G
G
S
S
S
S
VIN
C211
C211
C1U16X5
C1U16X5
D
D
S
S
Q23
Q23
N-NTD4809NT4G_DPAK3-RH
N-NTD4809NT4G_DPAK3-RH
Q27
N-NTD4806NT4G_DPAK3-RH
Q27
N-NTD4806NT4G_DPAK3-RH
D
D
D
D
G
G
S
S
S
S
C96
C96
C10u16Y1206
C10u16Y1206
CH-0.25u40A0.65m-RH
CH-0.25u40A0.65m-RH
R138
R138
2.2R1%0805
2.2R1%0805
C133
C133
C1000P50X0402
C1000P50X0402
C149
C149
C10u16Y1206
C10u16Y1206
R153
R153
2.2R1%0805
2.2R1%0805
C207
C207
C1000P50X0402
C1000P50X0402
C223
C223
C10u16Y1206
C10u16Y1206
R180
R180
2.2R1%0805
2.2R1%0805
C264
C264
C1000P50X0402
C1000P50X0402
CHOKE2
CHOKE2
1 2
12
CP41CP41
PHASE11
ISEN1
CH-0.25u40A0.65m-RH
CH-0.25u40A0.65m-RH
CHOKE4
CHOKE4
1 2
12
CP43CP43
PHASE22
ISEN2
CH-0.25u40A0.65m-RH
CH-0.25u40A0.65m-RH
CHOKE6
CHOKE6
1 2
12
CP45CP45
PHASE33
ISEN3
VCCP
12
CP40CP40
VCCP
EC29
EC29
+
+
1 2
CD820u2.5SO-RH
CD820u2.5SO-RH
EC33
EC33
+
+
1 2
CD820u2.5SO-RH
CD820u2.5SO-RH
EC34
EC34
+
+
1 2
CD820u2.5SO-RH
VCCP
12
CP42CP42
CD820u2.5SO-RH
EC36
EC36
+
+
1 2
CD820u2.5SO-RH
CD820u2.5SO-RH
EC41
EC41
+
+
1 2
CD820u2.5SO-RH
CD820u2.5SO-RH
EC42
EC42
+
+
1 2
CD820u2.5SO-RH
CD820u2.5SO-RH
EC43
EC43
+
+
1 2
CD820u2.5SO-RH
CD820u2.5SO-RH
EC45
EC45
+
+
1 2
CD820u2.5SO-RH
CD820u2.5SO-RH
VCCP
12
CP44CP44
Modify 0902
TP125TP125
TP126TP126
VIN
C56
C56
C59
D
D
G
G
S
S
C1U16X5
C1U16X5
Q9
Q9
C59
C10u16Y1206
C10u16Y1206
CHOKE1
CHOKE1
CH-0.5u40A0.81m-RH
CH-0.5u40A0.81m-RH
12
CPU_VDDNB
R101
R101
2.2R1%0805
2.2R1%0805
C60
C60
C1000P50X0402
C1000P50X0402
N-NTD4806NT4G_DPAK3-RH
N-NTD4806NT4G_DPAK3-RH
VCC5
VIN
12
12
CP39CP39
CP38CP38
PHASE_NB_A
ISEN_NB_A
Title
Title
Title
Intersil 6323 3 Phase
Intersil 6323 3 Phase
Intersil 6323 3 Phase
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
VL390 0A
VL390 0A
VL390 0A
Date: Sheet
Date: Sheet
Date: Sheet
CPU_VDDNB
EC51
EC51
+
+
1 2
CD820u2.5SO-RH
CD820u2.5SO-RH
EC53
EC53
+
+
1 2
CD820u2.5SO-RH
CD820u2.5SO-RH
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
637Tuesday, September 09, 2008
637Tuesday, September 09, 2008
637Tuesday, September 09, 2008
of
of
1
of
Q6
Q6
D
D
G
G
S
S
Q7
Q7
D
D
G
G
S
S
2
5
JPW1
JPW1
GND GND
GND GND
12V
12V
12V
12V
CHOKE7
CHOKE7
CH-1.1u27A2.5m-RH
CH-1.1u27A2.5m-RH
5
1
2
CPU_CORE_TYPE7
R340 X_27R0402R340 X_27R0402
VIN
EC17
CD1000U16EL20-2+EC17
CD1000U16EL20-2
+
12
+
+
12
12
CD1000U16EL20-2
EC28
CD1000U16EL20-2+EC28
CD1000U16EL20-2
EC10
CD1000U16EL20-2+EC10
C270
C0.1U16Y0402
C270
C0.1U16Y0402
EC6
X_CD1000U16EL20-2+EC6
X_CD1000U16EL20-2
+
12
4
+12VIN
3
4
C283
C283
PWR-2X2M_natural-RH
X_C0.01u25X0402
X_C0.01u25X0402
+12VIN
A A
PWR-2X2M_natural-RH
1 2
C284
X_C0.01u25X0402
C284
X_C0.01u25X0402
VCC_DDR
R66 X_300R0402R66 X_300R0402
VID1_SEL
LOW FOR SVID
R78
R78
300R0402
300R0402
3
UGATE_NB
PHASE_NB
LGATE_NB
N-NTD4809NT4G_DPAK3-RH
N-NTD4809NT4G_DPAK3-RH
R120 1R0805R120 1R0805
R118
R118
10KR0402
10KR0402
N-NTD4806NT4G_DPAK3-RH
N-NTD4806NT4G_DPAK3-RH
R77 1R0805R77 1R0805
R94 1R0805R94 1R0805
5
4
3
2
1
CPU1A
CPU1A
L0_CLKIN_H(1)
L0_CLKIN_L(1)
L0_CLKIN_H(0)
L0_CLKIN_L(0)
L0_CTLIN_H(1)
L0_CTLIN_L(1)
L0_CTLIN_H(0)
L0_CTLIN_L(0)
L0_CADIN_H(15)
L0_CADIN_L(15)
L0_CADIN_H(14)
L0_CADIN_L(14)
L0_CADIN_H(13)
L0_CADIN_L(13)
L0_CADIN_H(12)
L0_CADIN_L(12)
L0_CADIN_H(11)
L0_CADIN_L(11)
L0_CADIN_H(10)
L0_CADIN_L(10)
L0_CADIN_H(9)
L0_CADIN_L(9)
L0_CADIN_H(8)
L0_CADIN_L(8)
L0_CADIN_H(7)
L0_CADIN_L(7)
L0_CADIN_H(6)
L0_CADIN_L(6)
L0_CADIN_H(5)
L0_CADIN_L(5)
L0_CADIN_H(4)
L0_CADIN_L(4)
L0_CADIN_H(3)
L0_CADIN_L(3)
L0_CADIN_H(2)
L0_CADIN_L(2)
L0_CADIN_H(1)
L0_CADIN_L(1)
L0_CADIN_H(0)
L0_CADIN_L(0)
HT_CADIN_H[15..0]
HT_CADIN_L[15..0]
HT_CADOUT_H[15..0]
HT_CADOUT_L[15..0]
HYPERTRANSPORT
HYPERTRANSPORT
L0_CLKOUT_H(1)
L0_CLKOUT_L(1)
L0_CLKOUT_H(0)
L0_CLKOUT_L(0)
L0_CTLOUT_H(1)
L0_CTLOUT_L(1)
L0_CTLOUT_H(0)
L0_CTLOUT_L(0)
L0_CADOUT_H(15)
L0_CADOUT_L(15)
L0_CADOUT_H(14)
L0_CADOUT_L(14)
L0_CADOUT_H(13)
L0_CADOUT_L(13)
L0_CADOUT_H(12)
L0_CADOUT_L(12)
L0_CADOUT_H(11)
L0_CADOUT_L(11)
L0_CADOUT_H(10)
L0_CADOUT_L(10)
L0_CADOUT_H(9)
L0_CADOUT_L(9)
L0_CADOUT_H(8)
L0_CADOUT_L(8)
L0_CADOUT_H(7)
L0_CADOUT_L(7)
L0_CADOUT_H(6)
L0_CADOUT_L(6)
L0_CADOUT_H(5)
L0_CADOUT_L(5)
L0_CADOUT_H(4)
L0_CADOUT_L(4)
L0_CADOUT_H(3)
L0_CADOUT_L(3)
L0_CADOUT_H(2)
L0_CADOUT_L(2)
L0_CADOUT_H(1)
L0_CADOUT_L(1)
L0_CADOUT_H(0)
L0_CADOUT_L(0)
VCC_1V2
AD5
AD4
AD1
AC1
Y6
W6
W2
W3
Y5
Y4
AB6
AA6
AB5
AB4
AD6
AC6
AF6
AE6
AF5
AF4
AH6
AG6
AH5
AH4
Y1
W1
AA2
AA3
AB1
AA1
AC2
AC3
AE2
AE3
AF1
AE1
AG2
AG3
AH1
AG1
RS740
R442 X_51R1%0402R442 X_51R1%0402
RS740
R599 X_51R1%0402R599 X_51R1%0402
HT_CADOUT_H15
HT_CADOUT_L15
HT_CADOUT_H14
HT_CADOUT_L14
HT_CADOUT_H13
HT_CADOUT_L13
HT_CADOUT_H12
HT_CADOUT_L12
HT_CADOUT_H11
HT_CADOUT_L11
HT_CADOUT_H10
HT_CADOUT_L10
HT_CADOUT_H9
HT_CADOUT_L9
HT_CADOUT_H8
HT_CADOUT_L8
HT_CADOUT_H7
HT_CADOUT_L7
HT_CADOUT_H6
HT_CADOUT_L6
HT_CADOUT_H5
HT_CADOUT_L5
HT_CADOUT_H4
HT_CADOUT_L4
HT_CADOUT_H3
HT_CADOUT_L3
HT_CADOUT_H2
HT_CADOUT_L2
HT_CADOUT_H1
HT_CADOUT_L1
HT_CADOUT_H0
HT_CADOUT_L0
HT_CLKOUT_H1 13
HT_CLKOUT_L1 13
HT_CLKOUT_H0 13
HT_CLKOUT_L0 13
HT_CTLOUT_H1 13
HT_CTLOUT_L1 13
HT_CTLOUT_H0 13
HT_CTLOUT_L0 13
HT_CTLIN_H1
HT_CTLIN_L1
CPU_CLK12
CPU_CLK#12
Note: CRB Reserved
CPU_DBREQ_L
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST_L
LDT_STOP#
LDT_RST#
LDT_PWRGD
R294 X_1KR0402R294 X_1KR0402
R281 X_1KR0402R281 X_1KR0402
R249 X_1KR0402R249 X_1KR0402
R247 X_1KR0402R247 X_1KR0402
R240 X_1KR0402R240 X_1KR0402
C801 X_C180p50N0402C801 X_C180p50N0402
C802 X_C180p50N0402C802 X_C180p50N0402
C803 X_C180p50N0402C803 X_C180p50N0402
C84
C84
C3900P50X
C3900P50X
C91
C91
C3900P50X
C3900P50X
VCC_DDR
R121
R121
169R1%0402
169R1%0402
VCC_DDR
R162
R162
39.2R1%0402
39.2R1%0402
R160
R160
39.2R1%0402
39.2R1%0402
LDT_PWRGD6,17
LDT_STOP#15,17
LDT_RST#15,17
CPU_M_VREF
VDDA25
C77
C77
C69
C69
C0.22U16X
C0.22U16X
C1U10Y
C1U10Y
C4.7U10Y0805
C4.7U10Y0805
LDT_PWRGD
LDT_STOP# VID4
LDT_RST#
COREFB+6
COREFB-6
CPU_VDDR_SENSE
TP1TP1
CPU_STRAP_HI_E11
CPU_STRAP_LO_F11
CPU_TEST25_H
CPU_TEST25_L
R534 X_300R0402R534 X_300R0402
R564 X_300R0402R564 X_300R0402
TP19TP19
TP20TP20
TP23TP23
TP18TP18
TP25TP25
C89
C89
C3300P50X0402
C3300P50X0402
CPUCLKIN
CPUCLKIN#
CPU_PRESENT_L
CPU_SIC
CPU_SID
CPU_ALERT#
R146 0R0402R146 0R0402
CPU_TDI
CPU_TRST_L
CPU_TCK
CPU_TMS
CPU_DBREQ_L
COREFB+
COREFB-
C74
C74
CPU1D
CPU1D
C10
VDDA1
D10
VDDA2
A8
CLKIN_H
B8
CLKIN_L
C9
PWROK
D8
LDTSTOP_L
C7
RESET_L
AL3
CPU_PRESENT_L
AL6
SIC
AK6
SID
AL4
ALERT_L
AK4
SA0
AL10
TDI
AJ10
TRST_L
AH10
TCK
AL9
TMS
A5
DBREQ_L
G2
VDD_FB_H
G1
VDD_FB_L
E12
VTT_SENSE
F12
M_VREF
AH11
M_ZN
AJ11
M_ZP
A10
TEST25_H
B10
TEST25_L
F10
TEST19
E9
TEST18
AJ7
TEST13
F6
TEST9
D6
TEST17
E7
TEST16
F8
TEST15
C5
TEST14
AH9
TEST12
E5
TEST7
AJ5
TEST6
AH7
TEST3
AJ6
TEST2
VDDA25VDDA_25
L5
L5
21
47n300mA_0805-RH-2
47n300mA_0805-RH-2
MISC
MISC
KEY/VSS1
KEY/VSS2
PLATFORM_TYPE
CORE_TYPE
VID(5)
VID(4)
SVC/VID(3)
SVD/VID(2)
PVIEN/VID(1)
VID(0)
THERMDC
THERMDA
THERMTRIP_L
PROCHOT_L
TDO
DBRDY
VDDIO_FB_H
VDDIO_FB_L
VDDNB_FB_H
VDDNB_FB_L
PSI_L
HTREF1
HTREF0
TEST29_H
TEST29_L
TEST24
TEST23
TEST22
TEST21
TEST20
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
TEST8
CPU_CORE_TYPE
VID3_SVC
VID2_SVD
Remove H22,AE9
H22
AE9
CPU_PF_TYPE
F2
CPU_CORE_TYPE
G5
VID5
D2
D1
VID3_SVC
C1
VID2_SVD
E3
VID1_SEL
E2
VRFIXEN
E1
AG9
AG8
CPU_THRIP_L#
AK7
PROCHOT_L
AL7
CPU_TDO
AK10
CPU_DBRDY
B6
AK11
AL11
G4
G3
CPU_PSI_L
F1
HTREF1
V8
V7
C11
D11
AK8
AH8
AJ9
AL8
AJ8
J10
H9
AK9
AK5
G7
D4
R168 44.2R1%R168 44.2R1%
HTREF2
R171 44.2R1%R171 44.2R1%
R123 X_80.6R1%0402R123 X_80.6R1%0402
Keep trace < 1" from CPU.
TP28TP28
TP24TP24
R531 300R0402R531 300R0402
TP26TP26
R165 X_300R0402R165 X_300R0402
TP5TP5
TP6TP6
TP7TP7
R102 0R0402R102 0R0402
R163 100R0402R163 100R0402
TP4TP4
TP3TP3
TP27TP27
R80 1KR0402R80 1KR0402
R72 1KR0402R72 1KR0402
R71 1KR0402R71 1KR0402
change pin F2 from
PLATFORM_TYPE to RSVD
TP2TP2
CPU_CORE_TYPE 6
VID3_SVC 6
VID2_SVD 6
VID1_SEL 6
THERMDC_CPU 25,32
THERMDA_CPU 25,32
V_NB 6
V_GND 6
VCC_1V2
R567 300R0402R567 300R0402
VCC_DDR
VCC_DDR
Note: Change the PU
resister to 1KR
CPU_PROCHOT# 17
DDR_FB 27
HT_CADIN_H[15..0]13
HT_CADIN_L[15..0]13
HT_CADOUT_H[15..0]13
HT_CADOUT_L[15..0]13
D D
HT_CLKIN_H113
HT_CLKIN_L113
HT_CLKIN_H013
HT_CLKIN_L013
HT_CTLIN_H113
HT_CTLIN_L113
HT_CTLIN_H013
HT_CTLIN_L013
HT_CADIN_H15
HT_CADIN_L15
HT_CADIN_H14
HT_CADIN_L14
HT_CADIN_H13
HT_CADIN_L13
HT_CADIN_H12
HT_CADIN_L12
HT_CADIN_H11
HT_CADIN_L11
HT_CADIN_H10
HT_CADIN_L10
HT_CADIN_H9
HT_CADIN_L9
HT_CADIN_H8
C C
B B
HT_CADIN_L8
HT_CADIN_H7
HT_CADIN_L7
HT_CADIN_H6
HT_CADIN_L6
HT_CADIN_H5
HT_CADIN_L5
HT_CADIN_H4
HT_CADIN_L4
HT_CADIN_H3
HT_CADIN_L3
HT_CADIN_H2
HT_CADIN_L2
HT_CADIN_H1
HT_CADIN_L1
HT_CADIN_H0
HT_CADIN_L0
N6
P6
N3
N2
V4
V5
U1
V1
U6
V6
T4
T5
R6
T6
P4
P5
M4
M5
L6
M6
K4
K5
J6
K6
U3
U2
R1
T1
R3
R2
N1
P1
L1
M1
L3
L2
J1
K1
J3
J2
AMD REQUEST
VCC_DDRVCC3
R21
R22
R22
X_1KR0402
X_1KR0402
SW1 X_SW-TACT4PSSW1 X_SW-TACT4PS
1
3
2
4
CPU_DBREQ_L
CPU_DBRDY
CPU_TCK
A A
CPU_TMS
CPU_TDI
CPU_TRST_L
CPU_TDO
5
VCC_DDR
X_100R0402
X_100R0402
LDT_RST_L LDT_RST#
R8
R8
J1
1
3
5
7
9
11
13
15
17
19
21
23
J1
KEY
KEY
X_H2X13[25]_black
X_H2X13[25]_black
R21
X_4.7KR0402
X_4.7KR0402
B
CE
Q1
Q1
X_N-MMBT3904_NL_SOT23
X_N-MMBT3904_NL_SOT23
2
4
6
8
10
12
14
16
18
20
22
24
26
LDT_RST_L
4
VCC3
R174
R174
X_39.2KR1%0402
X_39.2KR1%0402
For SIC/SID
CPU_ALERT#
CPU_SID
CPU_SIC
CPU_PRESENT_L
CPU_TEST25_H
CPU_TEST25_L
R184
R184
20KR1%0402
20KR1%0402
C255
C255
C0.1U16Y0402
C0.1U16Y0402
R177 1KR0402R177 1KR0402
R231 1KR0402R231 1KR0402
R167 1KR0402R167 1KR0402
R170 10KR0402R170 10KR0402
R111 510R0402R111 510R0402
R119 510R0402R119 510R0402
CPU_SIC
CPU_SID
CPU_FETGATE
CPU_ALERT#
CPU_PRESENT_L
VCC_DDR
3
Q102
Q102
S1
G1
S2
G2
S1
G1
S2
G2
LDT_STOP#
LDT_RST#
LDT_PWRGD
PROCHOT_L
D1
D2
NN-2N7002DW-7-F_SOT363-6-RH
NN-2N7002DW-7-F_SOT363-6-RH
Q103
Q103
D1
D2
NN-2N7002DW-7-F_SOT363-6-RH
NN-2N7002DW-7-F_SOT363-6-RH
R106 300R0402R106 300R0402
R105 300R0402R105 300R0402
R107 300R0402R107 300R0402
R103 300R0402R103 300R0402
Modify 0902
R182 0R0402R182 0R0402
R178 0R0402R178 0R0402
R183 X_0R0402R183 X_0R0402
VCC_DDR
AMD_TSI_C 25
AMD_TSI_D 25
TALERT# 19
CPU_PRESENT# 18
HTREF1
HTREF2
LDT_RST#
CPU_THRIP_L#
C227 X_C1000P50X0402C227 X_C1000P50X0402
C228 X_C1000P50X0402C228 X_C1000P50X0402
C67 X_C1000P50X0402C67 X_C1000P50X0402
2
R169
R169
300R0402
300R0402
Q24
Q24
N-MMBT3904_NL_SOT23
N-MMBT3904_NL_SOT23
VCC_DDR
B
R166
R166
4.7KR0402
4.7KR0402
CE
CPU_THRIP# 18
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
VCC_DDR
CPU_M_VREF
R110
R110
15R1%
15R1%
C86
C86
C92
1
C92
C1000P50X0402
C1000P50X0402
CPU_CLK
CPU_CLK#
LDT_PWRGD
LDT_RST#
737Tuesday, September 09, 2008
737Tuesday, September 09, 2008
737Tuesday, September 09, 2008
R109
R109
15R1%
15R1%
C0.1U16Y0402
C0.1U16Y0402
TP135TP135
TP136TP136
TP137TP137
TP138TP138
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
CPU AM2 HT I/F,CTRL&DEBUG
CPU AM2 HT I/F,CTRL&DEBUG
CPU AM2 HT I/F,CTRL&DEBUG
VL390 0A
VL390 0A
VL390 0A
of
of
of
5
MEM_MA_DQS_L[7..0]10,11
MEM_MA_DQS_H[7..0]10,11
MEM_MA_DM[7..0]10,11
AG21
AG20
G19
AC25
AA24
AC28
AE20
AE19
G20
G21
W27
AD27
AA25
AC27
AB25
AB27
AA26
AA27
M25
M27
AC26
W24
AD15
AE15
AG18
AG19
AG24
AG25
AG27
AG28
G15
AF15
AF19
AJ25
AH29
H19
U27
U26
V27
N25
Y27
L27
N24
N26
P25
Y25
N27
R24
P27
R25
R26
R27
T25
U25
T27
D29
C29
C25
D25
E19
F19
F15
B29
E24
E18
H15
MEM_MA_CHECK[7..0]10,11
CPU1B
CPU1B
MA0_CLK_H(2)
MA0_CLK_L(2)
MA0_CLK_H(1)
MA0_CLK_L(1)
MA0_CLK_H(0)
MA0_CLK_L(0)
MA0_CS_L(1)
MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)
MA1_CLK_L(2)
MA1_CLK_H(1)
MA1_CLK_L(1)
MA1_CLK_H(0)
MA1_CLK_L(0)
MA1_CS_L(1)
MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_L
MA_WE_L
MA_RAS_L
MA_BANK(2)
MA_BANK(1)
MA_BANK(0)
MA_CKE(1)
MA_CKE(0)
MA_ADD(15)
MA_ADD(14)
MA_ADD(13)
MA_ADD(12)
MA_ADD(11)
MA_ADD(10)
MA_ADD(9)
MA_ADD(8)
MA_ADD(7)
MA_ADD(6)
MA_ADD(5)
MA_ADD(4)
MA_ADD(3)
MA_ADD(2)
MA_ADD(1)
MA_ADD(0)
MA_DQS_H(7)
MA_DQS_L(7)
MA_DQS_H(6)
MA_DQS_L(6)
MA_DQS_H(5)
MA_DQS_L(5)
MA_DQS_H(4)
MA_DQS_L(4)
MA_DQS_H(3)
MA_DQS_L(3)
MA_DQS_H(2)
MA_DQS_L(2)
MA_DQS_H(1)
MA_DQS_L(1)
MA_DQS_H(0)
MA_DQS_L(0)
MA_DM(7)
MA_DM(6)
MA_DM(5)
MA_DM(4)
MA_DM(3)
MA_DM(2)
MA_DM(1)
MA_DM(0)
MEMORY INTERFACE A
MEMORY INTERFACE A
D D
MEM_MA1_CLK_H111
MEM_MA1_CLK_L111 MEM_MB1_CLK_H111
MEM_MA0_CS_L110
MEM_MA0_CS_L010
MEM_MA0_ODT010
MEM_MA0_CLK_H010
MEM_MA0_CLK_L010
MEM_MA1_CS_L111
MEM_MA1_CS_L011
MEM_MA1_ODT011
C C
B B
MEM_MA_CAS_L10,11
MEM_MA_WE_L10,11
MEM_MA_RAS_L10,11
MEM_MA_BANK210,11
MEM_MA_BANK110,11
MEM_MA_BANK010,11
MEM_MA_CKE110,11
MEM_MA_CKE010,11
MEM_MA_ADD[15..0]10,11
Pin naming for memory pins indicate
"DDR3"/"DDR2" connections.
MEM_MA1_CLK_H1
MEM_MA1_CLK_L1 MEM_MB1_CLK_H1
MEM_MA0_CS_L1
MEM_MA0_CS_L0
MEM_MA0_ODT0
MEM_MA0_CLK_H0
MEM_MA0_CLK_L0
MEM_MA1_CS_L1
MEM_MA1_CS_L0
MEM_MA1_ODT0
MEM_MA_CAS_L
MEM_MA_WE_L
MEM_MA_RAS_L
MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0
MEM_MA_CKE1
MEM_MA_CKE0
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0
4
MA_DATA(63)
MA_DATA(62)
MA_DATA(61)
MA_DATA(60)
MA_DATA(59)
MA_DATA(58)
MA_DATA(57)
MA_DATA(56)
MA_DATA(55)
MA_DATA(54)
MA_DATA(53)
MA_DATA(52)
MA_DATA(51)
MA_DATA(50)
MA_DATA(49)
MA_DATA(48)
MA_DATA(47)
MA_DATA(46)
MA_DATA(45)
MA_DATA(44)
MA_DATA(43)
MA_DATA(42)
MA_DATA(41)
MA_DATA(40)
MA_DATA(39)
MA_DATA(38)
MA_DATA(37)
MA_DATA(36)
MA_DATA(35)
MA_DATA(34)
MA_DATA(33)
MA_DATA(32)
MA_DATA(31)
MA_DATA(30)
MA_DATA(29)
MA_DATA(28)
MA_DATA(27)
MA_DATA(26)
MA_DATA(25)
MA_DATA(24)
MA_DATA(23)
MA_DATA(22)
MA_DATA(21)
MA_DATA(20)
MA_DATA(19)
MA_DATA(18)
MA_DATA(17)
MA_DATA(16)
MA_DATA(15)
MA_DATA(14)
MA_DATA(13)
MA_DATA(12)
MA_DATA(11)
MA_DATA(10)
MA_DATA(9)
MA_DATA(8)
MA_DATA(7)
MA_DATA(6)
MA_DATA(5)
MA_DATA(4)
MA_DATA(3)
MA_DATA(2)
MA_DATA(1)
MA_DATA(0)
MA_DQS_H(8)
MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)
MA_CHECK(6)
MA_CHECK(5)
MA_CHECK(4)
MA_CHECK(3)
MA_CHECK(2)
MA_CHECK(1)
MA_CHECK(0)
AE14
AG14
AG16
AD17
AD13
AE13
AG15
AE16
AG17
AE18
AD21
AG22
AE17
AF17
AF21
AE21
AF23
AE23
AJ26
AG26
AE22
AG23
AH25
AF25
AJ28
AJ29
AF29
AE26
AJ27
AH27
AG29
AF27
E29
E28
D27
C27
G26
F27
C28
E27
F25
E25
E23
D23
E26
C26
G23
F23
E22
E21
F17
G17
G22
F21
G18
E17
G16
E15
G13
H13
H17
E16
E14
G14
J28
J27
J25
K25
J26
G28
G27
L24
K27
H29
H27
MEM_MA_DATA63
MEM_MA_DATA62
MEM_MA_DATA61
MEM_MA_DATA60
MEM_MA_DATA59
MEM_MA_DATA58
MEM_MA_DATA57
MEM_MA_DATA56
MEM_MA_DATA55
MEM_MA_DATA54
MEM_MA_DATA53
MEM_MA_DATA52
MEM_MA_DATA51
MEM_MA_DATA50
MEM_MA_DATA49
MEM_MA_DATA48
MEM_MA_DATA47
MEM_MA_DATA46
MEM_MA_DATA45
MEM_MA_DATA44
MEM_MA_DATA43
MEM_MA_DATA42
MEM_MA_DATA41
MEM_MA_DATA40
MEM_MA_DATA39
MEM_MA_DATA38
MEM_MA_DATA37
MEM_MA_DATA36
MEM_MA_DATA35
MEM_MA_DATA34
MEM_MA_DATA33
MEM_MA_DATA32
MEM_MA_DATA31
MEM_MA_DATA30
MEM_MA_DATA29
MEM_MA_DATA28
MEM_MA_DATA27
MEM_MA_DATA26
MEM_MA_DATA25
MEM_MA_DATA24
MEM_MA_DATA23
MEM_MA_DATA22
MEM_MA_DATA21
MEM_MA_DATA20
MEM_MA_DATA19
MEM_MA_DATA18
MEM_MA_DATA17
MEM_MA_DATA16
MEM_MA_DATA15
MEM_MA_DATA14
MEM_MA_DATA13
MEM_MA_DATA12
MEM_MA_DATA11
MEM_MA_DATA10
MEM_MA_DATA9
MEM_MA_DATA8
MEM_MA_DATA7
MEM_MA_DATA6
MEM_MA_DATA5
MEM_MA_DATA4
MEM_MA_DATA3
MEM_MA_DATA2
MEM_MA_DATA1
MEM_MA_DATA0
MEM_MA_DQS_H8
MEM_MA_DQS_L8
MEM_MA_DM8
MEM_MA_CHECK7
MEM_MA_CHECK6
MEM_MA_CHECK5
MEM_MA_CHECK4
MEM_MA_CHECK3
MEM_MA_CHECK2
MEM_MA_CHECK1
MEM_MA_CHECK0
MEM_MA_DATA[63..0] 10,11
MEM_MA_DQS_H8 10,11
MEM_MA_DQS_L8 10,11
MEM_MA_DM8 10,11
3
AJ19
AK19
A18
A19
MEM_MB1_CLK_L111
MEM_MB0_CS_L110
MEM_MB0_CS_L010
MEM_MB0_ODT010
MEM_MB0_CLK_H010
MEM_MB0_CLK_L010
MEM_MB1_CS_L111
MEM_MB1_CS_L011
MEM_MB1_ODT011
MEM_MB_CAS_L10,11
MEM_MB_WE_L10,11
MEM_MB_RAS_L10,11
MEM_MB_BANK210,11
MEM_MB_BANK110,11
MEM_MB_BANK010,11
MEM_MB_CKE110,11
MEM_MB_CKE010,11
MEM_MB_ADD[15..0]10,11
MEM_MB1_CLK_L1
MEM_MB0_CS_L1
MEM_MB0_CS_L0
MEM_MB0_ODT0
MEM_MB0_CLK_H0
MEM_MB0_CLK_L0
MEM_MB1_CS_L1
MEM_MB1_CS_L0
MEM_MB1_ODT0
MEM_MB_CAS_L
MEM_MB_WE_L
MEM_MB_RAS_L
MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0
MEM_MB_CKE1
MEM_MB_CKE0
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0
U31
U30
AE30
AC31
AD29
AL19
AL18
C19
D19
W29
W28
AE29
AB31
AD31
AC29
AC30
AB29
N31
AA31
AA28
M31
M29
N28
N29
AE31
N30
P29
AA29
P31
R29
R28
R31
R30
U29
U28
AA30
AK13
AJ13
AK17
AJ17
AK23
AL23
AL28
AL29
D31
C31
C24
C23
D17
C17
C14
C13
AJ14
AH17
AJ23
AK29
C30
A23
B17
B13
T31
T29
MEM_MB_DQS_L[7..0]10,11
MEM_MB_DQS_H[7..0]10,11
MEM_MB_DM[7..0]10,11
MEM_MB_CHECK[7..0]10,11
CPU1C
CPU1C
MB0_CLK_H(2)
MB0_CLK_L(2)
MB0_CLK_H(1)
MB0_CLK_L(1)
MB0_CLK_H(0)
MB0_CLK_L(0)
MB0_CS_L(1)
MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)
MB1_CLK_L(2)
MB1_CLK_H(1)
MB1_CLK_L(1)
MB1_CLK_H(0)
MB1_CLK_L(0)
MB1_CS_L(1)
MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_L
MB_WE_L
MB_RAS_L
MB_BANK(2)
MB_BANK(1)
MB_BANK(0)
MB_CKE(1)
MB_CKE(0)
MB_ADD(15)
MB_ADD(14)
MB_ADD(13)
MB_ADD(12)
MB_ADD(11)
MB_ADD(10)
MB_ADD(9)
MB_ADD(8)
MB_ADD(7)
MB_ADD(6)
MB_ADD(5)
MB_ADD(4)
MB_ADD(3)
MB_ADD(2)
MB_ADD(1)
MB_ADD(0)
MB_DQS_H(7)
MB_DQS_L(7)
MB_DQS_H(6)
MB_DQS_L(6)
MB_DQS_H(5)
MB_DQS_L(5)
MB_DQS_H(4)
MB_DQS_L(4)
MB_DQS_H(3)
MB_DQS_L(3)
MB_DQS_H(2)
MB_DQS_L(2)
MB_DQS_H(1)
MB_DQS_L(1)
MB_DQS_H(0)
MB_DQS_L(0)
MB_DM(7)
MB_DM(6)
MB_DM(5)
MB_DM(4)
MB_DM(3)
MB_DM(2)
MB_DM(1)
MB_DM(0)
2
MEMORY INTERFACE B
MEMORY INTERFACE B
MB_DATA(63)
MB_DATA(62)
MB_DATA(61)
MB_DATA(60)
MB_DATA(59)
MB_DATA(58)
MB_DATA(57)
MB_DATA(56)
MB_DATA(55)
MB_DATA(54)
MB_DATA(53)
MB_DATA(52)
MB_DATA(51)
MB_DATA(50)
MB_DATA(49)
MB_DATA(48)
MB_DATA(47)
MB_DATA(46)
MB_DATA(45)
MB_DATA(44)
MB_DATA(43)
MB_DATA(42)
MB_DATA(41)
MB_DATA(40)
MB_DATA(39)
MB_DATA(38)
MB_DATA(37)
MB_DATA(36)
MB_DATA(35)
MB_DATA(34)
MB_DATA(33)
MB_DATA(32)
MB_DATA(31)
MB_DATA(30)
MB_DATA(29)
MB_DATA(28)
MB_DATA(27)
MB_DATA(26)
MB_DATA(25)
MB_DATA(24)
MB_DATA(23)
MB_DATA(22)
MB_DATA(21)
MB_DATA(20)
MB_DATA(19)
MB_DATA(18)
MB_DATA(17)
MB_DATA(16)
MB_DATA(15)
MB_DATA(14)
MB_DATA(13)
MB_DATA(12)
MB_DATA(11)
MB_DATA(10)
MB_DATA(9)
MB_DATA(8)
MB_DATA(7)
MB_DATA(6)
MB_DATA(5)
MB_DATA(4)
MB_DATA(3)
MB_DATA(2)
MB_DATA(1)
MB_DATA(0)
MB_DQS_H(8)
MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)
MB_CHECK(6)
MB_CHECK(5)
MB_CHECK(4)
MB_CHECK(3)
MB_CHECK(2)
MB_CHECK(1)
MB_CHECK(0)
AH13
AL13
AL15
AJ15
AF13
AG13
AL14
AK15
AL16
AL17
AK21
AL21
AH15
AJ16
AH19
AL20
AJ22
AL22
AL24
AK25
AJ21
AH21
AH23
AJ24
AL27
AK27
AH31
AG30
AL25
AL26
AJ30
AJ31
E31
E30
B27
A27
F29
F31
A29
A28
A25
A24
C22
D21
A26
B25
B23
A22
B21
A20
C16
D15
C21
A21
A17
A16
B15
A14
E13
F13
C15
A15
A13
D13
J31
J30
J29
K29
K31
G30
G29
L29
L28
H31
G31
MEM_MB_DATA63
MEM_MB_DATA62
MEM_MB_DATA61
MEM_MB_DATA60
MEM_MB_DATA59
MEM_MB_DATA58
MEM_MB_DATA57
MEM_MB_DATA56
MEM_MB_DATA55
MEM_MB_DATA54
MEM_MB_DATA53
MEM_MB_DATA52
MEM_MB_DATA51
MEM_MB_DATA50
MEM_MB_DATA49
MEM_MB_DATA48
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA45
MEM_MB_DATA44
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA41
MEM_MB_DATA40
MEM_MB_DATA39
MEM_MB_DATA38
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA35
MEM_MB_DATA34
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA31
MEM_MB_DATA30
MEM_MB_DATA29
MEM_MB_DATA28
MEM_MB_DATA27
MEM_MB_DATA26
MEM_MB_DATA25
MEM_MB_DATA24
MEM_MB_DATA23
MEM_MB_DATA22
MEM_MB_DATA21
MEM_MB_DATA20
MEM_MB_DATA19
MEM_MB_DATA18
MEM_MB_DATA17
MEM_MB_DATA16
MEM_MB_DATA15
MEM_MB_DATA14
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10
MEM_MB_DATA9
MEM_MB_DATA8
MEM_MB_DATA7
MEM_MB_DATA6
MEM_MB_DATA5
MEM_MB_DATA4
MEM_MB_DATA3
MEM_MB_DATA2
MEM_MB_DATA1
MEM_MB_DATA0
MEM_MB_DQS_H8
MEM_MB_DQS_L8
MEM_MB_DM8
MEM_MB_CHECK7
MEM_MB_CHECK6
MEM_MB_CHECK5
MEM_MB_CHECK4
MEM_MB_CHECK3
MEM_MB_CHECK2
MEM_MB_CHECK1
MEM_MB_CHECK0
1
MEM_MB_DATA[63..0] 10,11
MEM_MB_DQS_H8 10,11
MEM_MB_DQS_L8 10,11
MEM_MB_DM8 10,11
Add For ECC 0829 Add For ECC 0829
A A
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
CPU AM2 DDR MEMORY I/F
CPU AM2 DDR MEMORY I/F
CPU AM2 DDR MEMORY I/F
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
VL390 0A
VL390 0A
VL390 0A
1
of
of
of
837Tuesday, September 09, 2008
837Tuesday, September 09, 2008
837Tuesday, September 09, 2008
5
4
3
2
1
CPU AM2 PWR & GND
C693
C693
C22u6.3X1206
C22u6.3X1206
C715
C715
C10u6.3X50805
C10u6.3X50805
12
C111
C111
C0.01U16X0402
C0.01U16X0402
VCCPVCCP
M11
M13
M15
M17
M19
W10
W12
W14
W16
W18
W20
C701
C701
C22u6.3X1206
C22u6.3X1206
C22u6.3X1206
C22u6.3X1206
C710
C710
C10u6.3X50805
C10u6.3X50805
C0.01u16X-1
C0.01u16X-1
12
C110
C110
C0.01U16X0402
C0.01U16X0402
C180P50N0402
C180P50N0402
Bottom side
C708 C2.2u10Y-RHC708 C2.2u10Y-RH
C692 C2.2u10Y-RHC692 C2.2u10Y-RH
4
L14
L16
L18
M2
M3
M7
M9
N8
N10
N12
N14
N16
N18
P7
P9
P11
P13
P15
P17
P19
R4
R5
R8
R10
R12
R14
R16
R18
R20
T2
T3
T7
T9
T11
T13
T15
T17
T19
T21
U8
U10
U12
U14
U16
U18
U20
V9
V11
V13
V15
V17
V19
V21
W4
W5
W8
Y2
Y3
Y7
Y9
Y11
Y13
Y15
Y21
CPU1G
CPU1G
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD37
VDD38
VDD39
VDD40
VDD41
VDD42
VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54
VDD55
VDD56
VDD57
VDD58
VDD59
VDD60
VDD61
VDD62
VDD63
VDD64
VDD65
VDD66
VDD67
VDD68
VDD69
VDD70
VDD71
VDD72
VDD73
VDD74
VDD75
C694
C694
C695
C695
C4.7U10Y0805
C4.7U10Y0805
C241
C241
VDD2
VDD2
C699
C699
C4.7U10Y0805
C4.7U10Y0805
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
C707
C707
AK20
AK22
AK24
AK26
AK28
AK30
AL5
B4
B9
B11
B14
B16
B18
B20
B22
B24
B26
B28
B30
C3
D14
D16
D18
D20
D22
D24
D26
D28
D30
E11
F4
F14
F16
F18
F20
F22
F24
F26
F28
F30
G9
G11
H8
H10
H12
H14
H16
H18
H24
H26
H28
H30
J4
J5
J7
J9
J11
J13
J15
J17
J19
J21
J23
K2
K3
K8
K10
K12
K14
K16
K18
K20
K22
Y18
C696
C696
C4.7U10Y0805
C4.7U10Y0805
C180P50N0402
C180P50N0402
C88 C2.2u10Y-RHC88 C2.2u10Y-RH
CPU1I
VCCP
CPU1H
CPU1H
VDD3
VDD3
AA20
VDD1
AA22
VDD2
AB13
VDD3
AB15
VDD4
AB17
VDD5
AB19
VDD6
AB21
VDD7
AB23
VDD8
AC12
VDD9
AC14
VDD10
AC16
VDD11
AC18
VDD12
AC20
VDD13
AC22
VDD14
AD11
VDD15
AD23
VDD16
AE12
VDD17
AF11
VDD18
L20
VDD19
L22
VDD20
M21
VDD21
M23
VDD22
N20
VDD23
N22
VDD24
P21
VDD25
P23
VDD26
R22
VDD27
T23
VDD28
U22
VDD29
V23
VDD30
W22
VDD31
Y23
VDD32
5
GND
Change to
6
GND
Passive
7
Pin
GND
8
GND
1
GND
2
GND
3
GND
VCC_DDR
C697
C697
C681
C681
C22u6.3X1206
C22u6.3X1206
VCC_DDR
C239
C239
C4.7u6.3X5
C4.7u6.3X5
CPU_VDDR
CPU_VDDNBVCCP
C22u6.3X1206
C22u6.3X1206
CPU_VDDR
C0.22u10Y0402
C0.22u10Y0402
C22u6.3X1206
C22u6.3X1206
C22u6.3X1206
C22u6.3X1206
Place along the VCC_DDR/VSS plane splite
C131
C131
C210
C210
C4.7U10Y0805
C4.7U10Y0805
C4.7u6.3X5
C4.7u6.3X5
Bottom side
C224
C224
C50
C50
C0.01u16X-1
C0.01u16X-1
C0.22U16X
C0.22U16X
C68
C68
C90
C90
C0.22u10Y0402
C0.22u10Y0402
C0.22u10Y0402
C0.22u10Y0402
3
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
C702
C702
C22u6.3X1206
C22u6.3X1206
C220
C220
C4.7U10Y0805
C4.7U10Y0805
C716
C716
C0.01U16X0402
C0.01U16X0402
C66
C66
C0.22u10Y0402
C0.22u10Y0402
N17
N19
N21
N23
P2
P3
P8
P10
P12
P14
P16
P18
P20
P22
R7
R9
R11
R13
R15
R17
R19
R21
R23
T8
T10
T12
T14
T16
T18
T20
T22
U4
U5
U7
U9
U11
U13
U15
U17
U19
U21
U23
V2
V3
V10
V12
V14
V16
V18
V20
V22
W9
W11
W13
W15
W17
W19
W21
W23
Y8
Y10
Y12
W7
Y20
Y22
Bottom side
C684
C684
C712
C712
C0.22U16X
C0.22U16X
C774
C774
C132
C132
C180P50N0402
C180P50N0402
12
C246
C246
Place between the DIMM Slot
12
C76
C76
C233
C233
C0.01U16X0402
C0.01U16X0402
CPU_VDDR@4A
C0.01u16X-1
C0.01u16X-1
C180P50N0402
C180P50N0402
VTT_DDR
X_C4.7U10Y0805
X_C4.7U10Y0805
C4.7U10Y0805
C4.7U10Y0805
VCC_1V2
CPU_VDDR
VCC_DDR
MEM_MA1_CLK_H011
MEM_MA1_CLK_L011
MEM_MA0_CLK_H110
MEM_MA0_CLK_L110
MEM_MB1_CLK_H011
MEM_MB1_CLK_L011
MEM_MB0_CLK_H110
MEM_MB0_CLK_L110
C687
C687
C705
C705
C0.01u16X-1
C0.01u16X-1
C180p50N
C180p50N
C819
C819
C234
C234
C180P50N0402
C180P50N0402
C180P50N0402
C180P50N0402
Place behind the DIMM Slot
C287
C287
C267
C267
X_C4.7U10Y0805
X_C4.7U10Y0805
C4.7U10Y0805
C4.7U10Y0805
C252
C252
C61
C61
C4.7U10Y0805
C4.7U10Y0805
C4.7U10Y0805
C4.7U10Y0805
C690
C690
C243
C243
C57
C57
CPU1I
VDDIO
VDDIO
AJ4
AJ3
AJ2
AJ1
D12
C12
B12
A12
AB24
AB26
AB28
AB30
AC24
AD26
AD28
AD30
AF30
M24
M26
M28
M30
P24
P26
P28
P30
T24
T26
T28
T30
V25
V26
V28
V30
Y24
Y26
Y28
Y29
MEM_MA1_ODT111
MEM_MA0_ODT110
MEM_MB1_ODT111
MEM_MB0_ODT110
Remove pin H3, H4, H21, AD18, AD19, AE8;
change pin H20, AE7 to NP/VSS
C714
C714
C10u6.3X50805
C10u6.3X50805
If the distance between the processor
keepout and the keepout of the first DIMM
is less than 2.5 inches, there are four
additional 180-pF capacitors instead of two.
C65
C65
C130
C130
C4.7U10Y0805
C4.7U10Y0805
C258
C258
C10u6.3X50805
C10u6.3X50805
C4.7U10Y0805
C4.7U10Y0805
VLDT_A1
VLDT_A2
VLDT_A3
VLDT_A4
VTT1
VTT2
VTT3
VTT4
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDDIO28
VDDIO29
C0.22U16X
C0.22U16X
VLDT_B1
VLDT_B2
VLDT_B3
VLDT_B4
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
MEM_MA1_CLK_H0
MEM_MA1_CLK_L0
MEM_MA1_ODT1
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_ODT1
MEM_MB1_CLK_H0
MEM_MB1_CLK_L0
MEM_MB1_ODT1
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_ODT1
C768
C768
C331
C331
C262
C262
C4.7U10Y0805
C4.7U10Y0805
2
VTT5
VTT6
VTT7
VTT8
VTT9
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VCC_DDR
VCC_DDR
12
C4.7U10Y0805
C4.7U10Y0805
VLDT_RUN_B
H6
H5
H2
H1
AK12
AJ12
AH12
AG12
AL12
K24
K26
K28
K30
L7
L9
L11
L13
L15
L17
L19
L21
L23
M8
M10
M12
M14
M16
M18
M20
M22
N4
N5
N7
N9
N11
N13
N15
L25
L26
L31
L30
W26
W25
AE27
U24
V24
AE28
Y31
Y30
AG31
V31
W31
AF31
AD18
AD19
AE7
AE8
H3
H4
H20
H21
+
+
EC20
EC20
.CD1000U6.3EL11.5
.CD1000U6.3EL11.5
C263
C263
C4.7U10Y0805
C4.7U10Y0805
C120
C120
CPU_VDDR
C10u6.3X50805
C10u6.3X50805
CPU1E
CPU1E
INTERNAL MISC E
INTERNAL MISC E
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
KEY1
KEY2
KEY3
KEY4
KEY5
KEY6
KEY7
KEY8
CPU_VDDIO_PWRGD generater circuit
100ns after VCC_DDR valid
VCC3_SB
R635
R635
B
X_10KR0402
X_10KR0402
C276
C276
C261
C261
C4.7U10Y0805
C4.7U10Y0805
C116
C116
X_C0.01U25Y
X_C0.01U25Y
near (1900,-4700)*3, near C116*2
VCCP
C788
C788
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
MEM_MA_RESET#
E20
RSVD17
MEM_MB_RESET#
B19
RSVD18
AK3
RSVD21
CPU_VDDIO_PWRGD
F3
RSVD23
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
R172
R172
X_4.7KR0402
X_4.7KR0402
CE
Q39
Q39
X_N-MMBT3904
X_N-MMBT3904
Add pin B2 as NP/RSVD
AD25
AE24
AE25
AJ18
AJ20
C18
C20
G24
G25
H25
MEM_MB_EVENT#
V29
MEM_MA_EVENT#
W30
VCC3_SB
R661
R661
B
X_10KR0402
X_10KR0402
Title
Title
Title
CPU AM2 PWR & GND
CPU AM2 PWR & GND
CPU AM2 PWR & GND
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
VL390 0A
VL390 0A
VL390 0A
Date: Sheet
Date: Sheet
Date: Sheet
EMI_0B
C791
C789
C789
X_C0.1U16Y0402
X_C0.1U16Y0402
CE
Q43
Q43
X_N-MMBT3904
X_N-MMBT3904
TP129TP129
TP130TP130
TP131TP131
TP132TP132
C791
C792
C790
C790
X_C0.1U16Y0402
X_C0.1U16Y0402
R472
R472
X_5.6KR1%0402
X_5.6KR1%0402
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
C792
X_C0.1U16Y0402
X_C0.1U16Y0402
MEM_MA_RESET# 10,11
MEM_MB_RESET# 10,11
VCC_DDR
DG use 1KR PU
R300 301R0402R300 301R0402
R423 301R0402R423 301R0402
MEM_MB_EVENT# 10,11
MEM_MA_EVENT# 10,11
EVENT pins are for future AM3r2
Layout: Route as 60 ohms
with 5/10 W/S from CPU pins.
VCC_DDR
R199
R199
X_4.7KR0402
X_4.7KR0402
CPU_VDDIO_PWRGD
R662
R662
C855
C855
X_4.7KR0402
X_4.7KR0402
X_C1U10Y
X_C1U10Y
VCCP
VCC_1V2
CPU_VDDR
VCC_DDR
1
937Tuesday, September 09, 2008
937Tuesday, September 09, 2008
937Tuesday, September 09, 2008
of
of
of
CPU_VDDNB
CPU1F
CPU1F
VDD1
VDD1
A4
VDDNB1
A6
VDDNB2
B5
VDDNB3
B7
VDDNB4
C6
VDDNB5
C8
VDDNB6
D7
VDDNB7
D9
VDDNB8
D D
C C
B B
A A
VCCP
C685
C685
C22u6.3X1206
C22u6.3X1206
VCCP
C114
C114
C0.01u16X-1
C0.01u16X-1
CPU_VDDNB
C72
C72
C22u6.3X1206
C22u6.3X1206
VCC_1V2
C104
C104
C10u6.3X50805
C10u6.3X50805
C22u6.3X1206
C22u6.3X1206
C0.22U16X
C0.22U16X
C22u6.3X1206
C22u6.3X1206
C10u6.3X50805
C10u6.3X50805
E8
VDDNB9
E10
VDDNB10
F9
VDDNB11
F11
VDDNB12
G10
VDDNB13
G12
VDDNB14
AA8
VDD3
AA10
VDD4
AA12
VDD5
AA14
VDD6
AA16
VDD7
AA18
VDD8
AB7
VDD9
AB9
VDD10
AB11
VDD11
AC4
VDD12
AC5
VDD13
AC8
VDD14
AC10
VDD15
AD2
VDD16
AD3
VDD17
AD7
VDD18
AD9
VDD19
AE10
VDD20
AF7
VDD21
AF9
VDD22
AG4
VDD23
AG5
VDD24
AG7
VDD25
AH2
VDD26
AH3
VDD27
B3
VDD28
C2
VDD31
C4
VDD32
D3
VDD35
D5
VDD36
E4
VDD39
E6
VDD40
F5
VDD43
F7
VDD44
G6
VDD47
G8
VDD48
H7
VDD51
H11
VDD52
H23
VDD53
J8
VDD54
J12
VDD55
J14
VDD56
J16
VDD57
J18
VDD58
J20
VDD59
J22
VDD60
J24
VDD61
K7
VDD62
K9
VDD63
K11
VDD64
K13
VDD65
K15
VDD66
K17
VDD67
K19
VDD68
K21
VDD69
K23
VDD70
L4
VDD71
L5
VDD72
L8
VDD73
L10
VDD74
L12
VDD75
Y17
VDD150
Y19
VDD151
C698
C698
C706
C22u6.3X1206
C22u6.3X1206
C706
C713
C713
C22u6.3X1206
C22u6.3X1206
Bottom side
C709
C709
C686
C10u6.3X50805
C10u6.3X50805
C679
C679
C10u6.3X50805
C10u6.3X50805
C105
C105
C4.7U10Y0805
C4.7U10Y0805
C686
C107
C107
C236
C236
C682
C682
C0.22U16X
C0.22U16X
Bottom side TOP side, place close to CPU socket
C683
C683
C0.01u16X-1
C0.01u16X-1
C723
C723
C10u6.3X50805
C10u6.3X50805
5
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS240
VSS241
C689
C689
C22u6.3X1206
C22u6.3X1206
C680
C680
C10u6.3X50805
C10u6.3X50805
C81
C81
C10u6.3X50805
C10u6.3X50805
C229
C229
C4.7U10Y0805
C4.7U10Y0805
A3
A7
A9
A11
AA4
AA5
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AB2
AB3
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC7
AC9
AC11
AC13
AC15
AC17
AC19
AC21
AC23
AD8
AD10
AD12
AD14
AD16
AD20
AD22
AD24
AE4
AE5
AE11
AF2
AF3
AF8
AF10
AF12
AF14
AF16
AF18
AF20
AF22
AF24
AF26
AF28
AG10
AG11
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH30
AK2
AK14
AK16
AK18
Y14
Y16
Bottom side
C688
C688
C22u6.3X1206
C22u6.3X1206
C22u6.3X1206
C22u6.3X1206
C703
C703
C10u6.3X50805
C10u6.3X50805
C10u6.3X50805
C10u6.3X50805
C108
C108
C0.22U16X
C0.22U16X
C249
C249
C180P50N0402
C180P50N0402
C180P50N0402
C180P50N0402
C700
C700
C691
C691
C79
C79
X_C0.22U16X
X_C0.22U16X
C237
C237
C704
C704
C22u6.3X1206
C22u6.3X1206
C711
C711
C10u6.3X50805
C10u6.3X50805
C80
C80
C4.7U10Y0805
C4.7U10Y0805
VCC_DDR VCCP
MEM_MA_DQS_H[7..0]8,11
MEM_MA_DQS_L[7..0]8,11
MEM_MA_CHECK[7..0]8,11
MEM_MA_DATA[63..0]8,11
D D
C C
B B
De-coupling Caps For DIMMs
Place close to DIMM1
VCC_DDR
C806 C2.2u10Y-RHC806 C2.2u10Y-RH
C807 C2.2u10Y-RHC807 C2.2u10Y-RH
C808 C2.2u10Y-RHC808 C2.2u10Y-RH
C810 C220p25N0402C810 C220p25N0402
Place close to DIMM1
with DIMM2
VCC_DDR
A A
C809 C2.2u10Y-RHC809 C2.2u10Y-RH
Place close to DIMM2
VCC_DDR
C811 C0.1U16Y0402C811 C0.1U16Y0402
C812 C0.1U16Y0402C812 C0.1U16Y0402
VCC3
C813 C2.2u10Y-RHC813 C2.2u10Y-RH
5
5
MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63
VCC_DDR
C235 X_C0.1U16Y0402C235 X_C0.1U16Y0402
C242 X_C0.1U16Y0402C242 X_C0.1U16Y0402
VCC_DDR VCC3
54
DIMM1
DIMM1
3
DQ0
VDD51VDD
VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD
4
DQ1
9
DQ2
10
DQ3
122
DQ4
123
DQ5
128
DQ6
129
DQ7
12
DQ8
13
DQ9
18
DQ10
19
DQ11
131
DQ12
132
DQ13
137
DQ14
138
DQ15
21
DQ16
22
DQ17
27
DQ18
28
DQ19
140
DQ20
141
DQ21
146
DQ22
147
DQ23
30
DQ24
31
DQ25
36
DQ26
37
DQ27
149
DQ28
150
DQ29
155
DQ30
156
DQ31
81
DQ32
82
DQ33
87
DQ34
88
DQ35
200
DQ36
201
DQ37
206
DQ38
207
DQ39
90
DQ40
91
DQ41
96
DQ42
97
DQ43
209
DQ44
210
DQ45
215
DQ46
216
DQ47
99
DQ48
100
DQ49
105
DQ50
106
DQ51
218
DQ52
219
DQ53
224
DQ54
225
DQ55
108
DQ56
109
DQ57
114
DQ58
115
DQ59
227
DQ60
228
DQ61
233
DQ62
234
DQ63
2
VSS
5
VSS
8
VSS
11
VSS
14
VSS
17
VSS
20
VSS
23
VSS
26
VSS
29
VSS
32
VSS
35
VSS
38
VSS
41
VSS
44
VSS
47
VSS
80
VSS
83
VSS
86
VSS
89
VSS
92
VSS
95
VSS
98
VSS
101
VSS
104
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
107
110
113
VSS
116
119
121
124
127
130
133
136
139
DIMM1(CHANNEL-A A0)
ADDRESS=0:0(SA1:SA0)
170
173
176
179
182
VDD
VDD
VDD
VDD
DDR3
DDR3
VSS
VSS
VSS
VSS
VSS
142
145
148
151
154
183
186
189
191
VDD
VDD
VDD
VSS
VSS
VSS
157
160
163
166
4
VTT_DDR
120
240
194
197
VDD
VDD
VDD
VSS
VSS
VSS
199
202
205
VSS
236
VDDSPD
VSS
208
79
68
53
167
VTT
VTT
RSVD
NC/TEST4
NC/PAR_IN
NC/ERR_OUT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
211
214
217
220
223
226
229
232
4
MEM_MA_EVENT# MEM_MB_EVENT#
48
187
198
MEM_MA_ADD0
188
A0
MEM_MA_ADD1
181
A1
FREE1
FREE249FREE3
FREE4
MEM_MA_ADD2
61
A2
MEM_MA_ADD3
180
A3
MEM_MA_ADD4
59
A4
MEM_MA_ADD5
58
A5
MEM_MA_ADD6
178
A6
MEM_MA_ADD7
56
A7
MEM_MA_ADD8
177
A8
MEM_MA_ADD9
175
A9
MEM_MA_ADD10
70
A10/AP
MEM_MA_ADD11
55
A11
MEM_MA_ADD12
174
A12
MEM_MA_ADD13
196
A13
MEM_MA_ADD14
172
A14
MEM_MA_ADD15
171
A15
MEM_MA_CHECK0
39
CB0
MEM_MA_CHECK1
40
CB1
MEM_MA_CHECK2
45
CB2
MEM_MA_CHECK3
46
CB3
MEM_MA_CHECK4
158
CB4
MEM_MA_CHECK5
159
CB5
MEM_MA_CHECK6
164
CB6
MEM_MA_CHECK7
165
CB7
MEM_MA_DQS_H0
7
DQS0
MEM_MA_DQS_L0
6
DQS0#
MEM_MA_DQS_H1
16
DQS1
MEM_MA_DQS_L1
15
DQS1#
MEM_MA_DQS_H2
25
DQS2
MEM_MA_DQS_L2
24
DQS2#
MEM_MA_DQS_H3
34
DQS3
MEM_MA_DQS_L3
33
DQS3#
MEM_MA_DQS_H4
85
DQS4
MEM_MA_DQS_L4
84
DQS4#
MEM_MA_DQS_H5
94
DQS5
MEM_MA_DQS_L5
93
DQS5#
MEM_MA_DQS_H6
103
DQS6
MEM_MA_DQS_L6
102
DQS6#
MEM_MA_DQS_H7
112
DQS7
MEM_MA_DQS_L7
111
DQS7#
MEM_MA_DQS_H8
43
DQS8
MEM_MA_DQS_L8
42
DQS8#
MEM_MA_DM0
125
DM0/DQS9
126
NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
CK1#(NU)
VSS
VSS
235
239
MEM_MA_DM1
134
135
MEM_MA_DM2
143
144
MEM_MA_DM3
152
153
MEM_MA_DM4
203
204
MEM_MA_DM5
212
213
MEM_MA_DM6
221
222
MEM_MA_DM7
230
231
MEM_MA_DM8
161
162
MEM_MA0_ODT0
195
ODT0
MEM_MA0_ODT1
77
ODT1
MEM_MA_CKE0
50
CKE0
MEM_MA_CKE1
169
CKE1
MEM_MA0_CS_L0
193
CS0#
MEM_MA0_CS_L1
76
CS1#
MEM_MA_BANK0
71
BA0
MEM_MA_BANK1
190
BA1
MEM_MA_BANK2
52
BA2
MEM_MA_WE_L
73
WE#
MEM_MA_RAS_L
192
RAS#
MEM_MA_CAS_L
74
CAS#
MEM_MA_RESET# MEM_MB_RESET#
168
RESET#
MEM_MA0_CLK_H0
184
CK0
MEM_MA0_CLK_L0
185
CK0#
MEM_MA0_CLK_H1
63
CK1(NU)
MEM_MA0_CLK_L1
64
MEM_VREF_DQ
1
VREFDQ
MEM_VREF_CA
67
VREFCA
SCLK
118
SCL
SDATA
238
SDA
237
SA1
117
SA0
MEC1
MEC2
MEC3
DDRIII-240P_BLUE-RH
DDRIII-240P_BLUE-RH
MEC1
MEC2
MEC3
MEM_MA_EVENT# 9,11 MEM_MB_EVENT# 9,11
MEM_MA_ADD[15..0] 8,11
Add For ECC 0829
Add For ECC 0829
MEM_MA_DQS_H8 8,11
MEM_MA_DQS_L8 8,11
MEM_MA_DM[7..0] 8,11
MEM_MA_DM8 8,11
MEM_MA0_ODT0 8
MEM_MA0_ODT1 9
MEM_MA_CKE0 8,11
MEM_MA_CKE1 8,11
MEM_MA0_CS_L0 8
MEM_MA0_CS_L1 8
MEM_MA_BANK0 8,11
MEM_MA_BANK1 8,11
MEM_MA_BANK2 8,11
MEM_MA_WE_L 8,11
MEM_MA_RAS_L 8,11
MEM_MA_CAS_L 8,11
MEM_MA0_CLK_H0 8
MEM_MA0_CLK_L0 8
MEM_MA0_CLK_H1 9
MEM_MA0_CLK_L1 9
MEM_VREF_DQ
MEM_VREF_CA MEM_VREF_CA
SCLK 11,12,18,26
SDATA 11,12,18,26
VCC_DDR
R48
R48
C382
C382
C0.1U16Y0402
C0.1U16Y0402
15R1%
15R1%
C582
C582
R568
R568
15R1%
15R1%
Add For ECC 0829
MEM_VREF_DQ
C0.1U16Y0402
C0.1U16Y0402
C805
C1000P50X0402
C805
C1000P50X0402
MEM_MA_RESET# 9,11
VCC_DDR
C804
C1000P50X0402
C804
C1000P50X0402
3
MEM_MB_DQS_H[7..0]8,11
MEM_MB_DQS_L[7..0]8,11
MEM_MB_CHECK[7..0]8,11
MEM_VREF_CA
C785
C1000P50X0402
C785
C1000P50X0402
MEM_MB_DATA0
MEM_MB_DATA1
MEM_MB_DATA2
MEM_MB_DATA3
MEM_MB_DATA4
MEM_MB_DATA5
MEM_MB_DATA6
MEM_MB_DATA7
MEM_MB_DATA8
MEM_MB_DATA9
MEM_MB_DATA10
MEM_MB_DATA11
MEM_MB_DATA12
MEM_MB_DATA13
MEM_MB_DATA14
MEM_MB_DATA15
MEM_MB_DATA16
MEM_MB_DATA17
MEM_MB_DATA18
MEM_MB_DATA19
MEM_MB_DATA20
MEM_MB_DATA21
MEM_MB_DATA22
MEM_MB_DATA23
MEM_MB_DATA24
MEM_MB_DATA25
MEM_MB_DATA26
MEM_MB_DATA27
MEM_MB_DATA28
MEM_MB_DATA29
MEM_MB_DATA30
MEM_MB_DATA31
MEM_MB_DATA32
MEM_MB_DATA33
MEM_MB_DATA34
MEM_MB_DATA35
MEM_MB_DATA36
MEM_MB_DATA37
MEM_MB_DATA38
MEM_MB_DATA39
MEM_MB_DATA40
MEM_MB_DATA41
MEM_MB_DATA42
MEM_MB_DATA43
MEM_MB_DATA44
MEM_MB_DATA45
MEM_MB_DATA46
MEM_MB_DATA47
MEM_MB_DATA48
MEM_MB_DATA49
MEM_MB_DATA50
MEM_MB_DATA51
MEM_MB_DATA52
MEM_MB_DATA53
MEM_MB_DATA54
MEM_MB_DATA55
MEM_MB_DATA56
MEM_MB_DATA57
MEM_MB_DATA58
MEM_MB_DATA59
MEM_MB_DATA60
MEM_MB_DATA61
MEM_MB_DATA62
MEM_MB_DATA63
C772
C1000P50X0402
C772
C1000P50X0402
MEM_MB_DATA[63..0]8,11 MEM_MB_ADD[15..0] 8,11
C34
C34
R44
R44
C0.1U16Y0402
C0.1U16Y0402
15R1%
15R1%
C36
C0.1U16Y0402
C36
C0.1U16Y0402
R55
R55
15R1%
15R1%
3
VCC_DDR VCC3
54
DIMM2
DIMM2
3
DQ0
VDD51VDD
VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD
4
DQ1
9
DQ2
10
DQ3
122
DQ4
123
DQ5
128
DQ6
129
DQ7
12
DQ8
13
DQ9
18
DQ10
19
DQ11
131
DQ12
132
DQ13
137
DQ14
138
DQ15
21
DQ16
22
DQ17
27
DQ18
28
DQ19
140
DQ20
141
DQ21
146
DQ22
147
DQ23
30
DQ24
31
DQ25
36
DQ26
37
DQ27
149
DQ28
150
DQ29
155
DQ30
156
DQ31
81
DQ32
82
DQ33
87
DQ34
88
DQ35
200
DQ36
201
DQ37
206
DQ38
207
DQ39
90
DQ40
91
DQ41
96
DQ42
97
DQ43
209
DQ44
210
DQ45
215
DQ46
216
DQ47
99
DQ48
100
DQ49
105
DQ50
106
DQ51
218
DQ52
219
DQ53
224
DQ54
225
DQ55
108
DQ56
109
DQ57
114
DQ58
115
DQ59
227
DQ60
228
DQ61
233
DQ62
234
DQ63
2
VSS
5
VSS
8
VSS
11
VSS
14
VSS
17
VSS
20
VSS
23
VSS
26
VSS
29
VSS
32
VSS
35
VSS
38
VSS
41
VSS
44
VSS
47
VSS
80
VSS
83
VSS
86
VSS
89
VSS
92
VSS
95
VSS
98
VSS
101
VSS
104
VSS
VSS
VSS
VSS
VSS
VSS
107
110
113
116
119
VSS
VSS
VSS
VSS
VSS
VSS
121
124
127
130
133
136
2
170
173
176
179
182
183
186
189
191
194
197
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DDR3
DDR3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
139
142
145
DIMM2(CHANNEL-B B0)
ADDRESS=0:1(SA1:SA0)
2
VSS
148
151
154
157
160
163
166
199
202
205
TP133TP133
TP134TP134
VSS
236
VDDSPD
VSS
208
VTT_DDR
120
VTT
VSS
VSS
211
214
240
79
48
187
198
68
53
167
VTT
RSVD
FREE1
FREE249FREE3
NC/TEST4
NC/PAR_IN
NC/ERR_OUT
DM0/DQS9
NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
CK1#(NU)
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
217
220
223
226
229
232
235
239
MEM_VREF_DQ
MEM_VREF_CA
A0
A1
FREE4
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQS0
DQS0#
DQS1
DQS1#
DQS2
DQS2#
DQS3
DQS3#
DQS4
DQS4#
DQS5
DQS5#
DQS6
DQS6#
DQS7
DQS7#
DQS8
DQS8#
ODT0
ODT1
CKE0
CKE1
CS0#
CS1#
BA0
BA1
BA2
WE#
RAS#
CAS#
RESET#
CK0
CK0#
CK1(NU)
VREFDQ
VREFCA
SCL
SDA
SA1
SA0
MEC1
MEC2
MEC3
DDRIII-240P_BLANK-RH
DDRIII-240P_BLANK-RH
MEC1
MEC2
MEC3
188
181
61
180
59
58
178
56
177
175
70
55
174
196
172
171
39
40
45
46
158
159
164
165
7
6
16
15
25
24
34
33
85
84
94
93
103
102
112
111
43
42
125
126
134
135
143
144
152
153
203
204
212
213
221
222
230
231
161
162
195
77
50
169
193
76
71
190
52
73
192
74
168
184
185
63
64
1
67
118
238
237
117
MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15
MEM_MB_CHECK0
MEM_MB_CHECK1
MEM_MB_CHECK2
MEM_MB_CHECK3
MEM_MB_CHECK4
MEM_MB_CHECK5
MEM_MB_CHECK6
MEM_MB_CHECK7
MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H8
MEM_MB_DQS_L8
MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7
MEM_MB_DM8
MEM_MB0_ODT0
MEM_MB0_ODT1
MEM_MB_CKE0
MEM_MB_CKE1
MEM_MB0_CS_L0
MEM_MB0_CS_L1
MEM_MB_BANK0
MEM_MB_BANK1
MEM_MB_BANK2
MEM_MB_WE_L
MEM_MB_RAS_L
MEM_MB_CAS_L
MEM_MB0_CLK_H0
MEM_MB0_CLK_L0
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_VREF_DQ
MEM_VREF_CA
SCLK
SDATA
VCC3
Add For ECC 0829
Add For ECC 0829
MEM_MB_DQS_H8 8,11
MEM_MB_DQS_L8 8,11
MEM_MB_DM[7..0] 8,11
Add For ECC 0829
MEM_MB_DM8 8,11
MEM_MB0_ODT0 8
MEM_MB0_ODT1 9
MEM_MB_CKE0 8,11
MEM_MB_CKE1 8,11
MEM_MB0_CS_L0 8
MEM_MB0_CS_L1 8
MEM_MB_BANK0 8,11
MEM_MB_BANK1 8,11
MEM_MB_BANK2 8,11
MEM_MB_WE_L 8,11
MEM_MB_RAS_L 8,11
MEM_MB_CAS_L 8,11
MEM_MB0_CLK_H0 8
MEM_MB0_CLK_L0 8
MEM_MB0_CLK_H1 9
MEM_MB0_CLK_L1 9
MEM_VREF_DQ
Title
Title
Title
FIRST LOGICAL DDR DIMM
FIRST LOGICAL DDR DIMM
FIRST LOGICAL DDR DIMM
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
VL390 0A
VL390 0A
VL390 0A
Date: Sheet
Date: Sheet
Date: Sheet
1
MEM_MB_RESET# 9,11
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
10 37Tuesday, September 09, 2008
10 37Tuesday, September 09, 2008
10 37Tuesday, September 09, 2008
of
of
1
of
5
MEM_MA_DQS_H[7..0]8,10
MEM_MA_DQS_L[7..0]8,10
MEM_MA_CHECK[7..0]8,10
MEM_MA_DATA[63..0]8,10
D D
C C
B B
MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63
De-coupling Caps For DIMMs
Place close to DIMM3
VCC_DDR
C814 C2.2u10Y-RHC814 C2.2u10Y-RH
A A
Place close to DIMM3
with DIMM4
VCC_DDR
C821 C0.1U16Y0402C821 C0.1U16Y0402
C822 C0.1U16Y0402C822 C0.1U16Y0402
C829 C0.1U16Y0402C829 C0.1U16Y0402
VCC3
C824 C2.2u10Y-RHC824 C2.2u10Y-RH
5
VCC_DDR VCC3
54
DIMM3
DIMM3
3
DQ0
VDD51VDD
4
DQ1
9
DQ2
10
DQ3
122
DQ4
123
DQ5
128
DQ6
129
DQ7
12
DQ8
13
DQ9
18
DQ10
19
DQ11
131
DQ12
132
DQ13
137
DQ14
138
DQ15
21
DQ16
22
DQ17
27
DQ18
28
DQ19
140
DQ20
141
DQ21
146
DQ22
147
DQ23
30
DQ24
31
DQ25
36
DQ26
37
DQ27
149
DQ28
150
DQ29
155
DQ30
156
DQ31
81
DQ32
82
DQ33
87
DQ34
88
DQ35
200
DQ36
201
DQ37
206
DQ38
207
DQ39
90
DQ40
91
DQ41
96
DQ42
97
DQ43
209
DQ44
210
DQ45
215
DQ46
216
DQ47
99
DQ48
100
DQ49
105
DQ50
106
DQ51
218
DQ52
219
DQ53
224
DQ54
225
DQ55
108
DQ56
109
DQ57
114
DQ58
115
DQ59
227
DQ60
228
DQ61
233
DQ62
234
DQ63
2
VSS
5
VSS
8
VSS
11
VSS
14
VSS
17
VSS
20
VSS
23
VSS
26
VSS
29
VSS
32
VSS
35
VSS
38
VSS
41
VSS
44
VSS
47
VSS
80
VSS
83
VSS
86
VSS
89
VSS
92
VSS
95
VSS
98
VSS
101
VSS
104
VSS
VSS
VSS
VSS
107
110
113
116
Vref-DQ : Reference voltage for DQ0每DQ63, CB0每CB7 and PAR_IN. When in single ended mode used for
每
DQS7.
DQS0
Vref-CA : Reference voltage for A0-A15, BA0
RESET#(Output) : A synchronously forces all registered output LOW when RESET# is LOW.
This signal can be used during power up to ensure that CKE is LOW and DQs are High-Z.
VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
119
121
124
127
130
133
136
139
DIMM3(CHANNEL-A A1)
ADDRESS=1:0(SA1:SA0)
170
173
176
179
182
183
VDD
VDD
VDD
VDD
DDR3
DDR3
VSS
VSS
VSS
VSS
VSS
142
145
148
151
154
157
186
189
191
194
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
160
163
166
199
4
VTT_DDR
120
240
197
VDD
VDD
VSS
VSS
202
205
VSS
236
VDDSPD
VSS
208
211
79
68
53
167
VTT
VTT
RSVD
NC/TEST4
NC/PAR_IN
NC/ERR_OUT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
214
217
220
223
226
229
232
4
MEM_MA_EVENT#
48
187
198
MEM_MA_ADD0
188
A0
MEM_MA_ADD1
181
A1
FREE1
FREE249FREE3
FREE4
MEM_MA_ADD2
61
A2
MEM_MA_ADD3
180
A3
MEM_MA_ADD4
59
A4
MEM_MA_ADD5
58
A5
MEM_MA_ADD6
178
A6
MEM_MA_ADD7
56
A7
MEM_MA_ADD8
177
A8
MEM_MA_ADD9
175
A9
MEM_MA_ADD10
70
A10/AP
MEM_MA_ADD11
55
A11
MEM_MA_ADD12
174
A12
MEM_MA_ADD13
196
A13
MEM_MA_ADD14
172
A14
MEM_MA_ADD15
171
A15
MEM_MA_CHECK0
39
CB0
MEM_MA_CHECK1
40
CB1
MEM_MA_CHECK2
45
CB2
MEM_MA_CHECK3
46
CB3
MEM_MA_CHECK4
158
CB4
MEM_MA_CHECK5
159
CB5
MEM_MA_CHECK6
164
CB6
MEM_MA_CHECK7
165
CB7
MEM_MA_DQS_H0
7
DQS0
MEM_MA_DQS_L0
6
DQS0#
MEM_MA_DQS_H1
16
DQS1
MEM_MA_DQS_L1
15
DQS1#
MEM_MA_DQS_H2
25
DQS2
MEM_MA_DQS_L2
24
DQS2#
MEM_MA_DQS_H3
34
DQS3
MEM_MA_DQS_L3
33
DQS3#
MEM_MA_DQS_H4
85
DQS4
MEM_MA_DQS_L4
84
DQS4#
MEM_MA_DQS_H5
94
DQS5
MEM_MA_DQS_L5
93
DQS5#
MEM_MA_DQS_H6
103
DQS6
MEM_MA_DQS_L6
102
DQS6#
MEM_MA_DQS_H7
112
DQS7
MEM_MA_DQS_L7
111
DQS7#
MEM_MA_DQS_H8
43
DQS8
MEM_MA_DQS_L8
42
DQS8#
MEM_MA_DM0
125
DM0/DQS9
126
NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
CK1#(NU)
VSS
VSS
235
239
MEM_MA_DM1
134
135
MEM_MA_DM2
143
144
MEM_MA_DM3
152
153
MEM_MA_DM4
203
204
MEM_MA_DM5
212
213
MEM_MA_DM6
221
222
MEM_MA_DM7
230
231
MEM_MA_DM8
161
162
MEM_MA1_ODT0
195
ODT0
MEM_MA1_ODT1
77
ODT1
MEM_MA_CKE0
50
CKE0
MEM_MA_CKE1
169
CKE1
MEM_MA1_CS_L0
193
CS0#
76
CS1#
MEM_MA_BANK0
71
BA0
MEM_MA_BANK1
190
BA1
MEM_MA_BANK2
52
BA2
MEM_MA_WE_L
73
WE#
MEM_MA_RAS_L
192
RAS#
MEM_MA_CAS_L
74
CAS#
MEM_MA_RESET# MEM_MB_RESET#
168
RESET#
MEM_MA1_CLK_H0
184
CK0
MEM_MA1_CLK_L0
185
CK0#
MEM_MA1_CLK_H1
63
CK1(NU)
MEM_MA1_CLK_L1
64
MEM_VREF_DQ
1
VREFDQ
MEM_VREF_CA
67
VREFCA
SCLK
118
SCL
SDATA
238
SDA
237
SA1
117
SA0
MEC1
MEC2
MEC3
DDRIII-240P_BLUE-RH
DDRIII-240P_BLUE-RH
MEC1
MEC2
MEC3
每
BA2, RAS#, CAS#, WE#, S0#, S01#, CKE0, CKE1, ODT0 and ODT1.
MEM_MA_EVENT# 9,10
MEM_MA_ADD[15..0] 8,10
Add For ECC 0829
Add For ECC 0829
MEM_MA_DQS_H8 8,10
MEM_MA_DQS_L8 8,10
MEM_MA_DM[7..0] 8,10
Add For ECC 0829
MEM_MA_DM8 8,10
MEM_MA1_ODT0 8
MEM_MA1_ODT1 9
MEM_MA_CKE0 8,10
MEM_MA_CKE1 8,10
MEM_MA1_CS_L0 8
MEM_MA1_CS_L1 8
MEM_MA_BANK0 8,10
MEM_MA_BANK1 8,10
MEM_MA_BANK2 8,10
MEM_MA_WE_L 8,10
MEM_MA_RAS_L 8,10
MEM_MA_CAS_L 8,10
MEM_MA1_CLK_H0 9
MEM_MA1_CLK_L0 9
MEM_MA1_CLK_H1 8
MEM_MA1_CLK_L1 8
MEM_VREF_CA
SCLK 10,12,18,26
VCC3
SDATA 10,12,18,26
MEM_MA_RESET# 9,10
3
MEM_MB_DQS_H[7..0]8,10
MEM_MB_DQS_L[7..0]8,10
MEM_MB_CHECK[7..0]8,10
MEM_MB_DATA[63..0]8,10
3
MEM_MB_DATA0
MEM_MB_DATA1
MEM_MB_DATA2
MEM_MB_DATA3
MEM_MB_DATA4
MEM_MB_DATA5
MEM_MB_DATA6
MEM_MB_DATA7
MEM_MB_DATA8
MEM_MB_DATA9
MEM_MB_DATA10
MEM_MB_DATA11
MEM_MB_DATA12
MEM_MB_DATA13
MEM_MB_DATA14
MEM_MB_DATA15
MEM_MB_DATA16
MEM_MB_DATA17
MEM_MB_DATA18
MEM_MB_DATA19
MEM_MB_DATA20
MEM_MB_DATA21
MEM_MB_DATA22
MEM_MB_DATA23
MEM_MB_DATA24
MEM_MB_DATA25
MEM_MB_DATA26
MEM_MB_DATA27
MEM_MB_DATA28
MEM_MB_DATA29
MEM_MB_DATA30
MEM_MB_DATA31
MEM_MB_DATA32
MEM_MB_DATA33
MEM_MB_DATA34
MEM_MB_DATA35
MEM_MB_DATA36
MEM_MB_DATA37
MEM_MB_DATA38
MEM_MB_DATA39
MEM_MB_DATA40
MEM_MB_DATA41
MEM_MB_DATA42
MEM_MB_DATA43
MEM_MB_DATA44
MEM_MB_DATA45
MEM_MB_DATA46
MEM_MB_DATA47
MEM_MB_DATA48
MEM_MB_DATA49
MEM_MB_DATA50
MEM_MB_DATA51
MEM_MB_DATA52
MEM_MB_DATA53
MEM_MB_DATA54
MEM_MB_DATA55
MEM_MB_DATA56
MEM_MB_DATA57
MEM_MB_DATA58
MEM_MB_DATA59
MEM_MB_DATA60
MEM_MB_DATA61
MEM_MB_DATA62
MEM_MB_DATA63
VCC_DDR VCC3
54
DIMM4
DIMM4
3
DQ0
VDD51VDD
VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD
4
DQ1
9
DQ2
10
DQ3
122
DQ4
123
DQ5
128
DQ6
129
DQ7
12
DQ8
13
DQ9
18
DQ10
19
DQ11
131
DQ12
132
DQ13
137
DQ14
138
DQ15
21
DQ16
22
DQ17
27
DQ18
28
DQ19
140
DQ20
141
DQ21
146
DQ22
147
DQ23
30
DQ24
31
DQ25
36
DQ26
37
DQ27
149
DQ28
150
DQ29
155
DQ30
156
DQ31
81
DQ32
82
DQ33
87
DQ34
88
DQ35
200
DQ36
201
DQ37
206
DQ38
207
DQ39
90
DQ40
91
DQ41
96
DQ42
97
DQ43
209
DQ44
210
DQ45
215
DQ46
216
DQ47
99
DQ48
100
DQ49
105
DQ50
106
DQ51
218
DQ52
219
DQ53
224
DQ54
225
DQ55
108
DQ56
109
DQ57
114
DQ58
115
DQ59
227
DQ60
228
DQ61
233
DQ62
234
DQ63
2
VSS
5
VSS
8
VSS
11
VSS
14
VSS
17
VSS
20
VSS
23
VSS
26
VSS
29
VSS
32
VSS
35
VSS
38
VSS
41
VSS
44
VSS
47
VSS
80
VSS
83
VSS
86
VSS
89
VSS
92
VSS
95
VSS
98
VSS
101
VSS
104
VSS
VSS
VSS
VSS
VSS
VSS
VSS
107
110
113
116
119
121
170
VSS
VSS
VSS
VSS
VSS
VSS
VSS
124
127
130
133
136
139
142
DIMM2(CHANNEL-B B1)
ADDRESS=1:1(SA1:SA0)
2
173
176
179
182
183
186
189
VDD
VDD
VDD
VDD
VDD
VDD
DDR3
DDR3
VSS
VSS
VSS
VSS
VSS
VSS
145
148
151
154
157
160
163
2
1
VTT_DDR
120
240
191
194
197
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
166
199
202
205
236
VSS
208
VDDSPD
VSS
VSS
211
79
48
68
53
167
VTT
VTT
RSVD
FREE1
FREE249FREE3
NC/TEST4
NC/PAR_IN
NC/ERR_OUT
DM0/DQS9
NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
CK1#(NU)
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
214
217
220
223
226
229
232
235
239
187
198
A0
A1
FREE4
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQS0
DQS0#
DQS1
DQS1#
DQS2
DQS2#
DQS3
DQS3#
DQS4
DQS4#
DQS5
DQS5#
DQS6
DQS6#
DQS7
DQS7#
DQS8
DQS8#
ODT0
ODT1
CKE0
CKE1
CS0#
CS1#
BA0
BA1
BA2
WE#
RAS#
CAS#
RESET#
CK0
CK0#
CK1(NU)
VREFDQ
VREFCA
SCL
SDA
SA1
SA0
MEC1
MEC2
MEC3
DDRIII-240P_BLANK-RH
DDRIII-240P_BLANK-RH
MEC1
MEC2
MEC3
188
181
61
180
59
58
178
56
177
175
70
55
174
196
172
171
39
40
45
46
158
159
164
165
7
6
16
15
25
24
34
33
85
84
94
93
103
102
112
111
43
42
125
126
134
135
143
144
152
153
203
204
212
213
221
222
230
231
161
162
195
77
50
169
193
76
71
190
52
73
192
74
168
184
185
63
64
1
67
118
238
237
117
MEM_MB_EVENT#
MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15
MEM_MB_CHECK0
MEM_MB_CHECK1
MEM_MB_CHECK2
MEM_MB_CHECK3
MEM_MB_CHECK4
MEM_MB_CHECK5
MEM_MB_CHECK6
MEM_MB_CHECK7
MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H8
MEM_MB_DQS_L8
MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7
MEM_MB_DM8
MEM_MB1_ODT0
MEM_MB1_ODT1
MEM_MB_CKE0
MEM_MB_CKE1
MEM_MB1_CS_L0
MEM_MB1_CS_L1MEM_MA1_CS_L1
MEM_MB_BANK0
MEM_MB_BANK1
MEM_MB_BANK2
MEM_MB_WE_L
MEM_MB_RAS_L
MEM_MB_CAS_L
MEM_MB1_CLK_H0
MEM_MB1_CLK_L0
MEM_MB1_CLK_H1
MEM_MB1_CLK_L1
MEM_VREF_DQ
MEM_VREF_CA
SCLK
SDATA
MEM_MB_EVENT# 9,10
MEM_MB_ADD[15..0] 8,10
Add For ECC 0829
Add For ECC 0829
MEM_MB_DQS_H8 8,10
MEM_MB_DQS_L8 8,10
MEM_MB_DM[7..0] 8,10
Add For ECC 0829
MEM_MB_DM8 8,10
MEM_MB1_ODT0 8
MEM_MB1_ODT1 9
MEM_MB_CKE0 8,10
MEM_MB_CKE1 8,10
MEM_MB1_CS_L0 8
MEM_MB1_CS_L1 8
MEM_MB_BANK0 8,10
MEM_MB_BANK1 8,10
MEM_MB_BANK2 8,10
MEM_MB_WE_L 8,10
MEM_MB_RAS_L 8,10
MEM_MB_CAS_L 8,10
MEM_MB1_CLK_H0 9
MEM_MB1_CLK_L0 9
MEM_MB1_CLK_H1 8
MEM_MB1_CLK_L1 8
MEM_VREF_DQMEM_VREF_DQ
MEM_VREF_CA
VCC3
Title
Title
Title
SECOND LOGICAL DDR DIMM
SECOND LOGICAL DDR DIMM
SECOND LOGICAL DDR DIMM
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
VL390 0A
VL390 0A
VL390 0A
Date: Sheet
Date: Sheet
Date: Sheet
MEM_MB_RESET# 9,10
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
1
11 37Tuesday, September 09, 2008
11 37Tuesday, September 09, 2008
11 37Tuesday, September 09, 2008
of
of
of
5
Clock Gen SLG8LP625
CLK_VDD
L21
VCC3
D D
VCC3
CLK_VDD
VCC3
C C
B B
L21
600L500mA-300_0805
600L500mA-300_0805
L25
L25
600L500mA-300_0805
600L500mA-300_0805
C2.2u10Y-RH
C2.2u10Y-RH
L20
L20
600L500mA-300_0805
600L500mA-300_0805
L19
L19
600L500mA-300_0805
600L500mA-300_0805
FP_RST#18,26,34
R494 X_0R0402R494 X_0R0402
R207and R198 have
been change value
for support RS780
2007/08/07 MS-7500
OSC_14M_NB R207/R198
RS780 (Single-ended) 1.1V 200R/100R
RS740 3.3V 33R Serial
C364
C364
C22u6.3X1206
C22u6.3X1206
C0.1U16Y0402
C0.1U16Y0402
C348
C348
C0.1U16Y0402
C0.1U16Y0402
C321
C321
C2.2u10Y-RH
C2.2u10Y-RH
C335
C335
C2.2u10Y-RH
C2.2u10Y-RH
VCC3
SB_OSC_14M17
NB_OSC_14M15
Silego CRB Suggested
150 MILS WIDTH
Place Close to PIN.33,40,48,28,11,14,21
C358
C358
C354
C371
C371
C0.1U16Y0402
C0.1U16Y0402
C343
C343
C22u6.3X1206
C22u6.3X1206
Place Close to PIN.52
Place Close to PIN.56
C354
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
15 MILS WIDTH
CLK_VDDA
C347
C347
12 MILS WIDTH
CLK_VDDREF
12 MILS WIDTH
CLK_VDD48
C319 C27p50N0402C319 C27p50N0402 R263 0R0402R263 0R0402
14.318MHZ16P_D-RH
14.318MHZ16P_D-RH
C338 C22P50N0402C338 C22P50N0402
R210 4.7KR0402R210 4.7KR0402
R224
R224
X_75R1%0402
X_75R1%0402
CLK_VDD
4
C324
C324
C363
C0.1U16Y0402
C0.1U16Y0402
Y1
Y1
SCLK10,11,18,26
SDATA10,11,18,26
1 2
C363
C0.1U16Y0402
C0.1U16Y0402
C333
C333
C0.1U16Y0402
C0.1U16Y0402
R656 X_110R1%0402R656 X_110R1%0402
R207 158R1%0402R207 158R1%0402
R198
R198
90.9R1%0402
90.9R1%0402
C368
C368
C0.1U16Y0402
C0.1U16Y0402
CLK_VDDA
CLK_VDDREF
CLK_VDD48
CLK_VDD
R216
R216
X_1MR0402
X_1MR0402
CLK_RST#
R496R496
R582R582
R211 1KR0402R211 1KR0402
CLK_VDD
R510
R510
X_8.2KR0402
X_8.2KR0402
R205
R205
8.2KR0402
8.2KR0402
C369
C369
CLK_PD#
HWM_14M_RR
OSC14M_REFOUT
NB_OSC_14M_R
U15
U15
36
VDD_A
35
VSS_A
52
VDD_REF
53
VSS_REF
56
VDD_48
3
VSS_48
33
VDD
34
VSS
40
VDD_CPU
39
VSS_CPU
48
VDD_HTT
45
VSS_HTT
28
VDD_ATIGCLK
11
VDD_SRC
14
VDD_SRC
21
VDD_SB_SRC
24
VSS_ATIGCLK
27
VSS_ATIGCLK
10
VSS_SRC
15
VSS_SRC
20
VSS_SB_SRC
54
XTAL_IN
55
XTAL_OUT
44
RESTORE#
4
SCL
5
SDA
43
PD#
51
REF_0/SEL_HTT66
50
REF_1
49
REF_2
3.3V
SLG8LP625TTR_TSSOP56-RH
SLG8LP625TTR_TSSOP56-RH
3
CPU_K8_0
CPU_K8_0#
CPU_K8_1
CPU_K8_1#
ATIGCLK_0
ATIGCLK_0#
ATIGCLK_1
ATIGCLK_1#
ATIGCLK_2
ATIGCLK_2#
SB_SRC_0
SB_SRC_0#
SB_SRC_1
SB_SRC_1#
SRC_0
SRC_0#
SRC_1
SRC_1#
SRC_2
SRC_2#
SRC_3
SRC_3#
HTT_0/66M_0
HTT_0#/66M_1
48MHz_0
48MHz_1
42
41
38
37
NB_GXF_CLK_R
32
NB_GXF_CLK#_R
31
30
29
PE16_GXF_CLK_R
26
PE16_GXF_CLK#_R
25
NB_SBREF_CLK_R
23
NB_SBREF_CLK#_R
22
SB_LINK_CLK_R
19
SB_LINK_CLK#_R
18
PE1_GPP_CLK1_R
17
PE1_GPP_CLK1#_R
16
13
12
LAN_CLK_R
9
LAN_CLK#_R
8
7
6
NBHTT_CLK_R
47
NBHTT_CLK#_R
46
SIO_48M_CLK_R
2
USB_48M_CLK_R
1
Clock chip has internal serial terminations
for differencial pairs, external resistors are
reserved for debug purpose.
R265 0R0402R265 0R0402
R268 0R0402R268 0R0402
R250 0R0402R250 0R0402
R267 0R0402R267 0R0402
R261 0R0402R261 0R0402
R274 0R0402R274 0R0402
R269 0R0402R269 0R0402
R266 0R0402R266 0R0402
R264 0R0402R264 0R0402
R504 0R0402R504 0R0402
R505 0R0402R505 0R0402
R208 0R0402R208 0R0402
R209 0R0402R209 0R0402
R223 33R0402R223 33R0402
R222 33R0402R222 33R0402
2
NB CLOCK INPUT TABLE
NB CLOCKS
HT_REFCLKP
HT_REFCLKN
REFCLK_P
REFCLK_N
GFX_REFCLK
GPP_REFCLK 100M DIFF(OUT)
GPPSB_REFCLK 100M DIFF
66M SE(SE)
NC
14M SE (3.3V) 14M SE (1.1V)
NC vref
100M DIFF
NC
100M DIFF
* RS780 can be used as clock buffer to output two PCIE referecence clocks
By deault, chip will configured as input mode, BIOS can program it to output mode.
RS740 RS780
CPU_CLK 7
CPU_CLK# 7
NB_GXF_CLK 15
NB_GXF_CLK# 15
PE16_GXF_CLK 30
PE16_GXF_CLK# 30
NB_SBREF_CLK 15
NB_SBREF_CLK# 15
SB_LINK_CLK 17
SB_LINK_CLK# 17
PE1_GPP_CLK1 30
PE1_GPP_CLK1# 30
LAN_CLK 24
LAN_CLK# 24
NBHTT_CLK 15
NBHTT_CLK# 15
SIO_48M_CLK 25
USB_48M_CLK 18
To CPU
To North Bridge GXF
To PCI-E x16 Slot 100MHz
To North Bridge SB Reference clock
To South Bridge Link clock
PCIEx1 Slot-1 GPP
PCIE LAN 100MHz GPP
NB HTT 100M Clock(RS780)
NB HTT 66M Clock (RS740)
Super I/O 48MHz Clock
USB 48MHz Clock
1- PLACE ALL THE SERIES TERMINATION RESISTORS AS CLOSE AS U6 AS POSSIBLE
2- ROUTE ALL CPUCLK/#, NBSRCCLK/#, GPPCLK/# AS DIFFERENT PAIR RULE
3- PUT DECOUPLING CAPS CLOSE TO U15 POWER PIN
4-Enabled spread spectrum on all high frequency clocks; set to 0.5% down spread, for EMI reasons
100M DIFF
100M DIFF
100M DIFF(IN/OUT)*
Place close to Clock GEN
CPU_CLK
CPU_CLK#
SIO_48M_CLK
USB_48M_CLK
C780
C780
C5P50N0402
C5P50N0402
1
C779
C779
X_C5P50N0402
X_C5P50N0402
100M DIFF
100M DIFF
C815
C815
X_C5P50N0402
X_C5P50N0402
C816
C816
X_C5P50N0402
X_C5P50N0402
VCC3_SB
clock generator should not be enable before
+1.2v(VCC_1V2 is this design) is ready.
VCC5_SB
R663
R663
4.7KR0402
B
C853
C853
C1U10Y
C1U10Y
4.7KR0402
1.2V_PWRGD_R
CE
Q96
Q96
N-MMBT3904
N-MMBT3904
A A
VCC_1V2
R664 10KR0402R664 10KR0402
5
R665
R665
10KR0402
10KR0402
1.2V_PWRGD CLK_PD#
DS
Q98
Q98
G
N-2N7002_SOT23
N-2N7002_SOT23
4
D48
D48
S-RB751V-40_SOD323-RH
S-RB751V-40_SOD323-RH
REF_0/SEL_HTT66 (Pin51)1 HTT_0/66M_0 & HTT_0#/66M_1 (Pin 46,47)
RS780
0
RS740
3
Configure as differential 100MHz output
Configure as single-ended 66MHz output
2
TP110TP110
TP111TP111
TP112TP112
TP113TP113
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Clock Gen ICS9LPR472
Clock Gen ICS9LPR472
Clock Gen ICS9LPR472
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
MICRO-START INT'L CO.,LTD.
VL390 0A
VL390 0A
VL390 0A
CLK_VDD
CLK_VDDA
CLK_VDD48
CLK_VDDREF
1
of
of
of
12 37Tuesday, September 09, 2008
12 37Tuesday, September 09, 2008
12 37Tuesday, September 09, 2008
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