MSI MS-7389L2 Schematics

1

VL390 FOR uBTX

Cover Sheet BLOCK DIAGRAM

1 2

CPU:

AMD AM3

3GPIO Configuration Clock Distribution Power Deliver Chart VRM Intersil 6323 3 Phase AMD Socket AM3 DDR III DIMM 1 & 2 & 3 & 4

Clock Gen SLG8LP625

AMD - RS780 AMD - SB710

A A

DVI / VGA Connector

SATA/KB/ FAN Control LAN-Realtek 8111CP

LPC I/O ITE8720 ACPI UPI & SYS POWER Core Power & DDR Power Azalia CODEC ALC662/888 USB CONNECTORS PCI EXPRESS X16 & X 1 SLOT

4

5

6

7 ~ 9

10 ~ 11

12

13 ~ 16

17 ~ 21

22

23

24

25

26

27

28

29

30

System Chipset:

AMD - RS780(North Bridge) AMD - SB710 (South Bridge)

On Board Chipset:

BIOS - SPI Azalia CODEC - Realtek ALC662(Default)/888 LPC Super I/O -- ITE8720 CLOCK GEN --SLG8LP625 LAN-Realtek 8111CP TMP - INFINEON/SLB9635T

Main Memory:

DDR III * 4

Expansion Slots:

PCI Express X16 Slot * 1 PCI Express X1 Slot * 1 PCI 2.3 Slot * 2

PCI Slot 1&2 TMP ATX & Front Panel Auto BOM Manual History History

31

32

33

34

35

36

Intersil PWM:

Controller - Intersil 6323 3 Phase

MICRO-START INT'L CO.,LTD.

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Project RS-780 BLOCK DIAGRAM

DDRIII 800~1333

D D

AMD AM3

AM3 SOCKET

7,8,9

OUT

16x16 2.6GHZ(HT3)HyperTransport LINK

IN

128bit

DDRIII 800~1333

128bit

UNBUFFERED DDRIII DIMM1

UNBUFFERED DDRIII DIMM2

DDRIII FIRST LOGICAL DIMM DDRIII SECOND LOGICAL DIMM

10

UNBUFFERED DDRIII DIMM3

UNBUFFERED DDRIII DIMM4

11

Display Port

ATI NB - RS780

HyperTransport LINK0 CPU I/F 1 16X PCIE VIDEO I/F

USB 2.0

1 4X PCIE I/F WITH SB 2 1X PCIE I/F

A-LINK

4X PCIE

ATI SB - SB710

USB2.0 (12) SATA2 (4 PORTS) AC97 2.3 HD AUDIO 1.0 ACPI 1.1 SPI I/F PCI/PCI BRIDGE ASF

17,18,19,20,21

ITE SIO

IT8720

13,14,15,16

LPC BUS

26

AZALIA

SERIAL ATA 2.0

SPI Bus

HD AUDIO HDR

AZALIA CODEC

SATA#0 SATA#1

SPI ROM 8M

TPM

33

29

SATA#2 SATA#3

24

24 24 24

19

PCIE GFX x16

C C

4X1 PCIE INTERFACE

Gbit ETHERNET

30

IEEE-1394

23

8039/8056 /8071/8075

USB-4USB-5

30 30 30 30 30

HDR HDR HDR HDR

PCIE x1 SLOT1,2

USB-1USB-2USB-3

USB-7USB-8USB-9

31

USB-0 REARREARREARREARREARREAR

USB-6

PCIE x16

3125

30303030

B B

PCI BUS

ACPI CONTROLLER

UPi

CPU CORE POWER NB CORE POWER Intersil ISL6323 Intersil ISL6612A

PCI SLOT

6

30

27

CPU VLDT Power CPU VDDR Power CPU VDDA Power DUAL POWER

A A

NB & SB POWER

27

DDR3 DRAM POWER RS780 CORE POWER

ATX CON

5

28

FLOPPY

KBD MOUSE

26

34

4

3

SERIAL PORT

24 26

MICRO-START INT'L CO.,LTD.

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SB700/710 GPIO Config

GPIO Name Type Function description Pin CLK_REQ0#/SATA_IS3#/GPIO0

SMARTVOLT/SATA_IS2#/GPIO4

D D

C C

B B

CLK_REQ3#/SATA_IS1#/GPIO6 DDC1_SDA/GPIO8 DDC1_SCL/GPIO9 SATA_IS0#/GPIO10 SPI_DO/GPIO11 BMREQ#/REQ5#/GPIO68 LAN_RST#/GPIO13 ROM_RST#/GPIO14

SPI_HOLD#/GPIO31 SPI_HOLD_L SPI_CS#/GPIO32 SPI_CS# CLK_REQ1#/GPIO39 Not connected (internal pull-down). CLK_REQ2#/GPIO40 PCICLK5/GPIO41 Terminated with a strapping resistor AZ_SDIN0/GPIO42 SDATA_IN_R AZ_SDIN1/GPIO43 Not connected (internal pull-down) AZ_SDIN2/GPIO44 AZ_SDIN3/GPIO46

GPIO[49:48]/ FANOUT[2:1]] GPIO[52:50]/ FANIN[2:0] GPIO[60:53]/ VIN[7:0] GPIO[63:61]/ TEMPIN[2:0] GPIO64/ TALERT#/ TEMPIN3 GPIO65/ BMREQ#/ REQ5# GPIO66/ LLB# GPIO67/ SATA_ACT# GPIO68/ LDRQ1#/ GNT5# GPIO[71:70]/ REQ[4:3]# GPIO[73:72]/ GNT[4:3]# GPOC0#/ SCL0 GPOC1#/ SDA0 GPOC2#/ SCL1 GPOC3#/ SDA1 SDATA1 USB_OC[5:0]#/GPM[5:0]# SYS_RESET#/GPM7# AZ_DOCK_RST#/GPM8# SLP_S2/GPM9#

NOTE1

Configured for one of these options: "10-k? 5% pull-up resistor to +3.3V_S0. "10-k? 5% pull-down resistor. "Configured GPIO to output mode. "Configured for internal pull-up or pull-down resistor.

3.3V Not connected(internal pull-down) SPKRSPKR/GPIO2 Not connected (internal PU to +3.3V_S0)FANOUT0/GPIO3 CPU_PRESENT#:CPU present detect R377 10KR to GNDSHUTDOWN#/GPIO5

Note1 Note1 Note1

Note1 SPI_DATAOUT SPI_DATAIN Reserve TP Not connected (defaults to output driven low) Not connectedGPIO[30:15]/IDE_D[15:0]

Not connected (internal pull-down)

Not connected (internal pull-down) Not connected (internal pull-down) SPI_CLKSPI_CLK/GPIO47 Not connected (internal pull-up to +3.3V_S0)

Note1 Note1 Note1

TALERT#

Note1 LC_SENSE SATA_LED#

Reserve TP54 Not connected (internal pull-up to +3.3V_S0) Not connected (defaults to output HIGH). SCLK SDATA SCLK1

OC#[6::1] FP_RST# Not connected (internal pull-up to +3.3V_S5). GFX16_PCIERST#

SIO IT8720 GPIO Config

GPIO Name Type Function description Pin

VDIMM_STR_EN / PCIRST3#/GP10

SMARTVOLT/SATA_IS2#/GPIO4

CLK_REQ3#/SATA_IS1#/GPIO6 DDC1_SDA/GPIO8 DDC1_SCL/GPIO9 SATA_IS0#/GPIO10 SPI_DO/GPIO11 BMREQ#/REQ5#/GPIO68 LAN_RST#/GPIO13 ROM_RST#/GPIO14

SPI_HOLD#/GPIO31 SPI_HOLD_L SPI_CS#/GPIO32 SPI_CS# CLK_REQ1#/GPIO39 Not connected (internal pull-down). CLK_REQ2#/GPIO40 PCICLK5/GPIO41 Terminated with a strapping resistor AZ_SDIN0/GPIO42 SDATA_IN_R AZ_SDIN1/GPIO43 Not connected (internal pull-down) AZ_SDIN2/GPIO44 AZ_SDIN3/GPIO46

GPIO[49:48]/ FANOUT[2:1]] GPIO[52:50]/ FANIN[2:0] GPIO[60:53]/ VIN[7:0] GPIO[63:61]/ TEMPIN[2:0] GPIO64/ TALERT#/ TEMPIN3 GPIO65/ BMREQ#/ REQ5# GPIO66/ LLB# GPIO67/ SATA_ACT# GPIO68/ LDRQ1#/ GNT5# GPIO[71:70]/ REQ[4:3]# GPIO[73:72]/ GNT[4:3]# GPOC0#/ SCL0 GPOC1#/ SDA0 GPOC2#/ SCL1 GPOC3#/ SDA1 SDATA1 USB_OC[5:0]#/GPM[5:0]# SYS_RESET#/GPM7# AZ_DOCK_RST#/GPM8# SLP_S2/GPM9#

3.3V Not connected(internal pull-down) SPKRSPKR/GPIO2 Not connected (internal PU to +3.3V_S0)FANOUT0/GPIO3 CPU_PRESENT#:CPU present detect R377 10KR to GNDSHUTDOWN#/GPIO5

Note1 Note1 Note1

Note1 SPI_DATAOUT SPI_DATAIN Reserve TP Not connected (defaults to output driven low) Not connectedGPIO[30:15]/IDE_D[15:0]

Not connected (internal pull-down)

Not connected (internal pull-down) Not connected (internal pull-down) SPI_CLKSPI_CLK/GPIO47 Not connected (internal pull-up to +3.3V_S0)

Note1 Note1 Note1

TALERT#

Note1 LC_SENSE SATA_LED#

Reserve TP54 Not connected (internal pull-up to +3.3V_S0) Not connected (defaults to output HIGH). SCLK SDATA SCLK1

OC#[6::1] FP_RST# Not connected (internal pull-up to +3.3V_S5). GFX16_PCIERST#

A A

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GPIO Configuration

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DIMM3 DIMM4

D D

DIMM1 DIMM2

2 PAIR MEM CLK

AM3 CPU AM3SOCKET

C C

B B

2 PAIR MEM CLK

1 PAIR CPU CLK

200MHZ

HT REFCLK

100MHz DIFF(RX780/RS780)

EXTERNAL CLK GEN.

Y1

NB-OSCIN

14.318MHZ

NB ALINK PCIE CLK

100MHZ

SB ALINK PCIE CLK

100MHZ

NB GFX PCIE CLK

100MHZ

PCIE GFX CLK

100MHZ

PCIE GPP CLK

100MHZ

PCIE GPP CLK

100MHZ

PCIE GPP CLK

100MHZ

PCIE GPP CLK

100MHZ

USB CLK

48MHZ

SIO CLK

48MHZ

AMD NB RS780/RS740

PCIE GFX SLOT 1 - 16 LANES

PCIE GPP SLOT 1 - 1 LANE

PCIE GPP SLOT 2 - 1 LANES

PCIE GBE

PCIE IEEE1394

25MHZ OSC INPUT

24.576MHZ OSC INPUT

25MHz LAN

Y2

Y4

24.576MHz 1394

CPU_HT_CLK

NB_HT_CLK

25M_48M_66M_OSC

AMD SB SB700

NB_DISP_CLK

GPP_CLK3

PCIE_RCLK/ NB_LNK_CLK

SLT_GFX_CLK

GPP_CLK0

GPP_CLK1

GPP_CLK2

USB_CLK

Y3

PCI CLK0

33MHZ

PCI CLK1

33MHZ

PCI CLK2

33MHZ

PCI CLK3

33MHZ

PCI CLK4

33MHZ

PCI CLK5

33MHZ

LPC_CLK0

33MHZ

LPC CLK1

33MHZ

SB_BITCLK

48MHZ

Y5

32.768KHz

PCI SLOT 0 33MHz

SUPER IO IT8720

TPM 33MHz

HD AUDIO ALC 662/888

Y6

14.318MHz

25MHz SATA

14.31818MHz

A A

5

External clock mode

Internal clock mode

4

MICRO-START INT'L CO.,LTD.

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Power Deliver Chart

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2.5V Shunt Regulator

VRM SW REGUALTOR

D D

ATX P/S WITH 1A STBY CURRENT

5V

5VSB

+/-5%

3.3V +/-5%

12V +/-5%

-12V +/-5%

CPU PW 12V +/-5%

5VDIMM Linear REGULATOR

1.8V VDD SW REGULATOR

1.8V VCC Linear REGULATOR

VDDA25 (S0, S1)

VCCP (S0, S1) / VCC_NB (S0, S1)

0.9V VTT_DDR REGULATOR

1.1V VCC Linear REGULATOR

1.2V VCC Linear REGULATOR

VCC_DDR (S0, S1, S3) VTT_DDR (S0, S1, S3)

DDRII DIMMX4

VDD MEM

12A

VTT_DDR

2A

NB_VCC1P1 (S0, S1)

VCC_1V2 (S0, S1)

+1.8V_S0 (S0, S1)

C C

AMD AM2r2 CPU

VDDA 2.5V 0.2A VDDCORE

0.8-1.55V

DDR2 MEM I/F VDD MEM 1.8V VTT MEM 0.9V

VLDT 1.2V

NB RS780

VDDHT/RX 1.1V VDDHTTX 1.2V VDDPCIE 1.1V NB CORE VDDC

1.1V VDDA18PCIE 1.8V

PLLs 1.8V VDD18/VDD18_MEM

1.8V VDD_MEM 1.8V/1.5V

AVDD 3.3V

110A

10A 2A

0.5A

1.2A

0.5A 2A 7A

0.9A

0.1A

0.01A

0.5A

0.135A

SB700

VCC3_SB Linear REGULATOR

VCC3_SB (S0, S1, S3, S5)

1.2V_SB Linear REGULATOR

+1.2VSB (S0, S1) VCC3_SB (S0, S1, S3, S5)

VCC3 (S0, S1)

+5VA Linear

B B

5VDUAL Linear REGULATOR

REGULATOR

+5VA (S0, S1)

VCC3_SB (S0, S1, S3, S5)

X4 PCI-E

ATA I/O

ATA PLL

PCI-E PVDD

SB CORE

CLOCK

1.2V S5 PW

3.3V S5 PW

USB CORE I/O

3.3V I/O

AUDIO CODEC

3.3V CORE

5V ANALOG

+3.3VDUAL (S3)

+3.3V (S0, S1)

+5V (S0, S1)

0.8A

0.5A

0.01A 80mA

0.6A

0.22A

0.01A

0.2A

0.45A

0.1A

SUPER I/O

0.01A

0.1A

5.0A

7.6A

0.5A

0.1A

X1 PCIE per

3.3V 12V

3.3Vaux

PCI Slot (per slot)

A A

5

5V

3.3V 12V

3.3VDual

-12V

0.375A

3.0A

0.5A

0.1A

4

X16 PCIE per

3.3V 12V

3.3VDual

3.0A

5.5A

0.1A

USB X4 FR

VDD 5VDual

2.0A

USB X6 RL 2XPS/2

VDD 5VDual

3.0A

3

5VDual

0.5A

ENTHENET

3.3V (S3)

3.3V (S0, S1)

0.1A

0.5A

IEEE-1394 x1

3.3V (S0, S1)

12V (S0, S1) 1.1A

0.1A

MICRO-START INT'L CO.,LTD.

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Power Deliver Chart

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Intersil 6323 3 Phase

+12VIN

Make sure +12vin connect plug in

R38

B

R63

R63 10KR0402

10KR0402

X_C680P50X0402

R59

C8

R4

C24

X_C0.1U16Y0402

R38 10KR0402

10KR0402

CE

1KR0402

Q97

Q97 N-MMBT3904

N-MMBT3904

R206 X_0R0402R206 X_0R0402

C42

C40

C40 X_C0.1U16Y0402

X_C0.1U16Y0402

C38

C38 X_C0.1U16Y0402

X_C0.1U16Y0402

1.2KR1%0402

1.2KR1%0402 R34

R34

R17

1.3KR1%0402

C30

C587 C0.1U10X0402C587 C0.1U10X0402 R37 56KR1%0402R37 56KR1%0402

R19 59KR1%0402R19 59KR1%0402

R28

X_10KR0402

R36

0.85V Threshold

VRM_PWROK

TP8TP8 TP9TP9

TP10TP10

R69

1.2KR1%0402

1.2KR1%0402 C44 C10P50N0402C44 C10P50N0402

ISEN_NB_A

R53 0R0402R53 0R0402 R54 X_0R0402R54 X_0R0402

C0.01U16X0402

1 2

C7 C33P50N0402C7 C33P50N0402

C19 C0.01U16X0402C19 C0.01U16X0402

COREFB+ COREFB-

R16

4.99KR1%0402

VRM_SET

VCC5

120KR1%0402

C20 C0.1U16Y0402C20 C0.1U16Y0402

VR_VID5 VR_VID4

VR_FIXEN

C0.01U16X0402

1 2

C48

C23

12

C0.1U16Y0402

C22

OFS

R47

X_100KR0402

R45

R39

2.2R0805

7X7 QFN

U1

24

EN

37

VDDPWRGD

34

PWROK

9

VID5

8

VID4

7

VID3/SVC

6

VID2/SVD

5

VID1/SEL

4

VID0/VFIXEN

48

COMP_NB

1

FB_NB

2

VSEN_NB

3

RGND_NB

18

COMP

17

FB

15

RCOMP

13

VSEN

12

RGND

19

APA

16

RESET

14

OFS

11

FS

BOTTOM PAD CONNECT TO GND Through 8 VIAs

VCC5

C32

C32 C4.7U10Y0805

C4.7U10Y0805

10

PVCC1_2

VCC

BOOT1

UGATE1 PHASE1 LGATE1

ISEN1+

ISEN1-

BOOT2

UGATE2 PHASE2 LGATE2

ISEN2+

ISEN2-

PWM3

ISEN3+

ISEN3-

PWM4

ISEN4+

ISEN4-

PVCC_NB

BOOT_NB

UGATE_NB PHASE_NB LGATE_NB

ISEN_NB

GND

49

ISL6323CRZ_QFN48-RH

+12VIN

R51

2.2R0805

C35

C35 C1U16X5

C1U16X5

29

R52 2.2R1%0805R52 2.2R1%0805

31

U_G1

32

PHASE1

33

L_G1

30

20

ISEN1-

21

PHASE11

R46 2.2R1%0805R46 2.2R1%0805

27

U_G2

26

PHASE2

25

L_G2

28

ISEN2+

22

ISEN2-

23

PHASE22

PWM3

35

ISEN3+

44

ISEN3-

43

PHASE33

36

Disable PWM4 Use 3phase

46 45

VCC5

R70 2.2R1%0805R70 2.2R1%0805

42

C52 C1U25X0805C52 C1U25X0805

R68

40

2.2R1%0805

UGATE_NB

39

PHASE_NB

38

LGATE_NB

41

47

PHASE_NB_A ISEN_NB_A

R62

5.6KR1%0402

LDT_PWRGD7,17

C41 C0.1U25XC41 C0.1U25X

R33 200R1%0402R33 200R1%0402 R32

R32

4.32KR1%0402

4.32KR1%0402 C27 C0.1U25XC27 C0.1U25X

R31 150R1%0402R31 150R1%0402 R30

R30

4.32KR1%0402

R65 0R0402R65 0R0402 R64

R64

4.32KR1%0402

C51 C0.1U25XC51 C0.1U25X

R75 X_6.2KR1%0402R75 X_6.2KR1%0402

C53

C53 C0.1U16Y0402

C0.1U16Y0402

C5

C5 C0.1U16Y0402

C0.1U16Y0402

C3

C0.1U16Y0402

C54

C0.1U16Y0402

+12VIN

ISEN1ISEN1+

ISEN2

ISEN3

C6

C4

C55

C0.1U16Y0402C6C0.1U16Y0402

C0.1U16Y0402C4C0.1U16Y0402

C0.1U16Y0402

VCC5_SB

R637

R637 10KR0402

10KR0402

VCORE_EN#

VCORE_EN#26

D D

R636 10KR0402R636 10KR0402

VCC5

VRM_GD26

NB_PWRGD15,26

VID3_SVC7 VID2_SVD7 VID1_SEL7

CPU_VDDNB

R58

100R0402

V_NB7

X_C0.1U16Y0402

C C

V_GND7

R50

100R0402

COREFB+7

100R0402R5100R0402

COREFB-7

100R0402

R5

R42

C39

VCCP

R57

X_470R1%0402

360R1%0402

X_470R1%0402

X_470R1%0402 R18

R18

X_C1000P50X0402

560R1%0402-RH

C26

C26 X_C0.1U16Y0402

X_C0.1U16Y0402

VCC5

B B

R584

4.7KR0402

B

CE

Q100

Q100 N-MMBT3904

N-MMBT3904

VCC3VCC_DDR

+12VIN

R191

2.2R0805

C271

C1U25X0805

PWM3

R580

R580 10KR0402

10KR0402

VRM_PWROKLDT_PWRGD

U11

6

VCC

7

PVCC

4

GND

3

PWM

ISL6612ACBZT_SOIC8-RH

UGATE

BOOT

PHASE

LGATE

U_G1

PHASE1

L_G1

U_G2

PHASE2

L_G2

1 2

R186

2.2R1%0805

8

5

R137 1R0805R137 1R0805

R151 1R0805R151 1R0805

U_G3

PHASE3

L_G3

R136

10KR0402

N-NTD4806NT4G_DPAK3-RH

R152

10KR0402

N-NTD4806NT4G_DPAK3-RH

R176 1R0805R176 1R0805 C260

C260 C0.1U25X

C0.1U25X

N-NTD4806NT4G_DPAK3-RH

Q16

Q21

R175

R175 10KR0402

10KR0402

Q28

G

VIN

C101

C101 C1U16X5

C1U16X5

D

S

Q14

Q14 N-NTD4809NT4G_DPAK3-RH

N-NTD4809NT4G_DPAK3-RH

Q17

N-NTD4806NT4G_DPAK3-RH

Q17

N-NTD4806NT4G_DPAK3-RH

D

G

S

VIN

C140

C140 C1U16X5

C1U16X5

D

S

Q20

Q20 N-NTD4809NT4G_DPAK3-RH

N-NTD4809NT4G_DPAK3-RH

Q22

N-NTD4806NT4G_DPAK3-RH

Q22

N-NTD4806NT4G_DPAK3-RH

D

G

S

VIN

C211

C211 C1U16X5

C1U16X5

D

S

Q23

Q23 N-NTD4809NT4G_DPAK3-RH

N-NTD4809NT4G_DPAK3-RH

Q27

N-NTD4806NT4G_DPAK3-RH

Q27

N-NTD4806NT4G_DPAK3-RH

D

G

S

C96

C96 C10u16Y1206

C10u16Y1206

CH-0.25u40A0.65m-RH

R138

2.2R1%0805

C133

C133 C1000P50X0402

C1000P50X0402

C149

C149 C10u16Y1206

C10u16Y1206

R153

2.2R1%0805

C207

C207 C1000P50X0402

C1000P50X0402

C223

C223 C10u16Y1206

C10u16Y1206

R180

2.2R1%0805

C264

C264 C1000P50X0402

C1000P50X0402

CHOKE2

1 2

12

CP41CP41

PHASE11 ISEN1

CH-0.25u40A0.65m-RH

CH-0.25u40A0.65m-RH CHOKE4

CHOKE4

1 2

12

CP43CP43

PHASE22 ISEN2

CH-0.25u40A0.65m-RH

CH-0.25u40A0.65m-RH CHOKE6

CHOKE6

1 2

12

CP45CP45

PHASE33 ISEN3

VCCP

12

CP40CP40

VCCP

EC29

+

1 2

CD820u2.5SO-RH

EC33

+

1 2

CD820u2.5SO-RH

EC34

+

1 2

CD820u2.5SO-RH

VCCP

12

CP42CP42

CD820u2.5SO-RH

EC36

+

1 2

CD820u2.5SO-RH

EC41

+

1 2

CD820u2.5SO-RH

EC42

+

1 2

CD820u2.5SO-RH

EC43

+

1 2

CD820u2.5SO-RH

EC45

+

1 2

CD820u2.5SO-RH

VCCP

12

CP44CP44

Modify 0902

TP125TP125

TP126TP126

VIN

C56

C59

D

G

S

C1U16X5

Q9

C59 C10u16Y1206

C10u16Y1206

CHOKE1

CH-0.5u40A0.81m-RH

12

CPU_VDDNB

R101

2.2R1%0805

C60

C1000P50X0402

N-NTD4806NT4G_DPAK3-RH

VCC5 VIN

12

CP39CP39

CP38CP38

PHASE_NB_A ISEN_NB_A

Title

Intersil 6323 3 Phase

Size Document Number Rev

C

VL390 0A

Date: Sheet

CPU_VDDNB

EC51

+

1 2

CD820u2.5SO-RH

EC53

+

1 2

CD820u2.5SO-RH

MICRO-START INT'L CO.,LTD.

637Tuesday, September 09, 2008

of

1

of

Q6

D

G

S

Q7

D

G

S

2

5

JPW1

GND GND

12V

CHOKE7

CH-1.1u27A2.5m-RH

5

1

2

CPU_CORE_TYPE7

R340 X_27R0402R340 X_27R0402

VIN

EC17

CD1000U16EL20-2+EC17

CD1000U16EL20-2

+

12

+

12

CD1000U16EL20-2

EC28

CD1000U16EL20-2+EC28

CD1000U16EL20-2

EC10

CD1000U16EL20-2+EC10

C270

C0.1U16Y0402

C270

C0.1U16Y0402

EC6

X_CD1000U16EL20-2+EC6

X_CD1000U16EL20-2

+

12

4

+12VIN

3

4

C283

PWR-2X2M_natural-RH

X_C0.01u25X0402

+12VIN

A A

PWR-2X2M_natural-RH

1 2

C284

X_C0.01u25X0402

C284

X_C0.01u25X0402

VCC_DDR

R66 X_300R0402R66 X_300R0402

VID1_SEL

LOW FOR SVID

R78

R78 300R0402

300R0402

3

UGATE_NB

PHASE_NB

LGATE_NB

N-NTD4809NT4G_DPAK3-RH

R120 1R0805R120 1R0805

R118

10KR0402

N-NTD4806NT4G_DPAK3-RH

R77 1R0805R77 1R0805

R94 1R0805R94 1R0805

5

4

3

2

1

CPU1A

L0_CLKIN_H(1) L0_CLKIN_L(1) L0_CLKIN_H(0) L0_CLKIN_L(0)

L0_CTLIN_H(1) L0_CTLIN_L(1) L0_CTLIN_H(0) L0_CTLIN_L(0)

L0_CADIN_H(15) L0_CADIN_L(15) L0_CADIN_H(14) L0_CADIN_L(14) L0_CADIN_H(13) L0_CADIN_L(13) L0_CADIN_H(12) L0_CADIN_L(12) L0_CADIN_H(11) L0_CADIN_L(11) L0_CADIN_H(10) L0_CADIN_L(10) L0_CADIN_H(9) L0_CADIN_L(9) L0_CADIN_H(8) L0_CADIN_L(8)

L0_CADIN_H(7) L0_CADIN_L(7) L0_CADIN_H(6) L0_CADIN_L(6) L0_CADIN_H(5) L0_CADIN_L(5) L0_CADIN_H(4) L0_CADIN_L(4) L0_CADIN_H(3) L0_CADIN_L(3) L0_CADIN_H(2) L0_CADIN_L(2) L0_CADIN_H(1) L0_CADIN_L(1) L0_CADIN_H(0) L0_CADIN_L(0)

HT_CADIN_H[15..0] HT_CADIN_L[15..0] HT_CADOUT_H[15..0] HT_CADOUT_L[15..0]

HYPERTRANSPORT

L0_CLKOUT_H(1) L0_CLKOUT_L(1) L0_CLKOUT_H(0) L0_CLKOUT_L(0)

L0_CTLOUT_H(1) L0_CTLOUT_L(1) L0_CTLOUT_H(0) L0_CTLOUT_L(0)

L0_CADOUT_H(15)

L0_CADOUT_L(15)

L0_CADOUT_H(14)

L0_CADOUT_L(14)

L0_CADOUT_H(13)

L0_CADOUT_L(13)

L0_CADOUT_H(12)

L0_CADOUT_L(12)

L0_CADOUT_H(11)

L0_CADOUT_L(11)

L0_CADOUT_H(10)

L0_CADOUT_L(10)

L0_CADOUT_H(9)

L0_CADOUT_L(9)

L0_CADOUT_H(8)

L0_CADOUT_L(8)

L0_CADOUT_H(7)

L0_CADOUT_L(7)

L0_CADOUT_H(6)

L0_CADOUT_L(6)

L0_CADOUT_H(5)

L0_CADOUT_L(5)

L0_CADOUT_H(4)

L0_CADOUT_L(4)

L0_CADOUT_H(3)

L0_CADOUT_L(3)

L0_CADOUT_H(2)

L0_CADOUT_L(2)

L0_CADOUT_H(1)

L0_CADOUT_L(1)

L0_CADOUT_H(0)

L0_CADOUT_L(0)

VCC_1V2

AD5 AD4 AD1 AC1

Y6 W6 W2 W3

Y5 Y4 AB6 AA6 AB5 AB4 AD6 AC6 AF6 AE6 AF5 AF4 AH6 AG6 AH5 AH4

Y1 W1 AA2 AA3 AB1 AA1 AC2 AC3 AE2 AE3 AF1 AE1 AG2 AG3 AH1 AG1

RS740

R442 X_51R1%0402R442 X_51R1%0402

RS740

R599 X_51R1%0402R599 X_51R1%0402

HT_CADOUT_H15 HT_CADOUT_L15 HT_CADOUT_H14 HT_CADOUT_L14 HT_CADOUT_H13 HT_CADOUT_L13 HT_CADOUT_H12 HT_CADOUT_L12 HT_CADOUT_H11 HT_CADOUT_L11 HT_CADOUT_H10 HT_CADOUT_L10 HT_CADOUT_H9 HT_CADOUT_L9 HT_CADOUT_H8 HT_CADOUT_L8

HT_CADOUT_H7 HT_CADOUT_L7 HT_CADOUT_H6 HT_CADOUT_L6 HT_CADOUT_H5 HT_CADOUT_L5 HT_CADOUT_H4 HT_CADOUT_L4 HT_CADOUT_H3 HT_CADOUT_L3 HT_CADOUT_H2 HT_CADOUT_L2 HT_CADOUT_H1 HT_CADOUT_L1 HT_CADOUT_H0 HT_CADOUT_L0

HT_CLKOUT_H1 13 HT_CLKOUT_L1 13 HT_CLKOUT_H0 13 HT_CLKOUT_L0 13

HT_CTLOUT_H1 13 HT_CTLOUT_L1 13 HT_CTLOUT_H0 13 HT_CTLOUT_L0 13

HT_CTLIN_H1 HT_CTLIN_L1

CPU_CLK12

CPU_CLK#12

Note: CRB Reserved

CPU_DBREQ_L CPU_TCK CPU_TMS CPU_TDI CPU_TRST_L

LDT_STOP# LDT_RST# LDT_PWRGD

R294 X_1KR0402R294 X_1KR0402 R281 X_1KR0402R281 X_1KR0402 R249 X_1KR0402R249 X_1KR0402 R247 X_1KR0402R247 X_1KR0402 R240 X_1KR0402R240 X_1KR0402

C801 X_C180p50N0402C801 X_C180p50N0402 C802 X_C180p50N0402C802 X_C180p50N0402 C803 X_C180p50N0402C803 X_C180p50N0402

C84

C84 C3900P50X

C3900P50X

C91

C91 C3900P50X

C3900P50X

VCC_DDR

R121

R121 169R1%0402

169R1%0402

VCC_DDR

R162

39.2R1%0402

R160

39.2R1%0402

LDT_PWRGD6,17 LDT_STOP#15,17

LDT_RST#15,17

CPU_M_VREF

VDDA25

C77

C69

C0.22U16X

C1U10Y

C4.7U10Y0805

LDT_PWRGD LDT_STOP# VID4 LDT_RST#

COREFB+6 COREFB-6

CPU_VDDR_SENSE

TP1TP1

CPU_STRAP_HI_E11 CPU_STRAP_LO_F11

CPU_TEST25_H CPU_TEST25_L

R534 X_300R0402R534 X_300R0402 R564 X_300R0402R564 X_300R0402

TP19TP19 TP20TP20 TP23TP23 TP18TP18 TP25TP25

C89

C3300P50X0402

CPUCLKIN CPUCLKIN#

CPU_PRESENT_L CPU_SIC

CPU_SID CPU_ALERT#

R146 0R0402R146 0R0402

CPU_TDI CPU_TRST_L CPU_TCK CPU_TMS

CPU_DBREQ_L COREFB+

COREFB-

C74

CPU1D

C10

VDDA1

D10

VDDA2

A8

CLKIN_H

B8

CLKIN_L

C9

PWROK

D8

LDTSTOP_L

C7

RESET_L

AL3

CPU_PRESENT_L

AL6

SIC

AK6

SID

AL4

ALERT_L

AK4

SA0

AL10

TDI

AJ10

TRST_L

AH10

TCK

AL9

TMS

A5

DBREQ_L

G2

VDD_FB_H

G1

VDD_FB_L

E12

VTT_SENSE

F12

M_VREF

AH11

M_ZN

AJ11

M_ZP

A10

TEST25_H

B10

TEST25_L

F10

TEST19

E9

TEST18

AJ7

TEST13

F6

TEST9

D6

TEST17

E7

TEST16

F8

TEST15

C5

TEST14

AH9

TEST12

E5

TEST7

AJ5

TEST6

AH7

TEST3

AJ6

TEST2

VDDA25VDDA_25

L5

21

47n300mA_0805-RH-2

MISC

KEY/VSS1 KEY/VSS2

PLATFORM_TYPE

CORE_TYPE

VID(5)

VID(4) SVC/VID(3) SVD/VID(2)

PVIEN/VID(1)

VID(0)

THERMDC THERMDA

THERMTRIP_L

PROCHOT_L

TDO

DBRDY

VDDIO_FB_H VDDIO_FB_L

VDDNB_FB_H

VDDNB_FB_L

PSI_L

HTREF1 HTREF0

TEST29_H TEST29_L

TEST24 TEST23 TEST22 TEST21 TEST20

TEST28_H TEST28_L

TEST27 TEST26 TEST10

TEST8

CPU_CORE_TYPE VID3_SVC

VID2_SVD

Remove H22,AE9

H22 AE9

CPU_PF_TYPE

F2

CPU_CORE_TYPE

G5

VID5

D2 D1

VID3_SVC

C1

VID2_SVD

E3

VID1_SEL

E2

VRFIXEN

E1 AG9

AG8

CPU_THRIP_L#

AK7

PROCHOT_L

AL7

CPU_TDO

AK10

CPU_DBRDY

B6 AK11

AL11 G4 G3

CPU_PSI_L

F1

HTREF1

V8 V7

C11 D11

AK8 AH8 AJ9 AL8 AJ8

J10 H9 AK9 AK5 G7 D4

R168 44.2R1%R168 44.2R1%

HTREF2

R171 44.2R1%R171 44.2R1%

R123 X_80.6R1%0402R123 X_80.6R1%0402

Keep trace < 1" from CPU.

TP28TP28 TP24TP24

R531 300R0402R531 300R0402 TP26TP26

R165 X_300R0402R165 X_300R0402

TP5TP5 TP6TP6

TP7TP7

R102 0R0402R102 0R0402

R163 100R0402R163 100R0402

TP4TP4

TP3TP3

TP27TP27

R80 1KR0402R80 1KR0402 R72 1KR0402R72 1KR0402

R71 1KR0402R71 1KR0402

change pin F2 from PLATFORM_TYPE to RSVD

TP2TP2

CPU_CORE_TYPE 6

VID3_SVC 6 VID2_SVD 6 VID1_SEL 6

THERMDC_CPU 25,32 THERMDA_CPU 25,32

V_NB 6 V_GND 6

VCC_1V2

R567 300R0402R567 300R0402

VCC_DDR

Note: Change the PU resister to 1KR

CPU_PROCHOT# 17

DDR_FB 27

HT_CADIN_H[15..0]13

HT_CADIN_L[15..0]13 HT_CADOUT_H[15..0]13 HT_CADOUT_L[15..0]13

D D

HT_CLKIN_H113 HT_CLKIN_L113 HT_CLKIN_H013 HT_CLKIN_L013

HT_CTLIN_H113 HT_CTLIN_L113 HT_CTLIN_H013 HT_CTLIN_L013

HT_CADIN_H15 HT_CADIN_L15 HT_CADIN_H14 HT_CADIN_L14 HT_CADIN_H13 HT_CADIN_L13 HT_CADIN_H12 HT_CADIN_L12 HT_CADIN_H11 HT_CADIN_L11 HT_CADIN_H10 HT_CADIN_L10 HT_CADIN_H9 HT_CADIN_L9 HT_CADIN_H8

C C

B B

HT_CADIN_L8 HT_CADIN_H7

HT_CADIN_L7 HT_CADIN_H6 HT_CADIN_L6 HT_CADIN_H5 HT_CADIN_L5 HT_CADIN_H4 HT_CADIN_L4 HT_CADIN_H3 HT_CADIN_L3 HT_CADIN_H2 HT_CADIN_L2 HT_CADIN_H1 HT_CADIN_L1 HT_CADIN_H0 HT_CADIN_L0

N6 P6 N3 N2

V4 V5 U1 V1

U6 V6

T4 T5

R6

T6 P4 P5 M4 M5

L6 M6 K4 K5

J6 K6

U3 U2 R1

T1 R3 R2 N1 P1

L1 M1

L3

L2

J1 K1

J3

J2

AMD REQUEST

VCC_DDRVCC3

R21

R22

X_1KR0402

SW1 X_SW-TACT4PSSW1 X_SW-TACT4PS

1

3

2

4

CPU_DBREQ_L CPU_DBRDY CPU_TCK

A A

CPU_TMS CPU_TDI CPU_TRST_L CPU_TDO

5

VCC_DDR

X_100R0402

LDT_RST_L LDT_RST#

R8

J1

1 3 5 7

9 11 13 15 17 19 21 23

J1

KEY

X_H2X13[25]_black

R21 X_4.7KR0402

X_4.7KR0402

B

CE

Q1

Q1 X_N-MMBT3904_NL_SOT23

X_N-MMBT3904_NL_SOT23

2 4 6 8 10 12 14 16 18 20 22 24 26

LDT_RST_L

4

VCC3

R174

X_39.2KR1%0402

For SIC/SID

CPU_ALERT# CPU_SID

CPU_SIC CPU_PRESENT_L

CPU_TEST25_H CPU_TEST25_L

R184

R184 20KR1%0402

20KR1%0402

C255

C255 C0.1U16Y0402

C0.1U16Y0402

R177 1KR0402R177 1KR0402 R231 1KR0402R231 1KR0402

R167 1KR0402R167 1KR0402 R170 10KR0402R170 10KR0402

R111 510R0402R111 510R0402 R119 510R0402R119 510R0402

CPU_SIC CPU_SID

CPU_FETGATE

CPU_ALERT# CPU_PRESENT_L

VCC_DDR

3

Q102

S1 G1 S2 G2

LDT_STOP# LDT_RST# LDT_PWRGD PROCHOT_L

D1 D2

NN-2N7002DW-7-F_SOT363-6-RH

Q103

D1 D2

NN-2N7002DW-7-F_SOT363-6-RH

R106 300R0402R106 300R0402 R105 300R0402R105 300R0402 R107 300R0402R107 300R0402 R103 300R0402R103 300R0402

Modify 0902

R182 0R0402R182 0R0402 R178 0R0402R178 0R0402

R183 X_0R0402R183 X_0R0402

VCC_DDR

AMD_TSI_C 25 AMD_TSI_D 25

TALERT# 19 CPU_PRESENT# 18

HTREF1 HTREF2 LDT_RST#

CPU_THRIP_L#

C227 X_C1000P50X0402C227 X_C1000P50X0402 C228 X_C1000P50X0402C228 X_C1000P50X0402 C67 X_C1000P50X0402C67 X_C1000P50X0402

2

R169

300R0402

Q24

N-MMBT3904_NL_SOT23

VCC_DDR

B

R166

4.7KR0402

CE

CPU_THRIP# 18

Title

Size Document Number Rev

Custom

Date: Sheet

VCC_DDR

CPU_M_VREF

R110

R110 15R1%

15R1%

C86

C92

1

C92 C1000P50X0402

C1000P50X0402

CPU_CLK CPU_CLK#

LDT_PWRGD LDT_RST#

737Tuesday, September 09, 2008

R109

R109 15R1%

15R1%

C0.1U16Y0402

TP135TP135 TP136TP136

TP137TP137

TP138TP138

MICRO-START INT'L CO.,LTD.

CPU AM2 HT I/F,CTRL&DEBUG

VL390 0A

of

5

MEM_MA_DQS_L[7..0]10,11 MEM_MA_DQS_H[7..0]10,11

MEM_MA_DM[7..0]10,11

AG21 AG20

G19

AC25 AA24

AC28 AE20

AE19

G20 G21

W27

AD27 AA25

AC27

AB25 AB27 AA26

AA27

M25 M27

AC26

W24

AD15 AE15 AG18 AG19 AG24 AG25 AG27 AG28

G15

AF15 AF19 AJ25

AH29

H19 U27 U26

V27

N25 Y27

L27

N24 N26

P25 Y25 N27 R24 P27 R25 R26 R27 T25 U25 T27

D29 C29 C25 D25 E19 F19 F15

B29 E24 E18 H15

MEM_MA_CHECK[7..0]10,11

CPU1B

MA0_CLK_H(2) MA0_CLK_L(2) MA0_CLK_H(1) MA0_CLK_L(1) MA0_CLK_H(0) MA0_CLK_L(0)

MA0_CS_L(1) MA0_CS_L(0)

MA0_ODT(0) MA1_CLK_H(2)

MA1_CLK_L(2) MA1_CLK_H(1) MA1_CLK_L(1) MA1_CLK_H(0) MA1_CLK_L(0)

MA1_CS_L(1) MA1_CS_L(0)

MA1_ODT(0)

MA_CAS_L MA_WE_L MA_RAS_L

MA_BANK(2) MA_BANK(1) MA_BANK(0)

MA_CKE(1) MA_CKE(0)

MA_ADD(15) MA_ADD(14) MA_ADD(13) MA_ADD(12) MA_ADD(11) MA_ADD(10) MA_ADD(9) MA_ADD(8) MA_ADD(7) MA_ADD(6) MA_ADD(5) MA_ADD(4) MA_ADD(3) MA_ADD(2) MA_ADD(1) MA_ADD(0)

MA_DQS_H(7) MA_DQS_L(7) MA_DQS_H(6) MA_DQS_L(6) MA_DQS_H(5) MA_DQS_L(5) MA_DQS_H(4) MA_DQS_L(4) MA_DQS_H(3) MA_DQS_L(3) MA_DQS_H(2) MA_DQS_L(2) MA_DQS_H(1) MA_DQS_L(1) MA_DQS_H(0) MA_DQS_L(0)

MA_DM(7) MA_DM(6) MA_DM(5) MA_DM(4) MA_DM(3) MA_DM(2) MA_DM(1) MA_DM(0)

MEMORY INTERFACE A

D D

MEM_MA1_CLK_H111 MEM_MA1_CLK_L111 MEM_MB1_CLK_H111

MEM_MA0_CS_L110 MEM_MA0_CS_L010

MEM_MA0_ODT010

MEM_MA0_CLK_H010 MEM_MA0_CLK_L010

MEM_MA1_CS_L111 MEM_MA1_CS_L011

MEM_MA1_ODT011

C C

B B

MEM_MA_CAS_L10,11 MEM_MA_WE_L10,11 MEM_MA_RAS_L10,11

MEM_MA_BANK210,11 MEM_MA_BANK110,11 MEM_MA_BANK010,11

MEM_MA_CKE110,11 MEM_MA_CKE010,11

MEM_MA_ADD[15..0]10,11

Pin naming for memory pins indicate "DDR3"/"DDR2" connections.

MEM_MA1_CLK_H1 MEM_MA1_CLK_L1 MEM_MB1_CLK_H1

MEM_MA0_CS_L1 MEM_MA0_CS_L0

MEM_MA0_ODT0

MEM_MA0_CLK_H0 MEM_MA0_CLK_L0

MEM_MA1_CS_L1 MEM_MA1_CS_L0

MEM_MA1_ODT0

MEM_MA_CAS_L MEM_MA_WE_L MEM_MA_RAS_L

MEM_MA_BANK2 MEM_MA_BANK1 MEM_MA_BANK0

MEM_MA_CKE1 MEM_MA_CKE0

MEM_MA_ADD15 MEM_MA_ADD14 MEM_MA_ADD13 MEM_MA_ADD12 MEM_MA_ADD11 MEM_MA_ADD10 MEM_MA_ADD9 MEM_MA_ADD8 MEM_MA_ADD7 MEM_MA_ADD6 MEM_MA_ADD5 MEM_MA_ADD4 MEM_MA_ADD3 MEM_MA_ADD2 MEM_MA_ADD1 MEM_MA_ADD0

MEM_MA_DQS_H7 MEM_MA_DQS_L7 MEM_MA_DQS_H6 MEM_MA_DQS_L6 MEM_MA_DQS_H5 MEM_MA_DQS_L5 MEM_MA_DQS_H4 MEM_MA_DQS_L4 MEM_MA_DQS_H3 MEM_MA_DQS_L3 MEM_MA_DQS_H2 MEM_MA_DQS_L2 MEM_MA_DQS_H1 MEM_MA_DQS_L1 MEM_MA_DQS_H0 MEM_MA_DQS_L0

MEM_MA_DM7 MEM_MA_DM6 MEM_MA_DM5 MEM_MA_DM4 MEM_MA_DM3 MEM_MA_DM2 MEM_MA_DM1 MEM_MA_DM0

4

MA_DATA(63) MA_DATA(62) MA_DATA(61) MA_DATA(60) MA_DATA(59) MA_DATA(58) MA_DATA(57) MA_DATA(56) MA_DATA(55) MA_DATA(54) MA_DATA(53) MA_DATA(52) MA_DATA(51) MA_DATA(50) MA_DATA(49) MA_DATA(48) MA_DATA(47) MA_DATA(46) MA_DATA(45) MA_DATA(44) MA_DATA(43) MA_DATA(42) MA_DATA(41) MA_DATA(40) MA_DATA(39) MA_DATA(38) MA_DATA(37) MA_DATA(36) MA_DATA(35) MA_DATA(34) MA_DATA(33) MA_DATA(32) MA_DATA(31) MA_DATA(30) MA_DATA(29) MA_DATA(28) MA_DATA(27) MA_DATA(26) MA_DATA(25) MA_DATA(24) MA_DATA(23) MA_DATA(22) MA_DATA(21) MA_DATA(20) MA_DATA(19) MA_DATA(18) MA_DATA(17) MA_DATA(16) MA_DATA(15) MA_DATA(14) MA_DATA(13) MA_DATA(12) MA_DATA(11) MA_DATA(10)

MA_DATA(9) MA_DATA(8) MA_DATA(7) MA_DATA(6) MA_DATA(5) MA_DATA(4) MA_DATA(3) MA_DATA(2) MA_DATA(1) MA_DATA(0)

MA_DQS_H(8)

MA_DQS_L(8)

MA_DM(8)

MA_CHECK(7) MA_CHECK(6) MA_CHECK(5) MA_CHECK(4) MA_CHECK(3) MA_CHECK(2) MA_CHECK(1) MA_CHECK(0)

AE14 AG14 AG16 AD17 AD13 AE13 AG15 AE16 AG17 AE18 AD21 AG22 AE17 AF17 AF21 AE21 AF23 AE23 AJ26 AG26 AE22 AG23 AH25 AF25 AJ28 AJ29 AF29 AE26 AJ27 AH27 AG29 AF27 E29 E28 D27 C27 G26 F27 C28 E27 F25 E25 E23 D23 E26 C26 G23 F23 E22 E21 F17 G17 G22 F21 G18 E17 G16 E15 G13 H13 H17 E16 E14 G14

J28 J27

J25 K25

J26 G28 G27 L24 K27 H29 H27

MEM_MA_DATA63 MEM_MA_DATA62 MEM_MA_DATA61 MEM_MA_DATA60 MEM_MA_DATA59 MEM_MA_DATA58 MEM_MA_DATA57 MEM_MA_DATA56 MEM_MA_DATA55 MEM_MA_DATA54 MEM_MA_DATA53 MEM_MA_DATA52 MEM_MA_DATA51 MEM_MA_DATA50 MEM_MA_DATA49 MEM_MA_DATA48 MEM_MA_DATA47 MEM_MA_DATA46 MEM_MA_DATA45 MEM_MA_DATA44 MEM_MA_DATA43 MEM_MA_DATA42 MEM_MA_DATA41 MEM_MA_DATA40 MEM_MA_DATA39 MEM_MA_DATA38 MEM_MA_DATA37 MEM_MA_DATA36 MEM_MA_DATA35 MEM_MA_DATA34 MEM_MA_DATA33 MEM_MA_DATA32 MEM_MA_DATA31 MEM_MA_DATA30 MEM_MA_DATA29 MEM_MA_DATA28 MEM_MA_DATA27 MEM_MA_DATA26 MEM_MA_DATA25 MEM_MA_DATA24 MEM_MA_DATA23 MEM_MA_DATA22 MEM_MA_DATA21 MEM_MA_DATA20 MEM_MA_DATA19 MEM_MA_DATA18 MEM_MA_DATA17 MEM_MA_DATA16 MEM_MA_DATA15 MEM_MA_DATA14 MEM_MA_DATA13 MEM_MA_DATA12 MEM_MA_DATA11 MEM_MA_DATA10 MEM_MA_DATA9 MEM_MA_DATA8 MEM_MA_DATA7 MEM_MA_DATA6 MEM_MA_DATA5 MEM_MA_DATA4 MEM_MA_DATA3 MEM_MA_DATA2 MEM_MA_DATA1 MEM_MA_DATA0

MEM_MA_DQS_H8 MEM_MA_DQS_L8

MEM_MA_DM8 MEM_MA_CHECK7

MEM_MA_CHECK6 MEM_MA_CHECK5 MEM_MA_CHECK4 MEM_MA_CHECK3 MEM_MA_CHECK2 MEM_MA_CHECK1 MEM_MA_CHECK0

MEM_MA_DATA[63..0] 10,11

MEM_MA_DQS_H8 10,11 MEM_MA_DQS_L8 10,11

MEM_MA_DM8 10,11

3

AJ19

AK19

A18 A19

MEM_MB1_CLK_L111 MEM_MB0_CS_L110

MEM_MB0_CS_L010 MEM_MB0_ODT010

MEM_MB0_CLK_H010 MEM_MB0_CLK_L010

MEM_MB1_CS_L111 MEM_MB1_CS_L011

MEM_MB1_ODT011

MEM_MB_CAS_L10,11 MEM_MB_WE_L10,11 MEM_MB_RAS_L10,11

MEM_MB_BANK210,11 MEM_MB_BANK110,11 MEM_MB_BANK010,11

MEM_MB_CKE110,11 MEM_MB_CKE010,11

MEM_MB_ADD[15..0]10,11

MEM_MB1_CLK_L1 MEM_MB0_CS_L1

MEM_MB0_CS_L0 MEM_MB0_ODT0

MEM_MB0_CLK_H0 MEM_MB0_CLK_L0

MEM_MB1_CS_L1 MEM_MB1_CS_L0

MEM_MB1_ODT0

MEM_MB_CAS_L MEM_MB_WE_L MEM_MB_RAS_L

MEM_MB_BANK2 MEM_MB_BANK1 MEM_MB_BANK0

MEM_MB_CKE1 MEM_MB_CKE0

MEM_MB_ADD15 MEM_MB_ADD14 MEM_MB_ADD13 MEM_MB_ADD12 MEM_MB_ADD11 MEM_MB_ADD10 MEM_MB_ADD9 MEM_MB_ADD8 MEM_MB_ADD7 MEM_MB_ADD6 MEM_MB_ADD5 MEM_MB_ADD4 MEM_MB_ADD3 MEM_MB_ADD2 MEM_MB_ADD1 MEM_MB_ADD0

MEM_MB_DQS_H7 MEM_MB_DQS_L7 MEM_MB_DQS_H6 MEM_MB_DQS_L6 MEM_MB_DQS_H5 MEM_MB_DQS_L5 MEM_MB_DQS_H4 MEM_MB_DQS_L4 MEM_MB_DQS_H3 MEM_MB_DQS_L3 MEM_MB_DQS_H2 MEM_MB_DQS_L2 MEM_MB_DQS_H1 MEM_MB_DQS_L1 MEM_MB_DQS_H0 MEM_MB_DQS_L0

MEM_MB_DM7 MEM_MB_DM6 MEM_MB_DM5 MEM_MB_DM4 MEM_MB_DM3 MEM_MB_DM2 MEM_MB_DM1 MEM_MB_DM0

U31 U30

AE30 AC31

AD29 AL19

AL18

C19 D19 W29 W28

AE29 AB31

AD31

AC29 AC30 AB29

N31 AA31 AA28

M31

M29

N28

N29 AE31

N30

P29 AA29

P31

R29

R28

R31

R30

U29

U28 AA30

AK13

AJ13

AK17

AJ17 AK23 AL23 AL28 AL29

D31 C31 C24 C23 D17 C17 C14 C13

AJ14 AH17

AJ23 AK29

C30 A23 B17 B13

T31 T29

MEM_MB_DQS_L[7..0]10,11 MEM_MB_DQS_H[7..0]10,11

MEM_MB_DM[7..0]10,11

MEM_MB_CHECK[7..0]10,11

CPU1C

MB0_CLK_H(2) MB0_CLK_L(2) MB0_CLK_H(1) MB0_CLK_L(1) MB0_CLK_H(0) MB0_CLK_L(0)

MB0_CS_L(1) MB0_CS_L(0)

MB0_ODT(0) MB1_CLK_H(2)

MB1_CLK_L(2) MB1_CLK_H(1) MB1_CLK_L(1) MB1_CLK_H(0) MB1_CLK_L(0)

MB1_CS_L(1) MB1_CS_L(0)

MB1_ODT(0)

MB_CAS_L MB_WE_L MB_RAS_L

MB_BANK(2) MB_BANK(1) MB_BANK(0)

MB_CKE(1) MB_CKE(0)

MB_ADD(15) MB_ADD(14) MB_ADD(13) MB_ADD(12) MB_ADD(11) MB_ADD(10) MB_ADD(9) MB_ADD(8) MB_ADD(7) MB_ADD(6) MB_ADD(5) MB_ADD(4) MB_ADD(3) MB_ADD(2) MB_ADD(1) MB_ADD(0)

MB_DQS_H(7) MB_DQS_L(7) MB_DQS_H(6) MB_DQS_L(6) MB_DQS_H(5) MB_DQS_L(5) MB_DQS_H(4) MB_DQS_L(4) MB_DQS_H(3) MB_DQS_L(3) MB_DQS_H(2) MB_DQS_L(2) MB_DQS_H(1) MB_DQS_L(1) MB_DQS_H(0) MB_DQS_L(0)

MB_DM(7) MB_DM(6) MB_DM(5) MB_DM(4) MB_DM(3) MB_DM(2) MB_DM(1) MB_DM(0)

2

MEMORY INTERFACE B

MB_DATA(63) MB_DATA(62) MB_DATA(61) MB_DATA(60) MB_DATA(59) MB_DATA(58) MB_DATA(57) MB_DATA(56) MB_DATA(55) MB_DATA(54) MB_DATA(53) MB_DATA(52) MB_DATA(51) MB_DATA(50) MB_DATA(49) MB_DATA(48) MB_DATA(47) MB_DATA(46) MB_DATA(45) MB_DATA(44) MB_DATA(43) MB_DATA(42) MB_DATA(41) MB_DATA(40) MB_DATA(39) MB_DATA(38) MB_DATA(37) MB_DATA(36) MB_DATA(35) MB_DATA(34) MB_DATA(33) MB_DATA(32) MB_DATA(31) MB_DATA(30) MB_DATA(29) MB_DATA(28) MB_DATA(27) MB_DATA(26) MB_DATA(25) MB_DATA(24) MB_DATA(23) MB_DATA(22) MB_DATA(21) MB_DATA(20) MB_DATA(19) MB_DATA(18) MB_DATA(17) MB_DATA(16) MB_DATA(15) MB_DATA(14) MB_DATA(13) MB_DATA(12) MB_DATA(11) MB_DATA(10)

MB_DATA(9) MB_DATA(8) MB_DATA(7) MB_DATA(6) MB_DATA(5) MB_DATA(4) MB_DATA(3) MB_DATA(2) MB_DATA(1) MB_DATA(0)

MB_DQS_H(8)

MB_DQS_L(8)

MB_DM(8)

MB_CHECK(7) MB_CHECK(6) MB_CHECK(5) MB_CHECK(4) MB_CHECK(3) MB_CHECK(2) MB_CHECK(1) MB_CHECK(0)

AH13 AL13 AL15 AJ15 AF13 AG13 AL14 AK15 AL16 AL17 AK21 AL21 AH15 AJ16 AH19 AL20 AJ22 AL22 AL24 AK25 AJ21 AH21 AH23 AJ24 AL27 AK27 AH31 AG30 AL25 AL26 AJ30 AJ31 E31 E30 B27 A27 F29 F31 A29 A28 A25 A24 C22 D21 A26 B25 B23 A22 B21 A20 C16 D15 C21 A21 A17 A16 B15 A14 E13 F13 C15 A15 A13 D13

J31 J30

J29 K29

K31 G30 G29 L29 L28 H31 G31

MEM_MB_DATA63 MEM_MB_DATA62 MEM_MB_DATA61 MEM_MB_DATA60 MEM_MB_DATA59 MEM_MB_DATA58 MEM_MB_DATA57 MEM_MB_DATA56 MEM_MB_DATA55 MEM_MB_DATA54 MEM_MB_DATA53 MEM_MB_DATA52 MEM_MB_DATA51 MEM_MB_DATA50 MEM_MB_DATA49 MEM_MB_DATA48 MEM_MB_DATA47 MEM_MB_DATA46 MEM_MB_DATA45 MEM_MB_DATA44 MEM_MB_DATA43 MEM_MB_DATA42 MEM_MB_DATA41 MEM_MB_DATA40 MEM_MB_DATA39 MEM_MB_DATA38 MEM_MB_DATA37 MEM_MB_DATA36 MEM_MB_DATA35 MEM_MB_DATA34 MEM_MB_DATA33 MEM_MB_DATA32 MEM_MB_DATA31 MEM_MB_DATA30 MEM_MB_DATA29 MEM_MB_DATA28 MEM_MB_DATA27 MEM_MB_DATA26 MEM_MB_DATA25 MEM_MB_DATA24 MEM_MB_DATA23 MEM_MB_DATA22 MEM_MB_DATA21 MEM_MB_DATA20 MEM_MB_DATA19 MEM_MB_DATA18 MEM_MB_DATA17 MEM_MB_DATA16 MEM_MB_DATA15 MEM_MB_DATA14 MEM_MB_DATA13 MEM_MB_DATA12 MEM_MB_DATA11 MEM_MB_DATA10 MEM_MB_DATA9 MEM_MB_DATA8 MEM_MB_DATA7 MEM_MB_DATA6 MEM_MB_DATA5 MEM_MB_DATA4 MEM_MB_DATA3 MEM_MB_DATA2 MEM_MB_DATA1 MEM_MB_DATA0

MEM_MB_DQS_H8 MEM_MB_DQS_L8

MEM_MB_DM8 MEM_MB_CHECK7

MEM_MB_CHECK6 MEM_MB_CHECK5 MEM_MB_CHECK4 MEM_MB_CHECK3 MEM_MB_CHECK2 MEM_MB_CHECK1 MEM_MB_CHECK0

1

MEM_MB_DATA[63..0] 10,11

MEM_MB_DQS_H8 10,11 MEM_MB_DQS_L8 10,11

MEM_MB_DM8 10,11

Add For ECC 0829 Add For ECC 0829

A A

MICRO-START INT'L CO.,LTD.

Title

CPU AM2 DDR MEMORY I/F

Size Document Number Rev

Custom

Date: Sheet

5

4

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

VL390 0A

1

of

837Tuesday, September 09, 2008

5

4

3

2

1

CPU AM2 PWR & GND

C693

C22u6.3X1206

C715

C10u6.3X50805

12

C111

C0.01U16X0402

VCCPVCCP

M11 M13 M15 M17 M19

W10 W12 W14 W16 W18 W20

C701

C22u6.3X1206

C710

C10u6.3X50805

C0.01u16X-1

12

C110

C0.01U16X0402

C180P50N0402

Bottom side

C708 C2.2u10Y-RHC708 C2.2u10Y-RH C692 C2.2u10Y-RHC692 C2.2u10Y-RH

4

L14 L16 L18 M2 M3 M7 M9

N8 N10 N12 N14 N16 N18

P7

P9 P11 P13 P15 P17 P19

R4 R5

R8 R10 R12 R14 R16 R18 R20

T2 T3 T7

T9 T11 T13 T15 T17 T19 T21

U8 U10 U12 U14 U16 U18 U20

V9 V11 V13 V15 V17 V19 V21

W4 W5 W8

Y2

Y3

Y7

Y9 Y11 Y13 Y15 Y21

CPU1G

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24 VDD25 VDD26 VDD27 VDD28 VDD29 VDD30 VDD31 VDD32 VDD33 VDD34 VDD35 VDD36 VDD37 VDD38 VDD39 VDD40 VDD41 VDD42 VDD43 VDD44 VDD45 VDD46 VDD47 VDD48 VDD49 VDD50 VDD51 VDD52 VDD53 VDD54 VDD55 VDD56 VDD57 VDD58 VDD59 VDD60 VDD61 VDD62 VDD63 VDD64 VDD65 VDD66 VDD67 VDD68 VDD69 VDD70 VDD71 VDD72 VDD73 VDD74 VDD75

C694

C695

C4.7U10Y0805

C241

VDD2

C699

C4.7U10Y0805

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8

VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48

VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75

C707

AK20 AK22 AK24 AK26 AK28 AK30 AL5 B4 B9 B11 B14 B16 B18 B20 B22 B24 B26 B28 B30 C3 D14 D16 D18 D20 D22 D24 D26 D28 D30 E11 F4 F14 F16 F18 F20 F22 F24 F26 F28 F30 G9 G11 H8 H10 H12 H14 H16 H18

H24 H26 H28 H30 J4 J5 J7 J9 J11 J13 J15 J17 J19 J21 J23 K2 K3 K8 K10 K12 K14 K16 K18 K20 K22 Y18

C696

C4.7U10Y0805

C180P50N0402

C88 C2.2u10Y-RHC88 C2.2u10Y-RH

CPU1I

VCCP

CPU1H

VDD3

AA20

VDD1

AA22

VDD2

AB13

VDD3

AB15

VDD4

AB17

VDD5

AB19

VDD6

AB21

VDD7

AB23

VDD8

AC12

VDD9

AC14

VDD10

AC16

VDD11

AC18

VDD12

AC20

VDD13

AC22

VDD14

AD11

VDD15

AD23

VDD16

AE12

VDD17

AF11

VDD18

L20

VDD19

L22

VDD20

M21

VDD21

M23

VDD22

N20

VDD23

N22

VDD24

P21

VDD25

P23

VDD26

R22

VDD27

T23

VDD28

U22

VDD29

V23

VDD30

W22

VDD31

Y23

VDD32

5

GND

Change to

6

GND

Passive

7

GND

8

GND

1

GND

2

GND

3

GND

VCC_DDR

C697

C681

C22u6.3X1206

VCC_DDR

C239

C4.7u6.3X5

CPU_VDDR

CPU_VDDNBVCCP

C22u6.3X1206

CPU_VDDR

C0.22u10Y0402

C22u6.3X1206

Place along the VCC_DDR/VSS plane splite

C131

C210

C4.7U10Y0805

C4.7u6.3X5

Bottom side

C224

C50

C0.01u16X-1

C0.22U16X

C68

C90

C0.22u10Y0402

3

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8

VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65

C702

C22u6.3X1206

C220

C4.7U10Y0805

C716

C0.01U16X0402

C66

C0.22u10Y0402

N17 N19 N21 N23 P2 P3 P8 P10 P12 P14 P16 P18 P20 P22 R7 R9 R11 R13 R15 R17 R19 R21 R23 T8 T10 T12 T14 T16 T18 T20 T22 U4 U5 U7 U9 U11 U13 U15 U17 U19 U21 U23 V2 V3 V10 V12 V14 V16 V18 V20 V22 W9 W11 W13 W15 W17 W19 W21 W23 Y8 Y10 Y12 W7 Y20 Y22

Bottom side

C684

C712

C0.22U16X

C774

C132

C180P50N0402

12

C246

Place between the DIMM Slot

12

C76

C233

C0.01U16X0402

CPU_VDDR@4A

C0.01u16X-1

C180P50N0402

VTT_DDR

X_C4.7U10Y0805

C4.7U10Y0805

VCC_1V2

CPU_VDDR

VCC_DDR

MEM_MA1_CLK_H011 MEM_MA1_CLK_L011

MEM_MA0_CLK_H110 MEM_MA0_CLK_L110

MEM_MB1_CLK_H011 MEM_MB1_CLK_L011

MEM_MB0_CLK_H110 MEM_MB0_CLK_L110

C687

C705

C0.01u16X-1

C180p50N

C819

C234

C180P50N0402

Place behind the DIMM Slot

C287

C267

X_C4.7U10Y0805

C4.7U10Y0805

C252

C61

C4.7U10Y0805

C690

C243

C57

CPU1I

VDDIO

AJ4 AJ3 AJ2 AJ1

D12 C12 B12 A12

AB24 AB26 AB28 AB30 AC24 AD26 AD28 AD30

AF30

M24 M26 M28 M30 P24 P26 P28 P30 T24 T26 T28 T30 V25 V26 V28 V30 Y24 Y26 Y28 Y29

MEM_MA1_ODT111

MEM_MA0_ODT110

MEM_MB1_ODT111

MEM_MB0_ODT110

Remove pin H3, H4, H21, AD18, AD19, AE8; change pin H20, AE7 to NP/VSS

C714

C10u6.3X50805

If the distance between the processor keepout and the keepout of the first DIMM is less than 2.5 inches, there are four additional 180-pF capacitors instead of two.

C65

C130

C4.7U10Y0805

C258

C10u6.3X50805

C4.7U10Y0805

VLDT_A1 VLDT_A2 VLDT_A3 VLDT_A4

VTT1 VTT2 VTT3 VTT4

VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12 VDDIO13 VDDIO14 VDDIO15 VDDIO16 VDDIO17 VDDIO18 VDDIO19 VDDIO20 VDDIO21 VDDIO22 VDDIO23 VDDIO24 VDDIO25 VDDIO26 VDDIO27 VDDIO28 VDDIO29

C0.22U16X

VLDT_B1 VLDT_B2 VLDT_B3 VLDT_B4

VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28

MEM_MA1_CLK_H0 MEM_MA1_CLK_L0

MEM_MA1_ODT1 MEM_MA0_CLK_H1 MEM_MA0_CLK_L1

MEM_MA0_ODT1 MEM_MB1_CLK_H0

MEM_MB1_CLK_L0

MEM_MB1_ODT1 MEM_MB0_CLK_H1 MEM_MB0_CLK_L1

MEM_MB0_ODT1

C768

C331

C262

C4.7U10Y0805

2

VTT5 VTT6 VTT7 VTT8 VTT9

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9

VCC_DDR

12

C4.7U10Y0805

VLDT_RUN_B

H6 H5 H2 H1

AK12 AJ12 AH12 AG12 AL12

K24 K26 K28 K30 L7 L9 L11 L13 L15 L17 L19 L21 L23 M8 M10 M12 M14 M16 M18 M20 M22 N4 N5 N7 N9 N11 N13 N15

L25 L26 L31 L30

W26 W25

AE27

U24 V24

AE28

Y31 Y30

AG31

V31

W31

AF31 AD18

AD19

AE7 AE8

H3

H4 H20 H21

+

EC20

EC20 .CD1000U6.3EL11.5

.CD1000U6.3EL11.5

C263

C4.7U10Y0805

C120

CPU_VDDR

C10u6.3X50805

CPU1E

INTERNAL MISC E

RSVD1 RSVD2 RSVD3 RSVD4

RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10

RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16

KEY1 KEY2 KEY3 KEY4 KEY5 KEY6 KEY7 KEY8

CPU_VDDIO_PWRGD generater circuit

100ns after VCC_DDR valid

VCC3_SB

R635

B

X_10KR0402

C276

C261

C4.7U10Y0805

C116

C116 X_C0.01U25Y

X_C0.01U25Y

near (1900,-4700)*3, near C116*2

VCCP

C788

X_C0.1U16Y0402

MEM_MA_RESET#

E20

RSVD17

MEM_MB_RESET#

B19

RSVD18

AK3

RSVD21

CPU_VDDIO_PWRGD

F3

RSVD23

RSVD27 RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 RSVD33 RSVD34 RSVD35 RSVD36 RSVD37 RSVD38

R172

R172 X_4.7KR0402

X_4.7KR0402

CE

Q39

Q39 X_N-MMBT3904

X_N-MMBT3904

Add pin B2 as NP/RSVD

AD25 AE24 AE25 AJ18 AJ20 C18 C20 G24 G25 H25

MEM_MB_EVENT#

V29

MEM_MA_EVENT#

W30

VCC3_SB

R661

B

X_10KR0402

Title

CPU AM2 PWR & GND

Size Document Number Rev

C

VL390 0A

Date: Sheet

EMI_0B

C791

C789

X_C0.1U16Y0402

CE

Q43

Q43 X_N-MMBT3904

X_N-MMBT3904

TP129TP129

TP130TP130

TP131TP131

TP132TP132

C791

C792

C790

X_C0.1U16Y0402

R472

R472 X_5.6KR1%0402

X_5.6KR1%0402

MICRO-START INT'L CO.,LTD.

C792

X_C0.1U16Y0402

MEM_MA_RESET# 10,11 MEM_MB_RESET# 10,11

VCC_DDR

DG use 1KR PU

R300 301R0402R300 301R0402 R423 301R0402R423 301R0402

MEM_MB_EVENT# 10,11 MEM_MA_EVENT# 10,11

EVENT pins are for future AM3r2

Layout: Route as 60 ohms with 5/10 W/S from CPU pins.

VCC_DDR

R199

R199 X_4.7KR0402

X_4.7KR0402

CPU_VDDIO_PWRGD

R662

C855

X_4.7KR0402

X_C1U10Y

VCCP

VCC_1V2

CPU_VDDR

VCC_DDR

1

937Tuesday, September 09, 2008

of

CPU_VDDNB

CPU1F

VDD1

A4

VDDNB1

A6

VDDNB2

B5

VDDNB3

B7

VDDNB4

C6

VDDNB5

C8

VDDNB6

D7

VDDNB7

D9

VDDNB8

D D

C C

B B

A A

VCCP

C685

C22u6.3X1206

VCCP

C114

C0.01u16X-1

CPU_VDDNB

C72

C22u6.3X1206

VCC_1V2

C104

C10u6.3X50805

C22u6.3X1206

C0.22U16X

C22u6.3X1206

C10u6.3X50805

E8

VDDNB9

E10

VDDNB10

F9

VDDNB11

F11

VDDNB12

G10

VDDNB13

G12

VDDNB14

AA8

VDD3

AA10

VDD4

AA12

VDD5

AA14

VDD6

AA16

VDD7

AA18

VDD8

AB7

VDD9

AB9

VDD10

AB11

VDD11

AC4

VDD12

AC5

VDD13

AC8

VDD14

AC10

VDD15

AD2

VDD16

AD3

VDD17

AD7

VDD18

AD9

VDD19

AE10

VDD20

AF7

VDD21

AF9

VDD22

AG4

VDD23

AG5

VDD24

AG7

VDD25

AH2

VDD26

AH3

VDD27

B3

VDD28

C2

VDD31

C4

VDD32

D3

VDD35

D5

VDD36

E4

VDD39

E6

VDD40

F5

VDD43

F7

VDD44

G6

VDD47

G8

VDD48

H7

VDD51

H11

VDD52

H23

VDD53

J8

VDD54

J12

VDD55

J14

VDD56

J16

VDD57

J18

VDD58

J20

VDD59

J22

VDD60

J24

VDD61

K7

VDD62

K9

VDD63

K11

VDD64

K13

VDD65

K15

VDD66

K17

VDD67

K19

VDD68

K21

VDD69

K23

VDD70

L4

VDD71

L5

VDD72

L8

VDD73

L10

VDD74

L12

VDD75

Y17

VDD150

Y19

VDD151

C698

C706

C22u6.3X1206

C706

C713

C22u6.3X1206

Bottom side

C709

C686

C10u6.3X50805

C679

C10u6.3X50805

C105

C4.7U10Y0805

C686

C107

C236

C682

C0.22U16X

Bottom side TOP side, place close to CPU socket

C683

C0.01u16X-1

C723

C10u6.3X50805

5

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8

VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44

VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74

VSS240 VSS241

C689

C22u6.3X1206

C680

C10u6.3X50805

C81

C10u6.3X50805

C229

C4.7U10Y0805

A3 A7 A9 A11 AA4 AA5 AA7 AA9 AA11 AA13 AA15 AA17 AA19 AA21 AA23 AB2 AB3 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC7 AC9 AC11 AC13 AC15 AC17 AC19 AC21 AC23 AD8 AD10 AD12 AD14 AD16 AD20 AD22 AD24 AE4 AE5

AE11 AF2 AF3 AF8 AF10 AF12 AF14 AF16 AF18 AF20 AF22 AF24 AF26 AF28 AG10 AG11 AH14 AH16 AH18 AH20 AH22 AH24 AH26 AH28 AH30 AK2 AK14 AK16 AK18 Y14 Y16

Bottom side

C688

C22u6.3X1206

C703

C10u6.3X50805

C108

C0.22U16X

C249

C180P50N0402

C700

C691

C79

X_C0.22U16X

C237

C704

C22u6.3X1206

C711

C10u6.3X50805

C80

C4.7U10Y0805

VCC_DDR VCCP

MEM_MA_DQS_H[7..0]8,11 MEM_MA_DQS_L[7..0]8,11 MEM_MA_CHECK[7..0]8,11

MEM_MA_DATA[63..0]8,11

D D

C C

B B

De-coupling Caps For DIMMs

Place close to DIMM1

VCC_DDR

C806 C2.2u10Y-RHC806 C2.2u10Y-RH C807 C2.2u10Y-RHC807 C2.2u10Y-RH C808 C2.2u10Y-RHC808 C2.2u10Y-RH C810 C220p25N0402C810 C220p25N0402

Place close to DIMM1 with DIMM2

VCC_DDR

A A

C809 C2.2u10Y-RHC809 C2.2u10Y-RH

Place close to DIMM2

VCC_DDR

C811 C0.1U16Y0402C811 C0.1U16Y0402 C812 C0.1U16Y0402C812 C0.1U16Y0402

VCC3

C813 C2.2u10Y-RHC813 C2.2u10Y-RH

5

MEM_MA_DATA0 MEM_MA_DATA1 MEM_MA_DATA2 MEM_MA_DATA3 MEM_MA_DATA4 MEM_MA_DATA5 MEM_MA_DATA6 MEM_MA_DATA7 MEM_MA_DATA8 MEM_MA_DATA9 MEM_MA_DATA10 MEM_MA_DATA11 MEM_MA_DATA12 MEM_MA_DATA13 MEM_MA_DATA14 MEM_MA_DATA15 MEM_MA_DATA16 MEM_MA_DATA17 MEM_MA_DATA18 MEM_MA_DATA19 MEM_MA_DATA20 MEM_MA_DATA21 MEM_MA_DATA22 MEM_MA_DATA23 MEM_MA_DATA24 MEM_MA_DATA25 MEM_MA_DATA26 MEM_MA_DATA27 MEM_MA_DATA28 MEM_MA_DATA29 MEM_MA_DATA30 MEM_MA_DATA31 MEM_MA_DATA32 MEM_MA_DATA33 MEM_MA_DATA34 MEM_MA_DATA35 MEM_MA_DATA36 MEM_MA_DATA37 MEM_MA_DATA38 MEM_MA_DATA39 MEM_MA_DATA40 MEM_MA_DATA41 MEM_MA_DATA42 MEM_MA_DATA43 MEM_MA_DATA44 MEM_MA_DATA45 MEM_MA_DATA46 MEM_MA_DATA47 MEM_MA_DATA48 MEM_MA_DATA49 MEM_MA_DATA50 MEM_MA_DATA51 MEM_MA_DATA52 MEM_MA_DATA53 MEM_MA_DATA54 MEM_MA_DATA55 MEM_MA_DATA56 MEM_MA_DATA57 MEM_MA_DATA58 MEM_MA_DATA59 MEM_MA_DATA60 MEM_MA_DATA61 MEM_MA_DATA62 MEM_MA_DATA63

VCC_DDR

C235 X_C0.1U16Y0402C235 X_C0.1U16Y0402 C242 X_C0.1U16Y0402C242 X_C0.1U16Y0402

VCC_DDR VCC3

54

DIMM1

3

DQ0

VDD51VDD

VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD

4

DQ1

9

DQ2

10

DQ3

122

DQ4

123

DQ5

128

DQ6

129

DQ7

12

DQ8

13

DQ9

18

DQ10

19

DQ11

131

DQ12

132

DQ13

137

DQ14

138

DQ15

21

DQ16

22

DQ17

27

DQ18

28

DQ19

140

DQ20

141

DQ21

146

DQ22

147

DQ23

30

DQ24

31

DQ25

36

DQ26

37

DQ27

149

DQ28

150

DQ29

155

DQ30

156

DQ31

81

DQ32

82

DQ33

87

DQ34

88

DQ35

200

DQ36

201

DQ37

206

DQ38

207

DQ39

90

DQ40

91

DQ41

96

DQ42

97

DQ43

209

DQ44

210

DQ45

215

DQ46

216

DQ47

99

DQ48

100

DQ49

105

DQ50

106

DQ51

218

DQ52

219

DQ53

224

DQ54

225

DQ55

108

DQ56

109

DQ57

114

DQ58

115

DQ59

227

DQ60

228

DQ61

233

DQ62

234

DQ63

2

VSS

5

VSS

8

VSS

11

VSS

14

VSS

17

VSS

20

VSS

23

VSS

26

VSS

29

VSS

32

VSS

35

VSS

38

VSS

41

VSS

44

VSS

47

VSS

80

VSS

83

VSS

86

VSS

89

VSS

92

VSS

95

VSS

98

VSS

101

VSS

104

VSS

107

110

113

VSS

116

119

121

124

127

130

133

136

139

DIMM1(CHANNEL-A A0) ADDRESS=0:0(SA1:SA0)

170

173

176

179

182

VDD

DDR3

VSS

142

145

148

151

154

183

186

189

191

VDD

VSS

157

160

163

166

4

VTT_DDR

120

240

194

197

VDD

VSS

199

202

205

VSS

236

VDDSPD

VSS

208

79

68

53

167

VTT

RSVD

NC/TEST4

NC/PAR_IN

NC/ERR_OUT

VSS

211

214

217

220

223

226

229

232

4

MEM_MA_EVENT# MEM_MB_EVENT#

48

187

198

MEM_MA_ADD0

188

A0

MEM_MA_ADD1

181

A1

FREE1

FREE249FREE3

FREE4

MEM_MA_ADD2

61

A2

MEM_MA_ADD3

180

A3

MEM_MA_ADD4

59

A4

MEM_MA_ADD5

58

A5

MEM_MA_ADD6

178

A6

MEM_MA_ADD7

56

A7

MEM_MA_ADD8

177

A8

MEM_MA_ADD9

175

A9

MEM_MA_ADD10

70

A10/AP

MEM_MA_ADD11

55

A11

MEM_MA_ADD12

174

A12

MEM_MA_ADD13

196

A13

MEM_MA_ADD14

172

A14

MEM_MA_ADD15

171

A15

MEM_MA_CHECK0

39

CB0

MEM_MA_CHECK1

40

CB1

MEM_MA_CHECK2

45

CB2

MEM_MA_CHECK3

46

CB3

MEM_MA_CHECK4

158

CB4

MEM_MA_CHECK5

159

CB5

MEM_MA_CHECK6

164

CB6

MEM_MA_CHECK7

165

CB7

MEM_MA_DQS_H0

7

DQS0

MEM_MA_DQS_L0

6

DQS0#

MEM_MA_DQS_H1

16

DQS1

MEM_MA_DQS_L1

15

DQS1#

MEM_MA_DQS_H2

25

DQS2

MEM_MA_DQS_L2

24

DQS2#

MEM_MA_DQS_H3

34

DQS3

MEM_MA_DQS_L3

33

DQS3#

MEM_MA_DQS_H4

85

DQS4

MEM_MA_DQS_L4

84

DQS4#

MEM_MA_DQS_H5

94

DQS5

MEM_MA_DQS_L5

93

DQS5#

MEM_MA_DQS_H6

103

DQS6

MEM_MA_DQS_L6

102

DQS6#

MEM_MA_DQS_H7

112

DQS7

MEM_MA_DQS_L7

111

DQS7#

MEM_MA_DQS_H8

43

DQS8

MEM_MA_DQS_L8

42

DQS8#

MEM_MA_DM0

125

DM0/DQS9

126

NC/DQS9# DM1/DQS10 NC/DQS10# DM2/DQS11 NC/DQS11# DM3/DQS12 NC/DQS12# DM4/DQS13 NC/DQS13# DM5/DQS14 NC/DQS14# DM6/DQS15 NC/DQS15# DM7/DQS16 NC/DQS16# DM8/DQS17 NC/DQS17#

CK1#(NU)

VSS

235

239

MEM_MA_DM1

134 135

MEM_MA_DM2

143 144

MEM_MA_DM3

152 153

MEM_MA_DM4

203 204

MEM_MA_DM5

212 213

MEM_MA_DM6

221 222

MEM_MA_DM7

230 231

MEM_MA_DM8

161 162

MEM_MA0_ODT0

195

ODT0

MEM_MA0_ODT1

77

ODT1

MEM_MA_CKE0

50

CKE0

MEM_MA_CKE1

169

CKE1

MEM_MA0_CS_L0

193

CS0#

MEM_MA0_CS_L1

76

CS1#

MEM_MA_BANK0

71

BA0

MEM_MA_BANK1

190

BA1

MEM_MA_BANK2

52

BA2

MEM_MA_WE_L

73

WE#

MEM_MA_RAS_L

192

RAS#

MEM_MA_CAS_L

74

CAS#

MEM_MA_RESET# MEM_MB_RESET#

168

RESET#

MEM_MA0_CLK_H0

184

CK0

MEM_MA0_CLK_L0

185

CK0#

MEM_MA0_CLK_H1

63

CK1(NU)

MEM_MA0_CLK_L1

64

MEM_VREF_DQ

1

VREFDQ

MEM_VREF_CA

67

VREFCA

SCLK

118

SCL

SDATA

238

SDA

237

SA1

117

SA0

MEC1

MEC2

MEC3

DDRIII-240P_BLUE-RH

MEC1

MEC2

MEC3

MEM_MA_EVENT# 9,11 MEM_MB_EVENT# 9,11

MEM_MA_ADD[15..0] 8,11

Add For ECC 0829

MEM_MA_DQS_H8 8,11 MEM_MA_DQS_L8 8,11

MEM_MA_DM[7..0] 8,11

MEM_MA_DM8 8,11

MEM_MA0_ODT0 8 MEM_MA0_ODT1 9 MEM_MA_CKE0 8,11 MEM_MA_CKE1 8,11 MEM_MA0_CS_L0 8 MEM_MA0_CS_L1 8 MEM_MA_BANK0 8,11 MEM_MA_BANK1 8,11 MEM_MA_BANK2 8,11

MEM_MA_WE_L 8,11 MEM_MA_RAS_L 8,11 MEM_MA_CAS_L 8,11

MEM_MA0_CLK_H0 8 MEM_MA0_CLK_L0 8 MEM_MA0_CLK_H1 9 MEM_MA0_CLK_L1 9

MEM_VREF_DQ MEM_VREF_CA MEM_VREF_CA

SCLK 11,12,18,26 SDATA 11,12,18,26

VCC_DDR

R48

C382

C382 C0.1U16Y0402

C0.1U16Y0402

15R1%

C582

R568

R568 15R1%

15R1%

Add For ECC 0829

MEM_VREF_DQ

C0.1U16Y0402

C805

C1000P50X0402

C805

C1000P50X0402

MEM_MA_RESET# 9,11

VCC_DDR

C804

C1000P50X0402

C804

C1000P50X0402

3

MEM_MB_DQS_H[7..0]8,11 MEM_MB_DQS_L[7..0]8,11 MEM_MB_CHECK[7..0]8,11

MEM_VREF_CA

C785

C1000P50X0402

C785

C1000P50X0402

MEM_MB_DATA0 MEM_MB_DATA1 MEM_MB_DATA2 MEM_MB_DATA3 MEM_MB_DATA4 MEM_MB_DATA5 MEM_MB_DATA6 MEM_MB_DATA7 MEM_MB_DATA8 MEM_MB_DATA9 MEM_MB_DATA10 MEM_MB_DATA11 MEM_MB_DATA12 MEM_MB_DATA13 MEM_MB_DATA14 MEM_MB_DATA15 MEM_MB_DATA16 MEM_MB_DATA17 MEM_MB_DATA18 MEM_MB_DATA19 MEM_MB_DATA20 MEM_MB_DATA21 MEM_MB_DATA22 MEM_MB_DATA23 MEM_MB_DATA24 MEM_MB_DATA25 MEM_MB_DATA26 MEM_MB_DATA27 MEM_MB_DATA28 MEM_MB_DATA29 MEM_MB_DATA30 MEM_MB_DATA31 MEM_MB_DATA32 MEM_MB_DATA33 MEM_MB_DATA34 MEM_MB_DATA35 MEM_MB_DATA36 MEM_MB_DATA37 MEM_MB_DATA38 MEM_MB_DATA39 MEM_MB_DATA40 MEM_MB_DATA41 MEM_MB_DATA42 MEM_MB_DATA43 MEM_MB_DATA44 MEM_MB_DATA45 MEM_MB_DATA46 MEM_MB_DATA47 MEM_MB_DATA48 MEM_MB_DATA49 MEM_MB_DATA50 MEM_MB_DATA51 MEM_MB_DATA52 MEM_MB_DATA53 MEM_MB_DATA54 MEM_MB_DATA55 MEM_MB_DATA56 MEM_MB_DATA57 MEM_MB_DATA58 MEM_MB_DATA59 MEM_MB_DATA60 MEM_MB_DATA61 MEM_MB_DATA62 MEM_MB_DATA63

C772

C1000P50X0402

C772

C1000P50X0402

MEM_MB_DATA[63..0]8,11 MEM_MB_ADD[15..0] 8,11

C34

R44

C0.1U16Y0402

15R1%

C36

C0.1U16Y0402

C36

C0.1U16Y0402

R55

R55 15R1%

15R1%

3

VCC_DDR VCC3

54

DIMM2

3

DQ0

VDD51VDD

VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD

4

DQ1

9

DQ2

10

DQ3

122

DQ4

123

DQ5

128

DQ6

129

DQ7

12

DQ8

13

DQ9

18

DQ10

19

DQ11

131

DQ12

132

DQ13

137

DQ14

138

DQ15

21

DQ16

22

DQ17

27

DQ18

28

DQ19

140

DQ20

141

DQ21

146

DQ22

147

DQ23

30

DQ24

31

DQ25

36

DQ26

37

DQ27

149

DQ28

150

DQ29

155

DQ30

156

DQ31

81

DQ32

82

DQ33

87

DQ34

88

DQ35

200

DQ36

201

DQ37

206

DQ38

207

DQ39

90

DQ40

91

DQ41

96

DQ42

97

DQ43

209

DQ44

210

DQ45

215

DQ46

216

DQ47

99

DQ48

100

DQ49

105

DQ50

106

DQ51

218

DQ52

219

DQ53

224

DQ54

225

DQ55

108

DQ56

109

DQ57

114

DQ58

115

DQ59

227

DQ60

228

DQ61

233

DQ62

234

DQ63

2

VSS

5

VSS

8

VSS

11

VSS

14

VSS

17

VSS

20

VSS

23

VSS

26

VSS

29

VSS

32

VSS

35

VSS

38

VSS

41

VSS

44

VSS

47

VSS

80

VSS

83

VSS

86

VSS

89

VSS

92

VSS

95

VSS

98

VSS

101

VSS

104

VSS

107

110

113

116

119

VSS

121

124

127

130

133

136

2

170

173

176

179

182

183

186

189

191

194

197

VDD

DDR3

VSS

139

142

145

DIMM2(CHANNEL-B B0) ADDRESS=0:1(SA1:SA0)

2

VSS

148

151

154

157

160

163

166

199

202

205

TP133TP133

TP134TP134

VSS

236

VDDSPD

VSS

208

VTT_DDR

120

VTT

VSS

211

214

240

79

48

187

198

68

53

167

VTT

RSVD

FREE1

FREE249FREE3

NC/TEST4

NC/PAR_IN

NC/ERR_OUT

DM0/DQS9

NC/DQS9# DM1/DQS10 NC/DQS10# DM2/DQS11 NC/DQS11# DM3/DQS12 NC/DQS12# DM4/DQS13 NC/DQS13# DM5/DQS14 NC/DQS14# DM6/DQS15 NC/DQS15# DM7/DQS16 NC/DQS16# DM8/DQS17 NC/DQS17#

CK1#(NU)

VSS

217

220

223

226

229

232

235

239

MEM_VREF_DQ

MEM_VREF_CA

A0 A1

FREE4

A2 A3 A4 A5 A6 A7 A8 A9

A10/AP

A11 A12 A13 A14 A15

CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7

DQS0

DQS0#

DQS1

DQS1#

DQS2

DQS2#

DQS3

DQS3#

DQS4

DQS4#

DQS5

DQS5#

DQS6

DQS6#

DQS7

DQS7#

DQS8

DQS8#

ODT0 ODT1 CKE0 CKE1 CS0# CS1#

BA0 BA1 BA2

WE# RAS# CAS#

RESET#

CK0

CK0#

CK1(NU)

VREFDQ

VREFCA

SCL SDA SA1 SA0

MEC1

MEC2

MEC3

DDRIII-240P_BLANK-RH

MEC1

MEC2

MEC3

188 181 61 180 59 58 178 56 177 175 70 55 174 196 172 171

39 40 45 46 158 159 164 165

7 6 16 15 25 24 34 33 85 84 94 93 103 102 112 111 43 42

125 126 134 135 143 144 152 153 203 204 212 213 221 222 230 231 161 162

195 77 50 169 193 76 71 190 52

73 192 74 168

184 185 63 64

1 67 118 238 237 117

MEM_MB_ADD0 MEM_MB_ADD1 MEM_MB_ADD2 MEM_MB_ADD3 MEM_MB_ADD4 MEM_MB_ADD5 MEM_MB_ADD6 MEM_MB_ADD7 MEM_MB_ADD8 MEM_MB_ADD9 MEM_MB_ADD10 MEM_MB_ADD11 MEM_MB_ADD12 MEM_MB_ADD13 MEM_MB_ADD14 MEM_MB_ADD15

MEM_MB_CHECK0 MEM_MB_CHECK1 MEM_MB_CHECK2 MEM_MB_CHECK3 MEM_MB_CHECK4 MEM_MB_CHECK5 MEM_MB_CHECK6 MEM_MB_CHECK7

MEM_MB_DQS_H0 MEM_MB_DQS_L0 MEM_MB_DQS_H1 MEM_MB_DQS_L1 MEM_MB_DQS_H2 MEM_MB_DQS_L2 MEM_MB_DQS_H3 MEM_MB_DQS_L3 MEM_MB_DQS_H4 MEM_MB_DQS_L4 MEM_MB_DQS_H5 MEM_MB_DQS_L5 MEM_MB_DQS_H6 MEM_MB_DQS_L6 MEM_MB_DQS_H7 MEM_MB_DQS_L7 MEM_MB_DQS_H8 MEM_MB_DQS_L8

MEM_MB_DM0 MEM_MB_DM1 MEM_MB_DM2 MEM_MB_DM3 MEM_MB_DM4 MEM_MB_DM5 MEM_MB_DM6 MEM_MB_DM7 MEM_MB_DM8

MEM_MB0_ODT0 MEM_MB0_ODT1 MEM_MB_CKE0 MEM_MB_CKE1 MEM_MB0_CS_L0 MEM_MB0_CS_L1 MEM_MB_BANK0 MEM_MB_BANK1 MEM_MB_BANK2

MEM_MB_WE_L MEM_MB_RAS_L MEM_MB_CAS_L

MEM_MB0_CLK_H0 MEM_MB0_CLK_L0 MEM_MB0_CLK_H1 MEM_MB0_CLK_L1

MEM_VREF_DQ MEM_VREF_CA SCLK SDATA

VCC3

Add For ECC 0829

MEM_MB_DQS_H8 8,11 MEM_MB_DQS_L8 8,11

MEM_MB_DM[7..0] 8,11

Add For ECC 0829

MEM_MB_DM8 8,11

MEM_MB0_ODT0 8 MEM_MB0_ODT1 9 MEM_MB_CKE0 8,11 MEM_MB_CKE1 8,11 MEM_MB0_CS_L0 8 MEM_MB0_CS_L1 8 MEM_MB_BANK0 8,11 MEM_MB_BANK1 8,11 MEM_MB_BANK2 8,11

MEM_MB_WE_L 8,11 MEM_MB_RAS_L 8,11 MEM_MB_CAS_L 8,11

MEM_MB0_CLK_H0 8 MEM_MB0_CLK_L0 8 MEM_MB0_CLK_H1 9 MEM_MB0_CLK_L1 9

MEM_VREF_DQ

Title

FIRST LOGICAL DDR DIMM

Size Document Number Rev

Custom

VL390 0A

Date: Sheet

1

MEM_MB_RESET# 9,11

MICRO-START INT'L CO.,LTD.

10 37Tuesday, September 09, 2008

of

1

of

5

MEM_MA_DQS_H[7..0]8,10 MEM_MA_DQS_L[7..0]8,10 MEM_MA_CHECK[7..0]8,10

MEM_MA_DATA[63..0]8,10

D D

C C

B B

MEM_MA_DATA0 MEM_MA_DATA1 MEM_MA_DATA2 MEM_MA_DATA3 MEM_MA_DATA4 MEM_MA_DATA5 MEM_MA_DATA6 MEM_MA_DATA7 MEM_MA_DATA8 MEM_MA_DATA9 MEM_MA_DATA10 MEM_MA_DATA11 MEM_MA_DATA12 MEM_MA_DATA13 MEM_MA_DATA14 MEM_MA_DATA15 MEM_MA_DATA16 MEM_MA_DATA17 MEM_MA_DATA18 MEM_MA_DATA19 MEM_MA_DATA20 MEM_MA_DATA21 MEM_MA_DATA22 MEM_MA_DATA23 MEM_MA_DATA24 MEM_MA_DATA25 MEM_MA_DATA26 MEM_MA_DATA27 MEM_MA_DATA28 MEM_MA_DATA29 MEM_MA_DATA30 MEM_MA_DATA31 MEM_MA_DATA32 MEM_MA_DATA33 MEM_MA_DATA34 MEM_MA_DATA35 MEM_MA_DATA36 MEM_MA_DATA37 MEM_MA_DATA38 MEM_MA_DATA39 MEM_MA_DATA40 MEM_MA_DATA41 MEM_MA_DATA42 MEM_MA_DATA43 MEM_MA_DATA44 MEM_MA_DATA45 MEM_MA_DATA46 MEM_MA_DATA47 MEM_MA_DATA48 MEM_MA_DATA49 MEM_MA_DATA50 MEM_MA_DATA51 MEM_MA_DATA52 MEM_MA_DATA53 MEM_MA_DATA54 MEM_MA_DATA55 MEM_MA_DATA56 MEM_MA_DATA57 MEM_MA_DATA58 MEM_MA_DATA59 MEM_MA_DATA60 MEM_MA_DATA61 MEM_MA_DATA62 MEM_MA_DATA63

De-coupling Caps For DIMMs

Place close to DIMM3

VCC_DDR

C814 C2.2u10Y-RHC814 C2.2u10Y-RH

A A

Place close to DIMM3 with DIMM4

VCC_DDR

C821 C0.1U16Y0402C821 C0.1U16Y0402 C822 C0.1U16Y0402C822 C0.1U16Y0402 C829 C0.1U16Y0402C829 C0.1U16Y0402

VCC3

C824 C2.2u10Y-RHC824 C2.2u10Y-RH

5

VCC_DDR VCC3

54

DIMM3

3

DQ0

VDD51VDD

4

DQ1

9

DQ2

10

DQ3

122

DQ4

123

DQ5

128

DQ6

129

DQ7

12

DQ8

13

DQ9

18

DQ10

19

DQ11

131

DQ12

132

DQ13

137

DQ14

138

DQ15

21

DQ16

22

DQ17

27

DQ18

28

DQ19

140

DQ20

141

DQ21

146

DQ22

147

DQ23

30

DQ24

31

DQ25

36

DQ26

37

DQ27

149

DQ28

150

DQ29

155

DQ30

156

DQ31

81

DQ32

82

DQ33

87

DQ34

88

DQ35

200

DQ36

201

DQ37

206

DQ38

207

DQ39

90

DQ40

91

DQ41

96

DQ42

97

DQ43

209

DQ44

210

DQ45

215

DQ46

216

DQ47

99

DQ48

100

DQ49

105

DQ50

106

DQ51

218

DQ52

219

DQ53

224

DQ54

225

DQ55

108

DQ56

109

DQ57

114

DQ58

115

DQ59

227

DQ60

228

DQ61

233

DQ62

234

DQ63

2

VSS

5

VSS

8

VSS

11

VSS

14

VSS

17

VSS

20

VSS

23

VSS

26

VSS

29

VSS

32

VSS

35

VSS

38

VSS

41

VSS

44

VSS

47

VSS

80

VSS

83

VSS

86

VSS

89

VSS

92

VSS

95

VSS

98

VSS

101

VSS

104

VSS

107

110

113

116

Vref-DQ : Reference voltage for DQ0每DQ63, CB0每CB7 and PAR_IN. When in single ended mode used for

每

DQS7.

DQS0 Vref-CA : Reference voltage for A0-A15, BA0

RESET#(Output) : A synchronously forces all registered output LOW when RESET# is LOW. This signal can be used during power up to ensure that CKE is LOW and DQs are High-Z.

VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD

VSS

119

121

124

127

130

133

136

139

DIMM3(CHANNEL-A A1) ADDRESS=1:0(SA1:SA0)

170

173

176

179

182

183

VDD

DDR3

VSS

142

145

148

151

154

157

186

189

191

194

VDD

VSS

160

163

166

199

4

VTT_DDR

120

240

197

VDD

VSS

202

205

VSS

236

VDDSPD

VSS

208

211

79

68

53

167

VTT

RSVD

NC/TEST4

NC/PAR_IN

NC/ERR_OUT

VSS

214

217

220

223

226

229

232

4

MEM_MA_EVENT#

48

187

198

MEM_MA_ADD0

188

A0

MEM_MA_ADD1

181

A1

FREE1

FREE249FREE3

FREE4

MEM_MA_ADD2

61

A2

MEM_MA_ADD3

180

A3

MEM_MA_ADD4

59

A4

MEM_MA_ADD5

58

A5

MEM_MA_ADD6

178

A6

MEM_MA_ADD7

56

A7

MEM_MA_ADD8

177

A8

MEM_MA_ADD9

175

A9

MEM_MA_ADD10

70

A10/AP

MEM_MA_ADD11

55

A11

MEM_MA_ADD12

174

A12

MEM_MA_ADD13

196

A13

MEM_MA_ADD14

172

A14

MEM_MA_ADD15

171

A15

MEM_MA_CHECK0

39

CB0

MEM_MA_CHECK1

40

CB1

MEM_MA_CHECK2

45

CB2

MEM_MA_CHECK3

46

CB3

MEM_MA_CHECK4

158

CB4

MEM_MA_CHECK5

159

CB5

MEM_MA_CHECK6

164

CB6

MEM_MA_CHECK7

165

CB7

MEM_MA_DQS_H0

7

DQS0

MEM_MA_DQS_L0

6

DQS0#

MEM_MA_DQS_H1

16

DQS1

MEM_MA_DQS_L1

15

DQS1#

MEM_MA_DQS_H2

25

DQS2

MEM_MA_DQS_L2

24

DQS2#

MEM_MA_DQS_H3

34

DQS3

MEM_MA_DQS_L3

33

DQS3#

MEM_MA_DQS_H4

85

DQS4

MEM_MA_DQS_L4

84

DQS4#

MEM_MA_DQS_H5

94

DQS5

MEM_MA_DQS_L5

93

DQS5#

MEM_MA_DQS_H6

103

DQS6

MEM_MA_DQS_L6

102

DQS6#

MEM_MA_DQS_H7

112

DQS7

MEM_MA_DQS_L7

111

DQS7#

MEM_MA_DQS_H8

43

DQS8

MEM_MA_DQS_L8

42

DQS8#

MEM_MA_DM0

125

DM0/DQS9

126

NC/DQS9# DM1/DQS10 NC/DQS10# DM2/DQS11 NC/DQS11# DM3/DQS12 NC/DQS12# DM4/DQS13 NC/DQS13# DM5/DQS14 NC/DQS14# DM6/DQS15 NC/DQS15# DM7/DQS16 NC/DQS16# DM8/DQS17 NC/DQS17#

CK1#(NU)

VSS

235

239

MEM_MA_DM1

134 135

MEM_MA_DM2

143 144

MEM_MA_DM3

152 153

MEM_MA_DM4

203 204

MEM_MA_DM5

212 213

MEM_MA_DM6

221 222

MEM_MA_DM7

230 231

MEM_MA_DM8

161 162

MEM_MA1_ODT0

195

ODT0

MEM_MA1_ODT1

77

ODT1

MEM_MA_CKE0

50

CKE0

MEM_MA_CKE1

169

CKE1

MEM_MA1_CS_L0

193

CS0#

76

CS1#

MEM_MA_BANK0

71

BA0

MEM_MA_BANK1

190

BA1

MEM_MA_BANK2

52

BA2

MEM_MA_WE_L

73

WE#

MEM_MA_RAS_L

192

RAS#

MEM_MA_CAS_L

74

CAS#

MEM_MA_RESET# MEM_MB_RESET#

168

RESET#

MEM_MA1_CLK_H0

184

CK0

MEM_MA1_CLK_L0

185

CK0#

MEM_MA1_CLK_H1

63

CK1(NU)

MEM_MA1_CLK_L1

64

MEM_VREF_DQ

1

VREFDQ

MEM_VREF_CA

67

VREFCA

SCLK

118

SCL

SDATA

238

SDA

237

SA1

117

SA0

MEC1

MEC2

MEC3

DDRIII-240P_BLUE-RH

MEC1

MEC2

MEC3

每

BA2, RAS#, CAS#, WE#, S0#, S01#, CKE0, CKE1, ODT0 and ODT1.

MEM_MA_EVENT# 9,10

MEM_MA_ADD[15..0] 8,10

Add For ECC 0829

MEM_MA_DQS_H8 8,10 MEM_MA_DQS_L8 8,10

MEM_MA_DM[7..0] 8,10

Add For ECC 0829

MEM_MA_DM8 8,10

MEM_MA1_ODT0 8 MEM_MA1_ODT1 9 MEM_MA_CKE0 8,10 MEM_MA_CKE1 8,10 MEM_MA1_CS_L0 8 MEM_MA1_CS_L1 8 MEM_MA_BANK0 8,10 MEM_MA_BANK1 8,10 MEM_MA_BANK2 8,10

MEM_MA_WE_L 8,10 MEM_MA_RAS_L 8,10 MEM_MA_CAS_L 8,10

MEM_MA1_CLK_H0 9 MEM_MA1_CLK_L0 9 MEM_MA1_CLK_H1 8 MEM_MA1_CLK_L1 8

MEM_VREF_CA

SCLK 10,12,18,26

VCC3

SDATA 10,12,18,26

MEM_MA_RESET# 9,10

3

MEM_MB_DQS_H[7..0]8,10 MEM_MB_DQS_L[7..0]8,10 MEM_MB_CHECK[7..0]8,10

MEM_MB_DATA[63..0]8,10

3

MEM_MB_DATA0 MEM_MB_DATA1 MEM_MB_DATA2 MEM_MB_DATA3 MEM_MB_DATA4 MEM_MB_DATA5 MEM_MB_DATA6 MEM_MB_DATA7 MEM_MB_DATA8 MEM_MB_DATA9 MEM_MB_DATA10 MEM_MB_DATA11 MEM_MB_DATA12 MEM_MB_DATA13 MEM_MB_DATA14 MEM_MB_DATA15 MEM_MB_DATA16 MEM_MB_DATA17 MEM_MB_DATA18 MEM_MB_DATA19 MEM_MB_DATA20 MEM_MB_DATA21 MEM_MB_DATA22 MEM_MB_DATA23 MEM_MB_DATA24 MEM_MB_DATA25 MEM_MB_DATA26 MEM_MB_DATA27 MEM_MB_DATA28 MEM_MB_DATA29 MEM_MB_DATA30 MEM_MB_DATA31 MEM_MB_DATA32 MEM_MB_DATA33 MEM_MB_DATA34 MEM_MB_DATA35 MEM_MB_DATA36 MEM_MB_DATA37 MEM_MB_DATA38 MEM_MB_DATA39 MEM_MB_DATA40 MEM_MB_DATA41 MEM_MB_DATA42 MEM_MB_DATA43 MEM_MB_DATA44 MEM_MB_DATA45 MEM_MB_DATA46 MEM_MB_DATA47 MEM_MB_DATA48 MEM_MB_DATA49 MEM_MB_DATA50 MEM_MB_DATA51 MEM_MB_DATA52 MEM_MB_DATA53 MEM_MB_DATA54 MEM_MB_DATA55 MEM_MB_DATA56 MEM_MB_DATA57 MEM_MB_DATA58 MEM_MB_DATA59 MEM_MB_DATA60 MEM_MB_DATA61 MEM_MB_DATA62 MEM_MB_DATA63

VCC_DDR VCC3

54

DIMM4

3

DQ0

VDD51VDD

VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD

4

DQ1

9

DQ2

10

DQ3

122

DQ4

123

DQ5

128

DQ6

129

DQ7

12

DQ8

13

DQ9

18

DQ10

19

DQ11

131

DQ12

132

DQ13

137

DQ14

138

DQ15

21

DQ16

22

DQ17

27

DQ18

28

DQ19

140

DQ20

141

DQ21

146

DQ22

147

DQ23

30

DQ24

31

DQ25

36

DQ26

37

DQ27

149

DQ28

150

DQ29

155

DQ30

156

DQ31

81

DQ32

82

DQ33

87

DQ34

88

DQ35

200

DQ36

201

DQ37

206

DQ38

207

DQ39

90

DQ40

91

DQ41

96

DQ42

97

DQ43

209

DQ44

210

DQ45

215

DQ46

216

DQ47

99

DQ48

100

DQ49

105

DQ50

106

DQ51

218

DQ52

219

DQ53

224

DQ54

225

DQ55

108

DQ56

109

DQ57

114

DQ58

115

DQ59

227

DQ60

228

DQ61

233

DQ62

234

DQ63

2

VSS

5

VSS

8

VSS

11

VSS

14

VSS

17

VSS

20

VSS

23

VSS

26

VSS

29

VSS

32

VSS

35

VSS

38

VSS

41

VSS

44

VSS

47

VSS

80

VSS

83

VSS

86

VSS

89

VSS

92

VSS

95

VSS

98

VSS

101

VSS

104

VSS

107

110

113

116

119

121

170

VSS

124

127

130

133

136

139

142

DIMM2(CHANNEL-B B1) ADDRESS=1:1(SA1:SA0)

2

173

176

179

182

183

186

189

VDD

DDR3

VSS

145

148

151

154

157

160

163

2

1

VTT_DDR

120

240

191

194

197

VDD

VSS

166

199

202

205

236

VSS

208

VDDSPD

VSS

211

79

48

68

53

167

VTT

RSVD

FREE1

FREE249FREE3

NC/TEST4

NC/PAR_IN

NC/ERR_OUT

DM0/DQS9

NC/DQS9# DM1/DQS10 NC/DQS10# DM2/DQS11 NC/DQS11# DM3/DQS12 NC/DQS12# DM4/DQS13 NC/DQS13# DM5/DQS14 NC/DQS14# DM6/DQS15 NC/DQS15# DM7/DQS16 NC/DQS16# DM8/DQS17 NC/DQS17#

CK1#(NU)

VSS

214

217

220

223

226

229

232

235

239

187

198

A0 A1

FREE4

A2 A3 A4 A5 A6 A7 A8 A9

A10/AP

A11 A12 A13 A14 A15

CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7

DQS0

DQS0#

DQS1

DQS1#

DQS2

DQS2#

DQS3

DQS3#

DQS4

DQS4#

DQS5

DQS5#

DQS6

DQS6#

DQS7

DQS7#

DQS8

DQS8#

ODT0 ODT1 CKE0 CKE1

CS0# CS1#

BA0 BA1 BA2

WE# RAS# CAS#

RESET#

CK0

CK0#

CK1(NU)

VREFDQ VREFCA

SCL SDA SA1 SA0

MEC1

MEC2

MEC3

DDRIII-240P_BLANK-RH

MEC1

MEC2

MEC3

188 181 61 180 59 58 178 56 177 175 70 55 174 196 172 171

39 40 45 46 158 159 164 165

7 6 16 15 25 24 34 33 85 84 94 93 103 102 112 111 43 42

125 126 134 135 143 144 152 153 203 204 212 213 221 222 230 231 161 162

195 77 50 169 193 76 71 190 52

73 192 74 168

184 185 63 64

1 67 118 238 237 117

MEM_MB_EVENT#

MEM_MB_ADD0 MEM_MB_ADD1 MEM_MB_ADD2 MEM_MB_ADD3 MEM_MB_ADD4 MEM_MB_ADD5 MEM_MB_ADD6 MEM_MB_ADD7 MEM_MB_ADD8 MEM_MB_ADD9 MEM_MB_ADD10 MEM_MB_ADD11 MEM_MB_ADD12 MEM_MB_ADD13 MEM_MB_ADD14 MEM_MB_ADD15

MEM_MB_CHECK0 MEM_MB_CHECK1 MEM_MB_CHECK2 MEM_MB_CHECK3 MEM_MB_CHECK4 MEM_MB_CHECK5 MEM_MB_CHECK6 MEM_MB_CHECK7

MEM_MB_DQS_H0 MEM_MB_DQS_L0 MEM_MB_DQS_H1 MEM_MB_DQS_L1 MEM_MB_DQS_H2 MEM_MB_DQS_L2 MEM_MB_DQS_H3 MEM_MB_DQS_L3 MEM_MB_DQS_H4 MEM_MB_DQS_L4 MEM_MB_DQS_H5 MEM_MB_DQS_L5 MEM_MB_DQS_H6 MEM_MB_DQS_L6 MEM_MB_DQS_H7 MEM_MB_DQS_L7 MEM_MB_DQS_H8 MEM_MB_DQS_L8

MEM_MB_DM0 MEM_MB_DM1 MEM_MB_DM2 MEM_MB_DM3 MEM_MB_DM4 MEM_MB_DM5 MEM_MB_DM6 MEM_MB_DM7 MEM_MB_DM8

MEM_MB1_ODT0 MEM_MB1_ODT1 MEM_MB_CKE0 MEM_MB_CKE1 MEM_MB1_CS_L0 MEM_MB1_CS_L1MEM_MA1_CS_L1 MEM_MB_BANK0 MEM_MB_BANK1 MEM_MB_BANK2

MEM_MB_WE_L MEM_MB_RAS_L MEM_MB_CAS_L

MEM_MB1_CLK_H0 MEM_MB1_CLK_L0 MEM_MB1_CLK_H1 MEM_MB1_CLK_L1

MEM_VREF_DQ MEM_VREF_CA SCLK SDATA

MEM_MB_EVENT# 9,10

MEM_MB_ADD[15..0] 8,10

Add For ECC 0829

MEM_MB_DQS_H8 8,10 MEM_MB_DQS_L8 8,10

MEM_MB_DM[7..0] 8,10

Add For ECC 0829

MEM_MB_DM8 8,10

MEM_MB1_ODT0 8 MEM_MB1_ODT1 9 MEM_MB_CKE0 8,10 MEM_MB_CKE1 8,10 MEM_MB1_CS_L0 8 MEM_MB1_CS_L1 8 MEM_MB_BANK0 8,10 MEM_MB_BANK1 8,10 MEM_MB_BANK2 8,10

MEM_MB_WE_L 8,10 MEM_MB_RAS_L 8,10 MEM_MB_CAS_L 8,10

MEM_MB1_CLK_H0 9 MEM_MB1_CLK_L0 9 MEM_MB1_CLK_H1 8 MEM_MB1_CLK_L1 8

MEM_VREF_DQMEM_VREF_DQ MEM_VREF_CA

VCC3

Title

SECOND LOGICAL DDR DIMM

Size Document Number Rev

Custom

VL390 0A

Date: Sheet

MEM_MB_RESET# 9,10

MICRO-START INT'L CO.,LTD.

1

11 37Tuesday, September 09, 2008

of

5

Clock Gen SLG8LP625

CLK_VDD

L21

VCC3

D D

VCC3

CLK_VDD

VCC3

C C

B B

L21

600L500mA-300_0805

L25

600L500mA-300_0805

C2.2u10Y-RH

L20

600L500mA-300_0805

L19

600L500mA-300_0805

FP_RST#18,26,34

R494 X_0R0402R494 X_0R0402

R207and R198 have been change value for support RS780 2007/08/07 MS-7500

OSC_14M_NB R207/R198 RS780 (Single-ended) 1.1V 200R/100R RS740 3.3V 33R Serial

C364

C22u6.3X1206

C0.1U16Y0402

C348

C0.1U16Y0402

C321

C321 C2.2u10Y-RH

C2.2u10Y-RH

C335

C335 C2.2u10Y-RH

C2.2u10Y-RH

VCC3

SB_OSC_14M17 NB_OSC_14M15

Silego CRB Suggested

150 MILS WIDTH

Place Close to PIN.33,40,48,28,11,14,21

C358

C354

C371

C0.1U16Y0402

C343

C22u6.3X1206

Place Close to PIN.52

Place Close to PIN.56

C354

C0.1U16Y0402

15 MILS WIDTH

CLK_VDDA

C347

12 MILS WIDTH

CLK_VDDREF

12 MILS WIDTH

CLK_VDD48

C319 C27p50N0402C319 C27p50N0402 R263 0R0402R263 0R0402

14.318MHZ16P_D-RH

C338 C22P50N0402C338 C22P50N0402

R210 4.7KR0402R210 4.7KR0402

R224

R224 X_75R1%0402

X_75R1%0402

CLK_VDD

4

C324

C363

C0.1U16Y0402

Y1

SCLK10,11,18,26 SDATA10,11,18,26

1 2

C363

C0.1U16Y0402

C333

C0.1U16Y0402

R656 X_110R1%0402R656 X_110R1%0402 R207 158R1%0402R207 158R1%0402

R198

90.9R1%0402

C368

C0.1U16Y0402

CLK_VDDA

CLK_VDDREF

CLK_VDD48

CLK_VDD

R216

R216 X_1MR0402

X_1MR0402

CLK_RST#

R496R496 R582R582

R211 1KR0402R211 1KR0402

CLK_VDD

R510

R510 X_8.2KR0402

X_8.2KR0402

R205

8.2KR0402

C369

CLK_PD#

HWM_14M_RR OSC14M_REFOUT NB_OSC_14M_R

U15

36

VDD_A

35

VSS_A

52

VDD_REF

53

VSS_REF

56

VDD_48

3

VSS_48

33

VDD

34

VSS

40

VDD_CPU

39

VSS_CPU

48

VDD_HTT

45

VSS_HTT

28

VDD_ATIGCLK

11

VDD_SRC

14

VDD_SRC

21

VDD_SB_SRC

24

VSS_ATIGCLK

27

VSS_ATIGCLK

10

VSS_SRC

15

VSS_SRC

20

VSS_SB_SRC

54

XTAL_IN

55

XTAL_OUT

44

RESTORE#

4

SCL

5

SDA

43

PD#

51

REF_0/SEL_HTT66

50

REF_1

49

REF_2

3.3V

SLG8LP625TTR_TSSOP56-RH

3

CPU_K8_0

CPU_K8_0#

CPU_K8_1

CPU_K8_1#

ATIGCLK_0

ATIGCLK_0#

ATIGCLK_1

ATIGCLK_1#

ATIGCLK_2

ATIGCLK_2#

SB_SRC_0

SB_SRC_0#

SB_SRC_1

SB_SRC_1#

SRC_0

SRC_0#

SRC_1

SRC_1#

SRC_2

SRC_2#

SRC_3

SRC_3#

HTT_0/66M_0

HTT_0#/66M_1

48MHz_0 48MHz_1

42 41 38 37

NB_GXF_CLK_R

32

NB_GXF_CLK#_R

31 30 29

PE16_GXF_CLK_R

26

PE16_GXF_CLK#_R

25

NB_SBREF_CLK_R

23

NB_SBREF_CLK#_R

22

SB_LINK_CLK_R

19

SB_LINK_CLK#_R

18

PE1_GPP_CLK1_R

17

PE1_GPP_CLK1#_R

16 13 12

LAN_CLK_R

9

LAN_CLK#_R

8 7 6

NBHTT_CLK_R

47

NBHTT_CLK#_R

46

SIO_48M_CLK_R

2

USB_48M_CLK_R

1

Clock chip has internal serial terminations for differencial pairs, external resistors are reserved for debug purpose.

R265 0R0402R265 0R0402 R268 0R0402R268 0R0402

R250 0R0402R250 0R0402 R267 0R0402R267 0R0402

R261 0R0402R261 0R0402 R274 0R0402R274 0R0402 R269 0R0402R269 0R0402 R266 0R0402R266 0R0402

R264 0R0402R264 0R0402

R504 0R0402R504 0R0402 R505 0R0402R505 0R0402

R208 0R0402R208 0R0402 R209 0R0402R209 0R0402

R223 33R0402R223 33R0402 R222 33R0402R222 33R0402

2

NB CLOCK INPUT TABLE

NB CLOCKS HT_REFCLKP HT_REFCLKN REFCLK_P REFCLK_N GFX_REFCLK GPP_REFCLK 100M DIFF(OUT) GPPSB_REFCLK 100M DIFF

66M SE(SE)

NC

14M SE (3.3V) 14M SE (1.1V) NC vref

100M DIFF NC 100M DIFF

* RS780 can be used as clock buffer to output two PCIE referecence clocks By deault, chip will configured as input mode, BIOS can program it to output mode.

RS740 RS780

CPU_CLK 7 CPU_CLK# 7

NB_GXF_CLK 15 NB_GXF_CLK# 15

PE16_GXF_CLK 30 PE16_GXF_CLK# 30

NB_SBREF_CLK 15 NB_SBREF_CLK# 15 SB_LINK_CLK 17 SB_LINK_CLK# 17

PE1_GPP_CLK1 30 PE1_GPP_CLK1# 30

LAN_CLK 24 LAN_CLK# 24

NBHTT_CLK 15 NBHTT_CLK# 15

SIO_48M_CLK 25 USB_48M_CLK 18

To CPU

To North Bridge GXF

To PCI-E x16 Slot 100MHz

To North Bridge SB Reference clock To South Bridge Link clock

PCIEx1 Slot-1 GPP

PCIE LAN 100MHz GPP

NB HTT 100M Clock(RS780) NB HTT 66M Clock (RS740)

Super I/O 48MHz Clock USB 48MHz Clock

1- PLACE ALL THE SERIES TERMINATION RESISTORS AS CLOSE AS U6 AS POSSIBLE 2- ROUTE ALL CPUCLK/#, NBSRCCLK/#, GPPCLK/# AS DIFFERENT PAIR RULE 3- PUT DECOUPLING CAPS CLOSE TO U15 POWER PIN 4-Enabled spread spectrum on all high frequency clocks; set to 0.5% down spread, for EMI reasons

100M DIFF 100M DIFF

100M DIFF(IN/OUT)*

Place close to Clock GEN

CPU_CLK CPU_CLK#

SIO_48M_CLK USB_48M_CLK

C780

C5P50N0402

1

C779

X_C5P50N0402

100M DIFF 100M DIFF

C815

X_C5P50N0402

C816

X_C5P50N0402

VCC3_SB

clock generator should not be enable before +1.2v(VCC_1V2 is this design) is ready.

VCC5_SB

R663

4.7KR0402

B

C853

C853 C1U10Y

C1U10Y

4.7KR0402

1.2V_PWRGD_R

CE

Q96

Q96 N-MMBT3904

N-MMBT3904

A A

VCC_1V2

R664 10KR0402R664 10KR0402

5

R665

R665 10KR0402

10KR0402

1.2V_PWRGD CLK_PD#

DS

Q98

G

N-2N7002_SOT23

4

D48

S-RB751V-40_SOD323-RH

REF_0/SEL_HTT66 (Pin51)1 HTT_0/66M_0 & HTT_0#/66M_1 (Pin 46,47)

RS780

0

RS740

3

Configure as differential 100MHz output

Configure as single-ended 66MHz output

2

TP110TP110

TP111TP111

TP112TP112

TP113TP113

MICRO-START INT'L CO.,LTD.

Title

Clock Gen ICS9LPR472

Size Document Number Rev

Custom

Date: Sheet

MICRO-START INT'L CO.,LTD.

VL390 0A

CLK_VDD

CLK_VDDA CLK_VDD48 CLK_VDDREF

1

of

12 37Tuesday, September 09, 2008

5

RS780-HT LINK I/F

4

3

2

1

D D

HT_CADOUT_H0 HT_CADOUT_L0 HT_CADOUT_H1 HT_CADOUT_L1 HT_CADOUT_H2 HT_CADOUT_L2 HT_CADOUT_H3 HT_CADOUT_L3 HT_CADOUT_H4 HT_CADOUT_L4 HT_CADOUT_H5 HT_CADOUT_L5 HT_CADOUT_H6

C C

B B

NB_VCC1P1

1.2V(RS740)

RS740 RS740

HT_CADOUT_L6 HT_CADOUT_H7 HT_CADOUT_L7

HT_CADOUT_H8 HT_CADOUT_L8 HT_CADOUT_H9 HT_CADOUT_L9 HT_CADOUT_H10 HT_CADOUT_L10 HT_CADOUT_H11 HT_CADOUT_L11 HT_CADOUT_H12 HT_CADOUT_L12 HT_CADOUT_H13 HT_CADOUT_L13 HT_CADOUT_H14 HT_CADOUT_L14 HT_CADOUT_H15 HT_CADIN_H15 HT_CADOUT_L15

HT_CLKOUT_H07 HT_CLKOUT_L07 HT_CLKOUT_H17 HT_CLKOUT_L17

HT_CTLOUT_H07 HT_CTLOUT_L07 HT_CTLOUT_H17 HT_CTLOUT_L17

RS780

R197 301R0402R197 301R0402 R196 301R0402R196 301R0402

R436 X_49.9R1%0402R436 X_49.9R1%0402 R443 X_49.9R1%0402R443 X_49.9R1%0402

HT_RXCALP HT_RXCALNHT_RXCALNHT_RXCALN

HT_CADIN_H[15..0]7

HT_CADIN_L[15..0]7 HT_CADOUT_H[15..0]7 HT_CADOUT_L[15..0]7

U14A

Y25

HT_RXCAD0P

Y24

HT_RXCAD0N

V22

HT_RXCAD1P

V23

HT_RXCAD1N

V25

HT_RXCAD2P

V24

HT_RXCAD2N

U24

HT_RXCAD3P

U25

HT_RXCAD3N

T25

HT_RXCAD4P

T24

HT_RXCAD4N

P22

HT_RXCAD5P

P23

HT_RXCAD5N

P25

HT_RXCAD6P

P24

HT_RXCAD6N

N24

HT_RXCAD7P

N25

HT_RXCAD7N

AC24

HT_RXCAD8P

AC25

HT_RXCAD8N

AB25

HT_RXCAD9P

AB24

HT_RXCAD9N

AA24

HT_RXCAD10P

AA25

HT_RXCAD10N

Y22

HT_RXCAD11P

Y23

HT_RXCAD11N

W21

HT_RXCAD12P

W20

HT_RXCAD12N

V21

HT_RXCAD13P

V20

HT_RXCAD13N

U20

HT_RXCAD14P

U21

HT_RXCAD14N

U19

HT_RXCAD15P

U18

HT_RXCAD15N

T22

HT_RXCLK0P

T23

HT_RXCLK0N

AB23

HT_RXCLK1P

AA22

HT_RXCLK1N

M22

HT_RXCTL0P

M23

HT_RXCTL0N

R21

HT_RXCTL1P

R20

HT_RXCTL1N

C23

HT_RXCALP

A24

HT_RXCALN

AMD-215-0674028-A13

HT_CADIN_H[15..0] HT_CADIN_L[15..0] HT_CADOUT_H[15..0] HT_CADOUT_L[15..0]

PART 1 OF 6

HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N

HT_TXCAD8P HT_TXCAD8N HT_TXCAD9P

HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N

HT_TXCLK0P HT_TXCLK0N

HYPER TRANSPORT CPU I/F

HT_TXCLK1P HT_TXCLK1N

HT_TXCTL0P HT_TXCTL0N HT_TXCTL1P HT_TXCTL1N

HT_TXCALP HT_TXCALN

D24 D25 E24 E25 F24 F25 F23 F22 H23 H22 J25 J24 K24 K25 K23 K22

F21 G21 G20 H21 J20 J21 J18 K17 L19 J19 M19 L18 M21 P21 P18 M18

H24 H25 L21 L20

M24 M25 P19 R18

B24 B25

HT_TXCALP HT_TXCALN

HT_CADIN_H0 HT_CADIN_L0 HT_CADIN_H1 HT_CADIN_L1 HT_CADIN_H2 HT_CADIN_L2 HT_CADIN_H3 HT_CADIN_L3 HT_CADIN_H4 HT_CADIN_L4 HT_CADIN_H5 HT_CADIN_L5 HT_CADIN_H6 HT_CADIN_L6 HT_CADIN_H7 HT_CADIN_L7

HT_CADIN_H8 HT_CADIN_L8 HT_CADIN_H9 HT_CADIN_L9 HT_CADIN_H10 HT_CADIN_L10 HT_CADIN_H11 HT_CADIN_L11 HT_CADIN_H12 HT_CADIN_L12 HT_CADIN_H13 HT_CADIN_L13 HT_CADIN_H14 HT_CADIN_L14

HT_CADIN_L15

HT_CLKIN_H0 7 HT_CLKIN_L0 7 HT_CLKIN_H1 7 HT_CLKIN_L1 7

HT_CTLIN_H0 7 HT_CTLIN_L0 7 HT_CTLIN_H1 7 HT_CTLIN_L1 7

U14D

AB12

MEM_A0(NC)

AE16

MEM_A1(NC)

V11

MEM_A2(NC)

AE15

MEM_A3(NC)

AA12

MEM_A4(NC)

AB16

MEM_A5(NC)

AB14

MEM_A6(NC)

AD14

MEM_A7(NC)

AD13

MEM_A8(NC)

AD15

MEM_A9(NC)

AC16

MEM_A10(NC)

AE13

MEM_A11(NC)

AC14

MEM_A12(NC)

Y14

MEM_A13(NC)

AD16

MEM_BA0(NC)

AE17

MEM_BA1(NC)

AD17

MEM_BA2(NC)

W12

MEM_RASb(NC)

Y12

MEM_CASb(NC)

AD18

MEM_WEb(NC)

AB13

MEM_CSb(NC)

AB18

MEM_CKE(NC)

V14

MEM_ODT(NC)

V15

MEM_CKP(NC)

W14

MEM_CKN(NC)

AE12

MEM_COMPP(NC)

AD12

MEM_COMPN(NC)

AMD-215-0674028-A13

PAR 4 OF 6

MEM_DQ0/DVO_VSYNC(NC) MEM_DQ1/DVO_HSYNC(NC)

MEM_DQ2/DVO_DE(NC) MEM_DQ3/DVO_D0(NC)

MEM_DQ4(NC) MEM_DQ5/DVO_D1(NC) MEM_DQ6/DVO_D2(NC) MEM_DQ7/DVO_D4(NC) MEM_DQ8/DVO_D3(NC) MEM_DQ9/DVO_D5(NC)

MEM_DQ10/DVO_D6(NC) MEM_DQ11/DVO_D7(NC)

MEM_DQ12(NC)

MEM_DQ13/DVO_D9(NC) MEM_DQ14/DVO_D10(NC) MEM_DQ15/DVO_D11(NC)

MEM_DQS0P/DVO_IDCKP(NC)

MEM_DQS0N/DVO_IDCKN(NC)

SBD_MEM/DVO_I/F

MEM_DQS1P(NC) MEM_DQS1N(NC)

MEM_DM0(NC)

MEM_DM1/DVO_D8(NC)

IOPLLVDD18(NC)

IOPLLVDD(NC) IOPLLVSS(NC)

MEM_VREF(NC)

AA18 AA20 AA19 Y19 V17 AA17 AA15 Y15 AC20 AD19 AE22 AC18 AB20 AD22 AC22 AD21

Y17 W18 AD20 AE21

W17 AE19

AE23 AE24

AD23 AE18

CP49CP49

1 2 1 2

CP50CP50

+1.8V_S0 NB_VCC1P1

1.2V(RS740)

RX780/RS740/RS780 difference table (HT LINK)

SIGNALS HT_RXCALP HT_RXCALN

A A

Decoupling Cap for HT.

C784

VCC_1V2

C784 X_C0.1U16Y0402

X_C0.1U16Y0402

5

VCCP

HT_TXCALP HT_TXCALN

RS740

49.9R (GND)

49.9R (VDDHT)

100R

4

RS780

301R

MICRO-START INT'L CO.,LTD.

Title

RS780-HT LINK I/F

Size Document Number Rev

B

Date: Sheet

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

VL390 0A

13 37Tuesday, September 09, 2008

of

1

of

A

RS780-PCIE I/F

B

C

D

E

4 4

GFX_RX0P30 GFX_RX0N30 GFX_RX1P30 GFX_RX1N30 GFX_RX2P30 GFX_RX2N30 GFX_RX3P30 GFX_RX3N30 GFX_RX4P30 GFX_RX4N30 GFX_RX5P30 GFX_RX5N30 GFX_RX6P30 GFX_RX6N30 GFX_RX7P30 GFX_RX7N30 GFX_RX8P30 GFX_RX8N30 GFX_RX9P30 GFX_RX9N30

3 3

2 2

GFX_RX10P30 GFX_RX10N30 GFX_RX11P30 GFX_RX11N30 GFX_RX12P30 GFX_RX12N30 GFX_RX13P30 GFX_RX13N30 GFX_RX14P30 GFX_RX14N30 GFX_RX15P30 GFX_RX15N30

GPP_RX0P30 GPP_RX0N30

RX_LANP024 RX_LANN024

A_RX0P17 A_RX0N17 A_RX1P17 A_RX1N17 A_RX2P17 A_RX2N17 A_RX3P17 A_RX3N17

RX_LANP0 RX_LANN0 TX_LANN0

U14B

D4

GFX_RX0P

C4

GFX_RX0N

A3

GFX_RX1P

B3

GFX_RX1N

C2

GFX_RX2P

C1

GFX_RX2N

E5

GFX_RX3P

F5

GFX_RX3N

G5

GFX_RX4P

G6

GFX_RX4N

H5

GFX_RX5P

H6

GFX_RX5N

J6

GFX_RX6P

J5

GFX_RX6N

J7

GFX_RX7P

J8

GFX_RX7N

L5

GFX_RX8P

L6

GFX_RX8N

M8

GFX_RX9P

L8

GFX_RX9N

P7

GFX_RX10P

M7

GFX_RX10N

P5

GFX_RX11P

M5

GFX_RX11N

R8

GFX_RX12P

P8

GFX_RX12N

R6

GFX_RX13P

R5

GFX_RX13N

P4

GFX_RX14P

P3

GFX_RX14N

T4

GFX_RX15P

T3

GFX_RX15N

AE3

GPP_RX0P

AD4

GPP_RX0N

AE2

GPP_RX1P

AD3

GPP_RX1N

AD1

GPP_RX2P

AD2

GPP_RX2N

V5

GPP_RX3P

W6

GPP_RX3N

U5

GPP_RX4P

U6

GPP_RX4N

U8

GPP_RX5P

U7

GPP_RX5N

AA8

SB_RX0P

Y8

SB_RX0N

AA7

SB_RX1P

Y7

SB_RX1N

AA5

SB_RX2P

AA6

SB_RX2N

W5

SB_RX3P

Y5

SB_RX3N

AMD-215-0674028-A13

PART 2 OF 6

PCIE I/F GFX

PCIE I/F GPP

PCIE I/F SB

PCE_CALRP(PCE_BCALRP)

PCE_CALRN(PCE_BCALRN)

GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P

GFX_TX9N GFX_TX10P GFX_TX10N GFX_TX11P GFX_TX11N GFX_TX12P GFX_TX12N GFX_TX13P GFX_TX13N GFX_TX14P GFX_TX14N GFX_TX15P GFX_TX15N

GPP_TX0P

GPP_TX0N

GPP_TX1P

GPP_TX1N

GPP_TX2P

GPP_TX2N

GPP_TX3P

GPP_TX3N

GPP_TX4P

GPP_TX4N

GPP_TX5P

GPP_TX5N

SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N

A5 B5 A4 B4 C3 B2 D1 D2 E2 E1 F4 F3 F1 F2 H4 H3 H1 H2 J2 J1 K4 K3 K1 K2 M4 M3 M1 M2 N2 N1 P1 P2

AC1 AC2 AB4 AB3 AA2 AA1 Y1 Y2 Y4 Y3 V1 V2

AD7 AE7 AE6 AD6 AB6 AC6 AD5 AE5

AC8 AB8

GPP_TX0P GPP_TX0N

TX_LANP0

A_TX0P_C A_TX0N_C A_TX1P_C A_TX1N_C A_TX2P0 A_TX2N0 A_TX3P0 A_TX3N0

GFX_TXC_0P 33 GFX_TXC_0N 33 GFX_TXC_1P 33 GFX_TXC_1N 33 GFX_TXC_2P 33 GFX_TXC_2N 33 GFX_TXC_3P 33 GFX_TXC_3N 33 GFX_TXC_4P 30 GFX_TXC_4N 30 GFX_TXC_5P 30 GFX_TXC_5N 30 GFX_TXC_6P 30 GFX_TXC_6N 30 GFX_TXC_7P 30 GFX_TXC_7N 30 GFX_TXC_8P 30 GFX_TXC_8N 30 GFX_TXC_9P 30 GFX_TXC_9N 30 GFX_TXC_10P 30 GFX_TXC_10N 30 GFX_TXC_11P 30 GFX_TXC_11N 30 GFX_TXC_12P 30 GFX_TXC_12N 30 GFX_TXC_13P 30 GFX_TXC_13N 30 GFX_TXC_14P 30 GFX_TXC_14N 30 GFX_TXC_15P 30 GFX_TXC_15N 30

GPP_TX0P 30 GPP_TX0N 30

C392 C0.1U10X0402C392 C0.1U10X0402 C390 C0.1U10X0402C390 C0.1U10X0402

C365 C0.1U10X0402C365 C0.1U10X0402 C362 C0.1U10X0402C362 C0.1U10X0402 C367 C0.1U10X0402C367 C0.1U10X0402 C375 C0.1U10X0402C375 C0.1U10X0402 C366 C0.1U10X0402C366 C0.1U10X0402 C372 C0.1U10X0402C372 C0.1U10X0402 C384 C0.1U10X0402C384 C0.1U10X0402 C377 C0.1U10X0402C377 C0.1U10X0402

R236 1.27KR1%0402R236 1.27KR1%0402 R243 2KR1%0402R243 2KR1%0402

1.2V (RS740)

TXLANP 24 TXLANN 24

A_TX0P 17 A_TX0N 17 A_TX1P 17 A_TX1N 17 A_TX2P 17 A_TX2N 17 A_TX3P 17 A_TX3N 17

NB_VCC1P1

1.1V(RS780)

RS780/RS740 GPP difference table

RS740 RS780

1 1

A

PCE_CALRP GPP4 GPP5

B

562R (GND) 1.27K (GND) NC NC

GPP4 GPP5

RS780/RS740 GPP Routing table

RS740 RX780/RS780 PCIE1_X1 CONNECTOR PCIE1_X2 CONNECTOR GIGABIT ETHERNET GPP3

C

GPP0

GPP1 GPP1

GPP0

GPP3

MICRO-START INT'L CO.,LTD.

Title

RS780-PCIE I/F

Size Document Number Rev

B

Date: Sheet

D

Date: Sheet

MICRO-START INT'L CO.,LTD.

VL390 0A

14 37Tuesday, September 09, 2008

of

E

of

5

4

3

2

1

RS780-SYSTEM I/F

U14C

RS780 RS780

F12 E12 F14 G15 H15 H14

E17 F17 F15

G18 G17 E18 F18 E19 F19

A11 B11

G14 A12

D14 B12

H17

A10 C10 C12

C25 C24

E11 F11

B10 G11

U14C

AVDD1(NC) AVDD2(NC) AVDDDI(NC) AVSSDI(NC) AVDDQ(NC) AVSSQ(NC)

C_Pr(DFT_GPIO5) Y(DFT_GPIO2) COMP_Pb(DFT_GPIO4)

RED(DFT_GPIO0) REDb(NC) GREEN(DFT_GPIO1) GREENb(NC) BLUE(DFT_GPIO3) BLUEb(NC)

DAC_HSYNC(PWM_GPIO4) DAC_VSYNC(PWM_GPIO6)

E8

DAC_SDA(PCE_TCALRN)

F8

DAC_SCL(PCE_RCALRN) DAC_RSET(PWM_GPIO1) PLLVDD(NC)

PLLVDD18(NC) PLLVSS(NC)

VDDA18HTPLL

D7

VDDA18PCIEPLL1

E7

VDDA18PCIEPLL2

D8

SYSRESETb POWERGOOD LDTSTOPb ALLOW_LDTSTOP

HT_REFCLKP HT_REFCLKN

REFCLK_P/OSCIN(OSCIN) REFCLK_N(PWM_GPIO3)

T2

GFX_REFCLKP

T1

GFX_REFCLKN

U1

GPP_REFCLKP

U2

GPP_REFCLKN

V4

GPPSB_REFCLKP(SB_REFCLKP)

V3

GPPSB_REFCLKN(SB_REFCLKN)

A9

I2C_DATA

B9

I2C_CLK

B8

DDC_DATA/AUX0P(NC)

A8

DDC_CLK/AUX0N(NC)

B7

AUX1P(NC)

A7

AUX1N(NC) STRP_DATA RSVD

C8

AUX_CAL(NC)

AMD-215-0674028-A13

PART 3 OF 6

TXOUT_U1P(PCIE_RESET_GPIO3)

TXOUT_U1N(PCIE_RESET_GPIO2)

TXOUT_U3P(PCIE_RESET_GPIO5)

CRT/TVOUT

TXCLK_UP(PCIE_RESET_GPIO4) TXCLK_UN(PCIE_RESET_GPIO1)

LVTM

PM

LVDS_DIGON(PCE_TCALRP)

LVDS_BLON(PCE_RCALRP)

LVDS_ENA_BL(PWM_GPIO2)

CLOCKs PLL PWR

MIS.

TXOUT_L0P(NC) TXOUT_L0N(NC) TXOUT_L1P(NC) TXOUT_L1N(NC) TXOUT_L2P(NC)

TXOUT_L2N(DBG_GPIO0)

TXOUT_L3P(NC)

TXOUT_L3N(DBG_GPIO2)

TXOUT_U0P(NC) TXOUT_U0N(NC)

TXOUT_U2P(NC) TXOUT_U2N(NC)

TXOUT_U3N(NC)

TXCLK_LP(DBG_GPIO1) TXCLK_LN(DBG_GPIO3)

VDDLTP18(NC)

VDDLT18_1(NC) VDDLT18_2(NC) VDDLT33_1(NC) VDDLT33_2(NC)

TMDS_HPD(NC)

TVCLKIN(PWM_GPIO5)

THERMALDIODE_P THERMALDIODE_N

VSSLTP18(NC)

VSSLT1(VSS) VSSLT2(VSS) VSSLT3(VSS) VSSLT4(VSS) VSSLT5(VSS) VSSLT6(VSS) VSSLT7(VSS)

HPD(NC)

TESTMODE

A22 B22 A21 B21 B20 A20 A19 B19

B18 A18 A17 B17 D20 D21 D18 D19

B16 A16 D16 D17

VDDLTP18

A13 B13

VDDLT18

A15 B15

VDDLT33

A14 B14

C14 D15 C16 C18 C20 E20 C22

E9 F7 G12

D9

R660

D10

X_0R0402

D12

R537 10KR0402R537 10KR0402

AE8 AD8

R219 1.8KR0402R219 1.8KR0402

D13

ONLY single-link DVI is applicable to the RS780L.

RS740/RS780: STRAP_DEBUG_BUS_GPIO_ENABLE

VCC3

Enables the Test Debug Bus using GPIO and/or memory IO 1 : Disable (RS740); Enable (RX780/RS780) 0 : Enable (RS740); Disable(RX780/RS780) RS740: pin DFT_GPIO5 RS780: pin VSYNC

DFT_GPIO[4:2]: STRAP_PCIE_GPP_CFG[2:0]

These pin straps are used to configure PCI-E GPP mode. 111: register defined (register default to Config E) default 110: 4-0-0-0-0 Config A 101: 4-4-0-0-0 Config B 100: 4-2-2-0-0 Config C 011: 4-2-1-1-0 Config D 010: 4-1-1-1-1 Config E others: register defined (default to Config E)

RS740/RS780: LOAD_EEPROM_STRAPS

Selects Loading of STRAPS from EPROM 1 : Bypass the loading of EEPROM straps and use Hardware Default Values 0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected RS740: pin DFT_GPIO1 RS780: pin SUS_STAT#

RS740/RS780: SIDE-PORT MEMORY ENABLE

VCC3

Enables Side port memory

1. Disable (RS740/RS780) 0 : Enable (RS740/RS780) RS740: pin DFT_GPIO0 RS780: pin HSYNC

3

R323

R323 R338

R338

X_1.27KR1%0402

X_1.27KR1%0402 X_1.27KR1%0402

X_1.27KR1%0402

RS740

VDDLTP18

C10u10Y0805

VDDLT18

C0.1U16Y0402

VDDLT33

X_C0.1U16Y0402

COMM_EN 30,33

RS740-DFT_GPIO5

2

C729

C349

C329

RS780 RS780

C344

C729

Button Sdie

C2.2u10Y-RH

RS780RS780

C328

Button Sdie

C4.7U10Y0805

C725

Button Sdie

X_C2.2u10Y-RH

1.2V (RS740)

HPD_DP 33

VCC3

+1.8V_S0

CP17CP17

1 2

L27 X_220L250mA-600-RHL27 X_220L250mA-600-RH

CP7CP7

1 2

L17 X_220L250mA-600-RHL17 X_220L250mA-600-RH

CP13CP13

1 2

L23 X_220L250mA-600-RHL23 X_220L250mA-600-RH

NB_VCC1P1

RS740

L52 X_220L250mA-600-RHL52 X_220L250mA-600-RH

+1.8V_S0

RS780

L38 220L250mA-600-RHL38 220L250mA-600-RH

C735

Button Sdie

C2.2u10Y-RH

NB_RST#_L

C820 X_C180p50N0402C820 X_C180p50N0402

NB_PWRGD

C823 X_C180p50N0402C823 X_C180p50N0402

NB_OSC_14M

R275 X_39.2KR1%0402R275 X_39.2KR1%0402 R283 X_39.2KR1%0402R283 X_39.2KR1%0402 R251 X_10KR0402R251 X_10KR0402

C370 C22P50N0402C370 C22P50N0402

RS740

Title

RS780-SYSTEM I/F

Size Document Number Rev

C

Date: Sheet

Stuff For RS780

N-2N7002_SOT23

RS780;RS740

Q34

Q35

Q35 X_N-2N7002_SOT23

X_N-2N7002_SOT23

D

S

G

RS780;RS740

R214 4.7KR0402R214 4.7KR0402

R213 X_4.7KR0402R213 X_4.7KR0402

G

S

D

VCC3

+1.8V_S0

+12V

Stuff For RS740

Stuff For RS780

VDDA18PCIEPLL

C387

C387 C0.1U16Y0402

C0.1U16Y0402

Stuff For RS740

I2C_CLK I2C_DATA

STRP_DATA

TP139TP139

TP140TP140 TP141TP141

TP142TP142 TP143TP143

VL390 0A

NB_OSC_14M

NB_GXF_CLK NB_GXF_CLK#

NB_SBREF_CLK NB_SBREF_CLK#

MICRO-START INT'L CO.,LTD.

15 37Tuesday, September 09, 2008

1

15 37Tuesday, September 09, 2008

of

VCC3

L31 220L250mA-600-RHL31 220L250mA-600-RH

RS780

+1.8V_S0

D D

+1.8V_S0

C C

CP16CP16

1 2

L26 X_600L350mA-450-RHL26 X_600L350mA-450-RH

RS780

L22 220L250mA-600-RHL22 220L250mA-600-RH

RS780

NB_VCC1P1

L30 220L250mA-600-RHL30 220L250mA-600-RH

RS780

+1.8V_S0

220L250mA-600-RH

220L250mA-600-RH L28

L28

RS780

Button Sdie

C2.2u10Y-RH

+1.8V_S0

L42 220L250mA-600-RHL42 220L250mA-600-RH

RS780 RS780

RS780

RS740/RS780 difference table (Control signal)

NB_PWRGD IN

ALLOW_LDTSTOP OUT(default)/IN

LDT_STOP# IN(default)/OUT SYSTEMRESETb IN

B B

LDT_RST#7,17

PE_NB_RST#17

Patch the timing of SYSRESET# & LDT_RST# & LDT_STOP# (ER_RS780B6)

LDT_STOP#7,17

A A

RS740;RS780 & DDR3 based CPU: Level shifted and pulled up to 3.3V_S0 through a 4.7-k resistor on the Northbridge side

ALLOW_LDTSTOP17

Stuff For RS780

C734

Button Sdie

C2.2u10Y-RH

RS780

C726

Button Sdie

C0.1U16Y0402

RS780

C722

Button Sdie

C2.2u10Y-RH

RS780

C731

Button Sdie

C2.2u10Y-RH

RS780

VDDA18HTPLL

C728

C724

C728 C2.2u10Y-RH

C2.2u10Y-RH

C797

Button Sdie

C2.2u10Y-RH

RS780

RS740

3.3V IN OD OD/3.3V IN

3.3V IN

3.3V IN 3.3V IN

+1.8V_S0

G

RS780

Q48

DS

X_N-FDV301N_SOT23-3-RH

RS780

R570 X_0R0402R570 X_0R0402 R571 0R0402R571 0R0402

+1.8V_S0

G

Q40

DS

N-FDV301N_SOT23-3-RH

+1.8V_S0

R350

R350 1KR0402

1KR0402

ALLOW_LDTSTOP

5

VCC3

AVDD

AVDDDI

AVDDQ

PLLVDD

PLLVDD18

RS780

1.8V IN

3.3V IN/OD

R305

R305 X_4.7KR0402

X_4.7KR0402

RS780

NB_RST#_L

R159

R159 X_100R0402

X_100R0402

R277

4.7KR0402

LDT_STOP_NB#

SWAP

NB_PWRGD6,26

NBHTT_CLK12 NBHTT_CLK#12

NB_OSC_14M12

NB_GXF_CLK12 NB_GXF_CLK#12

NB_SBREF_CLK12 NB_SBREF_CLK#12

HSYNC22 VSYNC22 DAC_SDA22 DAC_SCL22

NB_VCC1P1

DP_AUX_DP33 DP_AUX_DN33

VSYNC

RS740-DFT_GPIO5

RS740_DFT_GPIO2 RS740_DFT_GPIO3 RS740_DFT_GPIO4

RS740_DFT_GPIO1

HSYNC

RS740_DFT_GPIO0

4

HSYNC VSYNC

R244 150R0402R244 150R0402 R238 150R0402R238 150R0402

I2C_DATA I2C_CLK

AVDD AVDDDI AVDDQ

NB_VGA_R22 NB_VGA_G22 NB_VGA_B22

DACSDA DACSCL

RS780

R220 715R1%0402R220 715R1%0402

PLLVDD PLLVDD18

VDDA18HTPLL VDDA18PCIEPLL

NB_RST#_L LDT_STOP_NB#

ALLOW_LDTSTOP

RS740_DFT_GPIO4

RS780 RS780

TP38TP38 TP39TP39

DP_AUX_DP

DP_AUX_DN HPD_DP RS740_DFT_GPIO0 RS740_DFT_GPIO2

STRP_DATA RS740_DFT_GPIO3 RS740_DFT_GPIO1

RS780

R232 3KR0402R232 3KR0402 R230 X_3KR0402R230 X_3KR0402

RS740

R237 X_3KR0402R237 X_3KR0402

R297 X_3KR0402R297 X_3KR0402 R290 X_3KR0402R290 X_3KR0402 R262 X_3KR0402R262 X_3KR0402

RS780

R291 150R1%0402R291 150R1%0402

RS780

R227 3KR0402R227 3KR0402 R225 X_3KR0402R225 X_3KR0402 R292 X_3KR0402R292 X_3KR0402

5

4

3

2

1

RS740/RX780/RS780 POWER DIFFERENCE TABLE

E14

AB11

E15

VSS5

VSS28

VSS29

AB15

J15

VSS6

VSS30

AB17

J12

VSS7

VSS31

AB19

K14

VSS8

VSS32

AE20

M11

VSS9

VSS33

AB21

L15

VSS10

VSS34

K11

PIN NAME VDDHT VDDHTRX VDDHTTX VDDA18PCIE

VDD18_MEM VDDPCIE VDDC VDD_MEM VDD33 IOPLLVDD18

RS740

NC

+1.2V NC +1.8V NC NC +1.2V +1.1V +1.1V +1.2V +1.8V +3.3V +1.8V +1.8VNC

RX780

+1.1V +1.1V +1.2V +1.8V +1.8VVDD18 NC

+1.1V NC NC

+1.8V(DDR2) +1.5V(DDR3)

RS780

+1.1V +1.1V +1.2V +1.8V +1.8V +1.8V

+1.1V

+3.3V

PIN NAME IOPLLVDD

AVDDDI AVDDQ PLLVDD PLLVDD18

VDDA18HTPLL VDDLTP18 VDDLT18 VDDLT33

RS740 RX780 RS780

+1.2V +3.3V NC

+1.2V +1.8V +1.2VVDDA18PCIEPLL +1.8V +1.8V +1.8V +3.3V

NC

+1.1V

+3.3VAVDDNC NC+1.8V +1.8V NC+1.8V +1.8V

+1.1V

+1.8V

NC

+1.8V

+1.8V +1.8V

+1.8V

NC

+1.8V

NC

J4

R7

L1

L2

L4

L7

M6

N4

P6

R1

R2

R4

V7

U4

V8

V6

W1

W2

W4

W7

W8

Y6

AA4

AB5

AB1

AB7

VSSAPCIE30

VSSAPCIE31

VSSAPCIE32

VSSAPCIE33

VSSAPCIE34

VSSAPCIE35

GROUND

VSS12

VSS13

VSS14

VSS15

VSS16

VSS17

P12

P15

N13

R11

R14

M14

AC3

VSSAPCIE36

VSS18

T12

A2

U14F

U14F AMD-215-0674028-A13

AMD-215-0674028-A13

VSSAPCIE1

D D

VSSAPCIE2B1VSSAPCIE3D3VSSAPCIE4D5VSSAPCIE5E4VSSAPCIE6G1VSSAPCIE7G2VSSAPCIE8G4VSSAPCIE9

PART 6/6

VSSAHT1

VSSAHT2

A25

D23

VSSAHT3

VSSAHT4

E22

G22

G24

VSSAHT5

VSSAHT6

VSSAHT7

H19

G25

H7

VSSAHT8

VSSAHT9

J22

L17

L22

VSSAPCIE10

VSSAPCIE11

VSSAPCIE12

VSSAPCIE13

VSSAHT10

VSSAHT11

VSSAHT12

VSSAHT13

L24

L25

N22

M20

VSSAPCIE14

VSSAPCIE15

VSSAPCIE16

VSSAPCIE17

VSSAHT14

VSSAHT15

VSSAHT16

VSSAHT17

P20

R19

R22

R24

VSSAPCIE18

VSSAPCIE19

VSSAPCIE20

VSSAPCIE21

VSSAHT18

VSSAHT19

VSSAHT21

VSSAHT20

V19

R25

U22

H20

VSSAPCIE22

VSSAPCIE23

VSSAPCIE24

VSSAPCIE25

VSSAHT22

VSSAHT23

VSSAHT24

VSSAHT25

Y21

W22

W24

W25

VSSAPCIE26

VSSAPCIE27

VSSAPCIE28

VSSAPCIE29

VSSAHT26

VSSAHT27

VSS11

L12

AD25

AC4

AE1

AE4

AB2

VSSAPCIE37

VSSAPCIE38

VSSAPCIE39

VSSAPCIE40

VSS19

VSS20

VSS21

VSS22

V12

U14

U11

U15

W11

VSS23

VSS24

W15

AE14

VSS1

VSS25

AC12

VSS2

VSS26

AA14

VSS3G8VSS4

VSS27

Y18

D11

NB_VCC1P1

120 MILS WIDTH

C312

C0.1U16Y0402

C303

X_C0.1U16Y0402

C296

C0.1U16Y0402

C360

C0.1U16Y0402

Bottom side

C730

C730 C1U10Y

C1U10Y

4

Bottom side

C721

C0.1U25Y

Bottom side

C720

C0.1U25Y

Bottom side

C719

C0.1U25Y

C733

C0.1U25Y

L16

C C

NB_VCC1P1

L16

RS780

220L2A-50-RH

VDDHTRXNB

C305

C4.7U10Y0805

C301

C0.1U16Y0402

70 MILS WIDTH

C302

C308

C4.7U10Y0805

L14 X_200L400_350_0805L14 X_200L400_350_0805 CP6CP6

1 2

L29

220L2A-50-RH

Y

X

21

C4.7U10Y0805

RS780

C4.7U10Y0805

+1.8V_S0

R143 X_0R0805R143 X_0R0805

/N

R144 0R0805R144 0R0805

Z

Y

/N

D39

BAV99-7-F_SOT23-LF

VCC_1V2

B B

A A

VCC3

+1.8V_S0

X

D38

BAV99-7-F_SOT23-LF

5

Z

C292

C0.1U16Y0402

C350

C4.7U10Y0805

1 2

CP52CP52

C0.1U16Y0402

VDDHTTXNB

C297

X_C0.1U16Y0402

C351

C0.1U16Y0402

VDDG18

15 MILS WIDTH

C304

C0.1U16Y0402

45 MILS WIDTH

C298

C299

C0.1U16Y0402

VDD18NB

20 MILS WIDTH

C352

C353

C0.1U16Y0402

RS780 without Side-port: Connected to GND plane

+1.8V_S0

U14E

J17

VDDHT_1

K16 L16

M16

P16

R16

T16

H18 G19

F20 E21

D22

B23 A23

AE25 AD24 AC23 AB22 AA21

Y20

W19

V18

U17

T17

R17

P17

M17

J10 P10 K10

M10

L10

W9

H9

T10

R10

Y9 AA9 AB9 AD9 AE9 U10

F9

G9 AE11 AD11

VDDC 1.1V@13A VDD18 1.8V@10 mA (Pin G9,F9) VDD33 3.3 V at 60 mA (Pin H11,H12) VDDA18PCIE 1.8 V at 700 mA VDDA18PCIEPLL 1.8 V (RS780/RX780) or 1.2 V (RS740) at 120 mA.(Pin D7,E7) VDDHT 1.1 V at 600 mA VDDHTRX 1.1 V at 700 mA VDDHTTX 1.2 V at 400 mA VDDA18HTPLL 1.8 V at 20 mA (Pin H17) PLLVDD18 1.8 V at 20 mA (Pin D14) Combine with H17 PLLVDD 1.2 V (RS740) or 1.1 V (RS780) at 65 mA (Pin A12) AVDD 3.3 V at 110 mA (Pin E12,F12) AVDDQ 1.8 V at 4 mA (Pin H15) AVDDDI 1.8 V at 20 mA(Pin F14) VDDLT33 3.3 V at 180 mA (Pin A14,B14) RS740 only VDDLT18 1.8 V at 300 mA (Pin A15,B15) VDDLTP18 1.8 V at 15 mA (Pin A13)

PART 5/6

VDDHT_2 VDDHT_3 VDDHT_4 VDDHT_5 VDDHT_6 VDDHT_7

VDDHTRX_1 VDDHTRX_2 VDDHTRX_3 VDDHTRX_4 VDDHTRX_5 VDDHTRX_6 VDDHTRX_7

VDDHTTX_1 VDDHTTX_2 VDDHTTX_3 VDDHTTX_4 VDDHTTX_5 VDDHTTX_6 VDDHTTX_7 VDDHTTX_8 VDDHTTX_9 VDDHTTX_10 VDDHTTX_11 VDDHTTX_12 VDDHTTX_13

VDDA18PCIE_1 VDDA18PCIE_2 VDDA18PCIE_3 VDDA18PCIE_4 VDDA18PCIE_5 VDDA18PCIE_6 VDDA18PCIE_7 VDDA18PCIE_8 VDDA18PCIE_9 VDDA18PCIE_10 VDDA18PCIE_11 VDDA18PCIE_12 VDDA18PCIE_13 VDDA18PCIE_14 VDDA18PCIE_15

VDDG18_1(VDD18_1) VDDG18_2(VDD18_2) VDD18_MEM1(NC) VDD18_MEM2(NC)

AMD-215-0674028-A13

VDDPCIE_1 VDDPCIE_2 VDDPCIE_3 VDDPCIE_4 VDDPCIE_5 VDDPCIE_6 VDDPCIE_7 VDDPCIE_8

VDDPCIE_9 VDDPCIE_10 VDDPCIE_11 VDDPCIE_12 VDDPCIE_13 VDDPCIE_14 VDDPCIE_15 VDDPCIE_16 VDDPCIE_17

VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8

VDDC_9 VDDC_10 VDDC_11

POWER

VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22

VDD_MEM1(NC) VDD_MEM2(NC) VDD_MEM3(NC) VDD_MEM4(NC) VDD_MEM5(NC) VDD_MEM6(NC)

VDDG33_1(NC) VDDG33_2(NC)

3

A6 B6 C6 D6 E6 F6 G7 H8 J9 K9 M9 L9 P9 R9 T9 V9 U9

K12 J14 U16 J11 K15 M12 L14 L11 M13 M15 N12 N14 P11 P13 P14 R12 R15 T11 T15 U12 T14 J16

AE10 AA11 Y11 AD10 AB10 AC10

H11 H12

Bottom side

C736

C0.1U25Y

C0.1U16Y0402

Bottom side

C727

C0.1U25Y

C0.1U16Y0402

RS780 without Side-port: Connected to GND plane

Bottom side

15 MILS WIDTH

C732

C732 C0.1U16Y0402

C0.1U16Y0402

300 MILS WIDTH

C393

C389

C1U10Y

300 MILS WIDTH

C311

C309

C0.1U16Y0402

RS780

C391

C391 C0.1U16Y0402

C0.1U16Y0402

C394

C1U10Y

C317

C0.1U16Y0402

VCC3

2

NB_VDDPCIE

C395

C4.7U10Y0805

C310

C316

C0.1U16Y0402

Title

Size Document Number Rev

Custom

Date: Sheet

1 2

C315

C0.1U16Y0402

C10u10Y0805

TP107TP107

TP108TP108

TP109TP109

RX780-POWER

VL390 0A

NB_VDDPCIE

L39

X_30L3_15_0805

21

CP21CP21

NB_VCC1P1

C306

C307

C10u10Y0805

VDDHTRXNB

VDDHTTXNB VDD18NB

MICRO-START INT'L CO.,LTD.

of

16 37Tuesday, September 09, 2008

1

A

B

C

D

E

PE_LAN_RST#24 PE_GF_RST#30 PE_NB_RST#15

4 4

3 3

2 2

1 1

PE_LAN_RST# PE_GF_RST# PE_NB_RST#

Reserve cystal for A14 to solve the system time lag issue; Also can connect the 14M from clock gen to 14M_X1 and leace 14M_X2 NC, 1.2V level shift may needed

C817 X_C22P50N0402C817 X_C22P50N0402

X_14.318MHZ16P_D

C818 X_C22P50N0402C818 X_C22P50N0402

32.768KHZ12.5P_D-1

R400 20MRR400 20MR

C541

C18p50N0402

PLACE THESE COMPONENTS CLOSE TO U600, AND USE GROUND GUARD FOR 32K_X1 AND 32K_X2

Y6

4

3

Y5

12

A

R593 33R0402R593 33R0402 R587 33R0402R587 33R0402 R441 33R0402R441 33R0402

A_RX0P14 A_RX0N14 A_RX1P14 A_RX1N14 A_RX2P14 A_RX2N14 A_RX3P14 A_RX3N14

A_TX0P14 A_TX0N14 A_TX1P14 A_TX1N14 A_TX2P14 A_TX2N14 A_TX3P14 A_TX3N14

VCC_SB_1V2

SB_OSC_14M12

R572

R572 X_10MR0402

X_10MR0402

1 2

32K_X1

32K_X2

C540

C18p50N0402

PCIE_VDDR

L40

L40 220L250mA-600-RH

220L250mA-600-RH

SB_LINK_CLK12 SB_LINK_CLK#12

14M_X2

R594 0R0402R594 0R0402

C467 C0.1U10X0402C467 C0.1U10X0402 C468 C0.1U10X0402C468 C0.1U10X0402 C465 C0.1U10X0402C465 C0.1U10X0402 C466 C0.1U10X0402C466 C0.1U10X0402 C464 C0.1U10X0402C464 C0.1U10X0402 C463 C0.1U10X0402C463 C0.1U10X0402 C412 C0.1U10X0402C412 C0.1U10X0402 C413 C0.1U10X0402C413 C0.1U10X0402

PE_PVDD

C2.2u10Y-RH

R659 X_0R0402R659 X_0R0402 R658 X_0R0402R658 X_0R0402

ALLOW_LDTSTOP15 CPU_PROCHOT#7

Note: LDT_PG, LDT_STP# & LDT_RST# are OD and require a PU to the CPU I/O rail. They are also in the S5 domain to prevent glitching at power up.

ARST#A_RST#

A_RX0P_C A_RX0N_C A_RX1P_C A_RX1N_C A_RX2P_C A_RX2N_C A_RX3P_C A_RX3N_C

R345 562R1%0402R345 562R1%0402 R344 2.05KR1%0402R344 2.05KR1%0402

C407

LDT_PWRGD6,7 LDT_STOP#7,15 LDT_RST#7,15

TP33TP33 TP32TP32

C410

C410 X_C0.1U16Y0402

X_C0.1U16Y0402

SB_14M14M_X1

14M_X2

32K_X1

32K_X2

40mA

N2

V23 V22 V24 V25 U25 U24

T23 T22

U22 U21 U19 V19 R20 R21 R18 R17

T25

T24 P24 P25

N25 N24

K23 K22

M24 M25

P17 M18

M23 M22

J19

J18

L20

L19 M19

M20 N22

P22

L18

J21

J20

A3

B3

F23

F24

F22 G25 G24

U23A

A_RST# PCIE_TX0P

PCIE_TX0N PCIE_TX1P PCIE_TX1N PCIE_TX2P PCIE_TX2N PCIE_TX3P PCIE_TX3N

PCIE_RX0P PCIE_RX0N PCIE_RX1P PCIE_RX1N PCIE_RX2P PCIE_RX2N PCIE_RX3P PCIE_RX3N

PCIE_CALRP PCIE_CALRN

PCIE_PVDD PCIE_PVSS

PCIE_RCLKP/NB_LNK_CLKP PCIE_RCLKN/NB_LNK_CLKN

NB_DISP_CLKP NB_DISP_CLKN

NB_HT_CLKP NB_HT_CLKN

CPU_HT_CLKP CPU_HT_CLKN

SLT_GFX_CLKP SLT_GFX_CLKN

GPP_CLK0P GPP_CLK0N

GPP_CLK1P GPP_CLK1N

GPP_CLK2P GPP_CLK2N

GPP_CLK3P GPP_CLK3N

25M_48M_66M_OSC

25M_X1

25M_X2

X1

X2

ALLOW_LDTSTP PROCHOT# LDT_PG LDT_STP# LDT_RST#

AMD-218S7EBLA12FG-A12-RH

B

Part 1 of 5

RTC XTAL

CPU

SB700

PCI EXPRESS INTERFACE

CLOCK GENERATOR

LPC

BMREQ#/REQ5#/GPIO65

RTC

PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4

PCICLK5/GPIO41

PCI CLKS

PCIRST#

CBE0# CBE1# CBE2# CBE3#

PCI INTERFACE

FRAME#

DEVSEL#

IRDY#

TRDY# STOP#

PERR# SERR# REQ0# REQ1#

REQ2# REQ3#/GPIO70 REQ4#/GPIO71

GNT0#

GNT1#

GNT2# GNT3#/GPIO72 GNT4#/GPIO73

CLKRUN#

LOCK#

INTE#/GPIO33

INTF#/GPIO34 INTG#/GPIO35 INTH#/GPIO36

LPCCLK0 LPCCLK1

LFRAME#

LDRQ0#

LDRQ1#/GNT5#/GPIO68

SERIRQ

RTCCLK

INTRUDER_ALERT#

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8

AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

PAR

LAD0 LAD1 LAD2 LAD3

VBAT

Place close to South Bridge

PCI_CLK0_R

P4 P3 P1 P2 T4 T3

SB_PCIRST#

N1

U2 P7 V4 T1 V3 U1 V1 V2 T2 W1 T9 R6 R7 R5 U8 U5 Y7 W8 V9 Y8 AA8 Y4 Y3 Y2 AA2 AB4 AA1 AB3 AB2 AC1 AC2 AD1 W2 U7 AA7 Y1 AA6 W5 AA5 Y5 U6 W6 W4 V7 AC3 AD4 AB7 AE6 AB6 AD2

PGNT#1

AE4

PGNT#2

AD5

PGNT#3

AC6

PGNT#4

AE5 AD6 V5

AD3 AC4 AE2 AE3

G22 E22 H24 H23 J25 J24 H25 H22 AB8 AD7 V15

SB700 has an internal 15k PU

C3 C2 B2

R440 22R0402R440 22R0402

PCI_CLK1_R

R446 22R0402R446 22R0402

PCI_CLK2_R PCI_CLK2

R478 22R0402R478 22R0402 R426 22R0402R426 22R0402

PCI_CLK4_R

R438 22R0402R438 22R0402

PCI_CLK5_R PCI_CLK5

R491 22R0402R491 22R0402

Place close to South Bridge

R657 0R0402R657 0R0402

TP42TP42 TP43TP43 TP21TP21

TP29TP29 TP37TP37 TP17TP17

C380

C380 C1U10Y

C1U10Y

AD[31..0]

C_BE#[3..0]

TP54TP54 TP56TP56

TP36TP36

C383

C383 C0.1U16Y0402

C0.1U16Y0402

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C_BE#0 C_BE#1 C_BE#2 C_BE#3

LPC_CLK0 LPC_CLK1

LDRQ#1

RTCCLK

INTRUDER_ALERT#

Put C308 & C383 Close to B2 pin

C

PCI_CLK0 PCI_CLK1

SIO_PCLKSIO_PCLK_R PCI_CLK4

PREQ#0 31 PREQ#1 31

PCI_INTA# 31 PCI_INTB# 31 PCI_INTC# 31 PCI_INTD# 31

LPC_CLK0 21

LPC_CLK1 21 LPC_AD0 25,32 LPC_AD1 25,32 LPC_AD2 25,32 LPC_AD3 25,32

LPC_DRQ#0 25

PCI_CLK0 31 PCI_CLK1 31 PCI_CLK2 21 SIO_PCLK 21,25 PCI_CLK4 21,32 PCI_CLK5 21

PCIRST#

AD[31..0] 31

C_BE#[3..0] 31

FRAME# 31 DEVSEL# 31 IRDY# 31 TRDY# 31 PAR 31 STOP# 31 PERR# 31 SERR# 31

PGNT#0 31 PGNT#1 31

PCI_CLKRUN# 32

LOCK# 31

LPC_FRAME# 25,32

SERIRQ 25,32

VBAT_IN

R303 510R0402R303 510R0402

PCICLK5/GPIO41 power up default A11:PCICLK5 A12:GPIO41

R425 33R0402R425 33R0402 R430 33R0402R430 33R0402 R456 33R0402R456 33R0402

BAT1

BAT-2P-RH-1

PCIRST_SLOT1# 31 PCIRST_SIO# 25 PCIRST_TPM# 32

Modify 0829

SB_PCIRST#

D

Chasiss Intrusion

VBAT_IN

JCI1

Chasiss

R416 1MR0402R416 1MR0402

N32-1020391-A10 CO-LAY N31-1020011-C09

R519 0R0402R519 0R0402 R517 X_1MR0402R517 X_1MR0402

Internal 50K PU

6

Y1

5

VCC

4

Y2

C569 C22P50N0402C569 C22P50N0402

C555 C22P50N0402C555 C22P50N0402

Chasiss

VCC3

R672

X_4.7KR0402

VBAT_IN

R673

X_4.7KR0402

A_RST#ARST#

PCIRST#

_BH1X2_white-3.5mm-RH

INTRUDER_ALERT#

U32

1

A1

2

GND

3

A2

X_NC7WZ07P6X_SC70-6

PCI_CLK0

SIO_PCLK

1 2

Place close to device

For EMI

TP114TP114

TP144TP144

MICRO-START INT'L CO.,LTD.

Title

SB700 PCIE/PCI/CPU/LPC

Size Document Number Rev

Custom

Date: Sheet

MICRO-START INT'L CO.,LTD.

VL390 0A

VBAT_IN

SB_14M

of

17 37Tuesday, September 09, 2008

E

17 37Tuesday, September 09, 2008

A

B

C

D

E

R418,R422,R212,R565,R655 may be removed

KBRST# SDATA_IN_R SCLK

AZ_SDOUT28 AZ_BIT_CLK28

AZ_SYNC28

AZ_SDIN28

AZ_RST#21,28

SB_TEST2 SB_TEST1 SB_TEST0

SDATA SUS_STAT# CPU_THRIP# LC_SENSE

SCLK1 SDATA1 RSMRST# RI# SUS_STAT# SB_PWRON# LPC_SMI#

SB_GPIO5

SB_PWRGD

SCLK SDATA

SCLK1 SDATA1

AZ_BIT_CLK

VCC3_SB

VCC3_SB VCC3_SB VCC3_SB

4 4

3 3

2 2

1 1

R382 1KR0402R382 1KR0402 R428 10KR0402R428 10KR0402 R375 2.2KR0402R375 2.2KR0402 R374 2.2KR0402R374 2.2KR0402 R565 X_10KR0402R565 X_10KR0402 R212 4.7KR0402R212 4.7KR0402 R469 X_10KR0402R469 X_10KR0402

R427 2.2KR0402R427 2.2KR0402 R439 2.2KR0402R439 2.2KR0402 R413 10KR0402R413 10KR0402 R418 10KR0402R418 10KR0402 R412 0R0402R412 0R0402 R424 10KR0402R424 10KR0402 R422 1KR0402R422 1KR0402 R655 X_10KR0402R655 X_10KR0402

R377 10KR0402R377 10KR0402

C825 X_C180p50N0402C825 X_C180p50N0402

C484 X_C22P50N0402C484 X_C22P50N0402 C483 X_C22P50N0402C483 X_C22P50N0402

C584 X_C22P50N0402C584 X_C22P50N0402 C573 X_C22P50N0402C573 X_C22P50N0402

C585 X_C22P50N0402C585 X_C22P50N0402

RN33 8P4R-22R0402RN33 8P4R-22R0402

1

2

3

4

5

6

7

8

R429 22R0402R429 22R0402

RN11 8P4R-10KR0402RN11 8P4R-10KR0402

1

2

3

4

5

6

7

8

R574 10KR0402R574 10KR0402 R591 10KR0402R591 10KR0402

R419

R444

X_2.2KR0402

R437

X_10KR0402

R419

X_2.2KR0402

R417

X_10KR0402

A

VCC3

VCC3_SB

AZ_SDATA_OUT_R AZ_BITCLK_R AZ_SYNC_R SDATA_IN_R AZ_RST_R

OC#1 OC#2 OC#3 OC#4

OC#5 OC#6

R420

X_2.2KR0402

R421

X_10KR0402

PCI_PME#31

GFX16_PCIERST#30

SLP_S3#25,26

SLP_S5#26,27 SB_PWRON#25 SB_PWRGD26

A20GATE25

KBRST#25

LPC_PME#25 LPC_SMI#25

S3_STATE27

FP_RST#12,26,34

NB_PWRGD A12 Open Drain A11 Push pull

RSMRST# not de-asserted until at least 10 ms after S5_3.3V is valid. RSMRST# ramp up time (10% to 90%) 50 ms

WAKE#24,30

CPU_THRIP#7

WD_PWRGD26

IO_RSMRST#25

≒

CPU_PRESENT#7

SPKR34

SCLK10,11,12,26 SDATA10,11,12,26 SCLK124,30,31,32 SDATA124,30,31,32

SPI_WP#19

OC#529 OC#429 OC#329 OC#229 OC#129

B

RI#

SB_PWRON# SUS_STAT#

SB_TEST2 SB_TEST1 SB_TEST0 A20GATE KBRST#

LPC_SMI# S3_STATE

CPU_THRIP# WD_PWRGD

IO_RSMRST# RSMRST#

C547 X_C1000P50X0402C547 X_C1000P50X0402

R522 0R0402R522 0R0402

SCLK SDATA SCLK1 SDATA1

LC_SENSE SB_GPIO5

OC#6

TP34TP34

AZ_BITCLK_R AZ_SDATA_OUT_R SDATA_IN_R

AZ_SYNC_R AZ_RST_R

U23D

E1

PCI_PME#/GEVENT4#

E2

RI#/EXTEVNT0#

H7

SLP_S2/GPM9#

F5

SLP_S3#

G1

SLP_S5#

H2

PWR_BTN#

H1

PWR_GOOD

K3

SUS_STAT#

H5

TEST2

H4

TEST1

H3

TEST0

Y15

GA20IN/GEVENT0#

W15

KBRST#/GEVENT1#

K4

LPC_PME#/GEVENT3#

K24

LPC_SMI#/EXTEVNT1#

F1

S3_STATE/GEVENT5#

J2

SYS_RESET#/GPM7#

H6

WAKE#/GEVENT8#

F2

BLINK/GPM6#

J6

SMBALERT#/THRMTRIP#/GEVENT2#

W14

NB_PWRGD

D3

RSMRST#

AE18

SATA_IS0#/GPIO10

AD18

CLK_REQ3#/SATA_IS1#/GPIO6

AA19

SMARTVOLT/SATA_IS2#/GPIO4

W17

CLK_REQ0#/SATA_IS3#/GPIO0

V17

CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39

W20

CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40

W21

SPKR/GPIO2

AA18

SCL0/GPOC0#

W18

SDA0/GPOC1#

K1

SCL1/GPOC2#

K2

SDA1/GPOC3#

AA20

DDC1_SCL/GPIO9

Y18

DDC1_SDA/GPIO8

C1

LLB#/GPIO66

Y19

SHUTDOWN#/GPIO5

G5

DDR3_RST#/GEVENT7#

B9

USB_OC6#/IR_TX1/GEVENT6#

B8

USB_OC5#/IR_TX0/GPM5#

A8

USB_OC4#/IR_RX0/GPM4#

A9

USB_OC3#/IR_RX1/GPM3#

E5

USB_OC2#/GPM2#

F8

USB_OC1#/GPM1#

E4

USB_OC0#/GPM0#

M1

AZ_BITCLK

M2

AZ_SDOUT

J7

AZ_SDIN0/GPIO42

J8

AZ_SDIN1/GPIO43

L8

AZ_SDIN2/GPIO44

M3

AZ_SDIN3/GPIO46

L6

AZ_SYNC

M4

AZ_RST#

L5

AZ_DOCK_RST#/GPM8#

H19

PS2_DAT/EC_GPIO0

H20

PS2_CLK/EC_GPIO1

H21

SPI_CS2#/EC_GPIO2

F25

IDE_RST#/F_RST#/EC_GPO3

D22

PS2KB_DAT/EC_GPIO4

E24

PS2KB_CLK/EC_GPIO5

E25

PS2M_DAT/EC_GPIO6

D23

PS2M_CLK/EC_GPIO7

AMD-218S7EBLA12FG-A12-RH

C

SB700

ACPI / WAKE UP EVENTS

USB OC

HD AUDIO

EMBEDDED CTRL

Part 4 of 5

USBCLK/14M_25M_48M_OSC

USB_RCOMP

USB MISC

USB_FSDP13+ USB_FSDM13-

USB_FSDP12+ USB_FSDM12-

USB 1.1

USB_HSDP11+ USB_HSDM11-

USB_HSDP10+ USB_HSDM10-

USB_HSDP9+ USB_HSDM9-

USB_HSDP8+ USB_HSDM8-

USB_HSDP7+ USB_HSDM7-

USB_HSDP6+ USB_HSDM6-

USB_HSDP5+ USB_HSDM5-

USB_HSDP4+

USB 2.0

USB_HSDM4-

GPIO

USB_HSDP3+ USB_HSDM3-

USB_HSDP2+ USB_HSDM2-

USB_HSDP1+ USB_HSDM1-

USB_HSDP0+ USB_HSDM0-

KSO_16/EC_GPIO8 KSO_17/EC_GPIO9

EC_PWM0/EC_GPIO10

SCL2/EC_GPIO11

SDA2/EC_GPIO12 SCL3_LV/EC_GPIO13 SDA3_LV/EC_GPIO14

EC_PWM1/EC_GPIO15

EC_PWM2/EC_GPO16 EC_PWM3/EC_GPO17

KSI_0/EC_GPIO18

KSI_1/EC_GPIO19

KSI_2/EC_GPIO20

KSI_3/EC_GPIO21

KSI_4/EC_GPIO22

KSI_5/EC_GPIO23

KSI_6/EC_GPIO24

KSI_7/EC_GPIO25

KSO_0/EC_GPIO26 KSO_1/EC_GPIO27 KSO_2/EC_GPIO28 KSO_3/EC_GPIO29 KSO_4/EC_GPIO30 KSO_5/EC_GPIO31 KSO_6/EC_GPIO32 KSO_7/EC_GPIO33 KSO_8/EC_GPIO34 KSO_9/EC_GPIO35

KSO_10/EC_GPIO36

EMBEDDED CTRL

KSO_11/EC_GPIO37 KSO_12/EC_GPIO38 KSO_13/EC_GPIO39 KSO_14/EC_GPIO40 KSO_15/EC_GPIO41

C8 G8

E6 E7

F7 E8

H11 J10

E11 F11

A11 B11

C10 D10

G11 H12

E12 E14

C12 D12

B12 A12

G12 G14

H14 H15

A13 B13

B14 A14

A18 B18 F21 D21 F19 E20 E21 E19 D19 E18

G20 G21 D25 D24 C25 C24 B25 C23

B24 B23 A23 C22 A22 B22 B21 A21 D20 C20 A20 B20 B19 A19 D18 C18

USB_48M_CLK USB_RCOMP

GPIO8

STRAP pin to define use LPC or SPI ROM

USB_48M_CLK 12

R409 11.8KR1%0402R409 11.8KR1%0402

USB9+ 29 USB9- 29

USB8+ 29 USB8- 29

USB7+ 29 USB7- 29

USB6+ 29 USB6- 29

USB5+ 29 USB5- 29

USB4+ 29 USB4- 29

USB3+ 29 USB3- 29

USB2+ 29 USB2- 29

USB1+ 29 USB1- 29

USB0+ 29 USB0- 29

ISOLATEBR 24

SB_GP16 21 SB_GP17 21

D

USB_48M_CLK

C536

C22P50N0402

Place close to SB

USB9 FRONT PANEL USB8 FRONT PANEL USB7 FRONT PANEL USB6 FRONT PANEL USB5 STACK4 USB4 USB4 STACK4 USB3 USB3 STACK4 USB2 USB2 STACK4 USB1 USB1 LAN USB BOTTOM USB0 LAN USB TOP

R360

10KR0402

VCC3_SB

R367

R367 10KR0402

10KR0402

X_10KR0402

GPIO8

R361

VCC3

R941

X_0R0402

Add 0902

TP145TP145

MICRO-START INT'L CO.,LTD.

Title

SB700 ACPI/GPIO/USB/AUDIO

Size Document Number Rev

Custom

Date: Sheet

MICRO-START INT'L CO.,LTD.

VL390 0A

USB_48M_CLK

E

DSM_GPO# 24

18 37Tuesday, September 09, 2008

of

5

A

4

3

2

1

U23B

D D

SATA_LED#34

PLLVDD_SATA XTLVDD_SATA

SATA_TX0+ SATA_TX0-

SATA_RX0SATA_RX0+

SATA_TX1+ SATA_TX1-

SATA_RX1SATA_RX1+

SATA_TX2+ SATA_TX2-

SATA_RX2SATA_RX2+

SATA_TX3+ SATA_TX3-

SATA_RX3SATA_RX3+

SATA_TX4+ SATA_TX4-

SATA_RX4SATA_RX4+

SATA_CAL SATA_X1 SATA_X2 SATA_LED#

SATA_TX0+23 SATA_TX0-23

SATA_RX0-23 SATA_RX0+23

SATA_TX1+23 SATA_TX1-23

SATA_RX1-23 SATA_RX1+23

SATA_TX2+23 SATA_TX2-23

SATA_RX2-23 SATA_RX2+23

SATA_TX3+23 SATA_TX3-23

SATA_RX3-23 SATA_RX3+23

SATA_TX4+23 SATA_TX4-23

SATA_RX4-23

C C

SATA_RX4+23

Add ESATA 0901

R392 1KR1%0402R392 1KR1%0402

B B

U23B

AD9

SATA_TX0+

AE9

SATA_TX0-

AB10

SATA_RX0-

AC10

SATA_RX0+

AE10

SATA_TX1+

AD10

SATA_TX1-

AD11

SATA_RX1-

AE11

SATA_RX1+

AB12

SATA_TX2+

AC12

SATA_TX2-

AE12

SATA_RX2-

AD12

SATA_RX2+

AD13

SATA_TX3+

AE13

SATA_TX3-

AB14

SATA_RX3-

AC14

SATA_RX3+

AE14

SATA_TX4+

AD14

SATA_TX4-

AD15

SATA_RX4-

AE15

SATA_RX4+

AB16

SATA_TX5+

AC16

SATA_TX5-

AE16

SATA_RX5-

AD16

SATA_RX5+

V12

SATA_CAL

Y12

SATA_X1

AA12

SATA_X2

W11

SATA_ACT#/GPIO67

AA11

PLLVDD_SATA_1

W12

XTLVDD_SATA

AMD-218S7EBLA12FG-A12-RH

SB700

Part 2 of 5

SATA PWR SERIAL ATA

HW MONITOR

IDE_IORDY

IDE_IRQ

IDE_A0 IDE_A1 IDE_A2

IDE_DACK#

IDE_DRQ

IDE_IOR# IDE_IOW# IDE_CS1# IDE_CS3#

IDE_D0/GPIO15 IDE_D1/GPIO16 IDE_D2/GPIO17 IDE_D3/GPIO18 IDE_D4/GPIO19 IDE_D5/GPIO20 IDE_D6/GPIO21 IDE_D7/GPIO22 IDE_D8/GPIO23

ATA 66/100/133

IDE_D9/GPIO24 IDE_D10/GPIO25 IDE_D11/GPIO26 IDE_D12/GPIO27 IDE_D13/GPIO28 IDE_D14/GPIO29 IDE_D15/GPIO30

SPI_DI/GPIO12

SPI_DO/GPIO11

SPI_CLK/GPIO47

SPI_HOLD#/GPIO31

SPI_CS#/GPIO32

LAN_RST#/GPIO13

SPI ROM

ROM_RST#/GPIO14

FANOUT0/GPIO3

FANOUT1/GPIO48 FANOUT2/GPIO49

FANIN0/GPIO50

FANIN1/GPIO51

FANIN2/GPIO52

TEMP_COMM TEMPIN0/GPIO61 TEMPIN1/GPIO62 TEMPIN2/GPIO63

TEMPIN3/TALERT#/GPIO64

VIN0/GPIO53 VIN1/GPIO54 VIN2/GPIO55 VIN3/GPIO56 VIN4/GPIO57 VIN5/GPIO58 VIN6/GPIO59 VIN7/GPIO60

AVDD AVSS

AA24 AA25 Y22 AB23 Y23 AB24 AD25 AC25 AC24 Y25 Y24

AD24 AD23 AE22 AC22 AD21 AE20 AB20 AD19 AE19 AC20 AD20 AE21 AB22 AD22 AE23 AC23

G6 D2 D1 F4 F3

U15 J1

M8 M5 M7

P5 P8 R8

C6 B6 A6 A5 B5

A4 B4 C4 D4 D5 D6 A7 B7

F6 G7

SPI_DATAIN SPI_DATAOUT SPI_CLK SPI_HOLD_L SPI_CS#

R566 X_0R0402R566 X_0R0402 R403 10KR0402R403 10KR0402

CLR_COMS

AVDD_HWM

C550

C550 X_C2.2u10Y-RH

X_C2.2u10Y-RH

NS_VIA CONNECTS HWM_AGND TO GND

TP44TP44

TALERT# 7

VCC3_SB

X_30L3_15_0805

X_30L3_15_0805 L49

L49 CP36 X_CPCP36 X_CP

C553

C553 C0.1U16Y0402

C0.1U16Y0402

SPI_CS#

SPI_WP#18

21

VCC3_SB

SPI_DATAIN

VCC3_SB VCC3_SB

R390

R386

1KR0402

R388

R388 0R0402

0R0402

R390 10KR0402

10KR0402

1 2

SPI_WP SPI_CLK

3 4

SPI_CS# SPI_DATAOUT SPI_WP

VCC3

R394

R394 10KR0402

10KR0402

CLR_COMS1

CLR_COMS

1 2 3

N31-1030151+N33-1020271-RH

U22

CS#

VCC

DO

HOLD#

WP#

CLK

GND

DIO

W25X16AVSSIG-RH

16M

JSPI1

1 2 3 4

6

5 7 8

H2X4M_BLACK-RH

CMOS CLEAR JUMPER CLR_COMS Clear CMOS

R364

R364 10KR0402

10KR0402

8

SPI_HOLD#

7 6

SPI_DATAOUT

5

VCC3_SB

SPI_HOLD# SPI_CLK SPI_DATAIN

Normal

1 - 2 2 - 3 Clear CMOS

C487

C0.1U16Y0402

R358 X_0R0402R358 X_0R0402

C574

C574 C10u10Y0805

C10u10Y0805

SPI_HOLD_L

SATA_X1

R391

10MR0402

SATA_X2

5

C526 C10P50N0402C526 C10P50N0402

12

Y3

Y3 25MHZ18P_D-4

25MHZ18P_D-4

C502 C10P50N0402C502 C10P50N0402

VCC_SB_1V2

L47

L47 220L250mA-600-RH

220L250mA-600-RH

4

C527

C2.2u10Y-RH

C530

C530 X_C0.1U16Y0402

X_C0.1U16Y0402

3

L46

L46 220L250mA-600-RH

220L250mA-600-RH

XTLVDD_SATAVCC3PLLVDD_SATA

A

C520

C520 C1U10Y

C1U10Y

MICRO-START INT'L CO.,LTD.

Title

SB600 SATA/IDE/HWM/SPI

Size Document Number Rev

Custom

Date: Sheet

2

MICRO-START INT'L CO.,LTD.

VL390 0A

19 37Tuesday, September 09, 2008

of

1

5

VCC3

C511

C451

C22u6.3X1206

D D

C C

B B

C22u6.3X1206

VCC_SB_1V2

L58 220L250mA-600-RHL58 220L250mA-600-RH

VCC_SB_1V2

L57 220L250mA-600-RHL57 220L250mA-600-RH

VCC3_SB

L55 220L2A-50-RHL55 220L2A-50-RH

C4.7U10Y0805

C543

X_C1U10Y

VCC3

IDE Interface Not Implemented: Decoupling caps not used.

C411

C489

C22u6.3X1206

C519

C10u10Y0805

C461

X_C1U10Y

CP48CP48

C450

X_C1U10Y

C1U10Y

C474

C1U10Y

50 MILS WIDTH

C518

C1U10Y

C511

C566

C0.1U16Y0402

C1U10Y

100 MILS WIDTH

C457

C408

C0.1U16Y0402

50 MILS WIDTH

C538

C746

C0.1U16Y0402

C516

C773

C1U10Y

X_C1U10Y

4

C567

C568

C0.1U16Y0402

50 MILS WIDTH

C471

C744

C0.1U16Y0402

X_C0.1U16Y0402

C740

C0.1U16Y0402

AVDDSATA_SB

C537

C0.1U16Y0402

AVDDTX_SB

C515

C517

X_C0.1U16Y0402

C462

PCIE_VDDR

U23C

L9

VDDQ_1

M9

VDDQ_2

T15

VDDQ_3

U9

VDDQ_4

U16

VDDQ_5

U17

VDDQ_6

V8

VDDQ_7

W7

VDDQ_8

Y6

VDDQ_9

AA4

VDDQ_10

AB5

VDDQ_11

AB21

VDDQ_12

Y20

VDD33_18_1

AA21

VDD33_18_2

AA22

VDD33_18_3

AE25

VDD33_18_4

P18

PCIE_VDDR_1

P19

PCIE_VDDR_2

P20

PCIE_VDDR_3

P21

PCIE_VDDR_4

R22

PCIE_VDDR_5

R24

PCIE_VDDR_6

R25

PCIE_VDDR_7

AA14

AVDD_SATA_1

AB18

AVDD_SATA_4

AA15

AVDD_SATA_2

AA17

AVDD_SATA_3

AC18

AVDD_SATA_5

AD17

AVDD_SATA_6

AE17

AVDD_SATA_7

A16

AVDDTX_0

B16

AVDDTX_1

C16

AVDDTX_2

D16

AVDDTX_3

D17

AVDDTX_4

E17

AVDDTX_5

F15

AVDDRX_0

F17

AVDDRX_1

F18

AVDDRX_2

G15

AVDDRX_3

G17

AVDDRX_4

G18

AVDDRX_5

AMD-218S7EBLA12FG-A12-RH

SB700

Part 3 of 5

PCI/GPIO I/O

IDE/FLSH I/O

POWER

A-LINK I/O

3.3V_S5 I/OCORE S5

SATA I/O

USB_PHY_1.2V_1 USB_PHY_1.2V_2

PLL CLKGEN I/O

USB I/O

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8

CORE S0

VDD_9

CKVDD_1.2V_1 CKVDD_1.2V_2 CKVDD_1.2V_3 CKVDD_1.2V_4

S5_3.3V_1 S5_3.3V_2 S5_3.3V_3 S5_3.3V_4 S5_3.3V_5 S5_3.3V_6 S5_3.3V_7

S5_1.2V_1 S5_1.2V_2

V5_VREF AVDDCK_3.3V AVDDCK_1.2V

AVDDC

3

L15 M12 M14 N13 P12 P14 R11 R15 T16

L21 L22 L24 L25

A17 A24 B17 J4 J5 L1 L2

15 MILS WIDTH

G2 G4

A10 B10

AE7 J16 K17 E9

C738

C0.1U16Y0402

30 MILS WIDTH

C460

C2.2u10Y-RH

40 MILS WIDTH

C558

C2.2u10Y-RH

C544

C544 C1U10Y

C1U10Y

USB12SB

15 MILS WIDTH

C524

C524 C0.1U16Y0402

C0.1U16Y0402

V5_VREF AVDDCK_33 AVDDCK_12 AVDDC_33

C749

CKVDD12SB

C458

C2.2u10Y-RH

VCC3_SB

C494

C2.2u10Y-RH

+1.2VSB

C548

C548 C1U10Y

C1U10Y

C525

C0.1U16Y0402

R406 1KR0402R406 1KR0402

C542

C542 C1U10Y

C1U10Y

100 MILS WIDTH

VDD12SB

C747

C743

C1U10Y

C486

C486 X_C22u6.3X1206

X_C22u6.3X1206

CP33CP33

R399 X_0RR399 X_0R

C534

C534 C10u10Y0805

C10u10Y0805

10 MILS WIDTH

Y

Z

X

C742

C742 C1U10Y

C1U10Y

CP25CP25

VCC_SB_1V2

21

L43 X_30L3_15_0805L43 X_30L3_15_0805

+1.2VSB

VCC5

D21

S-BAT54C_SOT23

VCC3

C739

C739 C10u16Y1206

C10u16Y1206

2

L41

30L3_15_0805

21

VCC_SB_1V2

U23E

T10

AVSS_SATA_1

U10

AVSS_SATA_2

U11

AVSS_SATA_3

U12

AVSS_SATA_4

V11

AVSS_SATA_5

V14

AVSS_SATA_6

W9

AVSS_SATA_7

Y9

AVSS_SATA_8

Y11

AVSS_SATA_9

Y14

AVSS_SATA_10

Y17

AVSS_SATA_11

AA9

AVSS_SATA_12

AB9

AVSS_SATA_13

AB11

AVSS_SATA_14

AB13

AVSS_SATA_15

AB15

AVSS_SATA_16

AB17

AVSS_SATA_17

AC8

AVSS_SATA_18

AD8

AVSS_SATA_19

AE8

AVSS_SATA_20

A15

AVSS_USB_1

B15

AVSS_USB_2

C14

AVSS_USB_3

D8

AVSS_USB_4

D9

AVSS_USB_5

D11

AVSS_USB_6

D13

AVSS_USB_7

D14

AVSS_USB_8

D15

AVSS_USB_9

E15

AVSS_USB_10

F12

AVSS_USB_11

F14

AVSS_USB_12

G9

AVSS_USB_13

H9

AVSS_USB_14

H17

AVSS_USB_15

J9

AVSS_USB_16

J11

AVSS_USB_17

J12

AVSS_USB_18

J14

AVSS_USB_19

J15

AVSS_USB_20

K10

AVSS_USB_21

K12

AVSS_USB_22

K14

AVSS_USB_23

K15

AVSS_USB_24

H18

PCIE_CK_VSS_1

J17

PCIE_CK_VSS_2

J22

PCIE_CK_VSS_3

K25

PCIE_CK_VSS_4

M16

PCIE_CK_VSS_5

M17

PCIE_CK_VSS_6

M21

PCIE_CK_VSS_7

P16

PCIE_CK_VSS_8

F9

AVSSC

AMD-218S7EBLA12FG-A12-RH

SB700

PCIE_CK_VSS_9 PCIE_CK_VSS_10 PCIE_CK_VSS_11 PCIE_CK_VSS_12 PCIE_CK_VSS_13 PCIE_CK_VSS_14 PCIE_CK_VSS_15 PCIE_CK_VSS_16 PCIE_CK_VSS_17 PCIE_CK_VSS_18 PCIE_CK_VSS_19 PCIE_CK_VSS_20 PCIE_CK_VSS_21

Part 5 of 5

1

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8

VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42

GROUND

VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50

AVSSCK

A2 A25 B1 D7 F20 G19 H8 K9 K11 K16 L4 L7 L10 L11 L12 L14 L16 M6 M10 M11 M13 M15 N4 N12 N14 P6 P9 P10 P11 P13 P15 R1 R2 R4 R9 R10 R12 R14 T11 T12 T14 U4 U14 V6 Y21 AB1 AB19 AB25 AE1 AE24

P23 R16 R19 T17 U18 U20 V18 V20 V21 W19 W22 W24 W25

L17

15 MILS WIDTH

L45

VCC3

220L250mA-600-RH

A A

5

VCC5

C764

X_C0.1U16Y0402

AVDDCK_33

C745

C745 C2.2u10Y-RH

C2.2u10Y-RH

Bottom side

C758

C757

X_C0.1U16Y0402

For EMI

C763

C765

X_C0.1U16Y0402

4

VCC3_SB

C767

C771

X_C0.1U16Y0402

L48

220L250mA-600-RH

C777

15 MILS WIDTH 15 MILS WIDTH

C2.2u10Y-RH

C529

AVDDC_33 AVDDCK_12AVDDC_33

C531

C0.1U16Y0402

3

VCC_SB_1V2

VCC3

X_C0.1U16Y0402

220L250mA-600-RH

C760

VCC5

L56

C750

C750 X_C0.1U16Y0402

X_C0.1U16Y0402

C741

C741 C2.2u10Y-RH

C2.2u10Y-RH

Bottom side

VCC3

C648

X_C0.1U16Y0402

For EMI

C755

C756

X_C0.1U16Y0402

TP115TP115

TP116TP116

TP117TP117

TP118TP118

MICRO-START INT'L CO.,LTD.

Title

SB700 POWER & DECOUPLING

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

VL390 0A

VCC3

AVDDTX_SB VDD12SB USB12SB

of

20 37Tuesday, September 09, 2008

1

20 37Tuesday, September 09, 2008

5

4

3

2

1

REQUIRED STRAPS

D D

VCC3_SB VCC3_SBVCC3

R453

R464

R464 X_10KR0402

X_10KR0402

PCI_CLK217 SIO_PCLK17,25 PCI_CLK417,32 PCI_CLK517 LPC_CLK017 LPC_CLK117

C C

AZ_RST#18,28 SB_GP1618 SB_GP1718

R357

R452

R452 10KR0402

10KR0402

R451

R451 10KR0402

10KR0402

R447

R447 X_10KR0402

X_10KR0402

R434

R434 X_10KR0402

X_10KR0402

R357 10KR0402

10KR0402

R453 X_10KR0402

X_10KR0402

R454

R454 10KR0402

10KR0402

R353

R353 10KR0402

10KR0402

R372

2.2KR0402

R530

2.2KR0402

PCI_CLK2

B B

PULL HIGH

PULL LOW

A A

5

Watchdog timer on NB_PWGRD

ENABLED

DISABLED

DEFAULT

PCI_CLK3

SIO_PCLK

Debug straps

ENABLED (VCC3)(VCC3)

DISABLED

DEFAULT

PCI_CLK4 PCI_CLK5

TPM CLOCK

RESERVED

4

LPC_CLK0

ENABLE PCI MEM BOOT (A11) IMC ENABLED (A12)

ENABLED (VCC3_SB)

DISABLED DISABLED

DEFAULT

ENABLED ENABLED (VCC3_SB)

DEFAULT

Internal Clock Generator

RTC_CLKLPC_CLK1

INTERNAL RTC

NC IS EXT. RTC

DEFAULT

3

AZ_RST#

IMC ENABLED (A11) ENABLE PCI MEM BOOT (A12)

DISABLED

DEFAULT

GP17

GP16

ROM TYPE: H, H = Reserved H, L = SPI ROM L, H = LPC ROM L, L = FWH ROM

DEFAULT

MICRO-START INT'L CO.,LTD.

Title

SB700 STRAPS

Size Document Number Rev

B

Date: Sheet

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

VL390 0A

21 37Tuesday, September 09, 2008

of

1

of

8

D D

C C

7

6

5

4

3

VCC5

2

1

VGA CONNECTOR

VCC5

Y

D5

X

DDC_CLK

Z

6.8K (RS740)

4.7K (RS780)

6.8K (RS740)

4.7K (RS780)

7

D5

BAV99-7-F_SOT23-LF

X

5VDDCDA 5VDDCCL

CLOSE TO MCH

VSYNC

HSYNC

R234 0R0402R234 0R0402

R226 0R0402R226 0R0402

6

VSYNC15

HSYNC15

D7

BAV99-7-F_SOT23-LF

Z

CLOSE TO MCH

DDC_DATA

R147 33R0402R147 33R0402

DDC_CLK

R141 33R0402R141 33R0402

B B

VCC3

VCC5VCC3

R108

X_4.7KR0402

RS740

DAC_SCL15

R179 0R0402R179 0R0402

A A

R126

RS740

X_4.7KR0402

DAC_SDA15

R221 0R0402R221 0R0402

8

G

DS

RS740

Q11

Q11 X_N-2N7002_SOT23

X_N-2N7002_SOT23

RS780

VCC3

VCC5VCC3

G

DS

RS740

Q12

Q12 X_N-2N7002_SOT23

X_N-2N7002_SOT23

RS780

R122

4.7KR0402

R130

4.7KR0402

DDC_DATA

NB_VGA_R15

RS780 A12 and Earlier:R503,R158 150R;A13:140R

NB_VGA_G15

APnote:AN_RS780G1 APnote:AN_RS780G1

NB_VGA_B15

VCC5

C179

X_C0.1U16Y0402

1 2

53

1 2

U7

NC7WZ08U7NC7WZ08

R142 X_0R0402R142 X_0R0402

VCC5

53

1 2

U8

NC7WZ08U8NC7WZ08

R148 X_0R0402R148 X_0R0402

4

R145

47R0402

R149

47R0402

RS780

5

R503

R503 140R1%0402

140R1%0402

R502

R502 150R1%0402

150R1%0402

R501

R501 150R1%0402

150R1%0402

VCC5

D6

BAV99-7-F_SOT23-LF

Y

D8

BAV99-7-F_SOT23-LF

Y

X

Z

VSYNC_C

X

Z

HSYNC_C

CLOSE TO GMCH

CLOSE TO VGA Connector

R158

R158 140R1%0402

140R1%0402

R157

R157 150R1%0402

150R1%0402

R154

R154 150R1%0402

150R1%0402

4

L9 0.12U300m-1L9 0.12U300m-1

C214

C214 X_C5p50N0402

X_C5p50N0402

L8 0.12U300m-1L8 0.12U300m-1

C204

C204 X_C5p50N0402

X_C5p50N0402

L7 0.12U300m-1L7 0.12U300m-1

C196

C196 X_C5p50N0402

X_C5p50N0402

5VDDCCL VSYNC_C HSYNC_C 5VDDCDA

L77 47n250mA-RHL77 47n250mA-RH

C215

C215 C3p50N0402-RH

C3p50N0402-RH

L78 47n250mA-RHL78 47n250mA-RH

C205

C205 C3p50N0402-RH

C3p50N0402-RH

L79 47n250mA-RHL79 47n250mA-RH

C197

C197 C3p50N0402-RH

C3p50N0402-RH

C167

C100P50N0402

3

C856

X_C5p50N0402

C857

X_C5p50N0402

C858

X_C5p50N0402

C0.1U16Y0402

C171

C100P50N0402

C174

C191

C100P50N0402

C219

C1U10Y

VCC5

F-MICROSMD110F-RH

C183

C100P50N0402

D11

BAV99-7-F_SOT23-LF

Y

X

Z

D10

BAV99-7-F_SOT23-LF

Y

X

Z

D9

BAV99-7-F_SOT23-LF

Y

FS2

VDD_VGA

16

17

5

15

10 4

14

9 3

13

8 2

12

7 1

11

6

VGA1

VGA1 DSUB-VGAF_BLUE-RH-2

DSUB-VGAF_BLUE-RH-2

N51-15F0391-F02

Title

Size Document Number Rev

C

Date: Sheet

2

VGAGND

X

Z

VGAGND

C190

C190 C0.1U16Y0402

C0.1U16Y0402

BLUE GREEN RED

MICRO-START INT'L CO.,LTD.

DVI CONNECTOR

VL390 0A

22 37Tuesday, September 09, 2008

of

1

5

SERIAL ATA CONNECTOR BLOCK

4

3

2

1

PS2 KEYBOARD & MOUSE CONNECTOR

SATA 1 Blue SATA 3 Orange SATA2,4 Black

SATA1

SATA3

ST_TX#0 ST_RX#0

ST_TX1 ST_TX#1

ST_RX#1SATA_RX1-

ST_TX4 ST_TX#4

ST_RX#4 ST_RX4

SATA3

GND

9

GND

TX+

1 2

TX-

3

GND GND

4

RX-

5

RX+

6 7

GND

8

SATA7PM_ORANGE-P

SATA4

GND

9

GND

TX+

1 2

TX-

3

GND GND

4

RX-

5

RX+

6 7

GND

8

SATA7PM_BLACK-P-RH

For e-SATA

BLACK:N5N-07M0221-H06

1 2 3 4 5 6 7

ESATA7PM_BLUE-P-RH

ESATA1

GND TX+ TXGND RXRX+ GND

SATA_TX2+19 SATA_TX2-19

SATA_RX2-19 SATA_RX2+19

SATA_TX3+19 SATA_TX3-19

SATA_RX3-19

G1

G2

G3

G4

M1

M2

Default 10nF ,

D D

SATA_TX0+19

SATA_TX0-19 SATA_RX0-19

SATA_RX0+19

SATA_TX1+19

SATA_TX1-19

SATA_RX1-19 SATA_RX1+19 SATA_RX3+19

C C

SATA_TX4+19 SATA_TX4-19

SATA_RX4-19 SATA_RX4+19

Option 0 ohm

SATA_TX0+

C589 C0.01U16X0402C589 C0.01U16X0402

SATA_TX0SATA_RX0-

SATA_RX0+ ST_RX0

SATA_TX1+ SATA_TX1-

SATA_RX1+

SATA_TX4+ SATA_TX4-

SATA_RX4SATA_RX4+

1 2

C586 C0.01U16X0402C586 C0.01U16X0402

1 2

C571 C0.01U16X0402C571 C0.01U16X0402

1 2

C565 C0.01U16X0402C565 C0.01U16X0402

1 2

C577 C0.01U16X0402C577 C0.01U16X0402

1 2

C572 C0.01U16X0402C572 C0.01U16X0402

1 2

C557 C0.01U16X0402C557 C0.01U16X0402

1 2

C552 C0.01U16X0402C552 C0.01U16X0402

1 2

C583 C0.01U16X0402C583 C0.01U16X0402

1 2

C575 C0.01U16X0402C575 C0.01U16X0402

1 2

C564 C0.01U16X0402C564 C0.01U16X0402

1 2

C554 C0.01U16X0402C554 C0.01U16X0402

1 2

Add ESATA 0901

B B

SATA_TX2+

C493 C0.01U16X0402C493 C0.01U16X0402

SATA_TX2-

C488 C0.01U16X0402C488 C0.01U16X0402

SATA_RX2-

C482 C0.01U16X0402C482 C0.01U16X0402

SATA_RX2+

C479 C0.01U16X0402C479 C0.01U16X0402

SATA_TX3+

C514 C0.01U16X0402C514 C0.01U16X0402

SATA_TX3-

C508 C0.01U16X0402C508 C0.01U16X0402

SATA_RX3-

C499 C0.01U16X0402C499 C0.01U16X0402

SATA_RX3+

C496 C0.01U16X0402C496 C0.01U16X0402

Default 10nF , Option 0 ohm

1 2 1 2

CPUFAN_PWM25

ST_TX2ST_TX0 ST_TX#2

ST_RX#2 ST_RX2

ST_TX3 ST_TX#3

ST_RX#3 ST_RX3ST_RX1

CPUFAN_PWM

SATA1

GND

9

GND

TX+

1 2

TX-

3

GND GND

4

RX-

5

RX+

6 7

GND

8

CONN-SATA2P_blue

SATA2

GND

9

GND

TX+

1 2

TX-

3

GND GND

4

RX-

5

RX+

6 7

GND

8

SATA7PM_BLACK-P-RH

VCC5VCC3

R117

4.7KR0402

PWM FAN CONTROL

VCC3

R113

R113 X_4.7KR0402

X_4.7KR0402

R92 100R0402R92 100R0402

D3

D3 X_1N4148W-F

X_1N4148W-F

CPU FAN

+12V

D1 1N4148W-F_SOD123-RHD1 1N4148W-F_SOD123-RH R9 4.7KR0402R9 4.7KR0402

C28

C28 C0.1U16Y0402

C0.1U16Y0402

+

12

EC3

EC3 CD100u16EL11-RH

CD100u16EL11-RH

SVCC2

MSDATA25 MSCLK25

KBDATA25 KBCLK25

1 2

MSDATA MSCLK

KBDATA KBCLK

R6 27KR0402R6 27KR0402

BH1X4B_BROWN-RH

Default is 4-Pin FAN

3 4

5 6

7 8

CPU_FAN1

4 3 2 1

RN1

RN1 8P4R-2.2KR

8P4R-2.2KR

FB1 300L600m_150FB1 300L600m_150 FB2 300L600m_150FB2 300L600m_150

FB3 300L600m_150FB3 300L600m_150 FB4 300L600m_150FB4 300L600m_150

CPUFAN_TAC 25

R7 22KR0402R722KR0402

X_C0.1U25Y

C33

C33 C180P50N

C180P50N

C31

C31 C180P50N

C180P50N

C25

C25 C180P50N

C180P50N

C21

C21 C180P50N

C180P50N

C9

R20

R20 X_1KR1%0402

X_1KR1%0402

16

17

KBMS1

7

10

8

11

9

12

MS

1

4 2 5

3

6

KB

CONN-MiniDIN2X12P-RH

131415

VCC5

C604

C604 X_C0.1U16Y0402

X_C0.1U16Y0402

SYSTEM FAN

+12V

SYSFAN1

3 2 1

BH1X3_White

+

12

C895

EC88

CD470u16EL11.5

A A

5

4

3

C895

X_C0.1u16Y0402

BH1X3_White

2

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

C

Date: Sheet

MICRO-START INT'L CO.,LTD.

SATA & COM1 & LPT

VL390 0A

1

23 37Tuesday, September 09, 2008

of

5

VDD33

R810

0R/8

C860

D D

CHOKE10 close to U30 Pin 1 within 0.5cm

CH/4.7uH/4.0x4.3x2.0mm/1.24A

CHOKE10

CTRL18

1 2

C862

C0.1u25Y0402-RH

C862 , C863 CLOSE TO CHOKE1

MDIx+/Reference to GND plan.

C C

C864 use 0.01uF for better EMI performace.

R815

VL1_2 DVDD15

0R/8

B B

VCC3_SB VDD33

R808

VDD33 AVDD33

0R/8

EC77

100uf/16v/6.3x5/2.5mm

A A

EC77

R814

VL1_2 EVDD18

0R/8

C0.1u25Y0402-RH

R811

R811 0R/8

0R/8

C864

C0.01u25X0402

DVDD15

PE_LAN_RST#17

R809

12

0R/8

+

C0.1u25Y0402-RH

C873

R812

R812 0R/8

0R/8

C863

C22u6.3X1206

C870

EVDD18

5

C0.1u25Y0402-RH

FB12

CTRL18 AVDD33

AVDD18

AVDD18 DVDD15 VDD33

SCLK118,30,31,32 SDATA118,30,31,32

R669 0R/4R669 0R/4

AVDD33

C860

R668 Place near Pin64 of U30

2.49k for 8111CP ?

AVDD18

MDI_0+ MDI_0-

FB12

MDI_1+ MDI_1-

MDI_2+ MDI_2-

MDI_3+ MDI_3-

C872

C0.1u25Y0402-RH

C861

C22u6.3X1206

R668

2.49K/4/1%

1

VCTRL18

2

AVDD33

3

MDIP0

4

MDIN0

5

AVDD18

6

MDIP1

7

MDIN1

8

AVDD18

9

MDIP2

10

MDIN2

11

AVDD18

12

MDIP3

13

MDIN3

14

AVDD18

15

VDD15

16

VDD33

R385 33R0402R385 33R0402 R387 33R0402R387 33R0402

C0.1u25Y0402-RH

C871

C0.1u25Y0402-RH

VDD33

R818

R818 0R/6

0R/6

XTAL2

XTAL1

AVDD33

DVDD15

CTRL15/VDD33

60

63

64

59

62

65

GND

C865

58

GVDD

CKTAL261CKTAL1

VCTRL15

AVDD33

EVDD18

DVDD15

LED057LED156LED255LED3

VDD15

EGND

RSET

SBCLK17SMDATA18LANWAKEB19PERSTB20VDD1521EVDD1822HSIP23HSIN24EGND25REFCLK_P26REFCLK_N27EVDD1828HSOP29HSON30EGND31VDD15

4

LINK_UP

DSM_GPO# 18

LINK_100 LINK_1G

XTAL1

XTAL2

C868 C27p50NC868 C27p50N

Y7

25MHz/18pf/HC49S

C869 C27p50NC869 C27p50N

R666 330R/6R666 330R/6 R723 330R/6R723 330R/6

Pay attention to the This Pin

VDD33

DVDD15

U30

50

54

51

52

49

NC

VDD3353VDD15

VDD15

OGPIO

EESK

EEDI/AUX

VDD33

EEDO EECS

VDD15

VDD1

VDD15 VDD33

ISOLATEB

CLKREQB

32

DVDD15

EGND

EVDD18

RX_LANN0_C RX_LANP0_C

LAN_CLK# 12 LAN_CLK 12

TXLANN 14

WAKE#

TXLANP 14 WAKE# 18,30

AVDD18

C874 C0.1u25Y0402-RHC874 C0.1u25Y0402-RH C885 C0.1u25Y0402-RHC885 C0.1u25Y0402-RH C875 C0.1u25Y0402-RHC875 C0.1u25Y0402-RH C876 C0.1u25Y0402-RHC876 C0.1u25Y0402-RH

VDD33

C877 C0.1u25Y0402-RHC877 C0.1u25Y0402-RH

C879 C0.1u25Y0402-RHC879 C0.1u25Y0402-RH C880 C0.1u25Y0402-RHC880 C0.1u25Y0402-RH

4

EESK

48

EEDI_LAN

47

VDD33

46

EEDO

45

EECS

44

DVDD15

43 42

NC4

41 40

NC6

39

NC7

DVDD15

38

VDD33

37

ISOLATEB

36 35

NC8

34

NC9

33

R724

X_0R/4

RTL8111CP-VB-GR

B06-8111C3C-R09

EGND

C867 C0.1u10X0402C867 C0.1u10X0402 C866 C0.1u10X0402C866 C0.1u10X0402

0R/8

R813

R671 1K/4R671 1K/4 R670 15K/4R670 15K/4

CE

R82

B

X_10K/4

Q99

Q99 X_2N3904_SOT23

X_2N3904_SOT23

BIOS pull high/low on Pin36 ISOLATE to leave/enter DSM.

RX_LANN0 14 RX_LANP0 14

DVDD15

3

VCC3

ISOLATEBR 18

C886 C0.1u25Y0402-RHC886 C0.1u25Y0402-RH C887 C0.1u25Y0402-RHC887 C0.1u25Y0402-RH C888 C0.1u25Y0402-RHC888 C0.1u25Y0402-RH C881 C0.1u25Y0402-RHC881 C0.1u25Y0402-RH C882 C0.1u25Y0402-RHC882 C0.1u25Y0402-RHC878 C0.1u25Y0402-RHC878 C0.1u25Y0402-RH C883 C0.1u25Y0402-RHC883 C0.1u25Y0402-RH C884 C0.1u25Y0402-RHC884 C0.1u25Y0402-RH

3

R725

X_0R/4

C890

C680p50X0402-RH

C1000p50X0402

VDD33AVDD18

R727 0R/4R727 0R/4

C891

R677

3.6K/6/1%

EECS EESK EEDI_LAN EEDO

8111CP uses 93C66 and keep R607

C893

C1000p50X0402

R726

R726 330R/6

330R/6

LAN_ACTLED LINK_UP

MDI_0+ MDI_0MDI_1+ MDI_1MDI_2+ MDI_2MDI_3+ MDI_3-

LINK_100 LINK_1G

C1000p50X0402

MDI_3+ MDI_3-

MDI_1+ MDI_1-

19 20 13 18 12 17 11 16 10 15

9 14 21 22

RJ45_USBX2_LEDX2_TX-GIGA-RH-1

C892

VCC3

52

6 1

VCC3

52

6 1

2

VDD33

R679

R679 10K/4

10K/4

U31

1

CS

VCC

2

SK

NC

3

DI

NC

4

DO

GND

4K/93C66/10ms-SOIC8

C894

C1000p50X0402

LAN_USB1B

YELLOW+

YELLOW+ YELLOW-

YELLOW-

PWR

TD1+

TD1+ TD1-

TD1TD2+

TD2+ TD2-

TD2TD3+

TD3+ TD3-

GR/OR+

GR/OR+ GR/OR-

GR/OR-

TD3TD4+

TD4+ TD4-

TD4-

GND

21

22

N58-22F0181-F02

D30

IP4220/SOT457

MDI_2+

4

MDI_2-

3

D40

IP4220/SOT457

MDI_0+

4

MDI_0-

3

2

1

VDD33

8 7 6 5

C889

C0.1u25Y0402-RH

19

Left => YELLOW

20

Right => Orange / Green

MICRO-START INT'L CO.,LTD.

Title

LAN 8111CP

Size Document Number Rev

Custom

Date: Sheet

MICRO-START INT'L CO.,LTD.

VL390 0A

1

of

24 37Tuesday, September 09, 2008

5

LPC I/O IT8720

D D

C C

B B

SLP_S3# LPC_PME#

AMD_TSI_C AMD_TSI_D

AMD_TSI_C7 AMD_TSI_D7

PCIRST_SIO#17

LPC_DRQ#017 SERIRQ17,32

LPC_FRAME#17,32

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

SIO_PCLK17,21

SIO_48M_CLK12

LPC_PME#18

KBRST#18 A20GATE18 KBDATA23 KBCLK23 MSDATA23 MSCLK23

R25 X_10KR0402R25 X_10KR0402 R24 10KR0402R24 10KR0402

R378 2.2KR0402R378 2.2KR0402 R379 2.2KR0402R379 2.2KR0402

SUPER I/O STRAPPING RESISTOR

LPC_FRAME#

R115 X_10KR0402R115 X_10KR0402

SERIRQ

A A

/N

R116 X_10KR0402R116 X_10KR0402

RN4 X_8P4R-10KR0402RN4 X_8P4R-10KR0402

LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

IO30

R89 10KR0402R89 10KR0402

IO3

R84 10KR0402R84 10KR0402

RIA#

R112 X_10KR0402R112 X_10KR0402

Reserve For No COM port

DCDA# RIA# CTSA# DTRA# RTSA# DSRA# SOUTA SINA DCDB# RIB# CTSB# DTRB# RTSB# DSRB# SOUTB SINB

MB_ID0 MB_ID1

DRVDEN0 INDEX# MOA# AMD_TSI_C DSA# AMD_TSI_D DIR# STEP# WRDATA# WE# TRACK0# WP_# RDDATA# HEAD# DSKCHG#

PCIRST_SIO# LPC_DRQ#0 SERIRQ LPC_FRAME# LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

KBRST# A20GATE KBDATA KBCLK MSDATA MSCLK

VCC3_SB VCC5_SB

VCC3

VCC3 VCC3

1

2

3

4

5

6

7

8

5

VCC5

L2

30L3_15_0805L230L3_15_0805

C63

C62

4

35

C0.1U16Y0402

U3

X_C0.1U16Y0402

127 128

126 122 123 124 125

26 28 27 29 23 22 21 20

48 25 24

51 63 52 55 54 53 57 58 56 60 62 64 61 59 65

37 38 39 40 41 42 43 44 47

49 73

45 46 80 81 82 83

31 118 119 120

LPC_DRQ#0

RTSA#

DTRA#

DTRB#

SOUTA

A20GATE

For Lenovo FAN Speed Control 50% Power On default

VCC

DCD1# RI1#

1

CTS1# DTR1#/JP4 RTS1#/JP2 DSR1# SOUT1/JP3 SIN1 VIDO1/GP21/DCD2# VIDO6/GP17/RI2# VIDO0/GP20/CTS2# VIDO7/GP16/DTR2#/JP6 VIDO2/FAN_TAC5/GP24/RTS2# VIDO3/FAN_TAC4/GP25/DSR2# VIDO4/GP26/SOUT2 VIDO5/GP27/SIN2

SO/GP50 GP22/SCK GP23/SI

5

VCORE_EN/VID7/GP64

6

VCORE_GOOD/VID6/GP63

DENSEL# INDEX# MTRA# PECI/AMDTSI_C/DRVB# DRVA# SST/AMDTSI_D/PECI_AVA/MTRB# DIR# STEP# WDATA# WGATE# TRK0# WPT# RDATA# HDSEL# DSKCHG#

LRESET# LDRQ#/JP1 SERIRQ LFRAME# LAD0 LAD1 LAD2 LAD3 PCICLK

CLKIN PME#/GP54

KRST#/GP62 GA20/JP5 KDAT/GP61 KCLK/GP60 MDAT/GP57 MCLK/GP56

SVC/PECI_RQT/GP14 GP67/CPU_PG GP66/VLDT_EN GP65/VDDA_EN

SIO_48M_CLK

C43

X_C22P50N0402

Place close to SIO

R336 10KR0402R336 10KR0402 R61 10KR0402R61 10KR0402 R470 10KR0402R470 10KR0402 R74 10KR0402R74 10KR0402

R356 10KR0402R356 10KR0402 R347 X_680R0402-RHR347 X_680R0402-RH

R348 1KR0402R348 1KR0402 R91 X_680R0402-RHR91 X_680R0402-RH

VCC

GNDD

74

50

+

EC23 CD47u10EL7-1

1 2

C157 C0.1U16Y0402C157 C0.1U16Y0402

99

AVCC

IT8720F-RHU3IT8720F-RH

CE_N/RESETCON#/CIRTX1

RSMRST#/CIRRX1/GP55

PCIRSTIN#/CIRTX2/SVD/GP15

PCIRST3#/GP10/VDIMM_STR_EN

FAN_CTL5/CIRRX2/GP16

GNDA

GNDD

86

117

CP3

X_CP

VCC3

VCCH

CP1 X_CPCP1 X_CP

L1 X_30L3A-15_0805-RHL1 X_30L3A-15_0805-RH

C158

+

12

EC2

EC2 CD47u10EL7-1

67

VCCH

STB#/GP87/SMBC_M AFD#/GP86/SMBC_R

INIT#/GP85/SMBD_M

SLIN#/GP84/SMBD_R

FAN_CTL4/VID_TURBO

L3

L3 X_120L600mA-250

X_120L600mA-250

CD47u10EL7-1

C0.1U16Y0402

PD7/GP77/BUSSO2 PD6/GP76/BUSSO1 PD5/GP75/BUSSO0

116 115 114 113

PD4/GP74/BUSSI2

112

PD3/GP73/BUSSI1

111

PD2/GP72/BUSSI0

110

PD1/GP71

109

PD0/GP70

108 107 106

ERR#

105 104 103

ACK#/GP83

102

BUSY/GP82

101

PE/GP81

100

SLCT/GP80

78

PWROK2/GP41

77

SUSC#/GP53

76

PSON#/GP42

75

PANSWH#/GP43

72

PWRON#/GP44

71

SUSB#

30 85 66

IRTX/GP47

70

GP46/IRRX

68

COPEN#

79

3VSBSW#/GP40

3 84 34

PCIRST2#/GP11

32

PWROK1/GP13

33

PCIRST1#/GP12

98

VIN0

97

VIN1

96

VIN2

95

VIN3/ATXPG

94

VIN4/VLDT_12

93

VIN5/VDDA_25

92

VIN6/VDIMM_STR

91

VREF

90

TMPIN1

89

TMPIN2

88

TMPIN3

2 121 12

FAN_CTL3/GP36

11

FAN_TAC3/GP37

10

FAN_CTL2/GP51

9

FAN_TAC2/GP52

8

FAN_CTL1

7

FAN_TAC1

19

VID0/GP30

18

VID1/GP31

17

VID2/GP32

16

VID3/GP33

15

GNDD

14

VID4/GP34

13

VID5/GP35

87

TS_D-

69

VBAT

36

VIDVCC

VCC3

HW_AGND

Power On Strapping Options

Symbol

Flashseg1_EN (LPC_DRQ#0)

(RTSA#)

VIDO_EN

(SOUTA)

CHIP_SEL K8PWR_EN 1 (DTRA#)

(SOUTA/A20GATE)1124/46 SVID_EN

(DTRB#) WDT_EN (A20GATE)

4

R326

Giga10/100

1

MB_ID0

MB_ID1

MB_ID2

Description

R326 10KR0402

10KR0402

BIOS_SELECT1 BIOS_SELECT2

R280

R280 10KR0402

10KR0402

CPUFAN_PWM 23 CPUFAN_TAC 23

Z

VCC5_SB

R324 1KR0402R324 1KR0402

VCC5

RND7 RND6 RND5 RND4 RND3 RND2 RND1 RND0 PRSTB# PRAFD# PRERR# PRINIT# LPT_SLIN# PRACK# PRBUSY PRPE PRSLCT

R26 10KR0402R26 10KR0402 R27 X_0R0402R27 X_0R0402

SLP_S3#

IO_RSMRST# PWR_LED

CHASSIS SUS_LED

R229 4.7KR0402R229 4.7KR0402

R97 10KR0402R97 10KR0402

HM_VREF VR_TEMP_DA

SIO_THERMDA_CPU

R95 X_0R0402R95 X_0R0402 R96 X_0R0402R96 X_0R0402

MB_ID2 COM_GPIO2

BIOS_SELECT1 BIOS_SELECT2

SIO_THERMDC_CPU

value38PIN

122 124

126

29 46

VCC5_SB

LPC_SMI# 18 ATX_PSON# 26,34 PSIN 34 SB_PWRON# 18 SLP_S3# 18,26

Delay 60 ms from VCC5_SB ramp up to 4V

IO30

IO_RSMRST# 18 PWR_LED 34 SUS_LED 34

IO3

VCC3_SB

USB_EN 29

VCC5

VIN0 VIN1 VIN2 VIN3 VIN4 VIN5

C10

C10 C1U10Y

C1U10Y

CPUFAN_PWM

Add 0902

VBAT_IO

C12

Place close to SIO side

C1U10Y

MB_ID0

0 MB_ID1 MB_ID2

Disabled.

1

Flash I/F Address Segment 1 (FFFE_0000h~FFFF_FFFFh, 000F_0000h~000F_FFFFh) is enabled

0 1

Disable VIDOUT pins(except VIDO6 & VIDO7)

0

Enable VIDOUT pins Chip selection in configuration.

--

K8 POWER SEQUENCE FUNCION IS DISABLED

0 K8 POWER SEQUENCE FUNCION IS ENABLED

The default value of EC Index 15h / 16h / 17h is 40h (50%)

11

The default value of EC Index 15h / 16h / 17h is 7Fh(Fan off )FAN_CTL_SEL

10 01

The default value of EC Index 15h / 16h / 17h is 00h(Fan full speed )

00

The default value of EC Index 15h / 16h / 17h is 20h(75%) Parallel VIDOutput(Only for Parallel VID input)

1 0 Serial VIDOutput(Only for Parallel VID input)

Disable WDT to reset PWROK

0

Enable WDT to reset PWROK

4

JMAT_MODE1

1 2 3

N31-1030151+N33-1020271-RH

X_C0.1U16Y0402

R286

COM_GPIO2

10KR0402

VCC3_SB

Y

D25

S-BAT54C_SOT23

X

VBAT_IN

R98 X_10KR0402R98 X_10KR0402 R86 10KR0402R86 10KR0402

R523 X_10KR0402R523 X_10KR0402 R87 X_10KR0402R87 X_10KR0402

R553 X_10KR0402R553 X_10KR0402 R239 X_10KR0402R239 X_10KR0402

G

VCC3

C787

EMI_0B

VCC5

C793

VCC3

EMI_0B Placement close to C630

VCC5

VCC5_SB

VCC5

3

SERIAL PORT 1

VCC5

NRIA NCTSA#

C633

NDSRA#

NRTSA NDSRA# NCTSA# NRIA

NDCDA# NSOUTA NSINA NDTRA

NSINA NDCDA#

RTSA# DTRA# SOUTA

C638 C330p50XC638 C330p50X C642 C330p50XC642 C330p50X C632 C330p50XC632 C330p50X C630 C330p50XC630 C330p50X

C737 C330p50XC737 C330p50X C748 C330p50XC748 C330p50X C676 C330p50XC676 C330p50X C653 C330p50XC653 C330p50X

C0.1U16Y0402

SERIAL PORT 2

BOM Option: 10/100 /N

C0.1U16Y0402

COM2 HEADER

NDCDB# NSOUTB

NRTSB NRIB

VR_TEMP_DA

C2

C2200p50X0402

SIO_THERMDC_CPU VR_TEMP_DC

CP8 X_CPCP8 X_CP

D54

VCC5

RN47 8P4R-2.7KR0402RN47 8P4R-2.7KR0402

BAS32L_LL34

RND0

1 3 5 7

RN48 8P4R-2.7KR0402RN48 8P4R-2.7KR0402

1 3 5 7

RN49 8P4R-2.7KR0402RN49 8P4R-2.7KR0402

1 3 5 7

RN46 8P4R-2.7KR0402RN46 8P4R-2.7KR0402

1 3 5 7

R942 2.7KR0402R942 2.7KR0402

2 4 6 8

C899

RND1 RND2 RND3

RND4 RND5 RND6

PRSLCT PRPE PRBUSY PRACK#

LPT_SLIN# PRINIT# PRERR# PRAFD# PRSTB#

3

20

2 3 4 7 9

16 15 13 11

VCC5

C64

COM2

1 2 3 4 5 7 8 9

H2X5[10]_white-RH

CE

Q66

Q66 N-MMBT3904_NL_SOT23

N-MMBT3904_NL_SOT23

C0.1u25Y0402-RH

U36

VCC RA1 RA2 RA3 RA4 RA5

DA1 DA2 DA3 GND

GD75232_SSOP20

NRIB NCTSB# NDSRB# NSINB NDCDB#

RTSB# DTRB# SOUTB

NDSRB#

6

NCTSB#

TEMP SENSOR

Place close

B

to VRM

C0.1U16Y0402

C0.1U16Y0402 C635

C635

+12COM_1

1

VDD

RIA#

19

RY1

CTSA#

18

RY2

DSRA#

17

RY3

SINA

14

RY4

DCDA#

12

RY5

NRTSA

5

DY1

NDTRA

6

DY2

NSOUTA

8

DY3

-12COM_1

10

VSS

C677 C0.1U16Y0402C677 C0.1U16Y0402

JCOM1 CONNECTOR

1211

10

NDCDA#

1

NSINA NSOUTA

PRSTB# RND0 RND1 RND2 RND3 RND4RND7 RND5 RND6 RND7 PRACK# PRBUSY PRPE PRSLCT

6

2

7

3

8

4

9

5

U34

20

VCC

2

RA1

3

RA2

4

RA3

7

RA4

9

RA5

16

DA1

15

DA2

13

DA3

11

GND

GD75232_SSOP20

NRTSB

C649 C330p50XC649 C330p50X

NDSRB#

C650 C330p50XC650 C330p50X

NCTSB#

C651 C330p50XC651 C330p50X

NRIB

C652 C330p50XC652 C330p50X

NDCDB#

C674 C330p50XC674 C330p50X

NSOUTB

C752 C330p50XC752 C330p50X

NSINBNSINB

C672 C330p50XC672 C330p50X

NDTRBNDTRB

C675 C330p50XC675 C330p50X

COM_GPIO2

Close to COM PORT header

SIO_THERMDA_CPU

SIO_THERMDC_CPU

LPT1

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

BAS32L_LL34

D26

BAS32L_LL34

BAS32L_LL34 D53

D53

JCOM1

NDSRA# NRTSA NCTSA# NRIANDTRA

DSUB-COMM_GREEN-RH-6

C0.1U16Y0402

C0.1U16Y0402 C645

C645

+12COM_1

1

VDD

RIB#

19

RY1

CTSB#

18

RY2

DSRB#

17

RY3

SINB

14

RY4

DCDB#

12

RY5

NRTSB

5

DY1

NDTRB

6

DY2

NSOUTB

8

DY3

-12COM_1

10

VSS

C678 C0.1U16Y0402C678 C0.1U16Y0402

C794 C0.1U16Y0402C794 C0.1U16Y0402

C1

C2200p50X0402

CP2 X_CPCP2 X_CP

PRAFD# PRERR# PRINIT# LPT_SLIN#

28

27 26

DSUB-PRINTERF_BURGUNDY-RH-4

2

+12V

-12V

2

R535 0R0402R535 0R0402

R536 0R0402R536 0R0402

RND0 RND1 RND2 RND3

RND4 RND5 RND6 RND7

PRSLCT PRPE PRBUSY PRACK#

PRSTB#

THERMDA_CPU 7,32

THERMDC_CPU 7,32

CN4 8p4C-220p50NCN4 8p4C-220p50N

1

2

3

4

5

6

7

8

CN5 8p4C-220p50NCN5 8p4C-220p50N

1

2

3

4

5

6

7

8

CN6 8p4C-220p50NCN6 8p4C-220p50N

1

2

3

4

5

6

7

8

C898

C220p25N0402

Super I/O Chasiss

NOT USED

CHASSIS

FLOPPY CONNECTOR

WP_#

1

INDEX#

3

TRACK0#

5

RDDATA#

7

DSKCHG#

FDD1

1 2 3

7 8

9 10 11 12 13 14 15 16 17 18 19

20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

BH2X17[4][5][6]_BLACK-RH

Thermal Resistor

R13 47R0402R13 47R0402

VCCP

R10 10KR1%0402R10 10KR1%0402

VCC3

R14 47R0402R14 47R0402

VCC_DDR

R1 6.81KR1%0402R1 6.81KR1%0402

VCC5

R2 6.81KR1%0402R2 6.81KR1%0402

VCC5_SB

R3 30.1KR1%0402R3 30.1KR1%0402

+12V

TP119TP119

TP120TP120

TP127TP127

TP128TP128

TP149TP149

TP150TP150

TP151TP151

Title

LPC I/O IT8720

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

1

R23 1KR0402R23 1KR0402

VCC5

2

RN2

4

8P4R-1KR0402

6 8

R43

R43 1KR0402

1KR0402

DRVDEN0

INDEX# MOA#

DSA# DIR#

STEP# WRDATA# WE# TRACK0# WP_# RDDATA# HEAD# DSKCHG#

VIN4

C17 C0.1U16Y0402C17 C0.1U16Y0402

C13 C0.1U16Y0402C13 C0.1U16Y0402

C18 C0.1U16Y0402C18 C0.1U16Y0402

C14 C0.1U16Y0402C14 C0.1U16Y0402 R11 10KR1%0402R11 10KR1%0402

C15 C0.1U16Y0402C15 C0.1U16Y0402 R12 10KR1%0402R12 10KR1%0402

C16 C0.1U16Y0402C16 C0.1U16Y0402 R15 10KR1%0402R15 10KR1%0402

VL390 0A

HW_AGND

VIN0 HW_AGND

VIN5 HW_AGND

VIN1 HW_AGND

VIN2 HW_AGND

VIN3 HW_AGND

VCC5

VCCH

+12COM_1

-12COM_1

PCIRST_SIO# SIO_PCLK

SIO_48M_CLK

MICRO-START INT'L CO.,LTD.

of

25 37Tuesday, September 09, 2008

1

25 37Tuesday, September 09, 2008

LPC_DRQ#0

5

REFERENCE VOLTAGE

*Reference sinking/sourcing 100uA *Reference ramp-up 5mS

*5VSB > 4.2V POR *Pin8 > 1.4V Enable *Pin8 < 0.4V Disable

D D

SCLK10,11,12,18 SDATA10,11,12,18

VRM_GD6

5VDIMM

VCC5_SB

R909R909 R910R910

EN_HT

R615 0R0402R615 0R0402

Enable 0.9VREF and 1.25REF

R934 X_10RR934 X_10R

R933 10RR933 10R

U26

3

SCL

4

SDA

8

EN

C839 C0.1u16Y0402C839 C0.1u16Y0402

1

7

1.5V

5VSB

6

0.9V

5

1.2V

GND

UP6264AMA8_SOT23-8-RH

2

5VDIMM FOR DDR

MODE

R916

0R0402

5VDIMM_5V

U16

S3#55VSB_DRV

6

S5#

4

MODE

R912 510R0402R912 510R0402

VCC5

ATX_PWROK27,34

VCC5_SB

C C

CRB: MODE Low support S0/S3 Hi support S0/S3/S5

R913 10KR0402R913 10KR0402

SLP_S3#18,25 SLP_S5#18,27

R915 X_4.7KR0402R915 X_4.7KR0402

For special PSU sequence

VCC3 VCC5_SB

R918

X_1KR0402

R931

X_4.7KR0402

R927

X_47KR1%0402-RH

D

G

S

Q33

X_N-2N7002_SOT23

C94

X_C0.1u16Y0402

R914 10R0402R914 10R0402 C87 X_C0.1u16Y0402C87 X_C0.1u16Y0402

1

2

5VSB

5VCC

5VCC_DRV

GND

3

UP7501M8_SOT23-8-RH

D

Q31

G

S

X_N-2N7002_SOT23

5VSBDRV1

7

5VDRV1

8

5VDIMM_5V

+12V

???NEW rev UPI/uP6264BMA8 I34-0626419-U33 ???

VCC5_SB VCC5

R903

X_11KR1%0402

C840

C0.1u16Y0402

VCC5_SB

C843 C18000p16X0402C843 C18000p16X0402

C93

R917

1.5KR-RH

3VDUAL POWER

B B

A A

VCC5_SB

VCC3_SB

R618 X_0R0402R618 X_0R0402

C847

C10u10Y0805

C150

C10u10Y0805

VCC5_SB

R922 10RR922 10R

U18

1

POK

2

EN

3

VIN

5

VREF

1.2VDUAL POWER

For SB +1.2V_SUS Power Rail

U42

U42 UP7707M5-00_SOT23-5

UP7707M5-00_SOT23-5

1

VIN

3

EN

5

C845 C1U10YC845 C1U10Y

4

VOUT

VCTRL

GND8GND

UP7706U8_PSOP8-RH

9

VOUT

FB

GND

4

2

FB

6

C846

X_C0.015u16X0402

7

5

C854

X_C0.015u16X0402

Vo=0.8*(R1+R2)/R1

VCC3

S

D

R924

10KR0402

R926 200KR0402R926 200KR0402

R925

3.3KR0402

R2

R1

4

R902

X_11KR1%0402

R610 100R0402R610 100R0402 R614 100R0402R614 100R0402

C841

C842

C0.1u16Y0402

VCC5_SB

X_C0.1u16Y0402

G

D S

D

G

S

R911

200KR0402

VCC5

C0.022u16X0402-RH

R325

56KR1%0402

5VDRV1

G

Q42

N-APM3023NUC-TRL_TO252-RH

5VDRV1

1.2V@1.5A

R616

C151

1KR1%0402

R598

2KR1%0402

4

1.5V_REF

0.9V_REF

1.2V_REF

Q10

Q10 P06P03LCG_SOT89

P06P03LCG_SOT89

Q32

N-APM3023_TO252-RH

5VDRV1_EN 29

VCC3_SB

12

+1.2VSB

12

X_C10u10Y0805

5VDIMM

C844

X_C0.1u16Y0402

+

EC40

.CD1000U6.3EL11.5

+

EC37

EC37 CD100u16EL5-RH

CD100u16EL5-RH

3

0.9V_REF 1.2V_REF

D

Q80

G

VCC5

R644

10KR0402

C850

C0.1u16Y0402

G

S

N-2N7002_SOT23

VCC5 VCC3

12

+

EC8

.CD1000U6.3EL11.5

C146

C147

C10u10Y0805

X_C1U10Y0402-RH

R597 10KR0402R597 10KR0402

CPU_VDDR_REF

CPU_VDDR_FB

R647

X_270R1%0402

12

+

EC38

CPU_VDDR POWER

ATX_PSON#25,34

ATX_PWROK27,34

1.2V_REF VCC_DDR

ATX_PSON#

VCC5_SB

12

+

EC63

Place Close to U18

.CD1000U6.3EL11.5

CPU VDDA_25 POWER

U44

U44 UP7707M5-00_SOT23-5

UP7707M5-00_SOT23-5

1

VIN

3

EN

FB

GND

4

2

+12V

U51A

AZ358M-E1_SOIC8-RH

3

+

1

2

-

4 8

R646 0R0402R646 0R0402

VCC_1V2 POWER

1.2V_REF

R600

10KR0402

C833

C0.1u16Y0402

VCC_1V2_REF VCC_1V2_FB

R603

X_270R1%0402

+12V

U49A

AZ358M-E1_SOIC8-RH

3

+

1

2

-

4 8

R601

20KR1%0402

R602 0R0402R602 0R0402

ER_RS780E1.pdf from 1.35V change to normal 1.2V

VCC_SB_1V2 POWER

+1.2VSB_FB

R607

R607 3KR1%0402

3KR1%0402

5 6

For SB +1.2V_S5 Power Rail

+12V

U51B

AZ358M-E1_SOIC8-RH

+

7

-

4 8

R605

20KR1%0402

R606 1KR1%0402R606 1KR1%0402

3

1.2V_REF VCC_DDR

0.9V_REF

R604

R608

X_10KR0402

10KR0402

C835

C0.1u16Y0402

+1.2VSB_REF

VOUT

R645

20KR1%0402

VCC_DDR

D

Q82

G

S

N-2N7002_SOT23

2.5V/150mA

5

D

G

S

D

G

Q44

S

N-P0903BD_TO252

D

G

Q84

S

N-P0903BD_TO252

0.9V_REF

R609

10KR0402

C837

C0.1u16Y0402

R595

2.1KR1%0402

C828

R2

X_C0.1u16Y0402

R596

1KR1%0402

Vo=0.8*(R1+R2)/R1

R1

1.2V@4A

Q45

N-P0903BD_TO252

CPU_VDDR

C849

X_C10u6.3X50805

1.2V@2A

VCC_1V2

C832

X_C10u6.3X50805

South bridge All Power Rails: Ramp time is less than 40 ms.

1.2V@1.9A

VCC_SB_1V2

+

12

C834

X_C10u6.3X50805

VDDA_25

EC30

12

+

C143

X_C10u10Y0805

+

12

EC58

.CD1000U6.3EL11.5

+

12

EC32

X_.CD1000U6.3EL11.5

EC79

CD820u2.5SO-RH-1

2

+12V

0.9V

+1.8V_S0_REF +1.8V_S0_FB

R613

R613 1KR1%0402

1KR1%0402

CD100u16EL11-RH

VCC_DDR

R620 4.7KR0402R620 4.7KR0402

VDDA_25

R619 10KR0402R619 10KR0402

U49B

AZ358M-E1_SOIC8-RH

5

+

7

6

-

4 8

R612 1KR1%0402R612 1KR1%0402

R611

20KR1%0402

R648

R648 X_4.7KR0402

X_4.7KR0402

R649

4.7KR0402

B

C154

C154 C4.7U10Y0805

C4.7U10Y0805

B

C830

C0.1u16Y0402

SB700 & RS780 POWER GOOD CIRCUIT

ATX_PWROK27,34

FP_RST#12,18,34

NB_VCC1P1

R625 10KR0402R625 10KR0402

1.2V_REF

R650 X_10KR0402R650 X_10KR0402

SYS_PWRGD

SPEC. H :0.7VCC L: 0.3VCC

D44 S-RB751V-40_SOD323-RHD44 S-RB751V-40_SOD323-RH D45 S-RB751V-40_SOD323-RHD45 S-RB751V-40_SOD323-RH

VCC5_SB

B

C848

C848 X_C1U10Y

X_C1U10Y

U20

1

A1

2

GND A23Y2

X_NC7WZ07P6X_SC70-6

SYS_PWRGD SB_PWRGD

WD_PWRGD18

SB_PWRGD rise time 50 ms; fall time 1 ms de-asserted at least 80 ns before VDD drops 5% from nominal value. de-asserted at least 1 ns before RSMRST# is asserted when entering G3 state.

ATHLON64 PWRGD & ENABLECIRCUIT

D46

X_S-RB751V-40_SOD323-RH

SLP_S3#

R627

VRM_GD6

2

R627

X_4.7KR0402

1

VCC3

D

G

Q53

S

N-P0903BD_TO252

VCC5_SB

R622

4.7KR0402

G

CE

Q87

Q87 N-MMBT3904

N-MMBT3904

CE

Q86

Q86 N-MMBT3904

N-MMBT3904

R624

4.7KR0402

CE

Q90

Q90 N-MMBT3904

N-MMBT3904

6

Y1

5

VCC

4

R629 0R0402R629 0R0402 R667 0R0402R667 0R0402

≒≒

VCC5_SB

R626

R626 X_10KR0402

X_10KR0402

CE

B

Q92

Q92 X_N-MMBT3904

X_N-MMBT3904

Title

Size Document Number Rev

Date: Sheet

1.8V@2A

+1.8V_S0

12

+

C836

EC39

X_C10u6.3X50805

.CD1000U6.3EL11.5

VCC5_SB

R621

R621 10KR0402

10KR0402

DS

Q83

Q83 N-2N7002_SOT23

N-2N7002_SOT23

VCC3_SB

R623

R623 10KR0402

10KR0402

DS

Q89

G

N-2N7002_SOT23

VCC3 +1.8V_S0

VCC3_SB

NB_PWRGDWD_PWRGD

VCC5

DS

Q91

G

X_N-2N7002_SOT23

ACPI Controller UPI

Custom

VL390 0A

DS

G

R617 0R0402R617 0R0402

D43

S-RB751V-40_SOD323-RH

use Slp_s3# control SYS_PWRGD refer to AMD reference circuit

RS740 RS780

R638

R638 X_1KR0402

X_1KR0402

R643

R643 X_4.7KR0402

X_4.7KR0402

R628

R628 X_10KR0402

X_10KR0402

EN_HT

MICRO-START INT'L CO.,LTD.

1

VCORE_EN# 6

Q88

Q88 N-2N7002_SOT23

N-2N7002_SOT23

D42

ATX_PWROK 27,34

S-RB751V-40_SOD323-RH

SYS_PWRGD SLP_S3#

R642

4.7KR0402

NB_PWRGD 6,15

SB_PWRGD 18

26 37Tuesday, September 09, 2008

of

5

4

3

2

1

VTT_DDR POWER

D D

0.75V@2A

C C

Combining VLDT and VDDR For cost down ; All capacitors for VLDT and VDDR must be included

VCC_1V2 CPU_VDDR

B B

Combining VCC_1V2 andVCC_SB_1V2 For cost down

VCC_1V2 VCC_SB_1V2

R190

R190 1KR1%0402

1KR1%0402

+

12

R192

EC27

1KR1%0402

.CD1000U6.3EL11.5

R431 X_0R0805-1R431 X_0R0805-1 R432 X_0R0805-1R432 X_0R0805-1 R480 X_0R0805-1R480 X_0R0805-1 R481 X_0R0805-1R481 X_0R0805-1

R651 X_0R0805-1R651 X_0R0805-1 R652 X_0R0805-1R652 X_0R0805-1 R653 X_0R0805-1R653 X_0R0805-1 R654 X_0R0805-1R654 X_0R0805-1

VCC_DDRVTT_DDR

C268 X_C0.1U16Y0402C268 X_C0.1U16Y0402

C274

C0.1U16Y0402

VCC5_SB

U12

1

VIN

2

GND

3

REFIN

4

VOUT

9

GND

UP7711U8_PSOP8-RH

8

NC3

7

NC2

6

VCNTL

5

NC1

C277

C0.1U16Y0402

VCC5_SB

R630 4.7KR0402R630 4.7KR0402 Q93

R631 4.7KR0402R631 4.7KR0402

S3_STATE18 ATX_PWROK 26,34

R633 X_4.7KR0402R633 X_4.7KR0402

SLP_S5#18,26

1.5V_REF

R569 2KR1%0402R569 2KR1%0402

CE

B

Q94

Q94 N-MMBT3904

N-MMBT3904

B

Q95

Q95 N-MMBT3904

N-MMBT3904

R675

R675 X_1KR1%0402

X_1KR1%0402

R578

2KR1%0402

EN_DDR

DS

Q93

G

N-2N7002_SOT23

DDR_FB7

R632 4.7KR0402R632 4.7KR0402

1.2V_REF0.9V_REF

C37

C838

C0.1u16Y0402

R402

R402 1KR1%0402

1KR1%0402

R583

X_12.1KR1%0402

+12V

X

D37

S-BAT54C_SOT23

5VDIMM

NB__REF

Z

Y

R588 X_0RR588 X_0R

U6

DDR_REF DDR_BOOT

7

Vref

DDR_FB

6

FB

R576

X_12.1KR1%0402

C29 X_C10000p10X0402C29 X_C10000p10X0402

+12V

0.8V

NB_FB

R678

8.06KR1%0402

U41

7

Vref

6

FB

5

3

C98 X_C10000p10X0402C98 X_C10000p10X0402

5

3

VCC

GND

DDR III 1.5V POWER

Y

Z

X

D35

X_S-BAT54A_SOT23

R173

2.2R0805

C142 C1u25X0805C142 C1u25X0805

1

BOOT

VCC

DDR_PHASE

8

PHASE

DDR_HG

2

UG

DDR_LG

4

LG

GND

UP6103S8_SOP8-RH

R586 X_0R0402R586 X_0R0402

R577 3.09KR1%0402R577 3.09KR1%0402

NB_VCC1P1 POWER

D47

X_S-BAT54ALT1G_SOT23

Y

Z

X

R181

2.2R0805

C145 C1u25X0805C145 C1u25X0805

NB_BOOT NB_PHASE

NB_HG NB_LG

R639 X_0R0402R639 X_0R0402

R575 0RR575 0R

1

BOOT

8

PHASE

2

UG

4

LG

UP6103S8_SOP8-RH

R634 3.09KR1%0402R634 3.09KR1%0402

R573 0RR573 0R

C83

C1u25X0805

R640

X_27KR0402

Iocp=225/8.5=26.5

C102

C1u25X0805

R641

R641 X_10KR1%0402

X_10KR1%0402

Iocp=150/8.5=17.65

C71

X_C0.1u16Y0402

D

G

S

D

G

S

X_C0.1u16Y0402

Q15

N-NTD4809NT4G_DPAK3-RH

Q18

N-NTD4806NT4G_DPAK3-RH

1.1V@13A FOR RS780

C103

X_C0.1u16Y0402

D

G

S

D

G

S

X_C0.1u16Y0402

Q38

N-NTD4809NT4G_DPAK3-RH

Q41

N-NTD4806NT4G_DPAK3-RH

5VDIMM_IN

C123

C10u10Y0805

VCC3_IN

C124

C10u10Y0805

+

12

CHOKE5

CH-1.1u27A2.5m-RH

1 2

R589

2.2R0805

C75

C3300p50X0402

+

12

CHOKE9

CH-1.2u15A1.7m-RH

1 2

R674

2.2R0805

C100

C3300p50X0402

EC11

.CD1000U6.3EL11.5

+

12

EC13

.CD1000U6.3EL11.5

+

12

EC64

.CD1000U6.3EL11.5

EC74

.CD1000U6.3EL11.5

+

12

EC14

CD470u6.3SO-RH

C206

C206 C1U10Y

C1U10Y

1 2

C208

C208 C1U10Y

C1U10Y

CHOKE3

CH-1.2u15A3.0m-RH

1 2

+

12

EC22

.CD1000U6.3EL11.5

CHOKE8

CH-1.2u15A3.0m-RH

C99

+

12

EC35

X_.CD1000U6.3EL11.5

5VDIMM

C85

X_C0.1u16Y0402

1.5V@10A+10A

VCC_DDR

+

12

+

12

EC25

.CD1000U6.3EL11.5

VCC3

X_C0.1u16Y0402

1.1V@13A

NB_VCC1P1

EC61

EC31

+

12

+

12

CD100u16EL5-RH

EC21

X_.CD1000U6.3EL11.5

A A

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

Custom

Date: Sheet

5

4

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

NB Core Power & DDR Power

VL390 0A

1

27 37Tuesday, September 09, 2008

of

5

Audio Codec ALC662 (ALC888)

Default is ALC662

HP_SNS

R484 39.2KR1%0402R484 39.2KR1%0402

MIC_SNS

D D

SURRBACK_L

R506 0R0402R506 0R0402

SURRBACK_R

R507 0R0402R507 0R0402

R529

X_22KR0402

FRONT-JD

R449 5.1KR1%0402R449 5.1KR1%0402

LINE1-JD

R450 10KR1%0402R450 10KR1%0402

MIC1-JD

R448 20KR1%0402R448 20KR1%0402

JD resistors should be placed as close as possible to the sense pin of CODEC.

C C

Front Audio Jack

MIC2-VREFO

LINE2-VREFO

B B

MIC_IN-R

C851 C4.7u6.3X50805C851 C4.7u6.3X50805

MIC_IN-L

C852 C4.7u6.3X50805C852 C4.7u6.3X50805

+

HP_OUT-R HP_OUT-L

+

EC60 CD100u16EL5-RH

1 2

+

EC50 CD100u16EL5-RH

1 2

ESD CAP

AC_HP_SNS

For Standby Mode/De-pop

AVDD5

R550

R550 X_22KR0402

X_22KR0402

EC82 CD10U16EL5

EC82 CD10U16EL5 EC83 CD10U16EL5

EC83 CD10U16EL5

Sense_A

HP_OUT-L HP_OUT-R MIC_IN-L MIC_IN-R

VCC3

D29

S-BAT54A_SOT23

Z

D33

S-BAT54A_SOT23

R485 20KR1%0402R485 20KR1%0402 R559 47R1%0402R559 47R1%0402

R463

R463 X_10KR0402

X_10KR0402

45

12

+

46

12

+

47 48

13 14 15 16 17 18 19

20

C609

C0.1U16Y0402

Y X

HP_R_1 HP_L_1

R558

R558 1KR0402

1KR0402 R557

R557 1KR0402

1KR0402 R487

R487 75R0402

75R0402 R498

R498 75R0402

75R0402

D28

D28 ESD-SFI/SFI0603ML080C-LF

ESD-SFI/SFI0603ML080C-LF

D31

D31 ESD-SFI/SFI0603ML080C-LF

ESD-SFI/SFI0603ML080C-LF

D27

D27 ESD-SFI/SFI0603ML080C-LF

ESD-SFI/SFI0603ML080C-LF

AVDD5

C0.1U16Y0402

C0.1U16Y0402 C616

C616

FRONT-R

Sense_B

FRONT-L

R471 20KR1%0402R471 20KR1%0402

36

34

39

40

37

41

35

33

38

U28

NC

JDREF

AVDD2

SURR-L

Sense B

FRONT-L

FRONT-R

SIDE-L

PIN37-VREFO SIDE-R SPDIFI/EAPD SPDIFO

Sense A LINE2-L

REALTEK

LINE2-R MIC2-L

ALC888

MIC2-R CD-L CD-GND

CD-R

DVDD11GPOI0/DMIC-CLK2GPIO1/DMIC-DATA3DVSS14SDATA-OUT5BCLK6DVSS27SDATA-IN8DVDD-IO9SYNC10RESET#11PCBEEP

C608

C607

C0.1U16Y0402

C22p50N0402

R131 4.7KR0402R131 4.7KR0402 R132 4.7KR0402R132 4.7KR0402

R133 4.7KR0402R133 4.7KR0402 R139 4.7KR0402R139 4.7KR0402

12

D32

D32 ESD-SFI/SFI0603ML080C-LF

ESD-SFI/SFI0603ML080C-LF

1/16W, 2.5V, max:25mA

MIC_R MIC_L

HP_L

12

R497

R497 22KR0402

22KR0402

R493

R493 22KR0402

22KR0402

44

42

43

AVSS2

SURR-R

CENTER

R459 22R0402R459 22R0402 R460 22R0402R460 22R0402

R482

R482 22KR0402

22KR0402

R483

R483 22KR0402

22KR0402

Analog Area Digital Area

Audio Power

Digital Area

Trace Width 40mils.

D23

R901

BAS32L_LL34

10R0805

+12V

A A

10R0805

CD100u16EL5-RH

+

12

EC52

C0.1U16Y0402

5

U27

U27 LT1087S_SOT89

LT1087S_SOT89

VIN3VOUT

C590

1

Analog Area

S-1N5817_DO214AC

2

R462

ADJ

100R1%0402

R461

R461 324R1%0402

324R1%0402

Analog Area Digital Area

LFE

LINE1-R

MIC1-VREFO-L

LINE1-VREFO

MIC2-VREFO

LINE2-VREFO

MIC1-VREFO-R

12

AC_HP_SNS

Reference resistor for Jack Detection(close to the codec)

Spilt by DGND

21

MIC1-L

22

MIC1-R

23

LINE1-L

24 25

AVDD1

26

AVSS1

27

VREF

28 29 30 31

32

ALC888-GR-A2-RH

AZ_RST#

AZ_BIT_CLK

JAUD1

1 2 3 4

9 10

_H2X5[8]_green-2.6mm-RH-1

VCC5_SB

D22

39.2KR1%0402

+

12

MIC1-IN-L MIC1-IN-R

LINE1-IN-L LINE1-IN-R

C588 C0.1U16Y0402C588 C0.1U16Y0402

C610 C10u6.3X50805C610 C10u6.3X50805

MIC1-VREFO-L

MIC2-VREFO LINE2-VREFO

MIC1-VREFO-R

AZ_RST# 18,21 AZ_SYNC 18 AZ_SDIN 18 AZ_BIT_CLK 18 AZ_SDOUT 18

MIC_SNS

675

HP_SNS

R486

EC59

EC59 CD100u16EL5-RH

CD100u16EL5-RH

4

Layout Follow Route

PIN.36

PIN.46

PIN.47

PIN.1 PIN.12

AVDD5

AZ_RST#

C591 X_C100P50N0402C591 X_C100P50N0402

AZ_BIT_CLK

C603 X_C1000P50X0402C603 X_C1000P50X0402

AVDD5

R528

C646

X_10KR0402

X_C0.1U16Y0402

R488

R488 20KR1%0402

20KR1%0402

Modify 0828

AVDD5

C615

C615 C0.1U16Y0402

C0.1U16Y0402

4

PIN.25

PIN.24PIN.37

PIN.13PIN.48

Analog Area Digital Area

Rear Phone Jack

3

EC46

+

FRONT-R

FRONT-L

+

1 2

EC47

CD10u16EL5

+

1 2

CD10u16EL5

In order to meet the input/output performance of Vista Premium requirement, 10uF DIP caps. and 22K pull-down resistors.

EC57

EC57 CD100u16EL5-RH

CD100u16EL5-RH

+

F_R_0

1 2

+

1 2

EC56

EC56 CD100u16EL5-RH

CD100u16EL5-RH

R259

R259 22KR0402

22KR0402

R254 4.7KR0402R254 4.7KR0402 R253 4.7KR0402R253 4.7KR0402

EC49

+

1 2

EC48

CD10u16EL5

+

1 2

CD10u16EL5

R252

R252 22KR0402

22KR0402

R255

R255 22KR0402

22KR0402

R256

R256 22KR0402

22KR0402

LINE1-IN-R

MIC1-VREFO-L MIC1-VREFO-R

MIC1-IN-L M_INL_2

In order to meet the input/output performance of Vista Premium requirement, 10uF DIP caps. and 22K pull-down resistors.

M_INR_1MIC1-IN-R

M_INL_1

L_INL_1

75R0402

75R0402 R562

R562 75R0402

75R0402 R563

R563

R260

R260 22KR0402

22KR0402 R282

R282 22KR0402

22KR0402

R257

R257 75R0402

75R0402

R258

R258 75R0402

75R0402

75R0402 R560

R560 75R0402

75R0402 R561

R561

L_INR_0L_INR_1

L_INL_0

F_R_1

F_L_1F_L_0

M_INR_0M_INR_0

M_INL_0

120L600mA-250

120L600mA-250 L34

L34 120L600mA-250

120L600mA-250 L35

L35

120L600mA-250

120L600mA-250 L32

L32 120L600mA-250

120L600mA-250 L33

L33

120L600mA-250

120L600mA-250 L37

L37 120L600mA-250

120L600mA-250 L36

L36

12

D16

D16 ESD-SFI/SFI0603ML080C-LF

ESD-SFI/SFI0603ML080C-LF D18

D18 ESD-SFI/SFI0603ML080C-LF

ESD-SFI/SFI0603ML080C-LF

12

D15

D15 ESD-SFI/SFI0603ML080C-LF

ESD-SFI/SFI0603ML080C-LF D14

D14 ESD-SFI/SFI0603ML080C-LF

ESD-SFI/SFI0603ML080C-LF

12

D13

D13 ESD-SFI/SFI0603ML080C-LF

ESD-SFI/SFI0603ML080C-LF D12

D12 ESD-SFI/SFI0603ML080C-LF

ESD-SFI/SFI0603ML080C-LF

JSPK_OUT HEADER

AVDD5

JSPK_OUT

SURRBACK_L SURRBACK_R

c610 change to X5R;C591 leave empty;R449 change to 1% EC61,EC62 change to C851,C8524.7uX5R;R557,R558 change to 1KR; D33,,R139,R133,R482,R483 leave empty; R253,R254 change to 4.7KR and connect to M_INR_0/M_INL_0; R256,R259 connect to F_R_0/F_L_0

JSPK_OUT

1 2 3 4 5

H2X3[6]_green-RH

R508

R508 33R0402

33R0402

Add for NEC spec0828

EMI

Sense_B

MIC_R MIC_L

HP_L

X_C1000P50X0402

C673

C663

X_C1000P50X0402

3

C660

X_C0.1U16Y0402

C751

LINE1-IN-R

C578 X_C100P50N0402C578 X_C100P50N0402

LINE1-IN-L

C579 X_C100P50N0402C579 X_C100P50N0402

FRONT-R

C614 X_C100P50N0402C614 X_C100P50N0402

FRONT-L

C613 X_C100P50N0402C613 X_C100P50N0402

MIC1-IN-R

C580 X_C100P50N0402C580 X_C100P50N0402

MIC1-IN-L

C581 X_C100P50N0402C581 X_C100P50N0402

For EMI Placement close to Codec chip

C381 C1000P50X0402C381 C1000P50X0402

12

M_INR_2

L_INR_2

L_INL_2LINE1-IN-L

12

LINE1-JD

F_R_2 FRONT-JD

F_L_2

MIC1-JD

2

AUDIO1A

3 10 11 12 13

JACK-AUDIOX3F_PK/GR/BU-RH-4

AUDIO1B

6

7

8

9

JACK-AUDIOX3F_PK/GR/BU-RH-4

AUDIO1C

1

2

4

5

JACK-AUDIOX3F_PK/GR/BU-RH-4

2

16 14 15

18 17

35mm

ALC888/ALC662 Desktop Configuation(5.1 Channel solution)

(3 Jacks at rear panel , 2 jacks at front panel)

Pin Assignment Re-tasking

LINE1 (pin-23/24) FRONT(pin-35/36) MIC1 (pin-21/22)

SURR (pin-39/41) CEN/LFE (pin-43/44)

SIDE-SURR (pin-45/46) LINE2 (pin-14/15)

FMIC (pin-16/17)

CP47CP47

1 2

CP46CP46

1 2

C658

C658 C0.1U16Y0402

C0.1U16Y0402

Tied at one point only under the codec or near the codec

AUDIO PANEL AUDIO1

1

LINE_OUT

LINE IN(A)

LINE OUT(B)

MIC IN(C)

Location

Rear Panel Rear Panel Rear Panel

Rear RCA Jack N/A

N/A Front Panel

Front Panel

Title

Size Document Number Rev

Custom

Date: Sheet

(front channel)

SURROUND or LINE_IN

CENTER-LEF or MIC INPUT

line input AMP output MIC input

Line output Line output

Line output AMP output

Stereo MIC input

TP124TP124

MICRO-START INT'L CO.,LTD.

ALC888

VL390 0A

AVDD5

28 37Tuesday, September 09, 2008

1

28 37Tuesday, September 09, 2008

of

E

POWER CIRCUIT FOR USB PORT 2,3,4,5

VCC5

EC68

12

+

X_.CD1000U6.3EL11.5

U40

5

5VDRV1_EN26

OC#118

4 4

USB_EN25

VCC5

5VDRV1_EN26

OC#318

USB_EN25

3 3

NEAR USB CONNECTOR

SBD2+

SBD2-

USB3+ SBD3+ USB3- SBD3USB2+ SBD2+ USB2- SBD2-

S3#

6

OC#

4

EN

U48

5

S3#

6

OC#

4

EN

SVCC2

U9 ESD-IP4220U9ESD-IP4220

52

6

4

1

3

1

2

5VSB

5VCC

GND

3

VCC5_SB

7

VOUT1

8

VOUT2

UP7533AM8_SOT23-8-RH

SVCC1 SVCC2

C266

EC67

+

12

C0.1U16Y0402

.CD1000U6.3EL11.5

POWER CIRCUIT FOR USB PORT 0,1

Rear

1

2

5VSB

5VCC

GND

3

VCC5_SB

7

VOUT1

8

VOUT2

UP7533AM8_SOT23-8-RH

SVCC3

EC87

+

12

.CD1000U6.3EL11.5

C637

C0.1U16Y0402

REAR PANEL USB CONNECTOR FOR USB PORT 2,3,4,5

USB3+18

SBD3+ SBD3-

USB3-18

USB2+18

USB2-18

22 / 7.5 / 7.5 / 7.5 / 22 / 7.5 / 7.5 / 7.5 / 22

VCC5

5VDRV1_EN26

OC#218

USB_EN25

4

1

L72

X_CMC-L02-9008034-M09

3

2

4

1

L73

X_CMC-L02-9008034-M09

3

2

D

Rear

VCC5_SB

1

2

U45

5

S3#

6

4

SBD2+

SBD2-

OC#

EN

SBD3+

SBD3-

5VCC

VOUT1

5VSB

VOUT2

GND

UP7533AM8_SOT23-8-RH

3

SBD2+ SBD2-

SBD3+ SBD3-

7

8

SVCC2

C513

EC69

+

12

.CD1000U6.3EL11.5

USB1B

16 15

13

14 13

UP

12 11

9

10

9

SECOND

USBAX4M_BLACK-RH-3

C0.1U16Y0402

21 22

C

NEAR USB CONNECTOR

SBD7+ SBD7-

USB6- SBD6USB6+ SBD6+ USB7- SBD7USB7+ SBD7+

POWER CIRCUIT FOR USB PORT 6,7

VCC5

EC73

12

+

X_.CD1000U6.3EL11.5

5VDRV1_EN26

OC#418

USB_EN25

X_.CD1000U6.3EL11.5

1

2

U46

5

S3#

6

OC#

VOUT1

5VSB

5VCC

4

VOUT2

EN

GND

UP7533AM8_SOT23-8-RH

3

POWER CIRCUIT FOR USB PORT 8,9

VCC5

VCC5_SB

1

2

U47

5

5VDRV1_EN26

OC#518

USB_EN25

S3#

6

OC#

4

EN

VOUT1

5VSB

5VCC

VOUT2

GND

UP7533AM8_SOT23-8-RH

3

FRONT PANEL USB CONNECTOR FOR USB PORT 6,7

SVCC4

U29

U29 ESD-IP4220

ESD-IP4220

52

614

SBD6+

SBD6-

3

7

8

VCC5_SB

7

8

USB6+18

USB6-18

USB7+18

USB7-18

B

Front

SVCC4

EC81

C522

12

+

C0.1U16Y0402

.CD1000U6.3EL11.5

Front

SVCC1 SVCC3SVCC2 SVCC4

SVCC5

EC85

+

12

.CD1000U6.3EL11.5

C631

C0.1U16Y0402

12

C717

C251

X_C0.01U16X0402

For EMI Placement close to ESD doide power pin.

X_C0.01U16X0402

22 / 7.5 / 7.5 / 7.5 / 22 / 7.5 / 7.5 / 7.5 / 22

SBD6+

4

1

L62

X_CMC-L02-9008034-M09

3

2

4

1

L61

X_CMC-L02-9008034-M09

3

2

SBD6SBD7+

SBD7-

40 mils

SBD7- SBD6-

_H2X5[9][10]_yellow-RH

12

JUSB1

1 2 3 4 5 6 7 8

C656

A

12

C654

X_C0.01U16X0402

10

SVCC5

SVCC4

12

C655

X_C0.01U16X0402

C625

C625 C0.1U16Y0402

C0.1U16Y0402

EMI

SBD6+SBD7+

SVCC2

U10

U10 ESD-IP4220

2 2

SBD5+

USB5+ SBD5+ USB5- SBD5-

SBD1-

1 1

SBD1+

USB1+ SBD1+ USB1- SBD1USB0+ SBD0+ USB0- SBD0-

SBD5-

52

614

SVCC3

52

614

3

U13

U13 ESD-IP4220

ESD-IP4220

3

E

SBD4SBD4+

SBD4+USB4+ SBD4-USB4-

SBD0SBD0+

USB5+18

USB5-18

USB4+18

USB4-18

REAR PANEL USB CONNECTOR FOR USB PORT 0,1

USB1+18

USB1-18

USB0+18

USB0-18

ESD-IP4220

4

1

3

2

4

1

3

2

4

1

3

2

4

1

3

2

SBD5+

L74

X_CMC-L02-9008034-M09

SBD5-

SBD4+

L75

X_CMC-L02-9008034-M09

SBD4-

SBD1+

L76

X_CMC-L02-9008034-M09

SBD1-

SBD0+

L80

X_CMC-L02-9008034-M09

SBD0-

D

SBD0SBD0+

SBD1SBD1+

SBD4+ SBD4-

SBD5+ SBD5-

SVCC1

SVCC3

USB1A

8 17 7

5

6 5

THIRD

4 3

1

2 1

DOWN

USBAX4M_BLACK-RH-3

X_C0.1U16Y0402

X_C0.1U16Y0402 C718

C718

LAN_USB1A

5

PWR

6

USB-

7

USB+

8

GND

1

PWR

2

USB-

3

USB+

4

GND

RJ45_USBX2_LEDX2_TX-GIGA-RH-1

UP

DOWN

23

GND

24

GND

25

GND

26

GND

27

GND

28

GND

29

GND

30

GND

18 19 20

SBD8+ SBD8-

USB8+ SBD8+

C

SVCC5

U35

U35 ESD-IP4220

ESD-IP4220

52

6

4

1

3

USB9- SBD9USB9+ SBD9+ USB8- SBD8-

USB CARD READER + IR MODULE FOR USB PORT 8,9

4

SBD9+

SBD9-

USB9+18

USB9-18

USB8+18

USB8-18

B

1

3

2

4

1

3

2

L63

X_CMC-L02-9008034-M09

L64

X_CMC-L02-9008034-M09

Title

Size Document Number Rev

Custom

Date: Sheet

Modify USB Pinhead

SBD9+

SBD9-

SBD8+

40 mils

SBD8-

JUSB2

SBD9- SBD8-

USB CONNECTORS

VL390 0A

1 2 3 4 5 6 7 8

10

_H2X5[9][10]_yellow-RH

MICRO-START INT'L CO.,LTD.

A

SVCC5

C629

C629 C0.1U16Y0402

C0.1U16Y0402

EMI

SBD8+SBD9+

29 37Tuesday, September 09, 2008

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8

7

6

5

4

3

2

1

PCI Express Slot x16/x1

VCC3

R332 X_4.7KR0402R332 X_4.7KR0402 R328 X_4.7KR0402R328 X_4.7KR0402 R369 X_4.7KR0402R369 X_4.7KR0402

D D

C C

B B

A A

R329 X_4.7KR0402R329 X_4.7KR0402

SW_GFX_TXC_0P33 SW_GFX_TXC_0N33

SW_GFX_TXC_1P33 SW_GFX_TXC_1N33

SW_GFX_TXC_2P33 SW_GFX_TXC_2N33

SW_GFX_TXC_3P33 SW_GFX_TXC_3N33

GFX_TXC_4P14 GFX_TXC_4N14

GFX_TXC_5P14 GFX_TXC_5N14

GFX_TXC_6P14 GFX_TXC_6N14

GFX_TXC_7P14 GFX_TXC_7N14

GFX_TXC_8P14 GFX_TXC_8N14

GFX_TXC_9P14 GFX_TXC_9N14

GFX_TXC_10P14

GFX_TXC_10N14

GFX_TXC_11P14

GFX_TXC_11N14

GFX_TXC_12P14

GFX_TXC_12N14

GFX_TXC_13P14

GFX_TXC_13N14

GFX_TXC_14P14

GFX_TXC_14N14

GFX_TXC_15P14

GFX_TXC_15N14

8

DP_AUX1P_CON PE_TMS PE_TCK TMDS_HPD1_CON

SW_GFX_TXC_0P SW_GFX_TXC_0N

SW_GFX_TXC_1P SW_GFX_TXC_1N

SW_GFX_TXC_2P SW_GFX_TXC_2N

SW_GFX_TXC_3P SW_GFX_TXC_3N

GFX_TXC_4P GFX_TXC_4N

GFX_TXC_5P GFX_TXC_5N

GFX_TXC_6P GFX_TXC_6N

GFX_TXC_7P GFX_TXC_7N

GFX_TXC_8P GFX_TXC_8N

GFX_TXC_9P GFX_TXC_9N

GFX_TXC_10P GFX_TXC_10N

GFX_TXC_11P GFX_TXC_11N

GFX_TXC_12P GFX_TXC_12N

GFX_TXC_13P GFX_TXC_13N

GFX_TXC_14P GFX_TXC_14N

GFX_TXC_15P GFX_TXC_15N

SCLK118,24,31,32 SDATA118,24,31,32

VCC3

VCC3_SB

WAKE#18,24

C415 C0.1U10X0402C415 C0.1U10X0402 C414 C0.1U10X0402C414 C0.1U10X0402

C424 C0.1U10X0402C424 C0.1U10X0402 C420 C0.1U10X0402C420 C0.1U10X0402

C421 C0.1U10X0402C421 C0.1U10X0402 C425 C0.1U10X0402C425 C0.1U10X0402

C426 C0.1U10X0402C426 C0.1U10X0402 C422 C0.1U10X0402C422 C0.1U10X0402

C427 C0.1U10X0402C427 C0.1U10X0402 C428 C0.1U10X0402C428 C0.1U10X0402

C429 C0.1U10X0402C429 C0.1U10X0402 C430 C0.1U10X0402C430 C0.1U10X0402

C423 C0.1U10X0402C423 C0.1U10X0402 C431 C0.1U10X0402C431 C0.1U10X0402

C432 C0.1U10X0402C432 C0.1U10X0402 C433 C0.1U10X0402C433 C0.1U10X0402

C434 C0.1U10X0402C434 C0.1U10X0402 C435 C0.1U10X0402C435 C0.1U10X0402

C436 C0.1U10X0402C436 C0.1U10X0402 C437 C0.1U10X0402C437 C0.1U10X0402

C438 C0.1U10X0402C438 C0.1U10X0402 C439 C0.1U10X0402C439 C0.1U10X0402

C440 C0.1U10X0402C440 C0.1U10X0402 C441 C0.1U10X0402C441 C0.1U10X0402

C442 C0.1U10X0402C442 C0.1U10X0402 C443 C0.1U10X0402C443 C0.1U10X0402

C444 C0.1U10X0402C444 C0.1U10X0402 C445 C0.1U10X0402C445 C0.1U10X0402

C416 C0.1U10X0402C416 C0.1U10X0402 C417 C0.1U10X0402C417 C0.1U10X0402

C418 C0.1U10X0402C418 C0.1U10X0402 C419 C0.1U10X0402C419 C0.1U10X0402

C521

X_C0.1u16Y0402

C0.1U16Y0402

7

WAKE#

EXP_A_TXP_0_C EXP_A_TXN_0_C

EXP_A_TXP_1_C EXP_A_TXN_1_C

EXP_A_TXP_2_C EXP_A_TXN_2_C

EXP_A_TXP_3_C EXP_A_TXN_3_C

EXP_A_TXP_4_C EXP_A_TXN_4_C

EXP_A_TXP_5_C EXP_A_TXN_5_C

EXP_A_TXP_6_C EXP_A_TXN_6_C

EXP_A_TXP_7_C EXP_A_TXN_7_C

EXP_A_TXP_8_C EXP_A_TXN_8_C

EXP_A_TXP_9_C EXP_A_TXN_9_C

EXP_A_TXP_10_C EXP_A_TXN_10_C

EXP_A_TXP_11_C EXP_A_TXN_11_C

EXP_A_TXP_12_C EXP_A_TXN_12_C

EXP_A_TXP_13_C EXP_A_TXN_13_C

EXP_A_TXP_14_C EXP_A_TXN_14_C

EXP_A_TXP_15_C EXP_A_TXN_15_C

C403

C0.1U16Y0402

SCLK1

SDATA1

TMDS_HPD1_CON

C400

C523

X_C0.1u16Y0402

PCI EXPRESS x16 Slot PCI EXPRESS 1 Slot-1

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18

A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32

A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49

A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82

+

12

EC44

C0.1U16Y0402

+12V

COMM_EN 15,33

PE_TCK DP_AUX1P_CON

PE_TMS

PE_GF_RST#_A

PE16_GXF_CLK PE16_GXF_CLK#

GFX_RX0P GFX_RX0N

GFX_RX1P GFX_RX1N

GFX_RX2P GFX_RX2N

GFX_RX3P GFX_RX3N

GFX_RX4P GFX_RX4N

GFX_RX5P GFX_RX5N

GFX_RX6P GFX_RX6N

GFX_RX7P GFX_RX7N

GFX_RX8P GFX_RX8N

GFX_RX9P GFX_RX9N

GFX_RX10P GFX_RX10N

GFX_RX11P GFX_RX11N

GFX_RX12P GFX_RX12N

GFX_RX13P GFX_RX13N

GFX_RX14P GFX_RX14N

GFX_RX15P GFX_RX15N

VCC3_SBVCC3+12VVCC3_SBVCC3+12V

C490

C447

X_C0.1u16Y0402

5

GFX_RX0P 14 GFX_RX0N 14

GFX_RX1P 14 GFX_RX1N 14

GFX_RX2P 14 GFX_RX2N 14

GFX_RX3P 14 GFX_RX3N 14

GFX_RX4P 14 GFX_RX4N 14

GFX_RX5P 14 GFX_RX5N 14

GFX_RX6P 14 GFX_RX6N 14

GFX_RX7P 14 GFX_RX7N 14

GFX_RX8P 14 GFX_RX8N 14

GFX_RX9P 14 GFX_RX9N 14

GFX_RX10P 14 GFX_RX10N 14

GFX_RX11P 14 GFX_RX11N 14

GFX_RX12P 14 GFX_RX12N 14

GFX_RX13P 14 GFX_RX13N 14

GFX_RX14P 14 GFX_RX14N 14

GFX_RX15P 14 GFX_RX15N 14

C446

C0.1U16Y0402

+12V

C401

C401 C0.1U16Y0402

C0.1U16Y0402

PCIE16_X1

X2

B1

12V#B1

B2

12V#B2

B3

RSVD#B3

B4

GND#B4

B5

SMCLK

B6

SMDAT

B7

GND#B7

B8

3.3V#B8

B9

JTAG1

B10

3.3VAUX

B11

WAKE#

B12

RSVD#B12

B13

GND#B13

B14

HSOP0

B15

HSON0

B16

GND#B16

B17

PRSNT2#

B18

GND#B18

B19

HSOP1

B20

HSON1

B21

GND#B21

B22

GND#B22

B23

HSOP2

B24

HSON2

B25

GND#B25

B26

GND#B26

B27

HSOP3

B28

HSON3

B29

GND#B29

B30

RSVD#B30

B31

PRSNT2##B31

B32

GND#B32

B33

HSOP4

B34

HSON4

B35

GND#B35

B36

GND#B36

B37

HSOP5

B38

HSON5

B39

GND#B39

B40

GND#B40

B41

HSOP6

B42

HSON6

B43

GND#B43

B44

GND#B44

B45

HSOP7

B46

HSON7

B47

GND#B47

B48

PRSNT2##B48

B49

GND#B49

B50

HSOP8

B51

HSON8

B52

GND#B52

B53

GND#B53

B54

HSOP9

B55

HSON9

B56

GND#B56

B57

GND#B57

B58

HSOP10

B59

HSON10

B60

GND#B60

B61

GND#B61

B62

HSOP11

B63

HSON11

B64

GND#B64

B65

GND#B65

B66

HSOP12

B67

HSON12

B68

GND#B68

B69

GND#B69

B70

HSOP13

B71

HSON13

B72

GND#B72

B73

GND#B73

B74

HSOP14

B75

HSON14

B76

GND#B76

B77

GND#B77

B78

HSOP15

B79

HSON15

B80

GND#B80

B81

PRSNT2##B81

B82

RSVD#B82

X1

SLOT-PCI164P_BLACK-2PITCH-RH-13

X_C0.1u16Y0402

Placement Close To PCIE16_X1Placement Between at PCIE_X1

6

PRSNT1#

12V

12V#A3

GND

JTAG2 JTAG3 JTAG4 JTAG5

3.3V

3.3V#A10 PWRGD

GND#A12 REFCLK+

REFCLK-

GND#A15

HSIP0 HSIN0

GND#A18

RSVD

GND#A20

HSIP1

HSIN1 GND#A23 GND#A24

HSIP2

HSIN2 GND#A27 GND#A28

HSIP3

HSIN3 GND#A31

RSVD#A32

RSVD#A33

GND#A34

HSIP4

HSIN4 GND#A37 GND#A38

HSIP5

HSIN5 GND#A41 GND#A42

HSIP6

HSIN6 GND#A45 GND#A46

HSIP7

HSIN7 GND#A49

RSVD#A50

GND#A51

HSIP8

HSIN8 GND#A54 GND#A55

HSIP9

HSIN9 GND#A58 GND#A59

HSIP10

HSIN10 GND#A62 GND#A63

HSIP11

HSIN11 GND#A66 GND#A67

HSIP12

HSIN12 GND#A70 GND#A71

HSIP13

HSIN13 GND#A74 GND#A75

HSIP14

HSIN14 GND#A78 GND#A79

HSIP15

HSIN15 GND#A82

C448

C492

C0.1U16Y0402

CD470u16EL11.5-RH

PESW_1.8V

R407

4.7KR0402

G

D

Q110

N-2N7002_SOT23

VCC3

From Clock Gen

PE16_GXF_CLK 12 PE16_GXF_CLK# 12

PESW_1.8VPESW_1.8V

R473

4.7KR0402

S

R474

4.7KR0402

SLI_SWITCH

SLI_SWITCH 33

Modify 0901

Connected to A_RST# ANDed with Southbridge GPIO (S5 domain).

GFX16_PCIERST#18

PE_GF_RST#17

4

+12V +12V

PCIE1_X1

VCC3

VCC3_SB

SCLK1 SDATA1

WAKE#

GPP_TX0P14 GPP_TX0N14

C402 C0.1U10X0402C402 C0.1U10X0402 C404 C0.1U10X0402C404 C0.1U10X0402

GPP_TX0P_C GPP_TX0N_C

VCC3

U54

NC7SZ08M5X_SOT23-5-RH

53

VCC

1

A

B

2

GND

PE_GF_RST#_APE_GF_RST#_A

4

Y

PCIE1_X1

B1

12V

B2

12V#B2

B3

RSVD

B4

GND

B5

SMCLK

B6

SMDATA

B7

GND#B7

B8

3.3V

B9

JTAG1

B10

3.3VAUX

B11

WAKE_#

B12

RSVD#B12

B13

GND#B13

B14

HSOP0+

B15

HSOP0-

B16

GND#B16

B17

PRSNT2_#

B18

GND#B18

SLOT-PCI36_WHITE-2PITCH-RH-4

PRSNT1_#

12V#A2 12V#A3

GND#A4

JTAG2 JTAG3 JTAG4 JTAG5

3.3V#A9

3.3V#A10 PWRGD

GND#A12 REFCLK+

REFCLK-

GND#A15

HSIP0+

HSIP0-

GND#A18

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 X1

X1

A12 A13 A14 A15 A16 A17 A18 X2

X2

TP152TP152

TP153TP153 TP154TP154

TP156TP156 TP157TP157

VCC3

PE_GF_RST#_A

PE1_GPP_CLK1 12 PE1_GPP_CLK1# 12

GPP_RX0P 14 GPP_RX0N 14

PE_GF_RST#_A

PE16_GXF_CLK PE16_GXF_CLK#

PE1_GPP_CLK1 PE1_GPP_CLK1#

R299 X_0R0402R299 X_0R0402

MICRO-START INT'L CO.,LTD.

Title

PCI EXPRESS X16 & X1 SLOT

Size Document Number Rev

Custom

Date: Sheet

3

Date: Sheet of

2

MICRO-START INT'L CO.,LTD.

VL390 0A

of

30 37Tuesday, September 09, 2008

1

8

7

6

5

4

3

2

1

PCI SLOT 1 (PCI VER: 2.3 COMPLY)

FRAME# IRDY# DEVSEL# TRDY#

SERR# PERR# LOCK# STOP#

PCI_INTD# PCI_INTC# PCI_INTA# PCI_INTB#

AD[31..0] C_BE#[3..0]

PCI_CLK017 PREQ#017

VCC5

PCI_INTB# PCI_INTD#

PREQ#0 AD31

AD29 AD27

AD25 C_BE#3

AD23 AD21

AD19 AD17

C_BE#2 IRDY# DEVSEL# LOCK#

PERR# SERR# C_BE#1

AD14 AD12

AD10

AD8 AD7

AD5 AD3

AD1 ACK#64

VCC3

-12V

PCI1

B1

-12V

B2

TCK

B3

GND#B3

B4

TDO

B5

+5V#B5

B6

+5V#B6

B7

INTB#

B8

INTD#

B9

PRSNT#1

B10

RESERVED#B10

B11

PRSNT#2

B12

GND#B12

B13

GND#B13

B14

RESERVED#B14

B15

GND#B15

B16

CLK

B17

GND#B17

B18

REQ#

B19

+5V(I/O)#B19

B20

AD31

B21

AD29

B22

GND#B22

B23

AD27

B24

AD25

B25

+3.3V#B25

B26

C/BE#3

B27

AD23

B28

GND#B28

B29

AD21

B30

AD19

B31

+3.3V#B31

B32

AD17

B33

C/BE#2

B34

GND#B34

B35

IRDY#

B36

+3.3V#B36

B37

DEVSEL#

B38

GND#B38

B39

LOCK#

B40

PERR#

B41

+3.3V#B41

B42

SERR#

B43

+3.3V#B43

B44

C/BE#1

B45

AD14

B46

GND#B46

B47

AD12

B48

AD10

B49

GND#B49

X1

B52

AD8

B53

AD7

B54

+3.3V#B54

B55

AD5

B56

AD3

B57

GND#B57

B58

AD1

B59

+5V(I/O)#B59

B60

ACK64#

B61

+5V#B61

B62

+5V#B62

SLOT-PCI120_white-RH

IDSEL = AD16 MASTER = PREQ#0

TRST#

+12V

INTA#

INTC#

+5V#A8

RESERVED

+5V(I/O)

RESERVED#A11

GND

GND#A13

3.3VAUX RST#

+5V(I/O)#A16

GNT#

GND#A18

PME#

AD30

+3.3V

AD28 AD26

GND#A24

AD24

IDSEL

AD22 AD20

GND#A30

AD18 AD16

+3.3V#A33

FRAME#

GND#A35

TRDY#

GND#A37

STOP#

+3.3V#A39

SMBCLK SMBDAT

GND#A42

AD15

+3.3V#A45

AD13 AD11

GND#A48

C/BE#0

+3.3V#A53

GND#A56

+5V(I/O)#A59

REQ64# +5V#A61 +5V#A62

TMS

+3.3

PAR

AD9

AD6 AD4

AD2 AD0

+12V

A1 A2 A3 A4

TDI

A5

+5V

A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 X2

X2

A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62

VCC5

VCC3

PCIRST_SLOT1#

R458 330R0402R458 330R0402

PCI_INTA# PCI_INTC#

PCI_PME# AD30

AD28 AD26

AD24

AD22 AD20

AD18 AD16

FRAME# TRDY# STOP# SCLK1

SDATA1 PAR

AD15 AD13

AD11 AD9

C_BE#0 AD6

AD4 AD2

AD0 REQ#64

VCC3_SB

PCIRST_SLOT1# 17 PGNT#0 17 PCI_PME# 18

AD16

SCLK1 18,24,30,32 SDATA1 18,24,30,32

PAR 17

ACK#64

REQ#64

R445 8.2KR0402R445 8.2KR0402 R433 8.2KR0402R433 8.2KR0402

VCC3

AD[31..0]17

C_BE#[3..0]17

AD[31..0]17

C_BE#[3..0]17

D D

FRAME#17

IRDY#17

DEVSEL#17

TRDY#17

C C

SERR#17 PERR#17 LOCK#17

STOP#17

PCI_INTD#17 PCI_INTC#17 PCI_INTA#17 PCI_INTB#17

PCI PULL-UP / DOWN RESISTORS

B B

AD[31..0] C_BE#[3..0]

PCI_CLK117 PREQ#117

PCI_INT A, B, C, D

PCI SLOT 2 (PCI VER: 2.3 COMPLY)

-12V

PCI2

B1

-12V

B2

TCK

B3

GND#B3

B4

TDO

B5

VCC5

PCI_INTC# PCI_INTA#

PREQ#1 AD31

AD29 AD27

AD25 C_BE#3

AD23 AD21

AD19 AD17

C_BE#2 IRDY# DEVSEL# LOCK#

PERR# SERR# C_BE#1

AD14 AD12

AD10

AD8 AD7

AD5 AD3

AD1 ACK#64

VCC3

+5V#B5

B6

+5V#B6

B7

INTB#

B8

INTD#

B9

PRSNT#1

B10

RESERVED#B10

B11

PRSNT#2

B12

GND#B12

B13

GND#B13

B14

RESERVED#B14

B15

GND#B15

B16

CLK

B17

GND#B17

B18

REQ#

B19

+5V(I/O)#B19

B20

AD31

B21

AD29

B22

GND#B22

B23

AD27

B24

AD25

B25

+3.3V#B25

B26

C/BE#3

B27

AD23

B28

GND#B28

B29

AD21

B30

AD19

B31

+3.3V#B31

B32

AD17

B33

C/BE#2

B34

GND#B34

B35

IRDY#

B36

+3.3V#B36

B37

DEVSEL#

B38

GND#B38

B39

LOCK#

B40

PERR#

B41

+3.3V#B41

B42

SERR#

B43

+3.3V#B43

B44

C/BE#1

B45

AD14

B46

GND#B46

B47

AD12

B48

AD10

B49

GND#B49

X1

B52

AD8

B53

AD7

B54

+3.3V#B54

B55

AD5

B56

AD3

B57

GND#B57

B58

AD1

B59

+5V(I/O)#B59

B60

ACK64#

B61

+5V#B61

B62

+5V#B62

SLOT-PCI120_white-RH

RESERVED

RESERVED#A11

GND#A13

3.3VAUX

+5V(I/O)#A16

GND#A18

GND#A24

GND#A30

+3.3V#A33

FRAME#

GND#A35 GND#A37

+3.3V#A39

SMBCLK SMBDAT

GND#A42

+3.3V#A45

GND#A48

+3.3V#A53

GND#A56

+5V(I/O)#A59

REQ64# +5V#A61 +5V#A62

IDSEL = AD17 MASTER = PREQ#1 PCI_INT B, C, D, A

TRST#

+12V

TMS

+5V INTA# INTC#

+5V#A8 +5V(I/O)

GND

RST# GNT# PME#

AD30 +3.3V

AD28

AD26

AD24 IDSEL

+3.3 AD22 AD20

AD18 AD16

TRDY# STOP#

PAR

AD15 AD13

AD11

AD9

C/BE#0

AD6

AD4

AD2

AD0

+12V

A1 A2 A3 A4

TDI

X2

VCC5

A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 X2

A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62

PCI_INTB# PCI_INTD#

VCC3

PCIRST_SLOT1#

PCI_PME# AD30

AD28 AD26

AD24

R466 330R0402R466 330R0402

AD22 AD20

AD18 AD16

FRAME# TRDY# STOP# SCLK1

SDATA1 PAR

AD15 AD13

AD11 AD9

C_BE#0 AD6

AD4 AD2

AD0 REQ#64

VCC3_SB

PGNT#1 17 PCI_PME# 18

AD17

SCLK1 18,24,30,32 SDATA1 18,24,30,32

PAR 17

PCI SLOT DECOUPLING CAPACITORS

+

EC54

1 2

.CD1000U6.3EL11.5

C500

C500 X_C0.1U16Y0402

X_C0.1U16Y0402 C562

C562 X_C0.1U16Y0402

X_C0.1U16Y0402

A A

8

7

6

+12V -12V

C560

C560 C0.1U16Y0402

C0.1U16Y0402 C602

C602 X_C0.1U16Y0402

X_C0.1U16Y0402 C593

C593 X_C0.1U16Y0402

X_C0.1U16Y0402

5

.CD1000U6.3EL11.5 C563

C563 C0.1U16Y0402

C0.1U16Y0402 C601

C601 C0.1U16Y0402

C0.1U16Y0402 C624

C624 X_C0.1U16Y0402

X_C0.1U16Y0402 C622

C622 C0.1U16Y0402

C0.1U16Y0402 C596

C596 X_C0.1U16Y0402

X_C0.1U16Y0402

C623

C623 C0.1U16Y0402

C0.1U16Y0402 C559

C559 X_C0.1U16Y0402

X_C0.1U16Y0402

VCC3VCC5 VCC3

+

1 2

4

EC55

EC55 X_.CD1000U6.3EL11.5

X_.CD1000U6.3EL11.5 C600

C600 C0.1U16Y0402

C0.1U16Y0402 C595

C595 C0.1U16Y0402

C0.1U16Y0402 C598

C598 X_C0.1U16Y0402

X_C0.1U16Y0402 C597

C597 X_C0.1U16Y0402

X_C0.1U16Y0402 C594

C594 X_C0.1U16Y0402

X_C0.1U16Y0402

VCC3_SBVCC5

C561

C561 C0.1U16Y0402

C0.1U16Y0402 C592

C592 C0.1U16Y0402

C0.1U16Y0402 C599

C599 X_C0.1U16Y0402

X_C0.1U16Y0402

TP161TP161

TP162TP162

MICRO-START INT'L CO.,LTD.

Title

PCI SLOT 1

Size Document Number Rev

Custom

Date: Sheet

3

Date: Sheet

2

MICRO-START INT'L CO.,LTD.

VL390 0A

PCI_CLK0

PCIRST_SLOT1#

31 37Tuesday, September 09, 2008

1

of

8

D D

7

6

5

VCC3

4

3

2

1

TPM - Security Controller

C668

X_C0.1U16Y0402

VSB

PP

X_C0.1U16Y0402

10 19 24

4 11 18 25

5

7

13 14

8

C659

C12P50N0402

C665

C0.1U16Y0402

VCC3_SB

1 2

VCC3

U25

R552

X_0R0402

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_FRAME# PCIRST_TPM# TPMLPCPD# SERIRQ

R532

R532 10KR0402

10KR0402

C C

B B

TPMLPCPD#

LPC_AD017,25 LPC_AD117,25 LPC_AD217,25 LPC_AD317,25

PCI_CLK417,21

LPC_FRAME#17,25

PCIRST_TPM#17

SERIRQ17,25

R546 X_0R0402R546 X_0R0402

R533 4.7KR0402R533 4.7KR0402

VCC3

PCI_CLKRUN#17

26

LAD0

23

LAD1

20

LAD2

17

LAD3

21

LCLK

22

LFRAME#

16

LRESET#

28

LPCPD#

27

SERIRQ

9

TESTBI/BADD

15

CLKRUN#

6

R551

R551 0R0402

0R0402

B0C-0963512(SLB9635TT1.2-RH)

GPIO

2

GPIO2

1

NC

3

NC

12

NC

VDD VDD VDD

GND GND GND GND

XTALI

XTALO

TESTI

C664

C664 X_C0.1U16Y0402

X_C0.1U16Y0402

C669

C669 C0.1U16Y0402

C0.1U16Y0402

Y8

32.768KHZ12.5P_D-LF

3 4

C671

C12P50N0402

CPU Thermo Sense

VCC3

/N

TALERT2#

VCC3

R524 X_0R0402R524 X_0R0402 R525 X_0R0402R525 X_0R0402 R527 X_1KR0402R527 X_1KR0402

THERMDA_CPU7,25 THERMDC_CPU7,25

U37

1

VCC

2 3 4

SCL

D+

SDA

D-

ALERT#

THERM#

GND

X_SNSR-F75383S-LF

SCLK1

8 7 6 5

SDATA1HWM_D+ TALERT1#HWM_D-

SCLK1 18,24,30,31 SDATA1 18,24,30,31

/N

R526 X_1KR0402R526 X_1KR0402

VCC3

HWM_D+

C782

Place close to F75383.

HWM_D-

A A

TP163TP163

TP164TP164

8

7

6

5

4

PCIRST_TPM#

PCI_CLK4

3

C782

X_C3300P50X0402

Title

Size Document Number Rev

B

Date: Sheet

VCC3

MICRO-START INT'L CO.,LTD.

TMP/Asset ID/HWM W83201G

VL390 0A

2

/N

C781 X_C10u6.3X50805C781 X_C10u6.3X50805

32 37Tuesday, September 09, 2008

of

1

5

e

4

3

2

1

PESW_1.8V

DPC_LINE0_DP

5

U24

D D

GFX_TXC_0N14 GFX_TXC_0P14

GFX_TXC_1N14 GFX_TXC_1P14

SLI_SWITCH30

GFX_TXC_2N14 GFX_TXC_2P14

GFX_TXC_3N14 GFX_TXC_3P14

C C

GFX_TXC_0N GFX_TXC_0P

GFX_TXC_1N GFX_TXC_1P

SLI_SWITCH

GFX_TXC_2N GFX_TXC_2P

GFX_TXC_3N GFX_TXC_3P

2

A0

3

A1

6

A2

7

A3

9

SEL

11

A4

12

A5

15

A6

16

A7

GND

1

40

VDD

VDD8VDD13VDD30VDD18VDD20VDD42VDD

GND

GND4GND14GND17GND19GND21GND39GND41GND

GND

10

0B1 1B1

2B1 3B1

0B2 1B2

2B2 3B2

4B1 5B1

6B1 7B1

4B2 5B2

6B2 7B2

PI2PCIE2412ZHE_TQFN42-RH

43

37 36

35 34

33 32

31 29

28 27

26 25

24 23

22

SW_DPC_LINE0_DP SW_DPC_LINE1_DN

SW_DPC_LINE1_DP SW_GFX_TXC_0N

SW_GFX_TXC_0P SW_GFX_TXC_1N

SW_GFX_TXC_1P SW_DPC_LINE2_DN

SW_DPC_LINE2_DP SW_DPC_LINE3_DN

SW_DPC_LINE3_DP SW_GFX_TXC_2N

SW_GFX_TXC_2P SW_GFX_TXC_3N

SW_GFX_TXC_3P

SW_DPC_LINE0_DN

38

SW_GFX_TXC_0N 30 SW_GFX_TXC_0P 30

SW_GFX_TXC_1N 30 SW_GFX_TXC_1P 30

SW_GFX_TXC_2N 30 SW_GFX_TXC_2P 30

SW_GFX_TXC_3N 30 SW_GFX_TXC_3P 30

R310

X_1KR/4

R311

X_1KR/4

A C

VCC3

S-1N5817_DO214AC

D19

SW_DPC_LINE0_DP

SW_DPC_LINE0_DN

SW_DPC_LINE1_DP

SW_DPC_LINE1_DN

SW_DPC_LINE2_DP

R312

X_1KR/4

SW_DPC_LINE2_DN SW_DPC_LINE3_DP

R314

X_1KR/4

SW_DPC_LINE3_DN

DPC_AUX_DP

B B

DPC_AUX_DN

C337 C0.1U16X0402C337 C0.1U16X0402

C336 C0.1U16X0402C336 C0.1U16X0402

R285

100KR/2

DPC_AUX_DP_C

DPC_AUX_DN_C

R284

R284 100KR/2

100KR/2

DPC_LINE0_DN DPC_LINE1_DP

DPC_LINE1_DN DPC_LINE2_DP

DPC_LINE2_DN DPC_LINE3_DP

DPC_LINE3_DN

DPC_AUX_DP DPC_AUX_DN

DPC_HPD

FS3

1 2

1.1A/6V/0.21ohm

DP_PWR

C176 C0.1U16X0402C176 C0.1U16X0402

C172 C0.1U16X0402C172 C0.1U16X0402

C173 C0.1U16X0402C173 C0.1U16X0402

C166 C0.1U16X0402C166 C0.1U16X0402

C164 C0.1U16X0402C164 C0.1U16X0402

C162 C0.1U16X0402C162 C0.1U16X0402 C161 C0.1U16X0402C161 C0.1U16X0402

C155 C0.1U16X0402C155 C0.1U16X0402

VCC3

C472 C0.1u16X0402-2C472 C0.1u16X0402-2

VCC5

C469

C469 C4.7u6.3X5

A A

C4.7u6.3X5

C459

C459 C0.1u16X0402-2

C0.1u16X0402-2

4

U33

4

VIN3VOUT

ADJ/GND

AMS1117_SOT223-3

1

2

REG_CTRL

500mA

R455

R455 240R1%0402

240R1%0402

R457

R457 100R1%0402

100R1%0402

PESW_1.8V

C4.7u6.3X5

C456

C0.1u16X0402-2

C470

C473 C0.1u16X0402-2C473 C0.1u16X0402-2 C475 C0.1u16X0402-2C475 C0.1u16X0402-2 C476 C0.1u16X0402-2C476 C0.1u16X0402-2 C396 C0.1u16X0402-2C396 C0.1u16X0402-2 C477 C0.1u16X0402-2C477 C0.1u16X0402-2 C405 C0.1u16X0402-2C405 C0.1u16X0402-2 C452 C0.1u16X0402-2C452 C0.1u16X0402-2 C453 C0.1u16X0402-2C453 C0.1u16X0402-2 C398 C0.1u16X0402-2C398 C0.1u16X0402-2

PESW_1.8VPESW_1.8V

C397 C0.1u16X0402-2C397 C0.1u16X0402-2

5

4

3

C478 C0.1u16X0402-2C478 C0.1u16X0402-2 C480 C0.1u16X0402-2C480 C0.1u16X0402-2 C481 C0.1u16X0402-2C481 C0.1u16X0402-2

C449 C0.1u16X0402-2C449 C0.1u16X0402-2 C454 C0.1u16X0402-2C454 C0.1u16X0402-2 C399 C0.1u16X0402-2C399 C0.1u16X0402-2 C455 C0.1u16X0402-2C455 C0.1u16X0402-2 C409 C0.1u16X0402-2C409 C0.1u16X0402-2 C406 C0.1u16X0402-2C406 C0.1u16X0402-2

DISPLAYPORT1

1

ML_LANE_0P

2

GND

3

ML_LANE_0N

4

ML_LANE_1P

5

GND

6

ML_LANE_1N

7

ML_LANE_2P

8

GND

9

ML_LANE_2N

10

ML_LANE_3P

11

GND

12

ML_LANE_3N

13

GND

14

GND

15

AUX_CHP

16

GND

17

AUX_CHN

18

HOT PLUG DETECT

19

RETURN DP_PWR

20

DP_PWR

DPC_LINE0_DP

DPC_LINE0_DN

DPC_LINE1_DP

DPC_LINE1_DN

DPC_LINE2_DP

DPC_LINE2_DN DPC_LINE3_DP

DPC_LINE3_DN

21

22

23

24

DISPO20PM_BLACK-RH

COMM_EN15,30

COMM_EN

2

Switch circuit for secondary displayport

DPC_AUX_DP_C

Q107

R943

D

X_0R0402

S

N-2N7002_SOT23

Q108

D

N-2N7002_SOT23

S

Q109

D

S

N-2N7002_SOT23

1

X_0R0402

DP_AUX_DP

DPC_AUX_DN_C

R944

X_0R0402

DP_AUX_DN

DPC_HPD

R940

X_0R0402

HPD_DP

33 37Tuesday, September 09, 2008

DP_AUX_DP 15

DP_AUX_DN 15

HPD_DP 15

of

G

+12V

R939

100KR0402

VCC3

R937

10KR0402

Q104

D

G

S

N-2N7002_SOT23

R936

10KR0402

Title

Size Document Number Rev

Custom

Date: Sheet

Q106

D

G

S

N-2N7002_SOT23

Q105

D

G

S

N-2N7002_SOT23

<Title>

<Doc> <RevCod

G

R938

4.7KR0402

8

7

6

5

4

3

2

1

ATX CONNECTOR

C0.1U16Y0402

C0.1U16Y0402 C232

C265

C253

C273

C232

VCC5_SB

VCC3

R188

D D

ATX_PSON#25,26

C C

R187 0R0402R187 0R0402

R188

10KR0402

-12V

C0.1U16Y0402

X_C1000P50X0402

VCC5

C0.1U16Y0402

25

ATX1

13

3.3V

14

-12V

15

GND

16

P_ON

17

GND

18

GND

19

GND

20

-5V

21

5V

22

5V

23

5V GND243.3V

PWRCONN24P_WHITE-1

3.3V

25

3.3V GND

GND

GND POK

5VSB

+12V +12V

1 2 3 4

5V

5 6

5V

7 8 9 10 11 12

C346

C346 C0.1U16Y0402

C0.1U16Y0402

C257

C257 C0.1U16Y0402

C0.1U16Y0402

C322

C294

C294 C0.1U16Y0402

C0.1U16Y0402

C231

C231 C0.1U16Y0402

C0.1U16Y0402

VCC3

VCC5

VCC5_SB +12V

VCC3

VCC5

R195

4.7KR0402

C289

C289 C1000P50X0402

C1000P50X0402

ATX_PWROK 26,27

VCC3

1

2

RN38

D2 D1

Q69

4 6 8 2 4 6 8

RN38 X_8P4R-10R

X_8P4R-10R

RN39

RN39 X_8P4R-10R

X_8P4R-10R

3 5 7 1 3 5

VCC5_SB VCC5_SB

VCC_DDR VCC_DDR

R307 X_1KR0402R307 X_1KR0402

R547 X_1KR0402R547 X_1KR0402

C799

X_C0.1U16Y0402

7

G2

S2

G1

S1

X_NN-2N7002DW-7-F_SOT363-6-RH

D02-0390479-D07 D02-0390479-D07 D02-0390479-O05 D02-0390479-O06

R549 X_1KR0402R549 X_1KR0402

R548 X_1KR0402R548 X_1KR0402

C800

X_C0.1U16Y0402

VCC5

1

2

RN40

D2 D1

Q70

4 6 8 2 4 6 8

RN40 X_8P4R-10R

X_8P4R-10R

RN41

RN41 X_8P4R-10R

X_8P4R-10R

3 5 7 1 3 5 7

G2 S2 G1 S1

X_NN-2N7002DW-7-F_SOT363-6-RH

3

POWER LED

SUSLED

C628

X_C0.1U16Y0402

PWRLED

C627

X_C0.1U16Y0402

Title

Size Document Number Rev

B

Date: Sheet

VCC5_SB

R516 300RR516 300R

CE

R514 4.7KR0402R514 4.7KR0402

B

Q68

Q68 N-MMBT3904_NL_SOT23

N-MMBT3904_NL_SOT23

VCC5_SB

R515 300RR515 300R

CE

R513 4.7KR0402R513 4.7KR0402

B

Q67

Q67 N-MMBT3904_NL_SOT23

N-MMBT3904_NL_SOT23

MICRO-START INT'L CO.,LTD.

ATX & FRONT PANEL

VL390 0A

2

SUS_LED

PWR_LED

SUS_LED 25

PWR_LED 25

34 37Tuesday, September 09, 2008

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1

NEC Front Panel Connector

Modify 0829

VCC3_SB

R499 330RR499 330R

VCC5

R320

4.7KR0402

B B

FP_RST#12,18,26

X_C0.1U16Y0402

BUZZER

A A

SPKR18

8

R479 33R/4R479 33R/4

C661

R468 10KR0402R468 10KR0402

R467 220RR467 220R R465 220RR465 220R

CE

B

Q62

Q62 N-MMBT3904_NL_SOT23

N-MMBT3904_NL_SOT23

7

HDD+ HDD-

R500

0R/4

RESETRESET+

C647

C647 X_C0.1U16Y0402

X_C0.1U16Y0402

JFP1

1

HDD+

3

HDDRESET-5PWSW+

7

RESET+

9

NC

HEADER,2*5(10)_Black

D24

D24 BAS32L_LL34

BAS32L_LL34

C612

C612 C0.1U16Y0402

C0.1U16Y0402

SPK1

PLED SLED

PWSW-

VCC5

PWR_LED

2

SUS_LED

4 6

PWRSW-

8

1 2

BZ1

BUZZER-RH

6

PWRSW+

R490

R490 300R

300R

PWR_LED 25 SUS_LED 25

HDD-

5

POWER BUTTON

R476

R476 33R0402

33R0402

PWRSW+

C0.1U16Y0402

D50

S-BAT54A_SOT23

Z

VCC5_SB

C626

Y X

R475

8.2KR0402

PSIN 25

R489 X_4.7KR0402R489 X_4.7KR0402

SATA_LED#

SATA_LED# 19

4

VCC3

8

7

6

5

4

3

2

1

HEAT SINK

U23_X1

XX1

U23_X1

XX1

MH1

7 6

5

981

X_MH001

4

7 6

MH3

5

981

X_MH001

4

2 3

981

MH2

2 3

MH2

7 6

5

X_MH001

4

2 3

7 6

MH4

5

981

X_MH001

4

2 3

U14_X1

XX1

D D

XX2

SB_HEATSINK

NB_HEATSINK

MANUAL PART

C C

AVL: D06-0100161-F52 D06-0100101-P01

BAT1_X1

BAT-BCR2032P-RH

PCB1

P30-0737711-E48

B B

P30-073890A-E48 P30-073890A-G37 P30-073890B-E48 P30-073890B-G37 P30-073890C-E48 P30-073890C-G37

SB_HEATSINK

Simulation

VCC5

SIM1

X_PIN1*2

SIM2

X_PIN1*2

X_JS1

X_JS2

XX2

MH5

7 6

5

981

X_MH001

4

7 6

MH7

5

981

X_MH001

4

2 3

981

MH6

2 3

MH6

7 6

5

X_MH001

4

2 3

7 6

MH8

5

981

X_MH001

4

2 3

Optics Orientation Holes

FM12

FM8

X_FM100

FM9

FM8

X_FM100

FM11

FM16

X_FM120

FM1

FM2

X_FM120

FM15

X_FM100

X_FM120

8

X_FM120

FM17

X_FM120

FM20

X_FM120

FM18

A A

X_FM120

FM19

X_FM120

X_FM100

FM5

X_FM100

FM3

X_FM100

FM14

X_FM100

FM10

X_FM100

MICRO-START INT'L CO.,LTD.

Title

Auto BOM Mnaual

Size Document Number Rev

B

Date: Sheet

7

6

5

4

3

Date: Sheet

MICRO-START INT'L CO.,LTD.

VL390 0A

2

35 37Tuesday, September 09, 2008

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1

5

4

3

2

1

MODIFY HISTORY

1,(page 7,8,9)change to AM3 socket :(Have to apply AM3 library and footprint) (1) add pin B2 as NP/RSVD (2) change pin F3 from RSVD to M_VDDIO_PWRGD (3) change pin W30 from RSVD to MA_EVENT# (4) change pin V29 from RSVD to MB_EVENT# (5) change pin A12,B12,C12,D12,AG12,AH12,AJ12,AK12,AL12 from VTT to VDDR (6) change pin H20, AE7 to NP/VSS

AM3

D D

PWROK(Pin C9)

RS780

NB_PWRGDPOWERGOOD(Pin A10)

LDT_PWRGDLDT_PG(Pin F22)

SB700

PWR_BTN#(Pin H2) SLP_S3#(Pin F5)

C C

ATX_PWROK VDDA_25 VCC_DDR

B B

ATX_PWROK NB_VCC1P1 FP_RST# SLP_S3#

SUSB#(Pin 71)SLP_S3#

PWRON# (Pin72)SB_PWRON#

ENABLE

PWROK

VDD&VDDNB

PWRGD

PSON# (Pin76)

PANSWH# (Pin75)

VCORE_EN

NB_PWRGD

LDT_PWRGD#

*

SYS_PWRGD

WD_PWRGD

*

EN(Pin 24)

VRM U1 ISL6323

PWROK(Pin 34)

metal_VID

SB_PWRGDPWR_GD#(Pin H1)

PS_ON#

VDDPWRGD(Pin 37)

NB_PWRGD

SB_PWRGD

ACTIVE

V_SVI

ATX1

Pin16

ATX_PWROK U2 (UP7501) 5VDIMM

Pin8

F_PANEL1PSIN

UP6264

VRM_GD

metal_VID

SYSTEM POWER REF.

U4 (UP7707) VDDA_25

+1.8V_S0 VCC_1V2 +1.2VSB

VCC_DDR NB_VCC1P1

(7) remove pin H3, H4, H21, H22, AD18, AD19, AE8, AE9 (8) change pin F2 from PLATFORM_TYPE to RSVD

2,(page 7) (1) CPU_CORE_TYPE PU reister change to 1KR refer to CRB (2) Reserve R567 300R to cnnetct TEST22 to GND (3) Reserve R240,R247,R249,R281,R294 HDT PU resisters (4) Reserve C801,C802,C803 (5) Reserve R442,R599 for RS740 HT1.0

3,(page 8,9) change to DDR3 (1) W26,W25 change to MEM_MA1_CLK0;U24,V24 change to MEM_MA0_CLK1 (2) Y31,Y30 change to MEM_MB1_CLK0;V31,W31 change to MEM_MB0_CLK1 (3) AE27 change to MEM_MA1_ODT1;AE28 change to MEM_MA0_ODT1 (4) AG31 change to MEM_MB1_ODT1;AF31 change to MEM_MB0_ODT1 (5) E20 change to MEM_MA_RESET#; B19 change to MEM_MB_RESET# (6) Reserve MEM_MA_DQS_8 , MEM_MA_DM8 and MEM_MB_DQS_8,MEM_MB_DM8

4,(page 10,11,) change to DDR3 (1) Placement A0,B0,A1,B1 (2) DIMM1,DIMM3 PN:N13-2400421-L06(Blue);DIMM2,DIMM4 PN:N13-2400631-F02 (GREEN)

5,(pag 6) Modify VRM_EN circuit;Reserve LDT_PWRGD to VRM_PWROK,VID_SEL circuit;Add C587 6,(page 12) Remove the termination resisters and decouping caps 7,(page 13) R196,R197 change to 301R1%;Reserve R436,R443 for RS740 7,(page 14) Lan TX/RX pairs connect to GPP3 to co-lay RS740 8,(page 15)

(1) ball B8 is RS780 (DDC_DATA0) and RS740 (BMREQ#), ball A8 as it is used as DDC_CLK0 for RS780 and DDC_DATA for RS740 (2) Reserve LDT_RST#,LDT_STOP# level-shift circuit for RS740; Reserve R570,R571,R159,to Patch the timing of SYSRESET# & LDT_RST# & LDT_STOP# (Errata:ER_RS780B6 ERN # RS780-024)) (3) Add R472 and power rail VDDG_NB;R305 change to 1KR (4) Reserce L52 to pin7,D7 for RS740;Remove CP20 (5) Leave empty R275,R283,R251 for RS740 only (6) Add L42,C797;leave empty R246 (7)modify the I2C_CLK/I2C_DATA,SDA0_AUX0P/SCL0_AUX0N Pull-up and level shift topology (8) COMM_EN connect to Pin F9

9,(page 16) (1) For RS780 without Side-port:For VDDMEMNB stuff R723=0R and leave the LC filter empty; (2) Reserve CP29,R529 for RS740 co-lay (3) Stuff D38,R144 for POWER UP SEQUENCE (4) Remove VDDMEMNB LC filers,remove R529,C326 with no side-port memory (5) Remove CP8,L18 and short NB_VCC1P1 to SB VDDC pins

10,(page 17) (1) Reserve cystal circuit(Y6,C817,C818,R572) for A14 to solve the system time lag issue; (2) Modify A_RST# topology:add R441,R587,R590,R591,R592,R593 (3) Remove R432,R442,C575,C556,C570(PCI_CLK1 & CK_P_33M_1394) (4) Reserve PGNT#1,PGNT#2 as TP

11,(pag 18) (1) USB OC[0::6]# PU RN11,R574; (2) Pin D3 RSMRST# connect to SIO Pin 85; (Reserve:remove R412,stuff R413=22KR,C547=2.2uF to meet timing requirement); (3) KRRST# PU resister R382 change to 1KR;Reserve R655(ITE suggest) (4) Add R117;Reserve R212,R655

12,(pag 19) Reserve C574;SPI rom change to M31-25X1613-W03 12,(pag 20) Modify the SB power rail from VCC_1V2 to VCC_SB_1V2 13,(page 22)

(1) Change termination R on RED channel R158,R503 to 140R follow AN_RS780G1(For A13) (2) add R179,R221,leave R108,R126,Q11,Q12 empty ,R122,R130 change to 4.7KR; (For RS 780 level shifter not requried ) (3) the VGA1 PN change from N51-15F0391-F02 to N51-15F0391-A10(the pin is same but outside of board different) (4) leave empty Q8,Q13,C95 for RS740 only and R104,R128 change to 4.7KR (5) Add Q59,Leave empty D2,reserve R203,R81 change to10KR,R85 change to 200KR (6) Leave shunt R empty R204,R201,R215,R218,R538,R540,R539

14,(pag 23) Clock Gen change to SLG8LP625 15,(pag 24) Remove LPT1 circuit;SATA4 change to black N5N-07M0221-H06 for e-SATA 16,(pag 25) LAN change to Broadcom BCM5784/5764/5906(all co-lay),defualt 5906 M 17,(pag 26) Super IO change to IT8720;Floppy leave empty default;COM1 header change to Rear COM port 18,(pag 27) The ACPI solution change to UPI;System power generater circuit;the NB,SB PWRGD sequence 19,(pag 28) The VCC_DDR (PWM)and NB_VCC1P1 (Linear) circuit;CPU_VDDR(1.2V) generater 20,(pag 29) Remove the CD-IN header;ADD SPIDIF OUT header 21,(pag 30)

(1) USB power regulater modify to UP7533; (2) Stuff Common choke L12-181D017-CA8 and L12-900D017-CA8

22,(pag 31) ADD PCIE1_X2 Slot;Reserve R579,R581 for RS740 23,(pag 32) Remove PCI2 slot ;Add PREQ#2 PU R528 24,(pag 34) Remove U20 circuit;Add D36 and leave R478 empty 24,(pag 35) NB heatsink change to HS_43_44X31_24

PE_NB_RST#

NB_RST# circuit PCIE 16X slot PCIE 1X slot 1 PCIE 1X slot 2 PCIE LAN PCIE 1394

Super IO

NOTICE

AM3

RESET_L(Pin C7)

RS780

SYSRESETb(Pin D8) NB_RST#_L

A_RST#(Pin N2)

LDT_RST#(Pin G24)

SB700

KBRST#(Pin W15)

SYS_PWRGD Circuit

PCIRST#(Pin N1)

SYS_RESET#(Pin J2)

CLOCK GEN FP_RST#

SB700

VCC3 PU

VCC3_SB PU

*

LDT_RST#

PE_NB_RST#

SCLK SDATA

SCLK1 SDATA1

*

PCI Slot 1 Super IO TPM

CPU_SIC/CPU_SID

Asset ID Chipset

LDT_RST#

F_PANEL1

DIMM1,2,3,4 UP6264 CLOCK Gen

PCIE 16X PCIE 1X PCI TPM

*

MEANS OPTION

3,(page 18) Configer GPIO5 to output mode or internal PU/PD can Leave R377 empty ;??

A A

VCC

1.5V

EN

0.9V

1.2V

6ms

3ms

6ms

10 ms

5

15~30 ms

3ms

6ms

10 ms

6ms

4

R360,R367 can leave empty 4,(page 17,22)

(1) PCICLK5/GPIO41 power up default&enabled register changed between A11 and A12 (2) LPC_CLK0&AZ_RST# the straps for the PCI ROM BOOT and IMC enable should be verified

5,(page 23) Make sure NB&SB PCIE PHY 100M REF CLOCK from the SRC PLLs rather than SB_SRC PLL Follow APnote PA_RS7X0A2

BOM

1, No AM3 socket PN,in the sche use AM2 PN N12-9400040-F02 2, CHIPSET: RS780 Ver A13PN. B01-RS78085-A08

ㄛ

SB700 Ver A12 PN. B01-SB70035-A082

3

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

HISTORY

VL390 0A

1

36 37Tuesday, September 09, 2008

of

5

BOM

For AMD check

6R165,R534,R564l eave empty 9stuff C713,C706,C688,C704,C694,C680,C703,C691,C711,C696,C682,C72,C81,C108,C110,C702,C684,C714,C210,C132,C712,C768,C50,C252,C57,C66,C236,C249 Add C239,C241,C819,C243,C261,C246,C104,C105,C723 remove C242,C244

16stuff C307,C309,C311,C316,C797L29,L31,L22,L42

12Add 369L19,L20L21,L25

1, page 22 D9,D10,D11 placed close to CRT connector; Stuff U7,U8 and leave emtpy R142,R148

remve RX780 parts

D D

6,reserve Q9

17,remove Q58,Q60,Q61,R466,R464,R408,C546

31,modify all the PU to 8.2KR to VCC3;leave empty PREQ#[0:5] PU R

17~19,Remove Reserved R378,R383,R506,R507,R508,R509,R401

18,remove R117,R385 duplicate with R638,R642 Remove WAKE ON LAN Circuit 15,remove VDDG_NB power(R472,R479) and use VCC3,remove R301,R246,R241,R298,R217

23,remove W83391TG,RN8,FS1

25,Modify SYS_TEM to VR_TEMP_DA(remove RT1,R35,C11 chagne to 2200pF) Remove BIOS WRITE PROTECT Circuit

15,remove DISPLAY PORT

9,Modify CPU_VDDIO_PWRGD

7,VDDIO_FB R163 connect to DDR_FB

12,clock generator should not be enable before VCC_1V2 is ready.

25, Add AMDTSI circuit

C C

4

3

2

1

B B

A A

VCC

EN

MICRO-START INT'L CO.,LTD.

Title

Size Document Number Rev

Custom

Date: Sheet

5

4

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

HISTORY

VL390 0A

1

37 37Tuesday, September 09, 2008

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MSI MS-7389L2 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual