MSI MS-7382-1 Schematics
5
4
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MSI
MS-7382 Ver:1.0
D D
C C
B B
CPU:
AMD M2 65W
System Chipset:
ATI RS690V
ATI SB600
On Board Chipset:
FINTEK Super I/O -- F71882
LAN -- RTL8101E
HD Codec --ALC883&888
BIOS -- SPI ROM
Main Memory:
DDRII* 2 (Max 8GB)
PWM:
Controller--Intersil ISL6566CR 2 Phase
Clock Generator:
Controller--RTM 870T-691
Title Page
Cover Sheet 1
Block Diagram
AMD M2 940
System Memory
DDR Terminations
2
3,4,5
6
7
ATI RS690C 8-11
CLOCK GENERATOR RTM 870T-691 12
ATI SB600 13-17
PCI-ExpressX1
I/O FINTEK
LAN RTL8111B/RTL8101E
HD Audio - ALC883&888
USB connectors
PWM - ISL6566CR
MS-6 ACPI Controller &MS-11
IDE / SATA / FAN / LPT
ATX Connector / Front Panel / KB / CON
VGA Connector
History
MANUAL PARTS
POWER OK MAP
POWER MAP
RESET MAP
18
19
20
21
22
23
24
25-26
27
28
29
30
31
32
33
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
<Title>
<Title>
<Title>
MS-7382 0A
MS-7382 0A
MS-7382 0A
129Wednesday, August 01, 2007
129Wednesday, August 01, 2007
129Wednesday, August 01, 2007
1
5
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1
BLOCK DIAGRAM
D D
C C
PRIMARY IDE
SATA CONN x4
FLOPPY CONN
PS2/KB CONN
B B
PARALLEL CONN
SERIAL CONN x2
POWER
SUPPLY
CONNECTOR
ATA 66/100/133
INTEGRATED SATA I/II
SIO
LPC SUPER I/O
F71882
SPI ROM 4M
PE X16
PE X1
PE X1
VREG
PCI EXPRESS
PCI EXPRESS
PCI EXPRESS
LPC BUS 33MHZ
SOCKET 940
K9
ATI
RS690
465 BGA
ATI
SB600
564 BGA
HT 16X16 1GHZ
HT 8X8 1GHZ
USB2.0 x10
128-BIT 400/533/667/800MHZ
AZAILIA
VGA CONN
BACK PANEL CONN
USB2 PORTS 0-1
DOUBLE STACK
USB2 PORTS 2-3
X2/GBIT LAN
FRONT PANEL HDR
USB2 PORTS 4-5
USB2 PORTS 6-7
USB2 PORTS 8-9
PCI-E 100MHZ
PCI 33MHZ
Realtek ALC 883/888 (HD, 7.1Channel)
DDRII CONN 0
DDRII CONN 1
LAN-RTL8111B
PCI SLOT 1
PCI SLOT 2
PCI SLOT 3
A A
Title
Title
Title
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
MS-7382 0A
Custom
MS-7382 0A
Custom
MS-7382 0A
Custom
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
229Wednesday, July 18, 2007
229Wednesday, July 18, 2007
229Wednesday, July 18, 2007
1
5
4
3
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1
HT_CADIN_H15
HT_CADIN_L15
HT_CADIN_H14
HT_CADIN_L14
HT_CADIN_H13
HT_CADIN_L13
HT_CADIN_H12
HT_CADIN_L12
HT_CADIN_H11
HT_CADIN_L11
HT_CADIN_H10
HT_CADIN_L10
HT_CADIN_H9
HT_CADIN_L9
HT_CADIN_H8
HT_CADIN_L8
HT_CADIN_H7
HT_CADIN_L7
HT_CADIN_H6
HT_CADIN_L6
HT_CADIN_H5
HT_CADIN_L5
HT_CADIN_H4
HT_CADIN_L4
HT_CADIN_H3
HT_CADIN_L3
HT_CADIN_H2
HT_CADIN_L2
HT_CADIN_H1
HT_CADIN_L1
HT_CADIN_H0
HT_CADIN_L0
HT_CADIN_H[15..0]
HT_CADIN_L[15..0]
HT_CADOUT_H[15..0]
HT_CADOUT_L[15..0]
CPU1ACPU1A
N6
L0_CLKIN_H(1)
P6
L0_CLKIN_L(1)
N3
L0_CLKIN_H(0)
N2
L0_CLKIN_L(0)
V4
L0_CTLIN_H(1)
V5
L0_CTLIN_L(1)
U1
L0_CTLIN_H(0)
V1
L0_CTLIN_L(0)
U6
L0_CADIN_H(15)
V6
L0_CADIN_L(15)
T4
L0_CADIN_H(14)
T5
L0_CADIN_L(14)
R6
L0_CADIN_H(13)
T6
L0_CADIN_L(13)
P4
L0_CADIN_H(12)
P5
L0_CADIN_L(12)
M4
L0_CADIN_H(11)
M5
L0_CADIN_L(11)
L6
L0_CADIN_H(10)
M6
L0_CADIN_L(10)
K4
L0_CADIN_H(9)
K5
L0_CADIN_L(9)
J6
L0_CADIN_H(8)
K6
L0_CADIN_L(8)
U3
L0_CADIN_H(7)
U2
L0_CADIN_L(7)
R1
L0_CADIN_H(6)
T1
L0_CADIN_L(6)
R3
L0_CADIN_H(5)
R2
L0_CADIN_L(5)
N1
L0_CADIN_H(4)
P1
L0_CADIN_L(4)
L1
L0_CADIN_H(3)
M1
L0_CADIN_L(3)
L3
L0_CADIN_H(2)
L2
L0_CADIN_L(2)
J1
L0_CADIN_H(1)
K1
L0_CADIN_L(1)
J3
L0_CADIN_H(0)
J2
L0_CADIN_L(0)
VCCA_1V2
C179
C179
224P/16v/6
224P/16v/6
C199
C199
224P/16v/6
224P/16v/6
L0_CLKOUT_H(1)
L0_CLKOUT_L(1)
L0_CLKOUT_H(0)
L0_CLKOUT_L(0)
L0_CTLOUT_H(1)
L0_CTLOUT_L(1)
L0_CTLOUT_H(0)
L0_CTLOUT_L(0)
L0_CADOUT_H(15)
L0_CADOUT_L(15)
L0_CADOUT_H(14)
L0_CADOUT_L(14)
L0_CADOUT_H(13)
L0_CADOUT_L(13)
L0_CADOUT_H(12)
L0_CADOUT_L(12)
L0_CADOUT_H(11)
L0_CADOUT_L(11)
L0_CADOUT_H(10)
L0_CADOUT_L(10)
L0_CADOUT_H(9)
L0_CADOUT_L(9)
L0_CADOUT_H(8)
L0_CADOUT_L(8)
L0_CADOUT_H(7)
L0_CADOUT_L(7)
L0_CADOUT_H(6)
L0_CADOUT_L(6)
L0_CADOUT_H(5)
L0_CADOUT_L(5)
L0_CADOUT_H(4)
L0_CADOUT_L(4)
L0_CADOUT_H(3)
L0_CADOUT_L(3)
L0_CADOUT_H(2)
L0_CADOUT_L(2)
L0_CADOUT_H(1)
L0_CADOUT_L(1)
L0_CADOUT_H(0)
L0_CADOUT_L(0)
HT_CADIN_H[15..0]8
HT_CADIN_L[15..0]8
HT_CADOUT_H[15..0]8
HT_CADOUT_L[15..0]8
D D
HT_CLKIN_H18
HT_CLKIN_L18
HT_CLKIN_H08
VCCA_1V2
HT_CLKIN_L08
R116 51/4R116 51/4
R117 51/4R117 51/4
HT_CTLIN_H08
HT_CTLIN_L08
C C
B B
A A
VID[0..4]20
C73
C73
180P50N
180P50N
AD5
AD4
AD1
AC1
Y6
W6
W2
W3
Y5
Y4
AB6
AA6
AB5
AB4
AD6
AC6
AF6
AE6
AF5
AF4
AH6
AG6
AH5
AH4
Y1
W1
AA2
AA3
AB1
AA1
AC2
AC3
AE2
AE3
AF1
AE1
AG2
AG3
AH1
AG1
VID[0..4]
C75
C75
180P50N
180P50N
TP15TP15
TP14TP14
HT_CADOUT_H15
HT_CADOUT_L15
HT_CADOUT_H14
HT_CADOUT_L14
HT_CADOUT_H13
HT_CADOUT_L13
HT_CADOUT_H12
HT_CADOUT_L12
HT_CADOUT_H11
HT_CADOUT_L11
HT_CADOUT_H10
HT_CADOUT_L10
HT_CADOUT_H9
HT_CADOUT_L9
HT_CADOUT_H8
HT_CADOUT_L8
HT_CADOUT_H7
HT_CADOUT_L7
HT_CADOUT_H6
HT_CADOUT_L6
HT_CADOUT_H5
HT_CADOUT_L5
HT_CADOUT_H4
HT_CADOUT_L4
HT_CADOUT_H3
HT_CADOUT_L3
HT_CADOUT_H2
HT_CADOUT_L2
HT_CADOUT_H1
HT_CADOUT_L1
HT_CADOUT_H0
HT_CADOUT_L0
HT_CLKOUT_H1 8
HT_CLKOUT_L1 8
HT_CLKOUT_H0 8
HT_CLKOUT_L0 8
HT_CTLOUT_H0 8
HT_CTLOUT_L0 8
VDDA_25
L4
80S/0805L480S/0805
C56 C3900P25XC56 C3900P25X
CPU_CLK11
C55 C3900P25XC55 C3900P25X
CPU_CLK#11
VCC_DDR
R104
R104
300/4
300/4
R280
R280
X_300/4
X_300/4
VCC_DDR
R112
R112
39.2R1%/4
39.2R1%/4
R113
R113
39.2R1%/4
39.2R1%/4
LDT_PWRGD12
LDT_STOP#9,12
The sideband signals on AMD platforms require a strong
Pull Down to GND to overcome the CPU drive during
power up and therefore allow the signals to maintain the
logic 0 state.
R73
R73
169R1%
169R1%
TP24TP24
TP27TP27
TP16TP16
TP22TP22
TP6TP6
COREFB+20
COREFB-20
TP1TP1
CPU_M_VREF
TP10TP10
TP11TP11
TP13TP13
TP8TP8
TP18TP18
THERMDC_CPU16
THERMDA_CPU16
LDT_RST#
LDT_RST#12
LDT_PWRGD
LDT_STOP#
C4.7U6.3X5
C4.7U6.3X5
C45
C45
X_C1000P50X
X_C1000P50X
R43 300/4R43 300/4
R42 300/4R42 300/4
C50
C50
C64
224P/16v/6
C64
224P/16v/6
CPUCLKIN
CPUCLKIN#
LDT_PWRGD
LDT_STOP#
CPU_PRESENT_L
THERM_SIC
CPU_TDI
CPU_TRST_L
CPU_TCK
CPU_TMS
CPU_DBREQ_L
COREFB+
COREFBÂCPU_VTT_SENSE
CPU_STRAP_HI_E11
CPU_STRAP_LO_F11
CPU_TEST25_H
CPU_TEST25_L
RN58
RN58
8P4R-680ohm
8P4R-680ohm
1
3
5
7
For SB600
VDDA25
C58
3300P/50V/4
C58
3300P/50V/4
CPU1DCPU1D
C10
VDDA1
D10
VDDA2
A8
CLKIN_H
B8
CLKIN_L
C9
PWROK
D8
LDTSTOP_L
C7
RESET_L
AL3
CPU_PRESENT_L
AL6
THERMTRIP_L
SIC
AK6
AL10
AJ10
AH10
AL9
A5
G2
G1
E12
F12
AH11
AJ11
A10
B10
F10
E9
AJ7
F6
D6
E7
F8
C5
AH9
E5
AJ5
AG9
AG8
AH7
AJ6
VCC_DDR
2
4
6
8
R54
R54
15/6/1
15/6/1
R57
R57
15/6/1
15/6/1
SID
TDI
TRST_L
TCK
TMS
DBREQ_L
VDD_FB_H
VDD_FB_L
VTT_SENSE
M_VREF
M_ZN
M_ZP
TEST25_H
TEST25_L
TEST19
TEST18
TEST13
TEST9
TEST17
TEST16
TEST15
TEST14
TEST12
TEST7
TEST6
TEST5
TEST4
TEST3
TEST2
PROCHOT_L
VDDIO_FB_H
VDDIO_FB_L
C65
C65
0.1u/10X/4
0.1u/10X/4
VID(5)
VID(4)
VID(3)
VID(2)
VID(1)
VID(0)
DBRDY
PSI_L
HTREF1
HTREF0
TEST29_H
TEST29_L
TEST24
TEST23
TEST22
TEST21
TEST20
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
TEST8
TP9TP9
VCC_DDR
D2
VID4
R18
R18
VID3LDT_RST#
300/4
300/4
VID2
VID1
VID0
R105 300/4R105 300/4
TP26TP26
VDDIO_FB_H should be used for systems which do not
support differential voltage feedback. In this case,
VDDIO_FB_L is not used and VDDIO_FB_H should be
routed as a 10-mil trace with 10-mil spacing (10/10).
VCC_DDR
TP12TP12
R52
80.6R1%/4
R52
80.6R1%/4
TP21TP21
TP17TP17
TP20TP20
TP19TP19
VCC_DDR
R108
R108
300/4
300/4
Test26 is pulled up to VDDIO according to CPU revision guide errata 133.
TEST18, TEST19, and TEST21 are pulled down to VSS according to CPU
revision guide errata 133.
CPU_PRESENT_L
CPU_TEST25_H
CPU_TEST25_L
TDO
CPU_M_VREF
D1
C1
E3
E2
E1
AK7
AL7
AK10
B6
AK11
AL11
F1
V8
V7
C11
D11
AK8
AH8
AJ9
AL8
AJ8
J10
H9
AK9
AK5
G7
D4
C59
C59
C1000P50X0402
C1000P50X0402
VCC_DDRVCC_DDR
R510
R510
300/4
300/4
B
VCC_DDR
C160
C1000P50X0402
C160
C1000P50X0402
R106
R106
300/4
300/4
R118 1KR1%0402R118 1KR1%0402
R67 510R/4R67 510R/4
R72 510R/4R72 510R/4
R511
R511
4.7K/4
4.7K/4
Q45
Q45
N-MMBT3904_NL_SOT23
N-MMBT3904_NL_SOT23
CE
CPU_THRIP# 13
R111 44.2RSTR111 44.2RST
R114 44.2RSTR114 44.2RST
C161
C1000P50X0402
C161
C1000P50X0402
VCC_DDR
VCCA_1V2
Title
Title
Title
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
MS-7382 0A
Custom
MS-7382 0A
Custom
MS-7382 0A
Custom
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
1
of
329Wednesday, July 18, 2007
of
329Wednesday, July 18, 2007
of
329Wednesday, July 18, 2007
5
4
3
2
1
MEM_MA_DATA[63..0]6
MEM_MA_ADD[15..0]6,7
MEM_MA_DQS_H[7..0]6
D D
C C
B B
A A
MEM_MA_DQS_L[7..0]6 MEM_MB_DQS_L[7..0]6
MEM_MA_DM[7..0]6
MEM_MA0_CLK_H26,7
MEM_MA0_CLK_L26,7
MEM_MA0_CLK_H16,7
MEM_MA0_CLK_L16,7
MEM_MA0_CLK_H06,7
MEM_MA0_CLK_L06,7
MEM_MA0_CS_L16,7
MEM_MA0_CS_L06,7
MEM_MA0_ODT06,7
MEM_MA_CAS_L6,7
MEM_MA_WE_L6,7
MEM_MA_RAS_L6,7
MEM_MA_BANK26,7
MEM_MA_BANK16,7
MEM_MA_BANK06,7
MEM_MA_CKE17
MEM_MA_CKE06,7
MEM_MA_DATA[63..0]
MEM_MA_ADD[15..0]
MEM_MA_DQS_H[7..0]
MEM_MA_DQS_L[7..0]
MEM_MA_DM[7..0]
MEM_MA0_CLK_H2
MEM_MA0_CLK_L2
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H0
MEM_MA0_CLK_L0
MEM_MA0_CS_L1
MEM_MA0_CS_L0
MEM_MA0_ODT0
MEM_MA_CAS_L
MEM_MA_WE_L
MEM_MA_RAS_L
MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0
MEM_MA_CKE1
MEM_MA_CKE0
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0
AG21
AG20
AC25
AA24
AC28
AE20
AE19
AD27
AA25
AC27
AB25
AB27
AA26
AA27
AC26
AD15
AE15
AG18
AG19
AG24
AG25
AG27
AG28
AF15
AF19
AH29
AJ25
G19
H19
U27
U26
G20
G21
V27
W27
N25
Y27
L27
M25
M27
N24
N26
P25
Y25
N27
R24
P27
R25
R26
R27
T25
U25
T27
W24
D29
C29
C25
D25
E19
F19
F15
G15
B29
E24
E18
H15
CPU1BCPU1B
MA0_CLK_H(2)
MA0_CLK_L(2)
MA0_CLK_H(1)
MA0_CLK_L(1)
MA0_CLK_H(0)
MA0_CLK_L(0)
MA0_CS_L(1)
MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)
MA1_CLK_L(2)
MA1_CLK_H(1)
MA1_CLK_L(1)
MA1_CLK_H(0)
MA1_CLK_L(0)
MA1_CS_L(1)
MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_L
MA_WE_L
MA_RAS_L
MA_BANK(2)
MA_BANK(1)
MA_BANK(0)
MA_CKE(1)
MA_CKE(0)
MA_ADD(15)
MA_ADD(14)
MA_ADD(13)
MA_ADD(12)
MA_ADD(11)
MA_ADD(10)
MA_ADD(9)
MA_ADD(8)
MA_ADD(7)
MA_ADD(6)
MA_ADD(5)
MA_ADD(4)
MA_ADD(3)
MA_ADD(2)
MA_ADD(1)
MA_ADD(0)
MA_DQS_H(7)
MA_DQS_L(7)
MA_DQS_H(6)
MA_DQS_L(6)
MA_DQS_H(5)
MA_DQS_L(5)
MA_DQS_H(4)
MA_DQS_L(4)
MA_DQS_H(3)
MA_DQS_L(3)
MA_DQS_H(2)
MA_DQS_L(2)
MA_DQS_H(1)
MA_DQS_L(1)
MA_DQS_H(0)
MA_DQS_L(0)
MA_DM(7)
MA_DM(6)
MA_DM(5)
MA_DM(4)
MA_DM(3)
MA_DM(2)
MA_DM(1)
MA_DM(0)
MA_DATA(63)
MA_DATA(62)
MA_DATA(61)
MA_DATA(60)
MA_DATA(59)
MA_DATA(58)
MA_DATA(57)
MA_DATA(56)
MA_DATA(55)
MA_DATA(54)
MA_DATA(53)
MA_DATA(52)
MA_DATA(51)
MA_DATA(50)
MA_DATA(49)
MA_DATA(48)
MA_DATA(47)
MA_DATA(46)
MA_DATA(45)
MA_DATA(44)
MA_DATA(43)
MA_DATA(42)
MA_DATA(41)
MA_DATA(40)
MA_DATA(39)
MA_DATA(38)
MA_DATA(37)
MA_DATA(36)
MA_DATA(35)
MA_DATA(34)
MA_DATA(33)
MA_DATA(32)
MA_DATA(31)
MA_DATA(30)
MA_DATA(29)
MA_DATA(28)
MA_DATA(27)
MA_DATA(26)
MA_DATA(25)
MA_DATA(24)
MA_DATA(23)
MA_DATA(22)
MA_DATA(21)
MA_DATA(20)
MA_DATA(19)
MA_DATA(18)
MA_DATA(17)
MA_DATA(16)
MA_DATA(15)
MA_DATA(14)
MA_DATA(13)
MA_DATA(12)
MA_DATA(11)
MA_DATA(10)
MA_DATA(9)
MA_DATA(8)
MA_DATA(7)
MA_DATA(6)
MA_DATA(5)
MA_DATA(4)
MA_DATA(3)
MA_DATA(2)
MA_DATA(1)
MA_DATA(0)
MA_DQS_H(8)
MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)
MA_CHECK(6)
MA_CHECK(5)
MA_CHECK(4)
MA_CHECK(3)
MA_CHECK(2)
MA_CHECK(1)
MA_CHECK(0)
AE14
AG14
AG16
AD17
AD13
AE13
AG15
AE16
AG17
AE18
AD21
AG22
AE17
AF17
AF21
AE21
AF23
AE23
AJ26
AG26
AE22
AG23
AH25
AF25
AJ28
AJ29
AF29
AE26
AJ27
AH27
AG29
AF27
E29
E28
D27
C27
G26
F27
C28
E27
F25
E25
E23
D23
E26
C26
G23
F23
E22
E21
F17
G17
G22
F21
G18
E17
G16
E15
G13
H13
H17
E16
E14
G14
J28
J27
J25
K25
J26
G28
G27
L24
K27
H29
H27
MEM_MA_DATA63
MEM_MA_DATA62
MEM_MA_DATA61
MEM_MA_DATA60
MEM_MA_DATA59
MEM_MA_DATA58
MEM_MA_DATA57
MEM_MA_DATA56
MEM_MA_DATA55
MEM_MA_DATA54
MEM_MA_DATA53
MEM_MA_DATA52
MEM_MA_DATA51
MEM_MA_DATA50
MEM_MA_DATA49
MEM_MA_DATA48
MEM_MA_DATA47
MEM_MA_DATA46
MEM_MA_DATA45
MEM_MA_DATA44
MEM_MA_DATA43
MEM_MA_DATA42
MEM_MA_DATA41
MEM_MA_DATA40
MEM_MA_DATA39
MEM_MA_DATA38
MEM_MA_DATA37
MEM_MA_DATA36
MEM_MA_DATA35
MEM_MA_DATA34
MEM_MA_DATA33
MEM_MA_DATA32
MEM_MA_DATA31
MEM_MA_DATA30
MEM_MA_DATA29
MEM_MA_DATA28
MEM_MA_DATA27
MEM_MA_DATA26
MEM_MA_DATA25
MEM_MA_DATA24
MEM_MA_DATA23
MEM_MA_DATA22
MEM_MA_DATA21
MEM_MA_DATA20
MEM_MA_DATA19
MEM_MA_DATA18
MEM_MA_DATA17
MEM_MA_DATA16
MEM_MA_DATA15
MEM_MA_DATA14
MEM_MA_DATA13
MEM_MA_DATA12
MEM_MA_DATA11
MEM_MA_DATA10
MEM_MA_DATA9
MEM_MA_DATA8
MEM_MA_DATA7
MEM_MA_DATA6
MEM_MA_DATA5
MEM_MA_DATA4
MEM_MA_DATA3
MEM_MA_DATA2
MEM_MA_DATA1
MEM_MA_DATA0
MEM_MB_DATA[63..0]6
MEM_MB_ADD[15..0]6,7
MEM_MB_DQS_H[7..0]6
MEM_MB_DM[7..0]6
MEM_MB0_CLK_H26,7
MEM_MB0_CLK_L26,7
MEM_MB0_CLK_H16,7
MEM_MB0_CLK_L16,7
MEM_MB0_CLK_H06,7
MEM_MB0_CLK_L06,7
MEM_MB0_CS_L16,7
MEM_MB0_CS_L06,7
MEM_MB0_ODT06,7
MEM_MB_CAS_L6,7
MEM_MB_WE_L6,7
MEM_MB_RAS_L6,7
MEM_MB_BANK26,7
MEM_MB_BANK16,7
MEM_MB_BANK06,7
MEM_MB_CKE17
MEM_MB_CKE06,7
MEM_MB_DATA[63..0]
MEM_MB_ADD[15..0]
MEM_MB_DQS_H[7..0]
MEM_MB_DQS_L[7..0]
MEM_MB_DM[7..0]
MEM_MB0_CLK_H2
MEM_MB0_CLK_L2
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_CLK_H0
MEM_MB0_CLK_L0
MEM_MB0_CS_L1
MEM_MB0_CS_L0
MEM_MB0_ODT0
MEM_MB_CAS_L
MEM_MB_WE_L
MEM_MB_RAS_L
MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0
MEM_MB_CKE1
MEM_MB_CKE0
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0
AJ19
AK19
A18
A19
U31
U30
AE30
AC31
AD29
AL19
AL18
C19
D19
W29
W28
AE29
AB31
AD31
AC29
AC30
AB29
N31
AA31
AA28
M31
M29
N28
N29
AE31
N30
P29
AA29
P31
R29
R28
R31
R30
T31
T29
U29
U28
AA30
AK13
AJ13
AK17
AJ17
AK23
AL23
AL28
AL29
D31
C31
C24
C23
D17
C17
C14
C13
AJ14
AH17
AJ23
AK29
C30
A23
B17
B13
CPU1CCPU1C
MB0_CLK_H(2)
MB0_CLK_L(2)
MB0_CLK_H(1)
MB0_CLK_L(1)
MB0_CLK_H(0)
MB0_CLK_L(0)
MB0_CS_L(1)
MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)
MB1_CLK_L(2)
MB1_CLK_H(1)
MB1_CLK_L(1)
MB1_CLK_H(0)
MB1_CLK_L(0)
MB1_CS_L(1)
MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_L
MB_WE_L
MB_RAS_L
MB_BANK(2)
MB_BANK(1)
MB_BANK(0)
MB_CKE(1)
MB_CKE(0)
MB_ADD(15)
MB_ADD(14)
MB_ADD(13)
MB_ADD(12)
MB_ADD(11)
MB_ADD(10)
MB_ADD(9)
MB_ADD(8)
MB_ADD(7)
MB_ADD(6)
MB_ADD(5)
MB_ADD(4)
MB_ADD(3)
MB_ADD(2)
MB_ADD(1)
MB_ADD(0)
MB_DQS_H(7)
MB_DQS_L(7)
MB_DQS_H(6)
MB_DQS_L(6)
MB_DQS_H(5)
MB_DQS_L(5)
MB_DQS_H(4)
MB_DQS_L(4)
MB_DQS_H(3)
MB_DQS_L(3)
MB_DQS_H(2)
MB_DQS_L(2)
MB_DQS_H(1)
MB_DQS_L(1)
MB_DQS_H(0)
MB_DQS_L(0)
MB_DM(7)
MB_DM(6)
MB_DM(5)
MB_DM(4)
MB_DM(3)
MB_DM(2)
MB_DM(1)
MB_DM(0)
MB_DATA(63)
MB_DATA(62)
MB_DATA(61)
MB_DATA(60)
MB_DATA(59)
MB_DATA(58)
MB_DATA(57)
MB_DATA(56)
MB_DATA(55)
MB_DATA(54)
MB_DATA(53)
MB_DATA(52)
MB_DATA(51)
MB_DATA(50)
MB_DATA(49)
MB_DATA(48)
MB_DATA(47)
MB_DATA(46)
MB_DATA(45)
MB_DATA(44)
MB_DATA(43)
MB_DATA(42)
MB_DATA(41)
MB_DATA(40)
MB_DATA(39)
MB_DATA(38)
MB_DATA(37)
MB_DATA(36)
MB_DATA(35)
MB_DATA(34)
MB_DATA(33)
MB_DATA(32)
MB_DATA(31)
MB_DATA(30)
MB_DATA(29)
MB_DATA(28)
MB_DATA(27)
MB_DATA(26)
MB_DATA(25)
MB_DATA(24)
MB_DATA(23)
MB_DATA(22)
MB_DATA(21)
MB_DATA(20)
MB_DATA(19)
MB_DATA(18)
MB_DATA(17)
MB_DATA(16)
MB_DATA(15)
MB_DATA(14)
MB_DATA(13)
MB_DATA(12)
MB_DATA(11)
MB_DATA(10)
MB_DATA(9)
MB_DATA(8)
MB_DATA(7)
MB_DATA(6)
MB_DATA(5)
MB_DATA(4)
MB_DATA(3)
MB_DATA(2)
MB_DATA(1)
MB_DATA(0)
MB_DQS_H(8)
MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)
MB_CHECK(6)
MB_CHECK(5)
MB_CHECK(4)
MB_CHECK(3)
MB_CHECK(2)
MB_CHECK(1)
MB_CHECK(0)
AH13
AL13
AL15
AJ15
AF13
AG13
AL14
AK15
AL16
AL17
AK21
AL21
AH15
AJ16
AH19
AL20
AJ22
AL22
AL24
AK25
AJ21
AH21
AH23
AJ24
AL27
AK27
AH31
AG30
AL25
AL26
AJ30
AJ31
E31
E30
B27
A27
F29
F31
A29
A28
A25
A24
C22
D21
A26
B25
B23
A22
B21
A20
C16
D15
C21
A21
A17
A16
B15
A14
E13
F13
C15
A15
A13
D13
J31
J30
J29
K29
K31
G30
G29
L29
L28
H31
G31
MEM_MB_DATA63
MEM_MB_DATA62
MEM_MB_DATA61
MEM_MB_DATA60
MEM_MB_DATA59
MEM_MB_DATA58
MEM_MB_DATA57
MEM_MB_DATA56
MEM_MB_DATA55
MEM_MB_DATA54
MEM_MB_DATA53
MEM_MB_DATA52
MEM_MB_DATA51
MEM_MB_DATA50
MEM_MB_DATA49
MEM_MB_DATA48
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA45
MEM_MB_DATA44
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA41
MEM_MB_DATA40
MEM_MB_DATA39
MEM_MB_DATA38
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA35
MEM_MB_DATA34
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA31
MEM_MB_DATA30
MEM_MB_DATA29
MEM_MB_DATA28
MEM_MB_DATA27
MEM_MB_DATA26
MEM_MB_DATA25
MEM_MB_DATA24
MEM_MB_DATA23
MEM_MB_DATA22
MEM_MB_DATA21
MEM_MB_DATA20
MEM_MB_DATA19
MEM_MB_DATA18
MEM_MB_DATA17
MEM_MB_DATA16
MEM_MB_DATA15
MEM_MB_DATA14
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10
MEM_MB_DATA9
MEM_MB_DATA8
MEM_MB_DATA7
MEM_MB_DATA6
MEM_MB_DATA5
MEM_MB_DATA4
MEM_MB_DATA3
MEM_MB_DATA2
MEM_MB_DATA1
MEM_MB_DATA0
Title
Title
Title
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
MS-7382 0A
Custom
MS-7382 0A
Custom
MS-7382 0A
Custom
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
1
of
429Wednesday, July 18, 2007
of
429Wednesday, July 18, 2007
of
429Wednesday, July 18, 2007
5
VCCP
CPU1FCPU1F
A4
VDD
A6
VDD
AA8
VDD
AA10
VDD
AA12
VDD
AA14
VDD
AA16
VDD
AA18
VDD
AB7
VDD
D D
C C
B B
VTT_DDR VCCP
C157
224P/16v/6
C157
224P/16v/6
AB9
VDD
AB11
VDD
AC4
VDD
AC5
VDD
AC8
VDD
AC10
VDD
AD2
VDD
AD3
VDD
AD7
VDD
AD9
VDD
AE10
VDD
AF7
VDD
AF9
VDD
AG4
VDD
AG5
VDD
AG7
VDD
AH2
VDD
AH3
VDD
B3
VDD
B5
VDD
B7
VDD
C2
VDD
C4
VDD
C6
VDD
C8
VDD
D3
VDD
D5
VDD
D7
VDD
D9
VDD
E4
VDD
E6
VDD
E8
VDD
E10
VDD
F5
VDD
F7
VDD
F9
VDD
F11
VDD
G6
VDD
G8
VDD
G10
VDD
G12
VDD
H7
VDD
H11
VDD
H23
VDD
J8
VDD
J12
VDD
J14
VDD
J16
VDD
J18
VDD
J20
VDD
J22
VDD
J24
VDD
K7
VDD
K9
VDD
K11
VDD
K13
VDD
K15
VDD
K17
VDD
K19
VDD
K21
VDD
K23
VDD
L4
VDD
L5
VDD
L8
VDD
L10
VDD
L12
VDD
Y17
VDD
Y19
VDD
C274
224P/16v/6
C274
224P/16v/6
C207
C4.7U10Y0805
C207
C4.7U10Y0805
X_180P50N
X_180P50N
A3
VSS
A7
VSS
A9
VSS
A11
VSS
AA4
VSS
AA5
VSS
AA7
VSS
AA9
VSS
AA11
VSS
AA13
VSS
AA15
VSS
AA17
VSS
AA19
VSS
AA21
VSS
AA23
VSS
AB2
VSS
AB3
VSS
AB8
VSS
AB10
VSS
AB12
VSS
AB14
VSS
AB16
VSS
AB18
VSS
AB20
VSS
AB22
VSS
AC7
VSS
AC9
VSS
AC11
VSS
AC13
VSS
AC15
VSS
AC17
VSS
AC19
VSS
AC21
VSS
AC23
VSS
AD8
VSS
AD10
VSS
AD12
VSS
AD14
VSS
AD16
VSS
AD20
VSS
AD22
VSS
AD24
VSS
AE4
VSS
AE5
VSS
AE9
VSS
AE11
VSS
AF2
VSS
AF3
VSS
AF8
VSS
AF10
VSS
AF12
VSS
AF14
VSS
AF16
VSS
AF18
VSS
AF20
VSS
AF22
VSS
AF24
VSS
AF26
VSS
AF28
VSS
AG10
VSS
AG11
VSS
AH14
VSS
AH16
VSS
AH18
VSS
AH20
VSS
AH22
VSS
AH24
VSS
AH26
VSS
AH28
VSS
AH30
VSS
AK2
VSS
AK14
VSS
AK16
VSS
AK18
VSS
Y14
VSS
Y16
VSS
C194
C194
C62
C1000P50X
C62
C1000P50X
C229
C1000P50X
C229
C1000P50X
C184
C184
C100p50N0402
C100p50N0402
4
VCCP VCCP
C633
X_C10U6.3X50805
C633
X_C10U6.3X50805
CPU1GCPU1G
L14
VDD
L16
VDD
L18
VDD
M2
VDD
M3
VDD
M7
VDD
M9
VDD
M11
VDD
M13
VDD
M15
VDD
M17
VDD
M19
VDD
N8
VDD
N10
VDD
N12
VDD
N14
VDD
N16
VDD
N18
VDD
P7
VDD
P9
VDD
P11
VDD
P13
VDD
P15
VDD
P17
VDD
P19
VDD
R4
VDD
R5
VDD
R8
VDD
R10
VDD
R12
VDD
R14
VDD
R16
VDD
R18
VDD
R20
VDD
T2
VDD
T3
VDD
T7
VDD
T9
VDD
T11
VDD
T13
VDD
T15
VDD
T17
VDD
T19
VDD
T21
VDD
U8
VDD
U10
VDD
U12
VDD
U14
VDD
U16
VDD
U18
VDD
U20
VDD
V9
VDD
V11
VDD
V13
VDD
V15
VDD
V17
VDD
V19
VDD
V21
VDD
W4
VDD
W5
VDD
W8
VDD
W10
VDD
W12
VDD
W14
VDD
W16
VDD
W18
VDD
W20
VDD
Y2
VDD
Y3
VDD
Y7
VDD
Y9
VDD
Y11
VDD
Y13
VDD
Y15
VDD
Y21
VDD
C640
X_C10U6.3X50805
C640
X_C10U6.3X50805
C635
C10U6.3X50805
C635
C10U6.3X50805
C642
C10U6.3X50805
C642
C10U6.3X50805
AK20
VSS
AK22
VSS
AK24
VSS
AK26
VSS
AK28
VSS
AK30
VSS
AL5
VSS
B4
VSS
B9
VSS
B11
VSS
B14
VSS
B16
VSS
B18
VSS
B20
VSS
B22
VSS
B24
VSS
B26
VSS
B28
VSS
B30
VSS
C3
VSS
D14
VSS
D16
VSS
D18
VSS
D20
VSS
D22
VSS
D24
VSS
D26
VSS
D28
VSS
D30
VSS
E11
VSS
F4
VSS
F14
VSS
F16
VSS
F18
VSS
F20
VSS
F22
VSS
F24
VSS
F26
VSS
F28
VSS
F30
VSS
G9
VSS
G11
VSS
H8
VSS
H10
VSS
H12
VSS
H14
VSS
H16
VSS
H18
VSS
H22
VSS
H24
VSS
H26
VSS
H28
VSS
H30
VSS
J4
VSS
J5
VSS
J7
VSS
J9
VSS
J11
VSS
J13
VSS
J15
VSS
J17
VSS
J19
VSS
J21
VSS
J23
VSS
K2
VSS
K3
VSS
K8
VSS
K10
VSS
K12
VSS
K14
VSS
K16
VSS
K18
VSS
K20
VSS
K22
VSS
Y18
VSS
C627
C10U6.3X50805
C627
C10U6.3X50805
VTT_DDR VCC_DDR
C636
C10U6.3X50805
C636
C10U6.3X50805
C646
X_C10U6.3X50805
C646
X_C10U6.3X50805
C632
X_C10U6.3X50805
C632
X_C10U6.3X50805
3
AA20
AA22
AB13
AB15
AB17
AB19
AB21
AB23
AC12
AC14
AC16
AC18
AC20
AC22
AD11
AD23
AE12
AF11
L20
L22
M21
M23
N20
N22
P21
P23
R22
T23
U22
V23
W22
Y23
C628
X_C10U6.3X50805
C628
X_C10U6.3X50805
2
VCCA_1V2
CPU1HCPU1H
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
5
5
6
6
7
7
8
8
C187
C187
X_180P50N
X_180P50N
C639
X_C10U6.3X50805
C639
X_C10U6.3X50805
C70
X_C10U6.3X50805
C70
X_C10U6.3X50805
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C630
C10U6.3X50805
C630
C10U6.3X50805
N17
N19
N21
N23
P2
P3
P8
P10
P12
P14
P16
P18
P20
P22
R7
R9
R11
R13
R15
R17
R19
R21
R23
T8
T10
T12
T14
T16
T18
T20
T22
U4
U5
U7
U9
U11
U13
U15
U17
U19
U21
U23
V2
V3
V10
V12
V14
V16
V18
V20
V22
W9
W11
W13
W15
W17
W19
W21
W23
Y8
Y10
Y12
W7
Y20
Y22
C10U6.3X50805
C10U6.3X50805
VTT_DDR
VCC_DDR
VCCP
C645
X_224P/16v/6
C645
C95
X_C10U6.3X50805
C95
X_C10U6.3X50805
X_224P/16v/6
C629
C10U6.3X50805
C629
C10U6.3X50805
C643
C643
CPU1ICPU1I
AJ4
VLDT_A1
AJ3
VLDT_A2
AJ2
VLDT_A3
AJ1
VLDT_A4
D12
VTT
C12
VTT
B12
VTT
A12
VTT
AB24
VDDIO
AB26
VDDIO
AB28
VDDIO
AB30
VDDIO
AC24
VDDIO
AD26
VDDIO
AD28
VDDIO
AD30
VDDIO
AF30
VDDIO
M24
VDDIO
M26
VDDIO
M28
VDDIO
M30
VDDIO
P24
VDDIO
P26
VDDIO
P28
VDDIO
P30
VDDIO
T24
VDDIO
T26
VDDIO
T28
VDDIO
T30
VDDIO
V25
VDDIO
V26
VDDIO
V28
VDDIO
V30
VDDIO
Y24
VDDIO
Y26
VDDIO
Y28
VDDIO
Y29
VDDIO
CPU1E
CPU1E
L25
RSVD1
L26
RSVD2
L31
RSVD3
L30
RSVD4
W26
RSVD5
W25
RSVD6
AE27
RSVD7
U24
RSVD8
V24
RSVD9
AE28
RSVD10
Y31
RSVD11
Y30
RSVD12
AG31
RSVD13
V31
RSVD14
W31
RSVD15
AF31
RSVD16
1
1
2
2
3
3
4
4
ZIF-SOCK940-RH-1
ZIF-SOCK940-RH-1
C648
X_224P/16v/6
C648
X_224P/16v/6
0.01u/50V/6/X7R
0.01u/50V/6/X7R
C647
224P/16v/6
C647
224P/16v/6
H6
VLDT_B1
H5
VLDT_B2
H2
VLDT_B3
H1
VLDT_B4
AK12
VTT
AJ12
VTT
AH12
VTT
AG12
VTT
AL12
VTT
K24
VSS
K26
VSS
K28
VSS
K30
VSS
L7
VSS
L9
VSS
L11
VSS
L13
VSS
L15
VSS
L17
VSS
L19
VSS
L21
VSS
L23
VSS
M8
VSS
M10
VSS
M12
VSS
M14
VSS
M16
VSS
M18
VSS
M20
VSS
M22
VSS
N4
VSS
N5
VSS
N7
VSS
N9
VSS
N11
VSS
N13
VSS
N15
VSS
E20
RSVD17
B19
RSVD18
AL4
RSVD19
AK4
RSVD20
AK3
RSVD21
F2
RSVD22
F3
RSVD23
G4
RSVD24
G3
RSVD25
G5
RSVD26
AD25
RSVD27
AE24
RSVD28
AE25
RSVD29
AJ18
RSVD30
AJ20
RSVD31
C18
RSVD32
C20
RSVD33
G24
RSVD34
G25
RSVD35
H25
RSVD36
V29
RSVD37
W30
RSVD38
C649
C649
C670
22P50N0402
C670
22P50N0402
VLDT_RUN_B
VTT_DDR
VCC_DDR
1
C84
C84
C4.7U6.3X5
C4.7U6.3X5
C678
C1000P50X0402
C678
C1000P50X0402
C681
C1000P50X0402
C681
C1000P50X0402
C682
C1000P50X0402
C682
C1000P50X0402
C683
C1000P50X0402
C683
C1000P50X0402
VTT_DDR
A A
C226
180P50N
C226
C291
C4.7U10Y0805
C291
C4.7U10Y0805
180P50N
C237
C1000P50X
C237
C1000P50X
C51
C1000P50X
C51
C1000P50X
4
C634
C634
C1000p50X
C1000p50X
C1000p50X
C1000p50X
C34
224P/16v/6
C34
224P/16v/6
C238
224P/16v/6
C238
224P/16v/6
C213
X_C4.7U10Y0805
C213
X_C4.7U10Y0805
5
C263
C4.7U10Y0805
C263
C4.7U10Y0805
C204
C204
C638
C638
C1000p50X
C1000p50X
VCC_DDRVCC_DDR
EC22
CD1000U16EL20-2+EC22
CD1000U16EL20-2
+
12
C641
X_C10U6.3X50805
C641
X_C10U6.3X50805
C195
C4.7U10Y0805
C195
C4.7U10Y0805
C220
C220
C631
C631
C197
C197
C1000p50X
C1000p50X
C1000p50X
C1000p50X
C1000p50X
C1000p50X
3
C644
C10U6.3X50805
C644
C10U6.3X50805
C669
180P50N
C669
180P50N
VCC3
C671
C671
103P/16V/4
103P/16V/4
2
Title
Title
Title
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
MS-7382 0A
Custom
MS-7382 0A
Custom
MS-7382 0A
Custom
Date: Sheet
Date: Sheet
Date: Sheet
1
of
529Friday, July 27, 2007
of
529Friday, July 27, 2007
of
529Friday, July 27, 2007
5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
5
VCC_DDR
170
55
102
75
19
68
NC
RC118RC0
VDD051VDD156VDD262VDD372VDD478VDD5
VDD3
NC#19
NC/TEST
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
100
103
106
VSS
109
112
115
118
121
124
127
130
133
197
191
194
181
175
VDD6
VDD7
VDD8
VDDQ0
VDDQ153VDDQ259VDDQ364VDDQ4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
136
VSS
139
142
145
148
151
154
157
160
163
MEM_MA_DATA[63..0]4
MEM_MA_ADD[15..0]4,7 MEM_MA_DQS_L[7..0]4
MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
D D
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33
C C
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
B B
MEM_MA_DATA63
A A
MEM_MA_DATA[63..0]
MEM_MA_ADD[15..0] MEM_MA_DQS_L[7..0]
DIMM1
DIMM1
3
4
9
10
122
123
128
129
12
13
21
22
131
132
140
141
24
25
30
31
143
144
149
150
33
34
39
40
152
153
158
159
80
81
86
87
199
200
205
206
89
90
95
96
208
209
214
215
98
99
107
108
217
218
226
227
110
111
116
117
229
230
235
236
2
5
8
11
14
17
20
23
26
29
32
35
38
41
44
47
50
65
66
79
82
85
88
91
94
97
172
187
184
189
178
VDDQ5
VDDQ6
VDDQ7
VDDQ469VDDQ7
VSS
VSS
VSS
VSS
VSS
166
169
198
201
204
67
VDDQ8
VSS
207
VCC3
VDDQ9
VSS
210
238
VSS
213
4
VDDSPD
VSS
VSS
216
219
4
161
CB042CB143CB248CB349CB4
DM0/DQS9
NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
CK1#(CK0#)
VSS
VSS
VSS
VSS
222
225
228
231
162
167
CB5
DQS0
DQS0#
DQS1
DQS1#
DQS2
DQS2#
DQS3
DQS3#
DQS4
DQS4#
DQS5
DQS5#
DQS6
DQS6#
DQS7
DQS7#
DQS8
DQS8#
A10_AP
A16/BA2
CAS#
RAS#
ODT0
ODT1
CKE0
CKE1
CK0(DU)
CK0#(DU)
CK1(CK0)
CK2(DU)
CK2#(DU)
VREF
VSS
VSS
234
237
CB6
WE#
CS0#
CS1#
VSS
MEM_MA_DQS_H[7..0]4
MEM_MA_DM[7..0]4
168
CB7
7
6
16
15
28
27
37
36
84
83
93
92
105
104
114
113
46
45
X3
X3
188
A0
183
A1
63
A2
182
A3
61
A4
60
A5
180
A6
58
A7
179
A8
177
A9
70
57
A11
176
A12
196
A13
174
A14
173
A15
54
190
BA1
71
BA0
73
74
192
125
126
134
135
146
147
155
156
202
203
211
212
223
224
232
233
164
165
195
77
52
171
193
76
185
186
137
138
220
221
120
SCL
119
SDA
X1
X1
1
X2
X2
239
SA0
240
SA1
101
SA2
Address A0
P240_DDR2_DIMM
P240_DDR2_DIMM
MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15
MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7
SCL
SDA
VDDR_VREF
C44
C44
0.1u/25Y/4
0.1u/25Y/4
MEM_MA_DQS_H[7..0]
MEM_MA_DM[7..0]
MEM_MA_BANK2 4,7
MEM_MA_BANK1 4,7
MEM_MA_BANK0 4,7
MEM_MA_WE_L 4,7
MEM_MA_CAS_L 4,7
MEM_MA_RAS_L 4,7
MEM_MA0_ODT0 4,7
MEM_MA_CKE0 4,7
MEM_MA0_CS_L0 4,7
MEM_MA0_CS_L1 4,7
MEM_MA0_CLK_H0 4,7
MEM_MA0_CLK_L0 4,7
MEM_MA0_CLK_H1 4,7
MEM_MA0_CLK_L1 4,7
MEM_MA0_CLK_H2 4,7
MEM_MA0_CLK_L2 4,7
SCL 11,13,21
SDA 11,13,21
VCC_DDR
R24
R24
56.2R1%
56.2R1%
R22
R22
56.2R1%
56.2R1%
3
MEM_MB_DATA[63..0]4
C19
C19
X_0.1u/25Y/4
X_0.1u/25Y/4
C26
C26
0.1u/25Y/4
0.1u/25Y/4
3
MEM_MB_ADD[15..0]4,7
MEM_MB_DATA0
MEM_MB_DATA1
MEM_MB_DATA2
MEM_MB_DATA3
MEM_MB_DATA4
MEM_MB_DATA5
MEM_MB_DATA6
MEM_MB_DATA7
MEM_MB_DATA8
MEM_MB_DATA9
MEM_MB_DATA10
MEM_MB_DATA11
MEM_MB_DATA12
MEM_MB_DATA13
MEM_MB_DATA14
MEM_MB_DATA15
MEM_MB_DATA16
MEM_MB_DATA17
MEM_MB_DATA18
MEM_MB_DATA19
MEM_MB_DATA20
MEM_MB_DATA21
MEM_MB_DATA22
MEM_MB_DATA23
MEM_MB_DATA24
MEM_MB_DATA25
MEM_MB_DATA26
MEM_MB_DATA27
MEM_MB_DATA28
MEM_MB_DATA29
MEM_MB_DATA30
MEM_MB_DATA31
MEM_MB_DATA32
MEM_MB_DATA33
MEM_MB_DATA34
MEM_MB_DATA35
MEM_MB_DATA36
MEM_MB_DATA37
MEM_MB_DATA38
MEM_MB_DATA39
MEM_MB_DATA40
MEM_MB_DATA41
MEM_MB_DATA42
MEM_MB_DATA43
MEM_MB_DATA44
MEM_MB_DATA45
MEM_MB_DATA46
MEM_MB_DATA47
MEM_MB_DATA48
MEM_MB_DATA49
MEM_MB_DATA50
MEM_MB_DATA51
MEM_MB_DATA52
MEM_MB_DATA53
MEM_MB_DATA54
MEM_MB_DATA55
MEM_MB_DATA56
MEM_MB_DATA57
MEM_MB_DATA58
MEM_MB_DATA59
MEM_MB_DATA60
MEM_MB_DATA61
MEM_MB_DATA62
MEM_MB_DATA63
VDDR_VREF
MEM_MB_DATA[63..0]
MEM_MB_ADD[15..0]
55
DIMM2
DIMM2
3
DQ0
4
DQ1
9
DQ2
10
DQ3
122
DQ4
123
DQ5
128
DQ6
129
DQ7
12
DQ8
13
DQ9
21
DQ10
22
DQ11
131
DQ12
132
DQ13
140
DQ14
141
DQ15
24
DQ16
25
DQ17
30
DQ18
31
DQ19
143
DQ20
144
DQ21
149
DQ22
150
DQ23
33
DQ24
34
DQ25
39
DQ26
40
DQ27
152
DQ28
153
DQ29
158
DQ30
159
DQ31
80
DQ32
81
DQ33
86
DQ34
87
DQ35
199
DQ36
200
DQ37
205
DQ38
206
DQ39
89
DQ40
90
DQ41
95
DQ42
96
DQ43
208
DQ44
209
DQ45
214
DQ46
215
DQ47
98
DQ48
99
DQ49
107
DQ50
108
DQ51
217
DQ52
218
DQ53
226
DQ54
227
DQ55
110
DQ56
111
DQ57
116
DQ58
117
DQ59
229
DQ60
230
DQ61
235
DQ62
236
DQ63
2
VSS
5
VSS
8
VSS
11
VSS
14
VSS
17
VSS
20
VSS
23
VSS
26
VSS
29
VSS
32
VSS
35
VSS
38
VSS
41
VSS
44
VSS
47
VSS
50
VSS
65
VSS
66
VSS
79
VSS
82
VSS
85
VSS
88
VSS
91
VSS
94
VSS
97
VSS
100
VSS
RC118RC0
VSS
103
19
106
102
NC#19
VSS
109
VCC_DDR
NC/TEST
VSS
68
NC
VDD051VDD156VDD262VDD372VDD478VDD5
VSS
VSS
VSS
VSS
112
115
118
121
2
VCC3
170
197
191
194
181
175
75
VDD6
VDD7
VDD8
VDD3
VDDQ0
VDDQ153VDDQ259VDDQ364VDDQ4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
124
127
130
VSS
133
136
139
142
145
148
151
154
157
160
2
238
172
187
184
189
67
VDDQ5
VDDQ6
VDDQ469VDDQ7
VSS
VSS
VSS
VSS
163
166
169
198
178
VDDQ7
VSS
201
VSS
204
161
162
167
168
CB042CB143CB248CB349CB4
CB5
CB6
CB7
VDDQ8
VDDQ9
VSS
VSS
VSS
207
210
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
DQS0
VDDSPD
DQS0#
DQS1
DQS1#
DQS2
DQS2#
DQS3
DQS3#
DQS4
DQS4#
DQS5
DQS5#
DQS6
DQS6#
DQS7
DQS7#
DQS8
DQS8#
X3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10_AP
A11
A12
A13
A14
A15
A16/BA2
BA1
BA0
WE#
CAS#
RAS#
DM0/DQS9
NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
ODT0
ODT1
CKE0
CKE1
CS0#
CS1#
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
SCL
SDA
X1
VREF
X2
SA0
SA1
VSS
213
Custom
Custom
Custom
SA2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
216
219
222
225
228
231
234
237
<Title>
<Title>
<Title>
MS-7382 0A
MS-7382 0A
MS-7382 0A
MEM_MB_DQS_H[7..0]4
MEM_MB_DQS_L[7..0]4
MEM_MB_DM[7..0]4
MEM_MB_DQS_H0
7
MEM_MB_DQS_L0
6
MEM_MB_DQS_H1
16
MEM_MB_DQS_L1
15
MEM_MB_DQS_H2
28
MEM_MB_DQS_L2
27
MEM_MB_DQS_H3
37
MEM_MB_DQS_L3
36
MEM_MB_DQS_H4
84
MEM_MB_DQS_L4
83
MEM_MB_DQS_H5
93
MEM_MB_DQS_L5
92
MEM_MB_DQS_H6
105
MEM_MB_DQS_L6
104
MEM_MB_DQS_H7
114
MEM_MB_DQS_L7
113
46
45
X3
MEM_MB_ADD0
188
MEM_MB_ADD1
183
MEM_MB_ADD2
63
MEM_MB_ADD3
182
MEM_MB_ADD4
61
MEM_MB_ADD5
60
MEM_MB_ADD6
180
MEM_MB_ADD7
58
MEM_MB_ADD8
179
MEM_MB_ADD9
177
MEM_MB_ADD10
70
MEM_MB_ADD11
57
MEM_MB_ADD12
176
MEM_MB_ADD13
196
MEM_MB_ADD14
174
MEM_MB_ADD15
173
54
190
71
73
74
192
MEM_MB_DM0
125
126
MEM_MB_DM1
134
135
MEM_MB_DM2
146
147
MEM_MB_DM3
155
156
MEM_MB_DM4
202
203
MEM_MB_DM5
211
212
MEM_MB_DM6
223
224
MEM_MB_DM7
232
233
164
165
195
77
52
171
193
76
185
186
137
138
220
221
120
119
X1
1
X2
239
VCC3
240
101
Address A2
P240_DDR2_DIMM
P240_DDR2_DIMM
1
SCL
SDA
C40
C40
0.1u/25Y/4
0.1u/25Y/4
1
MEM_MB_DQS_H[7..0]
MEM_MB_DQS_L[7..0]
MEM_MB_DM[7..0]
MEM_MB_BANK2 4,7
MEM_MB_BANK1 4,7
MEM_MB_BANK0 4,7
MEM_MB_WE_L 4,7
MEM_MB_CAS_L 4,7
MEM_MB_RAS_L 4,7
MEM_MB0_ODT0 4,7
MEM_MB_CKE0 4,7
MEM_MB0_CS_L0 4,7
MEM_MB0_CS_L1 4,7
MEM_MB0_CLK_H0 4,7
MEM_MB0_CLK_L0 4,7
MEM_MB0_CLK_H1 4,7
MEM_MB0_CLK_L1 4,7
MEM_MB0_CLK_H2 4,7
MEM_MB0_CLK_L2 4,7
VDDR_VREF
of
629Wednesday, July 18, 2007
of
629Wednesday, July 18, 2007
of
629Wednesday, July 18, 2007
5
MEM_MB_BANK24,6
MEM_MA_ADD124,6
MEM_MB_ADD124,6
MEM_MA_ADD94,6
MEM_MB_ADD144,6
MEM_MA_ADD114,6
MEM_MB_ADD94,6
D D
C C
B B
MEM_MA_ADD74,6
MEM_MB_ADD84,6
MEM_MA_ADD64,6
MEM_MB_ADD44,6
MEM_MA_ADD54,6
MEM_MB_ADD24,6
MEM_MA_ADD14,6
MEM_MB_ADD14,6
MEM_MA_ADD24,6
MEM_MB_RAS_L4,6
MEM_MA_RAS_L4,6
MEM_MB0_CS_L04,6
MEM_MA0_CS_L04,6
MEM_MB_ADD104,6
MEM_MA_ADD104,6
MEM_MB_BANK04,6
MEM_MA_BANK04,6
MEM_MB0_CS_L14,6
MEM_MA0_CS_L14,6
MEM_MB_BANK2
MEM_MA_ADD12
MEM_MB_ADD12
MEM_MA_ADD9
MEM_MB_ADD14
MEM_MA_ADD11
MEM_MB_ADD9
MEM_MA_ADD7
MEM_MB_ADD8
MEM_MA_ADD6
MEM_MB_ADD4
MEM_MA_ADD5
MEM_MB_ADD2
MEM_MA_ADD1
MEM_MB_ADD1
MEM_MA_ADD2
MEM_MB_RAS_L
MEM_MA_RAS_L
MEM_MB0_CS_L0
MEM_MA0_CS_L0
MEM_MB_ADD10
MEM_MA_ADD10
MEM_MB_BANK0
MEM_MA_BANK0
MEM_MB0_CS_L1
MEM_MA0_CS_L1
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_CAS_L
MEM_MA_WE_L
MEM_MA_RAS_L
MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
C93 22P50N0402C93 22P50N0402
C185 22P50N0402C185 22P50N0402
C99 22P50N0402C99 22P50N0402
C100 22P50N0402C100 22P50N0402
C141 22P50N0402C141 22P50N0402
C106 22P50N0402C106 22P50N0402
C110 22P50N0402C110 22P50N0402
C105 22P50N0402C105 22P50N0402
C115 22P50N0402C115 22P50N0402
C108 22P50N0402C108 22P50N0402 C121 22P50N0402C121 22P50N0402
C114 22P50N0402C114 22P50N0402
C120 22P50N0402C120 22P50N0402
C126 22P50N0402C126 22P50N0402
C131 22P50N0402C131 22P50N0402
C143 22P50N0402C143 22P50N0402
C154 22P50N0402C154 22P50N0402
C162 22P50N0402C162 22P50N0402
C145 22P50N0402C145 22P50N0402
C96 22P50N0402C96 22P50N0402
C146 22P50N0402C146 22P50N0402
C151 22P50N0402C151 22P50N0402
Decoupling Between Processor and DIMMs
4
VTT_DDR VTT_DDR
2
RN15
RN15
4
8P4R-47R0402
8P4R-47R0402
6
8
2
RN16
RN16
4
8P4R-47R0402
8P4R-47R0402
6
8
2
RN18
RN18
4
8P4R-47R0402
8P4R-47R0402
6
8
2
RN20
RN20
4
8P4R-47R0402
8P4R-47R0402
6
8
2
RN23
RN23
4
8P4R-47R0402
8P4R-47R0402
6
8
2
RN22
RN22
4
8P4R-47R0402
8P4R-47R0402
6
8
2
RN26
RN26
4
8P4R-47R0402
8P4R-47R0402
6
8
VCC_DDR VCC_DDR
MEM_MA_CKE14
MEM_MA_CKE04,6
MEM_MB_CKE14
MEM_MA_ADD154,6
MEM_MB_ADD114,6
MEM_MA_ADD84,6
MEM_MB_ADD74,6
MEM_MB_ADD54,6
MEM_MB_ADD64,6
MEM_MA_ADD44,6
MEM_MB_ADD34,6
MEM_MA_ADD34,6
MEM_MB_ADD04,6
MEM_MA_ADD04,6
MEM_MB_BANK14,6
MEM_MA_BANK14,6
MEM_MB_WE_L4,6
MEM_MA_WE_L4,6
MEM_MB_CAS_L4,6
MEM_MA_CAS_L4,6
MEM_MB_CKE04,6
MEM_MA_ADD144,6
MEM_MB_ADD154,6
MEM_MA_BANK24,6
MEM_MB0_ODT04,6
MEM_MA0_ODT04,6
MEM_MB_ADD134,6
MEM_MA_ADD134,6
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_CAS_L
MEM_MB_WE_L
MEM_MB_RAS_L
MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0
MEM_MA_CKE1
MEM_MA_CKE0
MEM_MB_CKE1
MEM_MA_ADD15
MEM_MB_ADD11
MEM_MA_ADD8
MEM_MB_ADD7
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MA_ADD4
MEM_MB_ADD3
MEM_MA_ADD3
MEM_MB_ADD0
MEM_MA_ADD0
MEM_MB_BANK1
MEM_MA_BANK1
MEM_MB_WE_L
MEM_MA_WE_L
MEM_MB_CAS_L
MEM_MA_CAS_L
MEM_MB_CKE0
MEM_MA_ADD14
MEM_MB_ADD15
MEM_MA_BANK2
MEM_MB0_ODT0
MEM_MA0_ODT0
MEM_MB_ADD13
MEM_MA_ADD13
C101 22P50N0402C101 22P50N0402
C98 22P50N0402C98 22P50N0402C90 22P50N0402C90 22P50N0402
C190 22P50N0402C190 22P50N0402
C109 22P50N0402C109 22P50N0402
C111 22P50N0402C111 22P50N0402
C163 22P50N0402C163 22P50N0402
C117 22P50N0402C117 22P50N0402
C124 22P50N0402C124 22P50N0402
C116 22P50N0402C116 22P50N0402
C129 22P50N0402C129 22P50N0402
C128 22P50N0402C128 22P50N0402
C132 22P50N0402C132 22P50N0402
C135 22P50N0402C135 22P50N0402
C138 22P50N0402C138 22P50N0402
C150 22P50N0402C150 22P50N0402
C170 22P50N0402C170 22P50N0402
C176 22P50N0402C176 22P50N0402
C168 22P50N0402C168 22P50N0402
C104 22P50N0402C104 22P50N0402
C153 22P50N0402C153 22P50N0402
C159 22P50N0402C159 22P50N0402
3
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
RN14
RN14
8P4R-47R0402
8P4R-47R0402
RN17
RN17
8P4R-47R0402
8P4R-47R0402
RN19
RN19
8P4R-47R0402
8P4R-47R0402
RN21
RN21
8P4R-47R0402
8P4R-47R0402
RN24
RN24
8P4R-47R0402
8P4R-47R0402
RN13
RN13
8P4R-47R0402
8P4R-47R0402
RN25
RN25
8P4R-47R0402
8P4R-47R0402
2
MEM_MA0_CLK_H24,6
MEM_MA0_CLK_L24,6
MEM_MA0_CLK_H14,6
MEM_MA0_CLK_L14,6
MEM_MA0_CLK_H04,6
MEM_MA0_CLK_L04,6
MEM_MB0_CLK_H24,6
MEM_MB0_CLK_L24,6
MEM_MB0_CLK_H14,6
MEM_MB0_CLK_L14,6
MEM_MB0_CLK_H04,6
MEM_MB0_CLK_L04,6
MEM_MA0_CLK_H2
C182
C182
C1.5P/4
MEM_MA0_CLK_L2
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H0
MEM_MA0_CLK_L0
MEM_MB0_CLK_H2
MEM_MB0_CLK_L2
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_CLK_H0
MEM_MB0_CLK_L0
VTT_DDR VCC_DDR
C94
0.1u/10X/4
C94
0.1u/10X/4
C92
0.1u/10X/4
C92
0.1u/10X/4
C67
0.1u/10X/4
C67
0.1u/10X/4
C1.5P/4
C63
C63
C1.5P/4
C1.5P/4
C107
C107
C1.5P/4
C1.5P/4
C173
C173
C1.5P/4
C1.5P/4
C47
C47
C1.5P/4
C1.5P/4
C113
C113
C1.5P/4
C1.5P/4
C97
0.1u/10X/4
C97
0.1u/10X/4
C66
0.1u/10X/4
C66
0.1u/10X/4
C273
0.1u/10X/4
C273
0.1u/10X/4
1
C140
0.1u/10X/4
C140
0.1u/10X/4
C155
0.1u/10X/4
C155
0.1u/10X/4
VCC_DDR
A A
VTT_DDR
5
Layout: Spread out on VCC_DDR pour EMI
C215
C1000P50X0402
C215
C178
X_0.1u/25Y/4
C178
C175
180P50N
C175
180P50N
C177
180P50N
C177
180P50N
X_0.1u/25Y/4
C180
0.1u/25Y/4
C180
0.1u/25Y/4
C136
180P50N
C136
180P50N
Layout: Spread out on VTT pour
C188
0.1u/25Y/4
C188
0.1u/25Y/4
C221
0.1u/25Y/4
C221
0.1u/25Y/4
C224
C224
C223
C223
C100p50N0402
C100p50N0402
C100p50N0402
C100p50N0402
C100p50N0402
C100p50N0402
C85
C85
C1000P50X0402
C1000P50X0402
C183
C1000P50X0402
C183
C1000P50X0402
C123
C123
C100p50N0402
C100p50N0402
C100p50N0402
C100p50N0402
C186
C186
C144
C144
C191
C1000P50X0402
C191
C1000P50X0402
C698
C100p50N0402
C698
C100p50N0402
4
C196
C1000P50X0402
C196
C1000P50X0402
C697
C697
C100p50N0402
C100p50N0402
C1000P50X0402
C1000P50X0402
C201
X_22P50N0402
C201
X_22P50N0402
C695
X_0.1u/25Y/4
C695
X_0.1u/25Y/4
C100p50N0402
C100p50N0402
C693
C693
C100p50N0402
C100p50N0402
C205
C205
C700
C700
C1000P50X0402
C222
C1000P50X0402
C222
C1000P50X0402
C200 X_22P50N0402C200 X_22P50N0402
C685 X_0.1u/25Y/4C685 X_0.1u/25Y/4
C209
C1000P50X0402
C209
C1000P50X0402
VCC_DDR
3
C181
C1000P50X0402
C181
C1000P50X0402
C208
0.1u/25Y/4
C208
0.1u/25Y/4
2
VTT_DDR
C689
X_0.1u/25Y/4
C689
X_0.1u/25Y/4
C688
C688
C687
C687
C686
C686
C100p50N0402
C100p50N0402
C100p50N0402
C100p50N0402
C100p50N0402
C100p50N0402
Title
Title
Title
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
MS-7382 0A
Custom
MS-7382 0A
Custom
MS-7382 0A
Custom
Date: Sheet
Date: Sheet
Date: Sheet
1
C691
X_0.1u/25Y/4
C691
X_0.1u/25Y/4
C690
C690
C100p50N0402
C100p50N0402
of
729Friday, July 20, 2007
of
729Friday, July 20, 2007
of
729Friday, July 20, 2007
C100p50N0402
C100p50N0402
C692
C692
5
4
3
2
1
HT_RXCALP
HT_RXCALN
HT_CADOUT_H[15..0]
HT_CADOUT_L[15..0]
HT_CADIN_H[15..0]
HT_CADIN_L[15..0]
U12A
U12A
R19
HT_RXCAD15P
R18
HT_RXCAD15N
R21
HT_RXCAD14P
R22
HT_RXCAD14N
U22
HT_RXCAD13P
U21
HT_RXCAD13N
U18
HT_RXCAD12P
U19
HT_RXCAD12N
W19
HT_RXCAD11P
W20
HT_RXCAD11N
AC21
HT_RXCAD10P
AB22
HT_RXCAD10N
AB20
HT_RXCAD9P
AA20
HT_RXCAD9N
AA19
HT_RXCAD8P
Y19
HT_RXCAD8N
T24
HT_RXCAD7P
R25
HT_RXCAD7N
U25
HT_RXCAD6P
U24
HT_RXCAD6N
V23
HT_RXCAD5P
U23
HT_RXCAD5N
V24
HT_RXCAD4P
V25
HT_RXCAD4N
AA25
HT_RXCAD3P
AA24
HT_RXCAD3N
AB23
HT_RXCAD2P
AA23
HT_RXCAD2N
AB24
HT_RXCAD1P
AB25
HT_RXCAD1N
AC24
HT_RXCAD0P
AC25
HT_RXCAD0N
W21
HT_RXCLK1P
W22
HT_RXCLK1N
Y24
HT_RXCLK0P
W25
HT_RXCLK0N
P24
HT_RXCTLP
P25
HT_RXCTLN
A24
HT_RXCALP
C24
HT_RXCALN
RS690
RS690
PART 1 OF 5
PART 1 OF 5
HT_TXCAD15P
HT_TXCAD15N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD0P
HT_TXCAD0N
HT_TXCLK1P
HT_TXCLK1N
HT_TXCLK0P
HT_TXCLK0N
HYPER TRANSPORT I/F
HYPER TRANSPORT I/F
HT_TXCTLP
HT_TXCTLN
HT_TXCALP
HT_TXCALN
P21
P22
P18
P19
M22
M21
M18
M19
L18
L19
G22
G21
J20
J21
F21
F22
N24
N25
L25
M24
K25
K24
J23
K23
G25
H24
F25
F24
E23
F23
E24
E25
L21
L22
J24
J25
N23
P23
C25
D24
HT_CADIN_L15
HT_CADIN_H14
HT_CADIN_L14
HT_CADIN_H13
HT_CADIN_L13
HT_CADIN_H12
HT_CADIN_L12
HT_CADIN_H11
HT_CADIN_L11
HT_CADIN_H10
HT_CADIN_L10
HT_CADIN_H9
HT_CADIN_L9
HT_CADIN_H8
HT_CADIN_L8
HT_CADIN_H7
HT_CADIN_L7
HT_CADIN_H6
HT_CADIN_L6
HT_CADIN_H5
HT_CADIN_L5
HT_CADIN_H4
HT_CADIN_L4
HT_CADIN_H3
HT_CADIN_L3
HT_CADIN_H2
HT_CADIN_L2
HT_CADIN_H1
HT_CADIN_L1
HT_CADIN_H0
HT_CADIN_L0
HT_TXCALP
HT_TXCALN
U12B
U12B
G5
G4
J8
J7
J4
J5
L8
L7
L4
L5
M8
M7
M4
M5
P8
P7
P4
P5
R4
R5
R7
R8
U4
U5
W4
W5
Y4
Y5
V9
W9
AB7
AB6
A_RX2P12
HT_CLKIN_H1 3
HT_CLKIN_L1 3
HT_CLKIN_H0 3
HT_CLKIN_L0 3
HT_CTLIN_H0 3
HT_CTLIN_L0 3
R138 100/4/1R138 100/4/1R152 49.9/4R152 49.9/4
A_RX2N12
A_RX3P12
A_RX3N12
RX_LANP017
RX_LANN017
A_RX0P12
A_RX0N12
A_RX1N12
A_RX1P12
W11
W12
AA11
AB11
Y7
AA7
AB9
AA9
W14
W15
AA12
AB12
AA14
AB14
GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
SB_RX0P
SB_RX0N
SB_RX1N
SB_RX1P
NC1
NC2
RS690
RS690
PART 2 OF 5
PART 2 OF 5
PCIE GFX I/F
PCIE GFX I/F
PCIE I/F GPP
PCIE I/F GPP
PCIE I/F SB
PCIE I/F SB
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
PCE_CALRP
PCE_CALRN
J1
H2
K2
K1
K3
L3
L1
L2
N2
N1
P2
P1
P3
R3
R1
R2
T2
U1
V2
V1
V3
W3
W1
W2
Y2
AA1
AA2
AB2
AB1
AC1
AE3
AE4
A_TX2P0
A_TX2N0
A_TX3P0
A_TX3N0
TX_LANP0
TX_LANN0
A_TX0P_C
A_TX0N_C
A_TX1P_C
A_TX1N_C
PCEH_PCAL
PCEH_NCAL
C347 0.1u/10X/4C347 0.1u/10X/4
C345 0.1u/10X/4C345 0.1u/10X/4
C354 0.1u/10X/4C354 0.1u/10X/4
C350 0.1u/10X/4C350 0.1u/10X/4
C355 0.1u/16Y/4C355 0.1u/16Y/4
C362 0.1u/16Y/4C362 0.1u/16Y/4
C322 0.1u/10X/4C322 0.1u/10X/4
C316 0.1u/10X/4C316 0.1u/10X/4
C341 0.1u/10X/4C341 0.1u/10X/4
C338 0.1u/10X/4C338 0.1u/10X/4
R191 562R/1/4R191 562R/1/4
R195 2KR1%0402R195 2KR1%0402
A_TX2P 12
A_TX2N 12
A_TX3P 12
A_TX3N 12
TXLANP 17
TXLANN 17
A_TX0P 12
A_TX0N 12
A_TX1P 12
A_TX1N 12
VDDA12_PKG2
AD8
AE8
AD7
AE7
AD4
AE5
AD5
AD6
AE9
AD10
AC8
AD9
AD11
AE11
HT_CADOUT_H[15..0]3
HT_CADOUT_L[15..0]3
HT_CADIN_H[15..0]3
D D
C C
VDDHT_PKG
B B
HT_CADIN_L[15..0]3
HT_CADOUT_H15 HT_CADIN_H15
HT_CADOUT_L15
HT_CADOUT_H14
HT_CADOUT_L14
HT_CADOUT_H13
HT_CADOUT_L13
HT_CADOUT_H12
HT_CADOUT_L12
HT_CADOUT_H11
HT_CADOUT_L11
HT_CADOUT_H10
HT_CADOUT_L10
HT_CADOUT_H9
HT_CADOUT_L9
HT_CADOUT_H8
HT_CADOUT_L8
HT_CADOUT_H7
HT_CADOUT_L7
HT_CADOUT_H6
HT_CADOUT_L6
HT_CADOUT_H5
HT_CADOUT_L5
HT_CADOUT_H4
HT_CADOUT_L4
HT_CADOUT_H3
HT_CADOUT_L3
HT_CADOUT_H2
HT_CADOUT_L2
HT_CADOUT_H1
HT_CADOUT_L1
HT_CADOUT_H0
HT_CADOUT_L0
HT_CLKOUT_H13
HT_CLKOUT_L13
HT_CLKOUT_H03
HT_CLKOUT_L03
HT_CTLOUT_H03
HT_CTLOUT_L03
R137 49.9/4R137 49.9/4
A A
Title
Title
Title
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
MS-7382 0A
Custom
MS-7382 0A
Custom
MS-7382 0A
Custom
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
1
of
829Wednesday, July 18, 2007
of
829Wednesday, July 18, 2007
of
829Wednesday, July 18, 2007
5
PLLVDD12VCCA_1V2
AVDDVCC3
AVDDDI
PLLVDD
HTPVDD
C260
C260
0.1u/16Y/4
0.1u/16Y/4
C296
C296
0.1u/16Y/4
0.1u/16Y/4
C312
C312
C4.7U10Y0805
C4.7U10Y0805
C344
C344
2.2u/6.3V/6
2.2u/6.3V/6
C246
C246
2.2u/6.3V/6
2.2u/6.3V/6
C252
C252
2.2u/6.3V/6
2.2u/6.3V/6
C340
C340
0.1u/16Y/4
0.1u/16Y/4
C243
C243
0.1u/16Y/4
0.1u/16Y/4
C254
C254
0.1u/16Y/4
0.1u/16Y/4
L19 X_500mALL19 X_500mAL
CP13CP13
D D
+1.8V_S0
R181 X_500mALR181 X_500mAL
CP20CP20
L30 500mALL30 500mAL
C C
+1.8V_S0
L32 X_500mALL32 X_500mAL
CP25CP25
+1.8V_S0
L15 X_500mALL15 X_500mAL
CP7CP7
B B
+1.8V_S0 AVDDQ
L21 X_500mALL21 X_500mAL
CP15CP15
4
LDT_STOP#3,12
VCC3
R239 10K/4R239 10K/4
R234 39K/4R234 39K/4
R256 4.7K/4R256 4.7K/4
R245 4.7K/4R245 4.7K/4
R233 4.7K/4R233 4.7K/4
R170 150R/1/4R170 150R/1/4
R168 150R/1/4R168 150R/1/4
R163 150R/1/4R163 150R/1/4
+1.8V_S0 VCC3
R249
R249
4.7K/4
4.7K/4
B
CE
Q34
Q34
N-MMBT3904_NL_SOT23
N-MMBT3904_NL_SOT23
STRP_DATA
DAC_SCL
DCC_DATA
I2C_CLK
I2C_DATA
R24
G24
B24
ALLOW_LDTSTOP12
R
G
B
VSYNC#24
HSYNC#24
DAC_SCL24
DAC_SDAT24
PCI_RST1#16,21
NB_PWRGD13,21
HTREFCLK11
NB_OSC_14M11
NBSRCCLK11
NBSRCCLK#11
SBLINKCLK11
SBLINKCLK#11
R257
R257
1KR1%0402
1KR1%0402
3
R176 715RR176 715R
PLLVDD
HTPVDD
LDT_STOP_NB#
VCC3
PLLVDD12
TP23TP23
R237
R237
4.7K/4
4.7K/4
AVDDDI
AVDDQ
R153 10K/4R153 10K/4
R246 10K/4R246 10K/4
I2C_CLK
I2C_DATA
DCC_DATA
STRP_DATA
RSET
AVDD
U12C
U12C
B22
C22
G17
H17
A20
B20
A21
A22
C21
C20
D19
E19
F19
G19
C6
A5
B21
B6
A6
A10
B10
B24
B25
C10
C11
C5
B5
C23
B23
C2
B11
A11
F2
E1
G1
G2
D6
D7
C8
C7
B8
A8
B2
A2
B4
AA15
AB15
C14
B3
C3
A3
RS690
RS690
AVDD
AVDD
AVSSN
AVSSN
AVDDDI
AVSSDI
AVDDQ
AVSSQ
C
Y
COMP
RED
GREEN
BLUE
DACVSYNC
DACHSYNC
RSET
DACSCL
DACSDA
PLLVDD18
PLLVSS
HTPVDD
HTPVSS
SYSRESET#
POWERGOOD
LDTSTOP#
ALLOW_LDTSTOP
HTTSTCLK
HTREFCLK
TVCLKIN
OSCIN
PLLVDD12
GFX_CLKP
GFX_CLKN
SB_CLKP
SB_CLKN
DFT_GPIO0
DFT_GPIO1
DFT_GPIO2
DFT_GPIO3
DFT_GPIO4
DFT_GPIO5
BMREQ#
I2C_CLK
I2C_DATA
THERMALDIODE_P
THERMALDIODE_N
TMDS_HPD
DDC_DATA
TESTMODE
STRP_DATA
PART 3 OF 5
PART 3 OF 5
CRT/TVOUT
CRT/TVOUT
PLL PWR
PLL PWR
PM
PM
CLOCKs
CLOCKs
MIS.
MIS.
2
TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N
TXCLK_LP
TXCLK_LN
TXCLK_UP
TXCLK_UN
LVTMDVO
LVTMDVO
LVDDR18D
LVDDR18D
LVDDR33
LVDDR33
GPP_TX0P
GPP_TX0N
GPP_RX0P
GPP_RX0N
DEBUG10
GPP_TX1N
GPP_TX1P
GPP_RX1N
GPP_RX1P
DEBUG15
DEBUG14
DEBUG13
LPVDD
LPVSS
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
GPIO3
GPIO2
GPIO4
DEBUG6
DEBUG9
DEBUG0
DEBUG2
DEBUG1
B14
B15
B13
A13
H14
G14
D17
E17
A15
B16
C17
C18
B17
A17
A18
B18
E15
D15
H15
G15
D14
+1.8V_S0
E14
A12
+1.8V_S0
B12
C12
VCC3
C13
A16
A14
D12
1. Each LVSSR ball should connect to GND
C19
through seperated via.
C15
C16
2. LPVSS connect to GND through dedicated via.
F14
F15
E12
G12
F12
AD14
AD15
AE15
AD16
AE16
AC17
AD18
AE19
AD19
AE20
AD20
AE21
AD13
AC13
AE13
AE17
AD17
1
A A
Title
Title
Title
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
MS-7382 0A
Custom
MS-7382 0A
Custom
MS-7382 0A
Custom
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
1
of
929Friday, July 27, 2007
of
929Friday, July 27, 2007
of
929Friday, July 27, 2007
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