MSI MS-6722 Schematics

5

Change History

4

3

2

1

Page Description

3

D D

4
7
8
9

10
12
13
14
15
16
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22
23

C C

24
25
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29
32
33
34
35
37
38
39

3

18
26

B B

28
30
31
33
34
35

DE-POP CE7,CB19
DE-POP CB138,CB129,C61~C66,C69,C80,C81,C83~C90
DE-POP CB144,CB149
DE-POP CB162
DE-POP CB136,CB138
DE-POP CB159,CB156,CB91,CB94,CB171
DE-POP CB7,CB4,CB153,CB23,CB104,CB72,CB81,CB139
DE-POP CB107,CB16,CB134,CB68,CB83,CB158,CB73,CB132,CB9,CB141,CB89,CB50,CB99
DE-POP CB218
DE-POP CB264
DE-POP CB212
DE-POP CB194,CB201,CB222,CB216
DE-POP CB178,CB180,CB176,CB184
REMOVE RN85~RN88 ,RN92~RN95 ,R330,R366,R341,R374
DE-POP L8,L9, COST DOWN FROM ESD/EMIC199,C195,C209,C204 (EMI) ,DE-POP C76~C79 (ESD) ,ADD R459~R462
REMOVE L2~L5 (EMI) ,REPLACE BY ADD R455~R458 COST DOWN FROM EMI
DE-POP C267
DE-POP C239
REMOVE R74/R39 AND REPLACE BY CP52/CP53
DE-POP C6,CB1

,DE-POP R126,R128,R133,Q15, POP R454
DE-POP C296,EC24
DE-POP EC16,EC30,EC15,EC5,D13,D10,C245,
DE-POP EC23,CB90,CB84,CB42,CB47,CB26,CB41,CB78,
DE-POP C298,C47,C180,C30,C179,C299,C274,C291,C254,C308,C29,C281,C295,CB206,CB220 ,C225,C82,C67
REMOVE C72,C91,C60,C94 AND ADD CP48~CP51
DE-POP R128,R133,R126 , POP R454 COST DOWN
DE-POP R237,R245,Q24,Q25
REMOVE R232,R233,Q22,Q23,E235,R234 ,DE-POP R194
REMOVE F2
DE-POP R386,RT1,R388,R387,R399,R390,R391,R389,R400,R401,R394,Q27
DE-POP D7,D4,R67,C301,R428,Q36
RESERVED R463 (0 ohm)
DE-POP D18,D14
REMOVE R152
POP D24

COST DOWN
COST DOWN
COST DOWN
COST DOWN
COST DOWN
COST DOWN
COST DOWN
COST DOWN
COST DOWN
COST DOWN
COST DOWN
COST DOWN
COST DOWN
COST DOWN

COST DOWN
COST DOWN
COST DOWN FROM ESD/EMI
COST DOWN FROM EMI
COST DOWN
COST DOWN
COST DOWN FROM EMI
COST DOWN
COST DOWN FROM ESD

COST DOWN
ONLY AGP 4X SPEC
COST DOWN
W/O HARDWARE MONITPR
W/O SERIAL PORT WAKE-UP
2M FLASHROM
COST DOWN
ONLY AGP 4X SPEC
3VSBY INDICATOR

Notice

DATE

02/09/10
02/09/10
02/09/10
02/09/10
02/09/10
02/09/10
02/09/10
02/09/10
02/09/10
02/09/10
02/09/10
02/09/10
02/09/10
02/09/10
02/09/10
02/09/10
02/09/10
02/09/10
02/09/10
02/09/10
02/09/10
02/09/10
02/09/10
02/09/10
02/09/10
02/09/11
02/09/12
02/09/12
02/09/12
02/09/12
02/09/12
02/09/12
02/09/12
02/09/12
02/09/12

A A

Title

History

Size Document Number Rev

MS-6722 0A

Custom

5

4

3

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Date: Sheet

041Thursday, September 12, 2002

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DDR SDRAM SLOT *3

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Last Schematic Update Date:
09/11/2002

History

Cover Sheet
Block Diagram

D D

MS-6722

VERSION:0.A

SIS 645DX CHIPSET
Willamette/Northwood 478pin mPGA-B Processor Schematics

MAIN CLOCK GEN
DDR CLOCK BUFFER
mPGA478-B INTEL CPU Sockets
SIS 645 NORTH BRIDGE
DDR SLOT

CPU:

Willamette/Northwood mPGA-478B Processor

DDR TERMINATOR
SIS 962 SOUTH BRIDGE

System Chipset:

AGP SLOT
PCI SLOTS

C C

SIS 645DX (NB)+ SIS962L (SB)

On Board Chipset:

LPC Super I/O -- W83697HF
ETHERNET CONTROLLER--INTEL 82551QM

(OPTIONAL)

IDE CONNECTOR
USB CONNECTOR
KB/MS CONNECTOR

AC'97 CODEC

AUDIO CONNECTOR

Expansion Slots:

DDR SDRAM SLOT*3
AGP2.0 SLOT * 1

PCI2.2 SLOT* 5

B B

LPC I/O(W83697HF)
HARDWARE MONITOR
PARALLEL PORT
SERIAL PORT
FLASH MEMORY
VRM 9.X
VOLTAGE REGULATOR
ACPI CONTROL
ATX POWER CON
FRONT PANEL
Decoupling Capacitor
LAVON (1)
LAVON (2)
LAYOUT SCREW

A A

0

1
2
3

4
5 - 6
7- 10

11-12

13

14-17

18
19-21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

MICRO-STAR INT'L CO.,LTD.

Title

COVER PAGE

Size Document Number Rev

MS-6722 0A

C

8

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5

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3

Date: Sheet

2

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141Thursday, September 12, 2002

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System Block Diagram

D D

SOCKET-478

Host Bus

Support Dual Monitor

VGA

D-SUB

VGA SLOT

DDR SDRAM

SSTL-2 Termination

(Only for DDR)

SIS645

C C

INTEL
82551

PCI SLOT 6

PCI SLOT 4PCI SLOT 5

VGA Connector

Support Max to six-PCI Devices

PCI SLOT 3 PCI SLOT 2 PCI SLOT 1

VGA CONNECTOR

VGA

HyperZip

512 MB

SiS962

IDE 1

B B

IDE 2

KEYBOARD
/MOUSE

FAN1FAN

Legacy
ROM

2

PS/2

FAN CONTROL

FAN CONTROL

LPC Super I/O

LPC Bus

VOLTAGE MONITOR

TEMPERATURE MONITOR

DIMM 1 DIMM 2 DIMM 3

AC'97

Audio Codec

ACR

USB 3 USB 0

USB 2

USB 4

USB 5

USB 1

Analog In

Analog Out

Rtt

IR/CIR

8

7

6

GAME/MIDIGPIOs

SERIAL PARALLEL FLOPPY

5

MICRO-STAR INT'L CO.,LTD.

Title

System Block Diagram

Size Document Number Rev

MS-6722 0A

B

4

3

Date: Sheet

2

241Thursday, September 12, 2002

of

1

A

8

A

VCC3

L21

X_80-0805

CP25

X_COPPER

D D

CE7
X_22u

C C

VCCP

CB188

+

0.1u

VCC3

R237

X_10K

X_NPN-3904LT1-S-SOT23

CB204

CB187

0.1u

0.1u

R246
X_10K

Q24

X_NPN-3904LT1-S-SOT23

VCC3

B B

CB190

0.1u

Q25

R245
10K

VCC3

VCC3

+

7

CB189

0.1u

CB207

0.1u

R244

CP26 X_COPPER

L23

X_80-0805

CB203

X_0.1u

CE6

X_22u

CB214

0.1u

CB192

0.1u

CB195

0.1u

CB208

0.1u

475ST

CB193

100p

6

5

Main Clock Generator

(3 OPTIONS)
1: (ICS)
2: (Cypress)

3. (Hitachi)

U11
952001AF

1

VDDREF

11

VDDZ

13

VDDPCI

19

VDDPCI

28

VDD48

29

VDDAGP

42

VDDCPU

CB191

X_100p

48

VDDSD

12

PCI_STOP#

45

CPU_STOP#

5

VSSREF

8

VSSZ

18

VSSPCI

24

VSSPCI

25

VSS48

32

VSSAGP

41

VSSCPU

46

VSSSD

33

PD#/VTT_PWRGD

38

IREF

36

VDDA

37

VSSA

XIN

6

Y2

14M-32pf-HC49S-D

C205
22p

CPUCLK0

CPUCLK#0

CPUCLK1

CPUCLK#1

AGPCLK0
AGPCLK1

PCICLK_F0/FS3
PCICLK_F1/FS4

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5

REF0/FS0
REF1/FS1
REF2/FS2

24_48M/MULTISEL

XOUT

7

C196
22p

SDCLK

ZCLK0
ZCLK1

48M

SCLK

SDATA

4

Damping Resistors
Place near to the
Clock Outputs

R261

40
39

44
43

47
31

30
9

10

FS3

14

FS4

15
16
17
20
21
22
23

FS0

2

FS1

3

FS2

4
27

26

MULTISEL SIO48M

35
34

R262
R259

R260
R258

R263
R264

R306

R307

RN73 33

7 8
5 6
3 4
1 2

Option:A/B (Remove)

RN72 33

R315
R265
R266

33
33

33
33

22
22
22

22

22

7 8
5 6
3 4
1 2

RN74 33

7 8
5 6
3 4
1 2

X_22
22
22

SMBCLK
SMBDAT

VCC3

R302 2.7K
R308 X_2.7K

R290 X_2.7K
R317 2.7K

MULTISEL

3

CPUCLK0
CPUCLK-0

CPUCLK1
CPUCLK-1

UCLK48M

AGPCLK0
AGPCLK1

ZCLK0
ZCLK1

CPUCLK0 5
CPUCLK-0 5

CPUCLK1 7
CPUCLK-1 7

SDCLK 8
AGPCLK0 7
AGPCLK1 18

ZCLK0 9
ZCLK1 14

96XPCLK
SIOPCLK
PCICLK1

PCICLK3
PCICLK4
PCICLK5
LAN_CLK

REFCLK0
REFCLK1
APICCLK APICCLK

96XPCLK 14
SIOPCLK 28
PCICLK1 19
PCICLK2 20

PCICLK3 20
PCICLK4 21
PCICLK5 21
LAN_CLK 39

REFCLK0 9
REFCLK1 15
APICCLK 15

REFCLK2 25
UCLK48M 16
SIO48M 28

SMBCLK 4,11,12,15,27,35,40
SMBDAT 4,11,12,15,27,35,40

FS0
FS1

FS3

R247 X_0

2

By-Pass Capacitors
Place near to the Clock Outputs

CPUCLK0
CPUCLK-0

CPUCLK1
CPUCLK-1

SDCLK

AGPCLK0
AGPCLK1SDCLK

ZCLK0

ZCLK1

PCICLK2
PCICLK1PCICLK2
SIOPCLK
96XPCLK

LAN_CLK
PCICLK5
PCICLK4
PCICLK3

REFCLK0
REFCLK1

REFCLK2

UCLK48M
SIO48M

Frequency Selection

BSEL0 5

R316
R318

10K
10K

VCC3 VCC3

R242
R243

R240
R241

C173 10p

C174 X_10p

C175 X_10p

C221 X_10p

C234 X_10p

CN9 10p

1 2
3 4
5 6
7 8

CN8 10p

1 2
3 4
5 6
7 8

C236 10p

C227 10p

C235 10p

C233 10p

C176 10p

C177 10p

FS2
FS4

49.9ST

49.9ST

49.9ST

49.9ST

1

FS4 FS1FS2FS3 FS0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

000

0

001

0

010

0

011

0
0

101

0

11

0

111

0

000

1

001

1

010

1

011

1
1

101

1

11

1

111

1

8

SIS650 CLOCK SIS650 CLOCK

CPU PCI
(MHz) (MHz) (MHz)

001

0

001

0

7

SDRAM

ZCLK
(MHz)

AGPCLK
(MHz)

6

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

001

0

010

0

011

0
0

101

0

11

0

111

0

000

1

001

1

010

1

011

1
1

101

1

11

1

111

1

000

0

5

R267 X_4.7K

CPU PCI

SDRAM

(MHz) (MHz) (MHz)

001

0

001

0

ZCLKFS4 FS1FS2FS3 FS0

4

AGPCLK
(MHz)(MHz)

3

VCC3

MICRO-STAR INT'L CO.,LTD.

Title

Size Document Number Rev

B

Date: Sheet

C273
1000p

MAIN CLOCK GEN

MS-6722 0A

2

C214
1000p

C292
1000p

VCC5

341Thursday, September 12, 2002

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D D

VCC2.5V

CB137

0.1u

C C

CP9 X_COPPER

VCC2.5V

L12
X_80-0805

B B

CP7 X_COPPER

L10
X_80-0805

CB138
X_0.01u

CE3
X_22u

CB129

X_0.1u

CB101

0.1u

SMBCLK
SMBDAT

CB130

0.01u

CB100

0.1u

CBVDD

FWDSDCLKO

FB_OUT

Clock Buffer (DDR)

(OPTIONS)
1: (ICS-93705)

CBVDD

CB115

0.1u

15
11

21
28
34
38
45

16

17
12

37
13

14
35

4

U3
93705CF

VDDI2C
VDD
VDD
VDD
VDD
VDD
VDD
VDD

AVDD

AGND
SCLK

SDATA
CLK_IN

NC
FB_IN

CB128

0.1u

CB114

0.1u

CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9

CLK#0
CLK#1
CLK#2
CLK#3
CLK#4
CLK#5
CLK#6
CLK#7
CLK#8
CLK#9

FB_OUT

3
5
10
20
22
46
44
39
29
27

2
6
9
19
23
47
43
40
30
26

R84

33
32

NC

DDRCLK[0..8]
DDRCLK-[0..8]
SMBCLK

SMBDAT
FWDSDCLKO

DDRCLK0
DDRCLK1
DDRCLK2
DDRCLK3
DDRCLK5
DDRCLK4
DDRCLK8
DDRCLK7
DDRCLK6

DDRCLK-0
DDRCLK-1
DDRCLK-2
DDRCLK-3
DDRCLK-5
DDRCLK-4
DDRCLK-8
DDRCLK-7
DDRCLK-6

22

FB_OUT

C68

10p

DDRCLK[0..8] 11,12
DDRCLK-[0..8] 11,12
SMBCLK 3,11,12,15,27,35,40

SMBDAT 3,11,12,15,27,35,40
FWDSDCLKO 8

By-Pass Capacitors
Place near to the Clock Buffer

DDRCLK0
DDRCLK1
DDRCLK2
DDRCLK3
DDRCLK5
DDRCLK4
DDRCLK8
DDRCLK7
DDRCLK6

DDRCLK-0
DDRCLK-1
DDRCLK-2
DDRCLK-3
DDRCLK-5
DDRCLK-4
DDRCLK-8
DDRCLK-7
DDRCLK-6

C81 X_10p
C83 X_10p
C86 X_10p
C88 X_10p
C89 X_10p
C62 X_10p
C63 X_10p
C66 X_10p
C70 X_10p

C80 X_10p
C84 X_10p
C85 X_10p
C87 X_10p
C90 X_10p
C61 X_10p
C64 X_10p
C65 X_10p
C69 X_10p

36

NC

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

178182425314142

48

A

MICRO-STAR INT'L CO.,LTD.

Title

DDR CLOCK BUFFER

Size Document Number Rev

MS-6722 0A

B

8

7

6

5

4

3

Date: Sheet

2

441Thursday, September 12, 2002

of

1

8

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CPU GTL REFERNCE VOLTAGE BLOCKCPU SIGNAL BLOCK

HA#[3..31]7

VID[0..4] 33

D D

U2A

HDBI#[0..3]7

STPCLK#15

HDBSY#7

HDRDY#7

HTRDY#7

C C

B B

A A

HDEFER#7

Trace : 10
mil width
10mil space

CPU_TMPA29

VTIN_GND29

PROCHOT#28

CPUSLP#15

BSEL03

CPURST#7

HD#[0..63]7

8

HLOCK#7

R55 X_33

IGNNE#15

CPU_GD7

HDBI#0
HDBI#1
HDBI#2
HDBI#3

FERR#15

INIT#15

HADS#7
HBNR#7

HIT#7

HITM#7

HBPRI#7

ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_TCK
CPU_TMPA

THERMTRIP#

PROCHOT#
IGNNE#
SMI#

SMI#15

A20M#15

A20M#
CPUSLP#

CPU_GD
CPURST#
HD#63

HD#62
HD#61
HD#60
HD#59
HD#58
HD#57
HD#56
HD#55
HD#54

E21
G25
P26
V21

AC3

AA3
AB2

AF26

AB26

A22

AD2

AD3
AE21
AF24
AF25

AD6

AD5
AB23
AB25
AA24

AA22
AA25

Y21
Y24
Y23

W25

Y26

W26

V24

V6
B6
Y4

W5

H5
H2

J6

G1
G4
G2
F3
E3
D2
E2

C1
D5
F7
E6
D4
B3
C4
A2

C3
B2
B5
C6

A7

DBI0#
DBI1#
DBI2#
DBI3#

IERR#
MCERR#
FERR#
STPCLK#
BINIT#
INIT#
RSP#

DBSY#
DRDY#
TRDY#

ADS#
LOCK#
BNR#
HIT#
HITM#
BPRI#
DEFER#

TDI
TDO
TMS
TRST#
TCK
THERMDA
THERMDC
THERMTRIP#
GND/SKTOCC#
PROCHOT#
IGNNE#
SMI#
A20M#
SLP#

RESERVED0
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6

BSEL0
BSEL1

PWRGOOD
RESET#
D63#

D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#

AB1Y1W2V3U4T5W1R6V2T4U3P6U1T2R3P4P3R2T1N5N4N2M1N1M4M3L2M6L3K1L6K4K2

A35#

D53#

D52#

D51#

D50#

V22

U21

V25

U23

U24

HD#52

HD#50

HD#49

HD#51

HD#53

7

A34#

D49#

U26

HD#48

A33#

D48#

T23

HD#47

HA#31

A32#

D47#

HD#46

T22

HA#30HD#45

A31#

D46#

T25

HA#29

A30#

D45#

HD#44

T26

HA#28

A29#

D44#

HD#43

R24

HA#27

A28#

D43#

R25

HD#42

HA#26

A27#

D42#

HD#41

P24

HA#25

A26#

D41#

R21

HD#40

HA#24

A25#

D40#

N25

HD#39

HA#23

A24#

D39#

HD#38

N26

HA#22

A23#

D38#

M26

HD#37

HA#21

A22#

D37#

HD#36

N23

HA#20

A21#

D36#

M24

HD#35

HA#19

A20#

D35#

P21

HD#34

6

HA#18HD#33

A19#

D34#

N22

HA#17

A18#

D33#

HD#32

M23

HA#16

A17#

D32#

H25

HD#31

HA#15

A16#

D31#

K23

HD#30

HA#14

A15#

D30#

J24

HD#29

HA#13

A14#

D29#

HD#28

L22

HA#12

A13#

D28#

M21

HD#27

HA#11

A12#

D27#

H24

HD#26

HA#10

A11#

D26#

G26

HD#25

HA#9

A10#

D25#

L21

HD#24

A9#

D24#

HA#5

HA#4

HA#3

HA#8

HA#7

HA#6

AE25A5A4

AD26

A8#

A7#

A6#

A5#

A4#

A3#

DBR#

VSS_SENSE

VCC_SENSE

Differential
Host Data
Strobes

D23#

D22#

D21#

D20#

D19#

D18#

D17#

D16#

D15#

D14#

D13#

D12#

D11#

D26

F26

E25

F24

F23

G23

E24

H22

D25

J21

D23

C26

H21

G22

HD#17

HD#13

HD#22

HD#19

HD#21

HD#23

HD#20

HD#18

HD#12

HD#14

HD#11

HD#16

HD#10

HD#15

5

VID2

VID0

VID1

VID4

VID3

AC26

AE1

AE2

AE3

AE4

AE5

VID4#

VID3#

VID2#

VID1#

ITP_CLK1

ITP_CLK0

D10#

D9#

D8#

B25

C24

HD#8

HD#9

VID0#

LINT1/NMI

LINT0/INTR

D7#

D6#

D5#

D4#

D3#

D2#

C23

B24

D22

C21

A25

A23

B22

HD#3

HD#5

HD#7

HD#6

HD#1

HD#4

HD#2

GTLREF3
GTLREF2
GTLREF1
GTLREF0

BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#

REQ4#
REQ3#
REQ2#
REQ1#
REQ0#

TESTHI12
TESTHI11
TESTHI10

TESTHI9
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0

BCLK1#
BCLK0#

RS2#
RS1#
RS0#

AP1#
AP0#
BR0#

COMP1
COMP0

DP3#
DP2#
DP1#
DP0#

ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#

D1#

D0#

B21

HD#0

AA21
AA6
F20
F6

AB4
AA5
Y6
AC4
AB5
AC6

H3
J3
J4
K5
J1

AD25
A6
Y3
W4
U6
AB22
AA20
AC23
AC24
AC20
AC21
AA2
AD24

AF23
AF22

F4
G5
F1

V5
AC1
H6

P1
L24

L25
K26
K25
J26

R5
L5
W23
P23
J23
F21
W22
R22
K22
E22

E5
D1

PGA-S478-F02

4

GTLREF1

BPM#5
BPM#4

BPM#1
BPM#0

HREQ#4
HREQ#3
HREQ#2
HREQ#1
HREQ#0

R52 56
R25 56

R51 56

R50 56

RS#2
RS#1

RS#0

R31 49.9ST
R58 49.9ST

VCCP

CPUCLK-0 3
CPUCLK0 3

RS#[0..2] 7

HBR#0 7

* Short trace

HADSTB#1 7
HADSTB#0 7
HDSTBP#3 7
HDSTBP#2 7
HDSTBP#1 7
HDSTBP#0 7
HDSTBN#3 7
HDSTBN#2 7
HDSTBN#1 7
HDSTBN#0 7

NMI 15
INTR 15

HREQ#[0..4] 7

3

Length < 1.5inch.

GTLREF1

2/3*Vccp

C36 R54

C35

220p

220p

Every pin put one 220pF cap near it.
Trace Width 15mils, Space 15mils.
Keep the voltage dividers within 1.5 inches of the
first GTLREF Pin

CPU ITP BLOCK

ITP_TMS
ITP_TDO

ITP_TCK

R27 39
R28 75

R30 27

CPU STRAPPING RESISTORS

ALL COMPONENTS CLOSE TO CPU

PROCHOT#
CPU_GD
HBR#0
CPURST#
THERMTRIP#

BPM#0
BPM#1
BPM#4
BPM#5

ITP_TDI
ITP_TRST#

CPU_GD
CPURST#
CPUSLP#

MICRO-STAR INT'L CO.,LTD.

Title

mPGA478 CPU-1

Size Document Number Rev

MS-6722 0A
Custom
Date: Sheet of

2

R15 62
R56 62
R34 49.9ST
R57 49.9ST
R36 62

R21 49.9ST
R22 49.9ST
R24 49.9ST
R23 49.9ST

R35 150
R29 680

VCCP

R53

49.9ST

C42

1u

X_1000pC45
X_1000pC46
X_0.022uC7

VCCP

100ST

VCCP

VCCP

VCCP

541Thursday, September 12, 2002

1

8

7

6

5

4

3

2

1

AD22

Y5
Y25
Y22
Y2
W6
W3
W24
W21
V4
V26
V23
V1
U5
U25
U22
U2
T6
T3
T24
T21
R4
R26
R23
R1
P5
P25
P22
P2
N6
N3
N24
N21
M5
M25
M22
M2
L4
L26
L23
L1
K6
K3
K24

C43
22u-1206

VCC_VID 35

C40
22u-1206

C315
1u

C316
1u

L7 4.7u-10%
L6 4.7u-10%

VCCP

CPU VOLTAGE BLOCK

VCCP

A10

A12

A14

A16

A18

A20A8AA10

AA12

AA14

AA16

AA18

AA8

AB11

AB13

AB15

AB17

AB19

AB7

AB9

AC10

AC12

AC14

AC16

AC18

AC8

AD11

AD13

AD15

AD17

AD19

AD7

AD9

AE10

AE12

AE14

AE16

AE18

AE20

AE6

AE8

AF11

AF13

AF15

AF17

AF19

AF2

AF21

AF5

AF7

AF9

B11

B13

B15

B17

B19B7B9

C10

C12

C14

C16

C18

C20C8D11

D13

D15

D17

D19D7D9

E10

E12

E14

E16

E18

E20E8F11

F13

F15

F17

F19

VCC

VSS

VCC

VSS

VCC

VSS

G21G6G24

VCC

VCC

VCC

VSS

VSS

VSS

G3H1H23

F9

VCC

VSS

VSS

U2B

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

F14

VSS

F16

VSS

VSS

F18F2F22

VSS

VCC

VSS

VSS

F25F5F8

D D

C C

D10
A11
A13
A15
A17
A19
A21
A24
A26

AA1
AA11
AA13
AA15
AA17
AA19
AA23
AA26

AA4

AA7

AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24

AB3

AB6

AB8

AC11
AC13
AC15
AC17
AC19

AC2
AC22
AC25

AC5

AC7

AC9

AD1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A3

VSS

A9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

AD10

AD12

AD14

AD16

AD18

AD21

AD4

AD23

AD8

AE11

AE13

AE15

AE17

AE19

AE22

AE24

AE26

AE7

AE9

AF1

AF10

AF12

AF14

AF16

AF18

AF20

AF6

AF8

B10

B12

B14

B16

B18

B23

B20

B26B4B8

C11

C13

C15

C17C2C19

C22

C25C5C7C9D12

D14

D16

D18

D20

D21D3D24D6D8E1E11

E13

E15

E17

E19

E23

E7E9F10

F12

E4

E26

AF4

VCC-VID

VSS

H26H4J2

VSS

AF3

VCC-VIDPRG

VSS

VSS

J22

AE23

VCC-IOPLL

VSS

J25J5K21

VSS

AD20

VCCA

VSSA

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

PGA-S478-F02

B B

CPU DECOUPLING CAPACITORS

VCCP

CB17
X_10u-1206
CB19
10u-1206
CB22
X_10u-1206
CB37
10u-1206
CB46
X_10u-1206
CB49
10u-1206
CB61
X_10u-1206
CB64
10u-1206

A A

8

CB66
X_10u-1206

VCCP VCCP VCCP VCCP

CB15
10u-0805

CB55
10u-0805

CB51
10u-1206

CB56
10u-0805

CB57
10u-0805

CB28
10u-0805
CB29
10u-0805
CB30
10u-0805
CB31
10u-0805
CB32
10u-0805
CB33
10u-0805
CB34
10u-0805

CB65
10u
CB35
10u
CB58
10u
CB48
10u
CB20
10u
CB62
10u
CB38
10u
CB18
10u

PLACE CAPS WITHIN CPU CAVITY

7

6

5

CB67
10u
CB39
10u
CB59
10u
CB21
10u
CB14
10u

BOTTOM

VCCP

CB228

X_10u-1206

{Asm Cfg}

CB227

X_10u-1206

MICRO-STAR INT'L CO.,LTD.

Title

mPGA478 CPU-2

Size Document Number Rev

MS-6722 0A

Custom

4

3

Date: Sheet

2

641Thursday, September 12, 2002

of

1

8

A

D D

CPUCLK13

CPUCLK-13

HDEFER#5

HLOCK#5
HTRDY#5

CPURST#5

CPU_GD5

HBPRI#5

HBR#05

RS#[0..2]5

HADS#5

HITM#5

HIT#5

HDRDY#5

HDBSY#5

HBNR#5

C C

HREQ#[0..4]5

HREQ#[0..4]

HA#[3..31]5

B B

VCCP

VCCP VCCP

R127
75ST

R129

150ST

8

CPUCLK1 ACBE#3

CPUCLK-1 ACBE#2

HLOCK#
HTRDY# AREQ#
CPURST# AGNT#
CPU_GD AFRAME#

HBPRI# AIRDY#

HBR#0 ATRDY#

RS#2 ASERR#
RS#1 ASTOP#

RS#[0..2]

HITM# RBF#
HDRDY# PIPE#

HDBSY#

HADSTB#15
HADSTB#05

HA#[3..31]

R105

20ST

R92

110ST

place this capacitor
under 650 solder side

RS#0
HADS#
HIT# WBF#

HBNR#

HREQ#4 ADBIL
HREQ#3
HREQ#2 SBSTB
HREQ#1 SBSTB#
HREQ#0

HADSTB#1 ADSTB#0
HADSTB#0

HA#31
HA#30
HA#29
HA#28
HA#27
HA#26
HA#25
HA#24
HA#23
HA#22
HA#21
HA#20
HA#19
HA#18
HA#17
HA#16
HA#15
HA#14
HA#13
HA#12
HA#11
HA#10
HA#9
HA#8
HA#7
HA#6
HA#5
HA#4
HA#3

HNCOMP

Rds-on(n) = 10 ohm
HNCVERF = 1/3 VCCP

Rds-on(p) = 56 ohm
HPCVERF = 2/3 VCCP

HD#[0..63]5

CB125
X_0.01u

CB131

0.01u

HD#[0..63]

HVREF

CB133

0.1u

7

AJ26

AH26

U26
U24

V26
C20
D19

T27
U25

T24

T26
U29

V28

T28
U28

W26

V24

V27

W28
W29
W24
W25

Y27

AD24
AA24

AF26
AE25
AH28
AD26
AG29
AE26
AF28
AC24
AG28
AE29
AD28
AC25
AD27
AE28
AF27
AB24
AB26
AC28
AC26
AC29
AA26
AB28
AB27
AA25
AA29
AA28

Y26

Y24

Y28

7

CPUCLK
CPUCLK#

DEFER#
HLOCK#
HTRDY#
CPURST#
CPUPWRGD
BPRI#
BREQ0#

RS#2
RS#1
RS#0

ADS#
HITM#
HIT#
DRDY#
DBSY#
BNR#

HREQ#4
HREQ#3
HREQ#2
HREQ#1
HREQ#0

HASTB#1
HASTB#0

HA#31
HA#30
HA#29
HA#28
HA#27
HA#26
HA#25
HA#24
HA#23
HA#22
HA#21
HA#20
HA#19
HA#18
HA#17
HA#16
HA#15
HA#14
HA#13
HA#12
HA#11
HA#10
HA#9
HA#8
HA#7
HA#6
HA#5
HA#4
HA#3

B21

HD#63

C1XAVSS

C1XAVDD

C4XAVSS

AH25

AJ25

AH27

AJ27

C1XAVSS

C4XAVSS

C1XAVDD

HOST

HD#63

HD#62

HD#61

HD#60

HD#59

HD#58

HD#57

HD#56

F19

A21

E19

D22

D20

B22

C22

B23

HD#62

HD#61

HD#60

HD#59

HD#58

HD#57

HD#56

HD#55

R94

150ST

HNCVREF

R97

75ST

C4XAVDD

HVREF

U21

HVREF0

C4XAVDD

HD#55

HD#54

HD#53

A23

D21

HD#54

HD#53

HD#52

CB106
X_0.01u

CB108

0.01u

6

T21

P21

HVREF1

HVREF2

HD#52

HD#51

F22

D24

HD#51

6

5

HPCOMP

HNCOMP

HNCVREF

ST0

ST1

ST2

AAD0

AAD1

AAD2

AAD3

AAD4

AAD5

AAD6

AAD7

AAD8

AAD9

AAD10

AAD11

AAD12

AAD13

AAD14

AAD15

AAD16

AAD17

AAD18

AAD19

AAD20

AAD21

N21

J17

B20

B19

A19A7F9B7M6M5M4L3L6L4K6L2K3J3K4J2J6J4J1H6F4F1G6E3F5E2E4E1D3D4C2F7C3E6B2D5D6A3D7C5A5C6D8

ST0

ST1

ST2

AAD0

AAD1

AAD2

AAD3

AAD4

AAD5

AAD6

AAD7

AAD8

AAD9

AAD10

AAD11

AAD12

AAD13

AAD14

AAD15

AAD16

AAD17

AAD18

AAD19

AAD20

HVREF3

HVREF4

HPCOMP

HNCOMP

HNCOMPVREF

AAD21

AAD22

AAD23

AAD22

AAD23

AAD24

AAD25

AAD24

AAD26

AAD25

AAD26

4

AAD27

AAD27

645-1

HD#50

HD#49

HD#48

HD#47

HD#46

HD#45

HD#44

HD#43

HD#42

HD#41

HD#40

HD#39

HD#38

HD#37

HD#36

HD#35

HD#34

HD#33

HD#32

HD#31

HD#30

HD#29

HD#28

HD#27

HD#26

HD#25

HD#24

HD#23

HD#22

HD#21

HD#20

HD#19

HD#18

HD#17

HD#16

HD#15

HD#14

HD#13

D23

C24

B24

E25

E23

D25

A25

C26

B26

B27

D26

B28

E26

F28

G25

F27

F26

G24

H24

G29

J26

G26

J25

H26

G28

H28

J24

K28

J29

K27

J28

M24

L26

K26

L25

L28

M26

P26

L29

HD#50

HD#49

HD#48

HD#47

HD#46

HD#45

HD#44

HD#43

HD#42

HD#41

HD#40

HD#39

HD#38

HD#37

HD#36

HD#35

HD#33

HD#32

HD#31

HD#30

C1XAVDD

C1XAVSS

CB98

0.01u

HD#34

CP4

1 2

X_COPPER

CP6

1 2

X_COPPER

5

HD#29

HD#28

VCC3

HD#27

HD#26

HD#25

CT14
X_10u-0805

HD#18

HD#24

HD#23

HD#22

HD#21

HD#20

HD#19

HD#17

HD#16

HD#15

HD#14

HD#13

HD#12

C4XAVDD

C4XAVSS

4

AAD28

AAD29

AAD30

AAD31

SBA7

SBA6

SBA5

SBA7

SBA6

AAD29

AAD30

AAD31

SBA5

AAD28

AGP

HD#12

HD#11

HD#10

HD#9

HD#8

HD#7

HD#6

HD#5

N24

N26

M27

N28

P27

N29

R24

HD#8

HD#7

HD#6

HD#5

HD#9

HD#11

HD#10

CB97

0.01u

SBA4

SBA3

SBA4

SBA3

HD#4

HD#3

R28

M28

HD#4

HD#3

HD#2

1 2

X_COPPER

1 2

X_COPPER

P28

CP3

SBA2

SBA2

HD#2

R26

HD#1

CP5

SBA1

C7

SBA1

HD#1

R29

HD#0

SBA0

SBA0

HD#0

AC/BE#3
AC/BE#2
AC/BE#1
AC/BE#0

AREQ#
AGNT#

AFRAME#

AIRDY#

ATRDY#

ADEVSEL#

ASERR#
ASTOP#

APAR

RBF#
WBF#
PIPE#

AGP8XDET

ADBIH
ADBIL

SB_STB

SB_STB#
AD_STB0

AD_STB#0

AD_STB1

AD_STB#1

AGPCLK

AGPRCOMP

A1XAVDD
A1XAVSS

A4XAVDD
A4XAVSS

AGPVREF

AGPVSSREF

HDSTBN#3
HDSTBN#2
HDSTBN#1
HDSTBN#0

HDSTBP#3
HDSTBP#2
HDSTBP#1
HDSTBP#0

DBI#3

DBI#2

DBI#1

DBI#0

E21

A27

H27

R25

HDBI#3

HDBI#2

HDBI#1

HDBI#0

VCC3

CT13
X_10u-0805

3

U6A

F6
F3

ACBE#1

H4

ACBE#0HDEFER#

K5
C9

A6
G2
G1
G3

ADEVSEL#

G4
H5
H1

APAR

H3
E8

F8
D9

D10

ADBIH

B3
C4

B5
A4

ADSTB0

K1
L1

ADSTB1

C1

ADSTB#1

D1

AGPCLK0

B10

AGPRCOMP

M1

A1XAVDD

B9

A1XAVSS

A9

A4XAVDD

B8

A4XAVSS

A8

AVREFGC

M3
M2

HDSTBN#3

F20

HDSTBN#2

F23

HDSTBN#1

K24

HDSTBN#0

P24

HDSTBP#3

F21

HDSTBP#2

F24

HDSTBP#1

L24

HDSTBP#0

N25

SIS645

HDBI#[0..3] 5

Title

Size Document Number Rev

B

Date: Sheet

3

2

AAD[0..31]
SBA[0..7]
ACBE#[0..3]
ST[0..2]
ADSTB[0..1]
ADSTB#[0..1]

AREQ# 18
AGNT# 18
AFRAME# 18
AIRDY# 18
ATRDY# 18
ADEVSEL# 18
ASERR# 18
ASTOP# 18

APAR 18
RBF# 18

WBF# 18
PIPE# 18

ADBIH 18
ADBIL 18

SBSTB 18
SBSTB# 18

AGPCLK0 3

AVREFGC 18

HDSTBN#3 5
HDSTBN#2 5
HDSTBN#1 5
HDSTBN#0 5

HDSTBP#3 5
HDSTBP#2 5
HDSTBP#1 5
HDSTBP#0 5

MICRO-STAR INT'L CO.,LTD.

SIS645/650-1

MS-6722 0A

A1XAVDD

A1XAVSSHPCOMP

A4XAVDD

A4XAVSS

AAD[0..31] 18

SBA[0..7] 18

ACBE#[0..3] 18

ST[0..2] 18
ADSTB[0..1] 18
ADSTB#[0..1] 18

AGPRCOMP

CB144

0.1u

CB148

0.1u

CB149
X_0.01u

2

R164

62

1 2

X_COPPER

CB142
X_0.01u

1 2

X_COPPER

CP14

1 2

X_COPPER

CP13

1 2

X_COPPER

CP12

CP11

741Thursday, September 12, 2002

1

VDDQ

VCC3

CT20
X_10u-0805

VCC3

CT22
X_10u-0805

of

1

A

8

A

7

6

5

4

3

2

1

RMD[0..63]

RMA0
RMA1
RMA2
RMA3

RMA4
RMA5
RMA6
RMA7
RMA8
RMA9
RMA10

RMA11

RMA12
RMA13
RMA14

RSRAS#
RSCAS#
RSWE#

RCS-0
RCS-1
RCS-2
RCS-3
RCS-4
RCS-5

RDQM[0..7]
RDQS[0..7]
RMA[0..14]
RCS-[0..5]
CKE[0..5]

RSRAS# 11,12,13
RSCAS# 11,12,13
RSWE# 11,12,13

S3AUXSW# 34

VCC3SBY

SDCLK 3

FWDSDCLKO 4

D D

Rs place close to DIMM1

RMD1 MD1 MD0
RMD5 MD5 MD1
RMD4 MD4 MD2
RMD0 MD0 MD3
RMD6 MD6 MD4
RMD2 MD2 MD5
RDQM0 DQM0 MD6
RDQS0 DQS0 MD7
RMD9 MD9 DQM0
RMD8 MD8 DQS0
RMD7 MD7 MD8
RMD3 MD3 MD9
RMD11 MD11 MD10
RMD10 MD10 MD11
RMD15 MD15 MD12
RMD14 MD14 MD13
RDQM1 DQM1 MD14
RMD13 MD13 MD15
RDQS1 DQS1 DQM1
RMD12 MD12 DQS1
RMD21 MD21 MD16
RMD17 MD17 MD17
RMD16 MD16 MD18

C C

B B

RMD20 MD20 MD19
RMD22 MD22 MD20
RMD18 MD18 MD21
RDQM2 DQM2 MD22
RDQS2 DQS2 MD23
RMD28 MD28 DQM2
RMD24 MD24 DQS2
RMD23 MD23 MD24
RMD19 MD19 MD25
RMD31 MD31 MD26
RMD27 MD27 MD27
RMD30 MD30 MD28
RMD26 MD26 MD29
RDQM3 DQM3 MD30
RDQS3 DQS3 MD31
RMD25 MD25 DQM3
RMD29 MD29 DQS3
RMD37 MD37 MD32 CKE0
RMD33 MD33 MD33 CKE1
RMD36 MD36 MD34 CKE2
RMD32 MD32 MD35 CKE3
RMD38 MD38 MD36 CKE4
RMD34 MD34 MD37 CKE5
RDQM4 DQM4 MD38
RDQS4 DQS4 MD39
RMD44 MD44 DQM4
RMD40 MD40 DQS4
RMD35 MD35 MD40 SDCLK
RMD39 MD39 MD41
RDQS5 DQS5 MD42 FWDSDCLKO
RDQM5 DQM5 MD43
RMD41 MD41 MD44
RMD45 MD45 MD45
RMD47 MD47 MD46

RMD43 MD43
RMD42 MD42 DQS5
RMD55 MD55 MD48 SDAVSS
RDQS6 DQS6 MD49
RMD54 MD54 MD50
RDQM6 DQM6 MD51 DDRAVDD
RMD53 MD53 MD52
RMD52 MD52 MD53 DDRAVSS
RMD49 MD49
RMD48 MD48 MD55
RMD56 MD56 DQM6
RMD60 MD60 DQS6 DDRVREFA
RMD51 MD51 MD56 DDRVREFB
RMD50 MD50 MD57
RMD62 MD62
RDQM7 DQM7 MD59 DDRAVDD
RMD57 MD57
RMD61 MD61 MD61

RMD63 MD63
RMD58 MD58
RDQS7 DQS7

RN3

10
RN5

10
RN7

10
RN11

10
RN9

10
RN16

10
RN19

10
RN25

10
RN31

10
RN28

10
RN38

10
RN40

10
RN41

10
RN44

10
RN47

RN52

10
RN50

10
RN54

10
RN57

10

RN61
10

10

1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8

MD47RMD46 MD46
DQM5 SDAVDD

MD54

MD58
MD60
MD62RMD59 MD59

MD63
DQM7
DQS7

AJ23
AG22
AH21

AJ21
AD23
AE23
AF22
AF21
AD22
AH22
AD21
AG20
AE19
AF19
AE21
AD20
AD19
AH19
AF20
AH20
AF18
AG18
AH17
AD16
AD18
AD17
AF17

AJ17
AE17
AH18
AD14
AG14

AJ13
AE13

AJ15
AF14
AD13
AF13
AH13
AH14
AD10
AH10

AE9

AD8
AG10
AF10

AH9

AF9

AD9

AH5

AG4

AE5

AH3

AG6

AF6

AF5

AF4

AH4

AE4

AD6

AE2

AC5

AG2

AG1

AF3

AC6

AD4

AF2

AB6

AD3

AA6

AB3

AC4

AE1

AD2

AC1

AB4

AC2

AJ9

AJ3

U6B

MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
DQM0
DQS0/CSB#0
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
DQM1
DQS1/CSB#1
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
DQM2
DQS2/CSB#2
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
DQM3
DQS3/CSB#3
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
DQM4
DQS4/CSB#4
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
DQM5
DQS5/CSB#5
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
DQM6
DQS6/CSB#6
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
DQM7
DQS7/CSB#7

SIS645

645-2

MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8

MA9
MA10
MA11
MA12
MA13
MA14

SRAS#
SCAS#

SWE#

CS#0
CS#1
CS#2
CS#3
CS#4
CS#5

CKE0
CKE1
CKE2
CKE3
CKE4
CKE5

S3AUXSW#

SDCLK

FWDSDCLKO

SDRCLKI

SDAVDD
SDAVSS

DDRAVDD
DDRAVSS

DDRVREFA
DDRVREFB

DRAM_SEL

AH11
AF12
AH12
AG12
AD12
AH15
AF15
AH16
AE15
AD15
AF11
AG8
AJ11
AG16
AF16

AH8
AJ7
AH7

AE7
AF7
AH6
AJ5
AF8
AD7

AB2
AA4
AB1
Y6
AA5
Y5
Y4

AA3
AD11
AE11

Y1
Y2

AA1
AA2

AJ19
AH2

R201 4.7K

W3

Rs place close to DIMM1

R134 22

S3AUXSW#

R208 4.7K

C100

10u-0805

SDAVDD

SDAVSS

DDRAVSS

RMD[0..63] 11,12,13

RDQM[0..7] 11,12,13
RDQS[0..7] 11,12,13
RMA[0..14] 11,12,13
RCS-[0..5] 11,12,13

CKE[0..5] 11,12

DDRVREFA

DDRVREFB

CB163

0.1u

CB162

CB160

0.1u
X_0.01u

CB117
X_0.01u

CB116

0.01u

CB150
X_0.01u

CB151

0.01u

CP23

1 2

X_COPPER

L19

X_80

CB164
X_0.01u

CP22

1 2

X_COPPER

CP20

1 2

X_COPPER

L17

X_80

CP15 X_COPPER

1 2

VCCM

VCCM

R108
150ST

R120
150ST

R153
150ST

R154
150ST

VCC3

VCC3VCC3SBY

CT25
X_10u-0805

CT23
X_10u-0805

A

MICRO-STAR INT'L CO.,LTD.

Title

SIS645/650-2

Size Document Number Rev

MS-6722 0A

B

8

7

6

5

4

3

Date: Sheet

2

841Thursday, September 12, 2002

of

1

8

A

D D

ZAD[0..15]14
ZSTB[0..1]14

ZSTB-[0..1]14

ZAD[0..15]
ZSTB[0..1]
ZSTB-[0..1]

C C

VCC1_8

CB165

R178

X_0.1u

150ST

ZVREF

CB161

R172

0.1u

150ST

B B

VCC3

L18 X_80

CP21

1 2

C135

C136

8

VCC3

X_COPPER

L15 X_80

CP17

1 2

X_COPPER

X_10u-0805

X_10u-0805

C126

0.1u

0.1u

C129

Z1XAVDD

Z1XAVSS

Z4XAVDD

Z4XAVSS

7

NOTE: This page is for universal PCB design( suitable for both 645 or 650)

ZCLK03

ZUREQ14
ZDREQ14

VCC1_8

C138

X_10u-0805

7

6

NB Hardware Trap Table

DLLEN#
DRAM_SEL
TRAP0

TRAP1
CSYNC
RSYNC
LSYNC

ZCLK0
ZUREQ

ZDREQ
ZSTB0

ZSTB-0
ZSTB1

ZSTB-1
ZAD0

ZAD1 TRAP1
ZAD2
ZAD3 CSYNC
ZAD4
ZAD5 INTA# LSYNC
ZAD6
ZAD7
ZAD8 CSYNC
ZAD9 RSYNC
ZAD10 LSYNC
ZAD11
ZAD12
ZAD13 VCOMP
ZAD14 VRSET
ZAD15 VVBWN ENTEST
ZVREF
VDDZCMP

ZCMP_N
ZCMP_P DACAVSS2

VSSZCMP
Z1XAVDD DCLKAVSS

Z1XAVSS
Z4XAVDD ECLKAVSS

Z4XAVSS

L16 X_80

CP19

1 2

X_COPPER

0
enable PLL disable PLL
SDR DDR
normal NB debug mode

TV selection, NTSC/PAL(0/1) 0
enable VB
enable VGA interface
enable panel link

U6C
SIS645

V3

ZCLK

U6

ZUREQ

U1

ZDREQ

T3

ZSTB0

T1

ZSTB#0

P1

ZSTB1

P3

ZSTB#1

T4

ZAD0

R3

ZAD1

T5

ZAD2

T6

ZAD3

R2

ZAD4

R6

ZAD5

R1

ZAD6

R4

ZAD7

P4

ZAD8

N3

ZAD9

P5

ZAD10

P6

ZAD11
ZAD12
ZAD13
ZAD14
ZAD15
ZVREF
VDDZCMP

ZCMP_N
ZCMP_P

VSSZCMP
Z1XAVDD

Z1XAVSS
Z4XAVDD

Z4XAVSS

PCIRST1#

PWRGD
AUXOK

HyperZip

R175 56

R176 56

N1
N6
N2
N4
U3

V5
U4
U2

V6

W1
W2

V2

V1

PCIRST1#28,35,39

PWRGD15,35,39

AUXOK15,34

C137

0.1u

6

PCIRST#

PWROK

Y3W4W6

5

1

VGA

Stereo
Glass

645-3

AUXOK

TRAP1

TRAP0

D11

E10

TRAP1

5

TESTMODE2

TESTMODE1

A10

F11

C11

VDDZCMP

ZCMP_N

ZCMP_P

VSSZCMP

Default

1(DDR)

TESTMODE0

E11

0

0

0
1
0

DLLEN#

ENTEST

F10

ENTEST

4

embedded pull-low
(30~50K Ohm)

yes
yes
yes

C15

VOSCI

A12

ROUT

B13

GOUT

A13

BOUT

F13

HSYNC

E13

VSYNC

D13

VGPIO0

D12

VGPIO1

B11

INT#A

E12

CSYNC

A11

RSYNC

F12

LSYNC

E14

VCOMP

D14

VRSET

F14

VVBWN

B12

DACAVDD1

C12

DACAVSS1

C13

DACAVDD2

C14

DACAVSS2

B15

DCLKAVDD

A15

DCLKAVSS

B14

ECLKAVDD

A14

ECLKAVSS

DCLKAVDD

DCLKAVSS

4

ECLKAVDD

ECLKAVSS

3

REFCLK0

DACAVDD2 PWRGD
DACAVSS2

DACAVDD2

DCLKAVDD

ECLKAVDD

CB121

X_0.1u

CB123

X_0.1u

REFCLK0 3

INTA# 14,18,19,20,21

CSYNC 18
RSYNC 18
LSYNC 18

VCC3

CE2

X_10u-0805

VCC3

CE1

X_10u-0805

3

for 650 only

CB122

VVBWN

CB120

VCOMP

DACAVDD2

DACAVSS2

MICRO-STAR INT'L CO.,LTD.

Title

SIS645/650

Size Document Number Rev

MS-6722 0A

B

Date: Sheet

2

RSYNC

2

X_0.1u

X_0.1u

CB135

X_1u

R157 X_4.7K
R149 X_4.7K
R161 X_4.7K
R166 X_4.7K

R144 4.7K
C150 X_0.1u

VRSET

VCC1_8

1

VCC3

CE5

X_10u-0805

941Thursday, September 12, 2002

1

R130

X_130ST

of

A

8

A

VCCP VCC1_8 VCC3

H21

H22

J16

J20

J21

VTT

PVDDP

PVDDP

R19

U19

VCC1_8

VTT

VTT

PVDDP

PVDDP

W19

VTT

J22

VTT

VTT

VSS

VSS

M12

M13

VCCP

A16

VTT

A17

VTT

A18

VTT

B16

VTT

8

AB5
AD5
AE6

AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE22

V10

V11

W18

Y10

Y12

Y14

Y16

Y18

Y19

AA8

AA9
AA10
AA13
AA14
AA15
AA16
AA17

AB8

AB9
AB13
AB17

K11

K13

N10

P10

R10

B17
B18
C16
C17
C18
D15
D16
D17
D18
E15
E16
E17
E18
F15
F16
F17
F18

J10
J13

L10

W5

T10
T11

VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT

VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM

VDDM
VDDM
VDDM

Y9

VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM

E5

VDDQ

E7

VDDQ

E9

VDDQ

G5

VDDQ

J5

VDDQ

L5

VDDQ

H8

VDDQ

H9

VDDQ

J8

VDDQ

J9

VDDQ
VDDQ
VDDQ

K9

VDDQ
VDDQ
VDDQ
VDDQ

N9

VDDQ
VDDQ

N5

VDDZ

R5

VDDZ

U5

VDDZ
VDDZ

P9

VDDZ
VDDZ

R9

VDDZ
VDDZ

T9

VDDZ
VDDZ
VDDZ

PVDDP

PVDDP

L17

L19

N19

D D

VCCM

C C

VDDQ

B B

VCC1_8

K16

M14

VTT

VSS

K17

M15

VTT

VSS

K18

M16

VTT

VSS

K19

M17

VTT

VSS

K20

M18

VTT

VSS

K21

N12

VTT

VSS

7

L20

M20

N20

P20

R20

R21

T20

U20

V20

W20

Y20

Y21

AA20

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VTT

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

N13

N14

N15

N16

N17

N18

P12

P13

P14

P15

P16

P17

P18

7

6

AA21

AA22

AB21

AB22

L12

L14

L15

L16

L18

VTT

VTT

VTT

VTT

IVDD

IVDD

IVDD

IVDD

645-4

Power

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

R12

R13

R14

R15

R16

R17

R18

T12

T13

T14

6

IVDD

VSS

M11

T15

IVDD

VSS

M19

T16

N11

IVDD

VSS

T17

P19

IVDD

VSS

T18

IVDD

VSS

R11

U12

IVDD

VSS

T19

U13

IVDD

VSS

U11

U14

IVDD

VSS

V19

U15

IVDD

VSS

W11

U16

W13

IVDD

VSS

U17

IVDD

VSS

W15

U18

W17

IVDD

VSS

V12

IVDD

VSS

V13

VSS

P11

PVDDZ

VSS

V14

V15

VSS

5

5

J14

OVDD

VSS

V16

J15

OVDD

VSS

V17

K15

OVDD

VSS

V18

K10

PVDD

K12

PVDD

VSS

B25

K14

PVDD

VSS

C28

VCC3SBY

M10

PVDD

VSS

VSS

C29

D27

W10

Y11

PVDDM

VSS

D28

E28

Y13

Y15

PVDDM

PVDDM

VSS

VSS

E29

AF23

Y17

PVDDM

PVDDM

VSS

VSS

AF24

AF25

VSS

AG24

AUX1.8
AUX3.3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS

AG26

VSS

AH23

VSS

AH24

4

U6D

U10
U9

A20
A22
A24
A26
C19
C21
C23
C25
C27
E20
E22
E24
F25
H25
K25
M25
P25
T25
V25
Y25
AB25
AD25
E27
G27
J27
L27
N27
R27
U27
W27
AA27
AC27
AE27
D29
F29
H29
K29
M29
P29
T29
V29
Y29
AB29
AD29
AF29
AE24
AG25
B4
B6
C8
C10
D2
F2
H2
K2

P2
T2
V4
AD1
AF1
AC3
AE3
AG3
AG5
AG7
AG9
AG11
AG13
AG15
AG17
AG19
AG21
AG23
AJ4
AJ6
AJ8
AJ10
AJ12
AJ14
AJ16
AJ18
AJ20
AJ22
AJ24
AG27

SIS645

4

3

VCC3SBY

VCC1_8SBY
VCC3SBY

VCCP

CB118

1u
CB113

1u
CB77

1u
CB94

X_1u

VDDQ

CB157

0.1u
CB159

X_0.1u

Place these capacitors under 635 solder side

VCCP

CB230

X_0.1u
CB231

X_0.1u
CB234

X_0.1u
CB229

X_0.1u

VCC1_8

3

CB156

X_0.1u
CB155

0.1u

CB240

X_0.1u
CB241

X_0.1u
CB232

X_0.1u
CB246

X_0.1u

2

VCC3

CB126

1u

CB171

X_1u
CB172

0.1u

CB119

0.1u
CB102

0.1u
CB76

0.1u
CB45

0.1u

VCCM

CT19

X_10u-0805

CT21

X_10u-0805

VCCM

CB233

X_0.1u
CB235

X_0.1u
CB242

X_0.1u
CB238

X_0.1u

MICRO-STAR INT'L CO.,LTD.

Title

SIS645/650-4

Size Document Number Rev

MS-6722 0A

B

Date: Sheet

CB224

0.1u
CB226

0.1u

VCC3

CB239

X_0.1u

CB236

X_0.1u

VCC1_8SBY

CB91

X_0.1u
CB124

0.1u

2

CB173

1u
CB174

0.1u

VCC3SBY

VDDQ

1

CB112

1u
CB143

0.1u

CB237

X_0.1u
CB244

X_0.1u

CB245

X_0.1u
CB243

X_0.1u

10 41Thursday, September 12, 2002

of

1

A

8

A

RMD[0..63]8,12,13

RMA[0..14]8,12,13

RDQM[0..7]8,12,13

RDQS[0..7]8,12,13

RMA[0..14]
RDQM[0..7] RDQM[0..7]
RDQS[0..7]

D D

NOTE:

VDDID IS A TRAP ON THE DIMM
MODULE TO INDICATE:

VDDID

REQUIRED POWER

OPEN

VDD=VDDQ

GND

VDD!=VDDQ

MEMORY MUX TABLE:

C C

DDR

SDR
CS0

CS0

CS1

CS1

CS2

CS2

CS3

CS3

CS4

CS4
CS5 CS5
CSB0

DQS0
CSB1

DQS1
CSB2

DQS2
CSB3

DQS3

DQS4

CSB4

DQS5

CSB5

DQS6

CSB6

DQS7

CSB7

VCCM VCCM

R68 8.2K R66 8.2K

B B

9,21,22





RSRAS#8,12,13
RSCAS#8,12,13

RSWE#8,12,13

RCS-[0..5]
CKE[0..5]
DDRCLK[0..8]
DDRCLK-[0..8]

9,21,22
9,21,22

RCS-[0..5]8,12,13

CKE[0..5]8,12

DDRCLK[0..8]4,12

DDRCLK-[0..8]4,12

8

7

RDQM0
RDQM1
RDQM2
RDQM3
RDQM4
RDQM5
RDQM6
RDQM7

RDQS0
RDQS1
RDQS2
RDQS3
RDQS4
RDQS5

RDQS7

RSRAS#
RSCAS#
RSWE#

RCS-0
RCS-1

CKE0
CKE1

DDRCLK1
DDRCLK8
DDRCLK2
DDRCLK-1
DDRCLK-8
DDRCLK-2

7

VCCM

VCC3

RMA0
RMA1
RMA2
RMA3
RMA4
RMA5
RMA6
RMA7
RMA8
RMA9
RMA10
RMA13
RMA14

RMA11
RMA12

120
148
168
184

48
43
41

130

37
32

125

29

122

27
141
118
115
103

59

52
113

97
107
119
129
149
159
169
177
140

14

25

36

56

67

78

86

47

44

45

49

51
134
135
142
144

10
101
102
173
167

154

65

63
157

158

71
163

21
111

137

16

76
138

17

75

VDD
VDD
VDD
VDDSPD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13

BA0
BA1
BA2

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8

5

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

9

NC
NC(RESET#)
NC
NC
NC
NC(FETEN)

RAS#
CAS#
WE#

S0#
S1#
NC(S2#)
NC(S3#)

CKE0
CKE1

CK0
CK1
CK2
CK0#
CK1#
CK2#

176

VDD

VSS

160

VDD

VSS

6

104

112

128

136

143

156

164

172

180738467085108

VDD

VDD

VDD

VDD

VDDQ

VSS

VSS

VSS

VSS

VSS

116

124

132

139

145

152

VDDQ

VDDQ

VSS

VSS

100

VDDQ

VDDQ

VDDQ

addr =

1010000b

VSS

VSS

VSS

VDDQ

VSS

VDDQ

VSS

VDDQ

VDDQ

VSS

VSS

VDDQ

VDDQ

VSS

VSS

VDDQ

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

VREF

VDDID

VSS

VDDQ

VDDQ

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

WP
SCL
SDA

SA0
SA1
SA2

VSS

VSS

6

DIMM1

15223054627796

VDDQ

2
4
6
8
94
95
98
99
12
13
19
20
105
106
109
110
23
24
28
31
114
117
121
123
33
35
39
40
126
127
131
133
53
55
57
60
146
147
150
151
61
64
68
69
153
155
161
162
72
73
79
80
165
166
170
171
83
84
87
88
174
175
178
179

1
82

90
92
91

181
182
183

VSS

DDR SDRAM DIMM

3111826344250586674818993

5

RMD0
RMD1
RMD2
RMD3
RMD4
RMD5
RMD6
RMD7
RMD8
RMD9
RMD10
RMD11
RMD12
RMD13
RMD14
RMD15
RMD16
RMD17
RMD18
RMD19
RMD20
RMD21
RMD22
RMD23
RMD24
RMD25
RMD26
RMD27
RMD28
RMD29
RMD30
RMD31
RMD32
RMD33
RMD34
RMD35
RMD36
RMD37
RMD38
RMD39
RMD40
RMD41
RMD42
RMD43
RMD44
RMD45
RMD46
RMD47
RMD48
RMD49
RMD50
RMD51
RMD52

RMD53

RMD54
RMD55
RMD56
RMD57
RMD58
RMD59
RMD60
RMD61
RMD62
RMD63

DDRVREF

5

WP
SMBCLK
SMBDAT

RMD[0..63]
RMA[0..14]

RDQS[0..7]

4

VCCM

VCC3

RMA0
RMA1
RMA2
RMA3
RMA4
RMA5
RMA6
RMA7
RMA8
RMA9
RMA10
RMA13
RMA14

RMA11
RMA12

RDQM0
RDQM1
RDQM2
RDQM3
RDQM4
RDQM5
RDQM6
RDQM7

RDQS0
RDQS1
RDQS2
RDQS3
RDQS4
RDQS5
RDQS6RDQS6
RDQS7

RSRAS#
RSCAS#
RSWE#

RCS-2
RCS-3

CKE2 WP
CKE3 SMBCLK

DDRCLK0
DDRCLK7
DDRCLK3
DDRCLK-0
DDRCLK-7
DDRCLK-3

4

120
148
168
184

48
43
41

130

37
32

125

29

122

27
141
118
115
103

59

52
113

97
107
119
129
149
159
169
177
140

5
14
25
36
56
67
78
86
47

44
45
49
51

134
135
142
144

9
10

101
102
173
167

154

65
63

157
158

71

163

21

111
137

16
76

138

17
75

3

VDD

VDD

VDD

VDD

VDD
VDD
VDD
VDDSPD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13

BA0
BA1
BA2

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

NC
NC(RESET#)
NC
NC
NC
NC(FETEN)

RAS#
CAS#
WE#

S0#
S1#
NC(S2#)
NC(S3#)

CKE0
CKE1

CK0
CK1
CK2
CK0#
CK1#
CK2#

VSS

VSS

VSS

VSS

145

152

160

176

3

2

DIMM2

VDDQ

VSS

VDDQ

VDDQ

VSS

VSS

VDDQ

VDDQ

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

VREF

VDDID

VSS

VSS

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

SCL

SDA

SA0
SA1
SA2

WP

15223054627796

VDDQ

VDDQ

2
4
6
8
94
95
98
99
12
13
19
20
105
106
109
110
23
24
28
31
114
117
121
123
33
35
39
40
126
127
131
133
53
55
57
60
146
147
150
151
61
64
68
69
153
155
161
162
72
73
79
80
165
166
170
171
83
84
87
88
174
175
178
179

1
82

90
92
91

181
182
183

VSS

VSS

DDR SDRAM DIMM

3111826344250586674818993

RMD0
RMD1
RMD2
RMD3
RMD4
RMD5
RMD6
RMD7
RMD8
RMD9
RMD10
RMD11
RMD12
RMD13
RMD14
RMD15
RMD16
RMD17
RMD18
RMD19
RMD20
RMD21
RMD22
RMD23
RMD24
RMD25
RMD26
RMD27
RMD28
RMD29
RMD30
RMD31
RMD32
RMD33
RMD34
RMD35
RMD36
RMD37
RMD38
RMD39
RMD40
RMD41
RMD42
RMD43
RMD44
RMD45
RMD46
RMD47
RMD48
RMD49
RMD50
RMD51
RMD52

RMD53

RMD54
RMD55
RMD56
RMD57
RMD58
RMD59
RMD60
RMD61
RMD62
RMD63

DDRVREF

SMBDAT

104

112

128

136

143

156

164

172

180738467085108

VDD

VDD

VDDQ

VDDQ

VSS

VSS

VSS

VSS

100

116

124

132

139

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

addr =

1010001b

VSS

VSS

VSS

VSS

VSS

VSS

VSS

MICRO-STAR INT'L CO.,LTD.

Title

DDR1 & DDR2

Size Document Number Rev

MS-6722 0A

B

Date: Sheet

2

1

DDRVREF 12

WP 12
SMBCLK 3,4,12,15,27,35,40
SMBDAT 3,4,12,15,27,35,40

VCC3

11 41Thursday, September 12, 2002

of

1

A

8

A

RMD[0..63]8,11,13

RMA[0..14]8,11,13

RDQM[0..7]8,11,13

RDQS[0..7]8,11,13

RMD[0..63]
RMA[0..14]
RDQM[0..7]
RDQS[0..7]

D D

C C

VCCM

R70 8.2K

B B

RSRAS#8,11,13
RSCAS#8,11,13

RSWE#8,11,13

RCS-[0..5]8,11,13

CKE[0..5]8,11

DDRCLK[0..8]4,11

DDRCLK-[0..8]4,11

8

RCS-[0..5]
CKE[0..5]
DDRCLK[0..8]
DDRCLK-[0..8]

7

VCCM

VDD

120
148
168
184

48
43
41

130

37
32

125

29

122

27
141
118
115
103

59

52
113

97
107
119
129
149
159
169
177
140

14

25

36

56

67

78

86

47

44

45

49

51
134
135
142
144

10
101
102
173
167

154

65

63
157

158

71
163

21
111

137

16

76
138

17

75

VDD
VDD
VDD
VDDSPD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13

BA0
BA1
BA2

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8

5

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

9

NC
NC(RESET#)
NC
NC
NC
NC(FETEN)

RAS#
CAS#
WE#

S0#
S1#
NC(S2#)
NC(S3#)

CKE0
CKE1

CK0
CK1
CK2
CK0#
CK1#
CK2#

176

VDD

VSS

VSS

160

VCC3

RMA0
RMA1
RMA2
RMA3
RMA4
RMA5
RMA6
RMA7
RMA8
RMA9
RMA10
RMA13
RMA14

RMA11
RMA12

RDQM0
RDQM1
RDQM2
RDQM3
RDQM4
RDQM5
RDQM6
RDQM7

RDQS0
RDQS1
RDQS2
RDQS3
RDQS4
RDQS5
RDQS6
RDQS7

RSRAS#
RSCAS#
RSWE#

RCS-4
RCS-5

CKE4 WP
CKE5 SMBCLK

DDRCLK4
DDRCLK6
DDRCLK5
DDRCLK-4
DDRCLK-6
DDRCLK-5

7

6

104

112

128

136

143

156

164

172

180738467085108

VDD

VDD

VDD

VDD

VDDQ

VSS

VSS

VSS

VSS

VSS

116

124

132

139

145

152

VDDQ

VDDQ

VSS

VSS

100

VDDQ

VDDQ

VDDQ

addr =

1010010b

VSS

VSS

VSS

VDDQ

VSS

VDDQ

VSS

VDDQ

VDDQ

VSS

VSS

VDDQ

VDDQ

VSS

VSS

VDDQ

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

VREF

VDDID

VSS

VDDQ

VDDQ

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

WP
SCL
SDA

SA0
SA1
SA2

VSS

VSS

6

DIMM3

15223054627796

VDDQ

2
4
6
8
94
95
98
99
12
13
19
20
105
106
109
110
23
24
28
31
114
117
121
123
33
35
39
40
126
127
131
133
53
55
57
60
146
147
150
151
61
64
68
69
153
155
161
162
72
73
79
80
165
166
170
171
83
84
87
88
174
175
178
179

1
82

90
92
91

181
182
183

VSS

DDR SDRAM DIMM

3111826344250586674818993

5

RMD0
RMD1
RMD2
RMD3
RMD4
RMD5
RMD6
RMD7
RMD8
RMD9
RMD10
RMD11
RMD12
RMD13
RMD14
RMD15
RMD16
RMD17
RMD18
RMD19
RMD20
RMD21
RMD22
RMD23
RMD24
RMD25
RMD26
RMD27
RMD28
RMD29
RMD30
RMD31
RMD32
RMD33
RMD34
RMD35
RMD36
RMD37
RMD38
RMD39
RMD40
RMD41
RMD42
RMD43
RMD44
RMD45
RMD46
RMD47
RMD48
RMD49
RMD50
RMD51
RMD52

RMD53

RMD54
RMD55
RMD56
RMD57
RMD58
RMD59
RMD60
RMD61
RMD62
RMD63

DDRVREF

R168 4.7K

SMBDAT

5

4

VCC3

WP 11
SMBCLK 3,4,11,15,27,35,40
SMBDAT 3,4,11,15,27,35,40

VCC3

4

R33
75ST

R32
75ST

VCCM

VCCM

CKE3
CKE2
CKE0
CKE1

CKE4
CKE5

3

RN13

1 2
3 4
5 6
7 8

470

R41 470
R40 470

DDRVREF GEN. & DECOUPLING

CB7
X_0.01u

CB5

0.01u

DIMM DECOUPLING

CB11

0.1u
CB153

X_0.1u
CB110

0.1u
CB92

X_0.1u
CB82

0.1u
CB23

X_0.1u

3

2

VCCM

CB6

0.01u

CB12

0.1u
CB140

X_0.1u
CB71

0.1u
CB93

X_0.1u
CB72

X_0.1u
CB104

X_0.1u

DDRVREF

CB4
X_0.01u

DDRVREF 11

CB152

0.1u
CB139

X_0.1u
CB109

X_0.1u
CB81

X_0.1u
CB24

X_0.1u
CB103

0.1u

MICRO-STAR INT'L CO.,LTD.

Title

DDR3

Size Document Number Rev

MS-6722 0A

B

Date: Sheet

2

1

12 41Thursday, September 12, 2002

of

1

A