Page 1
5
MS-56111-0A
SHEET01:
SHEET02:
SHEET03:
D D
SHEET04:
SHEET05:
SHEET06:
SHEET07:
SHEET08:
SHEET09:
SHEET10:
SHEET11:
SHEET12:
SHEET13:
SHEET14:
PRELIMINARY SCHEMATICS ONLY - NOT TESTED AND NOT
C C
QUALIFIED FOR MANUFACTURING
B B
A A
INDEX (This page)
BLOCK DIAGRAM
AP10_1 PROCESSOR
AP10_2 WiFi & Video & GPIO
AP10_3 POWER
AP10_4 AUDIO
FM tuner
Memory (SDRAM/Flash/Harp/EEPROM)
Bluetooth
LCD and switch
Docking
AS3517
Micro-SD and JTAG
BOOTSTRAP
5
4
REVISION HISTORY:
REV 0A : 12/8/2006 release
REV 0A-0302 : 3/2/2007 release
REV 0A-0305 : 3/5/2007 release
REV 0A-0307 : 3/7/2007 release
REV 0A-0313 : 3/13/2007 release
REV 0A-0314 : 3/14/2007 release
REV 0A-0316 : 3/16/2007 release
REV 0A-0319 : 3/19/2007 release
REV 0A-0320 : 3/20/2007 release
4
Page-3 BMM3_CMD / MM3_CMD change pin
Add SM3_CS2#, SM3_CS3#
Page-4 WLAN_AFE termination, 9.6MHz Osc. R28-33R,
C11-0.1uF
Page-5 R43 connect to VCC_3V3
Page-6 U1.E18~E20, B20~B21 floating
VDL,VDR connect to VCC_3V0
Add R69~R71
D1,D2,L13 connect to AGND_HP
R58,R59 change to 15 Ohm
Page-7 Add U20 and Y4 to provide 32k to FM chip
Page-8 Delete U6 NAND and add these signal to Harp CN
Page-9 Delete U19 chip antenna
Page-10 Add R203~R206 and Q9 to LED control
Page-12 Modify LDO5 for BT power, HC_LDO not used
Use Vsys on PMU_ONKEY power source
Page-14 Bootstrap resistor modified
Page-3 Add U3 for 32k level shift
MM3 bus re-connect to test point
Page-8 Harp interface re-connect to bus switch
Page-13 Add U8 and U9 for HSM3 bus switch
Page-13 Remove bus switch and add resistor to select
harp or u-SD
JTAG modify to 8-pin
Page-3 Add ADP_5V_SENSE to GPIO
Add to DOCK_3V_EN GPIO
Add BMM3 port to micro-SD
Add I2S bus
Page-7 Delete R75, R76
Page-11 Add R188 and R189 to provide VDD_5V sense
to CPU
Add 3.3V LDO out to docking pin-19
Page-12 Add Q4 and Q5 to control backlight power
Add D15 to limit backlight power under 15V
Change L14 to 22uH
Add U6 LDO for docking 3.3V output
Add sub-battery for backup power
Add Q7 and D19 for VDD_5V / USB5V power switch
Add I2S bus
Add TP1 and TP2 for HPOUT
Remove R185 for reset double pull high
Page-13 BMM3 bus connect to micro-SD
Page-3 Add CLK_SUS_OUT for WLAN_PLL
Page-4 Delete 9.6MHz osc. and use CLK_SUS_OUT
Page-13 Use HSM3_MUX port for Micro-SD
Page-3 Change C230 to 1uF/0603
Page-9 Add U8 chip antenna and R75 for BT power
Page-12 Change reset to Powergood pin
Add D30, change sub-batt out to RTC only
Change VCC_2V7 to VCC_VB3_TBD
Page-4 Delete TP15~TP18,TP21 and TP22
Page-5 Floating U1.E11, E13, B3
Page-9 Add R75 to reserve VCC_3V3_FIX to BT
Page-5 Floating U1.E11, E13, B3
Page-12 Add D5 for main batt to RTC power in
Add R76 for VCC_3V3_FIX
Add R15, R16 for CVDD3 1.2V 3.3V select
Delete VREF and AGND's cap.
Page-3 Delete R4 and R7
Page-6 Add FM_ANT to HP_JACK_GND
Page-9 Change R75 to VCC_3V3 power rail
Page-12 Add TP1 to VPRG1
3
3
2
2
REV 0A-0321 : 3/21/2007 release
Page-3 Delete TP7, TP61 and R10
Page-6 Delete de-pop circuit, add D6
Change C107 to 10uF/0805
REV 0A-0323 : 3/23/2007 release
Page-3 Add RTCK from PM3_PWM0 to JTAG
Page-12 Add USB IF circuit
Add R19, R20, R192
REV 0A-0326 : 3/26/2007 release
Page-9 Delete J8
Page-13 Add R185
REV 0A-0327 : 3/27/2007 release
Page-8 SDRAM Resistor pack pin / signal swap
REV 0A-0328 : 3/28/2007 release
Page-3 R6 not stuff, R12 33R->0R
Change RTCK to FM_RESET#
Page-4 R25 1.15K-->205K
Page-6 U1.D19 connect to U1.E18
Add C139 for EMI
Add C117
Page-7 R78 change to 200R
Page-8 R84, R87 pull high to VCC_HARP
Page-9 Add C140 for EMI
Page-11 Add R140 and J5.9 / J5.10 connect to
VDD_5V
Page-13 Change R185 to connect J6.5 and J6.8
Page-14 Delete R307~R309, add R332
REV 0A-0329 : 3/29/2007 release
Page-4 R25 205K-->2.05K
Page-11 Fix J5.7 short to DGND
Page-12 Delete R96~R98, Q4, Q5
REV 0A-0330 : 3/30/2007 release
Page-9 Add con5 for 50 Ohm impedance control
measurement
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
<Doc> 0A
C
<Doc> 0A
C
<Doc> 0A
C
Date: Sheet
Date: Sheet
Date: Sheet
INDEX
INDEX
INDEX
1
1
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Page 2
5
4
3
2
1
GoForce6100 SYSTEM BLOCK DIAGRAM
DEBUG
D D
12MHz
CRYSTAL
XTAL
PORT
RESET DBG
Micro-SD
CONNECTOR
HSM3_MUX
HSM3
NAND
UART
HARP
40-pin B-B
CSR BC4
Bluetooth
OR
Antenna
NAND flash
DOCKING
CONNECTOR
USB2.0
Video Out
LINE-IN
ANT.
5V
C C
POWER BUTTON
I2C
VBUS
PWGD
B B
AS3517
DC/DC
POWER SUPPLY,
&
LI-ION BATTERY
CHARGER
1.2V
1.8V
2.7V
3.0V
3.0V
3.0V
3.3V
Line-OUT
HEADPHONE
DIFFERENTIAL
MIC
AP10 CORE,PLLs
AP10,SDRAM
Audio AMP
LCD
FM
AP10 audio codec
I/O, AP10, Peripherals, BT
TFT BL
DP,DM,VBUS
VIDEO OUT
LINE-IN
LINE-OUT
MHPOUT R/L
MMICBIAS2
MMICIN2
MMICIN3_0
I2C
64Kb
EEPROM
GoForce6100
CLK_32K_IN
Si4702
FM
module
74AVC1T45
32k clock
LCD_DB[0..23]
GPIOs
CLK_SUS_OUT
WLAN_AFE_PLL
Power rail
VCC_1V2
VCC_1V8
VCC_3V3
VCC_LDO3
VCC_3V0
VCC_3V0LCD
VCC_3V3_FIX
BVDD
USB_VBUS
VDD_5V
LED+/-
GP3_PT
SDRAM
QVGA+ 2.2"
TFT LCD
6 BUTTON
SWITCHES
Wheel Encoder
1.8V
MOBILE
SDRAM
16MBX32
GND plane
PGND
DGND
AGND_A
AGND_HP
AGND_W
AGND_V
A A
32.768 KHz
CRYSTAL
5
Battery
4
3
PRELIMINARY SCHEMATICS ONLY - NOT TESTED AND NOT
QUALIFIED FOR MANUFACTURING
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet
Date: Sheet
2
Date: Sheet
Block diagram
Block diagram
Block diagram
PAGE02 : BLOCK DIAGRAM
PAGE02 : BLOCK DIAGRAM
PAGE02 : BLOCK DIAGRAM
1
[email protected]
886-2-232345599 ext 8481
886-2-232345599 ext 8481
886-2-232345599 ext 8481
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214Monday, April 02, 2007
0A
0A
0A
Page 3
5
U1-1
AA15
AB16
AA16
AA18
AA17
AC17
AC16
AB18
AC19
AA19
AB19
AC18
AB17
AA20
AA7
AA8
AC7
AC8
AA9
Y16
Y17
W19
W16
Y18
U19
R20
Y19
Y20
V19
T20
V20
U20
W20
T19
W6
Y6
W7
Y8
G4
K3
L2
E4
F4
L4
M1
H4
M4
N1
N3
N4
N2
P4
P2
P1
P3
R3
U3
R1
R4
T5
T1
T4
R2
U5
U1
V5
U4
T3
V4
W4
E3
F1
D3
E2
G2
D4
H2
G1
G3
H3
H1
J4
J3
E5
J1
F2
E6
K1
E7
D6
L3
K2
E1
D1
F3
J2
M3
K4
M2
L1
D2
C3
B1
U1-1
AP10
AP10
DTV3_XCLK
DTV3_PD0
DTV3_PD1
DTV3_PD2
DTV3_PD3
DTV3_PD4
DTV3_PD5
DTV3_PD6
DTV3_PD7
LCD3_AA0
LCD3_CS2
LCD3_RD
LCD3_RST
LCD3_RW
LCD3_DB0
LCD3_DB1
LCD3_DB2
LCD3_DB3
LCD3_DB4
LCD3_DB5
LCD3_DB6
LCD3_DB7
LCD3_DB8
LCD3_DB9
LCD3_DB10
LCD3_DB11
LCD3_DB12
LCD3_DB13
LCD3_DB14
LCD3_DB15
LCD3_DB16
LCD3_DB17
LCD3_DB18
LCD3_DB19
LCD3_DB20
LCD3_DB21
LCD3_DB22
LCD3_DB23
XM2_MD00
XM2_MD01
XM2_MD02
XM2_MD03
XM2_MD04
XM2_MD05
XM2_MD06
XM2_MD07
XM2_MD08
XM2_MD09
XM2_MD10
XM2_MD11
XM2_MD12
XM2_MD13
XM2_MD14
XM2_MD15
XM2_MD16
XM2_MD17
XM2_MD18
XM2_MD19
XM2_MD20
XM2_MD21
XM2_MD22
XM2_MD23
XM2_MD24
XM2_MD25
XM2_MD26
XM2_MD27
XM2_MD28
XM2_MD29
XM2_MD30
XM2_MD31
XM2_MA00
XM2_MA01
XM2_MA02
XM2_MA03
XM2_MA04
XM2_MA05
XM2_MA06
XM2_MA07
XM2_MA08
XM2_MA09
XM2_MA10
XM2_MA11
XM2_MA12
XM2_MA13
XM2_MA14
XM2_MA15
XM2_MA16
XM2_MA17
XM2_MA18
XM2_MA19
XM2_MA20
XM2_CKE
XM2_CS_A
XM2_CS_B
XM2_CS_C
XM2_CS_D
XM2_DQM_H
XM2_DQM_L
XM2_LDQS
XM2_UDQS
XM2_MIO_RDY
XM2_RE
XM2_WE
HSM3_MUX_CLK13
HSM3_MUX_D[0..3]13
Mux HSMMC
LCD3_XRESET10
D D
LCD3_DE10
LCD3_HSYNC10
LCD3_PCLK10
LCD3_VSYNC10
LCD3_DB[0..17]10
TFT LCD 18-BIT RGB I/F
XM2_MD[0..31]8
SDRAM DATA BUS
C C
XM2_MA[0..20]8,14
SDRAM ADDRESS BUS
B B
SDRAM CONTROL
VCC_1V8
1 2
R14
R14
10K
10K
LCD3_DB[0..17]
XM2_MD[0..31]
XM2_MA[0..20]
1 2
12
C189
C189
10pF
10pF
SDR_CKE8
TP57TP57
TP58TP58
XM2_CS_C#8
TP59TP59
XM2_DQM18
XM2_DQM08
XM2_DQM38
XM2_DQM28
HSM3_MUX_D0
HSM3_MUX_D1
HSM3_MUX_D2
HSM3_MUX_D3
R133 R133
TP64TP64
TP65TP65
TP66TP66
TP67TP67
TP68TP68
TP69TP69
TP70TP70
TP71TP71
TP72TP72
R29110R291
1 2
HSM3_MUX_CLK
LCD3_XRESET
LCD3_DE
LCD3_HSYNC
LCD3_PCLKR
LCD3_VSYNC
LCD3_DB0
LCD3_DB1
LCD3_DB2
LCD3_DB3
LCD3_DB4
LCD3_DB5
LCD3_DB6
LCD3_DB7
LCD3_DB8
LCD3_DB9
LCD3_DB10
LCD3_DB11
LCD3_DB12
LCD3_DB13
LCD3_DB14
LCD3_DB15
LCD3_DB16
LCD3_DB17
LCD3_DB18
LCD3_DB19
LCD3_DB20
LCD3_DB21
LCD3_DB22
LCD3_DB23
XM2_MD0
XM2_MD1
XM2_MD2
XM2_MD3
XM2_MD4
XM2_MD5
XM2_MD6
XM2_MD7
XM2_MD8
XM2_MD9
XM2_MD10
XM2_MD11
XM2_MD12
XM2_MD13
XM2_MD14
XM2_MD15
XM2_MD16
XM2_MD17
XM2_MD18
XM2_MD19
XM2_MD20
XM2_MD21
XM2_MD22
XM2_MD23
XM2_MD24
XM2_MD25
XM2_MD26
XM2_MD27
XM2_MD28
XM2_MD29
XM2_MD30
XM2_MD31
XM2_MA0
XM2_MA1
XM2_MA2
XM2_MA3
XM2_MA4
XM2_MA5
XM2_MA6
XM2_MA7
XM2_MA8
XM2_MA9
XM2_MA10
XM2_MA11
XM2_MA12
XM2_MA13
XM2_MA14
XM2_MA15
XM2_MA16
XM2_MA17
XM2_MA18
XM2_MA19
XM2_MA20
XM2_CKE
XM2_CS_A#
10
XM2_CS_B#
XM2_CS_C#
XM2_CS_D#
XM2_DQM1
XM2_DQM0
XM2_MIO_RDY
XM2_DQM3
XM2_DQM2
4
DTV
DTV
LCD INTERFACE
LCD INTERFACE
3
K19
CNF3_TST
DBG3_TRST
DBG3_TMS
DBG3_TDO
DBG3_TDI
DBG3_TCK
JTAG &
CONFIG
JTAG &
CONFIG
BM3_KSO_7
BM3_KSO_6
BM3_KSO_5
BM3_KSO_4
BM3_KSO_3
BM3_KSO_2
BM3_KSO_1
BM3_KSO_0
BM3_KSI_7
BM3_KSI_6
BM3_KSI_5
BM3_KSI_4
GPIOI2CI2SUSB
GPIOI2CI2SUSB
BM3_KSI_3
BM3_KSI_2
BM3_KSI_1
BM3_KSI_0
RM3_SDA
RM3_SCL
I2S_SCLK
I2S_DOUT
I2S_DIN
I2S_LRCK
SPDIF_IN
SPDIF_OUT
USB_BP
USB_BN
XTAL_12M_IN
XTAL_12M_OUT
CLK_32K_IN
CLK3_SYS_OUT
CLK3_SYS_OUT_N
CLK3_SUS_OUT
CLOCKS
CLOCKS
CLK3_DEV_OUT
AT3_HD15
AT3_HD14
AT3_HD13
AT3_HD12
AT3_HD11
AT3_HIORDY
AT3_HRESET
AT3_HIRQ0
AT3_HIRQ1
AT3_HDMARQ
AT3_HDMACK
ATAPI/EDID INTERFACE
ATAPI/EDID INTERFACE
AT3_S_HDMACK
AT3_S_HDMARQ
AT3_S_HIOR
AT3_S_HIOW
D_LCD3_RST
D_LCD3_RW
D_LCD3_RD
D_LCD3_DB7
D_LCD3_DB6
D_LCD3_DB5
D_LCD3_DB4
D_LCD3_DB3
D_LCD3_DB2
D_LCD3_DB1
D_LCD3_DB0
D_LCD3_AA0
D_LCD3_CS2
PM3_PWM1
PM3_PWM0
PWMUART D LCD
PWMUART D LCD
AT3_HD10
AT3_HD09
AT3_HD08
AT3_HD07
AT3_HD06
AT3_HD05
AT3_HD04
AT3_HD03
AT3_HD02
AT3_HD01
AT3_HD00
AT3_HA2
AT3_HA1
AT3_HA0
AT3_HIOW
AT3_HIOR
AT3_HCS0
AT3_HCS1
IR3_TXD
IR3_RXD
UA3_TXD
UA3_RXD
SDRAM, SRAM, FLASH ROM
MEMORY INTERFACE
SDRAM, SRAM, FLASH ROM
MEMORY INTERFACE
PP6110A-TFBGA441
PP6110A-TFBGA441
VBUS
REXT
RESET
DBG3_TRST
H22
DBG3_TMS
K21
DBG3_TDO
L20
DBG3_TDI
P21
DBG3_TCK
L22
Y9
W9
HSM3_MUX_CMD
Y7
MM3_D3
Y22
MM3_D2
AB21
MM3_D1
Y21
MM3_D0
W21
MM3_CLK
AC20
USB_VBUS_SENSE
U23
R22
T22
N21
J19
PMU_IRQ
T21
U22
BMM3_CMD
V21
I2C_DATA
H20
I2C_CLK
J20
K23
J21
L23
J23
J22
K22
USB_BP
AA23
USB_BN
AB23
R6
AA22
1 2
USB_RREF GND_USB_IO
W23
XTAL_12M_IN
P23
XTAL_12M_OUT
P22
CLK_32K_IN
C1
CLK_SYS_OUT
L5
M5
R120R12
AC9
M19
AB6
AC5
AB5
AC2
AB2
AC1
AA3
AB1
AB3
W1
AA4
V3
AA2
AA1
W2
Y1
T2
Y5
Y2
AC6
Y4
W3
AB4
V2
AC3
Y3
AC4
V1
U2
AC21
AC22
AB20
AC23
Y11
AB10
AC12
Y13
AC10
AA11
AA10
Y12
Y10
AB9
AB11
AA12
AC11
W17
W12
V22
R21
N19
P20
M23
1 2
HSM3_D3
HSM3_D2
HSM3_D1
HSM3_D0
SM3_D7
SM3_D6
SM3_D5
SM3_D4
SM3_D3
SM3_D2
SM3_D1
SM3_D0
PM3_PWM1
PM3_PWM0
UB3_TXD
UB3_RXD
UB3_RTS
UB3_CTS
RESET#
DBG3_TRST 13
DBG3_TMS 13
DBG3_TDO 13
DBG3_TDI 13
DBG3_TCK 13
USB_VBUS_SENSE 11
VBUS_ON 13
PHASE_1 10
PHASE_2 10
ADP_5V_SENSE 11
PMU_IRQ# 12
DOCK_3V_EN 12
TP6TP6
X_0R6X_0
USB_VBUS 11,12
R9 33R9 33
1 2
0
CLK_SUS_OUT 4
BT_PWR_EN# 9
SM3_CLE
SM3_ALE
SM3_WE#
SM3_RE#
SM3_BSY0#
HSM3_CLK
HSM3_CMD
SM3_CS0#
SM3_CS1#
PDN 10
SD_PWR_OFF# 13
HARP_PWR_OFF# 8
DOCKING_IRQ 4,5,6,8,10,11,12,13,14
DOCKING_DETECT 4,5,6,8,10,11,12,13,14
LED_ON 10
I2C_WP 8
FM3_SEN# 7
TP8TP8
FM_RESET# 8
UB3_TXD 9
UB3_RXD 9
UB3_RTS 9
UB3_CTS 9
RESET# 7,12,13
12
C230
C230
X_1U/16V/0603
X_1U/16V/0603
HSM3_MUX_CMD 13
TP11TP11
TP12TP12
TP13TP13
TP14TP14
TP20TP20
R2
10KR210K
R8
1 2
6.04K, 1%R86.04K, 1%
12
C190
C190
10pF
10pF
SM3_CS3# 8
SM3_CLE 8
SM3_ALE 8
SM3_WE# 8
SM3_RE# 8
SM3_BSY0# 8
SM3_CS2# 8
HSM3_CLK 8
HSM3_CMD 8
SM3_CS0# 8
SM3_CS1# 8
1 2
SDR_CLK 8
JTAG
Primary SDIO1 I/F(MM3)
VCC_3V3
R3
10KR310K
1 2
I2C_DATA 7,8,11,12
I2C_CLK 7,8,11,12
T1
3
4
90 OHMST190 OHMS
2
1
For the Harp
NAND control
HSMMC control
NAND control
FM
BT UART I/F
USB_DP 11
USB_DN 11
GND_USB_IO 5
HSM3_D[0..3]
SM3_D[0..7]
2
NAND bus
XTAL_12M_IN
XTAL_12M_OUT
HSM3_D[0..3] 8
HSMMC data
SM3_D[0..7] 8
CLK_32K_IN
R5
12
10MR510M
Y1
1
4
12
C1
33PFC133PF
VCC_1V8 VCC_3V3
U3
U3
A1
VCCA
VCCB
B1
GND
DIR
C1
A
SN74AVC1T45YZP
SN74AVC1T45YZP
VCC_3V3
VCC_3V3 4,5,8,9,10,11,12,13
VCC_1V8
VCC_1V8 5,8,12,14
DGND 4,5,6,8,10,11,12,13,14
B
12.00MHZY112.00MHZ
A2
B2
C2
2
3
33PFC233PF
12
C2
1
XTAL_GND 5
CLK_32K 7,12
A A
PRELIMINARY SCHEMATICS ONLY - NOT TESTED AND NOT
QUALIFIED FOR MANUFACTURING
[email protected]
886-2-232345599 ext 8481
886-2-232345599 ext 8481
886-2-232345599 ext 8481
Drawn by Phil Chen
Drawn by Phil Chen
Drawn by Phil Chen
MS-5611
MS-5611
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
AP10_1: PROCESSOR
AP10_1: PROCESSOR
AP10_1: PROCESSOR
PAGE03 : AP10_1: PROCESSOR 0A
PAGE03 : AP10_1: PROCESSOR 0A
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MS-5611
314Monday, April 02, 2007
314Monday, April 02, 2007
314Monday, April 02, 2007
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VCC_1V2
4
3
2
1
R3291KR329
LCD3_XCS10
LCD3_SCL10
LCD3_SDOUT10
NAND_WP#8
DOCK_I2C_OE11
MM3_CD#13
LCD3_SDI10
VIDEO_SENSE11
GP3_PT[0..7]
1K
WLAN_AFE_PLLIN
WLAN_AFE_VINPI
WLAN_AFE_VINNI
WLAN_AFE_VINPQ
WLAN_AFE_VINNQ
GP3_PR1
GP3_PR2
GP3_PR3
GP3_PR4
GP3_PS2
MM3_CD#
GP3_PS6
GP3_PS7
GP3_PT0
GP3_PT1
GP3_PT2
GP3_PT3
GP3_PT4
GP3_PT5
GP3_PT6
GP3_PT7
U1-2
U1-2
AP10
AP10
C13
WLAN_AFE_PLLIN
A2
WLAN_AFE_VINPI
A3
WLAN_AFE_VINNI
B4
WLAN_AFE_VINPQ
A4
WLAN_AFE_VINNQ
D8
WLAN_AFE_VAINP_0
D7
WLAN_AFE_VAINN_0
C8
WLAN_AFE_VAINP_1
C7
WLAN_AFE_VAINN_1
C5
WLAN_AFE_VREFP
C4
WLAN_AFE_VREFN
B5
WLAN_AFE_VBG
A1
WLAN_AFE_VCM
A9
WLAN_AFE_IBEXT
C9
BT_RX_ACTIVE
E9
BT_TX_ACTIVE
C18
GP3_PR0
B15
GP3_PR1
E17
GP3_PR2
C16
GP3_PR3
D17
GP3_PR4
D18
GP3_PR5
E16
GP3_PR6
A15
GP3_PR7
C17
GP3_PS0
A14
GP3_PS1
C15
GP3_PS2
D16
GP3_PS3
D15
GP3_PS4
B14
GP3_PS5
C14
GP3_PS6
B13
GP3_PS7
N22
GP3_PT0
K20
GP3_PT1
V23
GP3_PT2
U21
GP3_PT3
AB8
GP3_PT4
AA5
GP3_PT5
AA6
GP3_PT6
AB7
GP3_PT7
WLAN_LDO_CTRL_EN
WLAN_LDO_EN
WLAN_LDO_PWR_OK
WLAN_AFE_VOUTPI
WLAN_AFE_VOUTNI
WLAN_AFE_VOUTPQ
WLAN_AFE_VOUTNQ
WLAN_AFE_VOUT
WLAN_RFSPI_CLK
WLAN_RFSPI_CSB
WLAN_RFSPI_WDATA
WLAN_RF_SLEEP
WLAN_RX_ON
WLAN_HP_FILTER_ENABLE
WLAN_TX_ON
WLAN_TX_PA_ON_G
WLAN_ANT_SEL
WLAN_ANT_SEL_B
WLAN_ALP_GAIN_3
WLAN_ALP_GAIN_4
WLAN_ALP_GAIN_5
WLAN_ALP_GAIN_6
WLAN_ALP_GAIN_7
WLAN_ALP_GAIN_8
WLAN_ALP_GAIN_9
WLAN_RX_ACTIVE
WLAN_TX_ACTIVE
VDAC_IOUTP0
VDAC_IOUTN0
VDAC_IOUTP1
VDAC_IOUTN1
VDAC_IOUTP2
VDAC_IOUTN2
VDAC_IREF
VDAC_VDREF
B8
A10
B12
A7
A6
B7
C6
A8
D10
D9
C11
E8
D11
B10
E10
B11
D14
A13
C12
A12
D12
E14
D13
E15
A11
B9
C10
AC15
AA14
AC13
AB14
AC14
AA13
AB12
AB13
12
D D
CLK_SUS_OUT3
VCC_1V2
VCC_1V2 5,12
C C
B B
VCC_3V3
VCC_1V8
AGND_V
VCC_3V3 3,5,8,9,10,11,12,13
VCC_1V8 3,5,8,12,14
DGND 3,5,6,8,10,11,12,13,14
AGND_V 5,11,12
LCD SPI I/F
Key buttons GPIO
GP3_PT[0..7]10
R290R29
1 2
VDAC0
VDAC1
VDAC2
AGND_V
C8
1UF/6.3VC91UF/6.3V
0.1UFC80.1UF
1 2
AGND_V AGND_V
VCC_3V3
0
R181 0R181 0
1 2
R180 0R180 0
1 2
R24
R24
R23
R23
R182
1 2
AGND_V
75, 1%
75, 1%
R182
75, 1%
75, 1%
R61 0R61 0
1 2
1 2
R49 0R49 0
1 2
12
C9
R25
R25
2.05K, 1%
2.05K, 1%
75, 1%
75, 1%
1 2
1 2
C88 22PFC88 22PF
R88 0R88 0
1 2
1 2
C240 22PFC240 22PF
R50 0R50 0
1 2
1 2
C95 22PFC95 22PF
OPTION
1 2
C235 33PFC235 33PF
L23
L23
1 2
2.7UH
2.7UH
LQM21NN2R7K10 COMPOSITE
12
C233
C233
560PF
560PF
AGND_V AGND_V AGND_V
C239 33PFC239 33PF
1 2
LQM21NN2R7K10
12
C237
C237
560PF
560PF
AGND_V
C236 33PFC236 33PF
1 2
LQM21NN2R7K10
12
C231
C231
560PF
560PF
AGND_V AGND_V AGND_V
OPTION
1 2
2.7UH
2.7UH
OPTION
1 2
2.7UH
2.7UH
L24
L24
L22
L22
12
D17
D17
C234
C234
BAT54S
BAT54S
560PF
560PF
12
D18
D18
C238
C238
BAT54S
BAT54S
560PF
560PF
AGND_V AGND_V
12
D16
D16
C232
C232
BAT54S
BAT54S
560PF
560PF
VCC_3V3
Y_OUT
C_OUT
CVBS_OUT 11
Y_OUT 11
C_OUT 11
3
1
2
VCC_3V3
3
1
2
VCC_3V3
3
1
2
A A
5
4
3
PRELIMINARY SCHEMATICS ONLY - NOT TESTED AND NOT
QUALIFIED FOR MANUFACTURING
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet
Date: Sheet
2
Date: Sheet
AP10_2: WiFi & Video
AP10_2: WiFi & Video
AP10_2: WiFi & Video
PAGE04 : AP10_2: WiFi & Video 0A
PAGE04 : AP10_2: WiFi & Video 0A
PAGE04 : AP10_2: WiFi & Video 0A
1
[email protected]
886-2-232345599 ext 8481
886-2-232345599 ext 8481
886-2-232345599 ext 8481
Drawn by Phil Chen
Drawn by Phil Chen
Drawn by Phil Chen
MS-5611
MS-5611
MS-5611
414Monday, April 02, 2007
414Monday, April 02, 2007
414Monday, April 02, 2007
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VCC_3V3
D D
VCC_3V3
VCC_3V3
VCC_3V3
C C
VCC_3V3
VCC_3V3
VCC_3V3
B B
VCC_3V3
VCC_1V8
R300R30
1 2
0
R320R32
1 2
0
R350R35
1 2
0
R360R36
1 2
0
R380R38
1 2
0
R410R41
1 2
0
R420R42
1 2
0
R430R43
1 2
0
R440R44
1 2
0
VDD_IO
VDD_IO_DBG
VDD_IO_I2S
VDD_IO_DTV
VDD_IO_AT
VDD_IO_DLCD
VDD_IO_WLAN
VDD_IO_MEM
12
C14
C14
0.1UF
0.1UF
12
C19
C19
0.1UF
0.1UF
12
C25
C25
0.1UF
0.1UF
12
C31
C31
0.1UF
0.1UF
12
C36
C36
0.1UF
0.1UF
12
C42
C42
0.1UF
0.1UF
12
C43
C43
0.1UF
0.1UF
12
C68
C68
0.1UF
0.1UF
12
C69
C69
0.1UF
0.1UF
GND_USB_IO3
12
C26
C26
0.1UF
0.1UF
12
12
C37
C37
C38
C38
0.1UF
0.1UF
0.1UF
0.1UF
VCC_1V2
12
C44
C44
0.1UF
0.1UF
12
C45
C45
0.1UF
0.1UF
12
12
12
C70
C70
C71
C71
C72
0.1UF
0.1UF
C72
0.1UF
0.1UF
0.1UF
0.1UF
VCC_1V2
L10L1
1 2
0
VCC_3V3
L40L4
1 2
0
VCC_3V3
L20L2
1 2
0
VCC_3V3
L30L3
1 2
0
VCC_1V2
L50L5
1 2
0
VCC_1V2
L60L6
1 2
0
12
12
12
12
C46
C46
C48
C48
C49
C49
C47
C47
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
12
C73
C73
0.1UF
0.1UF
12
12
12
C52
C52
C50
C50
C51
C51
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
VCC_3V3
12
C75
C75
0.1UF
0.1UF
12
AGND_V
C76
C76
0.1UF
0.1UF
12
C77
C77
0.1UF
0.1UF
R34 0R34 0
1 2
12
R31 0R31 0
1 2
R33 0R33 0
1 2
R37 0R37 0
1 2
R39 0R39 0
1 2
R40 0R40 0
1 2
12
C78
C78
C79
C79
0.1UF
0.1UF
0.1UF
0.1UF
12
12
12
12
12
12
12
12
12
C15
C15
1UF/6.3V
1UF/6.3V
C16
C16
1UF/6.3V
1UF/6.3V
C20
C20
1UF/6.3V
1UF/6.3V
C24
C24
1UF/6.3V
1UF/6.3V
C27
C27
1UF/6.3V
1UF/6.3V
C29
C29
1UF/6.3V
1UF/6.3V
C32
C32
1UF/6.3V
1UF/6.3V
C34
C34
1UF/6.3V
1UF/6.3V
C40
C40
1UF/6.3V
1UF/6.3V
12
C13
C13
0.1UF
0.1UF
12
C17
C17
0.1UF
0.1UF
12
12
C22
C22
C21
C21
0.1UF
0.1UF
0.1UF
0.1UF
12
C18
C18
0.1UF
0.1UF
12
C28
C28
0.1UF
0.1UF
12
C30
C30
0.1UF
0.1UF
12
C33
C33
0.1UF
0.1UF
12
C35
C35
0.1UF
0.1UF
12
C41
C41
0.1UF
0.1UF
12
C23
C23
0.1UF
0.1UF
VDD_USB
GND_USB
VCC_3VA
GND_USB_IO
VDAC_AVDD
GND_VDAC_GNDA
WLAN_AFE_AVDD33
WLAN_AFE_AVDD
WLAN_AFE_AVDD
VCC_1V2PA
GND_PA
VCC_1V2PC
GND_PC
VCC_1V2PP
GND_PP
VDD_IO_WLAN
VDD_IO_MEM
VDD_IO_ATVDD_IO_LCD
VDD_IO_DBG
VDD_IO_DLCD
VDD_IO_DTV
VDD_IO_I2S
VDD_IO_LCD
VDD_IO
U1-3
U1-3
AP10
AP10
W22
USB_VDDP
Y23
USB_VSSP
AB22
USB_VDDA
AA21
USB_VSSA
AB15
VDAC_AVDD1
W15
VDAC_AVDD2
Y14
VDAC_AVDD3
Y15
VDAC_AGND2
W14
VDAC_AGND1
A5
WLAN_AFE_AVDD33
B2
WLAN_AFE_AVDD
C2
WLAN_AFE_AGND2
B3
WLAN_AFE_AGND1
D5
WLAN_AFE_VDREF
B6
WLAN_AFE_AGNDREF
E12
VDD_IO_WLAN
M20
PLLA_VDD
L21
PLLA_VSS
M21
PLLC_VDD
N20
PLLC_VSS
M22
PLLP_VDD
N23
PLLP_VSS
R5
VDD_IO_MEM1
F5
VDD_IO_MEM2
G5
VDD_IO_MEM3
H5
VDD_IO_MEM4
J5
VDD_IO_MEM5
P5
VDD_IO_MEM6
W5
VDD_IO_AT
P19
VDD_IO_DBG
W10
VDD_IO_DLCD
W8
VDD_IO_DTV
H19
VDD_IO_I2S
W18
VDD_IO_LCD
R19
VDD_IO
H11
VDD_CORE1
H12
VDD_CORE2
H13
VDD_CORE3
L8
VDD_CORE4
L16
VDD_CORE5
M8
VDD_CORE6
M16
VDD_CORE7
N8
VDD_CORE8
N16
VDD_CORE9
T11
VDD_CORE10
T12
VDD_CORE11
T13
VDD_CORE12
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
GND65
GND66
GND67
GND68
GND69
GND70
GND71
GND72
GND73
GND74
GND75
GND76
XTAL_12M_VDD
XTAL_12M_VSS
XTAL_GND3
VCC_3V3
VCC_1V8
VCC_1V2
AGND_V
XTAL12M_VDD
VCC_3V3 3,4,8,9,10,11,12,13
VCC_1V8 3,8,12,14
VCC_1V2 4,12
DGND 3,4,6,8,10,11,12,13,14
AGND_V 4,11,12
VCC_1V2
L90L9
0
1 2
12
C67
C67
0.1UF
0.1UF
L100L10
1 2
0
E11
E13
H8
H9
H16
H15
H14
H10
J8
J9
J10
J11
J12
J13
J14
J15
J16
K5
K8
K9
K10
K11
K12
K13
K14
K15
K16
L9
L10
L11
L12
L13
L14
L15
L19
M9
M10
M11
M12
M13
M14
M15
N5
N9
N10
N11
N12
N13
N14
N15
R8
R9
R10
R11
R12
R13
R14
R15
R16
T8
T9
T10
T14
T15
T16
P16
P15
P14
P13
P12
P11
P10
P9
P8
W11
W13
T23
R23
A A
PRELIMINARY SCHEMATICS ONLY - NOT TESTED AND NOT
QUALIFIED FOR MANUFACTURING
[email protected]
886-2-232345599 ext 8481
886-2-232345599 ext 8481
886-2-232345599 ext 8481
Drawn by Phil Chen
Drawn by Phil Chen
Drawn by Phil Chen
MS-5611
MS-5611
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
AP10_3: POWER
AP10_3: POWER
AP10_3: POWER
PAGE05 : AP10_3: POWER 0A
PAGE05 : AP10_3: POWER 0A
PAGE05 : AP10_3: POWER 0A
MS-5611
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514Monday, April 02, 2007
514Monday, April 02, 2007
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514Monday, April 02, 2007
Page 6
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R46 1.1K, 1%R46 1.1K, 1%
XMIC1BIAS
1 2
X2
X2
HIT_4mm_Microphone
HIT_4mm_Microphone
D D
C C
B B
A A
MICP
2
MICN
1
AVDD AVDD
R3301KR330
1K
12
C101
C101
1UF/6.3V
1UF/6.3V
AGND_A
12
12
R54
R54
1.1K, 1%
1.1K, 1%
AGND_A
R3311KR331
1K
12
C102
C102
1UF/6.3V
1UF/6.3V
Docking line-in
FM audio in
1 2
C89 1UF/6.3VC89 1UF/6.3V
C90
C90
47PF
47PF
1 2
C93 1UF/6.3VC93 1UF/6.3V
12
C103
C103
1UF/6.3V
1UF/6.3V
12
LIN1_L11
LIN1_R11
LIN2_L7
LIN2_R7
5
C104
C104
1UF/6.3V
1UF/6.3V
12
C91
C91
47PF
47PF
AGND_A
12
C86
C86
0.1UF
0.1UF
AGND_A
PLACE NEAR CHIP
12
C107
C107
10UF/6.3V
10UF/6.3V
12
C108
C108
4.7UF/6.3V
4.7UF/6.3V
AGND_HP
LIN1_L
LIN2_L
LIN2_R
R47 0R47 0
1 2
12
C109
C109
4.7UF/6.3V
4.7UF/6.3V
MIC2_IN
MIC3_IN
TP29TP29
4.7UF/6.3V
4.7UF/6.3V
4.7UF/6.3V
4.7UF/6.3V
12
C119
C119
47PF
47PF
12
C123
C123
47PF
47PF
12
C125
C125
47PF
47PF
12
C132
C132
47PF
47PF
(P)
(N)
C110
C110
C117
C117
1
12
12
MICBIAS2
MLIN1L
MLIN1R
MLIN2L
MLIN2R
MIC1_IN
MICBIAS2
MIC2_IN
MIC3_IN
MVREFAL
MVREFAR
MVREFDL
MVREFDR
MREFCOM
MHP25P
MHP50P
MHP75P
AGND_A
AGND_A
AGND_A
AGND_A
12
C118 1UF/6.3VC118 1UF/6.3V
R66
R66
5.6K, 5%
5.6K, 5%
OPTION
12
C120 1UF/6.3VC120 1UF/6.3V
R67
R67
5.6K, 5%
5.6K, 5%
OPTION
12
R68
R68
5.6K, 5%
5.6K, 5%
OPTION
12
R72
R72
5.6K, 5%
5.6K, 5%
OPTION
1 2
1 2
1 2
1UF/6.3V
1UF/6.3V
1 2
1UF/6.3V
1UF/6.3V
C124
C124
C131
C131
G23
D22
E22
G22
C22
B21
B23
G21
C23
H23
F22
E21
D23
D21
B22
D20
C20
C19
D19
E18
E20
B20
U1-4
U1-4
AP10
AP10
MICDET
MLIN1L
MLIN1R
MLIN2L
MLIN2R
MMICBIAS1
MMICIN1
MMICBIAS2
MMICIN2
MICIN3
MVREFAL
MVREFAR
MVREFDL
MVREFDR
MVREFCOM
MHP25P
MHP25PHPA
MHP50P
MHP75P
MHP75PHPA
MCFPOS
MCFNEG
F21
AGND_HP AGND_A
MLIN1L
MLIN1RLIN1_R
MLIN2L
MLIN2R
R48
C85 1UF/6.3VC85 1UF/6.3V
1 2
C92
MLOUTL
MLOUTR
MHPOUTL
MHPOUTR
MHPCOM
MHPSENS
DOUTNL
DOUTPL
DOUTNR
DOUTPR
MLOUTL
F23
MLOUTR LOUT_R
E23
HPOUT_L
A20
HPOUT_R
A21
E19
C21
A18
A19
A16
A17
C92
1 2
1UF/6.3V
1UF/6.3V
VDDCP
VDDCP
A22
DVDDCP
DGNDCP
A23
DGNDCP
MW_AVDD
HPGND
MW_AGND
F19
DVDD
HPVDD
AVDD
G19
DVDD
G20
HPVDD
F20
B19
VDL
B18
VSL
B17
VDR
B16
VSR
DGND
H21
AVDD
HPVDD
C100
C100
C99
C99
10UF/6.3V
10UF/6.3V
0.1UF
0.1UF
DVDD
12
12
C111
C111
C112
C112
0.1UF
0.1UF
1UF/6.3V
1UF/6.3V
DGND
AVDD
12
12
C115
C115
C114
C114
1UF/6.3V
1UF/6.3V
0.1UF
0.1UF
HPVDD
12
C121
C121
0.1UF
0.1UF
C139
C139
1 2
0.1UF
0.1UF
AGND_A
12
12
Reservd for EMI
4
LOUT_L
12
12
FB10FB1
1 2
FB20FB2
1 2
C116
C116
10UF/6.3V
10UF/6.3V
OPTION
C122
C122
10UF/6.3V
10UF/6.3V
12
0
0
R48
100, 5%
100, 5%
1 2
R51
R51
47K
47K
AGND_A
VCC_3V0
R57 0R57 0
1 2
VCC_3V0
FB30FB3
1 2
0
AGND_A
FB40FB4
1 2
0
12
VCC_3V0
VCC_3V0
AGND_HP
C87
C87
47PF
47PF
HPH_L 11
Line-output to dockingOPTION
R52
R52
100, 5%
100, 5%
12
HPOUT_R
HPOUT_L
12
12
R58
R58
R59
R59
15, 1%
15, 1%
15, 1%
15, 1%
12
12
C105
C105
C106
C106
0.22UF
0.22UF
0.22UF
0.22UF
PLACE CLOSE TO CHIP
AGND_HP
R60 0R60 0
1 2
AGND_HPAGND_A
R69 0R69 0
1 2
R70 0R70 0
1 2
R71 0R71 0
1 2
1 2
R53
R53
47K
47K
AGND_A
AGND_HPAGND_A
AGND_HPAGND_A
AGND_HPAGND_A
C97
C97
220UF/4V
220UF/4V
VCC_3V0
12
C94
C94
47PF
47PF
OPTION
220UF/4V
220UF/4V
HPH_R 11
C98
C98
MLVS0402M04-220
MLVS0402M04-220
VCC_3V0 12
HP_COUT_R
HP_COUT_L
D1
D1
2 1
MLVS0402M04-220
MLVS0402M04-220
AGND_A
AGND_HP AGND_HPAGND_HP
D2
D2
2 1
X_MLVS0402M04-220
X_MLVS0402M04-220
L11
L11
1 2
2.2uH
2.2uH
D6
D6
2 1
AGND_A 7,11,12
DGND 3,4,5,8,10,11,12,13,14
PRELIMINARY SCHEMATICS ONLY - NOT TESTED AND NOT
QUALIFIED FOR MANUFACTURING
3
2
L12
L12
1 2
2.2uH
2.2uH
L13
L13
2.2uH
2.2uH
1 2
J1 PJK-631MJ1 PJK-631M
2
HP_JACK_R
3
HP_JACK_L
HP_JACK_GND
1
5
647
FM_ANT 7,11
[email protected]
886-2-232345599 ext 8481
886-2-232345599 ext 8481
886-2-232345599 ext 8481
Drawn by Phil Chen
Drawn by Phil Chen
Drawn by Phil Chen
MS-5611
MS-5611
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
AP10_4: Audio
AP10_4: Audio
AP10_4: Audio
PAGE06 : AP10_4: Audio 0A
PAGE06 : AP10_4: Audio 0A
PAGE06 : AP10_4: Audio 0A
MS-5611
614Monday, April 02, 2007
614Monday, April 02, 2007
614Monday, April 02, 2007
of
of
1
of
Page 7
5
D D
4
3
2
1
12
C137
C137
0.1UF
0.1UF
VCC_LDO3
FM_LOUT
FM_ROUT
C135
C135
12
C136
C136
0.022uF
0.022uF
AGND_A
R78 200R78 200
1 2
R79 200R79 200
1 2
R80 200R80 200
1 2
R81
R81
1 2
200
200
C134 0.1UFC134 0.1UF
12
0.1UF
0.1UF
VCC_LDO3
12
R74
R74
47K
47K
12
LIN2_L 6
LIN2_R 6
AGND_A
FM_RESET# 3,12,13
FM3_SEN# 3
I2C_CLK 3,8,11,12
I2C_DATA 3,8,11,12
C138
C138
0.01UF
0.01UF
1 2
VCC_1V2
VCC_1V2 4,5,12
VCC_LDO3
VCC_LDO3 12
DGND 3,4,5,6,8,10,11,12,13,14
AGND_A 6,11,12
19
21
NC1
FMIP
RFGND
GND1
20
NC2
PLANE
RST5SEN6SCLK7SDIO8RCLK9VIO
10
GPIO317GPIO218GPIO1
GND3
LOUT
ROUT
GND2
VA
VD
16
15
14
13
12
11
VCC_LDO3
AGND_A
U4
C133
C133
FM_ANT6,11
C C
B B
100pF
100pF
12
AGND_A
CLK_32K3,12
1
2
3
4
SI4702U4SI4702
AGND_A
[email protected]
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886-2-232345599 ext 8481
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
FM Tuner
FM Tuner
FM Tuner
PAGE07 : FM Tuner 0A
PAGE07 : FM Tuner 0A
PAGE07 : FM Tuner 0A
886-2-232345599 ext 8481
Drawn by Phil Chen
Drawn by Phil Chen
Drawn by Phil Chen
MS-5611
MS-5611
MS-5611
714Monday, April 02, 2007
714Monday, April 02, 2007
714Monday, April 02, 2007
of
of
1
of
Page 8
5
D D
SDR_CLK3
RN1310RN13
SDR_CKE3
12
34
56
78
RN1010RN10
10
RN1210RN12
12
10pF
10pF
C245
C245
RN910RN9
12
34
56
RN1110RN11
78
10
12
34
56
78
10
12
10pF
10pF
XM2_MA[0..20]3,14
XM2_CS_C#3
XM2_DQM13
C C
XM2_DQM23
XM2_DQM33
XM2_DQM03
XM2_MA[0..20]
XM2_DQM2
XM2_MA15
XM2_MA11
XM2_MA14 SDR_MA14
XM2_CS_C#
XM2_DQM1
XM2_MA9
XM2_MA8
XM2_MA7
XM2_MA12
XM2_MA4
XM2_MA5
XM2_DQM3
XM2_MA0
XM2_MA10
XM2_MA1
XM2_MA17
XM2_MA16
XM2_MA13
XM2_DQM0
XM2_MA3
XM2_MA6
C244
C244
12
34
56
78
10
RN1410RN14
4
12
34
56
78
10
12
34
56
78
10
SDR_MA15
SDR_MA16
SDR_MA17
12
C243
C243
10pF
10pF
SDR_MA15
SDR_MA11
SDR_CS_C#
SDR_DQM1
SDR_MA12
SDR_MA4
SDR_MA5
SDR_DQM3
SDR_MA0
SDR_MA10
SDR_MA1
SDR_MA2XM2_MA2
SDR_MA17
SDR_MA16
SDR_MA13
SDR_DQM0
SDR_MA3
SDR_MA6
SDR_CLK
SDR_CKE
SDR_MA14
SDR_MA13
SDR_MA12
SDR_MA11
SDR_MA10
SDR_MA9
SDR_MA8
SDR_MA7
SDR_MA6
SDR_MA5
SDR_MA4
SDR_MA3
SDR_MA2
SDR_MA1
SDR_MA0
SDR_CS_C#
SDR_MA15
SDR_MA16
SDR_MA17
SDR_DQM3
SDR_DQM2
SDR_DQM1
SDR_DQM0
VCC_1V8
U5
U5
R7
VDD1A7VDD2F9VDD3L7VDD4
J1
CLK
J2
CKE
H8
BA1
J7
BA0
H3
A12/NC
H9
A11/NC
G7
A10/AP
J3
A9
H2
A8
H1
A7
G3
A6
HY5S7B2LF
A5
A4
A3
A2
A1
A0
CS
RAS
CAS
WE
DQM3
DQM2
DQM1
DQM0
NC1
NC2
NC3
NC4
NC5
HY5S7B2LF
G2
G1
F3
F7
G9
G8
J8
J9
K7
K8
F2
F8
K1
K9
E3
E7
H7
K2
K3
VSS1A3VSS2F1VSS3L3VSS4R3VSSQ1B3VSSQ2B8VSSQ3C1VSSQ4D1VSSQ5E9VSSQ6L9VSSQ7M1VSSQ8N1VSSQ9P3VSSQ10
3
VDDQ1B2VDDQ2B7VDDQ3C9VDDQ4D9VDDQ5E1VDDQ6L1VDDQ7M9VDDQ8N9VDDQ9
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
2
P7
P2
VDDQ10
E2
D3
D2
B1
C2
A1
C3
A2
A8
C7
A9
C8
B9
D8
D7
E8
R2
N3
R1
N2
P1
M2
M3
L2
L8
M7
M8
P9
N8
R9
N7
R8
SDR_MD31
SDR_MD30
SDR_MD29
SDR_MD28
SDR_MD27
SDR_MD26
SDR_MD25
SDR_MD24
SDR_MD23
SDR_MD22
SDR_MD21
SDR_MD20
SDR_MD19
SDR_MD18
SDR_MD17
SDR_MD16
SDR_MD15
SDR_MD14
SDR_MD13
SDR_MD12
SDR_MD11
SDR_MD10
SDR_MD9
SDR_MD8
SDR_MD7
SDR_MD6
SDR_MD5
SDR_MD4
SDR_MD3
SDR_MD2
SDR_MD1
SDR_MD0
SDR_MD28
SDR_MD30
SDR_MD31
SDR_MD25
SDR_MD24
SDR_MD26
SDR_MD27
SDR_MD19
SDR_MD21
SDR_MD23
SDR_MD22
SDR_MD11
SDR_MD15
SDR_MD8
SDR_MD12
SDR_MD3
SDR_MD5
SDR_MD6
SDR_MD7
SDR_MD2
SDR_MD0
SDR_MD4
RN110RN1
RN310RN3
RN510RN5
RN710RN7
XM2_MD28
12
XM2_MD30
34
XM2_MD29
56
XM2_MD31
RN210RN2
78
10
12
34
56
RN410RN4
78
10
12
34
56
RN610RN6
78
10
12
34
56
RN810RN8
78
10
12
34
56
78
10
12
34
56
78
XM2_MD11
10
XM2_MD14
XM2_MD13
XM2_MD15
12
34
56
78
XM2_MD3
10
XM2_MD5
XM2_MD6
XM2_MD7
12
34
56
78
10
XM2_MD25
XM2_MD24
XM2_MD26
XM2_MD27
XM2_MD19
XM2_MD21
XM2_MD23
XM2_MD20
XM2_MD22
XM2_MD18
XM2_MD17
XM2_MD16
XM2_MD8
XM2_MD10
XM2_MD9
XM2_MD12
XM2_MD2
XM2_MD0
XM2_MD1
XM2_MD4
XM2_MD[0..31]
1
XM2_MD[0..31] 3
P8
VCC
SCL
SDA
VCC_3V3
VCC_1V8
8
7
WP
6
5
VCC_3V3 3,4,5,9,10,11,12,13
VCC_1V8 3,5,12,14
DGND 3,4,5,6,10,11,12,13,14
VCC_3V3
C144
C144
0.1UF
0.1UF
I2C_WP
VCC_3V3
R94
R94
100K, 5%
100K, 5%
1 2
[email protected]
886-2-232345599 ext 8481
886-2-232345599 ext 8481
886-2-232345599 ext 8481
Drawn by Phil Chen
Drawn by Phil Chen
Drawn by Phil Chen
MS-5611
MS-5611
MS-5611
814Monday, April 02, 2007
814Monday, April 02, 2007
814Monday, April 02, 2007
1
I2C_WP 3
of
of
of
12
I2C_CLK 3,7,11,12
I2C_DATA 3,7,11,12
MEMORY
MEMORY
MEMORY
PAGE08 : MEMORY 0A
PAGE08 : MEMORY 0A
PAGE08 : MEMORY 0A
HARP_PWR_OFF#3
VCC_3V3
B B
HSM3_D[0..3]3
VCC_1V8
A A
12
C146
C146
0.1UF
0.1UF
12
C147
C147
0.1UF
0.1UF
12
C148
C148
0.1UF
0.1UF
12
C226
C226
10UF/6.3V
10UF/6.3V
HSM3_D[0..3]
12
C149
C149
0.1UF
0.1UF
100K, 5%
100K, 5%
12
C150
C150
0.1UF
0.1UF
5
R65
R65
C227
C227
0.1UF
0.1UF
12
C151
C151
0.1UF
0.1UF
12
U17
U17
HSM3_CLK3
HSM3_CMD3
12
C152
C152
0.1UF
0.1UF
12
C153
C153
0.1UF
0.1UF
4
ON/OFF
5
IN
AAT4250_SOT23-5
AAT4250_SOT23-5
R178
R178
HSM3_CLK
HSM3_D2
HSM3_D0
HSM3_D1
HSM3_D3
HSM3_CMD
12
C154
C154
0.1UF
0.1UF
X_0
X_0
12
C155
C155
0.1UF
0.1UF
GND
OUT
3
NC
2
1
SM3_D[0..7]3
R95 0R95 0
12
C156
C156
0.1UF
0.1UF
12
C157
C157
0.1UF
0.1UF
12
12
C158
C158
0.1UF
0.1UF
C159
C159
0.1UF
0.1UF
VCC_HARP
12
12
12
R91 10KR91 10K
R92 10KR92 10K
12
R93 10KR93 10K
SM3_D7
SM3_D6
SM3_D5
SM3_D3
SM3_D1
SM3_D0
SM3_D4
SM3_D2
J11
J11
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
40-pin header
40-pin header
12
R90 10KR90 10K
R89 10KR89 10K
12
C145
C145
1 2
22PF
22PF
12
21
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
PRELIMINARY SCHEMATICS ONLY - NOT TESTED AND NOT
QUALIFIED FOR MANUFACTURING
4
C142
C142
0.1UF
0.1UF
VCC_HARP
3
12
C143
C143
X_4.7UF
X_4.7UF
VCC_HARP
R84
R84
100K, 5%
100K, 5%
1 2
SM3_BSY0# 3
SM3_WE# 3
SM3_CLE 3
SM3_CS3# 3
SM3_CS2# 3
R87
R87
100K, 5%
100K, 5%
SM3_CS1# 3
NAND_WP# 4
SM3_CS0# 3
SM3_RE# 3
SM3_ALE 3
NAND flash move to memory daughter board
1 2
2
U7
U7
1
A0
2
A1
3
A2
4
GND
24LC64IMS
24LC64IMS
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
Page 9
5
D D
4
3
2
C140
C140
1 2
0.1UF
AGND_W
0.1UF
1
Reservd for EMI
VCC_3V3
R750R75
0
R316
R316
1 2
Q6
G
4
4
1
3
2
2
J4
VSS_ANAI
Q6
D S
P-IRLML6402TR_SOT23
P-IRLML6402TR_SOT23
AGND_W
C262
C262
3
4.7PF
4.7PF
1 2
AGND_WAGND_W
AGND_W
K5
21
R3270R327
0
J3
XTAL_OUT
PCM_SYNC
PCM_IN
PCM_OUT
PCM_CLK
SPI_CLK
SPI_MISO
SPI_MOSI
SPI_CSB
USB_DP
USB_DN
UART_RX
UART_TX
UART_CTS
UART_RTS
RESETB
TEST_EN
VDD_PRGG3VREG_EN
3V3
100K, 5%
BT_PWR_EN#3
U8
U8
2
112
CAN4311153002451K-RH
CAN4311153002451K-RH
C C
B B
BT_RF
A A
5
C249
C249
10pF (DNI)
10pF (DNI)
L26
L26
1.2nH (DNI)
1.2nH (DNI)
AGND_W AGND_W
BT_RFRF0
L27
L27
1.2nH (DNI)
1.2nH (DNI)
50 ohm
AGND_W
6
U23
U23
1
GND2
UNBAL
2
DC
1V8
12
L28
L28
0.022UH
0.022UH
C264
C264
2.7PF
2.7PF
1 2
AGND_W AGND_W
BAL1
BAL2
GND1
3
DEA252450BT
DEA252450BT
AGND_W
4
CON5
CON5
TEST_RES
TEST_RES
For 50 Ohm impedance test
4
5
1
1
2
2
1V8
12
C254
C254
R321
R321
2.2
2.2
C259
C259
C258
C258
0.01UF
0.01UF
1 2
1 2
AGND_WAGND_W
VDD_ANA
VSS_ANA3
VSS_ANA2
J1
F3
K2
1 2
AGND_W
2.2UF
2.2UF
E10
K9
VDD_USB
VDD_CORE
VSS_CORE
VSS_ANA4K1VSS_ANA1J2VSS_ANA5
VSS_USB1
J9
E9
H2
AGND_WAGND_WAGND_WAGND_WAGND_WAGND_W
C255
C255
15pF
15pF
D1
F1
E1
D3
G1
G2
1 2
AGND_W
U24
U24
BC04
BC04
1V8 1V8
C256
C256
H1
RF_IN
TX_A
TX_B
AUX_DAC
VSS_VCO1
VSS_VCO2
3V3
1V8 3V3
C263
C263
C257
C257
0.01UF
0.01UF
0.01UF
0.01UF
0.01UF
1 2
C1
C2
VDD_VCO
VDD_RADIO1
VDD_RADIO2
VSS_RADIO1
E2
D2
0.01UF
1 2
1 2
AGND_WAGND_WAGND_W
D10
A3
K4
VDD_PIO
VDD_PADS
VSS_PADSD9VSS_SUB
VSS_RADIO3F2VSS_RADIO2
VSS_PIO2
VSS_PIO1
A2
A1
3
100K, 5%
3V3
Y3
16MHzY316MHz
2.2UF
2.2UF
C260
C260
1
3.3PF
3.3PF
1 2
K6
K3
XTAL_IN
VREG_IN
VSS_USB2
K10
PIO11
PIO10
RESET
VCC_3V3_FIX
DGND 3,4,5,8,10,11,12,13
R325
R325
10K
10K
1V8
12
VCC_3V3
VCC_3V3 3,4,5,8,10,11,12,13
VCC_3V3_FIX
VCC_3V3_FIX 12
AGND_W 12
AGND_W
3V3
C261
C261
12
0.01UF
12
12
R322
R322
R323
R323
R324
R324
2.2K
2.2K
2.2K
2.2K
2.2K
2.2K
WP
SCL
SDA
UB3_TXD 3
UB3_RXD 3
UB3_RTS 3
UB3_CTS 3
12
R326
R326
10K
10K
AGND_W
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet of
0.01UF
12
AGND_W
U22
U22
8
A0
VCC
7
A1
WP
6
A2
SCL
5
GND
SDA
AT24C16A
AT24C16A
3V3
J9
J9
1
1
2
2
3
3
4
4
5
5
6
6
7
7
X_7-pin header
X_7-pin header
AGND_W
Bluetooth and antenna
Bluetooth and antenna
Bluetooth and antenna
PAGE09 : Bluetooth 0A
PAGE09 : Bluetooth 0A
PAGE09 : Bluetooth 0A
1
1
2
3
4
AGND_W
[email protected]
886-2-232345599 ext 8481
886-2-232345599 ext 8481
886-2-232345599 ext 8481
Drawn by Phil Chen
Drawn by Phil Chen
Drawn by Phil Chen
MS-5611
MS-5611
MS-5611
914Monday, April 02, 2007
914Monday, April 02, 2007
914Monday, April 02, 2007
of
of
3V3
E3
C4
C3
PIO9
C5
PIO8
PIO7
PIO6
PIO5
PIO4
PIO3
PIO2
PIO1
PIO0
AIO2
AIO1
AIO0
2
SDA
F9
SCL
F10
F8
E8
B4
B3
B2
B1
G10
G9
G8
H10
SPI_CLK
C10
SPI_DOUT
B9
SPI_DIN
C8
BT_SPI_CS#
C9
J8
K8
H9
J10
H8
H7
C7
D8
C6
J5
H5
H4
AGND_W
C265
C265
0.01UF
0.01UF
1 2
AGND_W
Page 10
5
VCC_3V0LCDVCC_3V3VCC_3V3
C191
C191
12
0.1UF
12
12
R124
R124
10K
D D
LCD3_XRESET3
LCD3_SDOUT4
LCD3_SDI4
LCD3_SCL4
LCD3_XCS4
LCD3_VSYNC3
LCD3_HSYNC3
LCD3_PCLK3
LCD3_DE3
LCD3_DB[0..17]3
C C
B B
10K
C193
C193
1 2
X_10PF
X_10PF
VCC_3V0LCD BVDD
0.1UF
12
R125
R125
R126
R126
10K
10K
100K, 5%
100K, 5%
LCD3_DB17
LCD3_DB16
LCD3_DB15
LCD3_DB14
LCD3_DB13
LCD3_DB12
LCD3_DB11
LCD3_DB10
LCD3_DB9
LCD3_DB8
LCD3_DB7
LCD3_DB6
LCD3_DB5
LCD3_DB4
LCD3_DB3
LCD3_DB2
LCD3_DB1
LCD3_DB0
LED-12
LED+12
L190L19
0
VCC_3V0LCD 12
12
12
C194
C194
0.1UF
0.1UF
12
C192
C192
0.1UF
0.1UF
12
VCC_3V3
L180L18
0
4
R127
R127
100K, 5%
100K, 5%
1 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
BVDD 6,12
GP3_PT[0..7]4
J4
NC1
RESETB
SDO
SDI
SCL
CSB
GND1
VSYNC
HSYNC
DOTCLK
ENABLE
GND2
RIN5
RIN4
RIN3
RIN2
RIN1
RIN0
GND3
GIN5
GIN4
GIN3
GIN2
GIN1
GIN0
GND4
BIN5
BIN4
BIN3
BIN2
BIN1
BIN0
GND5
IOVCC
VDD
AGND
VCI
LEDÂLED+
NC2
LCDJ4LCD
NP1
NP2
NC3
NC4
GP3_PT[0..7]
GP3_PT0
GP3_PT1
GP3_PT4
GP3_PT2
GP3_PT3
GP3_PT6
GP3_PT5
GP3_PT7
LCM1
LCM1
Foxlink FL039-A0 240*320 2.2" TFT
Foxlink FL039-A0 240*320 2.2" TFT
3
VCC_3V3
12
R11
R11
100K, 5%
100K, 5%
SW3SW3
1 2
21
D27D27
12
12
R123
R123
R121
R121
100K, 5%
100K, 5%
100K, 5%
100K, 5%
D22D22
21
21
D9D9
21
R1200R120
1 2
0
MENU / Power OFF
RECORD
12
R122
R122
100K, 5%
100K, 5%
D23D23
21
12
D24D24
3 4
R135
R135
100K, 5%
100K, 5%
21
D25D25
12
12
R134
R134
100K, 5%
100K, 5%
21
D26D26
PHASE_13
PMU_ONKEY 12
R1361MR136
1M
GPIO VIH 1.32v~3.6v
PMU_ONKEY High range 2.3v~3.2v
PMU_ONKEY is low active
2
SW SLIDE-SPDT
SW SLIDE-SPDT
5 6
7
PHASE_23
R2233R22
LED_ON3
SW4
SW4
GP3_PT4
GP3_PT2
GP3_PT3
GP3_PT6
GP3_PT5
PDN3
1 2
33
C246
C246
0.01UF
0.01UF
VCC_3V3
4
13 2
HOLD
12
C247
C247
0.01UF
0.01UF
R11333R113
1 2
12
12
R137
R137
100K, 5%
100K, 5%
33
21
D20D20
R203
R203
47, 5%
47, 5%
1
VCC_3V3VCC_3V3
C248
C248
0.1UF
0.1UF
21
D21D21
J7
J7
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
R205
R205
R204
R204
47, 5%
47, 5%
47, 5%
47, 5%
1 2
1 2
1 2
D
Q9
G
S
1. Vcc1
1. Vcc1
2. B out
2. B out
3. S1
3. S1
4. S2
4. S2
5. S5
5. S5
6. COM
6. COM
7. S4
7. S4
8. S3
8. S3
9. PDN
9. PDN
10. GND
10. GND
11. A out
11. A out
12. LED_VCC
12. LED_VCC
13. LED1
13. LED1
14. LED2
14. LED2
15. LED3
15. LED3
16. LED4
16. LED4
CONN-FPC16U_WHITE-RH
CONN-FPC16U_WHITE-RH
R206
R206
47, 5%
47, 5%
1 2
AO3414Q9AO3414
P1
NUTP1NUT
B5V-1422-D01-L04 switch
B5V-1422-D01-L04 switch
1
SW11
SW11
1
1
P2
NUTP2NUT
2
2
345
345
1
VCC_3V3
VCC_3V3 3,4,5,8,9,11,12,13
A A
5
DGND 3,4,5,6,8,11,12,13,14
PRELIMINARY SCHEMATICS ONLY - NOT TESTED AND NOT
QUALIFIED FOR MANUFACTURING
4
3
[email protected]
886-2-232345599 ext 8481
886-2-232345599 ext 8481
886-2-232345599 ext 8481
Drawn by Phil Chen
Drawn by Phil Chen
Drawn by Phil Chen
MS-5611
MS-5611
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet
Date: Sheet
2
Date: Sheet
LCD and switch
LCD and switch
LCD and switch
PAGE10 : LCD
PAGE10 : LCD
PAGE10 : LCD
MS-5611
1
0A
0A
0A
10 14Monday, April 02, 2007
10 14Monday, April 02, 2007
10 14Monday, April 02, 2007
of
of
of
Page 11
5
J5
J5
Docking-connect
Docking-connect
34
ANTENNA
323234
D D
C C
B B
A A
AGND3
AUDIO_OUT_L
AUDIO_OUT_R
AGND2
AUDIO_IN_L
AUDIO_IN_R
AGND1
I2C_CLK
I2C_DATA
GND3
+3.3Vdc
VAGND2
S-Video C or Pr
S-Video Y or Pb
Sense/VAGND
CVBS_OUT or Y
VAGND1
CVBS_IN
VAGND/Sense
VDD3
VDD2
DOCKING_DETECT
GND2
USB_D-
USB_D+
GND1
VDD1
Vbus
313133
33
CON1
CON1
1
1
2
2
TEST_RES
TEST_RES
CON3
CON3
1
1
2
2
TEST_RES
TEST_RES
5
IRQ
D13
D13
SMF6.0A
SMF6.0A
LAYER2 GND
R1280R128
30
29
28
27
26
25
24
23
DOCK_I2C_CLK
22
DOCK_I2C_DAT
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
EGA10402V05AH
EGA10402V05AH
A C
AGND_V
LAYER2 GND
For impedance test
12
0
R1400 R1400
1 2
D14
D14
DOCK_I2C_OE4
VCC_3V3
R1290R129
12
0
R132 0R132 0
R133 0R133 0
C_OUT 4
Y_OUT 4
VIDEO_SENSE 4
CVBS_OUT 4
1 2
PGB1010603MR
PGB1010603MR
2 1
12
C57
C57
+
+
10UF/10V
10UF/10V
C_TAJA
C_TAJA
DOCK_I2C_OE
CON2
CON2
1
1
2
2
TEST_RES
TEST_RES
CON4
CON4
1
1
2
2
TEST_RES
TEST_RES
FM_ANT 6,7
12
12
+3V3DC 12
R1380 R1380
D11
D11
PGB1010603MR
PGB1010603MR
2 1
I2C_CLK3,7,8,12
E1
E1
Rubber_Jack
Rubber_Jack
E4
SPONGEE4SPONGE
4
DOCKING_IRQ 3
D12
D12
2 1
DOCK_I2C_CLK
4
C197
C197
X_10PF
X_10PF
1 2
USB_DN 3
USB_DP 3
R177
R177
100K, 5%
100K, 5%
R176
R176
200K
200K
1 2
U15
U15
2
1A
3
1B
1
1OE
7
2OE
SN74CB3T3306DCUR
SN74CB3T3306DCUR
E2
E2
Rubber_Micro SD
Rubber_Micro SD
E5
E5
Rubber_Rec
Rubber_Rec
3
R130 0R130 0
12
HPH_L 6
12
FM3
FM3
BADMARK
BADMARK
PAD4
PAD4
Screw
Screw
PAD5
PAD5
Screw
Screw
HPH_R 6
1
1
FM4
FM4
BADMARK
BADMARK
DOCKING_DETECT 3,4,5,6,8,10,12,13,14
R139
R139
100K, 5%
100K, 5%
1 2
FM1
FM1
X_FIDUCIAL
X_FIDUCIAL
F_PAD_M120
F_PAD_M120
FM5
FM5
X_FIDUCIAL
X_FIDUCIAL
F_PAD_M120
F_PAD_M120
FM7
FM7
X_FIDUCIAL
X_FIDUCIAL
F_PAD_M120
F_PAD_M120
FM9
FM9
X_FIDUCIAL
X_FIDUCIAL
F_PAD_M120
F_PAD_M120
LIN1_L 6
LIN1_R 6
C198
C198
X_10PF
X_10PF
1 2
USB_VBUS 3,12
USB_VBUS_SENSE 3
8
VCC
5
2A
6
2B
4
GND
E3
E3
Rubber_Hold
Rubber_Hold
E6
E6
Mylar_Sub battery
Mylar_Sub battery
C195
C195
X_10PF
X_10PF
VCC_3V3
12
DOCK_I2C_DAT
C199
C199
0.1UF
0.1UF
12
R131 0R131 0
12
C196
C196
X_10PF
X_10PF
DOCKING_DETECT
VDD_5V 12
R188
R188
100K, 5%
100K, 5%
ADP_5V_SENSE 3
R189
R189
200K
200K
1 2
I2C_DATA 3,7,8,12
PAD1
PAD1
1
Screw
Screw
PAD2
PAD2
1
Screw
Screw
PCB corner screw hole
PRELIMINARY SCHEMATICS ONLY - NOT TESTED AND NOT
QUALIFIED FOR MANUFACTURING
3
2
2
FM2
FM2
X_FIDUCIAL
X_FIDUCIAL
F_PAD_M120
F_PAD_M120
FM6
FM6
X_FIDUCIAL
X_FIDUCIAL
F_PAD_M120
F_PAD_M120
FM8
FM8
X_FIDUCIAL
X_FIDUCIAL
F_PAD_M120
F_PAD_M120
FM10
FM10
X_FIDUCIAL
X_FIDUCIAL
F_PAD_M120
F_PAD_M120
1
AGND_V 4,5,12
AGND_V
AGND_A 6,7,12
VCC_3V3
VCC_3V3 3,4,5,8,9,10,12,13
PCB1
PCB1
DGND 3,4,5,6,8,10,12,13,14
PCB542*50
PCB542*50
[email protected]
886-2-232345599 ext 8481
886-2-232345599 ext 8481
886-2-232345599 ext 8481
Drawn by Phil Chen
Drawn by Phil Chen
Drawn by Phil Chen
MS-5611
MS-5611
1
MS-5611
11 14Monday, April 02, 2007
11 14Monday, April 02, 2007
11 14Monday, April 02, 2007
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
DOCKING
DOCKING
DOCKING
PAGE11 : DOCKING 0A
PAGE11 : DOCKING 0A
PAGE11 : DOCKING 0A
Page 12
5
D30
D30
X_RB551
X_RB551
A C
BVDD
J12
J12
4
1T1T2
2
6
3
5
BAT-3PS-RH
BAT-3PS-RH
D D
VBUS_VDD_5V
R45
R45
10K
10K
VDD_5V11
R318
C C
USB_VBUS3,11
PMU_IRQ#3
B B
R318
4.7K
4.7K
RESET#3,7,13
PMU_ONKEY10
Q2
IRLML6402Q2IRLML6402
D
BATTEMP
R108
R108
X_0
X_0
1 2
U19
U19
1
OUT
2
GND
3
12
SET
AAT4610AIGV-T1_SOT23-5-RH
AAT4610AIGV-T1_SOT23-5-RH
Q7
IRLML6402Q7IRLML6402
D
S
G
VCC_3V3
R186
R186
100K, 5%
100K, 5%
1 2
VSYS
X_ESD-MLVS0402M04
X_ESD-MLVS0402M04
S
G
R17
R17
300
300
R18
R18
5.1K
5.1K
IN
ON
R193
R193
100K, 5%
100K, 5%
R319
R319
470K
470K
D19
D19
A C
S-RB161M-20
S-RB161M-20
R77
R77
100K, 5%
100K, 5%
1 2
SW12SW12
1 2
VSYS
D29
D29
S-RB161M-20
S-RB161M-20
A C
For USB IF
5
4
12
I2C_CLK3,7,8,11
I2C_DATA3,7,8,11
VCC_3V3
CLK_32K3,7
21
D28
D28
RB521D3RB521
BAT1
BAT1
sub-battery
sub-battery
C39
C39
0.1UF
0.1UF
1 2
VBUS_ON 2
CHG_IN
VCC_LDO3
12
C60
C60
0.1UF
0.1UF
VCC_3V3
R191
R191
X_100K, 5%
X_100K, 5%
1 2
TP1TP1
R190
R190
150K
150K
1 2
12
R187
R187
100K, 5%
100K, 5%
1 2
R183
R183
200K
200K
1 2
D3
12
C217
C217
33PF
33PF
C59
C59
2.2UF
2.2UF
BVDDR
A C
BVDD
R2891KR289
1K
A C
RB521D5RB521
D4
RB521D4RB521
G1
J2
G3
H3
F6
G4
F4
G5
H4
J3
J4
F3
H5
J5
J7
J8
G6
H6
J6
AS3517
AS3517
D5
VCC_3V3
AC
U25
U25
DVDD
DVSS
CSCL
CSDA
PWGD
LRCLK
SCLK
SDO
SDI
Q32K
Q24M
HBT
XIRQ
XRES
XIN24
XOUT24
VPRG1
VPRG2
PWRUP
4
BVDDR
Interface
Interface
Interface
Interface
Interface
Interface
Sequence
Sequence
Y4
32.768KHzY432.768KHz
I2C
I2C
I2S
I2S
OSCDigital
OSCDigital
Startup
Startup
12
J1
XOUT32
12
C130
C58
C58
1uF
1uF
E9
C130
2.2UF
2.2UF
BVDDR
BATTEMP
G2
F2
H1
RTC Charger
RTC Charger
E2
XIN32
RVDD
BVDDR
BATTEMP
BVDD
E1
MIC1BG8MIC1PG9MIC1NH9MIC2BE8MIC2PF9MIC2N
CHG_IN
F1
CHG_IN
CHG_OUT
VCC_3V0LCD
12
C128
C128
2.2UF
2.2UF
D8
R76
R76
X_0
X_0
12
VSYS
D1
Programmable
Programmable
LDOs USB
LDOs USB
AS3517
AS3517
CTBGA81
CTBGA81
Line OutMicrophone
Line OutMicrophone
LOUT1R
LOUT1L
LOUT2R
LOUT2L
E7
C6
C7
3
VSYS
12
12
C74
C82
C82
0.1UF
0.1UF
DOCK_3V_EN3
VCC_3V3_FIX
12
C129
C129
2.2UF
2.2UF
C4
C5
C1
BVDD2D3BVDD1E3PVDD1D2PVDD2
CN_GEXT
USBH_PG
Line In
Line In
LIN1RD6LIN1L
LIN2RF7LIN2L
F8
D7
C74
1UF/6.3V
1UF/6.3V
R192
R192
100K, 5%
100K, 5%
CHG_IN
D4
C2
C3
VBUS
CP_CP
USBH_CSP
USBH_CSN
Headphone
Headphone
D9
12
E6
Not
Not
Connected
Connected
HPLA9VSSHB9HPRC9BVDDHB8HPCMC8HPGND
U6
U6
1
VIN
3
CE
NC4E5NC3F5NC2E4NC1
NC
D5
DCDC 15V
DCDC 15V
DCDC CVDD1DCDC CVDD2
DCDC CVDD1DCDC CVDD2
DCDC CVDD3
DCDC CVDD3
Analog
Analog
5
VOUT
4
NC
VSS
XC6204B332MR_SOT23-5-RH
XC6204B332MR_SOT23-5-RH
2
H2
FVDD
B1
ISINK
B2
VSS15
A1
SW15
B7
CVDD1
A6
CVSS1
A7
LXC1
A8
BVDDC1
B5
CVDD2
B6
CVSS2
A5
LXC2
A4
BVDDC2
B3
CVDD3
A2
CVSS3
A3
LXC3
B4
BVDDC3
H7
AVDD
H8
VREF
G7
AGND
Supply
Supply
J9
AVSS
12
C83
C83
1UF/6.3V
1UF/6.3V
12
C127
C127
0.1UF
0.1UF
L14
L14
22uH
22uH
L21 4.7uHL21 4.7uH
L20 4.7uHL20 4.7uH
L25 4.7uHL25 4.7uH
R1840R184
2
+3V3DC 11
VCC_LDO3
12
C126
C126
2.2UF
2.2UF
12
0
VCC_LDO3
VCC_1V2
R200 R200
1 2
R19X_0 R19X_0
12
VSYS
RB551V-30-S
RB551V-30-S
C268
C268
10uF/10V/0805
10uF/10V/0805
VCC_1V8
C267
C267
10uF/10V/0805
10uF/10V/0805
C266
C266
10uF/10V/0805
10uF/10V/0805
DGND 3,4,5,6,8,10,11,13,14
VCC_LDO3 7
VCC_3V3
D10
D10
A C
12
C96
C96
4.7UF/6.3V
4.7UF/6.3V
12
C66
C66
4.7UF/6.3V
4.7UF/6.3V
12
C65
C65
4.7UF/6.3V
4.7UF/6.3V
C64
C64
0.1UF
0.1UF
AC
D15
D15
BZT52C15
BZT52C15
12
C113
C113
1U/16V/0603
1U/16V/0603
R150 R150
1 2
VCC_3V0
12
BVDD
VCC_3V3
VCC_1V8
VCC_1V2
VCC_3V3_FIX
VCC_3V0
VCC_3V0LCD
LED- 10
VCC_3V3
R16X_0 R16X_0
12
12
C63
C63
2.2UF
2.2UF
1
BVDD 6
VCC_3V3 3,4,5,8,9,10,11,13
VCC_1V8 3,5,8,14
VCC_1V2 4,5
VCC_3V3_FIX 9
VCC_3V0 6
VCC_3V0LCD 10
LED+ 10
VCC_1V2
A A
R1520R152
12
AGND_W 9
0
5
4
3
R1540R154
R1560R156
12
0
12
0
2
AGND_V 4,5,11
AGND_A 6,7,11
[email protected]
886-2-232345599 ext 8481
886-2-232345599 ext 8481
886-2-232345599 ext 8481
Drawn by Phil Chen
Drawn by Phil Chen
Drawn by Phil Chen
MS-5611
MS-5611
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
Power Management Unit
Power Management Unit
Power Management Unit
PAGE12 : AS3517
PAGE12 : AS3517
PAGE12 : AS3517
MS-5611
of
of
of
12 14Monday, April 02, 2007
12 14Monday, April 02, 2007
1
12 14Monday, April 02, 2007
0A
0A
0A
Page 13
5
4
3
2
1
SD_PWR_OFF#3
D D
C C
VCC_3V3
12
C229
C229
10UF/6.3V
10UF/6.3V
HSM3_MUX_D[0..3]3
R73
R73
100K, 5%
100K, 5%
C228
C228
0.1UF
0.1UF
12
U18
U18
4
ON/OFF
5
IN
AAT4250_SOT23-5
AAT4250_SOT23-5
HSM3_MUX_CMD3
HSM3_MUX_CLK3
R179
R179
X_0
X_0
3
NC
2
GND
1
OUT
HSM3_MUX_D2
HSM3_MUX_D3
HSM3_MUX_D0
HSM3_MUX_D1
MM3_CD#4
R162
R162
10K
10K
VCC_3V_SD
C218
C218
12
X_4.7UF
X_4.7UF
12
12
R161
R161
R159
C223
C223
X_10PF
X_10PF
1 2
R159
10K
10K
C224
C224
X_10PF
X_10PF
1 2
C225
C225
X_10PF
X_10PF
1 2
10K
10K
12
R160
R160
10K
10K
R16833R168
33
12
R163
R163
10K
10K
12
C220
C220
X_10PF
X_10PF
12
1 2
MM3_CD#
12
R164
R164
10K
10K
R1650R165
0
12
R1670R167
0
R1660R166
0
12
12
R1690R169
12
0
R1700R170
12
0
C221
C221
C222
C222
X_10PF
X_10PF
X_10PF
X_10PF
1 2
C219
C219
12
0.1UF
0.1UF
CONN1
CONN1
11
MICRO-SD-CONNECT
MICRO-SD-CONNECT
11
12
12
CARD DETECT6
13
DAT2
DUMMY1
CD/DAT3
CMD
VDD
CLK
VSS
DAT0
DUMMY2
DAT1
15
15
14
14
1
2
3
4
5
6
7
8
9
10
1 2
B B
PRELIMINARY SCHEMATICS ONLY - NOT TESTED AND NOT
QUALIFIED FOR MANUFACTURING
VCC_3V3
VCC_3V3
10K
10K
DBG3_TRST
DBG3_TDI
DBG3_TMS
DBG3_TCK
DBG3_TDO
H1X8#_BLACK-2.6MM-RH
H1X8#_BLACK-2.6MM-RH
VCC_3V3
VCC_3V3 3,4,5,8,9,10,11,12
J6
J6
1
2
3
4
5
6
7
8
9
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet
Date: Sheet
2
Date: Sheet
DGND 3,4,5,6,8,10,11,12,14
[email protected]
886-2-232345599 ext 8481
886-2-232345599 ext 8481
886-2-232345599 ext 8481
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MS-5611
MS-5611
MS-5611
Micro-SD and JTAG
Micro-SD and JTAG
Micro-SD and JTAG
PAGE13 : Micro-SD and JTAG 0A
PAGE13 : Micro-SD and JTAG 0A
PAGE13 : Micro-SD and JTAG 0A
13 14Monday, April 02, 2007
13 14Monday, April 02, 2007
13 14Monday, April 02, 2007
of
of
1
of
R174
R174
R175
R172
R172
R173
R171
R171
10K
10K
1 2
DBG3_TRST3
DBG3_TDI3
DBG3_TMS3
DBG3_TCK3
DBG3_TDO3
A A
RESET#3,7,12
R185 10KR185 10K
R173
10K
10K
10K
10K
1 2
1 2
12
R175
10K
10K
1 2
1 2
JTAG port
5
4
3
Page 14
5
SECURE LEVEL (HARDWARE SELECT)
ADDRESS
A17
0
1
IMAGE UPDATE (HARDWARE SELECT)
ADDRESS
A16
0
D D
C C
B B
A A
1
JTAG (FIRMWARE SELECT)
ADDRESS
A15
0
1
BOOT VECTOR LOCATION (FIRMWARE SELECT)
ADDRESS DESCRIPTION
A14 A13
0 0
0 1
1 0
1 1
JTAG CONFIG (HARDWARE SELECT)
ADDRESS DESCRIPTION
A12 A11
0 0
0 1
1 0
1 1
FIRMWARE BOOT SOURCE PARAMETERS (FIRMWARE SELECT)
A10 A9 A8 A7
X 0 0 1
X 0 1 0 CE-ATA
X 0 1 1
X 1 0 0
X 1 0 1 SPI FLASH BOOT XM2
X 1 1 X
MIO TYPE (FIRMWARE SELECT)
ADDRESS
A6
0
1
MIO BUS WIDTH (FIRMWARE SELECT)
ADDRESS
A5
0
1
USB RECOVERY
ADDRESS
A4
0
1
SDR RAM BUS WIDTH (FIRMWARE SELECT)
ADDRESS
A3
0
1
UART BAUD RATE (HARDWARE SELECT)
ADDRESS
A2
0
1
ROMTYPE (FIRMWARE SELECT)
ADDRESS
A1
0
1
FLASH MEMORY BUS WIDTH (HARDWARE SELECT)
A0(0:16b, 1:8b)
DESCRIPTION
0: INSECURE BOOTING
1: SECURE BOOTONG
DESCRIPTION
0: NO UPDATE FIRMWARE IMAGE
1: UPDATE FIRMWARE IMAGE
DESCRIPTION
0: ENABLE JATG (DEFAULT)
1: DISABLE JTAG
00 = EXT ROM0 (0000:0000)
01 = EXT ROM1(0800:0000)
10 = INTERNAL UART BOOT LOADER
11 = INTERNAL BOOT ROM
00 = Serial (CPU->COP) (DEFAULT)
01 = CPU only (CPU)
10 = COP only (COP)
11 = Parallel (CPU||COP)
ADDRESS
ADDRESS
DESCRIPTION
NAND FLASH
I2C EEPROM
SPI FLASH BOOT AT-S
RESERVED
DESCRIPTION
DESCRIPTION
0 = 16 BIT
1 = 32 BIT (DEFAULT)
DESCRIPTION
0 = ENABLE
1 = DISABLE (DEFAULT)
DESCRIPTION
0 = 16 BIT
1 = 32 BIT (DEFAULT)
DESCRIPTION
0 = 56K BAUD (DEFAULT)
1 = 750K BAUD
DESCRIPTION
0 = ?
1 = NOR FLASH
DESCRIPTION
5
DEFAULT
0FLASH BUS WIDTH
Press to enter
USB recovery
mode
VCC_1V8
VCC_1V8
VCC_1V8
VCC_1V8
VCC_1V8
VCC_1V8
SW10
SW10
EVQPQHB55
EVQPQHB55
VCC_1V8
VCC_1V8
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R310
R310
1 2
1 2
1 2
1 2
R292
R292
R294
R294
R332
R332
R297
R297
R298
R298
R299
R299
R300
R300
R301
R301
R302
R302
R303
R303
R304
R304
R305
R305
R293
R293
option
R312
R312
R313
R313
R314
R314
R315
R315
4
R306
R306
100K, 5%
100K, 5%
R311
R311
1 2
4
100K, 5%
100K, 5%
100K, 5%
100K, 5%
X_100K, 5%
X_100K, 5%
100K, 5%
100K, 5%
100K, 5%
100K, 5%
100K, 5%
100K, 5%
100K, 5%
100K, 5%
100K, 5%
100K, 5%
100K, 5%
100K, 5%
100K, 5%
100K, 5%
100K, 5%
100K, 5%
X_100K, 5%
X_100K, 5%
100K, 5%
100K, 5%
X_100K, 5%
X_100K, 5%
100K, 5%
100K, 5%
100K, 5%
100K, 5%
100K, 5%
100K, 5%
100K, 5%
100K, 5%
100K, 5%
100K, 5%
XM2_MA17
XM2_MA16
XM2_MA15
XM2_MA14
XM2_MA13
XM2_MA12
XM2_MA11
XM2_MA10
XM2_MA9
XM2_MA8
XM2_MA7
XM2_MA4
XM2_MA3
XM2_MA2
XM2_MA1
XM2_MA0
XM2_MA[0..20]
3
3
XM2_MA[0..20] 3,8
2
VCC_1V8
VCC_1V8 3,5,8,12
DGND 3,4,5,6,8,10,11,12,13
1
PRELIMINARY SCHEMATICS ONLY - NOT TESTED AND NOT
QUALIFIED FOR MANUFACTURING
[email protected]
886-2-232345599 ext 8481
886-2-232345599 ext 8481
886-2-232345599 ext 8481
Drawn by Phil Chen
Drawn by Phil Chen
Drawn by Phil Chen
MS-5611
MS-5611
1
MS-5611
14 14Monday, April 02, 2007
14 14Monday, April 02, 2007
14 14Monday, April 02, 2007
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
BOOTSTRAP
BOOTSTRAP
BOOTSTRAP
PAGE14 : BOOTSTRAP 0A
PAGE14 : BOOTSTRAP 0A
PAGE14 : BOOTSTRAP 0A
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