Page 1
1
8
8
8
(1) PCI-EXPRESS EDGE CONNECTOR
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
A A
+3.3V_BUS
G_SMBCLK
5,17
IN
G_SMBDAT
5,17
BI
C
C
C
B B
C C
PLACE THESE CAPS AS CLOSE TO
PCIE CONN ECTOR AS POSSIBLE
+12V_BUS
C110
C111
10uF
0.15uF
16V
16V
+3.3V_BUS
C113
C114
10uF
0.1uF
6.3V
6.3V
C112
0.15uF
16V
C115
C116
1uF
0.01uF
6.3V
10V
R103
45.3K
1%
DNI DNI
+3.3V_BUS
2
Q100B
R104
45.3K
1%
+3.3V_BUS
2N7002DW
61
R105 0R 5%
R106 0R 5%
34
Q100A
2N7002DW
5
DNI
DNI
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
2
OUT
+3.3V_BUS +12V_BUS +12V_BUS +3.3V_BUS
MPCIE1
Mechanical Key
x16 PCIe
SMBCLK
SMBDAT
PETP0_GFXRP0
PETN0_GFXRN0
PETP1_GFXRP1
PETN1_GFXRN1
PETP2_GFXRP2
PETN2_GFXRN2
PETP3_GFXRP3
PETN3_GFXRN3
PETP4_GFXRP4
PETN4_GFXRN4
PETP5_GFXRP5
PETN5_GFXRN5
PETP6_GFXRP6
PETN6_GFXRN6
PETP7_GFXRP7
PETN7_GFXRN7
PETP8_GFXRP8
PETN8_GFXRN8
PETP9_GFXRP9
PETN9_GFXRN9
PETP10_GFXRP10
PETN10_GFXRN10
PETP11_GFXRP11
PETN11_GFXRN11
PETP12_GFXRP12
PETN12_GFXRN12
PETP13_GFXRP13
PETN13_GFXRN13
PETP14_GFXRP14
PETN14_GFXRN14
PETP15_GFXRP15
PETN15_GFXRN15
PRESENCE
B1
+12V
B2
+12V
B3
+12V
B4
GND
B5
SMCLK
B6
SMDAT
B7
GND
B8
+3.3V
B9
JTAG1
B10
3.3Vaux
B11
WAKE_
B12
RSVD_B12
B13
GND
B14
PETp0
B15
PETn0
B16
GND
B17
PRSNT2_B17
B18
GND
B19
PETp1
B20
PETn1
B21
GND
B22
GND
B23
PETp2
B24
PETn2
B25
GND
B26
GND
B27
PETp3
B28
PETn3
B29
GND
B30
RSVD_B30
B31
PRSNT2_B31
B32
GND
B33
PETp4
B34
PETn4
B35
GND
B36
GND
B37
PETp5
B38
PETn5
B39
GND
B40
GND
B41
PETp6
B42
PETn6
B43
GND
B44
GND
B45
PETp7
B46
PETn7
B47
GND
B48
PRSNT2_B48
B49
GND
B50
PETp8
B51
PETn8
B52
GND
B53
GND
B54
PETp9
B55
PETn9
B56
GND
B57
GND
B58
PETp10
B59
PETn10
B60
GND
B61
GND
B62
PETp11
B63
PETn11
B64
GND
B65
GND
B66
PETp12
B67
PETn12
B68
GND
B69
GND
B70
PETp13
B71
PETn13
B72
GND
B73
GND
B74
PETp14
B75
PETn14
B76
GND
B77
GND
B78
PETp15
B79
PETn15
B80
GND
B81
PRSNT2_B81
B82
RSVD_B82
PRSNT1_A1
PERST_
REFCLK+
REFCLK-
RSVD_A19
RSVD_A32
RSVD_A33
RSVD_A50
PERp10
PERn10
PERp11
PERn11
PERp12
PERn12
PERp13
PERn13
PERp14
PERn14
PERp15
PERn15
A1
A2
+12V
A3
+12V
A4
GND
A5
JTAG2
A6
JTAG3
A7
JTAG4
A8
JTAG5
A9
+3.3V
A10
+3.3V
A11
A12
GND
A13
A14
A15
GND
A16
PERp0
A17
PERn0
A18
GND
A19
A20
GND
A21
PERp1
A22
PERn1
A23
GND
A24
GND
A25
PERp2
A26
PERn2
A27
GND
A28
GND
A29
PERp3
A30
PERn3
A31
GND
A32
A33
A34
GND
A35
PERp4
A36
PERn4
A37
GND
A38
GND
A39
PERp5
A40
PERn5
A41
GND
A42
GND
A43
PERp6
A44
PERn6
A45
GND
A46
GND
A47
PERp7
A48
PERn7
A49
GND
A50
A51
GND
A52
PERp8
A53
PERn8
A54
GND
A55
GND
A56
PERp9
A57
PERn9
A58
GND
A59
GND
A60
A61
A62
GND
A63
GND
A64
A65
A66
GND
A67
GND
A68
A69
A70
GND
A71
GND
A72
A73
A74
GND
A75
GND
A76
A77
A78
GND
A79
GND
A80
A81
A82
GND
PRESENCE
JTDIO_LOOP
PCIE_REFCLKP
PCIE_REFCLKN
PERP0
PERN0
PERP1
PERN1
PERP2
PERN2
PERP3
PERN3
PERP4
PERN4
PERP5
PERN5
PERP6
PERN6
PERP7
PERN7
PERP8
PERN8
PERP9
PERN9
PERP10
PERN10
PERP11
PERN11
PERP12
PERN12
PERP13
PERN13
PERP14
PERN14
PERP15
PERN15
15,14
2
OUT
2
OUT
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
2
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
2
2
2
2
2
2
2
2
2
2
2
2
2
2
+3.3V_BUS
R101 10K 5%
DNI
C101 0.1uF 6.3V
DNI
1.8V_EN
PERSTB
R102 0R 5%
+3.3V_BUS
IN
RST_EN
C100
0.1uF
6.3V
U100B
3 5
NC7SZ08P5X
U100A
1
2
NC7SZ08P5X
R100 1K 5%
PLACE R100 I N U100
4
PERSTB_BUF
DNI
2,11,16
OUT
SYMBOL LEGEND
DNI
DO NOT
INSTALL
b or #
ACTIVE
LOW
BUO
BRING UP
ONLY
DIGITAL
GROUND
ANALOG
GROUND
DD
DD
DD
C
C
C
BB
BB
BB
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
1.0
1.0
1.0
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
C
C
C
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
information incl uded herein.
information incl uded herein.
information incl uded herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
A
A
A
1
1
1
8
4
4
4
5
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
PCI-EXPRESS EDGE CONNECTOR
PCI-EXPRESS EDGE CONNECTOR
PCI-EXPRESS EDGE CONNECTOR
SHEET:
SHEET:
SHEET:
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
Mon Nov 24 11:06:52 2014
Mon Nov 24 11:06:52 2014
Mon Nov 24 11:06:52 2014
1 19
1 19
1 19
OF
OF
OF
105-C913xx-00B
105-C913xx-00B
105-C913xx-00B
3
3
3
6
REV:
REV:
REV:
A
A
A
D D
8
8
8
1
7
7
7
2
6
6
6
3
5
5
5
4
Page 2
1
8
8
8
(2) TOBAGO PCIE INTERFACE
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
AH52
AH50
AG53
AG51
AF52
AF50
AE53
AE51
AD52
AD50
AC53
AC51
AA53
AA51
AJ51
AJ53
AU48
AR48
AA42
AA43
AC42
AC43
AG43
AE42
AE43
AE44
AG42
AA44
Y52
Y50
W53
W51
V52
V50
U53
U51
R53
R51
P52
P50
N53
N51
M52
M50
L53
L51
U43
U44
U42
W43
W42
R42
N42
N43
L43
U1B
PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N
PCIE_RX13P
PCIE_RX13N
PCIE_RX14P
PCIE_RX14N
PCIE_RX15P
PCIE_RX15N
PCIE_REFCLKP
PCIE_REFCLKN
PCIE_PVDD_1
PCIE_PVDD_2
BIF_VDDC
BIF_VDDC
BIF_VDDC
BIF_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
VSS
VSS
NC_VSS
PART 2 OF 16
BONAIRE
DD
DD
PCIE_TX0P
AL48
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIEXPRESS
PCIE_TX13P
PCIE_TX13N
PCIE_TX14P
PCIE_TX14N
PCIE_TX15P
PCIE_TX15N
PCIE_CALR_RX
PCIE_CALR_TX
PERSTB
PX_EN
NC_PX_EN_1
PCIE_TX0N
AL47
PCIE_TX1P
AL45
PCIE_TX1N
AL44
PCIE_TX2P
AJ48
PCIE_TX2N
AJ47
PCIE_TX3P
AG48
PCIE_TX3N
AG47
PCIE_TX4P
AG45
PCIE_TX4N
AG44
PCIE_TX5P
AE48
PCIE_TX5N
AE47
PCIE_TX6P
AC48
PCIE_TX6N
AC47
PCIE_TX7P
AC45
PCIE_TX7N
AC44
PCIE_TX8P
AA48
PCIE_TX8N
AA47
PCIE_TX9P
W48
PCIE_TX9N
W47
PCIE_TX10P
W45
PCIE_TX10N
W44
PCIE_TX11P
U48
PCIE_TX11N
U47
PCIE_TX12P
R48
PCIE_TX12N
R47
PCIE_TX13P
R45
PCIE_TX13N
R44
PCIE_TX14P
N48
PCIE_TX14N
N47
PCIE_TX15P
L48
PCIE_TX15N
L47
PCIE_CALR_RX
AN47
PCIE_CALR_TX
AN48
AK50
PERSTB_BUF
J48
PX_EN
J45
R152
1K
5%
DNI
C150 0.22uF 6.3V
C151 0.22uF 6.3V
C152 0.22uF 6.3V
C153 0.22uF 6.3V
C154 0.22uF 6.3V
C155 0.22uF 6.3V
C156 0.22uF 6.3V
C157 0.22uF 6.3V
C158 0.22uF 6.3V
C159 0.22uF 6.3V
C160 0.22uF 6.3V
C161 0.22uF 6.3V
C162 0.22uF 6.3V
C163 0.22uF 6.3V
C164 0.22uF 6.3V
C165 0.22uF 6.3V
C166 0.22uF 6.3V
C167 0.22uF 6.3V
C168 0.22uF 6.3V
C169 0.22uF 6.3V
C170 0.22uF 6.3V
C171 0.22uF 6.3V
C172 0.22uF 6.3V
C173 0.22uF 6.3V
C174 0.22uF 6.3V
C175 0.22uF 6.3V
C176 0.22uF 6.3V
C177 0.22uF 6.3V
C178 0.22uF 6.3V
C179 0.22uF 6.3V
C180 0.22uF 6.3V
C181 0.22uF 6.3V
R150 1K 1%
R151 1.69K 1%
PERP0
PERN0
PERP1
PERN1
PERP2
PERN2
PERP3
PERN3
PERP4
PERN4
PERP5
PERN5
PERP6
PERN6
PERP7
PERN7
PERP8
PERN8
PERP9
PERN9
PERP10
PERN10
PERP11
PERN11
PERP12
PERN12
PERP13
PERN13
PERP14
PERN14
PERP15
PERN15
+0.95V
1,11,16
IN
17,15,16
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
1
OUT
DD
C
C
C
BB
BB
BB
A A
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
C
C
C
B B
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
1
IN
C C
TP100
TP101
TP130
TP131
+1.8V
C120
10uF
6.3V
+0.95V
C130
1uF
6.3V
C134
1uF
6.3V
PETP0_GFXRP0
PETN0_GFXRN0
PETP1_GFXRP1
PETN1_GFXRN1
PETP2_GFXRP2
PETN2_GFXRN2
PETP3_GFXRP3
PETN3_GFXRN3
PETP4_GFXRP4
PETN4_GFXRN4
PETP5_GFXRP5
PETN5_GFXRN5
PETP6_GFXRP6
PETN6_GFXRN6
PETP7_GFXRP7
PETN7_GFXRN7
PETP8_GFXRP8
PETN8_GFXRN8
PETP9_GFXRP9
PETN9_GFXRN9
PETP10_GFXRP10
PETN10_GFXRN10
PETP11_GFXRP11
PETN11_GFXRN11
PETP12_GFXRP12
PETN12_GFXRN12
PETP13_GFXRP13
PETN13_GFXRN13
PETP14_GFXRP14
PETN14_GFXRN14
PETP15_GFXRP15
PETN15_GFXRN15
PCIE_REFCLKP
PCIE_REFCLKN
C121
C122
C123
1uF
1uF
1uF
6.3V
6.3V
6.3V
C131
C132
C133
1uF
1uF
1uF
6.3V
6.3V
6.3V
C135
C136
C137
1uF
6.3V
C138
1uF
1uF
10uF
6.3V
6.3V
6.3V
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
1.0
1.0
1.0
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
C
C
C
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
information incl uded herein.
information incl uded herein.
information incl uded herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
A
A
A
1
1
1
8
4
4
4
5
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
TOBAGO PCIE
TOBAGO PCIE
TOBAGO PCIE
SHEET:
SHEET:
SHEET:
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
Mon Nov 24 11:06:52 2014
Mon Nov 24 11:06:52 2014
Mon Nov 24 11:06:52 2014
2 19
2 19
2 19
OF
OF
OF
105-C913xx-00B
105-C913xx-00B
105-C913xx-00B
3
3
3
6
REV:
REV:
REV:
A
A
A
D D
8
8
8
1
7
7
7
2
6
6
6
3
5
5
5
4
Page 3
1
(3) TOBAGO MEMORY INTERFACE
2
3
4
5
6
7
8
A A
DQA0_<0>
4
BI
DQA0_<1>
4
BI
DQA0_<2>
4
BI
DQA0_<3>
4
BI
DQA0_<4>
4
BI
DQA0_<5>
4
BI
DQA0_<6>
4
BI
DQA0_<7>
4
BI
DQA0_<8>
4
BI
DQA0_<9>
4
BI
DQA0_<10>
4
BI
DQA0_<11>
4
BI
DQA0_<12>
4
BI
DQA0_<13>
4
BI
DQA0_<14>
4
BI
DQA0_<15>
4
BI
DQA0_<16>
4
BI
DQA0_<17>
4
BI
DQA0_<18>
4
BI
DQA0_<19>
4
BI
DQA0_<20>
4
BI
DQA0_<21>
4
BI
DQA0_<22>
4
BI
DQA0_<23>
4
BI
DQA0_<24>
4
BI
DQA0_<25>
4
BI
DQA0_<26>
4
BI
DQA0_<27>
4
BI
DQA0_<28>
4
BI
DQA0_<29>
4
BI
DQA0_<30>
4
BI
DQA0_<31>
4
R3600 1%120R
C3601
120pF
50V
BI
MAA0_<0>
4
BI
MAA0_<1>
4
BI
MAA0_<2>
4
BI
MAA0_<3>
4
BI
MAA0_<4>
4
BI
MAA0_<5>
4
BI
MAA0_<6>
4
BI
MAA0_<7>
4
BI
MAA0_<8>
4
BI
WCKA0_0
4
BI
WCKA0B_0
4
BI
WCKA0_1
4
BI
WCKA0B_1
4
BI
EDCA0_0
4
BI
EDCA0_1
4
BI
EDCA0_2
4
BI
EDCA0_3
4
BI
DDBIA0_0
4
BI
DDBIA0_1
4
BI
DDBIA0_2
4
BI
DDBIA0_3
4
BI
ADBIA0
4
BI
CSA0B_0
4
OUT
CASA0B
4
OUT
RASA0B
4
OUT
WEA0B
4
OUT
CKEA0
4
OUT
CLKA0
4
OUT
CLKA0B
4
OUT
MEM_CALRA MEM_CALRBMVREFDA MVREFDB
DNI
DRAM_RST_A_R DRAM_RST_B_R
10R 1%R3604
R3603
5.1K
1%
B B
C C
DRAM_RST_A
4
OUT
U1C
PART 3 OF 16
G51
DQA0_0
F52
DQA0_1
F50
DQA0_2
E53
DQA0_3
D50
DQA0_4
C49
DQA0_5
A49
DQA0_6
D48
DQA0_7
B48
DQA0_8
C47
DQA0_9
D46
DQA0_10
B46
DQA0_11
D44
DQA0_12
B44
DQA0_13
C43
DQA0_14
D42
DQA0_15
A41
DQA0_16
D40
DQA0_17
B40
DQA0_18
C39
DQA0_19
C37
DQA0_20
A37
DQA0_21
D36
DQA0_22
B36
DQA0_23
C35
DQA0_24
D34
DQA0_25
B34
DQA0_26
C33
DQA0_27
D32
DQA0_28
B32
DQA0_29
C31
DQA0_30
D30
DQA0_31
L33
MAA0_0
G33
MAA0_1
F37
MAA0_2
G37
MAA0_3
F39
MAA0_4
K39
MAA0_5
F29
MAA0_6
G29
MAA0_7
F33
MAA0_8
L37
MAA0_9
J53
WCKA0_0
H52
WCKA0B_0
B42
WCKA0_1
C41
WCKA0B_1
E51
EDCA0_0
C45
EDCA0_1
B38
EDCA0_2
A33
EDCA0_3
H50
DDBIA0_0
A45
DDBIA0_1
D38
DDBIA0_2
B30
DDBIA0_3
L29
ADBIA0
K35
CSA0B_0
K31
CSA0B_1
K27
CASA0B
F35
RASA0B
M41
WEA0B
G25
CKEA0
F41
CLKA0
G41
CLKA0B
F31
MEM_CALRA
L25
DRAM_RSTA
BONAIRE
DQA1_0
DQA1_1
DQA1_2
DQA1_3
DQA1_4
DQA1_5
DQA1_6
DQA1_7
DQA1_8
DQA1_9
DQA1_10
DQA1_11
DQA1_12
DQA1_13
DQA1_14
DQA1_15
DQA1_16
DQA1_17
DQA1_18
DQA1_19
DQA1_20
DQA1_21
DQA1_22
DQA1_23
DQA1_24
DQA1_25
DQA1_26
DQA1_27
DQA1_28
DQA1_29
DQA1_30
DQA1_31
MAA1_0
MAA1_1
MAA1_2
MAA1_3
MAA1_4
MAA1_5
MAA1_6
MAA1_7
MEMORY INTERFACE BANK A
MAA1_8
MAA1_9
WCKA1_0
WCKA1B_0
WCKA1_1
WCKA1B_1
EDCA1_0
EDCA1_1
EDCA1_2
EDCA1_3
DDBIA1_0
DDBIA1_1
DDBIA1_2
DDBIA1_3
ADBIA1
CSA1B_0
CSA1B_1
CASA1B
RASA1B
WEA1B
CKEA1
CLKA1
CLKA1B
MVREFDA
A29
D28
B28
C27
B26
C25
A25
D24
B24
C23
D22
B22
D20
B20
C19
D18
A17
D16
B16
C15
C13
A13
D12
B12
C11
D10
B10
C9
D8
B8
C7
B6
K19
F17
G13
F15
F13
F11
F23
L21
F19
G17
C17
B18
A5
C5
D26
C21
B14
A9
C29
A21
D14
D6
G21
K15
F21
K23
L17
G11
F25
F9
G9
F27
DQA1_<0>
DQA1_<1>
DQA1_<2>
DQA1_<3>
DQA1_<4>
DQA1_<5>
DQA1_<6>
DQA1_<7>
DQA1_<8>
DQA1_<9>
DQA1_<10>
DQA1_<11>
DQA1_<12>
DQA1_<13>
DQA1_<14>
DQA1_<15>
DQA1_<16>
DQA1_<17>
DQA1_<18>
DQA1_<19>
DQA1_<20>
DQA1_<21>
DQA1_<22>
DQA1_<23>
DQA1_<24>
DQA1_<25>
DQA1_<26>
DQA1_<27>
DQA1_<28>
DQA1_<29>
DQA1_<30>
DQA1_<31>
MAA1_<0>
MAA1_<1>
MAA1_<2>
MAA1_<3>
MAA1_<4>
MAA1_<5>
MAA1_<6>
MAA1_<7>
MAA1_<8>
WCKA1_0
WCKA1B_0
WCKA1_1
WCKA1B_1
EDCA1_0
EDCA1_1
EDCA1_2
EDCA1_3
DDBIA1_0
DDBIA1_1
DDBIA1_2
DDBIA1_3
ADBIA1
CSA1B_0
CASA1B
RASA1B
WEA1B
CKEA1
CLKA1
CLKA1B
USE INTERNAL VREF
MVREFD = 0.7 * VDDR1
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
OUT
4
OUT
4
OUT
4
OUT
OUT
OUT
OUT
+MVDD +MVDD
4
4
4
R3601
40.2R
1%
DNI
R3602
C3600
100R
1uF
1%
6.3V
DNI
DNI
DRAM_RST_B
4
OUT
1%49.9RR36151%49.9RR3605
C3611
120pF
50V
DQB0_<0>
4
BI
DQB0_<1>
4
BI
DQB0_<2>
4
BI
DQB0_<3>
4
BI
DQB0_<4>
4
BI
DQB0_<5>
4
BI
DQB0_<6>
4
BI
DQB0_<7>
4
BI
DQB0_<8>
4
BI
DQB0_<9>
4
BI
DQB0_<10>
4
BI
DQB0_<11>
4
BI
DQB0_<12>
4
BI
DQB0_<13>
4
BI
DQB0_<14>
4
BI
DQB0_<15>
4
BI
DQB0_<16>
4
BI
DQB0_<17>
4
BI
DQB0_<18>
4
BI
DQB0_<19>
4
BI
DQB0_<20>
4
BI
DQB0_<21>
4
BI
DQB0_<22>
4
BI
DQB0_<23>
4
BI
DQB0_<24>
4
BI
DQB0_<25>
4
BI
DQB0_<26>
4
BI
DQB0_<27>
4
BI
DQB0_<28>
4
BI
DQB0_<29>
4
BI
DQB0_<30>
4
BI
DQB0_<31>
4
BI
MAB0_<0>
4
BI
MAB0_<1>
4
BI
MAB0_<2>
4
BI
MAB0_<3>
4
BI
MAB0_<4>
4
BI
MAB0_<5>
4
BI
MAB0_<6>
4
BI
MAB0_<7>
4
BI
MAB0_<8>
4
BI
WCKB0_0
4
BI
WCKB0B_0
4
BI
WCKB0_1
4
BI
WCKB0B_1
4
BI
EDCB0_0
4
BI
EDCB0_1
4
BI
EDCB0_2
4
BI
EDCB0_3
4
BI
DDBIB0_0
4
BI
DDBIB0_1
4
BI
DDBIB0_2
4
BI
DDBIB0_3
4
BI
ADBIB0
4
BI
CSB0B_0
4
OUT
CASB0B
4
OUT
RASB0B
4
OUT
WEB0B
4
OUT
CKEB0
4
OUT
CLKB0
4
OUT
CLKB0B
4
OUT
1%120RR3610
DNI
1%10RR 3614
R3613
5.1K
1%
U1D
PART 4 OF 16
AJ1
DQB0_0
AH4
DQB0_1
AH2
DQB0_2
AG3
DQB0_3
AF2
DQB0_4
AE3
DQB0_5
AE1
DQB0_6
AD4
DQB0_7
AD2
DQB0_8
AC3
DQB0_9
AB4
DQB0_10
AB2
DQB0_11
Y4
DQB0_12
Y2
DQB0_13
W3
DQB0_14
V4
DQB0_15
U1
DQB0_16
T4
DQB0_17
T2
DQB0_18
R3
DQB0_19
N3
DQB0_20
N1
DQB0_21
M4
DQB0_22
M2
DQB0_23
L3
DQB0_24
K4
DQB0_25
K2
DQB0_26
J3
DQB0_27
H4
DQB0_28
H2
DQB0_29
G3
DQB0_30
F2
DQB0_31
W10
MAB0_0
U6
MAB0_1
N7
MAB0_2
R6
MAB0_3
N6
MAB0_4
L6
MAB0_5
AC6
MAB0_6
AA11
MAB0_7
W6
MAB0_8
U7
MAB0_9
U3
WCKB0_0
V2
WCKB0B_0
E1
WCKB0_1
E3
WCKB0B_1
AF4
EDCB0_0
AA3
EDCB0_1
P2
EDCB0_2
J1
EDCB0_3
AJ3
DDBIB0_0
AA1
DDBIB0_1
P4
DDBIB0_2
F4
DDBIB0_3
AA7
ADBIB0
R10
CSB0B_0
AA6
CSB0B_1
AC10
CASB0B
U11
RASB0B
L7
WEB0B
AE6
CKEB0
J6
CLKB0
J7
CLKB0B
AL6
MEM_CALRB
AE11
DRAM_RSTB
BONAIRE
DQB1_0
DQB1_1
DQB1_2
DQB1_3
DQB1_4
DQB1_5
DQB1_6
DQB1_7
DQB1_8
DQB1_9
DQB1_10
DQB1_11
DQB1_12
DQB1_13
DQB1_14
DQB1_15
DQB1_16
DQB1_17
DQB1_18
DQB1_19
DQB1_20
DQB1_21
DQB1_22
DQB1_23
DQB1_24
DQB1_25
DQB1_26
DQB1_27
DQB1_28
DQB1_29
DQB1_30
DQB1_31
MAB1_0
MAB1_1
MAB1_2
MAB1_3
MAB1_4
MAB1_5
MAB1_6
MEMORY INTERFACE BANK B
MAB1_7
MAB1_8
MAB1_9
WCKB1_0
WCKB1B_0
WCKB1_1
WCKB1B_1
EDCB1_0
EDCB1_1
EDCB1_2
EDCB1_3
DDBIB1_0
DDBIB1_1
DDBIB1_2
DDBIB1_3
ADBIB1
CSB1B_0
CSB1B_1
CASB1B
RASB1B
WEB1B
CKEB1
CLKB1
CLKB1B
MVREFDB
AK4
AL3
AM2
AM4
AN3
AP2
AP4
AR3
AT2
AT4
AU1
AU3
AW3
AY2
AY4
BA1
BB4
BC3
BD2
BD4
BF2
BF4
BG3
BH2
BH4
BJ1
BJ3
BK4
BN5
BK6
BM6
BL7
AN11
AN6
AU7
AR10
AW6
AW10
AJ6
AJ7
AN7
AU11
BB2
BA3
BN9
BM8
AN1
AV2
BE3
BL5
AK2
AV4
BE1
BK8
AJ11
AU6
AL10
AG10
AR6
BA12
AE7
BA6
BA7
AG6
DQB1_<0>
DQB1_<1>
DQB1_<2>
DQB1_<3>
DQB1_<4>
DQB1_<5>
DQB1_<6>
DQB1_<7>
DQB1_<8>
DQB1_<9>
DQB1_<10>
DQB1_<11>
DQB1_<12>
DQB1_<13>
DQB1_<14>
DQB1_<15>
DQB1_<16>
DQB1_<17>
DQB1_<18>
DQB1_<19>
DQB1_<20>
DQB1_<21>
DQB1_<22>
DQB1_<23>
DQB1_<24>
DQB1_<25>
DQB1_<26>
DQB1_<27>
DQB1_<28>
DQB1_<29>
DQB1_<30>
DQB1_<31>
MAB1_<0>
MAB1_<1>
MAB1_<2>
MAB1_<3>
MAB1_<4>
MAB1_<5>
MAB1_<6>
MAB1_<7>
MAB1_<8>
WCKB1_0
WCKB1B_0
WCKB1_1
WCKB1B_1
EDCB1_0
EDCB1_1
EDCB1_2
EDCB1_3
DDBIB1_0
DDBIB1_1
DDBIB1_2
DDBIB1_3
ADBIB1
CSB1B_0
CASB1B
RASB1B
WEB1B
CKEB1
CLKB1
CLKB1B
USE INTERNAL VREF
MVREFD = 0.7 * VDDR1
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
BI
4
OUT
4
OUT
4
OUT
4
OUT
4
OUT
4
OUT
4
OUT
R3611
40.2R
1%
DNI
C3610
R3612
1uF
100R
6.3V
1%
DNI
DNI
D D
1
2
3
4
5
6
7
8
Page 4
1
2
3
4
5
6
7
8
(4) GDDR5 CHAB x32
MF = 0
U2000
DQA0_<16>
3
BI
DQA0_<17>
3
BI
DQA0_<19>
3
BI
DQA0_<18>
3
BI
DQA0_<23>
3
BI
DQA0_<21>
3
BI
DQA0_<22>
3
BI
DQA0_<20>
3
60.4R 1%R2003
60.4RR2004 1%
BI
DQA0_<25>
3
BI
DQA0_<26>
3
BI
DQA0_<27>
3
BI
DQA0_<24>
3
BI
DQA0_<29>
3
BI
DQA0_<30>
3
BI
DQA0_<28>
3
BI
DQA0_<31>
3
BI
DQA0_<14>
3
BI
DQA0_<15>
3
BI
DQA0_<13>
3
BI
DQA0_<12>
3
BI
DQA0_<9>
3
BI
DQA0_<11>
3
BI
DQA0_<10>
3
BI
DQA0_<8>
3
BI
DQA0_<7>
3
BI
DQA0_<6>
3
BI
DQA0_<4>
3
BI
DQA0_<5>
3
BI
DQA0_<0>
3
BI
DQA0_<2>
3
BI
DQA0_<1>
3
BI
DQA0_<3>
3
BI
MAA0_<8>
3
BI
MAA0_<7>
3
BI
MAA0_<6>
3
BI
MAA0_<5>
3
BI
MAA0_<4>
3
BI
MAA0_<3>
3
BI
MAA0_<2>
3
BI
MAA0_<1>
3
BI
MAA0_<0>
3
BI
WCKA0_0
3
IN
WCKA0B_0
3
IN
WCKA0_1
3
IN
WCKA0B_1
3
IN
EDCA0_2
3
OUT
EDCA0_3
3
OUT
EDCA0_1
3
OUT
EDCA0_0
3
OUT
3
3
3
3
DDBIA0_2
BI
DDBIA0_3
BI
DDBIA0_1
BI
DDBIA0_0
BI
RASA0B
3
IN
CASA0B
3
IN
CKEA0
3
IN
CLKA0B
3
IN
CLKA0
3
IN
CSA0B_0
3
IN
WEA0B
3
IN
ZQ_A0 ZQ_A1 ZQ_B0 ZQ_B1
1%120RR2000
DRAM_RST_A
3,4
IN
1%2.37KR2010
1%5.49KR2011
VREFD1_A0 VREFD1_A1 VREFD1_B0 VREFD1_B1
6.3V1uFC2000
1%2.37KR2012
1%5.49KR2013
VREFD2_A0 VREFD2_A1 VREFD2_B0 VREFD2_B1
6.3V1uFC2001
VREFC_A0 VREFC_A1 VREFC_B0 VREFC _B1
1%2.37KR2014
1%5.49KR2015
6.3V1uFC2002
ADBIA0
3
IN
A A
B B
+MVDD
C C
+MVDD
+MVDD
+MVDD
M2
M4
N2
N4
T2
T4
V2
V4
M13
M11
N13
N11
T13
T11
V13
V11
F13
F11
E13
E11
B13
B11
A13
A11
F2
F4
E2
E4
B2
B4
A2
A4
J5
K4
K5
K10
K11
H10
H11
H5
H4
D4
D5
P4
P5
R2
R13
C13
C2
P2
P13
D13
D2
G3
L3
J3
J11
J12
G12
L12
J13
J10
J2
J1
A5
V5
A10
V10
J14
J4
DQ31__DQ7
DQ30__DQ6
DQ29__DQ5
DQ28__DQ4
DQ27__DQ3
DQ26__DQ2
DQ25__DQ1
DQ24__DQ0
DQ23__DQ15
DQ22__DQ14
DQ21__DQ13
DQ20__DQ12
DQ19__DQ11
DQ18__DQ10
DQ17__DQ9
DQ16__DQ8
DQ15__DQ23
DQ14__DQ22
DQ13__DQ21
DQ12__DQ20
DQ11__DQ19
DQ10__DQ18
DQ9__DQ17
DQ8__DQ16
DQ7__DQ31
DQ6__DQ30
DQ5__DQ29
DQ4__DQ28
DQ3__DQ27
DQ2__DQ26
DQ1__DQ25
DQ0__DQ24
RFU_A12_NC
A7_A8__A0_A10
A6_A11__A1_A9
A5_BA1__A3_BA3
A4_BA2__A2_BA0
A3_BA3__A5_BA1
A2_BA0__A4_BA2
A1_A9__A6_A11
A0_A10__A7_A8
WCK01__WCK23
WCK01#__WCK23#
WCK23__WCK01
WCK23#__WCK01#
EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3
DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#
RAS#__CAS#
CAS#__RAS#
CKE#
CK#
CK
CS#__WE#
WE#__CS#
ZQ
SEN
RESET#
MF
Vpp_NC
Vpp_NC1
VREFD1
VREFD2
VREFC
ABI#
VDDQ_B1
VDDQ_B3
VDDQ_B12
VDDQ_B14
VDDQ_D1
VDDQ_D3
VDDQ_D12
VDDQ_D14
VDDQ_E5
VDDQ_E10
VDDQ_F1
VDDQ_F3
VDDQ_F12
VDDQ_F14
VDDQ_G2
VDDQ_G13
VDDQ_H3
VDDQ_H12
VDDQ_K3
VDDQ_K12
VDDQ_L2
VDDQ_L13
VDDQ_M1
VDDQ_M3
VDDQ_M12
VDDQ_M14
VDDQ_N5
VDDQ_N10
VDDQ_P1
VDDQ_P3
VDDQ_P12
VDDQ_P14
VDDQ_T1
VDDQ_T3
VDDQ_T12
VDDQ_T14
VDD_C5
VDD_C10
VDD_D11
VDD_G1
VDD_G4
VDD_G11
VDD_G14
VDD_L1
VDD_L4
VDD_L11
VDD_L14
VDD_P11
VDD_R5
VDD_R10
VSSQ_A1
VSSQ_A3
VSSQ_A12
VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4
VSSQ_C11
VSSQ_C12
VSSQ_C14
VSSQ_E1
VSSQ_E3
VSSQ_E12
VSSQ_E14
VSSQ_F5
VSSQ_F10
VSSQ_H2
VSSQ_H13
VSSQ_K2
VSSQ_K13
VSSQ_M5
VSSQ_M10
VSSQ_N1
VSSQ_N3
VSSQ_N12
VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4
VSSQ_R11
VSSQ_R12
VSSQ_R14
VSSQ_V1
VSSQ_V3
VSSQ_V12
VSSQ_V14
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
+MVDD
B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14
+MVDD
C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10
A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
+MVDD
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
+MVDD
V1
V3
V12
V14
+MVDD
B5
B10
D10
G5
+MVDD
G10
H1
H14
K1
K14
+MVDD
L5
L10
P10
T5
T10
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
BI
3
IN
3
IN
3
IN
3
IN
3
OUT
3
OUT
3
OUT
3
OUT
3
BI
3
BI
3
BI
3
BI
3
IN
3
IN
1%60.4RR2203
1%60.4RR2204
3
IN
3
IN
3
IN
3
IN
3
IN
1%120RR2200
3,4
IN
1%2.37KR2210
1%5.49KR2211
6.3V1uFC2200
1%2.37KR2212
1%5.49KR2213
6.3V1uFC2201
1%2.37KR2214
1%5.49KR2215
6.3V1uFC2202
3
IN
DQA1 _<1 6>
DQA1 _<1 7>
DQA1 _<1 9>
DQA1 _<1 8>
DQA1 _<2 3>
DQA1 _<2 1>
DQA1 _<2 2>
DQA1 _<2 0>
DQA1 _<2 4>
DQA1 _<2 5>
DQA1 _<2 6>
DQA1 _<2 7>
DQA1 _<3 0>
DQA1 _<3 1>
DQA1 _<2 8>
DQA1 _<2 9>
DQA1 _<1 3>
DQA1 _<1 4>
DQA1 _<1 5>
DQA1 _<1 2>
DQA1 _<1 0>
DQA1 _<9 >
DQA1 _<1 1>
DQA1 _<8 >
DQA1 _<7 >
DQA1 _<6 >
DQA1 _<4 >
DQA1 _<5 >
DQA1 _<0 >
DQA1 _<2 >
DQA1 _<1 >
DQA1 _<3 >
MAA1_<8>
MAA1_<0>
MAA1_<1>
MAA1_<3>
MAA1_<2>
MAA1_<5>
MAA1_<4>
MAA1_<6>
MAA1_<7>
WCKA1_0
WCKA1B_0
WCKA1_1
WCKA1B_1
EDCA1_2
EDCA1_3
EDCA1_1
EDCA1_0
DDBIA1_2
DDBIA1_3
DDBIA1_1
DDBIA1_0
CASA1B
RASA1B
CKEA1
CLKA1B
CLKA1
WEA1B
CSA1B_0
DRAM_RST_A
ADBIA1
MF = 1 MF = 0 MF = 1
U2200
M2
DQ31__DQ7
M4
DQ30__DQ6
N2
DQ29__DQ5
N4
DQ28__DQ4
T2
DQ27__DQ3
T4
DQ26__DQ2
V2
DQ25__DQ1
V4
DQ24__DQ0
M13
DQ23__DQ15
M11
DQ22__DQ14
N13
DQ21__DQ13
N11
DQ20__DQ12
T13
DQ19__DQ11
T11
DQ18__DQ10
V13
DQ17__DQ9
V11
DQ16__DQ8
F13
DQ15__DQ23
F11
DQ14__DQ22
E13
DQ13__DQ21
E11
DQ12__DQ20
B13
DQ11__DQ19
B11
DQ10__DQ18
A13
DQ9__DQ17
A11
DQ8__DQ16
F2
DQ7__DQ31
F4
DQ6__DQ30
E2
DQ5__DQ29
E4
DQ4__DQ28
B2
DQ3__DQ27
B4
DQ2__DQ26
A2
DQ1__DQ25
A4
DQ0__DQ24
J5
RFU_A12_NC
K4
A7_A8__A0_A10
K5
A6_A11__A1_A9
K10
A5_BA1__A3_BA3
K11
A4_BA2__A2_BA0
H10
A3_BA3__A5_BA1
H11
A2_BA0__A4_BA2
H5
A1_A9__A6_A11
H4
A0_A10__A7_A8
D4
WCK01__WCK23
D5
WCK01#__WCK23#
P4
WCK23__WCK01
P5
WCK23#__WCK01#
R2
EDC3__EDC0
R13
EDC2__EDC1
C13
EDC1__EDC2
C2
EDC0__EDC3
P2
DBI3#__DBI0#
P13
DBI2#__DBI1#
D13
DBI1#__DBI2#
D2
DBI0#__DBI3#
G3
RAS#__CAS#
L3
CAS#__RAS#
J3
CKE#
J11
CK#
J12
CK
G12
CS#__WE#
L12
WE#__CS#
J13
ZQ
J10
SEN
J2
RESET#
J1
MF
A5
Vpp_NC
V5
Vpp_NC1
A10
VREFD1
V10
VREFD2
J14
VREFC
J4
ABI#
VDDQ_B1
VDDQ_B3
VDDQ_B12
VDDQ_B14
VDDQ_D1
VDDQ_D3
VDDQ_D12
VDDQ_D14
VDDQ_E5
VDDQ_E10
VDDQ_F1
VDDQ_F3
VDDQ_F12
VDDQ_F14
VDDQ_G2
VDDQ_G13
VDDQ_H3
VDDQ_H12
VDDQ_K3
VDDQ_K12
VDDQ_L2
VDDQ_L13
VDDQ_M1
VDDQ_M3
VDDQ_M12
VDDQ_M14
VDDQ_N5
VDDQ_N10
VDDQ_P1
VDDQ_P3
VDDQ_P12
VDDQ_P14
VDDQ_T1
VDDQ_T3
VDDQ_T12
VDDQ_T14
VDD_C5
VDD_C10
VDD_D11
VDD_G1
VDD_G4
VDD_G11
VDD_G14
VDD_L1
VDD_L4
VDD_L11
VDD_L14
VDD_P11
VDD_R5
VDD_R10
VSSQ_A1
VSSQ_A3
VSSQ_A12
VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4
VSSQ_C11
VSSQ_C12
VSSQ_C14
VSSQ_E1
VSSQ_E3
VSSQ_E12
VSSQ_E14
VSSQ_F5
VSSQ_F10
VSSQ_H2
VSSQ_H13
VSSQ_K2
VSSQ_K13
VSSQ_M5
VSSQ_M10
VSSQ_N1
VSSQ_N3
VSSQ_N12
VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4
VSSQ_R11
VSSQ_R12
VSSQ_R14
VSSQ_V1
VSSQ_V3
VSSQ_V12
VSSQ_V14
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
+MVDD
B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14
+MVDD
C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10
A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
+MVDD
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
V1
V3
V12
V14
B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10
R2400 120R 1%
+MVDD
+MVDD
+MVDD
15
DQB0 _<1 5>
3
BI
14
DQB0 _<1 4>
3
BI
12
DQB0 _<1 2>
3
BI
13
DQB0 _<1 3>
3
BI
8
DQB0 _<8 >
3
BI
10
DQB0 _<1 0>
3
BI
9
DQB0 _<9 >
3
BI
11
DQB0 _<1 1>
3
BI
7
DQB0 _<7 >
3
BI
3
DQB0 _<3 >
3
BI
6
DQB0 _<6 >
3
BI
5
DQB0 _<5 >
3
BI
0
DQB0 _<0 >
3
BI
1
DQB0 _<1 >
3
BI
4
DQB0 _<4 >
3
BI
2
DQB0 _<2 >
3
BI
19
DQB0 _<1 9>
3
BI
17
DQB0 _<1 7>
3
BI
18
DQB0 _<1 8>
3
BI
16
DQB0 _<1 6>
3
BI
21
DQB0 _<2 1>
3
BI
22
DQB0 _<2 2>
3
BI
20
DQB0 _<2 0>
3
BI
23
DQB0 _<2 3>
3
BI
24
DQB0 _<2 4>
3
BI
25
DQB0 _<2 5>
3
BI
27
DQB0 _<2 7>
3
BI
26
DQB0 _<2 6>
3
BI
31
DQB0 _<3 1>
3
BI
29
DQB0 _<2 9>
3
BI
30
DQB0 _<3 0>
3
BI
28
DQB0 _<2 8>
3
BI
8
MAB 0_ <8>
3
BI
7
MAB 0_ <7>
3
BI
6
MAB 0_ <6>
3
BI
5
MAB 0_ <5>
3
BI
4
MAB 0_ <4>
3
BI
3
MAB 0_ <3>
3
BI
2
MAB 0_ <2>
3
BI
1
MAB 0_ <1>
3
BI
0
MAB 0_ <0>
3
BI
WCKB0_1
3
IN
WCKB0B_1
3
IN
WCKB0_0
3
IN
WCKB0B_0
3
IN
EDCB0_1
3
OUT
EDCB0_0
3
OUT
EDCB0_2
3
OUT
EDCB0_3
3
OUT
3
3
3
3
1%60.4RR2403
1%60.4RR2404
DDBIB0_1
BI
DDBIB0_0
BI
DDBIB0_2
BI
DDBIB0_3
BI
RASB0B
3
IN
CASB0B
3
IN
CKEB0
3
IN
CLKB0B
3
IN
CLKB0
3
IN
CSB0B_0
3
IN
WEB0B
3
IN
DRAM_RST_B
3,4
IN
1%2.37KR2410
1%5.49KR2411
6.3V1uFC2400
1%2.37KR2412
1%5.49KR2413
6.3V1uFC2401
1%2.37KR2414
1%5.49KR2415
6.3V1uFC2402
ADBIB0
3
IN
M2
M4
N2
N4
T2
T4
V2
V4
M13
M11
N13
N11
T13
T11
V13
V11
F13
F11
E13
E11
B13
B11
A13
A11
F2
F4
E2
E4
B2
B4
A2
A4
J5
K4
K5
K10
K11
H10
H11
H5
H4
D4
D5
P4
P5
R2
R13
C13
C2
P2
P13
D13
D2
G3
L3
J3
J11
J12
G12
L12
J13
J10
J2
J1
A5
V5
A10
V10
J14
J4
DQ31__DQ7
DQ30__DQ6
DQ29__DQ5
DQ28__DQ4
DQ27__DQ3
DQ26__DQ2
DQ25__DQ1
DQ24__DQ0
DQ23__DQ15
DQ22__DQ14
DQ21__DQ13
DQ20__DQ12
DQ19__DQ11
DQ18__DQ10
DQ17__DQ9
DQ16__DQ8
DQ15__DQ23
DQ14__DQ22
DQ13__DQ21
DQ12__DQ20
DQ11__DQ19
DQ10__DQ18
DQ9__DQ17
DQ8__DQ16
DQ7__DQ31
DQ6__DQ30
DQ5__DQ29
DQ4__DQ28
DQ3__DQ27
DQ2__DQ26
DQ1__DQ25
DQ0__DQ24
RFU_A12_NC
A7_A8__A0_A10
A6_A11__A1_A9
A5_BA1__A3_BA3
A4_BA2__A2_BA0
A3_BA3__A5_BA1
A2_BA0__A4_BA2
A1_A9__A6_A11
A0_A10__A7_A8
WCK01__WCK23
WCK01#__WCK23#
WCK23__WCK01
WCK23#__WCK01#
EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3
DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#
RAS#__CAS#
CAS#__RAS#
CKE#
CK#
CK
CS#__WE#
WE#__CS#
ZQ
SEN
RESET#
MF
Vpp_NC
Vpp_NC1
VREFD1
VREFD2
VREFC
ABI#
U2400
VDDQ_B1
VDDQ_B3
VDDQ_B12
VDDQ_B14
VDDQ_D1
VDDQ_D3
VDDQ_D12
VDDQ_D14
VDDQ_E5
VDDQ_E10
VDDQ_F1
VDDQ_F3
VDDQ_F12
VDDQ_F14
VDDQ_G2
VDDQ_G13
VDDQ_H3
VDDQ_H12
VDDQ_K3
VDDQ_K12
VDDQ_L2
VDDQ_L13
VDDQ_M1
VDDQ_M3
VDDQ_M12
VDDQ_M14
VDDQ_N5
VDDQ_N10
VDDQ_P1
VDDQ_P3
VDDQ_P12
VDDQ_P14
VDDQ_T1
VDDQ_T3
VDDQ_T12
VDDQ_T14
VDD_C5
VDD_C10
VDD_D11
VDD_G1
VDD_G4
VDD_G11
VDD_G14
VDD_L1
VDD_L4
VDD_L11
VDD_L14
VDD_P11
VDD_R5
VDD_R10
VSSQ_A1
VSSQ_A3
VSSQ_A12
VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4
VSSQ_C11
VSSQ_C12
VSSQ_C14
VSSQ_E1
VSSQ_E3
VSSQ_E12
VSSQ_E14
VSSQ_F5
VSSQ_F10
VSSQ_H2
VSSQ_H13
VSSQ_K2
VSSQ_K13
VSSQ_M5
VSSQ_M10
VSSQ_N1
VSSQ_N3
VSSQ_N12
VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4
VSSQ_R11
VSSQ_R12
VSSQ_R14
VSSQ_V1
VSSQ_V3
VSSQ_V12
VSSQ_V14
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
+MVDD
B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14
+MVDD
C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10
A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
V1
V3
V12
V14
B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10
VDDQ_B1
VDDQ_B3
VDDQ_B12
VDDQ_B14
VDDQ_D1
VDDQ_D3
VDDQ_D12
VDDQ_D14
VDDQ_E5
VDDQ_E10
VDDQ_F1
VDDQ_F3
VDDQ_F12
VDDQ_F14
VDDQ_G2
VDDQ_G13
VDDQ_H3
VDDQ_H12
VDDQ_K3
VDDQ_K12
VDDQ_L2
VDDQ_L13
VDDQ_M1
VDDQ_M3
VDDQ_M12
VDDQ_M14
VDDQ_N5
VDDQ_N10
VDDQ_P1
VDDQ_P3
VDDQ_P12
VDDQ_P14
VDDQ_T1
VDDQ_T3
VDDQ_T12
VDDQ_T14
VDD_C5
VDD_C10
VDD_D11
VDD_G1
VDD_G4
VDD_G11
VDD_G14
VDD_L1
VDD_L4
VDD_L11
VDD_L14
VDD_P11
VDD_R5
VDD_R10
VSSQ_A1
VSSQ_A3
VSSQ_A12
VSSQ_A14
VSSQ_C1
VSSQ_C3
VSSQ_C4
VSSQ_C11
VSSQ_C12
VSSQ_C14
VSSQ_E1
VSSQ_E3
VSSQ_E12
VSSQ_E14
VSSQ_F5
VSSQ_F10
VSSQ_H2
VSSQ_H13
VSSQ_K2
VSSQ_K13
VSSQ_M5
VSSQ_M10
VSSQ_N1
VSSQ_N3
VSSQ_N12
VSSQ_N14
VSSQ_R1
VSSQ_R3
VSSQ_R4
VSSQ_R11
VSSQ_R12
VSSQ_R14
VSSQ_V1
VSSQ_V3
VSSQ_V12
VSSQ_V14
VSS_B5
VSS_B10
VSS_D10
VSS_G5
VSS_G10
VSS_H1
VSS_H14
VSS_K1
VSS_K14
VSS_L5
VSS_L10
VSS_P10
VSS_T5
VSS_T10
+MVDD
B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14
+MVDD
C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10
A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
V1
V3
V12
V14
B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10
U2600
16
DQB1 _<1 6>
3
BI
17
DQB1 _<1 7>
3
BI
19
DQB1 _<1 9>
3
BI
18
DQB1 _<1 8>
3
BI
23
DQB1 _<2 3>
3
BI
21
DQB1 _<2 1>
3
BI
22
DQB1 _<2 2>
3
BI
20
DQB1 _<2 0>
3
BI
26
DQB1 _<2 6>
3
BI
24
DQB1 _<2 4>
3
BI
25
DQB1 _<2 5>
3
BI
27
DQB1 _<2 7>
3
BI
28
DQB1 _<2 8>
3
BI
30
DQB1 _<3 0>
3
BI
29
DQB1 _<2 9>
3
BI
31
DQB1 _<3 1>
3
BI
14
DQB1 _<1 4>
3
BI
13
DQB1 _<1 3>
3
BI
15
DQB1 _<1 5>
3
BI
12
DQB1 _<1 2>
3
BI
11
DQB1 _<1 1>
3
BI
8
DQB1 _<8 >
3
BI
10
DQB1 _<1 0>
3
BI
9
DQB1 _<9 >
3
BI
7
DQB1 _<7 >
3
BI
6
DQB1 _<6 >
3
BI
4
DQB1 _<4 >
3
BI
5
DQB1 _<5 >
3
BI
0
DQB1 _<0 >
3
BI
2
DQB1 _<2 >
3
BI
1
DQB1 _<1 >
3
BI
3
DQB1 _<3 >
3
BI
8
MAB 1_ <8>
3
BI
0
MAB 1_ <0>
3
BI
1
MAB 1_ <1>
3
BI
3
MAB 1_ <3>
3
BI
2
MAB 1_ <2>
3
BI
5
MAB 1_ <5>
3
BI
4
MAB 1_ <4>
3
BI
6
MAB 1_ <6>
3
BI
7
MAB 1_ <7>
3
BI
WCKB1_0
3
IN
WCKB1B_0
3
IN
WCKB1_1
3
IN
WCKB1B_1
3
IN
EDCB1_2
3
OUT
EDCB1_3
3
OUT
EDCB1_1
3
OUT
EDCB1_0
3
OUT
3
3
3
3
+MVDD
R2600 1%120R
+MVDD
+MVDD
+MVDD
+MVDD
DDBIB1_2
BI
DDBIB1_3
BI
DDBIB1_1
BI
DDBIB1_0
BI
CASB1B
3
IN
RASB1B
3
IN
1%60.4RR2603
1%60.4RR2604
CKEB1
3
IN
CLKB1B
3
IN
CLKB1
3
IN
WEB1B
3
IN
CSB1B_0
3
IN
DRAM_RST_B
3,4
IN
1%2.37KR2610
1%5.49KR2611
6.3V1uFC2600
1%2.37KR2612
1%5.49KR2613
6.3V1uFC2601
1%2.37KR2614
1%5.49KR2615
6.3V1uFC2602
ADBIB1
3
IN
M2
M4
N2
N4
T2
T4
V2
V4
M13
M11
N13
N11
T13
T11
V13
V11
F13
F11
E13
E11
B13
B11
A13
A11
F2
F4
E2
E4
B2
B4
A2
A4
J5
K4
K5
K10
K11
H10
H11
H5
H4
D4
D5
P4
P5
R2
R13
C13
C2
P2
P13
D13
D2
G3
L3
J3
J11
J12
G12
L12
J13
J10
J2
J1
A5
V5
A10
V10
J14
J4
DQ31__DQ7
DQ30__DQ6
DQ29__DQ5
DQ28__DQ4
DQ27__DQ3
DQ26__DQ2
DQ25__DQ1
DQ24__DQ0
DQ23__DQ15
DQ22__DQ14
DQ21__DQ13
DQ20__DQ12
DQ19__DQ11
DQ18__DQ10
DQ17__DQ9
DQ16__DQ8
DQ15__DQ23
DQ14__DQ22
DQ13__DQ21
DQ12__DQ20
DQ11__DQ19
DQ10__DQ18
DQ9__DQ17
DQ8__DQ16
DQ7__DQ31
DQ6__DQ30
DQ5__DQ29
DQ4__DQ28
DQ3__DQ27
DQ2__DQ26
DQ1__DQ25
DQ0__DQ24
RFU_A12_NC
A7_A8__A0_A10
A6_A11__A1_A9
A5_BA1__A3_BA3
A4_BA2__A2_BA0
A3_BA3__A5_BA1
A2_BA0__A4_BA2
A1_A9__A6_A11
A0_A10__A7_A8
WCK01__WCK23
WCK01#__WCK23#
WCK23__WCK01
WCK23#__WCK01#
EDC3__EDC0
EDC2__EDC1
EDC1__EDC2
EDC0__EDC3
DBI3#__DBI0#
DBI2#__DBI1#
DBI1#__DBI2#
DBI0#__DBI3#
RAS#__CAS#
CAS#__RAS#
CKE#
CK#
CK
CS#__WE#
WE#__CS#
ZQ
SEN
RESET#
MF
Vpp_NC
Vpp_NC1
VREFD1
VREFD2
VREFC
ABI#
+MVDD +MVDD
6.3V1uFC2214
6.3V1uFC2215
6.3V1uFC2216
6.3V1uFC2217
6.3V0.1uFC2220
6.3V0.1uFC2221
6.3V0.1uFC2222
6.3V1uFC2010
6.3V1uFC2011
6.3V1uFC2012
6.3V1uFC2013
6.3V1uFC2014
6.3V1uFC2015
6.3V1uFC2016
6.3V1uFC2017
6.3V0.1uFC2020
6.3V0.1uFC2021
6.3V0.1uFC2022
6.3V0.1uFC2023
6.3V0.1uFC2024
6.3V0.1uFC2025
6.3V0.1uFC2026
6.3V0.1uFC2027
6.3V10uFC 2030
6.3V1uFC2210
6.3V1uFC2211
6.3V1uFC2212
D D
1
2
6.3V1uFC2213
6.3V0.1uFC2223
6.3V0.1uFC2224
6.3V0.1uFC2225
3
+MVDD +MVDD
6.3V1uFC2410
6.3V1uFC2411
6.3V1uFC2412
6.3V1uFC2413
6.3V1uFC2414
6.3V1uFC2415
6.3V0.1uFC2226
6.3V0.1uFC2227
6.3V10uFC 2230
6.3V1uFC2416
5
6
7
8
6.3V0.1uFC2623
6.3V0.1uFC2624
6.3V0.1uFC2625
6.3V0.1uFC2626
6.3V1uFC2417
6.3V0.1uFC2420
6.3V0.1uFC2421
6.3V0.1uFC2422
6.3V0.1uFC2423
6.3V0.1uFC2424
6.3V0.1uFC2425
6.3V0.1uFC2426
6.3V0.1uFC2427
6.3V10uFC 2430
6.3V1uFC2610
6.3V1uFC2611
6.3V1uFC2612
6.3V1uFC2613
6.3V1uFC2614
6.3V1uFC2615
6.3V1uFC2616
6.3V1uFC2617
6.3V0.1uFC2627
6.3V0.1uFC2620
6.3V10uFC 2630
6.3V0.1uFC2621
6.3V0.1uFC2622
4
Page 5
1
8
8
8
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
(5) TOBAGO GPIO MLPS PLL XTAL
U1E
+3.3V_BUS
+1.8V
A A
C
C
C
B B
+1.8V
SCL/SDA BUS:
I2C ADRS
R50
3.24K
1%
PS_0
R51
C50
5.62K
0.082uF
1%
16V
R54
4.53K
1%
PS_2
R55
C52
4.99K
0.68uF
1%
4V
DEVICE
AD5274 - DIGIT AL POT FOR MVDD0x5C
+1.8V
R52
8.45K
1%
PS_1
R53
C51
2K
0.082uF
1%
16V
DNI
+1.8V
R56
4.99K
1%
DNI
PS_3
C53
R57
0.68uF
4.75K
4V
1%
+1.8V
R2 1K 5%
+1.8V
17,1
OUT
1,17
BI
15,17
OUT
15,17
BI
11,15
OUT
11,15
IN
11
OUT
DNIR1 1K 5%
PS_0
PS_1
PS_2
PS_3
G_SMBCLK
G_SMBDAT
SCL
SDA
SVC
SVD
SVT
TEST_PG
BC37
BC39
BD37
C1
1uF
BD39
6.3V
AV34
AV36
AW34
C2
1uF
AW36
6.3V
BE43
BC41
BE41
BG41
AL51
AL53
BD21
BC21
BD17
BD19
BC17
BC49
BC48
BM20
BE19
BE39
BE15
BH43
BH27
BE23
BE17
BH25
BH29
BE21
C C
U1G
+1.8V
+0.95V
+1.8V
A
A
A
D D
120R
B1
120R
B2
220R
B3
1
C15
4.7uF
6.3V
8
8
8
+SPLL_PVDD
C11
C12
C10
1uF
0.1uF
4.7uF
6.3V
6.3V
6.3V
+SPLL_VDDC
C13
C14
1uF
0.1uF
6.3V
6.3V
+MPLL_PVDD
C18
C16
4.7uF
6.3V
DNI
C19
C17
1uF
0.1uF
4.7uF
6.3V
6.3V
6.3V
7
7
7
2
PART 7 OF 16
AW23
SPLL_PVDD
AV23
SPLL_PVSS
AW25
SPLL_VDDC
PLLS XTAL
AV21
MPLL_PVDD
AV20
MPLL_PVDD
SPLL_CLKTEST A
SPLL_CLKTEST B
PLL_ANALOG_IN
PLL_ANALOG_OUT
BONAIRE
XO_IN2
BH50
XO_IN2
XO_IN
BH52
XO_IN
XTALIN
BJ53
XTALIN
XTALOUT
BJ51
XTALOUT
CLKTESTA
BD15
CLKTESTB
BC15
PLL_ANALOGIN
BD23
PLL_ANALOGOUT
BC23
MAKE SURE THEY ARE ACCESSI BLE
AVOID NOISY AREA
VDDR3
VDDR3
VDDR3
VDDR3
VDD_CT
VDD_CT
VDD_CT
VDD_CT
MLPS_0
MLPS_1
MLPS_2
MLPS_3
SMBCLK
SMBDAT
SCL
SDA
GPIO_SVC
GPIO_SVD
GPIO_SVT
DDCVAGCLK
DDCVGADATA
TEST_PG
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
R24 33R 5%
R26 33R 5%
R25 33R 5%
R27 0R 5%
C30 0.1uF 6.3V
C31 0.1uF 6.3V
6
6
6
3
OPTIONAL CLOCK C HIP
KEEP THE CLOCK PATH
AS SHORT AS POSSIBLE
PART 5 OF 16
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5_REGHOT_AC_BATT
GPIO_6_TACH
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15
GPIO_16
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20
GPIO_21
GPIO_22_ROMCSB
GPIO_29
GPIO
GPIO_30
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD 4
GENERICF_H PD5
GENERICG_HPD 6
HPD1
DIGON
VARY_BL
CLKREQB
WAKEB
NC_IDSC_AN ALOGOUT
NC_IDSC_I L0
NC_IDSC_PW M0
NC_IDSC_PW M1
NC_IDSC_C MON
NC_DSM_0
NC_DSM_1
NC_PS_4
BONAIRE
FOR SMALLER SIZ E - 502N270000G
C22 18pF 50V
CLK_100M
CLK_27M
3
1
R28
1M
1%
R30 51.1R 1%
R31 51.1R 1%
TP30
BG27
BH23
BN19
BG29
BE27
BH35
BC29
BA45
BG39
BH37
BH39
BE29
BC31
BD31
BK28
BG31
BG37
BD29
BK36
BC27
BH33
BH31
BH41
BE25
BG25
BE45
BC45
BG23
BL19
BK42
BA53
AW49
BM44
AW45
AW47
BK44
CEC
J47
AK52
G48
F47
F45
G45
F43
BG33
BG35
BC43
10
XTALOUT
5
100M_OUT
9
27M_OUT
C24 18pF 50V
4
Y2
27.000MHz
2
R29
0R
5%
C25 18pF 50V
16.2K 1%R32
DNI
GPIO_0
GPIO_2
GPIO_3
GPIO_5_VRHOTB
GPIO_6_TACH
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_14_HPD2
GPIO_15
GPIO_18_HPD3
GPIO_19_CTF
GPIO_22_ROMCSB
GENERICA
GENERICG_HPD 6
HPD1
CEC
G_CLKREQB
Y1
123
4
27.000MHz
U20
SL16020DC
5
5
5
4
XTALIN
VDD_100M
VDD_27M
SS_SEL0
SS_SEL1
GND_100M
GND_27M
GND_PAD
1 2
C7
1uF
1 2
6.3V
TP1
TP2
TP3
DNIR3 221R 1%
0.1uF 6.3V DNIC8
+3.3V_BUS
120R
120R
+3.3V_BUS
R20
R21
5.1K
5.1K
5%
5%
DNI
DNI
R22
R23
5.1K
5.1K
5%
5%
DNI
DNI
+3.3V_BUS
R5
10K
5%
ROMSO
ROMSI
ROMSCK
ROMCSB
MR7 10K 5%
MR8 10K 5%
MR9 10K 5%
NS1
+VDDR4
AV38
AV39
NS2
GENLK_VSYNC
DVPCLK
DVPCNTL_0
DVPCNTL_2
AW38
AW39
BD33
BC33
BC35
BD35
BH9
BM18
BK18
BG9
BL11
BN11
VREFG
BK20
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
TOBAGO GPIO MLPS PLL XTAL
TOBAGO GPIO MLPS PLL XTAL
TOBAGO GPIO MLPS PLL XTAL
SHEET:
SHEET:
SHEET:
Mon Nov 24 11:06:54 2014
Mon Nov 24 11:06:54 2014
Mon Nov 24 11:06:54 2014
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
+3.3V_BUS
3
2
5
6
1
+3.3V_BUS
DNI
DNI
DNI
U1F
VDDR4
VDDR4
VDDR4
VDDR4
SWAPLOCKA
SWAPLOCKB
GENLK_CLK
GENLK_VSYNC
DVPCLK
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
MVP_DVOCNTL_0
MVP_DVOCNTL_1
VREFG
5 19
5 19
5 19
105-C913xx-00B
105-C913xx-00B
105-C913xx-00B
3
3
3
VIDEO BIOS
FIRMWARE
U11
WP
SO
SI
SCK
CE
PM25LD010C-SCE
R7 10K 5%
R8 10K 5%
R9 10K 5%
PART 6 OF 16
DVP
BONAIRE
OF
OF
OF
6
VDD
HOLD
GND
+3.3V_BUS
8
7
4
PIN STRAPS
DNI
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23
C4
0.1uF
6.3V
HSYNC
VSYNC
BH11
BG11
BH13
BG13
BH15
BG15
BH17
BG17
BH19
BG19
BH21
BG21
BM12
BK12
BN13
BL13
BM14
BK14
BN15
BL15
BM16
BK16
BN17
BL17
GENLK_VSYNC
BIOS1
BIOS
REV:
REV:
REV:
OUT
OUT
1.0
1.0
1.0
HSYNC = AUD[1], VSYNC = AUD[ 0]
[00] NO AU DIO FU NCTION
6
[01] AUDI O FOR D P ONLY
[10] AUDI O FOR D P AND H DMI IF DONGLE IS DETECTED
[11] AUDI O FOR BOTH DP AND HDMI
6
HDMI MUST ONLY BE ENABLED ON SYSTEMS THAT ARE LEGALLY
ENTITLED. IT IS THE RESPONSIBI LITY OF THE SYSTEM DESIGN ERS
TO SUPPORT THIS FEATUR E.
CEC_DIS
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
C
C
C
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
information incl uded herein.
information incl uded herein.
information incl uded herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
DD
DD
DD
C
C
C
BB
BB
BB
A
A
A
1
1
1
8
TP10
17
OUT
TP11
12
IN
16
IN
DP
8
IN
TP12
HDMI
8
IN
16
OUT
TP15
DVI-I
9
IN
DVI-D
7
IN
TP16
XIN_OSCXOUT_OSC
1
C23 18pF 50V
VDD_100M
4
VDD_27M
8
SS_SEL0
7
SS_SEL1
3
6
2
11
+3.3V_BUS
+1.8V
C20
0.1uF
6.3V
RP1A 33R 5%
RP1B 33R 5%
RP1C 33R 5%
RP1D 33R 5%
R10
10K
5%
DNI
C5
1uF
6.3V
+1.8V
B20
B21
C21
0.1uF
6.3V
1 8
2 7
3 6
4 5
TP17
C6
1uF
6.3V
R4 110R 1% DNI
4
4
4
5
Page 6
1
8
8
8
(6) TOBAGO DAC
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
A A
U1H
+1.8V
+1.8V
C
C
C
B B
120R
B1500
120R
B1501
+VDD1DI
C1500
1uF
6.3V
+AVDD
C1502
1uF
6.3V
R1500 1%499R
C1501
0.1uF
6.3V
C1503
0.1uF
6.3V
RSET
BC47
BA47
AR47
AM52
AM50
+5V_VESA
+5V_VESA
VDD1DI
VSS1DI
AVDD
AVSSQ
RSET
U1500B
3 5
74AHCT1G126GW
U1501B
3 5
74AHCT1G126GW
PART 8 OF 16
R1510
150R
1%
R1512
150R
1%
R1514
150R
1%
1
2 4
U1500A
74AHCT1G126GW
1
2 4
U1501A
74AHCT1G126GW
R_DAC
G_DAC
B_DAC
AP50
R
AN51
G
AN53
B
AP52
AVSSN
DAC1
AR49
VSYNC
AU49
HSYNC
6.3V0.1uFC1504
HSYNC
5
OUT
6.3V0.1uFC1505
VSYNC
5
OUT
R1511
150R
1%
R1513
150R
1%
R1515
150R
1%
SEE BOM FOR Q UALIFIED FILTE RS
L1500
0.012uH
L1502
0.012uH
L1504
0.012uH
HSYNC_DAC_B
VSYNC_DAC_B
R_DAC_L
G_DAC_L
L1501
0.012uH
C1510
5pF
50V
L1503
0.012uH
C1512
5pF
50V
L1505
0.012uH
C1514
5pF
50V
C1511
5pF
50V
C1513
5pF
50V
C1515
5pF
50V
5%24RR 1501
C1506
12pF
50V
DNI
5%24RR 1502
C1507
12pF
50V
DNI
R_DAC_F
G_DAC_F
B_DAC_FB_DAC_L
HSYNC_D AC_R
VSYNC_DAC _R
9
OUT
9
OUT
9
OUT
9
OUT
9
OUT
C C
DD
DD
DD
C
C
C
BB
BB
BB
REV:
REV:
REV:
1.0
1.0
1.0
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
C
C
C
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
information incl uded herein.
information incl uded herein.
information incl uded herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
A
A
A
1
1
1
8
OPTIONAL ESD PROTECTION DIODES
ESD5V3U1U-02LRHD1500
12
ESD5V3U1U-02LRHD1501
12
ESD5V3U1U-02LRHD1502
12
ESD8V0R1B-02LRHD1505
12
A
A
A
ESD8V0R1B-02LRHD1506
12
D D
8
8
8
1
R_DAC_F
DNI
G_DAC_F
DNI
B_DAC_F
DNI
HSYNC_DAC_R
DNI
VSYNC_DAC_R
DNI
7
7
7
2
6
6
6
3
5
5
5
4
4
4
4
5
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
TOBAGO DAC
TOBAGO DAC
TOBAGO DAC
SHEET:
SHEET:
SHEET:
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
Mon Nov 24 11:06:54 2014
Mon Nov 24 11:06:54 2014
Mon Nov 24 11:06:54 2014
6 19
6 19
6 19
OF
OF
OF
105-C913xx-00B
105-C913xx-00B
105-C913xx-00B
3
3
3
6
Page 7
1
(7) TOBAGO TMDPAB dDVI
2
3
4
5
6
7
8
A A
+1.8V
C1700
C1701
C1702
C1703
C1704
1uF
1uF
1uF
6.3V
6.3V
6.3V
+0.95V
C1710
C1711
C1712
1uF
1uF
1uF
6.3V
6.3V
6.3V
C1705
1uF
10uF
10uF
6.3V
6.3V
6.3V
C1713
C1714
C1715
1uF
10uF
10uF
6.3V
6.3V
6.3V
B B
DPAB_CALR
1%150RR1700
C C
OPTIONAL ESD PROTECTION DIODES
D D
ESD5V3U1U-02LRHD1700
12
ESD5V3U1U-02LRHD1701
12
D1702 ESD5V3U1U-02LRH
12
ESD5V3U1U-02LRHD1703
12
ESD5V3U1U-02LRHD1704
12
ESD5V3U1U-02LRHD1705
12
ESD5V3U1U-02LRHD1706
12
ESD5V3U1U-02LRHD1707
12
ESD5V3U1U-02LRHD1708
12
ESD5V3U1U-02LRHD1709
12
ESD5V3U1U-02LRHD1710
12
ESD5V3U1U-02LRHD1711
12
ESD5V3U1U-02LRHD1712
12
ESD5V3U1U-02LRHD1713
12
ESD5V3U1U-02LRHD1714
12
ESD5V3U1U-02LRHD1715
12
U1I
PART 9 OF 16
AW42
DP_VDDR
AU44
DP_VDDR
AW43
DP_VDDR
AU42
DP_VDDR
AU43
DP_VDDR
BA42
DP_VDDR
AR44
DP_VDDR
AW44
DP_VDDR
AJ42
DP_VDDC
AJ43
DP_VDDC
AJ44
DP_VDDC
AL42
DP_VDDC
AN42
DP_VDDC
AN43
DP_VDDC
AN44
DP_VDDC
AR42
DP_VDDC
AR43
DP_VDDC
TMDP A/B
BM42
DPAB_CALR
BONAIRE
ABTX2P
DNI
ABTX2N
DNI
ABTX1P
DNI
ABTX1N
DNI
ABTX0P
DNI
ABTX0N
DNI
ABTXCP
DNI
ABTXCN
DNI
ABTX5P
DNI
ABTX5N
DNI
ABTX4P
DNI
ABTX4N
DNI
ABTX3P
DNI
ABTX3N
DNI
DDC4CLK_DVI
DNI
DDC4DAT_DVI
DNI
TX2P_DPA0P
TX2M_DPA0N
TX1P_DPA1P
TX1M_DPA1N
TX0P_DPA2P
TX0M_DPA2N
TXCAP_DPA3P
TXCAM_DPA3N
DDCAUX3P
DDCAUX3N
TX5P_DPB0P
TX5M_DPB0N
TX4P_DPB1P
TX4M_DPB1N
TX3P_DPB2P
TX3M_DPB2N
TXCBP_DPB3P
TXCBM_DPB3N
DDCAUX4P
DDCAUX4N
BL41
BN41
BK40
BM40
BL39
BN39
BK38
BM38
BL37
BN37
BL49
BN49
BK48
BM48
BL47
BN47
BK46
BM46
BL45
BN45
DPA_TX2P
DPA_TX2N
DPA_TX1P
DPA_TX1N
DPA_TX0P
DPA_TX0N
DPA_TXCP
DPA_TXCN
DDC3CLK_HD MI
DDC3DAT_HDMI
DPB_TX5P
DPB_TX5N
DPB_TX4P
DPB_TX4N
DPB_TX3P
DPB_TX3N
6.3V0.1uFC1720
6.3V0.1uFC1721
6.3V0.1uFC1722
6.3V0.1uFC1723
6.3V0.1uFC1724
6.3V0.1uFC1725
6.3V0.1uFC1726
6.3V0.1uFC1727
8
OUT
8
BI
Q1700
1
DVI_EN
9,8
6.3V0.1uFC1728
6.3V0.1uFC1729
6.3V0.1uFC1730
6.3V0.1uFC1731
6.3V0.1uFC1732
6.3V0.1uFC1733
IN
+5V_VESA
R1701
2.2K
5%
5
2N7002
2 3
R1702
2.2K
5%
HPD1
OUT
DPAB_GND
1%499RR1720
1%499RR1721
1%499RR1722
1%499RR1723
1%499RR1724
1%499RR1725
1%499RR1726
1%499RR1727
1%499RR1728
1%499RR1729
1%499RR1730
1%499RR1731
1%499RR1732
1%499RR1733
+3.3V_BUS
Q1701
MMBT3904
2 3
1
5%20KR1703
5%10KR1704
ABTX2P
ABTX2N
ABTX1P
ABTX1N
ABTX0P
ABTX0N
ABTXCP
ABTXCN
ABTX5P
ABTX5N
ABTX4P
ABTX4N
ABTX3P
ABTX3N
DDC4CLK_DVI
DDC4DAT_DVI
HPD_AB_DVI
12
D1716
ESD5V3U1U-02LRH
DNI
J1900B
B2
TMDS_Data2+
B1
TMDS_Data2-
B10
TMDS_Data1+
B9
TMDS_Data1-
B18
TMDS_Data0+
B17
TMDS_Data0-
B23
TMDS_Clock+
B24
TMDS_Clock-
B21
TMDS_Data5+
B20
TMDS_Data5-
B5
TMDS_Data4+
B4
TMDS_Data4-
B13
TMDS_Data3+
B12
TMDS_Data3-
B6
DDC_Clock
B7
DDC_Data
B8
Analog_VSYNC
B16
Hot_Plug_Detect
DVI-D_OVER_DVI -I
STACKED DVI - TOP
+5V_POWER
TMDS_Data0/5_Shield
TMDS_Data1/3_Shield
TMDS_Data2/4_Shield
TMDS_Clock_Shield
GND_(for_+5V)
+5V_VESA
B14
C1740
1uF
16V
SCREW1903
B19
SCREW1904
B11
B3
B22
B15
1
2
3
4
5
6
7
8
Page 8
1
2
3
4
5
6
7
8
(8) TOBAGO TMDPCD DP HDMI
U1J
A A
B B
DPCD_CALR
150R 1%R1800
PART 10 OF 16
TMDP C/D
BM28
DPCD_CALR
BONAIRE
TX2P_DPC0P
TX2M_DPC0N
TX1P_DPC1P
TX1M_DPC1N
TX0P_DPC2P
TX0M_DPC2N
TXCCP_DPC3P
TXCCM_DPC3N
AUX1P
AUX1N
DDC1CLK
DDC1DATA
TX5P_DPD0P
TX5M_DPD0N
TX4P_DPD1P
TX4M_DPD1N
TX3P_DPD2P
TX3M_DPD2N
TXCDP_DPD3P
TXCDM_DPD3N
AUX2P
AUX2N
DDC2CLK
DDC2DATA
BL27
BN27
BK26
BM26
BL25
BN25
BK24
BM24
BK22
BM22
BL23
BN23
BL35
BN35
BK34
BM34
BL33
BN33
BK32
BM32
BK30
BM30
BL31
BN31
DPC_C0P
DPC_C0N
DPC_C1P
DPC_C1N
DPC_C2P
DPC_C2N
DPC_C3P
DPC_C3N
AUX1P
AUX1N
DDC1CLK
DDC1DAT
DPD_TX2P
DPD_TX2N
DPD_TX1P
DPD_TX1N
DPD_TX0P
DPD_TX0N
DPD_TXCP
DPD_TXCN
R1832 0R 5%
61
Q1802B
2N7002DW
2
C1820 0.1uF 6.3V
C1821 0.1uF 6.3V
C1822 0.1uF 6.3V
C1823 0.1uF 6.3V
C1824 0.1uF 6.3V
C1825 0.1uF 6.3V
C1826 0.1uF 6.3V
C1827 0.1uF 6.3V
C1828 0.1uF 6.3V
C1829 0.1uF 6.3V
R1833 0R 5%
C1870 0.1uF 6.3V
C1871 0.1uF 6.3V
C1872 0.1uF 6.3V
C1873 0.1uF 6.3V
C1874 0.1uF 6.3V
C1875 0.1uF 6.3V
C1876 0.1uF 6.3V
C1877 0.1uF 6.3V
R1801 100K 5%
+12V_BUS +12V_BUS
R1807
R1808
10K
10K
5%
34
Q1802A
2N7002DW
5
AUX1_BYPASS_EN
5%
1
2 3
Q1804
2 3
MMBT3904
DVI_EN
9,7
IN
GPIO_14_HPD2
5
OUT
1
Q1805
2N7002
R1870 499R 1%
R1871 499R 1%
R1872 499R 1%
R1873 499R 1%
R1874 499R 1%
R1875 499R 1%
R1876 499R 1%
R1877 499R 1%
DPD_GND
Q1850
1
2N7002
2 3
7
GPIO_18_HPD3
5
OUT
R1802 100K 5%
+3.3V_BUS
Q1801
1
+3.3V_BUS
2 3
2 3
R1803 20K 5%
R1804 10K 5%
R1805 1M 5%
R1806 5.1M 5%
+5V_VESA
R1851
2.2K
5%
1
R1853 20K 5%
R1854 10K 5%
MMBT3904
7
IN
BI
Q1851
MMBT3904
DPC_0P
DPC_0N
DPC_1P
DPC_1N
DPC_2P
DPC_2N
DPC_3P
DPC_3N
AUX1P_DPC
AUX1N_DPC
+3.3V_BUS
HPD_DP
DONGLE_DET_DP
CONFIG2_DP
BTX2P
BTX2N
BTX1P
BTX1N
BTX0P
BTX0N
BTXCP
BTXCN
R1852
2.2K
5%
DDC3CLK_HD MI
DDC3DAT_HDMI
HPD_HDMI
12
10
12
15
17
18
D1717
ESD5V3U1U-02LRH
DNI
13
14
12
D1718
ESD5V3U1U-02LRH
DNI
J1800
1
ML_Lane_0p
3
ML_Lane_0n
4
ML_Lane_1p
6
ML_Lane_1n
7
ML_Lane_2p
9
ML_Lane_2n
ML_Lane_3p
ML_Lane_3n
AUX_CHp
AUX_CHn
Hot_Det
CONFIG 1
CONFIG 2
DP_RECEPTACLE_W/TAB
+5V_VESA
C1880
1uF
10V
DP_PWR
PWR_RTN
GND_2
G1
G2
G3
G4
GND_0
GND_1
GND_3
GND_6
20
19
G1
G2
G3
G4
2
5
8
11
16
DDC3CLK_HDMI
DDC3DAT_HDMI
HPD_HDMI
+3.3V_DP
C1840
C1841
22uF
100uF
6.3V
6.3V
DNI
SCREW1800
SCREW
J1850
BTX2P
1
D2+
2
D2 Shield
BTX2N
3
D2-
BTX1P
4
D1+
5
D1 Shield
BTX1N
6
D1-
BTX0P
7
D0+
8
D0 Shield
BTX0N
9
D0-
BTXCP
10
CK+
11
CK Shield
BTXCN
12
CK-
13
CE Remote
14
NC
15
DDC CLK
16
DDC DATA
17
GND
18
+5V
19
HP DET
HDMI19PM_BLACK-HF
N5Y-19M0061-L06
HDMI_D19_4
C C
F1800
SMD1206P110TFT
8V
SHELL1
SHELL2
+3.3V_BUS
21
23
MEC1
22
20
OPTIONAL ESD PROTECTION DIODES
DPC_0P DPC_0P
DPC_0N DPC_0N
DPC_1P DPC_1P
DPC_1N DPC_1N
DPC_2P DPC_2P
DPC_2N DPC_2N
DPC_3P DPC_3P
DPC_3N DPC_3N
D1802 ESD5V3U1U-02LRH
D1803 ESD5V3U1U-02LRH
D D
D1804 ESD5V3U1U-02LRH
D1800
5
D6Y4
4
7
C
Y3
3
8
GND
GND1
2
9
B
Y2
1
10
A
Y1
RCLAMP0524P DNI
D1801
5
D6Y4
4
7
C
Y3
3
8
GND
GND1
2
9
B
Y2
1
10
A
Y1
DNI
RCLAMP0524P
12
12
12
AUX1P_DPC
DNI
AUX1N_DPC
DNI
DONGLE_DET_DP DONGLE_DET_DP
DNI
BTX2P BTX2P
BTX2N BTX2N
BTX1P BTX1P
BTX1N BTX1N
BTX0P BTX0P
BTX0N BTX0N
BTXCP BTXCP
BTXCN BTXCN
D1852 ESD5V3U1U-02LRH
D1853 ESD5V3U1U-02LRH
D1850
5
D6Y4
4
C
Y3
3
GND
GND1
2
B
Y2
1
A
Y1
RCLAMP0524P
D1851
5
D6Y4
4
C
Y3
3
GND
GND1
2
B
Y2
1
A
Y1
RCLAMP0524P
12
12
7
8
9
10
DNI
7
8
9
10
DNI
DDC3CLK_HD MI
DNI
DDC3DAT_HDMI
DNI
DPC_0P
DPC_0N
DPC_1P
DPC_1N
DPC_2P
DPC_2N
DPC_3P
DPC_3N
AUX1P_DPC
AUX1N_DPC
HPD_DP
CONFIG2_DP
MJ1800
1
ML_Lane_0p
ML_Lane_0n
ML_Lane_1p
ML_Lane_1n
ML_Lane_2p
ML_Lane_2n
ML_Lane_3p
ML_Lane_3n
AUX_CHp
AUX_CHn
Hot_Det
CONFIG 1
CONFIG 2
DP_PWR
PWR_RTN
GND_2
DP_W/GASKET
3
4
6
7
9
10
12
15
17
18
13
14
+3.3V_DP
20
19
G1
G1
G2
G2
G3
G3
G4
G4
2
GND_0
5
GND_1
8
11
GND_3
16
GND_6
OVERLAP WITH J1800
SCREW1850
SCREW
1
2
3
4
5
6
7
8
Page 9
1
8
8
8
2
7
7
7
3
6
6
6
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6
345
345
345
7
2
2
2
8
1
1
1
(9) TOBAGO TMDPEF dDVI
U1K
PART 11 OF 16
A A
TMDP E/F
C
C
C
B B
DPEF_CALR
1%150RR1900
BA49
DPEF_CALR
BONAIRE
C C
OPTIONAL ESD PROTECTION DIODES
ESD5V3U1U-02LRHD1900
12
ESD5V3U1U-02LRHD1901
12
ESD5V3U1U-02LRHD1902
12
ESD5V3U1U-02LRHD1903
12
ESD5V3U1U-02LRHD1904
12
ESD5V3U1U-02LRHD1905
12
ESD5V3U1U-02LRHD1906
12
ESD5V3U1U-02LRHD1907
12
ESD5V3U1U-02LRHD1908
12
ESD5V3U1U-02LRHD1909
12
ESD5V3U1U-02LRHD1910
12
ESD5V3U1U-02LRHD1911
12
ESD5V3U1U-02LRHD1912
12
ESD5V3U1U-02LRHD1913
A
A
A
D D
8
8
8
1
12
ESD5V3U1U-02LRHD1914
12
ESD5V3U1U-02LRHD1915
12
EFTX2P EFTX2P
DNI
EFTX2N
DNI
EFTX1P
DNI
EFTX1N
DNI
EFTX0P
DNI
EFTX0N
DNI
EFTXCP
DNI
EFTXCN
DNI
EFTX5P
DNI
EFTX5N EFTX5N EFTX5N
DNI
EFTX4P
DNI
EFTX4N
DNI
EFTX3P
DNI
EFTX3N
DNI
DDC6CLK_DVI
DNI
DDC6DAT_DVI
DNI
7
7
7
2
TXOUT_L3P
TXOUT_L3N
TX2P_L2P_DPE0P
TX2M_L2N_DPE0N
TX1P_L1P_DPE1P
TX1M_L1N_DPE1N
TX0P_L0P_DPE2P
TX0M_L0N_DPE2N
TXCEP_LP_DPE3P
TXCEM_LN_DPE3N
DDCAUX5P
DDCAUX5N
TXOUT_U3P
TXOUT_U3N
TX5P_U2P_DPF0P
TX5M_U2N_DPF0N
TX4P_U1P_DPF1P
TX4M_U1N_DPF1N
TX3P_U0P_DPF2P
TX3M_U0N_DPF2N
TXCFP_UP_DPF3P
TXCFM_UN_DPF3N
DDCAUX6P
DDCAUX6N
BB52
BB50
BC53
BC51
BD52
BD50
BE53
BE51
BF52
BF50
BE48
BE49
AT52
AT50
AU53
AU51
AV52
AV50
AW53
AW51
AY52
AY50
AR53
AR51
DPE_TX2P
DPE_TX2N
DPE_TX1P
DPE_TX1N
DPE_TX0P
DPE_TX0N
DPE_TXCP
DPE_TXCN
DPF_TX5P
DPF_TX5N
DPF_TX4P
DPF_TX4N
DPF_TX3P
DPF_TX3N
MJ1900
25
3
6
6
6
CASE
1
TMDS_Data2-
2
TMDS_Data2+
3
TMDS_Data2/4_Shield
4
TMDS_Data4-
5
TMDS_Data4+
6
DDC_Clock
7
DDC_Data
8
Analog_VSYNC
9
TMDS_Data1-
10
TMDS_Data1+
11
TMDS_Data1/3_Shield
12
TMDS_Data3-
13
TMDS_Data3+
14
+5V_Power
15
GND_(for_+5V)
16
Hot_Plug_Detect
17
TMDS_Data0-
18
TMDS_Data0+
19
TMDS_Data0/5_Shield
20
TMDS_Data5-
21
TMDS_Data5+
22
TMDS_Clock_Shield
23
TMDS_Clock+
24
TMDS_Clock-
C1
Analog_Red
C2
Analog_Green
C3
Analog_Blue
C4
Analog_HYNC
C5
Analog_GND
C6
Analog_GND#C6
26
CASE#M2
27
CASE#M3
28
CASE#M4
29
CASE#M5
30
CASE#M6
DVI-I_BLACK
EFTX2N EFTX2N
EFTX4N EFTX4N
EFTX4P EFTX4P
DDC6CLK_DVI DDC6CLK_DVI
DDC6DAT_DVI DDC6DAT_DVI
VSYNC_DAC _R VSYNC_D AC_R
EFTX1N EFTX1N
EFTX1P EFTX1P
+5V_VESA +5V_VESA
EFTX3N EFTX3N
EFTX3P EFTX3P
+5V_VESA +5V_VESA
HPD_EF_DVI HPD_EF_DVI
EFTX0N EFTX0N
EFTX0P EFTX0P
EFTX5P EFTX5P
EFTXCP EFTXCP
EFTXCN EFTXCN
R_DAC_F R_DAC_F
G_DAC_F G_DAC_F
B_DAC_F B_DAC_F
HSYNC_D AC_R HSYNC_D AC_R
+5V_POWER
TMDS_Data0/5_Shield
TMDS_Data1/3_Shield
TMDS_Data2/4_Shield
TMDS_Clock_Shield
GND_(for_+5V)
Analog_GND
Analog_GND#C6
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
+5V_VESA
A14
C1940
1uF
16V
A19
A11
A3
A22
A15
C5
C6
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
SCREW1900
SCREW1901
DD
DD
DD
C
C
C
BB
BB
BB
A
A
A
1
1
1
8
6.3V0.1uFC1920
6.3V0.1uFC1921
6.3V0.1uFC1922
6.3V0.1uFC1923
6.3V0.1uFC1924
6.3V0.1uFC1925
6.3V0.1uFC1926
6.3V0.1uFC1927
+12V_BUS
R1905
100K
5%
DVI_EN
7,8
25
CASE
1
TMDS_Data2-
2
TMDS_Data2+
3
TMDS_Data2/4_Shield
4
TMDS_Data4-
5
TMDS_Data4+
6
DDC_Clock
7
DDC_Data
8
Analog_VSYNC
9
TMDS_Data1-
10
TMDS_Data1+
11
TMDS_Data1/3_Shield
12
TMDS_Data3-
13
TMDS_Data3+
14
+5V_Power
15
GND_(for_+5V)
16
Hot_Plug_Detect
17
TMDS_Data0-
18
TMDS_Data0+
19
TMDS_Data0/5_Shield
20
TMDS_Data5-
21
TMDS_Data5+
22
TMDS_Clock_Shield
23
TMDS_Clock+
24
TMDS_Clock-
C1
Analog_Red
C2
Analog_Green
C3
Analog_Blue
C4
Analog_HYNC
C5
Analog_GND
C6
Analog_GND#C6
26
CASE#M2
OUT
+5V_VESA
R1901
2.2K
5%
5
NJ1900
CASE#M3
CASE#M4
CASE#M5
CASE#M6
DVI-I
4
4
4
5
6.3V0.1uFC1928
6.3V0.1uFC1929
6.3V0.1uFC1930
6.3V0.1uFC1931
6.3V0.1uFC1932
6.3V0.1uFC1933
EFTX2P
SINGLE DVI OPTIONSINGLE DVI OPTION
5
5
5
4
Q1900
1
2N7002
C1905
2 3
0.1uF
16V
R1902
2.2K
5%
GENERICG_HPD6
OUT
27
28
29
30
SHEET:
SHEET:
SHEET:
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
1%499RR1920
1%499RR1921
1%499RR1922
1%499RR1923
1%499RR1924
1%499RR1925
1%499RR1926
1%499RR1927
1%499RR1928
1%499RR1929
1%499RR1930
1%499RR1931
1%499RR1932
1%499RR1933
DPEF_GND
+3.3V_BUS
Q1901
1
MMBT3904
2 3
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
TOBAGO TMDPEF dDVI BOTTOM
TOBAGO TMDPEF dDVI BOTTOM
TOBAGO TMDPEF dDVI BOTTOM
Mon Nov 24 11:06:54 2014
Mon Nov 24 11:06:54 2014
Mon Nov 24 11:06:54 2014
9 19
9 19
9 19
105-C913xx-00B
105-C913xx-00B
105-C913xx-00B
3
3
3
6
OF
OF
OF
EFTX2P
EFTX2N
EFTX1P
EFTX1N
EFTX0P
EFTX0N
EFTXCP
EFTXCN
EFTX5P
EFTX5N
EFTX4P
EFTX4N
EFTX3P
EFTX3N
DDC6CLK_DVI
DDC6DAT_DVI
R_DAC_F
6
IN
G_DAC_F
6
IN
B_DAC_F
6
IN
HSYNC_D AC_R
6
IN
VSYNC_DAC _R
6
IN
HPD_EF_DVI
5%20KR1903
5%10KR1904
12
D1719
ESD5V3U1U-02LRH
DNI
1.0
1.0
1.0
REV:
REV:
REV:
J1900A
A2
TMDS_Data2+
A1
TMDS_Data2-
A10
TMDS_Data1+
A9
TMDS_Data1-
A18
TMDS_Data0+
A17
TMDS_Data0-
A23
TMDS_Clock+
A24
TMDS_Clock-
A21
TMDS_Data5+
A20
TMDS_Data5-
A5
TMDS_Data4+
A4
TMDS_Data4-
A13
TMDS_Data3+
A12
TMDS_Data3-
A6
DDC_Clock
A7
DDC_Data
C1
Analog_Red
C2
Analog_Green
C3
Analog_Blue
C4
Analog_HYNC
A8
Analog_VSYNC
A16
Hot_Plug_Detect
DVI-D_OVER_DVI -I
STACKED DVI - BOTTOM
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
information incl uded herein.
information incl uded herein.
information incl uded herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
Page 10
1
15ci203
8
8
8
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
(10) TOBAGO POWER AND GROUND
U1L
+VDDC
A A
C
C
C
B B
C C
A
A
A
+MVDD
C1202
C1200
1uF
6.3V
C1205
1uF
6.3V
C1210
1uF
6.3V
C1215
1uF
6.3V
C1220
1uF
6.3V
C1225
1uF
6.3V
C1230
1uF
6.3V
C1235
1uF
6.3V
C1240
1uF
6.3V
C1245
1uF
6.3V
C1250
1uF
6.3V
C1300
1uF
6.3V
C1305
1uF
6.3V
C1310
10uF
6.3V
C1203
C1201
1uF
6.3V
C1206
1uF
6.3V
C1211
1uF
6.3V
C1216
1uF
6.3V
C1221
1uF
6.3V
C1226
1uF
6.3V
C1231
1uF
6.3V
C1236
1uF
6.3V
C1241
1uF
6.3V
C1246
1uF
6.3V
C1251
1uF
6.3V
C1301
1uF
6.3V
C1306
1uF
6.3V
C1204
1uF
1uF
1uF
6.3V
6.3V
6.3V
C1207
C1208
C1209
1uF
1uF
1uF
6.3V
6.3V
6.3V
C1212
C1213
C1214
1uF
1uF
1uF
6.3V
6.3V
6.3V
C1217
C1218
C1219
1uF
1uF
1uF
6.3V
6.3V
6.3V
C1222
C1223
C1224
1uF
1uF
1uF
6.3V
6.3V
6.3V
C1227
C1228
C1229
1uF
1uF
1uF
6.3V
6.3V
6.3V
C1232
C1233
C1234
1uF
1uF
1uF
6.3V
6.3V
6.3V
C1237
C1238
C1239
1uF
1uF
1uF
6.3V
6.3V
6.3V
C1242
C1243
C1244
1uF
1uF
1uF
6.3V
6.3V
6.3V
C1247
C1248
C1249
1uF
1uF
1uF
6.3V
6.3V
6.3V
C1252
1uF
6.3V
C1303
C1304
C1302
1uF
1uF
1uF
6.3V
6.3V
6.3V
C1308
C1309
C1307
1uF
1uF
1uF
6.3V
6.3V
6.3V
C1312
C1311
1uF
1uF
6.3V
6.3V
D D
8
8
8
1
7
7
7
2
PART 12 OF 16
AA15
VDDC
AA16
VDDC
AJ34
VDDC
AA23
VDDC
AA25
VDDC
AA29
VDDC
AA31
VDDC
AA34
VDDC
AA38
VDDC
AA39
VDDC
AC16
VDDC
AC18
VDDC
AE25
VDDC
AC20
VDDC
AC21
VDDC
AC33
VDDC
AC34
VDDC
AC27
VDDC
AC36
VDDC
AC38
VDDC
AE16
VDDC
AE18
VDDC
AA27
VDDC
AE20
VDDC
Y20
VDDC
AA20
VDDC
AE34
VDDC
AJ27
VDDC
AE36
VDDC
AE38
VDDC
AG16
VDDC
AG18
VDDC
AG21
VDDC
AG20
VDDC
AG27
VDDC
AE29
VDDC
AG34
VDDC
AG33
AG36
AG38
AL16
AL34
AJ16
AJ23
AJ25
AJ29
AJ31
AJ38
AE23
AE31
AJ15
AL27
AJ20
AL23
AL25
AL29
AL31
AL38
AL20
AJ39
AN15
AN18
AP20
AN23
AN25
AN29
AN31
AP34
F7
G15
AE9
W7
AJ9
W11
AW11
AR7
AU9
L39
AW7
BA9
BC7
L11
J13
N9
J17
G19
J21
G23
J25
G27
J29
G31
J33
G35
J37
G39
G43
J41
L19
J9
L27
L35
AA9
U9
AN9
R7
AC7
AG7
AL7
AG11
AR11
G6
BE6
BC11
POWER1
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
BONAIRE
U1M
PART 13 OF 16
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
POWER 2
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
BONAIRE
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
FB_VDDC
FB_VSSC
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
FB_VDDCI
FB_VSSCI
6
6
6
3
AN36
AN39
AP15
AP18
AP21
AP23
AP25
AP29
AP31
AP33
AP36
AP39
AT15
AT18
AT21
AE21
AT25
AT29
AE33
AT33
AT36
AT39
R15
R18
AE15
R21
R36
R25
R29
R33
AE39
R39
T16
T18
T21
T23
T25
T29
T31
T33
T36
T38
V16
V18
T20
V23
V25
V29
V31
T34
V36
V38
V15
Y16
Y27
Y23
Y25
Y29
Y31
Y34
Y38
V39
AV18
FB_VDDC
AW18
FB_VSSC
AA12
AC12
AE12
AG12
AJ12
AL12
AN12
AR12
AU12
M13
M15
M17
M19
M21
M23
M25
M27
M29
M31
M33
M35
M37
M39
AW12
N12
R12
U12
W12
BB13
BC13
BE13
AW15
FB_VDDCI
AW16
FB_VSSCI
C1261
C1262
C1260
22uF
22uF
22uF
4V
4V
4V
C1266
C1267
C1265
22uF
22uF
22uF
4V
4V
4V
11,17
IN
11,17
IN
C1401
C1402
C1400
1uF
1uF
1uF
6.3V
6.3V
6.3V
C1406
C1407
C1405
1uF
1uF
1uF
6.3V
6.3V
6.3V
C1411
C1410
22uF
22uF
4V
4V
11,17
IN
17
IN
5
5
5
4
+VDDC
C1263
C1264
22uF
22uF
4V
4V
+VDDCI
C1403
C1404
1uF
1uF
6.3V
6.3V
C1408
C1409
1uF
1uF
6.3V
6.3V
C1412
1uF
6.3V
U1N
PART 14 OF 16
A11
VSS
L23
VSS
A15
VSS
L41
VSS
A19
VSS
L31
VSS
A23
VSS
K17
VSS
A27
VSS
BB23
VSS
A31
VSS
L13
VSS
A35
VSS
A39
VSS
BB19
VSS
A43
VSS
BG6
VSS
A47
VSS
B50
VSS
A7
VSS
K21
VSS
W9
VSS
AL11
VSS
AA18
VSS
AT31
VSS
AA21
VSS
AA33
VSS
AA36
VSS
AA45
VSS
AA49
VSS
AA5
VSS
AC1
AW27
AC15
AC25
AG23
AC29
AC39
BA51
AC49
AC5
T50
T52
BK10
AV25
R23
AE27
AG31
AC31
R31
AE45
AE49
AE5
AG1
AC9
AG15
AG25
AJ33
AG29
AG39
AW48
AG49
AG5
AU10
AG9
AL15
AJ18
AJ21
AL39
AJ36
AJ45
AJ49
AJ5
AB52
GND 1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BONAIRE
AL1
VSS
AL9
VSS
AL18
VSS
AL21
VSS
AC23
VSS
AL33
VSS
AL36
VSS
BL29
VSS
AL49
VSS
AW5
VSS
AJ10
VSS
AR9
VSS
AN16
VSS
AN21
VSS
AN27
VSS
AN33
VSS
AN38
VSS
BA48
VSS
AN5
VSS
AP16
VSS
AN20
VSS
AP27
VSS
AN34
VSS
AP38
VSS
AB50
VSS
AR1
VSS
AW9
VSS
AN45
VSS
BE31
VSS
AR5
VSS
AT16
VSS
AT20
VSS
R27
VSS
AT34
VSS
AT38
VSS
G49
VSS
AE10
VSS
D4
VSS
AN49
VSS
AU5
VSS
AV15
VSS
AV16
VSS
AV33
VSS
AW1
VSS
BC9
VSS
BB41
VSS
BE5
VSS
B4
VSS
BN7
VSS
BC6
VSS
BA5
VSS
R11
VSS
BC1
VSS
BM10
VSS
BE37
VSS
BC5
VSS
BB21
VSS
BB17
VSS
BJ27
VSS
BJ29
VSS
BB31
VSS
BB33
VSS
BB35
VSS
BB37
VSS
BE33
VSS
BM4
VSS
BB15
VSS
BG43
VSS
AW33
VSS
BG5
VSS
BL9
VSS
BG1
VSS
BE11
VSS
U1O
PART 15 OF 16
BH7
VSS
BE9
VSS
BJ11
VSS
BJ13
VSS
BJ15
VSS
BJ5
VSS
BJ7
VSS
BJ9
VSS
BK2
VSS
E5
VSS
D52
VSS
D2
VSS
E11
VSS
E13
VSS
E15
VSS
E17
VSS
E19
VSS
E21
VSS
E23
VSS
E25
VSS
E27
VSS
E29
VSS
E31
VSS
E33
VSS
E35
VSS
E37
VSS
E39
VSS
E41
VSS
E43
VSS
E45
VSS
E47
VSS
E49
L5
E7
E9
G1
AW29
J43
G5
L15
N11
G53
J49
J5
K50
K52
L45
AN10
J15
BA11
J19
R9
J23
K25
K33
BB39
J31
AV27
J35
AV29
J39
L1
J11
AU47
K29
L49
AL5
L9
K37
N45
N49
N5
BM36
BG51
GND 2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BONAIRE
R1
VSS
AA10
VSS
R16
VSS
AT27
VSS
R20
VSS
R34
VSS
R38
VSS
AL43
VSS
BG53
VSS
AV31
VSS
AW31
VSS
R49
VSS
R5
VSS
T15
VSS
V20
VSS
T27
VSS
V34
VSS
T39
VSS
BE7
VSS
U10
VSS
U45
VSS
U49
VSS
U5
VSS
Y15
VSS
V21
VSS
V27
VSS
V33
VSS
Y39
VSS
W1
VSS
AC11
VSS
R43
VSS
W49
VSS
W5
VSS
J51
VSS
Y18
VSS
AT23
VSS
Y21
VSS
Y33
VSS
Y36
VSS
J27
VSS
BJ25
VSS
BL21
VSS
BE35
VSS
BA43
VSS
BK50
VSS
BK52
VSS
BJ17
VSS
BJ19
VSS
BJ21
VSS
BJ23
VSS
BB25
VSS
BB27
VSS
BB29
VSS
BJ31
VSS
BJ33
VSS
BJ35
VSS
BJ37
VSS
BJ39
VSS
BJ41
VSS
BJ43
VSS
BJ45
VSS
BJ49
VSS
BM50
VSS
BN43
VSS
BN29
VSS
BL43
VSS
BJ47
VSS
BN21
VSS
AR45
VSS
AU45
VSS
DD
DD
DD
C
C
C
BB
BB
BB
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
1.0
1.0
1.0
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
C
C
C
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
information incl uded herein.
information incl uded herein.
information incl uded herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
A
A
A
1
1
1
8
4
4
4
5
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
TOBAGO POWER GND
TOBAGO POWER GND
TOBAGO POWER GND
SHEET:
SHEET:
SHEET:
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
Mon Nov 24 11:06:54 2014
Mon Nov 24 11:06:54 2014
Mon Nov 24 11:06:54 2014
10 19
10 19
10 19
OF
OF
OF
105-C913xx-00B
105-C913xx-00B
105-C913xx-00B
3
3
3
6
REV:
REV:
REV:
Page 11
1
15ci203
8
8
8
(11) VDDC_VDDCI_I
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
+5V
VDDC_UG1
VDDC_PH1
VDDC_LG1
VDDC_LG2
VDDC_PH2
VDDC_UG2
C618
R662
C625
5%0R
25V
R520
1K
R521
1K 1%
C641
1%910K
25V
DNI
4
2.2R 5%
R624
5%2.2R
1%
50V4.7pF
R663
1%19.1K
C502
0.47uF
16V
R633
C500
C501
2.2uF
2.2uF
10V
10V
DNI
48
50
51
U601
1
UGATE2
2
BOOT2
3
PWM3
4
TONSET
5
ISEN2P
6
ISEN2N
7
ISEN1N
8
ISEN1P
9
ISEN3P
10
ISEN3N
11
VSEN
12
FB
13
COMP
C640
270pF 50V
R628
21.5K
R522
0R 5%
+3.3V_BUS +1.8V
3 5
PVCC
LGATE252PHASE2
RGND15IMON16V06417IMONA18VDDIO19PWROK20SVC21SVD22SVT23OFS24OFSA25SET126SET2
14
R623
U590B
NC7SZ08P5X
VDDCI_THERM_P
1%
8.06K
R646
20.5K
1%
VDDCI_THERM_N
2.2R
C590
0.1uF
16V
VDDC_PWROK
1%
VDDCI_LG
12
OUT
VDDCI_PH1
12
OUT
VDDCI_UG
12
C646
C626
0.22uF
0.22uF
25V
25V
R501
R500
2.2R
2.2R
5%
5%
40
41
42
43
44
46
47
BOOT1
PHASE149LGATE1
UGATE1
R631
5%
PWMA2
BOOTA1
PHASEA145LGATEA1
UGATEA1
TONSETA
12
OUT
12
OUT
C622
2.2uF
10V
OUT
R502
R503
1%140K
5%4.7R
C611
1uF
16V
R511
39
PGOOD
PGOODA
ISENA1P
ISENA1N
ISENA2N
ISENA2P
TH
53TH54TH55TH56
VSENA
COMPA
IBIAS
OCP_L
EN
FBA
VCC
RT8880AGQW
C643
0.1uF
10V
0R 5%
R512
38
0R
R513
37
0R 5%
36
R523
35
34
33
32
31
30
R626
29
100K 1%
28
+VCC5
27
OCP_L
+VCC5
R630
20K
1%
DNI
R650
0R
5%
R620
0R
5%
SVT
SVD
SVC
+VDDC_I_VIN
5%
1%1K
158K
R629
20K
1%
R647
0R
5%
R645
0R
5%
OUT
OUT
OUT
+3.3V_BUS
R514
10K
1%
C505
C627
50V1.5pF
R642
R643
1%
R618
2.2R 5%
C642
2.2uF
10V
R515
0R
C621
0.1uF
10V
5
15,5
5,15
FB_VDDCI
10,17
IN
VDDCI_LOC_P
12
IN
VDDC_I_PGOOD
VDDC_I_EN
VDDCI_ISEN P1
VDDCI_ISEN N1
16V0.1uF
0R 5%
1%10.5K
R627
10K
1%
+5V
DNI
C644
0.22uF
25V
+1.8V
R516
4.7K
5%
5%
+VCC5
R659
120K
1%
R622
4.99K
1%
R613
13.3K
1%
R637
909R
1%
R505
R506
15
OUT
15
OUT
12
OUT
12
OUT
R634
1%
10K
R524
0R 5%
R639
R640
10K 1%
C628
82pF
50V
R635
412K
1%
R632
20.5K
1%
R636
475R
1%
R610
5.1R
5%
A A
+VDDC_I_VIN
4.7R 5%
R525
+5V
R698
C
C
C
B B
C C
A
A
A
10K 1%
R641
FB_VDDC
10,17
IN
VDDC_LOC_P
FB_VSSC
10,17
IN
VDDC_LOC_N
VDDCI_LOC_N
12
IN
VDDC_THERM_P
VDDC_THERM_N
PERSTB_BUF
1,2,16
IN
VDDC_I_PGOOD
R611
1%10K
1%10K
R621
0R 5%
R612
110K
1%
C604
1uF
16V
0.22uF
VDDC_ISENP2
DNI
VDDC_ISENN 2
DNI
VDDC_ISENN 1
VDDC_ISENP1
C503
C504
0.1uF 16V
16V
0.1uF
R517
0R
5%
R649
10K 1%
C645
50V
82pF
R660
10K
1%
DNI
0.22uF
R625
5%0R
R504
100R 5%
R656
5%0R
R654
5%100R
R518
R655
5%100R
R651
0.5%11K
1%14K
R648
17.4K
1%
R519
5%0R
R590
U590A
1
2
NC7SZ08P5X
+VDDC_I_VIN
5%0R
5%100R
VDDC_UG1
VDDC_PH1
VDDC_LG1 VDDC_LG1_FET
+5V
VDDC_THERM_P
VDDC_THERM_N
VDDC_UG2
VDDC_PH2
VDDC_LG2 VDDC_LG2_FET
D D
8
8
8
1
7
7
7
2
6
6
6
3
5
5
5
4
4
4
4
5
INPUT FILTER & INPUT BULK CAPS LOCATED ON PWR MGT PAGE
C542
C543
C544
C545
10uF
10uF
16V
16V
R507
R508
5%0R
VDDC_LG1_FET
OUT
C558
C559
10uF
10uF
16V
16V
R509
R510
5%
VDDC_LG2_FET
OUT
Mon Nov 24 11:06:56 2014
Mon Nov 24 11:06:56 2014
Mon Nov 24 11:06:56 2014
11 19
11 19
11 19
C546
0.1uF
16V
C560
0.1uF
16V
105-C913xx-00B
105-C913xx-00B
105-C913xx-00B
3
3
3
10uF
10uF
16V
16V
DNI
DNI
0R 5%
C556
C557
10uF
10uF
16V
16V
DNI
DNI
0R 5%
0R
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
VDDC_VDDCI_I
VDDC_VDDCI_I
VDDC_VDDCI_I
SHEET:
SHEET:
SHEET:
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
567
4
Q510
NTMFS4927N
123
5
R529
1R
5%
DNI
Q511
NTMFS4983NF
4
12
123
C506
3300pF
50V
DNI
PLACE CLOSE TO THE VDDC INDUCTOR (L510&L520)
567
4
Q520
NTMFS4927N
123
5
R530
1R
5%
DNI
Q521
NTMFS4983NF
4
12
123
C507
3300pF
50V
DNI
OF
OF
OF
6
REV:
REV:
REV:
OVERLAP L510,ML510
12
NS500
R570
1%1.5K
OVERLAP L520,ML520
12
NS501
R575
1%1.5K
1.0
1.0
1.0
ML510
DNI
0.36uH
L510
0.36uH
12
NS505
C553
16V
0.47uF
R527
VDDC_ISENN 1
1.5K
1%
VDDC_ISENP1
R572
100K
1%
DNI
ML520
0.36uH
L520
0.36uH
12
NS506
C567
16V0.47uF
R528
VDDC_ISENN 2
1.5K 1%
VDDC_ISENP2
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
C
C
C
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
information incl uded herein.
information incl uded herein.
information incl uded herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
+
C584
820uF
2.5V
C547
C548
0.1uF
22uF
16V
4V
C561
C562
0.1uF
22uF
16V
4V
+
C585
820uF
2.5V
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
R581
100R
5%
NS507
1 2
NS508
1 2
DD
DD
DD
+VDDC
C549
C550
C551
22uF
22uF
22uF
4V
4V
4V
+
+
C554
C555
820uF
820uF
2.5V
2.5V
C
C
C
C563
C564
C565
22uF
22uF
22uF
4V
4V
+
C568
820uF
2.5V
VDDC_LOC_P
VDDC_LOC_N
4V
+
C569
820uF
2.5V
1
1
1
8
BB
BB
BB
A
A
A
Page 12
1
8
8
8
(12) VDDC_VDDCI_II
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
A A
+VDDC_I_VIN
INPUT FILTER & INPUT BULK CAPS LOCATED ON PWR MGT PAGE
C526
C527
C528
C529
C530
0.1uF
2.2uF
10uF
16V
16V
16V
DNI
VDDCI_UG
11
IN
VDDCI_PH1
11
C
C
C
B B
IN
VDDCI_LG
11
IN
VDDCI_THERM_P
11
IN
VDDCI_THERM_N
11
IN
C531 C532
10uF
10uF
10uF
16V
R563
0R 5%
R564
0R
16V
5%
VDDCI_LG1_FET
0.1uF
16V
4
4
567
123
123
OVERLAP L551,ML551,NL551
Q550
NTMFS4927N
5
R531
1R
5%
Q551
NTMFS4983NF
NL551
DNI
0.33uH
ML551
DNI
0.33uH
L551
0.33uH
12
NS502
R565
DNI
C508
3300pF
50V
DNI
12
C534
C535
C536
0.1uF
22uF
22uF
16V
4V
NS503
C539
1%1.91K
16V0.47uF
R526
1%1.05K
VDDCI_ISEN N1
VDDCI_ISEN P1
R567
100K
1%
4V
11
OUT
11
OUT
+VDDCI
C537
C538
22uF
22uF
4V
4V
NS504
1 2
VDDCI_LOC_P
+
+
C540
C541
R566
560uF
560uF
100R
2.5V
2.5V
5%
NS509
1 2
VDDCI_LOC_N
11
OUT
11
OUT
J500
HEADER_1X2
16V
DNI
PLACE CLOSE TO THE VDDCI INDUCTOR
+1.8V
1
2
PLACE @ HOT SPOT
C600
R606
0.01uF
13.3K
50V
1%
130C
R608
10K
1%
R599
10K 1%
R609
C601
8.25K
0.01uF
1%
50V
R607
2.49K
1%
R603
100K
1%
+3.3V_BUS
C602
0.1uF
16V
R600
1%
2M
5
3
V+
4
V-
1
U504
AP331AWG
2
VR TEMPERA TURE PROTECTION
R601
10K
1%
GPIO_5_VRHOTB
5
OUT
DD
DD
DD
C
C
C
MQ5X1 PARTS ADDED FOR FOOTPRINT COMPATIBILITY WITH MULTIPLE VENDORS.
OVERLAP WITH RESPECTIVE Q5X1.
C C
VDDC_LG1_FET VDDC_LG2_FET
VDDC_LG1_FET
11
IN
VDDC_PH1 VDDC_PH2
56789
MQ511
BSC010NE2LS
4
123
11
IN
VDDC_LG2_FET
56789
MQ521
VDDCI_LG1_FET
BSC010NE2LS
4
123
VDDCI_PH1
56789
MQ551
BSC010NE2LS
4
123
BB
BB
BB
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
1.0
1.0
1.0
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
C
C
C
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
information incl uded herein.
information incl uded herein.
information incl uded herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
A
A
A
1
1
1
8
4
4
4
5
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
VDDC_VDDCI_II
VDDC_VDDCI_II
VDDC_VDDCI_II
SHEET:
SHEET:
SHEET:
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
Mon Nov 24 11:06:56 2014
Mon Nov 24 11:06:56 2014
Mon Nov 24 11:06:56 2014
12 19
12 19
12 19
OF
OF
OF
105-C913xx-00B
105-C913xx-00B
105-C913xx-00B
3
3
3
6
REV:
REV:
REV:
A
A
A
D D
8
8
8
1
7
7
7
2
6
6
6
3
5
5
5
4
Page 13
(13) MVDD
1
8
8
8
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
A A
+MVDD_VIN
C701
C702
C711
C712
10uF
10uF
10uF
16V
16V
16V
DNI
DNI
R704
2.2R
5%
D700
DNI
C
C
C
B B
C707
1uF
16V
MVDD_EN
15
OUT
MVDD_FB
15,17
OUT
R_SFT
C706
0.068uF
16V
R703
2.74K
1%
CF_1C_SFT
Cp
C700
220pF
50V
RF_1
12
BAT54KFILM
D701
12
1N4148W
C709
0.015uF
16V
CH_1
C710
150pF
50V
DNI
R705
16.2K
1%
RFB1_1
R706
1.05K 1%
R707
10K 1%
RFB
RFB2 is on BFoard Engineer's page.
Default value is 11.3k for 1.5V.
RFB2 = RFB*(Vref/(Vout-Vref))
10uF
16V
MVDD_PH
C714
0.15uF
16V
C715
0.1uF
16V
R708
1R
1%
U700
NCP1587
CFB1_1
C713
0.0033uF 50V
1
BST
2
TG
3
GND
4
BG
R709
15K
1%
8
PHASE
7
COMP/DIS_L
6
FB
5
VCC
567
R710
0R
R711
0R
Q700
4
5%
NTMFS4927N
123
567
Q701
4
5%
NTMFS4935NT1G
123
PLACE Rs AN D Cs
ACROSS QL
L701
1.5uH
R700
1R
5%
C703
470pF
50V
12
DNI
NS700
DNI
R712
100R
5%
C716
C704
0.015uF
10V
C705
22uF
4V
DNI
DNI
0.1uF
10V
12
NS701
R713
0R
5%
+MVDD
+
C717
22uF
4V
+
C718
C719
820uF
820uF
2.5V
2.5V
C C
DD
DD
DD
C
C
C
BB
BB
BB
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
1.0
1.0
1.0
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
C
C
C
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
information incl uded herein.
information incl uded herein.
information incl uded herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
A
A
A
1
1
1
8
4
4
4
5
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
MVDD
MVDD
MVDD
SHEET:
SHEET:
SHEET:
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
Mon Nov 24 11:06:56 2014
Mon Nov 24 11:06:56 2014
Mon Nov 24 11:06:56 2014
13 19
13 19
13 19
OF
OF
OF
105-C913xx-00B
105-C913xx-00B
105-C913xx-00B
3
3
3
6
REV:
REV:
REV:
A
A
A
D D
8
8
8
1
7
7
7
2
6
6
6
3
5
5
5
4
Page 14
1
15ci203
8
8
8
(14) SMALL RAIL REGULATORS
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
A A
1.8V REGULATOR
DD
DD
DD
5V REGULATOR
1
2
3
4
OVERLAP U300 AND MU300
1
2
3
4
PROVIDE 50 TO 70 MM SQ.
COPPER AREA F OR COOLIN G
+12V_BUS
R351
1R
1%
C352
1uF
16V
C350
470pF
50V
DNI
R352
49.9K
1%
DNI
MU300
POK
EN
VIN
CNTL5NC
UP0104PDC8
U300
POK
EN
VIN
VDD5NC
THMPAD
GS7103-A
C354
4.7pF
50V
DNI
8
GND
7
FB
+1.8V
6
VOUT
9
GND
DNI
R301
C300
12.7K
33pF
1%
8
GND
1.8V_FB
7
FB
+1.8V
6
VOUT
9
0.95V_VCC
0.95V_COMP
C375
50V15pF
C373
R374
49.9K
1%
50V470pF
50V
R300
10K
1%
VOUT = VREF x (1 + R301/R300)
VREF = 0.8V
U376
8
PHASE
7
COMP
6
FB
5
VCC
TH_9#
APW7165CKAE
9
0.95V_FB
1
BOOT
2
UGATE
3
GND
4
LGATE
0.95V_UG
0.95V_LG
+1.8V
C303
C301
C302
0.1uF
10uF
10uF
6.3V
6.3V
6.3V
DNI
+3.3V_BUS
C353
C355
10uF
10uF
16V
16V
1.525mm
1.525mm
R360
5.1K
1%
30V
9/8A
Dual N-Channel MOSFET
Q350
8
3
PD1503YVS
1
2
7
6
5
4
0.95V_SWNODE
C361
0.15uF
16V
L380
2.2uH
R371
1R
1%
DNI
C372
100pF
50V
DNI
R357
0R
5%
C379
1uF
16V
R359
R358
0R 5%
5%0R
+12V_BUS
+
C356
330uF
2V
MC78M05CDT
U400
1
IN
OUT
GND
TAB
C400
1uF
2
4
16V
C362
22uF
4V
1.4mm
C363
C364
C365
22uF
22uF
22uF
4V
4V
4V
1.4mm
1.4mm
1.4mm
+5V +5V_VESA
3
C425
1uF
16V
C366
C367
22uF
22uF
4V
4V
1.4mm
1.4mm
F400
200mA
24V
C368
C369
22uF
22uF
4V
4V
1.4mm
1.4mm
NS382
C401
1uF
10V
C
C
C
BB
BB
BB
+0.95V
R370
10R
1%
1.8V_PGOOD
1.8V_EN 1.8V_FB
1.8V_VIN
+5V
+3.3V_BUS
1206 1/2W
1%1RR302
+5V
1%1RR303
1.8V_PGOOD
15
OUT
1.8V_EN
15,1
IN
C304
0.1uF
6.3V
DNI
C
C
C
B B
1.8V_VIN
+5V
C305
C306
10uF
1uF
6.3V
10V
0.95V REGULATOR
C C
0.95V_EN
15
IN
R350
1%1R
A
A
A
D D
8
8
8
1
7
7
7
2
6
6
6
3
R356
1.69K
R377
1%
29.4K
1%
C378
680pF
50V
R354
49.9K
1%
5
5
5
4
4
4
4
5
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SMALL RAIL REGULATORS
SMALL RAIL REGULATORS
SMALL RAIL REGULATORS
SHEET:
SHEET:
SHEET:
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
Thu Jan 08 02:35:31 2015 1.0
Thu Jan 08 02:35:31 2015 1.0
Thu Jan 08 02:35:31 2015 1.0
14 19
14 19
14 19
OF
OF
OF
105-C913xx-00B
105-C913xx-00B
105-C913xx-00B
3
3
3
6
REV:
REV:
REV:
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
C
C
C
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
information incl uded herein.
information incl uded herein.
information incl uded herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
A
A
A
1
1
1
8
Page 15
1
8
8
8
(15) POWER MANAGEMENT
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
1.8V_PGOOD
+3.3V_BUS
R1021
10K
5%
+0.95V
R1034 5%5.1K
+3.3V_BUS
VDDC_I_PGOOD
11
IN
A A
C
C
C
B B
INPUT POWER SEQUENCE
+12V_BUS
CTF_OUT
16,17
IN
R1010
11.3K
1%
R1011
1K
1%
12V_BUS_UP
+3.3V_BUS
R1014
5.11K
1%
INPUT_UP_B
6
Q1010A
2
MMDT3904-7
1
CTF_OUT_B
Q210
1
2.2K 5%R221
MMBT3904
2 3
3
Q1010B
5
MMDT3904-7
C1010
4
0.1uF
16V
MR223 5%0R DNI
5%0RR223
+3.3V_BUS
R1020
10K
5%
1.8V_EN
INTERNAL CTF L ATCH - 1.8V V DDCT REQUIRED
1,14
OUT
BUS RAILS (3.3V /12V UP) -> +1.8 V -> 0.95V
ENABLE THRES HOLD
+1.8V: >1.4 V
+0.95V: FLO AT
+VDDC/+VDDCI: >2.0V
+MVDD: FLOAT
POWER UP SEQUENCE
14
-> VDDC/VDDCI -> MVDD
IN
C C
A
A
A
D D
VDDC/VDDCI INPUT VOLTAGE CONTROL
+12V_BUS
R1001 5%0R
0.47uHL1000
OVERLAP
5%0RR1000
+VDDC_I_VIN
+
+
C1000
C1001
270uF
270uF
16V
16V
MVDD INPUT
+12V_BUS
+VDDC_I_VIN
8
8
8
1
R1002 5%0R
0.47uHL1002
OVERLAP
5%0RR1003
5%0RMR1002
5%0RMR1003
+MVDD_VIN
+
C1002
270uF
16V
7
7
7
2
+1.8V
R1050
R1052
10K
10K
5%
SVC
5,11
BI
SVD
11,5
IN
SCL
5,17
IN
SDA
5,17
BI
5%
R1051
R1053
10K
10K
5%
5%
+3.3V_BUS
R1058
R1059
10K
10K
5%
5%
6
6
6
3
BI
OUT
OUT
BI
SVI2 POWER UP VOL TAGE (VDDC/VDDCI)
SVC SVD
0
0
0
1
1
0
1
1
MVDD_FB
R714
11.3K
1%
RFB2
5
5
5
4
VOLTAGE
1.1V
1.0V
0.9V
0.8V
13,17
OUT
+MVDD OUTPUT VOLTAGE
VOUT = VREF * (1+ RFB/RFB2)
RFB2 = (RFB * VREF) / (VOUT - VREF)
VREF = 0.8V
4
4
4
5
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
POWER MANAGEMENT
POWER MANAGEMENT
POWER MANAGEMENT
SHEET:
SHEET:
SHEET:
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
Mon Nov 24 11:06:56 2014
Mon Nov 24 11:06:56 2014
Mon Nov 24 11:06:56 2014
15 19
15 19
15 19
OF
OF
OF
105-C913xx-00B
105-C913xx-00B
105-C913xx-00B
3
3
3
6
5%0RR1022
R1030
10K
5%
1
C1020
1uF
6.3V
DNI
1
C1021
1uF
6.3V
1
C1030
1uF
6.3V
DNI
REV:
REV:
REV:
+12V_BUS
R1023
10K
5%
Q1020
MMBT3904
2 3
+12V_BUS
R1035
10K
5%
Q1024
MMBT3904
2 3
IN BACO MODE
TURN OFF
VDDC, VDDCI AND MVDD
+12V_BUS
R1032
10K
5%
Q1030
2N7002
2 3
1.0
1.0
1.0
R1025 5%5.1K
DNI
PX_EN
2,17,16
IN
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
C
C
C
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
information incl uded herein.
information incl uded herein.
information incl uded herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
1
5%5.1KR1024
1
R1027 5%10K
1
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
Q1021
MMBT3904
2 3
Q1022
MMBT3904
2 3
Q1031
MMBT3904
2 3
0.95V_EN
+3.3V_BUS
R1026
10K
5%
VDDC_I_EN
Q1023
1
MMBT3904
2 3
R1028
10K
5%
DNI
MVDD_EN
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
14
OUT
11
OUT
13
OUT
1
1
1
8
DD
DD
DD
C
C
C
BB
BB
BB
A
A
A
Page 16
1
8
8
8
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
(16) MECHANICAL AND THERMAL MANAGEMENT
+1.8V
A A
TS_A
TP200
TP201
CRITICAL TEMPERATURE FAULT
C
C
C
B B
GPIO_19_CTF
5
IN
PERSTB_BUF
1,2,11,16
IN
HEATSINKS
C C
TEMPORARY
Verde_Fansink
HS1A
1234567
8
EM2
1
1
E23-5611010-RH
A
A
A
GND
D D
8
8
8
1
U1P
PART 16 OF 16
AW21
TSVDD
C200
1uF
6.3V
AW20
TSVSS
BC19
TS_A
R230 4. 7K 5%
D230
1 2
BAT54KFILM
Verde_Fansink
HS1B
9
1011121314
16
15
1
1
1
1
BONAIRE
17
FM1
SW_FB
FM2
SW_FB
FM3
SW_FB
FM4
SW_FB
TSS FDO
Verde_Fansink
1819202122
DMINUS
GPIO_28_FDO
HS1C
BD25
DPLUS
BC25
GPIO_28_FDO PW M
BD27
R210
10K
5%
DNI
MMBT3906
CTF_TRIP
R232
100K
5%
MR231 0R 5%
CTF BYPASS
Verde_Fansink
HS1D
25
FM5
SW_FB
FM6
SW_FB
2627282930
32
31
2
23
7
7
7
R231 47K 5%
24
1
1
R200 20K 5%
+3.3V_BUS
23
Q231
R233
20K
5%
MR271
0R
5%
DNI
C255
0.1uF
6.3V
DNI
1
2
CLRB
3
4
FAN_EN
Q_OUT
R205 1K 1%
R204
3.83K
1%
A
B
CLR
GND5Q
PWM_B
Q200
1
BRACKET
DUAL
2 3
MMBT3904
TO PREVENT
FAN RUNNING
FULL SPEED AT
POWER UP
1,2,11,16
IN
R234
20K
5%
1
R236 2. 2K 5%
R235
20K
5%
Q230
1
MMBT3904
2 3
C230
0.01uF
10V
R237
1K
5%
TO MAXI MIZE FAN OUTPUT
DURING CTF TRIGGER
CTF_OUT
ASIC SOCKET
SK1
BONAIRE M3 SO CKET
PN 609004 1300G
BRACKET
BKT1
BRACKET
8020058600G
8020058 600G
SS - DP W TAB, HDM I, SINGLE DVI
8020056 20AG
DS - DP W TAB, HDMI, SINGLE DVI
8020056 10AG
DS - DP W TAB, HDMI, STACKED DVI
D200
BAT54KFILM
1 2
DNI
PERSTB_BUF
CTF_FAN
OUT
15,17
BKT2
8020056200G
1
BRACKET
DUAL
2 3
SCREW201
Q232
MMBT3904
SCREW
BKT3
8020056100G
BRACKET MT HOLE
MT200
2
6
6
6
3
34567
NA
9
8
5
5
5
4
17
OUT
+3.3V_BUS
FOR 4-WIRE FAN
J2
X_PIN1*2
TOP
Single end
Memory
48 ohm +/- 5 ohm
4.33 mils
J3
X_PIN1*2
L3
Single end
Memory
48 ohm +/- 5 ohm
4.33 mils
J4
X_PIN1*2
Bottom
Single end
Memory
48 ohm +/- 5 ohm
4.33 mils
4
4
4
5
TO SHUTDOWN FAN IN BACO
2,17,15,16
IN
R201
5.1K
5%
R202 1K 5%
PX_EN
2,17,15,16
IN
PERSTB_BUF
1,2,11,16
IN
PX_EN
R257 20K 5%
1
TOP
Different
PCIE
85 ohm +/- 10 %
4.41 mils / 7.4 mils
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHEET:
SHEET:
SHEET:
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
2
Q250A
MMDT3904-7
+3.3V_BUS
R203
10K
5%
DNI
5
OUT
Q201
MMBT3904
2 3
J5
341
2
impedence
MECH AND THERM MANAGEMENT
MECH AND THERM MANAGEMENT
MECH AND THERM MANAGEMENT
Mon Nov 24 11:06:56 2014
Mon Nov 24 11:06:56 2014
Mon Nov 24 11:06:56 2014
16 19
16 19
16 19
R272 0R 5%
R271 0R 5%
+3.3V_BUS
R267
10K
5%
6
1
GPIO_6_TACH
OF
OF
OF
105-C913xx-00B
105-C913xx-00B
105-C913xx-00B
3
3
3
6
+3.3V_BUS
U201
8
VCC
7
Rext/Cex t
6
C271 10uF 6. 3V
Cext
SN74LVC1G123DCT
Q_OUT
3
Q250B
5
20KR260 5%
MMDT3904-7
4
+12V_BUS
R206
10K
5%
J6
341
2
impedence
L3
Different
TMDS
85 ohm +/- 10 %
4.61 mils / 7.2 mils
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
1.0
1.0
1.0
REV:
REV:
REV:
information incl uded herein.
information incl uded herein.
information incl uded herein.
TITLE:
TITLE:
TITLE:
2
2
2
C270
0.1uF
6.3V
R256
20K
5%
R255
20K
5%
6
Q251A
2
MMDT3904-7
MMDT3904-7
1
2014
2014
2014
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
C
C
C
7
+3.3V_BUS
D270
12
DNI
1N4148W
R270 499K 1%
12V_FAN
1
3
CTF_BACO
Q251B
5
4
Bottom
Different
Memory clock
80 ohm +/- 10 %
4.33 mils / 6.3 mils
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
23
Q252
AO3415L
FAN_PWM
TACH
FANOUT_P
R253
0R
5%
DNI
R264 2. 2K 5%
J7
341
2
impedence
1
1
1
+12V_BUS
B200
220R
C201
10uF
16V
CTF_OUT
J200
4
3
2
1
HEADER_1X4_SHROUDED
8
DD
DD
DD
C
C
C
BB
BB
BB
A
A
A
Page 17
1
8
8
8
(17) DEBUG CIRCUITS
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
A A
C
C
C
B B
C C
JTAG
SWITCHES
DIGITAL POT
LED LIGHTS
U1A
PART 1 OF 16
JTAG
BONAIRE
G_SMBCLK
5,1
OUT
G_SMBDAT
1,5
BI
JTAG_TDO
BH47
JTAG_TDO
JTAG_TDI
BG48
JTAG_TDI
JTAG_TM S
BE47
JTAG_TMS
JTAG_TCK
BG45
JTAG_TCK
TESTEN
BH45
TESTEN
BG49
JTAG_TRSTB
JTAG_TRSTB
J4001
1
2
3
HEADER_1X3
J4004
HEADER_RECEPT_2X4
7 8
5 6
3 4
1 2
2,15,16,17
OUT
+3.3V_BUS
5%1KR4003
5%1KR4000 DNI
+3.3V_BUS
PX_EN
+3.3V_BUS
5%33RR 4004
R4001
1K
5%
DNI
R4002
1K
5%
1
2
HEADER_1X2
LED RED "ON" INDICAT ES CTF FAULT
CTF_OUT
16,15,17
IN
LED GREEN "ON" INDICAT ES BACO M ODE
PX_EN
2,17,15,16
J4002
IN
CTF_LED_ON
5%1KR4023
BACO_LED_ON
5%1KR4025
6
2
1
3
5
4
Q4000A
MMDT3904-7
Q4000B
MMDT3904-7
CTF_LED
BACO_LED
D4000
CTF_LED_PWR
RED
D4001
BACO_LED_PWR
GREEN
+3.3V_BUS
1%499RR4024
+3.3V_BUS
1%499RR4026
VTMM - TEST CONNECTOR FOR VOLTAGE MEASUREMENTS
+3.3V_BUS
SW4002A
5%10KR1071 DNI
5%0RR1060
5%0RR1061
SCL_MVDD
SDA_MVDD
1 4
Slide
SW4002B
2 3
Slide
7
10
9
8
6
11
12
RESET_N
ADDR
SCL
SDA
GND
THM
THM
20K
BYPASS CT F
MAXIMIZE FAN
+3.3V_BUS
C1070
C1071
0.1uF
U1000
1
VDD
3
W
2
A
5
C1072 6.3V1uF
EXT_CAP
4
VSS
10uF
6.3V
6.3V
MVDD_FB
R1072
7.5K
1%
13,15
OUT
DEBUG BUS
CTF_OUT
16,15,17
IN
PWM_B
16
IN
+3.3V_BUS
R1070 5%10K DNI
SCL
5,15,17
IN
SDA
5,15,17
BI
J4010
SOCKET_2X5
1
2
GPIO_2
3
FB_VDDC
4
FB_VSSC
5
FB_VDDCI
6
FB_VSSCI
SCL_VTMM
7
SDA_VTMM
8
9
10
5%0RR4010
5%0RR4011
5
IN
10,11
IN
10,11
IN
10,11
IN
10
IN
SCL
5,15,17
IN
SDA
5,15,17
IN
DD
DD
DD
C
C
C
BB
BB
BB
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
1.0
1.0
1.0
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
C
C
C
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
information incl uded herein.
information incl uded herein.
information incl uded herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
A
A
A
1
1
1
8
4
4
4
5
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
DEBUG CIRCUITS
DEBUG CIRCUITS
DEBUG CIRCUITS
SHEET:
SHEET:
SHEET:
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
Mon Nov 24 11:06:56 2014
Mon Nov 24 11:06:56 2014
Mon Nov 24 11:06:56 2014
17 19
17 19
17 19
OF
OF
OF
105-C913xx-00B
105-C913xx-00B
105-C913xx-00B
3
3
3
6
REV:
REV:
REV:
A
A
A
D D
8
8
8
1
7
7
7
2
6
6
6
3
5
5
5
4
Page 18
1
8
8
8
2
7
7
7
3
6
6
6
4
5
6
345
345
345
7
2
2
2
8
1
1
1
A A
DVO
DEBUG HEADER
DP
+3.3V_DP
C
C
C
B B
HDMI
+5V_VESA
DVI-D
+5V_VESA
DVI-I
C C
+5V_VESA
AC CAPS
AC CAPS
TERMINATIONS
AC CAPS
TERMINATIONS
AC CAPS
TERMINATIONS
RGB FILTERS
STRAPS
EEPROM
VBIOS/UEFI
DVPDATA[15:0]
DVPCNTL_0
TMDPC
DDCAUX1
HPD2
TMDPD
DDC3
HPD3
TMDPAB
DDCAUX4
HPD1
LTDPEF
DDCAUX6
HPD6
CRTDAC
HSYNC/ VSYNC
MLPS
GPIO8/9/10/22
PCI-E x16
TOBAGO
MEMORY
CHA/B
SVC/D/T
SCL/SDA
M3
THERM
TS_FDO
GPIO6
GPIO19
XO_IN/2
XTALIN/OUT
CHA/B GDDR5 4pcs x32
JTAG
JTAG
DEBUG
HEADER
VOLTAGE REGULATORS
VRHOT
FROM +12V_BUS
+VDDC, +VDD CI, +MVDD, +5V, FAN
FROM +3.3V_BUS
+1.8V, +0.95V, +3.3V_D P, VDDR 3
FROM +VDDC (SMPS)
VDDC
FROM +VDDCI (SMPS)
VDDCI
FROM +MVDD (SMPS)
VDDR1, MVDD Q/C
FROM +0.95V (SMPS)
PCIE_VDDC, BIF_VDD C, DP_VD DC
SPLL_VDDC
FROM +1.8V (LDO)
PCIE_PVDD, VDD_CT, VD DR4
DP_VDDR, SPLL_PVDD, MPLL_PVDD
VDD1DI, AVDD, TSVDD
POWER ENABLE
SEQUNCING
POWER DELIVER Y
GPIO5
DYNAMIC POWER MANAGEMENT
PX_EN
BACO
(SVI2, I2C)
FAN SPEED
CONTROL
FAN
PCI-E TOBAGO GDDR5 4pcs. x32
DP HDMI STACKE D DL-DVI FH 6L 6.3"
27M/100M
27M
BUILT-IN PWM
TACH INPUT
CTF
CLOCK CHIP
CRYSTAL
DD
DD
DD
C
C
C
BB
BB
BB
+12V_BUS
+3.3V_BUS
PCI-EXPRESS BUS
A
A
A
D D
8
8
8
1
7
7
7
2
6
6
6
3
5
5
5
4
4
4
4
5
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
SHEET:
SHEET:
SHEET:
DATE:
DATE:
DATE:
SHEET NUMBER:
SHEET NUMBER:
SHEET NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
DOCUMENT NUMBER:
Mon Nov 24 11:06:56 2014
Mon Nov 24 11:06:56 2014
Mon Nov 24 11:06:56 2014
18 19
18 19
18 19
OF
OF
OF
105-C913xx-00B
105-C913xx-00B
105-C913xx-00B
3
3
3
6
REV:
REV:
REV:
1.0
1.0
1.0
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
2014
2014
2014
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
C
C
C
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
is provided only to entitie s under a non-dis closure agreemen t with AMD
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
for evaluation purposes. Further dis tribution or dis closure i s strictl y
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
prohibited. Use of this schema tic and des ign for any purpose other than
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
evaluation requires a Board T echnology Li cense Agreeme nt with AMD.
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
AMD makes no representations or warranties of a ny kind regarding this
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
schematic and design, i ncluding , not limit ed to, any implie d warranty
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
of merchantability or fitnes s for a particu lar purpose, and di sclai ms
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
responsibili ty for any consequences resulting f rom use of the
information incl uded herein.
information incl uded herein.
information incl uded herein.
TITLE:
TITLE:
TITLE:
2
2
2
7
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
A
A
A
1
1
1
8
Page 19
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TITLE:
TITLE:
AMD
AMD
AMD
REVISION HISTORY
REVISION HISTORY
REVISION HISTORY
PCB
SCH
PCB
SCH
PCB
SCH
Rev
Rev
Rev
A A
D D
D D
D D
Date
Date
Date
Rev
Rev
Rev
00B 11/25/2014 CORRECTING VCC5 TO +VCC51
TITLE:
INITIAL DESIGN0 00A 08/19/2014
2
7
7
7
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
TOBAGO GDDR5 x32
ENGINEER:
ENGINEER:
ENGINEER:
XXX
XXX
XXX
NOTES:
NOTES:
NOTES:
3
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6
6
DOCUMENT NUMBER: SHEET NUMBER:
DOCUMENT NUMBER: SHEET NUMBER:
DOCUMENT NUMBER: SHEET NUMBER:
NOTE
NOTE
NOTE
4
5 4 3
5 4 3
5 4 3
105-C913xx-00B
105-C913xx-00B
105-C913xx-00B
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and is provided only to entiti es under a non-dis clos ure agreement with AMD
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and is provided only to entiti es under a non-dis clos ure agreement with AMD
This AMD Board sch ematic and de sign is the exclusi ve property of AMD, and is provided only to entiti es under a non-dis clos ure agreement with AMD
for evaluation purposes. Further dis tribution or dis closure i s strictl y prohibited. Use of this sc hematic and design fo r any purpose other than
for evaluation purposes. Further dis tribution or dis closure i s strictl y prohibited. Use of this sc hematic and design fo r any purpose other than
for evaluation purposes. Further dis tribution or dis closure i s strictl y prohibited. Use of this sc hematic and design fo r any purpose other than
evaluation requires a Board T echnology Li cense Agreeme nt with AMD. AMD makes no representations or warranties of any kind regarding th is
evaluation requires a Board T echnology Li cense Agreeme nt with AMD. AMD makes no representations or warranties of any kind regarding th is
evaluation requires a Board T echnology Li cense Agreeme nt with AMD. AMD makes no representations or warranties of any kind regarding th is
schematic and design, i ncluding , not limit ed to, any implie d warranty of merchantabilit y or fitness for a partic ular purpose, and discl aims
schematic and design, i ncluding , not limit ed to, any implie d warranty of merchantabilit y or fitness for a partic ular purpose, and discl aims
schematic and design, i ncluding , not limit ed to, any implie d warranty of merchantabilit y or fitness for a partic ular purpose, and discl aims
responsibili ty for any consequences resulting f rom use of the info rmation incl uded herein.
responsibili ty for any consequences resulting f rom use of the info rmation incl uded herein.
REVISION DESCRIPTON
REVISION DESCRIPTON
REVISION DESCRIPTON
responsibili ty for any consequences resulting f rom use of the info rmation incl uded herein.
5
Mon Nov 24 11:07:56 2014
Mon Nov 24 11:07:56 2014
DATE:
DATE:
DATE:
Mon Nov 24 11:07:56 2014
2014
2014
2014
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
C
C
C
6
7
2
2
2
19 19
19 19
19 19
OF
OF
OF
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
AMD - PLATFORM HARDWARE ENG
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
#48, No.1387, ZHANGDONG ROAD
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
SHANGHAI, CHINA 201203
8
1
1
1
1.0
1.0
1.0
REV:
REV:
REV:
C
C
C
B B
C
C
C
B B
B B
B B
C C
A
A
A
D D
A
A
A
8
8
8
1
7 6
7 6
7 6
2
3
5
5
5
4
4
4
4
5
3
3
3
6
2
2
2
7
1
1
1
8
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