MSI GeForce GTX 960 GAMING 2G Schematics REV2.0
A B
D
HGFEC
PG301 A02
Comanche 192b GDDR5, <150W, 2-way SLI
1
Tall DVI-I + DP + DP + DP/HDMI + DP
TABLE OF CONTENTS
Page
2
3
4
Description
1
Table of Contents
2
Block Diagram
3
PCI Express
4
MEMORY: GPU Partition A/B
5
MEMORY: FBA[31:0]
6
MEMORY: FBA[63:32]
7
MEMORY: FBB[31:0]
8
MEMORY: FBB[63:32]
9
MEMORY: GPU Partition C
10
MEMORY: FBC[31:0]
11
MEMORY: FBC[63:32]
12
GPU PWR and GND
13
GPU Decoupling
14
DACA Interface
15
IFPAB DVI-I-DL
16
IFPEF with IFPE DP
17
IFPF DP
18
IFPC HDMI/DP
19
IFPD DP
20
MIOA
21
MISC1: Fan, Thermal, JTAG, GPIO
22
MISC2: ROM, XTAL, Straps
23
PS: 5V, PEX_VDD, VID_PLL
24
PS: FBVDD/Q
25
PS: NVVDD Controller OVR4 option
Page
Description
PS: NVVDD Phase 1,2
26
PS: NVVDD Phase 3,4
27
[RESERVED]
28
29
PS: NVVDD OVR2+1 option
PS: Inputs, Filtering, and Monitoring
30
31
PS: Sequence and Shutdown
32
LEDs
PS: IOVDD Regulator
33
34
MECH: Bracket/Thermal
V320-2.0 change item:
Page15:DVI add esd
Page18:remove DP colay
Page20:HDMI add esd
Page21:4pin housing colay 6pin housing
Page25:NVVDD enable phase4
Page27:Add phase4
Page29:remove colay NVVDD power solution
Page30: 12V input bead change to choke
6pin power con colay 8pin con
remove 0603 MLCC colay
Page32:stuff logo LED
1
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
A B D F H
5
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MS-V320
MS-V320
MSI
MSI
MSI
Size Document Description Rev
Size Document Description Rev
Size Document Description Rev
Custom
Custom
Custom
Tuesday, November 18, 2014
Tuesday, November 18, 2014
EC
G
Tuesday, November 18, 2014
MS-V320
01_Table of Contents
01_Table of Contents
01_Table of Contents
Sheet ofDate:
134
Sheet ofDate:
134
Sheet ofDate:
134
2.0
2.0
2.0
Block Diagram
A B C D E F G H
1
Power Supply
NVVDD-PH4
EXT_12V 2x3 PWR 1
(NORTH)
1
Power Supply
NVVDD-PH3
Power Supply
NVVDD-PH2
SLI/
2
DP
HDMI/
3
DP
QD:FRAME LOCK
DP
MEM MEM MEM B
C
LO
C
HI
LO
MEM
MEM
B
HI
A
LO
Power Supply
NVVDD-PH1
Power Supply
5V Linear
Power Supply
FBVDD/FBVDDQ
2
3
PEX_12V Finger
MEM A
DP
4
DVI-I
QD:STEREO
HI
PEX_VDD
LDO
4
QUADRO OPTIONS SHOWN IN YELLOW
and prefix "QD:"
VID_PLL
LDO
PEX_3V3 Finger
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C E
Fan
5
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MS-V320
MS-V320
MSI
MSI
MSI
Size Document Description Rev
Size Document Description Rev
Size Document Description Rev
Custom
Custom
Custom
Monday, November 17, 2014
Monday, November 17, 2014
FDBA
G
Monday, November 17, 2014
MS-V320
01_Table of Contents
01_Table of Contents
01_Table of Contents
Sheet ofDate:
Sheet ofDate:
Sheet ofDate:
H
2.0
2.0
2.0
234
234
234
A B C D E F G H
PCI Express
1
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
3V3
12
12
C817
C822
4.7uF
0.1uF
16V
6.3V
20%
10%
X5R
X7R
0402
0603
COMMON
COMMON
GND
PEX_PRSNT*
12V
B1
B2
A2
A3
B3
B8
A9
A10
B10
A1
B17
B12
B4
A4
B7
A12
B13
A15
B16
B18
A18
GND
B31
A19
B30
A32
A20
B21
B22
A23
A24
B25
B26
A27
A28
B29
A31
B32
B48
GND
A33
A34
B35
B36
A37
A38
B39
B40
A41
A42
B43
B44
A45
A46
B47
B49
A49
GND
B81
A50
B82
A51
B52
B53
A54
A55
B56
B57
A58
A59
B60
B61
A62
A63
B64
B65
A66
A67
B68
B69
A70
A71
B72
B73
A74
A75
B76
B77
A78
A79
B80
A82
GND
NONPHY-X16
CN2
CON_X16
COMMON
@electro_mechanic.con_pci_express(sym_1):page3_i662
+12V
+12V
+12V
+12V
+12V/RSVD
+3V3
+3V3
+3V3
+3V3AUX
PRSNT1
PRSNT2
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
PRSNT2
RSVD
RSVD
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PRSNT2
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TRST* JTAG1
END OF X1
END OF X4
END OF X8
PRSNT2
RSVD
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
END OF X16
TCLK JTAG2
TDI JTAG3
TDO JTAG4
TMS JTAG5
SMCLK
SMDAT
PERST
REFCLK
REFCLK
PERP0
PERN0
PETP0
PETN0
PERP1
PERN1
PETP1
PETN1
PERP2
PERN2
PETP2
PETN2
PERP3
PERN3
PETP3
PETN3
PERP4
PERN4
PETP4
PETN4
PERP5
PERN5
PETP5
PETN5
PERP6
PERN6
PETP6
PETN6
PERP7
PERN7
PETP7
PETN7
PERP8
PERN8
PETP8
PETN8
PERP9
PERN9
PETP9
PETN9
PERP10
PERN10
PETP10
PETN10
PERP11
PERN11
PETP11
PETN11
PERP12
PERN12
PETP12
PETN12
PERP13
PERN13
PETP13
PETN13
PERP14
PERN14
PETP14
PETN14
PERP15
PERN15
PETP15
PETN15
0402
0402
0402
5
S3D
4
0ohm
0ohm
COMMON0402
0ohm
COMMON0402
0ohm
COMMON
0ohm
COMMON
0ohm
COMMON
C804 0.22uF
1 2
6.3V0402
10%
X5R
C795
0.22uF
1 2
0402 6.3V
10%
X5R
C787
0.22uF
1 2
6.3V0402
10%
X5R
C779
0.22uF
1 2
0402 6.3V
10%
X5R
C769
0.22uF
1 2
0402 6.3V
10%
X5R
C782
0.22uF
1 2
0402
6.3V
10%
X5R
C780
0.22uF
1 2
0402 6.3V
10%
X5R
C776
0.22uF
1 2
0402 6.3V
10%
X5R
C770
0.22uF
1 2
0402 6.3V
10%
X5R
C766
0.22uF
1 2
0402
6.3V
10%
X5R
C684
0.22uF
1 2
0402
6.3V
10%
X5R
C659
0.22uF
1 2
0402
6.3V
10%
X5R
C639
0.22uF
1 2
0402
6.3V
10%
X5R
C609
0.22uF
1 2
0402
6.3V
10%
X5R
C584
0.22uF
1 2
0402 6.3V
10%
X5R
C574
0.22uF
1 2
0402
6.3V
10%
X5R
3,20,32
JTAG_TRST*
JTAG_TCLK
JTAG_TDI
JTAG_TDO
JTAG_TMS
C801
1 2
C790 0.22uF
1 2
C783
1 2
C777
1 2
C767
1 2
C781
1 2
C778
1 2
C771 0.22uF
1 2
C768
1 2
C765
1 2
C678
1 2
C652
1 2
C632
1 2
C601
1 2
C581
1 2
C570
1 2
0402
0402 6.3V
0402 6.3V
0402 6.3V
0402 6.3V
0402 6.3V
0402 6.3V
0402 6.3V
0402 6.3V
0402 6.3V
0402 6.3V
0402 6.3V
0402 6.3V
0402 6.3V
0402 6.3V
0402 6.3V
R688
1 2
R724
R118
0ohm
1 2
0402
@discrete.q_fet_n_enh(sym_2):page3_i897
PEX_RST*
PEX_REFCLK
PEX_REFCLK*
PEX_TXX0
PEX_TXX0*
PEX_RX0
PEX_RX0*
PEX_TXX1
PEX_TXX1*
PEX_RX1
PEX_RX1*
PEX_TXX2
PEX_TXX2*
PEX_RX2
PEX_RX2*
PEX_TXX3
PEX_TXX3*
PEX_RX3
PEX_RX3*
PEX_TXX4
PEX_TXX4*
PEX_RX4
PEX_RX4*
PEX_TXX5
PEX_TXX5*
PEX_RX5
PEX_RX5*
PEX_TXX6
PEX_TXX6*
PEX_RX6
PEX_RX6*
PEX_TXX7
PEX_TXX7*
PEX_RX7
PEX_RX7*
PEX_TXX8
PEX_TXX8*
PEX_RX8
PEX_RX8*
PEX_TXX9
PEX_TXX9*
PEX_RX9
PEX_RX9*
PEX_TXX10
PEX_TXX10*
PEX_RX10
PEX_RX10*
PEX_TXX11
PEX_TXX11*
PEX_RX11
PEX_RX11*
PEX_TXX12
PEX_TXX12*
PEX_RX12
PEX_RX12*
PEX_TXX13
PEX_TXX13*
PEX_RX13
PEX_RX13*
PEX_TXX14
PEX_TXX14*
PEX_RX14
PEX_RX14*
PEX_TXX15
PEX_TXX15*
PEX_RX15
PEX_RX15*
COMMON
Q518A
COMMON
SOT363
R162
1 2
PEX_REFCLK PEXGEN3_SIGNALS
PEX_TXX0 PEXGEN3_SIGNALS
PEX_RX1 PEXGEN3_SIGNALS
PEX_RX1 PEXGEN3_SIGNALS
PEX_TXX2 PEXGEN3_SIGNALS
PEX_TXX2 PEXGEN3_SIGNALS
PEX_RX2 PEXGEN3_SIGNALS
PEX_RX3 PEXGEN3_SIGNALS
PEX_RX4 PEXGEN3_SIGNALS
PEX_RX4 PEXGEN3_SIGNALS
PEX_RX5 PEXGEN3_SIGNALS
PEX_RX5 PEXGEN3_SIGNALS
PEX_RX6 PEXGEN3_SIGNALS
PEX_RX6 PEXGEN3_SIGNALS
PEX_TXX7 PEXGEN3_SIGNALS
PEX_TXX7 PEXGEN3_SIGNALS
PEX_RX7 PEXGEN3_SIGNALS
PEX_RX7 PEXGEN3_SIGNALS
PEX_RX8 PEXGEN3_SIGNALS
PEX_RX8 PEXGEN3_SIGNALS
PEX_RX9 PEXGEN3_SIGNALS
PEX_RX9 PEXGEN3_SIGNALS
PEX_RX10 PEXGEN3_SIGNALS
PEX_RX10 PEXGEN3_SIGNALS
PEX_RX11 PEXGEN3_SIGNALS
PEX_RX11 PEXGEN3_SIGNALS
PEX_TXX12 PEXGEN3_SIGNALS
PEX_TXX12 PEXGEN3_SIGNALS
PEX_RX12 PEXGEN3_SIGNALS
PEX_RX12 PEXGEN3_SIGNALS
PEX_TXX13 PEXGEN3_SIGNALS
PEX_TXX13 PEXGEN3_SIGNALS
PEX_RX13 PEXGEN3_SIGNALS
PEX_RX13 PEXGEN3_SIGNALS
PEX_TXX14 PEXGEN3_SIGNALS
PEX_TXX14 PEXGEN3_SIGNALS
PEX_RX14 PEXGEN3_SIGNALS
PEX_RX14 PEXGEN3_SIGNALS
PEX_TXX15 PEXGEN3_SIGNALS
PEX_TXX15 PEXGEN3_SIGNALS
PEX_RX15 PEXGEN3_SIGNALS
PEX_RX15 PEXGEN3_SIGNALS
G
2
S6D
1
0ohm
DNI0402
OUT
PEXGEN3_SIGNALSPEX_REFCLK
PEXGEN3_SIGNALSPEX_TXX0
PEXGEN3_SIGNALSPEX_RX0
PEXGEN3_SIGNALSPEX_RX0
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALSPEX_RX2
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALSPEX_RX3
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEX_TRST*
B9
PEX_TCLK
A5
PEX_TDI
A6
PEX_TDO
A7
PEX_TMS
A8
PEX_SMCLK
B5
PEX_SMDAT
B6
B11
WAKE
A11
A13
A14
A16
A17
B14
B15
A21
A22
B19
B20
A25
A26
B23
B24
A29
A30
B27
B28
A35
A36
B33
B34
A39
A40
B37
B38
A43
A44
B41
B42
A47
A48
B45
B46
A52
A53
B50
B51
A56
A57
B54
B55
A60
A61
B58
B59
A64
A65
B62
B63
A68
A69
B66
B67
A72
A73
B70
B71
A76
A77
B74
B75
A80
A81
B78
B79
1 2
R704
1 2
R705
1 2
R706
1 2
G
Q518B
@discrete.q_fet_n_enh(sym_2):page3_i898
COMMON
SOT363
1 2
0402 DNI
3
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
COMMON
C E
0.22uF
6.3V
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
0.22uF
NV3V3
3V3_F
@logic.u_buf_3_state(sym_10):page3_i876
SC70_5
5
COMMON
1
VCC
OE
A
2
GND
3
GND
0ohm
1 2
U_GPU_GB2B_192_BGA1428-TEST_GM206_GPU_GM206-INT-A1-GM206-INT-A1
BGA1428
21
G1A
21
@digital.u_gpu_gb2b_192(sym_1):page3_i864
BGA1428
COMMON
1/18 PCI_EXPRESS
PEX_WAKE
PEX_RST
PEX_CLKREQ
PEX_REFCLK
PEX_REFCLK
PEX_TX0
PEX_TX0
PEX_RX0
PEX_RX0
PEX_TX1
PEX_TX1
PEX_RX1
PEX_RX1
PEX_TX2
PEX_TX2
PEX_RX2
PEX_RX2
PEX_TX3
PEX_TX3
PEX_RX3
PEX_RX3
PEX_TX4
PEX_TX4
PEX_RX4
PEX_RX4
PEX_TX5
PEX_TX5
PEX_RX5
PEX_RX5
PEX_TX6
PEX_TX6
PEX_RX6
PEX_RX6
PEX_TX7
PEX_TX7
PEX_RX7
PEX_RX7
PEX_TX8
PEX_TX8
PEX_RX8
PEX_RX8
PEX_TX9
PEX_TX9
PEX_RX9
PEX_RX9
PEX_TX10
PEX_TX10
PEX_RX10
PEX_RX10
PEX_TX11
PEX_TX11
PEX_RX11
PEX_RX11
PEX_TX12
PEX_TX12
PEX_RX12
PEX_RX12
PEX_TX13
PEX_TX13
PEX_RX13
PEX_RX13
PEX_TX14
PEX_TX14
PEX_RX14
PEX_RX14
PEX_TX15
PEX_TX15
PEX_RX15
PEX_RX15
GM206-300-A1
PEX_RST_BUF*
Y
4
COMMON0402
GND
5 %
0402
DNI
PEX_PLL_HVDD
PEX_SVDD_3V3
NVVDD_SENSE
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
GND_SENSE
PEX_PLLVDD
TESTMODE
PEX_TERMP
FDBA
MIN_WIDTHNET
0.500
0.500
0.4008.5A0V
12
C132
22uF
nv_res
6.3V
20%
R1668
X5R
0ohm
0805
COMMON
0.05 ohm
0805
C136
22uF
6.3V
20%
X5R
0805
COMMON
COMMON
nv_res
R1669
0ohm
0.05 ohm
0805
COMMON
PEX_VDD
12
C750
22uF
6.3V
20%
X5R
0805
COMMON
GND
12
12
C133
22uF
6.3V
20%
X5R
0805
COMMON
PEX_VDD
nv_res
GND
R1670
0ohm
0.05 ohm
0805
COMMON
1
2
IOVDD
3
C722
0.1uF
16V
10%
X7R
0402
COMMON
IOVDD
12
GND
C679
4.7uF
6.3V
20%
X5R
0603
COMMON
12
C743
4.7uF
6.3V
20%
X5R
0603
COMMON
12
VOLTAGE MAX_CURRENT
12V
3.3V
12
12
C741
C751
22uF
22uF
6.3V
6.3V
20%
20%
X5R
X5R
0805
0805
COMMON
COMMON
0.400
C732
12
C721
0.1uF
1uF
16V
6.3V
10%
10%
X7R
X5R
0402
0402
COMMON
COMMON
GND
12
C137
4.7uF
6.3V
20%
X5R
0603
COMMON
25
25
5.5A
3.0A
12V
12V
3V3
NVVDD_SENSE
GND_SENSE
3,20,32
3V3
GND
GND
12
C762
1uF
6.3V
10%
X5R
0402
COMMON
GPU_PEX_IOVDDQ
12
12
12
C724
1uF
6.3V
10%
X5R
0402
COMMON
C729
4.7uF
6.3V
20%
X5R
0603
COMMON
12
OUT
OUT
C723
1uF
6.3V
10%
X5R
0402
COMMON
12
C672
0.1uF
16V
10%
X7R
0402
COMMON
OUT
AP29
AP30
AR27
AR28
AR29
AP17
AP18
AP19
AP20
AP21
AP22
AP23
AP24
AP25
AP26
AP27
AP28
AR19
AR20
AR21
AR22
AR23
AR24
AR25
AR26
AT22
AT28
AT42
AT41
4
BB36
BA36
AT25
AT21
AW35
PEX_PLL_CLK_OUT
PEX_PLL_CLK_OUT*
GPU_TESTMODE
PEX_TERMP
PEX_PLL_CLK PEXGEN3_SIGNALS
PEX_PLL_CLK PEXGEN3_SIGNALS
PEX_PLLVDD
R637
10k
1 2
COMMON
0402
5 %
R629
2.49k
1 2
COMMON
0402
1 %
R635
200ohm
5 %
0402
COMMON
12
C759
0.1uF
16V
10%
X7R
0402
COMMON
GND
GND
MSI
MSI
MSI
Size Document Description Rev
Size Document Description Rev
Size Document Description Rev
Custom
Custom
Custom
Date:
Monday, November 17, 2014
Date:
Monday, November 17, 2014
Date:
G
Monday, November 17, 2014
PEX_VDD IOVDD
R664
R663
0ohm
0ohm
0402
0402
COMMON
COMMON
12
12
C731
C761
1uF
4.7uF
6.3V
6.3V
10%
20%
X5R
X5R
0402
0603
COMMON
COMMON
GND
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MS-V320
MS-V320
MS-V320
01_Table of Contents
01_Table of Contents
01_Table of Contents
Sheet of
Sheet of
Sheet of
H
334
334
334
5
2.0
2.0
2.0
R1642
100k
5 %
0402
COMMON
21
21
21
3
21
21
NV3V3
R1643
100k
5 %
0402
COMMON
I2CS_SCL
I2CS_SDA
PEX_RST_BUF*
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEX_RST*
IN
OUT
OUT
BA15
BB19
BB18
AW17
AY17
AU19
AV19
BA19
AY19
AW20
AV20
AY21
BA21
AV21
AU21
BB21
BB22
AU22
AV22
BA22
AY22
AV23
AW23
AY24
BA24
AV24
AU24
BB24
BB25
AU25
AV25
BA25
AY25
AW26
AV26
AY27
BA27
AV27
AU27
BB27
BB28
AU28
AV28
BA28
AY28
AW29
AV29
AY30
BA30
AV30
AU30
BB30
BB31
AU31
AV31
BA31
AY31
AW32
AV32
AY33
BA33
AV33
AU33
BB33
BB34
AU34
AV34
BA34
AY34
OUT
OUT
OUT
OUT
OUT
IN
PEX_TX0
PEX_TX0*
10%
COMMON
X5R
PEX_TX1
PEX_TX1*
10%
COMMON
X5R
PEX_TX2
PEX_TX2*
10%
COMMON
X5R
PEX_TX3
PEX_TX3*
10%
COMMON
X5R
PEX_TX4
PEX_TX4*
10%
COMMON
X5R
PEX_TX5
PEX_TX5*
10%
COMMON
X5R
PEX_TX6
PEX_TX6*
10%
COMMON
X5R
PEX_TX7
PEX_TX7*
10%
COMMON
X5R
PEX_TX8
PEX_TX8*
10%
COMMON
X5R
PEX_TX9
PEX_TX9*
10%
COMMON
X5R
PEX_TX10
PEX_TX10*
10%
COMMON
X5R
PEX_TX11
PEX_TX11*
10%
COMMON
X5R
PEX_TX12
PEX_TX12*
10%
COMMON
X5R
PEX_TX13
PEX_TX13*
10%
COMMON
X5R
PEX_TX14
PEX_TX14*
10%
COMMON
X5R
PEX_TX15
PEX_TX15*
10%
COMMON
X5R
A B C D E F G H
MEMORY: GPU Partition A/B
1
FBA_D<0>
Fba_D<0>
Fba_D<1>
Fba_D<2>
Fba_D<3>
Fba_D<4>
Fba_D<5>
Fba_D<6>
Fba_D<7>
Fba_D<8>
Fba_D<9>
Fba_D<10>
Fba_D<11>
Fba_D<12>
Fba_D<13>
Fba_D<14>
Fba_D<15>
Fba_D<16>
Fba_D<17>
Fba_D<18>
Fba_D<19>
Fba_D<20>
Fba_D<21>
2
3
Fba_D<22>
Fba_D<23>
Fba_D<24>
Fba_D<25>
Fba_D<26>
Fba_D<27>
Fba_D<28>
Fba_D<29>
Fba_D<30>
Fba_D<31>
Fba_D<32>
Fba_D<33>
Fba_D<34>
Fba_D<35>
Fba_D<36>
Fba_D<37>
Fba_D<38>
Fba_D<39>
Fba_D<40>
Fba_D<41>
Fba_D<42>
Fba_D<43>
Fba_D<44>
Fba_D<45>
Fba_D<46>
Fba_D<47>
Fba_D<48>
Fba_D<49>
Fba_D<50>
Fba_D<51>
Fba_D<52>
Fba_D<53>
Fba_D<54>
Fba_D<55>
Fba_D<56>
Fba_D<57>
Fba_D<58>
Fba_D<59>
Fba_D<60>
Fba_D<61>
Fba_D<62>
Fba_D<63>
4
0
FBA_D<1>
1
FBA_D<2>
2
FBA_D<3>
3
FBA_D<4>
4
FBA_D<5>
5
FBA_D<6>
6
FBA_D<7>
7
FBA_D<8>
8
FBA_D<9>
9
FBA_D<10>
10
FBA_D<11>
11
FBA_D<12>
12
FBA_D<13>
13
FBA_D<14>
14
FBA_D<15>
15
FBA_D<16>
16
FBA_D<17>
17
FBA_D<18>
18
FBA_D<19>
19
FBA_D<20>
20
FBA_D<21>
21
FBA_D<22>
22
FBA_D<23>
23
FBA_D<24>
24
FBA_D<25>
25
FBA_D<26>
26
FBA_D<27>
27
FBA_D<28>
28
FBA_D<29>
29
FBA_D<30>
30
FBA_D<31>
31
FBA_D<32>
32
FBA_D<33>
33
FBA_D<34>
34
FBA_D<35>
35
FBA_D<36>
36
FBA_D<37>
37
FBA_D<38>
38
FBA_D<39>
39
FBA_D<40>
40
FBA_D<41>
41
FBA_D<42>
42
FBA_D<43>
43
FBA_D<44>
44
FBA_D<45>
45
FBA_D<46>
46
FBA_D<47>
47
FBA_D<48>
48
FBA_D<49>
49
FBA_D<50>
50
FBA_D<51>
51
FBA_D<52>
52
FBA_D<53>
53
FBA_D<54>
54
FBA_D<55>
55
FBA_D<56>
56
FBA_D<57>
57
FBA_D<58>
58
FBA_D<59>
59
FBA_D<60>
60
FBA_D<61>
61
FBA_D<62>
62
FBA_D<63>
63
FBA_DBI<0>
BI
FBA_DBI<1>
BI
FBA_DBI<2>
BI
FBA_DBI<3>
BI
FBA_DBI<4>
BI
FBA_DBI<5>
BI
FBA_DBI<6>
BI
FBA_DBI<7>
BI
FBA_EDC<0>
IN
FBA_EDC<1>
IN
FBA_EDC<2>
IN
FBA_EDC<3>
IN
FBA_EDC<4>
IN
FBA_EDC<5>
IN
FBA_EDC<6>
IN
FBA_EDC<7>
IN
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
U_GPU_GB2B_192_BGA1428-TEST_GM206_GPU_GM206-INT-A1-GM206-INT-A1
G1B
@digital.u_gpu_gb2b_192(sym_2):page4_i1905
BGA1428
COMMON
2/18 FBA
H38
FBA_D0
J39
FBA_D1
J38
FBA_D2
J37
FBA_D3
L36
FBA_D4
K38
FBA_D5
M39
FBA_D6
K39
FBA_D7
M42
FBA_D8
L40
FBA_D9
M41
FBA_D10
M40
FBA_D11
J42
FBA_D12
J41
FBA_D13
H40
FBA_D14
J40
FBA_D15
N40
FBA_D16
N41
FBA_D17
N42
FBA_D18
P40
FBA_D19
T40
FBA_D20
T42
FBA_D21
U40
FBA_D22
T41
FBA_D23
T38
FBA_D24
T37
FBA_D25
T39
FBA_D26
U36
FBA_D27
P36
FBA_D28
R39
FBA_D29
R38
FBA_D30
N39
FBA_D31
AT40
FBA_D32
AP39
FBA_D33
AR38
FBA_D34
AP38
FBA_D35
AN37
FBA_D36
AL37
FBA_D37
AN39
FBA_D38
AN38
FBA_D39
AL40
FBA_D40
AL41
FBA_D41
AL42
FBA_D42
AM40
FBA_D43
AP40
FBA_D44
AP42
FBA_D45
AR40
FBA_D46
AP41
FBA_D47
AK37
FBA_D48
AK39
FBA_D49
AK38
FBA_D50
AH39
FBA_D51
AF36
FBA_D52
AG37
FBA_D53
AG39
FBA_D54
AG38
FBA_D55
AF38
FBA_D56
AG41
FBA_D57
AG40
FBA_D58
AG42
FBA_D59
AJ40
FBA_D60
AK40
FBA_D61
AK42
FBA_D62
AK41
FBA_D63
K36
FBA_DQM0
K42
FBA_DQM1
R42
FBA_DQM2
R37
FBA_DQM3
AP37
FBA_DQM4
AN42
FBA_DQM5
AJ36
FBA_DQM6
AH42
FBA_DQM7
J36
FBA_DQS_WP0
K41
FBA_DQS_WP1
R41
FBA_DQS_WP2
T35
FBA_DQS_WP3
AN36
FBA_DQS_WP4
AN41
FBA_DQS_WP5
AH38
FBA_DQS_WP6
AH41
AM36
AN40
AH37
AH40
J35
K40
R40
R36
FBA_DQS_WP7
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
FBA_PLL_AVDD
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
FBA_CMD32
FBA_CMD33
FBA_CMD34
FBA_CMD35
FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1
FBA_WCK01
FBA_WCK01
FBA_WCKB01
FBA_WCKB01
FBA_WCK23
FBA_WCK23
FBA_WCKB23
FBA_WCKB23
FBA_WCK45
FBA_WCK45
FBA_WCKB45
FBA_WCKB45
FBA_WCK67
FBA_WCK67
FBA_WCKB67
FBA_WCKB67
FBA_CMD<1>
W37
FBA_CMD<2>
Y40
FBA_CMD<3>
Y38
FBA_CMD<4>
AC40
FBA_CMD<5>
Y36
FBA_CMD<6>
V36
FBA_CMD<7>
W42
FBA_CMD<8>
W41
FBA_CMD<9>
W40
FBA_CMD<10>
V35
FBA_CMD<11>
W39
FBA_CMD<12>
V40
FBA_CMD<13>
V39
FBA_CMD<14>
V38
FBA_CMD<15>
V37
FBA_CMD<16>
AE38
FBA_CMD<17>
AE37
FBA_CMD<18>
AE36
FBA_CMD<19>
AD39
FBA_CMD<20>
AE35
FBA_CMD<21>
AD38
FBA_CMD<22>
AE41
FBA_CMD<23>
AE42
FBA_CMD<24>
AD37
FBA_CMD<25>
AC38
FBA_CMD<26>
AC36
FBA_CMD<27>
W35
FBA_CMD<28>
AE40
FBA_CMD<29>
AD42
FBA_CMD<30>
AD41
FBA_CMD<31>
AD40
AE34
AF34
FBA_DEBUG0
AC35
FBA_DEBUG1
AD35
FBA_CLK0
V41
FBA_CLK0*
V42
FBA_CLK1
AF40
FBA_CLK1*
AF39
FBA_WCK01
M37
FBA_WCK01*
M38
M36
L35
FBA_WCK23
N37
FBA_WCK23*
N38
P35
N36
FBA_WCK45
AK36
FBA_WCK45*
AJ35
AH36
AG35
FBA_WCK67
AL38
FBA_WCK67*
AL39
AM35
AL36
IOVDD
AG34
12
0
FBA_CMD<0>
1
FBA_CMD<1>
2
FBA_CMD<2>
3
FBA_CMD<3>
4
FBA_CMD<4>
5
FBA_CMD<5>
6
FBA_CMD<6>
7
FBA_CMD<7>
8
FBA_CMD<8>
9
FBA_CMD<9>
10
FBA_CMD<10>
11
FBA_CMD<11>
12
FBA_CMD<12>
13
FBA_CMD<13>
14
FBA_CMD<14>
15
FBA_CMD<15>
16
FBA_CMD<16>
17
FBA_CMD<17>
18
FBA_CMD<18>
19
FBA_CMD<19>
20
FBA_CMD<20>
21
FBA_CMD<21>
22
FBA_CMD<22>
23
FBA_CMD<23>
24
FBA_CMD<24>
25
FBA_CMD<25>
26
FBA_CMD<26>
27
FBA_CMD<27>
28
FBA_CMD<28>
29
FBA_CMD<29>
30
FBA_CMD<30>
31
0402
12
GND
60.4ohm
DNI
1 %
C633
22uF
6.3V
20%
X5R
0805
COMMON
FBA_CMD<30>
FBA_CMD<14>
FBA_CMD<29>
FBA_CMD<13>
FBA_CMD<31>
R583
1 2
FB_CLK
FB_CLK
FB_CLK
FB_CLK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
60.4ohm
0402
DNI
1 %
R614
10k
5 %
0402
COMMON
R564
10k
5 %
0402
COMMON
R580
1 2
LB501
30ohm
COMMON
BEAD_0603
FB_PLLVDD FB_PLLVDD
C593
0.1uF
16V
10%
X7R
0402
COMMON
CKE*
FBA_CMD<0>
W38
C E
U_GPU_GB2B_192_BGA1428-TEST_GM206_GPU_GM206-INT-A1-GM206-INT-A1
G1C
@digital.u_gpu_gb2b_192(sym_3):page4_i1906
BGA1428
COMMON
FBB_D<0>
Fbb_D<0>
FBVDDQ
Fbb_D<1>
Fbb_D<2>
Fbb_D<3>
Fbb_D<4>
Fbb_D<5>
Fbb_D<6>
Fbb_D<7>
Fbb_D<8>
Fbb_D<9>
Fbb_D<10>
Fbb_D<11>
Fbb_D<12>
Fbb_D<13>
Fbb_D<14>
Fbb_D<15>
Fbb_D<16>
Fbb_D<17>
Fbb_D<18>
Fbb_D<19>
Fbb_D<20>
Fbb_D<21>
Fbb_D<22>
Fbb_D<23>
Fbb_D<24>
Fbb_D<25>
Fbb_D<26>
Fbb_D<27>
Fbb_D<28>
Fbb_D<29>
Fbb_D<30>
Fbb_D<31>
Fbb_D<32>
Fbb_D<33>
Fbb_D<34>
Fbb_D<35>
Fbb_D<36>
Fbb_D<37>
Fbb_D<38>
Fbb_D<39>
Fbb_D<40>
Fbb_D<41>
Fbb_D<42>
Fbb_D<43>
Fbb_D<44>
Fbb_D<45>
Fbb_D<46>
Fbb_D<47>
Fbb_D<48>
Fbb_D<49>
Fbb_D<50>
Fbb_D<51>
Fbb_D<52>
Fbb_D<53>
Fbb_D<54>
Fbb_D<55>
Fbb_D<56>
Fbb_D<57>
Fbb_D<58>
Fbb_D<59>
Fbb_D<60>
Fbb_D<61>
Fbb_D<62>
Fbb_D<63>
R550
10k
5 %
0402
COMMON
R553
10k
5 %
0402
COMMON
GND
GDDR5_BGA170_MIRROR
0..31 32..63
CMD0 CS*
CMD1 A3_BA3
CMD2 A2_BA0
CMD3 A4_BA2
CMD4 A5_BA1
CMD5 WE*
CMD6 A7_A8
CMD7 A6_A11
CMD8 ABI*
CMD9 A12_RFU
CMD10 A0_A10
CMD11 A1_A9
CMD12 RAS*
CMD13 RST*
CMD14 CKE*
CMD15 CAS*
CMD32
CKE*
FBB_CMD<30>
FBB_CMD<14>
FBB_CMD<29>
FBB_CMD<13>
RST*RST*
CMD34 DBG0 DBG0
CMD16 CS*
CMD17 A3_BA3
CMD18 A2_BA0
CMD19 A4_BA2
CMD20 A5_BA1
CMD21 WE*
CMD22 A7_A8
CMD23 A6_A11
CMD24 ABI*
CMD25 A12_RFU
CMD26 A0_A10
CMD27 A1_A9
CMD28 RAS*
CMD29 RST*
CMD30 CKE*
CMD31 CAS*
CMD33
CMD35 DBG1 DBG1
R552
10k
5 %
0402
COMMON
R551
10k
5 %
0402
COMMON
FBVDDQ
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
FBVDDQ
R561
10k
5 %
0402
COMMON
R621
10k
5 %
0402
COMMON
GND
0
FBB_D<1>
1
FBB_D<2>
2
FBB_D<3>
3
FBB_D<4>
4
FBB_D<5>
5
FBB_D<6>
6
FBB_D<7>
7
FBB_D<8>
8
FBB_D<9>
9
FBB_D<10>
10
FBB_D<11>
11
FBB_D<12>
12
FBB_D<13>
13
FBB_D<14>
14
FBB_D<15>
15
FBB_D<16>
16
FBB_D<17>
17
FBB_D<18>
18
FBB_D<19>
19
FBB_D<20>
20
FBB_D<21>
21
FBB_D<22>
22
FBB_D<23>
23
FBB_D<24>
24
FBB_D<25>
25
FBB_D<26>
26
FBB_D<27>
27
FBB_D<28>
28
FBB_D<29>
29
FBB_D<30>
30
FBB_D<31>
31
FBB_D<32>
32
FBB_D<33>
33
FBB_D<34>
34
FBB_D<35>
35
FBB_D<36>
36
FBB_D<37>
37
FBB_D<38>
38
FBB_D<39>
39
FBB_D<40>
40
FBB_D<41>
41
FBB_D<42>
42
FBB_D<43>
43
FBB_D<44>
44
FBB_D<45>
45
FBB_D<46>
46
FBB_D<47>
47
FBB_D<48>
48
FBB_D<49>
49
FBB_D<50>
50
FBB_D<51>
51
FBB_D<52>
52
FBB_D<53>
53
FBB_D<54>
54
FBB_D<55>
55
FBB_D<56>
56
FBB_D<57>
57
FBB_D<58>
58
FBB_D<59>
59
FBB_D<60>
60
FBB_D<61>
61
FBB_D<62>
62
FBB_D<63>
63
FBB_DBI<0>
BI
FBB_DBI<1>
BI
FBB_DBI<2>
BI
FBB_DBI<3>
BI
FBB_DBI<4>
BI
FBB_DBI<5>
BI
FBB_DBI<6>
BI
FBB_DBI<7>
BI
FBB_EDC<0>
IN
FBB_EDC<1>
IN
FBB_EDC<2>
IN
FBB_EDC<3>
IN
FBB_EDC<4>
IN
FBB_EDC<5>
IN
FBB_EDC<6>
IN
FBB_EDC<7>
IN
3/18 FBB
F15
D15
E15
G15
E16
D16
D18
E18
C18
C17
A18
B18
C15
A15
C14
B15
D19
E19
F19
D21
G23
F22
E22
D22
C23
B22
C22
A22
B21
C19
A19
B19
G41
F42
G42
F41
C41
D42
C39
C40
G35
F37
D36
D37
E37
E39
G37
F38
A36
C35
C36
B36
A34
A33
C33
B33
F35
G34
E36
A37
F34
E33
F33
G32
F16
A16
H22
A21
D40
D41
E34
D34
G16
B16
E21
C21
F40
D38
C34
B37
H15
C16
F21
C20
E40
D39
B34
C37
FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63
FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7
FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7
FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7
FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31
FBB_CMD32
FBB_CMD33
FBB_CMD34
FBB_CMD35
FBB_CLK0
FBB_CLK0
FBB_CLK1
FBB_CLK1
FBB_WCK01
FBB_WCK01
FBB_WCKB01
FBB_WCKB01
FBB_WCK23
FBB_WCK23
FBB_WCKB23
FBB_WCKB23
FBB_WCK45
FBB_WCK45
FBB_WCKB45
FBB_WCKB45
FBB_WCK67
FBB_WCK67
FBB_WCKB67
FBB_WCKB67
FBB_PLL_AVDD
FDBA
FBB_CMD<0>
D24
FBB_CMD<1>
E24
FBB_CMD<2>
F24
FBB_CMD<3>
H24
FBB_CMD<4>
C24
FBB_CMD<5>
A25
FBB_CMD<6>
B25
FBB_CMD<7>
C25
FBB_CMD<8>
D25
FBB_CMD<9>
G24
FBB_CMD<10>
F25
FBB_CMD<11>
E25
FBB_CMD<12>
C26
FBB_CMD<13>
C29
FBB_CMD<14>
C30
FBB_CMD<15>
B30
FBB_CMD<16>
B31
FBB_CMD<17>
G26
FBB_CMD<18>
E26
FBB_CMD<19>
C31
FBB_CMD<20>
A31
FBB_CMD<21>
A30
FBB_CMD<22>
G31
FBB_CMD<23>
D30
FBB_CMD<24>
F30
FBB_CMD<25>
E30
FBB_CMD<26>
E29
FBB_CMD<27>
H25
FBB_CMD<28>
G29
FBB_CMD<29>
D31
FBB_CMD<30>
E31
FBB_CMD<31>
F31
H29
H26
FBB_DEBUG0
H30
FBB_DEBUG1
H31
FBB_CLK0
B24
FBB_CLK0*
A24
FBB_CLK1
D32
FBB_CLK1*
C32
FBB_WCK01
H20
FBB_WCK01*
G19
G18
H17
FBB_WCK23
G17
FBB_WCK23*
F18
G20
G21
FBB_WCK45
C38
FBB_WCK45*
B39
G36
H35
FBB_WCK67
A39
FBB_WCK67*
B40
H36
H37
H23
G
0
Fbb_Cmd<0>
1
Fbb_Cmd<1>
2
Fbb_Cmd<2>
3
Fbb_Cmd<3>
4
Fbb_Cmd<4>
5
Fbb_Cmd<5>
6
Fbb_Cmd<6>
7
Fbb_Cmd<7>
8
Fbb_Cmd<8>
9
Fbb_Cmd<9>
10
Fbb_Cmd<10>
11
Fbb_Cmd<11>
12
Fbb_Cmd<12>
13
Fbb_Cmd<13>
14
Fbb_Cmd<14>
15
Fbb_Cmd<15>
16
Fbb_Cmd<16>
17
Fbb_Cmd<17>
18
Fbb_Cmd<18>
19
Fbb_Cmd<19>
20
Fbb_Cmd<20>
21
Fbb_Cmd<21>
22
Fbb_Cmd<22>
23
Fbb_Cmd<23>
24
Fbb_Cmd<24>
25
Fbb_Cmd<25>
26
Fbb_Cmd<26>
27
Fbb_Cmd<27>
28
Fbb_Cmd<28>
29
Fbb_Cmd<29>
30
Fbb_Cmd<30>
31
Fbb_Cmd<31>
R562
60.4ohm
1 2
12
C704
0.1uF
16V
10%
X7R
0402
COMMON
GND
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MSI
MSI
MSI
Size Document Description Rev
Size Document Description Rev
Size Document Description Rev
Custom
Custom
Custom
Date:
Monday, November 17, 2014
Date:
Monday, November 17, 2014
Date:
Monday, November 17, 2014
R566 60.4ohm
DNI
0402
1 2
1 %
0402
FB_CLK
FB_CLK
FB_CLK
FB_CLK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
IN
MS-V320
MS-V320
MS-V320
01_Table of Contents
01_Table of Contents
01_Table of Contents
DNI
1 %
H
FBVDDQ
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Sheet of
Sheet of
Sheet of
434
434
434
1
2
3
4
5
2.0
2.0
2.0
A B C D E F G H
MEMORY: FBA Partition 31..0
1
4
Fba_D<0>
4
Fba_D<1>
4
Fba_D<2>
4
Fba_D<3>
4
Fba_D<4>
4
Fba_D<5>
4
Fba_D<6>
4
Fba_D<7>
4
4
4
Fba_D<8>
4
Fba_D<9>
4
Fba_D<10>
4
Fba_D<11>
4
Fba_D<12>
4
Fba_D<13>
4
2
4
4
3
Fba_D<14>
4
Fba_D<15>
4
4
IN
IN
M2C
@memory.u_mem_sd_ddr5_x32(sym_6):page5_i558
BGA170
M2B
@memory.u_mem_sd_ddr5_x32(sym_5):page5_i556
BGA170
FBA_CMD<3>
FBA_VREF_Q
3
FBA_CMD<0>
0
FBA_CMD<10>
10
FBA_CMD<15>
15
FBA_CMD<7>
7
FBA_CMD<5>
5
FBA_CMD<4>
4
FBA_CMD<13>
13
FBA_CMD<14>
14
FBA_CMD<12>
12
FBA_CMD<11>
11
FBA_CMD<8>
8
FBA_CMD<9>
9
FBA_CMD<6>
6
FBA_CMD<2>
2
FBA_CMD<1>
1
FBA_CLK0
IN
FBA_CLK0*
IN
R563
R565
40.2ohm
40.2ohm
1 %
1 %
0402
0402
COMMON
COMMON
FBA_CLK0_CM
12
C578
10nF
16V
10%
X7R
0402
R659
549ohm
1 %
0402
COMMON
R181
1.33k
1 %
0402
COMMON
GND
R658
931ohm
1 %
0402
COMMON
COMMON
12
GND GND
FBVDDQ
GND
FBA_CMD<3>
FBA_CMD<0>
M2D
@memory.u_mem_sd_ddr5_x32(sym_1):page5_i468
BGA170
COMMON
FBA_D<0>
0
FBA_D<1>
1
FBA_D<2>
2
FBA_D<3>
3
FBA_D<4>
4
FBA_D<5>
5
FBA_D<6>
6
FBA_D<7>
7
FBA_EDC<0>
OUT
FBA_DBI<0>
OUT
FBA_D<8>
8
FBA_D<9>
9
FBA_D<10>
10
FBA_D<11>
11
FBA_D<12>
12
FBA_D<13>
13
FBA_D<14>
14
FBA_D<15>
15
FBA_EDC<1>
OUT
FBA_DBI<1>
OUT
FBA_WCK01
FBA_WCK01*
NORMAL
A4
DQ0
A2
DQ1
B4
DQ2
B2
DQ3
E4
DQ4
E2
DQ5
F4
DQ6
F2
DQ7
C2
EDC0
D2
DBI0
A10
VREFD
x16
x32
A11
DQ8
NC
A13
DQ9
NC
B11
DQ10
NC
B13
DQ11
NC
E11
DQ12
NC
E13
DQ13
NC
F11
DQ14
NC
F13
DQ15
NC
C13
EDC1
GND
D13
DBI1
NC
D4
WCK01
D5
WCK01
4
4
4
Fba_D<16>
4
Fba_D<17>
4
Fba_D<18>
4
Fba_D<19>
4
Fba_D<20>
4
Fba_D<21>
4
Fba_D<22>
4
Fba_D<23>
4
4
4
Fba_D<24>
4
Fba_D<25>
4
Fba_D<26>
4
Fba_D<27>
4
Fba_D<28>
4
Fba_D<29>
4
Fba_D<30>
4
Fba_D<31>
4
4
IN
IN
7,10,21
FBA_D<16>
16
FBA_D<17>
17
FBA_D<18>
18
FBA_D<19>
19
FBA_D<20>
20
FBA_D<21>
21
FBA_D<22>
22
FBA_D<23>
23
FBA_EDC<2>
OUT
FBA_DBI<2>
OUT
FBA_D<24>
24
FBA_D<25>
25
FBA_D<26>
26
FBA_D<27>
27
FBA_D<28>
28
FBA_D<29>
29
FBA_D<30>
30
FBA_D<31>
31
FBA_EDC<3>
OUT
FBA_DBI<3>
OUT
FBA_WCK23
FBA_WCK23*
GPIO10_FBVREF_SEL
IN
M2A
@memory.u_mem_sd_ddr5_x32(sym_3):page5_i507
BGA170
COMMON
NORMAL
V11
DQ16
V13
DQ17
T11
DQ18
T13
DQ19
N11
DQ20
N13
DQ21
M11
DQ22
M13
DQ23
R13
EDC2
P13
DBI2
VREFD
x16
x32
V4
DQ24
NC
V2
DQ25
NC
T4
DQ26
NC
T2
DQ27
NC
N4
DQ28
NC
N2
DQ29
NC
M4
DQ30
NC
M2
DQ31
NC
R2
EDC3
NC
P2
DBI3
NC
P4
WCK23
P5
WCK23
Use low VGSth part for Pascal
AO3420
1G1D1S
1
V10
3
D
Q515
@discrete.q_fet_n_enh(sym_2):page5_i506
SOT23_1G1D1S
G
COMMON
S
2
60V
0.26A
3000mohm@10V / 3000mohm@4.5V / 3000mohm@2.5V
0.31A
0.3W
20V
GND
FBA_CMD<10>
FBA_CMD<15>
FBA_CMD<7>
FBA_CMD<5>
FBA_CMD<4>
FBA_CMD<13>
FBA_CMD<14>
FBA_CMD<12>
FBA_CMD<11>
FBA_CMD<8>
FBA_CMD<9>
FBA_CMD<6>
FBA_CMD<2>
FBA_CMD<1>
4
4
0.350 1.05V
FBA_CMD<12>
FBA_CMD<15>
FBA_CMD<5>
FBA_CMD<0>
FBA_CMD<8>
FBA_CMD<10>
FBA_CMD<11>
FBA_CMD<2>
FBA_CMD<1>
FBA_CMD<3>
FBA_CMD<4>
FBA_CMD<7>
FBA_CMD<6>
FBA_CMD<9>
FBA_VREFC
0.350 0.140A
1.05V
C573
R204
1 2
10nF
6.3V
10%
X5R
0402
COMMON
FBA_CMD<13>
FBA_CMD<14>
OUT
1 %
121ohm
COMMON0402
FBA_ZQ_1
COMMON
G3
RAS
L3
CAS
L12
WE
G12
CS
J4
ABI
H4
A0_A10
H5
A1_A9
H11
A2_BA0
H10
A3_BA3
K11
A4_BA2
K10
A5_BA1
K5
A6_A11
K4
A7_A8
J5
RFU_A12
J2
RESET
J3
CKE
J12
CLK
J11
CLK
A5
NC_RFU_A5
V5
NC_RFU_V5
6
J14
VREFC
J13
ZQ
J10
SEN
COMMON
Normal
J1
MF_VSS/SOE*
add 1k to VSS
B10
VSS
B5
VSS
D10
VSS
G10
VSS
G5
VSS
H1
VSS
H14
VSS
K1
VSS
K14
VSS
L10
VSS
L5
VSS
P10
VSS
T10
VSS
T5
VSS
A1
VSSQ
A12
VSSQ
A14
VSSQ
A3
VSSQ
C1
VSSQ
C11
VSSQ
C12
VSSQ
C14
VSSQ
C3
VSSQ
C4
VSSQ
E1
VSSQ
E12
VSSQ
E14
VSSQ
E3
VSSQ
F10
VSSQ
F5
VSSQ
H13
VSSQ
H2
VSSQ
K13
VSSQ
K2
VSSQ
M10
VSSQ
M5
VSSQ
N1
VSSQ
N12
VSSQ
N14
VSSQ
N3
VSSQ
R1
VSSQ
R11
VSSQ
R12
VSSQ
R14
VSSQ
R3
VSSQ
R4
VSSQ
V1
VSSQ
V12
VSSQ
V14
VSSQ
V3
VSSQ
GND
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
FBVDDQ
C10
C5
D11
G1
G11
G14
G4
L1
L11
L14
L4
P11
R10
R5
B1
B12
B14
B3
D1
D12
D14
D3
E10
E5
F1
F12
F14
F3
G13
G2
H12
H3
K12
K3
L13
L2
M1
M12
M14
M3
N10
N5
P1
P12
P14
P3
T1
T12
T14
T3
1
2
3
4
FBVDDQ
12
12
12
12
12
12
12
C147
C140
C742
C694
1uF
1uF
6.3V
10%
X5R
0402
COMMON
12
C621
4.7uF
6.3V
20%
X5R
0603
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
COMMON
1uF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
12
12
C159
C554
4.7uF
4.7uF
6.3V
6.3V
20%
20%
X5R
X5R
0603
0603
COMMON
COMMON
C738
1uF
1uF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
12
C158
4.7uF
6.3V
20%
X5R
0603
COMMON
12
C693
1uF
6.3V
10%
X5R
0402
COMMON
C162
10uF
6.3V
20%
X5R
0805
COMMON
12
C181
1uF
6.3V
10%
X5R
0402
COMMON
12
C550
10uF
6.3V
20%
X5R
0805
COMMON
C739
1uF
6.3V
10%
X5R
0402
COMMON
12
12
C712
C703
1uF
1uF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
12
12
C176
47uF
4V
20%
X5R
0805
COMMON
C173
47uF
4V
20%
X5R
0805
COMMON
GND
GND
C E
4
5
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MS-V320
MS-V320
MSI
MSI
MSI
Size Document Description Rev
Size Document Description Rev
Size Document Description Rev
Custom
Custom
Custom
Date:
Monday, November 17, 2014
Date:
Monday, November 17, 2014
Date:
FDBA
G
Monday, November 17, 2014
MS-V320
01_Table of Contents
01_Table of Contents
01_Table of Contents
Sheet of
Sheet of
Sheet of
H
2.0
2.0
2.0
534
534
534
A B C D E F G H
MEMORY: FBA Partition 63..32
1
2
GND
M503C
@memory.u_mem_sd_ddr5_x32(sym_6):page6_i479
BGA170
COMMON
Normal
J1
MF_VSS/SOE*
add 1k to VSS
B10
VSS
B5
VSS
D10
VSS
G10
VSS
G5
VSS
H1
VSS
H14
VSS
K1
VSS
K14
VSS
L10
VSS
L5
VSS
P10
VSS
T10
VSS
T5
VSS
A1
VSSQ
A12
VSSQ
A14
VSSQ
A3
VSSQ
C1
VSSQ
C11
VSSQ
C12
VSSQ
C14
VSSQ
C3
VSSQ
C4
VSSQ
E1
VSSQ
E12
VSSQ
E14
VSSQ
E3
VSSQ
F10
VSSQ
F5
VSSQ
H13
VSSQ
H2
VSSQ
K13
VSSQ
K2
VSSQ
M10
VSSQ
M5
VSSQ
N1
VSSQ
N12
VSSQ
N14
VSSQ
N3
VSSQ
R1
VSSQ
R11
VSSQ
R12
VSSQ
R14
VSSQ
R3
VSSQ
R4
VSSQ
V1
VSSQ
V12
VSSQ
V14
VSSQ
V3
VSSQ
FBVDDQ
C10
VDD
C5
VDD
D11
VDD
G1
VDD
G11
VDD
G14
VDD
G4
VDD
L1
VDD
L11
VDD
L14
VDD
L4
VDD
P11
VDD
R10
VDD
R5
VDD
B1
VDDQ
B12
VDDQ
B14
VDDQ
B3
VDDQ
D1
VDDQ
D12
VDDQ
D14
VDDQ
D3
VDDQ
E10
VDDQ
E5
VDDQ
F1
VDDQ
F12
VDDQ
F14
VDDQ
F3
VDDQ
G13
VDDQ
G2
VDDQ
H12
VDDQ
H3
VDDQ
K12
VDDQ
K3
VDDQ
L13
VDDQ
L2
VDDQ
M1
VDDQ
M12
VDDQ
M14
VDDQ
M3
VDDQ
N10
VDDQ
N5
VDDQ
P1
VDDQ
P12
VDDQ
P14
VDDQ
P3
VDDQ
T1
VDDQ
T12
VDDQ
T14
VDDQ
T3
VDDQ
M503B
FBA_CMD<19>
3
M503D
@memory.u_mem_sd_ddr5_x32(sym_1):page6_i380
BGA170
COMMON
C653
10uF
6.3V
20%
X5R
0805
COMMON
NORMAL
A4
DQ0
A2
DQ1
B4
DQ2
B2
DQ3
E4
DQ4
E2
DQ5
F4
DQ6
F2
DQ7
C2
EDC0
D2
DBI0
A10
VREFD
x16
x32
A11
DQ8
NC
A13
DQ9
NC
B11
DQ10
NC
B13
DQ11
NC
E11
DQ12
NC
E13
DQ13
NC
F11
DQ14
NC
F13
DQ15
NC
C13
EDC1
GND
D13
DBI1
NC
D4
WCK01
D5
WCK01
12
12
C620
C151
1uF
1uF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
12
C145
47uF
4V
20%
X5R
0805
COMMON
4
4
12
C150
1uF
6.3V
10%
X5R
0402
COMMON
12
C569
47uF
4V
20%
X5R
0805
COMMON
4
Fba_D<48>
4
Fba_D<49>
4
Fba_D<50>
4
Fba_D<51>
4
Fba_D<52>
4
Fba_D<53>
4
Fba_D<54>
4
Fba_D<55>
4
4
4
Fba_D<56>
4
Fba_D<57>
4
Fba_D<58>
4
Fba_D<59>
4
Fba_D<60>
4
Fba_D<61>
4
Fba_D<62>
4
Fba_D<63>
4
4
FBA_WCK67
IN
FBA_WCK67*
IN
FBA_D<48>
48
FBA_D<49>
49
FBA_D<50>
50
FBA_D<51>
51
FBA_D<52>
52
FBA_D<53>
53
FBA_D<54>
54
FBA_D<55>
55
FBA_EDC<6>
OUT
FBA_DBI<6>
OUT
FBA_D<56>
56
FBA_D<57>
57
FBA_D<58>
58
FBA_D<59>
59
FBA_D<60>
60
FBA_D<61>
61
FBA_D<62>
62
FBA_D<63>
63
FBA_EDC<7>
OUT
FBA_DBI<7>
OUT
OUT
OUT
C595
1uF
6.3V
10%
X5R
0402
COMMON
FBA_D<32>
32
FBA_D<33>
33
FBA_D<34>
34
FBA_D<35>
35
FBA_D<36>
36
FBA_D<37>
37
FBA_D<38>
38
FBA_D<39>
39
FBA_EDC<4>
FBA_DBI<4>
FBA_D<40>
40
FBA_D<41>
41
FBA_D<42>
42
FBA_D<43>
43
FBA_D<44>
44
FBA_D<45>
45
FBA_D<46>
46
FBA_D<47>
47
FBA_EDC<5>
OUT
FBA_DBI<5>
OUT
12
12
C619
C154
1uF
1uF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
12
12
C129
10uF
6.3V
20%
X5R
0805
COMMON
4
Fba_D<32>
4
Fba_D<33>
4
Fba_D<34>
4
Fba_D<35>
4
Fba_D<36>
4
Fba_D<37>
4
Fba_D<38>
4
Fba_D<39>
4
4
4
Fba_D<40>
4
Fba_D<41>
4
Fba_D<42>
4
Fba_D<43>
4
Fba_D<44>
4
Fba_D<45>
4
4
4
5
IN
IN
FBVDDQ
FBA_WCK45
FBA_WCK45*
12
C566
1uF
6.3V
10%
X5R
0402
COMMON
12
C665
4.7uF
6.3V
20%
X5R
0603
COMMON
4
Fba_D<46>
4
Fba_D<47>
4
4
12
12
C567
1uF
6.3V
10%
X5R
0402
COMMON
12
C182
1uF
6.3V
10%
X5R
0402
COMMON
12
C674
4.7uF
6.3V
20%
X5R
0603
COMMON
12
C646
1uF
6.3V
10%
X5R
0402
COMMON
12
12
C754
C130
4.7uF
4.7uF
6.3V
6.3V
20%
20%
X5R
X5R
0603
0603
COMMON
COMMON
M503A
@memory.u_mem_sd_ddr5_x32(sym_3):page6_i420
BGA170
COMMON
NORMAL
V11
DQ16
V13
DQ17
T11
DQ18
T13
DQ19
N11
DQ20
N13
DQ21
M11
DQ22
M13
DQ23
R13
EDC2
P13
DBI2
VREFD
x16
x32
V4
DQ24
NC
V2
DQ25
NC
T4
DQ26
NC
T2
DQ27
NC
N4
DQ28
NC
N2
DQ29
NC
M4
DQ30
NC
M2
DQ31
NC
R2
EDC3
NC
P2
DBI3
NC
P4
WCK23
P5
WCK23
FBA_CMD<19>
FBA_CMD<16>
FBA_CMD<26>
FBA_CMD<31>
FBA_CMD<23>
FBA_CMD<21>
FBA_CMD<20>
FBA_CMD<29>
FBA_CMD<30>
FBA_CMD<28>
FBA_CMD<27>
FBA_CMD<24>
FBA_CMD<25>
FBA_CMD<22>
FBA_CMD<18>
FBA_CMD<17>
V10
5
19
FBA_CMD<16>
16
FBA_CMD<26>
26
FBA_CMD<31>
31
FBA_CMD<23>
23
FBA_CMD<21>
21
FBA_CMD<20>
20
FBA_CMD<29>
29
FBA_CMD<30>
30
FBA_CMD<28>
28
FBA_CMD<27>
27
FBA_CMD<24>
24
FBA_CMD<25>
25
FBA_CMD<22>
22
FBA_CMD<18>
18
FBA_CMD<17>
17
4
4
IN
FBA_CLK1
IN
FBA_CLK1*
IN
12
GND GND
C713
10nF
6.3V
10%
X5R
0402
COMMON
R609
40.2ohm
1 %
0402
COMMON
FBA_CLK1_CM
GND
12
C726
10nF
16V
10%
X7R
0402
COMMON
R619
1 2
0402
1 %
FBA_CMD<28>
FBA_CMD<31>
FBA_CMD<21>
FBA_CMD<16>
FBA_CMD<24>
FBA_CMD<26>
FBA_CMD<27>
FBA_CMD<18>
FBA_CMD<17>
FBA_CMD<19>
FBA_CMD<20>
FBA_CMD<23>
FBA_CMD<22>
FBA_CMD<25>
FBA_CMD<29>
FBA_CMD<30>
R600
40.2ohm
1 %
0402
COMMON
121ohm
COMMON
FBA_VREFC
FBA_ZQ_2_B
@memory.u_mem_sd_ddr5_x32(sym_5):page6_i477
BGA170
COMMON
G3
RAS
L3
CAS
L12
WE
G12
CS
J4
ABI
H4
A0_A10
H5
A1_A9
H11
A2_BA0
H10
A3_BA3
K11
A4_BA2
K10
A5_BA1
K5
A6_A11
K4
A7_A8
J5
RFU_A12
J2
RESET
J3
CKE
J12
CLK
J11
CLK
A5
NC_RFU_A5
V5
NC_RFU_V5
J14
VREFC
J13
ZQ
J10
SEN
1
2
3
4
5
GND
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C E
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MS-V320
MS-V320
MSI
MSI
MSI
Size Document Description Rev
Size Document Description Rev
Size Document Description Rev
Custom
Custom
Custom
Monday, November 17, 2014
Monday, November 17, 2014
FDBA
G
Monday, November 17, 2014
MS-V320
01_Table of Contents
01_Table of Contents
01_Table of Contents
Sheet ofDate:
Sheet ofDate:
Sheet ofDate:
H
2.0
2.0
2.0
634
634
634
A B C D E F G H
MEMORY: FBB Partition 31..0
1
4
4
2
4
Fbb_D<0>
4
Fbb_D<1>
4
Fbb_D<2>
4
Fbb_D<3>
4
Fbb_D<4>
4
Fbb_D<5>
4
Fbb_D<6>
4
Fbb_D<7>
4
4
4
Fbb_D<8>
4
Fbb_D<9>
4
Fbb_D<10>
4
Fbb_D<11>
4
Fbb_D<12>
4
Fbb_D<13>
4
Fbb_D<14>
4
Fbb_D<15>
4
4
IN
IN
M3C
@memory.u_mem_sd_ddr5_x32(sym_6):page7_i570
BGA170
M3B
@memory.u_mem_sd_ddr5_x32(sym_5):page7_i567
BGA170
FBB_ZQ_1
COMMON
G3
RAS
L3
CAS
L12
WE
G12
CS
J4
ABI
H4
A0_A10
H5
A1_A9
H11
A2_BA0
H10
A3_BA3
K11
A4_BA2
K10
A5_BA1
K5
A6_A11
K4
A7_A8
J5
RFU_A12
J2
RESET
J3
CKE
J12
CLK
J11
CLK
A5
NC_RFU_A5
V5
NC_RFU_V5
8
J14
VREFC
J13
ZQ
J10
SEN
FBB_CMD<3>
Fbb_Cmd<3>
Fbb_Cmd<0>
4
4
Fbb_Cmd<10>
Fbb_Cmd<15>
Fbb_Cmd<7>
Fbb_Cmd<5>
Fbb_Cmd<4>
Fbb_Cmd<13>
Fbb_Cmd<14>
Fbb_Cmd<12>
Fbb_Cmd<11>
Fbb_Cmd<8>
Fbb_Cmd<9>
Fbb_Cmd<6>
Fbb_Cmd<2>
Fbb_Cmd<1>
FBB_VREF_Q
M3D
@memory.u_mem_sd_ddr5_x32(sym_1):page7_i480
BGA170
COMMON
FBB_D<0>
FBB_D<1>
FBB_D<2>
FBB_D<3>
FBB_D<4>
FBB_D<5>
FBB_D<6>
FBB_D<7>
FBB_EDC<0>
OUT
FBB_DBI<0>
OUT
FBB_D<8>
FBB_D<9>
FBB_D<10>
FBB_D<11>
FBB_D<12>
FBB_D<13>
FBB_D<14>
FBB_D<15>
FBB_EDC<1>
OUT
FBB_DBI<1>
OUT
FBB_WCK01
FBB_WCK01*
NORMAL
A4
DQ0
A2
DQ1
B4
DQ2
B2
DQ3
E4
DQ4
E2
DQ5
F4
DQ6
F2
DQ7
C2
EDC0
D2
DBI0
A10
VREFD
x16
x32
A11
DQ8
NC
A13
DQ9
NC
B11
DQ10
NC
B13
DQ11
NC
E11
DQ12
NC
E13
DQ13
NC
F11
DQ14
NC
F13
DQ15
NC
C13
EDC1
GND
D13
DBI1
NC
D4
WCK01
WCK01
4
4
D5
4
Fbb_D<16>
4
Fbb_D<17>
4
Fbb_D<18>
4
Fbb_D<19>
4
Fbb_D<20>
4
Fbb_D<21>
4
Fbb_D<22>
4
Fbb_D<23>
4
4
4
Fbb_D<24>
4
Fbb_D<25>
4
Fbb_D<26>
4
Fbb_D<27>
4
Fbb_D<28>
4
Fbb_D<29>
4
Fbb_D<30>
4
Fbb_D<31>
4
4
IN
IN
5,10,21
FBB_D<16>
16
FBB_D<17>
17
FBB_D<18>
18
FBB_D<19>
19
FBB_D<20>
20
FBB_D<21>
21
FBB_D<22>
22
FBB_D<23>
23
FBB_EDC<2>
OUT
FBB_DBI<2>
OUT
FBB_D<24>
FBB_D<25>
FBB_D<26>
FBB_D<27>
FBB_D<28>
FBB_D<29>
FBB_D<30>
FBB_D<31>
FBB_EDC<3>
OUT
FBB_DBI<3>
OUT
FBB_WCK23
FBB_WCK23*
GPIO10_FBVREF_SEL
IN
M3A
@memory.u_mem_sd_ddr5_x32(sym_3):page7_i519
BGA170
COMMON
NORMAL
V11
DQ16
V13
DQ17
T11
DQ18
T13
DQ19
N11
DQ20
N13
DQ21
M11
DQ22
M13
DQ23
R13
EDC2
P13
DBI2
VREFD
x16
x32
V4
DQ24
V2
DQ25
T4
DQ26
T2
DQ27
N4
DQ28
N2
DQ29
M4
DQ30
M2
DQ31
R2
EDC3
P2
DBI3
P4
WCK23
P5
WCK23
Use low VGSth part for Pascal
1G1D1S
V10
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
AO3420
D
Q34
@discrete.q_fet_n_enh(sym_2):page7_i518
SOT23_1G1D1S
G
1
COMMON
S
GND
3
2
60V
0.26A
3000mohm@10V / 3000mohm@4.5V / 3000mohm@2.5V
0.31A
0.3W
20V
3
FBB_CMD<0>
0
FBB_CMD<10>
10
FBB_CMD<15>
15
FBB_CMD<7>
7
FBB_CMD<5>
5
FBB_CMD<4>
4
FBB_CMD<13>
13
FBB_CMD<14>
14
FBB_CMD<12>
12
FBB_CMD<11>
11
FBB_CMD<8>
8
FBB_CMD<9>
9
FBB_CMD<6>
6
FBB_CMD<2>
FBB_CMD<1>
FBB_CLK0
IN
FBB_CLK0*
IN
R532
R533
40.2ohm
40.2ohm
1 %
1 %
0402
0402
COMMON
COMMON
FBB_CLK0_CM
12
C510
10nF
16V
10%
X7R
0402
R543
549ohm
1 %
0402
COMMON
R212
1.33k
1 %
0402
COMMON
GND
R214
931ohm
1 %
0402
COMMON
COMMON
12
GND GND
FBVDDQ
GND
1.05V0.350
FBB_CMD<12>
FBB_CMD<15>
FBB_CMD<5>
FBB_CMD<0>
FBB_CMD<8>
FBB_CMD<10>
FBB_CMD<11>
FBB_CMD<2>
FBB_CMD<1>
FBB_CMD<3>
FBB_CMD<4>
FBB_CMD<7>
FBB_CMD<6>
FBB_CMD<9>
FBB_VREFC
0.350 0.140A
1.05V
C509
R216 121ohm
1 2
10nF
6.3V
10%
X5R
0402
COMMON
FBB_CMD<13>
FBB_CMD<14>
OUT
0402
1 %
COMMON
COMMON
Normal
J1
MF_VSS/SOE*
add 1k to VSS
B10
VSS
B5
VSS
D10
VSS
G10
VSS
G5
VSS
H1
VSS
H14
VSS
K1
VSS
K14
VSS
L10
VSS
L5
VSS
P10
VSS
T10
VSS
T5
VSS
A1
VSSQ
A12
VSSQ
A14
VSSQ
A3
VSSQ
C1
VSSQ
C11
VSSQ
C12
VSSQ
C14
VSSQ
C3
VSSQ
C4
VSSQ
E1
VSSQ
E12
VSSQ
E14
VSSQ
E3
VSSQ
F10
VSSQ
F5
VSSQ
H13
VSSQ
H2
VSSQ
K13
VSSQ
K2
VSSQ
M10
VSSQ
M5
VSSQ
N1
VSSQ
N12
VSSQ
N14
VSSQ
N3
VSSQ
R1
VSSQ
R11
VSSQ
R12
VSSQ
R14
VSSQ
R3
VSSQ
R4
VSSQ
V1
VSSQ
V12
VSSQ
V14
VSSQ
V3
VSSQ
GND
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
FBVDDQ
C10
C5
D11
G1
G11
G14
G4
L1
L11
L14
L4
P11
R10
R5
B1
B12
B14
B3
D1
D12
D14
D3
E10
E5
F1
F12
F14
F3
G13
G2
H12
H3
K12
K3
L13
L2
M1
M12
M14
M3
N10
N5
P1
P12
P14
P3
T1
T12
T14
T3
1
2
3
4
FBVDDQ
12
12
12
12
C572
C185
1uF
1uF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
C514
4.7uF
6.3V
20%
X5R
0603
COMMON
COMMON
12
12
C513
C177
4.7uF
4.7uF
6.3V
6.3V
20%
20%
X5R
X5R
0603
0603
COMMON
COMMON
12
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C184
1uF
6.3V
10%
X5R
0402
COMMON
12
C539
1uF
6.3V
10%
X5R
0402
COMMON
12
C525
4.7uF
6.3V
20%
X5R
0603
COMMON
C602
1uF
6.3V
10%
X5R
0402
COMMON
12
C538
1uF
6.3V
10%
X5R
0402
COMMON
C518
10uF
6.3V
20%
X5R
0805
COMMON
12
12
C524
1uF
6.3V
10%
X5R
0402
COMMON
12
C522
C540
1uF
1uF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
C533
47uF
4V
20%
X5R
0805
COMMON
COMMON
12
C174
47uF
4V
20%
X5R
0805
COMMON
GND
12
C523
1uF
6.3V
10%
X5R
0402
COMMON
12
C571
10uF
6.3V
20%
X5R
0805
COMMON
12
12
C E
3
4
5
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MS-V320
MS-V320
MSI
MSI
MSI
Size Document Description Rev
Size Document Description Rev
Size Document Description Rev
Custom
Custom
Custom
Date:
Monday, November 17, 2014
Date:
Monday, November 17, 2014
Date:
FDBA
G
Monday, November 17, 2014
MS-V320
01_Table of Contents
01_Table of Contents
01_Table of Contents
Sheet of
Sheet of
Sheet of
H
2.0
2.0
2.0
734
734
734
A B C D E F G H
MEMORY: FBB Partition 63..32
1
2
GND
M502C
@memory.u_mem_sd_ddr5_x32(sym_6):page8_i500
BGA170
COMMON
Normal
J1
MF_VSS/SOE*
add 1k to VSS
B10
VSS
B5
VSS
D10
VSS
G10
VSS
G5
VSS
H1
VSS
H14
VSS
K1
VSS
K14
VSS
L10
VSS
L5
VSS
P10
VSS
T10
VSS
T5
VSS
A1
VSSQ
A12
VSSQ
A14
VSSQ
A3
VSSQ
C1
VSSQ
C11
VSSQ
C12
VSSQ
C14
VSSQ
C3
VSSQ
C4
VSSQ
E1
VSSQ
E12
VSSQ
E14
VSSQ
E3
VSSQ
F10
VSSQ
F5
VSSQ
H13
VSSQ
H2
VSSQ
K13
VSSQ
K2
VSSQ
M10
VSSQ
M5
VSSQ
N1
VSSQ
N12
VSSQ
N14
VSSQ
N3
VSSQ
R1
VSSQ
R11
VSSQ
R12
VSSQ
R14
VSSQ
R3
VSSQ
R4
VSSQ
V1
VSSQ
V12
VSSQ
V14
VSSQ
V3
VSSQ
FBVDDQ
C10
VDD
C5
VDD
D11
VDD
G1
VDD
G11
VDD
G14
VDD
G4
VDD
L1
VDD
L11
VDD
L14
VDD
L4
VDD
P11
VDD
R10
VDD
R5
VDD
B1
VDDQ
B12
VDDQ
B14
VDDQ
B3
VDDQ
D1
VDDQ
D12
VDDQ
D14
VDDQ
D3
VDDQ
E10
VDDQ
E5
VDDQ
F1
VDDQ
F12
VDDQ
F14
VDDQ
F3
VDDQ
G13
VDDQ
G2
VDDQ
H12
VDDQ
H3
VDDQ
K12
VDDQ
K3
VDDQ
L13
VDDQ
L2
VDDQ
M1
VDDQ
M12
VDDQ
M14
VDDQ
M3
VDDQ
N10
VDDQ
N5
VDDQ
P1
VDDQ
P12
VDDQ
P14
VDDQ
P3
VDDQ
T1
VDDQ
T12
VDDQ
T14
VDDQ
T3
VDDQ
M502B
@memory.u_mem_sd_ddr5_x32(sym_5):page8_i498
3
Fbb_Cmd<19>
M502D
@memory.u_mem_sd_ddr5_x32(sym_1):page8_i401
BGA170
COMMON
NORMAL
A4
DQ0
A2
DQ1
B4
DQ2
B2
DQ3
E4
DQ4
E2
DQ5
F4
DQ6
F2
DQ7
C2
EDC0
D2
DBI0
A10
VREFD
x16
x32
A11
DQ8
NC
A13
DQ9
NC
B11
DQ10
NC
B13
DQ11
NC
E11
DQ12
NC
E13
DQ13
NC
F11
DQ14
NC
F13
DQ15
NC
C13
EDC1
GND
D13
DBI1
4,8 4,8
4,8 4,8
C519
1uF
6.3V
10%
X5R
0402
COMMON
12
C170
10uF
6.3V
20%
X5R
0805
COMMON
NC
D4
WCK01
D5
WCK01
12
12
12
C155
C179
C175
47uF
4V
20%
X5R
0805
COMMON
1uF
6.3V
10%
X5R
0402
COMMON
C520
1uF
6.3V
10%
X5R
0402
COMMON
12
C141
47uF
4V
20%
X5R
0805
COMMON
1uF
6.3V
10%
X5R
0402
COMMON
12
4
Fbb_D<48>
4
Fbb_D<49>
4
Fbb_D<50>
4
Fbb_D<51>
4
Fbb_D<52>
4
Fbb_D<53>
4
Fbb_D<54>
4
Fbb_D<55>
4
4
4
Fbb_D<56>
4
Fbb_D<57>
4
Fbb_D<58>
4
Fbb_D<59>
4
Fbb_D<60>
4
Fbb_D<61>
4
Fbb_D<62>
4
Fbb_D<63>
4,8
4,8
4
4
IN
IN
FBB_WCK67
FBB_WCK67*
48
49
50
51
52
53
54
55
FBB_EDC<6>
OUT
FBB_DBI<6>
OUT
56
57
58
59
60
61
62
63
FBB_EDC<7>
OUT
FBB_DBI<7>
OUT
FBB_D<48>
FBB_D<49>
FBB_D<50>
FBB_D<51>
FBB_D<52>
FBB_D<53>
FBB_D<54>
FBB_D<55>
FBB_D<56>
FBB_D<57>
FBB_D<58>
FBB_D<59>
FBB_D<60>
FBB_D<61>
FBB_D<62>
FBB_D<63>
OUT
OUT
OUT
OUT
C541
1uF
6.3V
10%
X5R
0402
COMMON
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
12
12
FBB_EDC<4>
FBB_DBI<4>
FBB_EDC<5>
FBB_DBI<5>
C521
1uF
6.3V
10%
X5R
0402
COMMON
C537
10uF
6.3V
20%
X5R
0805
COMMON
FBB_D<32>
FBB_D<33>
FBB_D<34>
FBB_D<35>
FBB_D<36>
FBB_D<37>
FBB_D<38>
FBB_D<39>
FBB_D<40>
FBB_D<41>
FBB_D<42>
FBB_D<43>
FBB_D<44>
FBB_D<45>
FBB_D<46>
FBB_D<47>
12
4
Fbb_D<32>
4
Fbb_D<33>
4
Fbb_D<34>
4
Fbb_D<35>
4
Fbb_D<36>
4
Fbb_D<37>
4
Fbb_D<38>
4
Fbb_D<39>
4
4
4
Fbb_D<40>
4
Fbb_D<41>
4
Fbb_D<42>
4
Fbb_D<43>
4
Fbb_D<44>
4
C547
1uF
6.3V
10%
X5R
0402
COMMON
Fbb_D<45>
4
Fbb_D<46>
4
Fbb_D<47>
4,8
4,8
FBB_WCK45
IN
FBB_WCK45*
IN
12
12
12
C169
C166
1uF
1uF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
12
12
C535
C534
4.7uF
4.7uF
6.3V
6.3V
20%
20%
X5R
X5R
0603
0603
COMMON
COMMON
4
4
4
FBVDDQ
12
12
C548
1uF
6.3V
10%
X5R
0402
COMMON
12
12
C171
C172
4.7uF
4.7uF
6.3V
6.3V
20%
20%
X5R
X5R
0603
0603
COMMON
5
COMMON
M502A
@memory.u_mem_sd_ddr5_x32(sym_3):page8_i441
BGA170
COMMON
NORMAL
V11
DQ16
V13
DQ17
T11
DQ18
T13
DQ19
N11
DQ20
N13
DQ21
M11
DQ22
M13
DQ23
R13
EDC2
P13
DBI2
VREFD
x16
x32
V4
DQ24
NC
V2
DQ25
NC
T4
DQ26
NC
T2
DQ27
NC
N4
DQ28
NC
N2
DQ29
NC
M4
DQ30
NC
M2
DQ31
NC
R2
EDC3
NC
P2
DBI3
NC
P4
WCK23
P5
WCK23
V10
Fbb_Cmd<16>
Fbb_Cmd<26>
Fbb_Cmd<31>
Fbb_Cmd<23>
Fbb_Cmd<21>
Fbb_Cmd<20>
Fbb_Cmd<29>
Fbb_Cmd<30>
Fbb_Cmd<28>
Fbb_Cmd<27>
Fbb_Cmd<24>
Fbb_Cmd<25>
Fbb_Cmd<22>
Fbb_Cmd<18>
Fbb_Cmd<17>
4
4
7
FBB_CMD<19>
19
FBB_CMD<16>
16
FBB_CMD<26>
26
FBB_CMD<31>
31
FBB_CMD<23>
23
FBB_CMD<21>
21
FBB_CMD<20>
20
FBB_CMD<29>
29
FBB_CMD<30>
30
FBB_CMD<28>
28
FBB_CMD<27>
27
FBB_CMD<24>
24
FBB_CMD<25>
25
FBB_CMD<22>
22
FBB_CMD<18>
18
FBB_CMD<17>
17
FBB_CLK1
IN
FBB_CLK1*
IN
IN
12
C511
10nF
6.3V
10%
X5R
0402
COMMON
GND GND
R534
40.2ohm
1 %
0402
COMMON
FBB_CLK1_CM
GND
FBB_CMD<28>
FBB_CMD<31>
FBB_CMD<21>
FBB_CMD<16>
FBB_CMD<24>
FBB_CMD<26>
FBB_CMD<27>
FBB_CMD<18>
FBB_CMD<17>
FBB_CMD<19>
FBB_CMD<20>
FBB_CMD<23>
FBB_CMD<22>
FBB_CMD<25>
FBB_CMD<29>
FBB_CMD<30>
R535
40.2ohm
1 %
0402
COMMON
12
C512
10nF
16V
10%
X7R
0402
COMMON
R536 121ohm
1 2
COMMON
0402
1 %
FBB_VREFC
FBB_ZQ_2_B
BGA170
COMMON
G3
RAS
L3
CAS
L12
WE
G12
CS
J4
ABI
H4
A0_A10
H5
A1_A9
H11
A2_BA0
H10
A3_BA3
K11
A4_BA2
K10
A5_BA1
K5
A6_A11
K4
A7_A8
J5
RFU_A12
J2
RESET
J3
CKE
J12
CLK
J11
CLK
A5
NC_RFU_A5
V5
NC_RFU_V5
J14
VREFC
J13
ZQ
J10
SEN
1
2
3
4
5
GND
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C E
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MS-V320
MS-V320
MSI
MSI
MSI
Size Document Description Rev
Size Document Description Rev
Size Document Description Rev
Custom
Custom
Custom
Date:
Monday, November 17, 2014
Date:
Monday, November 17, 2014
Date:
FDBA
G
Monday, November 17, 2014
MS-V320
01_Table of Contents
01_Table of Contents
01_Table of Contents
Sheet of
Sheet of
Sheet of
H
2.0
2.0
2.0
834
834
834
A B C D E F G H
MEMORY: GPU Partition C/D
1
10
Fbc_D<0>
10
Fbc_D<1>
10
Fbc_D<2>
10
Fbc_D<3>
10
Fbc_D<4>
10
Fbc_D<5>
10
Fbc_D<6>
10
Fbc_D<7>
10
Fbc_D<8>
10
Fbc_D<9>
10
Fbc_D<10>
10
Fbc_D<11>
10
Fbc_D<12>
10
Fbc_D<13>
10
Fbc_D<14>
10
Fbc_D<15>
10
Fbc_D<16>
10
Fbc_D<17>
10
Fbc_D<18>
10
Fbc_D<19>
10
Fbc_D<20>
10
Fbc_D<21>
10
2
3
10
10
10
10
11
11
11
11
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
Fbc_D<22>
10
Fbc_D<23>
10
Fbc_D<24>
10
Fbc_D<25>
10
Fbc_D<26>
10
Fbc_D<27>
10
Fbc_D<28>
10
Fbc_D<29>
10
Fbc_D<30>
10
Fbc_D<31>
11
Fbc_D<32>
11
Fbc_D<33>
11
Fbc_D<34>
11
Fbc_D<35>
11
Fbc_D<36>
11
Fbc_D<37>
11
Fbc_D<38>
11
Fbc_D<39>
11
Fbc_D<40>
11
Fbc_D<41>
11
Fbc_D<42>
11
Fbc_D<43>
11
Fbc_D<44>
11
Fbc_D<45>
11
Fbc_D<46>
11
Fbc_D<47>
11
Fbc_D<48>
11
Fbc_D<49>
11
Fbc_D<50>
11
Fbc_D<51>
11
Fbc_D<52>
11
Fbc_D<53>
11
Fbc_D<54>
11
Fbc_D<55>
11
Fbc_D<56>
11
Fbc_D<57>
11
Fbc_D<58>
11
Fbc_D<59>
11
Fbc_D<60>
11
Fbc_D<61>
11
Fbc_D<62>
11
Fbc_D<63>
10
10
10
10
11
11
11
11
FBC_D<0>
0
FBC_D<1>
1
FBC_D<2>
2
FBC_D<3>
3
FBC_D<4>
4
FBC_D<5>
5
FBC_D<6>
6
FBC_D<7>
7
FBC_D<8>
8
FBC_D<9>
9
FBC_D<10>
10
FBC_D<11>
11
FBC_D<12>
12
FBC_D<13>
13
FBC_D<14>
14
FBC_D<15>
15
FBC_D<16>
16
FBC_D<17>
17
FBC_D<18>
18
FBC_D<19>
19
FBC_D<20>
20
FBC_D<21>
21
FBC_D<22>
22
FBC_D<23>
23
FBC_D<24>
24
FBC_D<25>
25
FBC_D<26>
26
FBC_D<27>
27
FBC_D<28>
28
FBC_D<29>
29
FBC_D<30>
30
FBC_D<31>
31
FBC_D<32>
32
FBC_D<33>
33
FBC_D<34>
34
FBC_D<35>
35
FBC_D<36>
36
FBC_D<37>
37
FBC_D<38>
38
FBC_D<39>
39
FBC_D<40>
40
FBC_D<41>
41
FBC_D<42>
42
FBC_D<43>
43
FBC_D<44>
44
FBC_D<45>
45
FBC_D<46>
46
FBC_D<47>
47
FBC_D<48>
48
FBC_D<49>
49
FBC_D<50>
50
FBC_D<51>
51
FBC_D<52>
52
FBC_D<53>
53
FBC_D<54>
54
FBC_D<55>
55
FBC_D<56>
56
FBC_D<57>
57
FBC_D<58>
58
FBC_D<59>
59
FBC_D<60>
60
FBC_D<61>
61
FBC_D<62>
62
FBC_D<63>
63
FBC_DBI<0>
BI
FBC_DBI<1>
BI
FBC_DBI<2>
BI
FBC_DBI<3>
BI
FBC_DBI<4>
BI
FBC_DBI<5>
BI
FBC_DBI<6>
BI
FBC_DBI<7>
BI
FBC_EDC<0>
IN
FBC_EDC<1>
IN
FBC_EDC<2>
IN
FBC_EDC<3>
IN
FBC_EDC<4>
IN
FBC_EDC<5>
IN
FBC_EDC<6>
IN
FBC_EDC<7>
IN
U_GPU_GB2B_192_BGA1428-TEST_GM206_GPU_GM206-INT-A1-GM206-INT-A1
G1D
@digital.u_gpu_gb2b_192(sym_4):page9_i2034
BGA1428
COMMON
4/18 FBC
AB5
AB6
AC7
AB4
AA5
AA4
W4
W5
W1
Y3
W2
W3
AB1
AB2
AC3
AB3
V5
V6
V4
T4
P7
R5
R6
R4
P3
R1
R2
R3
U3
V2
V3
V1
D13
G14
E13
F13
D12
E12
E10
D10
B10
C10
A10
C11
C13
A13
D14
B13
D9
D7
G8
E7
G5
F6
E6
D6
C5
B6
C6
A6
C8
C9
A9
B9
AA6
AA1
U7
T1
F12
A12
H6
A7
AB8
AA2
T5
T2
H13
B12
G7
B7
AA7
AA3
T6
T3
G12
C12
F7
C7
FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63
FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7
FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7
FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7
F
B
C
N
O
T
A
V
A
I
L
A
B
L
E
W
I
T
H
G
M
2
0
6
FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CMD29
FBC_CMD30
FBC_CMD31
FBC_CMD32
FBC_CMD33
FBC_CMD34
FBC_CMD35
FBC_WCK01
FBC_WCK01
FBC_WCKB01
FBC_WCKB01
FBC_WCK23
FBC_WCK23
FBC_WCKB23
FBC_WCKB23
FBC_WCK45
FBC_WCK45
FBC_WCKB45
FBC_WCKB45
FBC_WCK67
FBC_WCK67
FBC_WCKB67
FBC_WCKB67
FBC_PLL_AVDD
FBC_CMD<0>
N6
N5
FBC_CMD<1>
FBC_CMD<2>
N4
FBC_CMD<3>
N7
FBC_CMD<4>
N8
FBC_CMD<5>
M4
FBC_CMD<6>
M5
FBC_CMD<7>
M6
FBC_CMD<8>
L5
FBC_CMD<9>
L7
FBC_CMD<10>
M8
FBC_CMD<11>
G3
FBC_CMD<12>
F3
FBC_CMD<13>
F1
FBC_CMD<14>
F2
FBC_CMD<15>
G2
FBC_CMD<16>
D4
FBC_CMD<17>
E4
FBC_CMD<18>
F4
FBC_CMD<19>
G4
FBC_CMD<20>
H4
FBC_CMD<21>
D3
FBC_CMD<22>
D1
FBC_CMD<23>
B3
FBC_CMD<24>
C2
FBC_CMD<25>
L3
FBC_CMD<26>
N3
FBC_CMD<27>
M3
FBC_CMD<28>
M1
FBC_CMD<29>
E3
FBC_CMD<30>
D2
FBC_CMD<31>
M2
K8
K9
FBC_DEBUG0
K7
FBC_DEBUG1
L8
FBC_CLK0
N2
FBC_CLK0
FBC_CLK0
FBC_CLK1
FBC_CLK1
FBC_CLK0*
N1
FBC_CLK1
A4
FBC_CLK1*
B4
FBC_WCK01
V7
FBC_WCK01*
U8
Y8
W7
FBC_WCK23
Y7
FBC_WCK23*
W6
R8
T7
FBC_WCK45
E9
FBC_WCK45*
F9
H8
H9
FBC_WCK67
G11
FBC_WCK67*
F10
H11
G10
P8
C E
GND
12
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R568
1 2
0402
FB_PLLVDD
C612
0.1uF
16V
10%
X7R
0402
COMMON
CKE*
FBC_CMD<30>
FBC_CMD<14>
FBC_CMD<29>
FBC_CMD<13>
RST*
Fbc_Cmd<0>
Fbc_Cmd<1>
Fbc_Cmd<2>
Fbc_Cmd<3>
Fbc_Cmd<4>
Fbc_Cmd<5>
Fbc_Cmd<6>
Fbc_Cmd<7>
Fbc_Cmd<8>
Fbc_Cmd<9>
Fbc_Cmd<10>
Fbc_Cmd<11>
Fbc_Cmd<12>
Fbc_Cmd<13>
Fbc_Cmd<14>
Fbc_Cmd<15>
Fbc_Cmd<16>
Fbc_Cmd<17>
Fbc_Cmd<18>
Fbc_Cmd<19>
Fbc_Cmd<20>
Fbc_Cmd<21>
Fbc_Cmd<22>
Fbc_Cmd<23>
Fbc_Cmd<24>
Fbc_Cmd<25>
Fbc_Cmd<26>
Fbc_Cmd<27>
Fbc_Cmd<28>
Fbc_Cmd<29>
Fbc_Cmd<30>
Fbc_Cmd<31>
60.4ohm
R570 60.4ohm
DNI
1 2
1 %
FB_CLK
FB_CLK
FB_CLK
FB_CLK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
R546
10k
5 %
0402
COMMON
R569
10k
5 %
0402
COMMON
1 %
1
GDDR5_BGA170_MIRROR
0..31 32..63
CMD0 CS*
CMD1 A3_BA3
CMD2 A2_BA0
CMD3 A4_BA2
CMD4 A5_BA1
CMD5 WE*
CMD6 A7_A8
CMD7 A6_A11
CMD8 ABI*
CMD9 A12_RFU
CMD10 A0_A10
CMD11 A1_A9
CMD12 RAS*
FBVDDQ
DNI0402
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
FBVDDQ
10
10
11
11
10
10
10
10
11
11
11
11
R573
10k
5 %
0402
COMMON
R547
10k
5 %
0402
COMMON
4,15
IN
GND
CMD13 RST*
CMD14 CKE*
CMD15 CAS*
CMD32
CMD34 DBG0 DBG0
CMD16 CS*
CMD17 A3_BA3
CMD18 A2_BA0
CMD19 A4_BA2
CMD20 A5_BA1
CMD21 WE*
CMD22 A7_A8
CMD23 A6_A11
CMD24 ABI*
CMD25 A12_RFU
CMD26 A0_A10
CMD27 A1_A9
CMD28 RAS*
CMD29 RST*
CMD30 CKE*
CMD31 CAS*
CMD33
CMD35 DBG1 DBG1
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MS-V320
MS-V320
MSI
MSI
MSI
Size Document Description Rev
Size Document Description Rev
Size Document Description Rev
Custom
Custom
Custom
Date:
Monday, November 17, 2014
Date:
Monday, November 17, 2014
Date:
FDBA
G
Monday, November 17, 2014
MS-V320
01_Table of Contents
01_Table of Contents
01_Table of Contents
Sheet of
Sheet of
Sheet of
H
934
934
934
2
3
4
5
2.0
2.0
2.0
A B C D E F G H
MEMORY: FBC Partition 31..0
1
9
Fbc_D<0>
9
Fbc_D<1>
9
Fbc_D<2>
9
Fbc_D<3>
9
Fbc_D<4>
9
Fbc_D<5>
9
Fbc_D<6>
9
Fbc_D<7>
9
9
9
Fbc_D<8>
9
Fbc_D<9>
9
Fbc_D<10>
9
Fbc_D<11>
9
Fbc_D<12>
9
Fbc_D<13>
9
Fbc_D<14>
9
Fbc_D<15>
9
9
2
FBC_WCK01
IN
FBC_WCK01*
IN
3
0
1
2
3
4
5
6
7
FBC_EDC<0>
OUT
FBC_DBI<0>
OUT
8
9
10
11
12
13
14
15
FBC_EDC<1>
OUT
FBC_DBI<1>
OUT
FBC_D<0>
FBC_D<1>
FBC_D<2>
FBC_D<3>
FBC_D<4>
FBC_D<5>
FBC_D<6>
FBC_D<7>
FBC_D<8>
FBC_D<9>
FBC_D<10>
FBC_D<11>
FBC_D<12>
FBC_D<13>
FBC_D<14>
FBC_D<15>
M1D
@memory.u_mem_sd_ddr5_x32(sym_1):page10_i480
BGA170
COMMON
NORMAL
A4
DQ0
A2
DQ1
B4
DQ2
B2
DQ3
E4
DQ4
E2
DQ5
F4
DQ6
F2
DQ7
C2
EDC0
D2
DBI0
VREFD
x16
x32
A11
DQ8
NC
A13
DQ9
NC
B11
DQ10
NC
B13
DQ11
NC
E11
DQ12
NC
E13
DQ13
NC
F11
DQ14
NC
F13
DQ15
NC
C13
EDC1
GND
D13
DBI1
NC
D4
WCK01
D5
WCK01
M1C
@memory.u_mem_sd_ddr5_x32(sym_6):page10_i572
BGA170
M1B
@memory.u_mem_sd_ddr5_x32(sym_5):page10_i568
BGA170
FBC_ZQ_1
COMMON
G3
RAS
L3
CAS
L12
WE
G12
CS
J4
ABI
H4
A0_A10
H5
A1_A9
H11
A2_BA0
H10
A3_BA3
K11
A4_BA2
K10
A5_BA1
K5
A6_A11
K4
A7_A8
J5
RFU_A12
J2
RESET
J3
CKE
J12
CLK
J11
CLK
A5
NC_RFU_A5
V5
NC_RFU_V5
11
J14
VREFC
J13
ZQ
J10
SEN
FBC_CMD<3>
Fbc_Cmd<3>
Fbc_Cmd<0>
M1A
@memory.u_mem_sd_ddr5_x32(sym_3):page10_i519
BGA170
COMMON
V11
V13
T11
T13
N11
N13
M11
M13
R13
P13
V4
V2
T4
T2
N4
N2
M4
M2
R2
P2
P4
P5
NORMAL
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
EDC2
DBI2
V10
VREFD
x16
x32
DQ24
NC
DQ25
NC
DQ26
NC
DQ27
NC
DQ28
NC
DQ29
NC
DQ30
NC
DQ31
NC
EDC3
NC
DBI3
NC
WCK23
WCK23
Use low VGSth part for Pascal
AO3420
1G1D1S
D
G
1
S
3
Q514
@discrete.q_fet_n_enh(sym_2):page10_i518
SOT23_1G1D1S
COMMON
2
60V
0.26A
3000mohm@10V / 3000mohm@4.5V / 3000mohm@2.5V
0.31A
0.3W
20V
GND
9
Fbc_D<16>
9
Fbc_D<17>
9
Fbc_D<18>
9
Fbc_D<19>
9
Fbc_D<20>
9
Fbc_D<21>
9
Fbc_D<22>
9
Fbc_D<23>
9
A10
9
9
9
9
Fbc_D<24>
9
Fbc_D<25>
9
Fbc_D<26>
9
Fbc_D<27>
9
Fbc_D<28>
9
Fbc_D<29>
9
Fbc_D<30>
9
Fbc_D<31>
9
9
FBC_WCK23
IN
FBC_WCK23*
IN
5,7,21
FBC_D<16>
16
FBC_D<17>
17
FBC_D<18>
18
FBC_D<19>
19
FBC_D<20>
20
FBC_D<21>
21
FBC_D<22>
22
FBC_D<23>
23
FBC_EDC<2>
OUT
FBC_DBI<2>
OUT
FBC_D<24>
24
FBC_D<25>
25
FBC_D<26>
26
FBC_D<27>
27
FBC_D<28>
28
FBC_D<29>
29
FBC_D<30>
30
FBC_D<31>
31
FBC_EDC<3>
OUT
FBC_DBI<3>
OUT
GPIO10_FBVREF_SEL
IN
Fbc_Cmd<10>
Fbc_Cmd<15>
Fbc_Cmd<7>
Fbc_Cmd<5>
Fbc_Cmd<4>
Fbc_Cmd<13>
Fbc_Cmd<14>
Fbc_Cmd<12>
Fbc_Cmd<11>
Fbc_Cmd<8>
Fbc_Cmd<9>
Fbc_Cmd<6>
Fbc_Cmd<2>
Fbc_Cmd<1>
9
9
FBC_VREF_Q
3
FBC_CMD<0>
0
FBC_CMD<10>
10
FBC_CMD<15>
15
FBC_CMD<7>
7
FBC_CMD<5>
5
FBC_CMD<4>
4
FBC_CMD<13>
13
FBC_CMD<14>
14
FBC_CMD<12>
12
FBC_CMD<11>
11
FBC_CMD<8>
8
FBC_CMD<9>
9
FBC_CMD<6>
6
FBC_CMD<2>
2
FBC_CMD<1>
1
FBC_CLK0
IN
FBC_CLK0*
IN
R571
R567
40.2ohm
40.2ohm
1 %
1 %
0402
0402
COMMON
COMMON
FBC_CLK0_CM
12
C603
10nF
16V
R556
549ohm
1 %
0402
COMMON
R208
1.33k
1 %
0402
COMMON
GND
R209
931ohm
1 %
0402
COMMON
10%
X7R
0402
COMMON
12
GND GND
FBVDDQ
GND
1.05V0.350
FBC_CMD<12>
FBC_CMD<15>
FBC_CMD<5>
FBC_CMD<0>
FBC_CMD<8>
FBC_CMD<10>
FBC_CMD<11>
FBC_CMD<2>
FBC_CMD<1>
FBC_CMD<3>
FBC_CMD<4>
FBC_CMD<7>
FBC_CMD<6>
FBC_CMD<9>
FBC_VREFC
0.350 0.140A
1.05V
C617
R206 121ohm
1 2
10nF
6.3V
10%
X5R
0402
COMMON
FBC_CMD<13>
FBC_CMD<14>
OUT
0402 COMMON
1 %
COMMON
Normal
J1
MF_VSS/SOE*
add 1k to VSS
B10
VSS
B5
VSS
D10
VSS
G10
VSS
G5
VSS
H1
VSS
H14
VSS
K1
VSS
K14
VSS
L10
VSS
L5
VSS
P10
VSS
T10
VSS
T5
VSS
A1
VSSQ
A12
VSSQ
A14
VSSQ
A3
VSSQ
C1
VSSQ
C11
VSSQ
C12
VSSQ
C14
VSSQ
C3
VSSQ
C4
VSSQ
E1
VSSQ
E12
VSSQ
E14
VSSQ
E3
VSSQ
F10
VSSQ
F5
VSSQ
H13
VSSQ
H2
VSSQ
K13
VSSQ
K2
VSSQ
M10
VSSQ
M5
VSSQ
N1
VSSQ
N12
VSSQ
N14
VSSQ
N3
VSSQ
R1
VSSQ
R11
VSSQ
R12
VSSQ
R14
VSSQ
R3
VSSQ
R4
VSSQ
V1
VSSQ
V12
VSSQ
V14
VSSQ
V3
VSSQ
GND
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
FBVDDQ
C10
C5
D11
G1
G11
G14
G4
L1
L11
L14
L4
P11
R10
R5
B1
B12
B14
B3
D1
D12
D14
D3
E10
E5
F1
F12
F14
F3
G13
G2
H12
H3
K12
K3
L13
L2
M1
M12
M14
M3
N10
N5
P1
P12
P14
P3
T1
T12
T14
T3
1
2
3
4
FBVDDQ
12
12
12
12
C580
C622
1uF
1uF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
12
C183
4.7uF
6.3V
20%
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
X5R
0603
COMMON
12
12
C553
C558
4.7uF
4.7uF
6.3V
6.3V
20%
20%
X5R
X5R
0603
0603
COMMON
COMMON
C576
1uF
6.3V
10%
X5R
0402
COMMON
12
C153
1uF
6.3V
10%
X5R
0402
COMMON
12
C156
4.7uF
6.3V
20%
X5R
0603
COMMON
C634
1uF
6.3V
10%
X5R
0402
COMMON
12
12
12
C152
1uF
6.3V
10%
X5R
0402
COMMON
C555
10uF
6.3V
20%
X5R
0805
COMMON
12
12
C583
1uF
6.3V
10%
X5R
0402
COMMON
12
C575
C149
1uF
1uF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
12
12
C611
C532
47uF
47uF
4V
4V
20%
20%
X5R
X5R
0805
0805
COMMON
COMMON
GND
C636
1uF
6.3V
10%
X5R
0402
COMMON
12
C157
10uF
6.3V
20%
X5R
0805
COMMON
C E
4
5
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MS-V320
MS-V320
MSI
MSI
MSI
Size Document Description Rev
Size Document Description Rev
Size Document Description Rev
Custom
Custom
Custom
Date:
Monday, November 17, 2014
Date:
Monday, November 17, 2014
Date:
FDBA
G
Monday, November 17, 2014
MS-V320
01_Table of Contents
01_Table of Contents
01_Table of Contents
Sheet of
Sheet of
Sheet of
H
10 34
10 34
10 34
2.0
2.0
2.0
A B C D E F G H
MEMORY: FBC Partition 63..32
1
2
3
M501D
@memory.u_mem_sd_ddr5_x32(sym_1):page11_i400
BGA170
COMMON
NORMAL
A4
DQ0
A2
DQ1
B4
DQ2
B2
DQ3
E4
DQ4
E2
DQ5
F4
DQ6
F2
DQ7
C2
EDC0
D2
DBI0
A10
VREFD
x16
x32
A11
DQ8
NC
A13
DQ9
NC
B11
DQ10
NC
B13
DQ11
NC
E11
DQ12
NC
E13
DQ13
NC
F11
DQ14
NC
F13
DQ15
NC
C13
EDC1
GND
D13
DBI1
NC
D4
WCK01
D5
WCK01
12
12
12
C167
1uF
6.3V
10%
X5R
0402
COMMON
C551
4.7uF
6.3V
20%
X5R
0603
COMMON
C543
1uF
6.3V
10%
X5R
0402
COMMON
12
C178
1uF
6.3V
10%
X5R
0402
COMMON
12
C560
10uF
6.3V
20%
X5R
0805
COMMON
C544
1uF
6.3V
10%
X5R
0402
COMMON
12
12
C549
4.7uF
6.3V
20%
X5R
0603
COMMON
9
Fbc_D<48>
9
Fbc_D<49>
9
Fbc_D<50>
9
Fbc_D<51>
9
Fbc_D<52>
9
Fbc_D<53>
9
Fbc_D<54>
9
Fbc_D<55>
9
9
9
Fbc_D<56>
9
Fbc_D<57>
9
Fbc_D<58>
9
Fbc_D<59>
9
Fbc_D<60>
9
Fbc_D<61>
9
Fbc_D<62>
9
Fbc_D<63>
9
9
9
9
12
12
C516
1uF
6.3V
10%
X5R
0402
COMMON
12
C557
10uF
6.3V
20%
X5R
0805
COMMON
C168
1uF
6.3V
10%
X5R
0402
COMMON
FBC_WCK67
IN
FBC_WCK67*
IN
12
12
C545
1uF
6.3V
10%
X5R
0402
COMMON
12
12
C582
C629
47uF
47uF
4V
4V
20%
20%
X5R
X5R
0805
0805
COMMON
COMMON
C546
1uF
6.3V
10%
X5R
0402
COMMON
FBC_D<48>
48
FBC_D<49>
49
FBC_D<50>
50
FBC_D<51>
51
FBC_D<52>
52
FBC_D<53>
53
FBC_D<54>
54
FBC_D<55>
55
FBC_EDC<6>
BI
FBC_DBI<6>
BI
FBC_D<56>
56
FBC_D<57>
57
FBC_D<58>
58
FBC_D<59>
59
FBC_D<60>
60
FBC_D<61>
61
FBC_D<62>
62
FBC_D<63>
63
FBC_EDC<7>
BI
FBC_DBI<7>
BI
GND
C E
BI
BI
BI
BI
C163
4.7uF
6.3V
20%
X5R
0603
COMMON
FBC_D<32>
32
FBC_D<33>
33
FBC_D<34>
34
FBC_D<35>
35
FBC_D<36>
36
FBC_D<37>
37
FBC_D<38>
38
FBC_D<39>
39
FBC_EDC<4>
FBC_DBI<4>
FBC_D<40>
FBC_D<41>
FBC_D<42>
FBC_D<43>
FBC_D<44>
FBC_D<45>
FBC_D<46>
FBC_D<47>
FBC_EDC<5>
FBC_DBI<5>
12
12
C515
C517
1uF
1uF
6.3V
6.3V
10%
10%
X5R
X5R
0402
0402
COMMON
COMMON
12
C161
4.7uF
6.3V
20%
X5R
0603
COMMON
9
Fbc_D<32>
9
Fbc_D<33>
9
Fbc_D<34>
9
Fbc_D<35>
9
Fbc_D<36>
9
Fbc_D<37>
9
Fbc_D<38>
9
Fbc_D<39>
9
9
9
Fbc_D<40>
9
Fbc_D<41>
9
Fbc_D<42>
9
4
9
9
Fbc_D<43>
9
Fbc_D<44>
9
Fbc_D<45>
9
Fbc_D<46>
9
Fbc_D<47>
9
9
FBC_WCK45
IN
FBC_WCK45*
IN
FBVDDQ
12
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
M501A
V11
V13
T11
T13
N11
N13
M11
M13
R13
P13
V4
V2
T4
T2
N4
N2
M4
M2
R2
P2
P4
P5
@memory.u_mem_sd_ddr5_x32(sym_3):page11_i442
BGA170
COMMON
NORMAL
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
EDC2
DBI2
V10
VREFD
x16
x32
DQ24
NC
DQ25
NC
DQ26
NC
DQ27
NC
DQ28
NC
DQ29
NC
DQ30
NC
DQ31
NC
EDC3
NC
DBI3
NC
WCK23
WCK23
10
Fbc_Cmd<19>
Fbc_Cmd<16>
Fbc_Cmd<26>
Fbc_Cmd<31>
Fbc_Cmd<23>
Fbc_Cmd<21>
Fbc_Cmd<20>
Fbc_Cmd<29>
Fbc_Cmd<30>
Fbc_Cmd<28>
Fbc_Cmd<27>
Fbc_Cmd<24>
Fbc_Cmd<25>
Fbc_Cmd<22>
Fbc_Cmd<18>
Fbc_Cmd<17>
1
2
GND
G
M501C
@memory.u_mem_sd_ddr5_x32(sym_6):page11_i499
BGA170
COMMON
Normal
J1
MF_VSS/SOE*
add 1k to VSS
B10
VSS
B5
VSS
D10
VSS
G10
VSS
G5
VSS
H1
VSS
H14
VSS
K1
VSS
K14
VSS
L10
VSS
L5
VSS
P10
VSS
T10
VSS
T5
VSS
A1
VSSQ
A12
VSSQ
A14
VSSQ
A3
VSSQ
C1
VSSQ
C11
VSSQ
C12
VSSQ
C14
VSSQ
C3
VSSQ
C4
VSSQ
E1
VSSQ
E12
VSSQ
E14
VSSQ
E3
VSSQ
F10
VSSQ
F5
VSSQ
H13
VSSQ
H2
VSSQ
K13
VSSQ
K2
VSSQ
M10
VSSQ
M5
VSSQ
N1
VSSQ
N12
VSSQ
N14
VSSQ
N3
VSSQ
R1
VSSQ
R11
VSSQ
R12
VSSQ
R14
VSSQ
R3
VSSQ
R4
VSSQ
V1
VSSQ
V12
VSSQ
V14
VSSQ
V3
VSSQ
MSI
MSI
MSI
Size Document Description Rev
Size Document Description Rev
Size Document Description Rev
Custom
Custom
Custom
Date:
Date:
Date:
C10
VDD
C5
VDD
D11
VDD
G1
VDD
G11
VDD
G14
VDD
G4
VDD
L1
VDD
L11
VDD
L14
VDD
L4
VDD
P11
VDD
R10
VDD
R5
VDD
B1
VDDQ
B12
VDDQ
B14
VDDQ
B3
VDDQ
D1
VDDQ
D12
VDDQ
D14
VDDQ
D3
VDDQ
E10
VDDQ
E5
VDDQ
F1
VDDQ
F12
VDDQ
F14
VDDQ
F3
VDDQ
G13
VDDQ
G2
VDDQ
H12
VDDQ
H3
VDDQ
K12
VDDQ
K3
VDDQ
L13
VDDQ
L2
VDDQ
M1
VDDQ
M12
VDDQ
M14
VDDQ
M3
VDDQ
N10
VDDQ
N5
VDDQ
P1
VDDQ
P12
VDDQ
P14
VDDQ
P3
VDDQ
T1
VDDQ
T12
VDDQ
T14
VDDQ
T3
VDDQ
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MS-V320
MS-V320
MS-V320
01_Table of Contents
01_Table of Contents
01_Table of Contents
Monday, November 17, 2014
Monday, November 17, 2014
Monday, November 17, 2014
FBVDDQ
Sheet of
Sheet of
Sheet of
H
11 34
11 34
11 34
3
4
5
2.0
2.0
2.0
M501B
@memory.u_mem_sd_ddr5_x32(sym_5):page11_i445
BGA170
COMMON
G3
RAS
L3
CAS
L12
WE
G12
CS
J4
ABI
H4
A0_A10
H5
A1_A9
H11
A2_BA0
H10
A3_BA3
K11
A4_BA2
K10
A5_BA1
K5
A6_A11
K4
A7_A8
J5
RFU_A12
J2
RESET
J3
CKE
J12
CLK
J11
CLK
A5
NC_RFU_A5
V5
NC_RFU_V5
J14
VREFC
J13
ZQ
J10
SEN
R529
40.2ohm
1 %
0402
COMMON
FBC_CLK1_CM
GND
R530
40.2ohm
1 %
0402
COMMON
12
C508
10nF
16V
10%
X7R
0402
COMMON
R531
1 2
0402
1 %
FBC_CMD<28>
FBC_CMD<31>
FBC_CMD<21>
FBC_CMD<16>
FBC_CMD<24>
FBC_CMD<26>
FBC_CMD<27>
FBC_CMD<18>
FBC_CMD<17>
FBC_CMD<19>
FBC_CMD<20>
FBC_CMD<23>
FBC_CMD<22>
FBC_CMD<25>
FBC_CMD<29>
FBC_CMD<30>
121ohm
COMMON
FBC_VREFC
FBC_ZQ_2_B
FBC_CMD<19>
19
FBC_CMD<16>
16
FBC_CMD<26>
26
FBC_CMD<31>
31
FBC_CMD<23>
23
FBC_CMD<21>
21
FBC_CMD<20>
20
FBC_CMD<29>
29
FBC_CMD<30>
30
FBC_CMD<28>
28
FBC_CMD<27>
27
FBC_CMD<24>
24
FBC_CMD<25>
25
FBC_CMD<22>
22
FBC_CMD<18>
18
FBC_CMD<17>
17
9
9
IN
IN
IN
12
GND GND
FBC_CLK1
FBC_CLK1*
C507
10nF
6.3V
10%
X5R
0402
COMMON
FDBA
Loading...