MOTOROLA SN74LS393D, SN74LS393DR2, SN74LS393M, SN74LS393MEL, SN74LS393ML1 Datasheet
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5-1
FAST AND LS TTL DAT A
DUAL DECADE COUNTER;
DUAL 4-STAGE
BINARY COUNTER
The SN54/74LS390 and SN54/74LS393 each contain a pair of high-speed
4-stage ripple counters. Each half of the LS390 is partitioned into a
divide-by-two section and a divide-by five section, with a separate clock input
for each section. The two sections can be connected to count in the 8.4.2.1
BCD code or they can count in a biquinary sequence to provide a square wave
(50% duty cycle) at the final output.
Each half of the LS393 operates as a Modulo-16 binary divider, with the last
three stages triggered in a ripple fashion. In both the LS390 and the LS393,
the flip-flops are triggered by a HIGH-to-LOW transition of their CP inputs.
Each half of each circuit type has a Master Reset input which responds to a
HIGH signal by forcing all four outputs to the LOW state.
• Dual Versions of LS290 and LS293
• LS390 has Separate Clocks Allowing ÷2, ÷2.5, ÷5
• Individual Asynchronous Clear for Each Counter
• Typical Max Count Frequency of 50 MHz
• Input Clamp Diodes Minimize High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
SN54/74LS390
SN54/74LS393
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
14 13 12 11 10 9
123456
8
7
VCCCP
MR Q0Q1Q2Q
3
CP
MR Q0Q1Q2Q3GND
14 13 12 1 1 10 9
123456
7
16 15
8
V
CC
CP
0
CP
0
MR Q0CP
1
Q
2
Q
1
Q
3
MR Q0CP
1Q1Q2Q3
GND
SN54/74LS390
SN54/74LS393
LOW POWER SCHOTTKY
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
16
1
D SUFFIX
SOIC
CASE 751B-03
DUAL DECADE COUNTER;
DUAL 4-ST AGE
BINARY COUNTER
J SUFFIX
CERAMIC
CASE 632-08
N SUFFIX
PLASTIC
CASE 646-06
14
1
14
1
14
1
D SUFFIX
SOIC
CASE 751A-02
5-2
FAST AND LS TTL DATA
SN54/74LS390 • SN54/74LS393
PIN NAMES LOADING (Note a)
HIGH
LOW
CP Clock (Active LOW going edge)
Input to +16 (LS393) 0.5 U.L. 1.0 U.L.
CP
0
Clock (Active LOW going edge)
Input to ÷2 (LS390) 0.5 U.L. 1.0 U.L.
CP
1
Clock (Active LOW going edge)
Input to ÷5 (LS390) 0.5 U.L. 1.5 U.L.
MR Master Reset (Active HIGH) Input 0.5 U.L. 0.25 U.L.
Q0–Q
3
Flip-Flop outputs (Note b) 10 U.L. 5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b) T emperature Ranges.
FUNCTIONAL DESCRIPTION
Each half of the SN54/74LS393 operates in the Modulo 16
binary sequence, as indicated in the ÷16 Truth T able. The first
flip-flop is triggered by HIGH-to-LOW transitions of the CP
input signal. Each of the other flip-flops is triggered by a
HIGH-to-LOW transition of the Q output of the preceding
flip-flop. Thus state changes of the Q outputs do not occur
simultaneously. This means that logic signals derived from
combinations of these outputs will be subject to decoding
spikes and, therefore, should not be used as clocks for other
counters, registers or flip-flops. A HIGH signal on MR forces
all outputs to the LOW state and prevents counting.
Each half of the LS390 contains a ÷5 section that is
independent except for the common MR function. The ÷ 5
section operates in 4.2.1 binary sequence, as shown in the ÷5
Truth Table, with the third stage output exhibiting a 20% duty
cycle when the input frequency is constant. To obtain a ÷10
function having a 50% duty cycle output, connect the input
signal to CP
1
and connect the Q3 output to the CP0 input; the
Q0 output provides the desired 50% duty cycle output. If the
input frequency is connected to CP
0
and the Q0 output is
connected to CP
1
, a decade divider operating in the 8.4.2.1
BCD code is obtained, as shown in the BCD Truth T able. Since
the flip-flops change state asynchronously, logic signals
derived from combinations of LS390 outputs are also subject
to decoding spikes. A HIGH signal on MR forces all outputs
LOW and prevents counting.
SN54/74LS390 LOGIC DIAGRAM (one half shown)
SN54/74LS393 LOGIC DIAGRAM (one half shown)
CP
1
CP
0
MR
MR
CP
KCP J
C
D
Q
KCP J
C
D
Q
KCP J
C
D
Q
KCP
J
C
D
Q
KCP J
C
D
Q
KCP J
C
D
Q
KCP J
C
D
Q
KCP J
C
D
Q
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
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