Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6
1 Publication Order Number:
SN74LS373/D
SN74LS373 SN74LS374
Octal Transparent Latch
with 3-State Outputs;
Octal D-Type Flip-Flop
with 3-State Output
The SN74LS373 consists of eight latches with 3-state outputs for
bus organized system applications. The flip-flops appear transparent
to the data (data changes asynchronously) when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup times is
latched. Data appears on the bus when the Output Enable (OE
) is
LOW . When OE is HIGH the bus output is in the high impedance state.
The SN74LS374 is a high-speed, low-power Octal D-type Flip-Flop
featuring separate D-type inputs for each flip-flop and 3-state outputs
for bus oriented applications. A buffered Clock (CP) and Output
Enable (OE) is common to all flip-flops. The SN74LS374 is
manufactured using advanced Low Power Schottky technology and is
compatible with all ON Semiconductor TTL families.
• Eight Latches in a Single Package
• 3-State Outputs for Bus Interfacing
• Hysteresis on Latch Enable
• Edge-Triggered D-Type Inputs
• Buffered Positive Edge-Triggered Clock
• Hysteresis on Clock Input to Improve Noise Margin
• Input Clamp Diodes Limit High Speed Termination Effects
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
Supply Voltage 4.75 5.0 5.25 V
T
A
Operating Ambient
T emperature Range
0 25 70 °C
I
OH
Output Current – High –2.6 mA
I
OL
Output Current – Low 24 mA
LOW
POWER
SCHOTTKY
Device Package Shipping
ORDERING INFORMATION
SN74LS373N 16 Pin DIP 1440 Units/Box
SN74LS373DW 16 Pin
SOIC
DW SUFFIX
CASE 751D
http://onsemi.com
2500/Tape & Reel
PLASTIC
N SUFFIX
CASE 738
20
1
20
1
SN74LS374N 16 Pin DIP 1440 Units/Box
SN74LS374DW 16 Pin
2500/Tape & Reel
SN74LS373 SN74LS374
http://onsemi.com
2
CONNECTION DIAGRAM DIP (TOP VIEW)
Data Inputs
Latch Enable (Active HIGH) Input
Clock (Active HIGH Going Edge) Input
Output Enable (Active LOW) Input
Outputs
D
0
– D
7
LE
CP
OE
O0 – O
7
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
65 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
HIGH LOW
(Note a)
LOADING
PIN NAMES
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
SN74LS373
SN74LS374
18 17 16 15 14 13
1234 56
7
20 19
8
V
CC
OE
O7D7D6O
6
D
5
O
5
D
4
O0D0D1O1O2D2D
3
910
O
3
GND
12
O
4
LE
18 17 16 15 14 13
123456
7
20 19
8
V
CC
OE
O7D7D6O
6
D
5
O
5
D
4
O0D0D1O1O2D2D
3
910
O
3
GND
12 11
O
4
CP
11
TRUTH TABLE
LS373
D
n
LE OE O
n
H H L H
L H L L
X L L Q
0
X X H Z*
LS374
D
n
LE OE O
n
H L H
L L L
X X H Z*
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
* Note: Contents of flip-flops unaffected by the state of the Output Enable input (OE
).
SN74LS373 SN74LS374
http://onsemi.com
3
LOGIC DIAGRAMS
SN74LS373
SN74LS374
D
D
G
Q
CP
QQ
CP
OE
OE
LE
LATCH
ENABLE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
D
0
14
1
26
73 84
5 9
11
12 16
13
15
VCC = PIN 20
GND = PIN 10
= PIN NUMBERS
D
G
Q
D
1
D
G
Q
D
2
D
G
Q
D
3
D
G
Q
D
4
D
G
Q
D
5
D
G
Q
D
6
D
G
Q
D
7
17 18
19
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
265 9 12 1615 19
D
0
1473 84 13
D
1
D
2
D
3
D
4
D
5
D
6
D
7
17 18
1
11
DCP
QQ
DCP
QQ
DCP
QQ
DCP
QQ
DCP
QQ
DCP
QQ
DCP
QQ
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol Parameter
Min Typ Max
Unit Test Conditions
V
IH
Input HIGH Voltage 2.0 V
Guaranteed Input HIGH Voltage for
All Inputs
V
IL
Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
V
IK
Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
V
OH
Output HIGH Voltage 2.4 3.1 V
VCC = MIN, IOH = MAX, VIN = V
IH
or VIL per Truth Table
p
0.25 0.4 V IOL = 12 mA
VCC = VCC MIN,
VOLOutput LOW Voltage
0.35 0.5 V IOL = 24 mA
V
IN
=
V
IL
or
V
IH
per Truth Table
I
OZH
Output Off Current HIGH 20 µA VCC = MAX, V
OUT
= 2.7 V
I
OZL
Output Off Current LOW –20 µA VCC = MAX, V
OUT
= 0.4 V
p
20 µA VCC = MAX, VIN = 2.7 V
IIHInput HIGH Current
0.1 mA VCC = MAX, VIN = 7.0 V
I
IL
Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V
I
OS
Short Circuit Current (Note 1) –30 –130 mA VCC = MAX
I
CC
Power Supply Current 40 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
SN74LS373 SN74LS374
http://onsemi.com
4
AC CHARACTERISTICS (T
A
= 25°C, VCC = 5.0 V)
Limits
LS373 LS374
Symbol Parameter
Min Typ Max Min Typ Max
Unit Test Conditions
f
MAX
Maximum Clock Frequency 35 50 MHz
t
PLH
t
PHL
Propagation Delay,
Data to Output
121218
18
ns
p
t
PLH
t
PHL
Clock or Enable
to Output
201830
30
151928
28
ns
C
L
= 45 pF,
R
L
= 667 Ω
t
PZH
t
PZL
Output Enable Time
152528
36
202128
28
ns
t
PHZ
t
PLZ
Output Disable Time
121520
25
121520
25
ns CL = 5.0 pF
AC SETUP REQUIREMENTS (T
A
= 25°C, VCC = 5.0 V)
Limits
LS373 LS374
Symbol Parameter
Min Max Min Max
Unit
t
W
Clock Pulse Width 15 15 ns
t
s
Setup Time 5.0 20 ns
t
h
Hold Time 20 0 ns
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to LE transition from HIGH-to-LOW in order to
be recognized and transferred to the outputs.
HOLD TIME (t
h
) — is defined as the minimum time
following the LE transition from HIGH-to-LOW that the
logic level must be maintained at the input in order to ensure
continued recognition.
SN74LS373 SN74LS374
http://onsemi.com
5
SN74LS373
AC WAVEFORMS
Figure 1.
t
W
t
W
LE
1.3 V
OUTPUT
D
n
t
s
t
h
t
PLH
t
PHL
Figure 2.
Figure 3.
1.3 V
1.3 V 1.3 V
OE
V
OUT
OE
V
OUT
t
PHZ
1.3 V 1.3 V
t
PZL
t
PLZ
V
OL
1.3 V
V
OH
0.5 V
t
PZH
1.3 V
1.3 V
0.5 V
SW2CL*
5.0 kΩ
SW1
V
CC
R
L
TO OUTPUT
UNDER TEST
Figure 4.
* Includes Jig and Probe Capacitance.
AC LOAD CIRCUIT
SWITCH POSITIONS
Closed
Open
Closed
Closed
Open
Closed
Closed
Closed
t
PZH
t
PZL
t
PLZ
t
PHZ
SW2SW1SYMBOL
SN74LS373 SN74LS374
http://onsemi.com
6
SN74LS374
AC WAVEFORMS
OE
V
OUT
1.3 V 1.3 V
t
PZL
t
PLZ
V
OL
1.3 V
≈ 1.3 V
0.5 V
SW2CL*
5.0 kΩ
SW1
V
CC
R
L
TO OUTPUT
UNDER TEST
* Includes Jig and Probe Capacitance.
AC LOAD CIRCUIT
CP
D
n
OUTPUT
t
PLH
tWHt
W
L
1.3 V 1.3 V 1.3 V
1.3 V
1.3 V 1.3 V
t
s
t
h
t
PHL
Figure 5.
1.3 V
1.3 V 1.3 V
OE
V
OUT
t
PHZ
≥ V
OH
0.5 V
t
PZH
≈ 1.3 V
Figure 6.
Figure 7.
Figure 8.
SWITCH POSITIONS
Closed
Open
Closed
Closed
Open
Closed
Closed
Closed
t
PZH
t
PZL
t
PLZ
t
PHZ
SW2SW1SYMBOL
SN74LS373 SN74LS374
http://onsemi.com
7
P ACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
M
L
J
20 PL
M
B
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 25.66 27.171.010 1.070
B 6.10 6.600.240 0.260
C 3.81 4.570.150 0.180
D 0.39 0.550.015 0.022
G 2.54 BSC0.100 BSC
J 0.21 0.380.008 0.015
K 2.80 3.550.110 0.140
L 7.62 BSC0.300 BSC
M 0 15 0 15
N 0.51 1.010.020 0.040
____
E
1.27 1.770.050 0.070
1
11
10
20
–A–
SEATING
PLANE
K
N
FG
D
20 PL
–T–
M
A
M
0.25 (0.010) T
E
B
C
F
1.27 BSC0.050 BSC
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–05
ISSUE F
20
1
11
10
B20X
H10X
C
L
18X
A1
A
SEATING
PLANE
q
h X 45
_
E
D
M
0.25
M
B
M
0.25
SAS
B
T
e
T
B
A
DIM MIN MAX
MILLIMETERS
A 2.35 2.65
A1 0.10 0.25
B 0.35 0.49
C 0.23 0.32
D 12.65 12.95
E 7.40 7.60
e 1.27 BSC
H 10.05 10.55
h 0.25 0.75
L 0.50 0.90
q
0 7
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
__
SN74LS373 SN74LS374
http://onsemi.com
8
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability ,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer .
PUBLICATION ORDERING INFORMATION
ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support
Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)
T oll Free from Hong Kong 800–4422–3781
Email: ONlit–asia@hibbertco.com
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, T okyo, Japan 141–8549
Phone: 81–3–5487–8345
Email: r14153@onsemi.com
Fax Response Line: 303–675–2167
800–344–3810 Toll Free USA/Canada
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
SN74LS373/D
North America Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 T oll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: ONlit@hibbertco.com
N. American Technical Support: 800–282–9855 Toll Free USA/Canada
EUROPE: LDC for ON Semiconductor – European Support
German Phone: (+1) 303–308–7140 (M–F 2:30pm to 5:00pm Munich Time)
Email: ONlit–german@hibbertco.com
French Phone: (+1) 303–308–7141 (M–F 2:30pm to 5:00pm Toulouse Time)
Email: ONlit–french@hibbertco.com
English Phone: (+1) 303–308–7142 (M–F 1:30pm to 5:00pm UK Time)
Email: ONlit@hibbertco.com
Loading...