MOTOROLA SN74LS109AD, SN74LS109AM, SN74LS109AMEL, SN74LS109AML1, SN74LS109AN Datasheet
Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6
1 Publication Order Number:
SN74LS109A/D
SN74LS109A
Dual JK Positive
Edge-Trigger ed Flip-Flop
The SN74LS109A consists of two high speed completely
independent transition clocked JK flip-flops. The clocking operation
is independent of rise and fall times of the clock waveform. The JK
design allows operation as a D flip-flop by simply connecting the J and
K pins together.
MODE SELECT – TRUTH TABLE
INPUTS OUTPUTS
OPERATING MODE
S
D
C
D
J K Q Q
Set
Reset (Clear)
*Undetermined
Load “1” (Set)
Hold
Toggle
Load “0” (Reset)
L
H
L
H
H
H
H
H
L
L
H
H
H
H
X
X
X
h
l
h
l
X
X
X
h
h
l
l
H
L
H
H
q
q
L
L
H
H
L
q
q
H
* Both outputs will be HIGH while both SD and CD are LOW, but the output
states are unpredictable if S
D
and CD go HIGH simultaneously.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input
i, h (q) = (or output) one set-up time prior to the LOW to HIGH clock transition.
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
Supply Voltage 4.75 5.0 5.25 V
T
A
Operating Ambient
T emperature Range
0 25 70 °C
I
OH
Output Current – High –0.4 mA
I
OL
Output Current – Low 8.0 mA
LOW
POWER
SCHOTTKY
Device Package Shipping
ORDERING INFORMATION
SN74LS109AN 16 Pin DIP 2000 Units/Box
SN74LS109AD 16 Pin
SOIC
D SUFFIX
CASE 751B
http://onsemi.com
2500/Tape & Reel
PLASTIC
N SUFFIX
CASE 648
16
1
16
1
SN74LS109A
http://onsemi.com
2
LOGIC DIAGRAM
SET (SD)
CLEAR (C
D
)
5(11)
1(15)
CLOCK
4(12)
J
2(14)
K
3(13)
Q
6(10)
Q
7(9)
LOGIC SYMBOL
VCC = PIN 16
GND = PIN 8
511
2
4
3
6
7
1
14
12
13
10
9
15
J
Q
CP
K
Q
S
D
C
D
J
Q
CP
K
Q
S
D
C
D
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol Parameter
Min Typ Max
Unit Test Conditions
V
IH
Input HIGH Voltage 2.0 V
Guaranteed Input HIGH Voltage for
All Inputs
V
IL
Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
V
IK
Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
V
OH
Output HIGH Voltage
2.7 3.5 V VCC = MIN, IOH = MAX, VIN = V
IH
or VIL per Truth Table
p
0.25 0.4 V IOL = 4.0 mA
VCC = VCC MIN,
VOLOutput LOW Voltage
0.35 0.5 V IOL = 8.0 mA
V
IN
=
V
IL
or
V
IH
per Truth Table
I
IH
Input HIGH Current
J, K
, Clock
Set, Clear
20
40
µA VCC = MAX, VIN = 2.7 V
IH
J, K, Clock
Set, Clear
0.1
0.2
mA VCC = MAX, VIN = 7.0 V
I
IL
Input LOW Current
J, K
, Clock
Set, Clear
–0.4
–0.8
mA VCC = MAX, VIN = 0.4 V
I
OS
Output Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
I
CC
Power Supply Current 8.0 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
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