MOTOROLA PowerPC 604 Technical data

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G522-0296-01
(IBM Order Number)

Advance Information

PowerPC

604e

™

RISC Microprocessor Family:

(Motorola Order Number)

MPC604E9VEC/D

5/97

REV 1

™

PID9v-604e Hardware Specifications

The PowerPC 604e microprocessor is an implementation of the PowerPC™ family of reduced
instruction set computing (RISC) microprocessors. In this document, the term ‘604’ is used as an
abbreviation for ‘PowerPC 604™ microprocessor’ and the term ‘604e’ is used as an abbreviation for
‘PowerPC 604e microprocessor’. The PowerPC 604e microprocessors are available from Motorola as
MPC604e and from IBM as PPC604e. This document contains pertinent physical characteristics of the
604e.

This document contains the following topics:

Topic Page

Section 1.1, “Overview” 2
Section 1.2, “Features” 2
Section 1.3, “General Parameters” 5
Section 1.4, “Electrical and Thermal Characteristics” 6
Section 1.5, “PowerPC 604e Microprocessor Pin Assignments” 17
Section 1.6, “PowerPC 604e Microprocessor Pinout Listings” 18
Section 1.7, “PowerPC 604e Microprocessor Package Description” 20
Section 1.8, “System Design Information” 22
Section 1.9, “Ordering Information 29

PRELIMINARY

T o locate any published errata or updates for this document, refer to the website at http://www .mot.com/
PowerPC/ or at http://www.chips.ibm.com/products/ppc.

The PowerPC name, the PowerPC logotype, PowerPC 604, and PowerPC 604e are trademarks
Corporation, used by Motorola under license from International Business Machines Corporation.

This document contains information on a new product under development by Motorola and IBM. Motorola and IBM reserve the right to
change or discontinue this product without notice.

Motorola Inc., 1997. All rights reserved.

©

Portions hereof

International Business Machines Corporation, 1991–1997. All rights reserved.

©

of International Business Machines

PID9v-604e Hardware Specifications

1.1 Overview

The 604e is an implementation of the PowerPC family of reduced instruction set computing (RISC)
microprocessors. The 604e implements the PowerPC architecture as it is specified for 32-bit addressing,
which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits, and floating­point data types of 32 and 64 bits (single-precision and double-precision). For 64-bit PowerPC
implementations, the PowerPC architecture provides additional 64-bit integer data types, 64-bit addressing,
and related features.

The 604e is a superscalar processor capable of issuing four instructions simultaneously. As many as seven
instructions can finish execution in parallel. The 604e has seven execution units that can operate in
parallel—a floating-point unit (FPU), a branch processing unit (BPU), a condition register unit (CRU), a
load/store unit (LSU), and three integer units (IUs)—two single-cycle integer units (SCIUs) and one
multiple-cycle integer unit (MCIU).

This parallel design, combined with the PowerPC architecture’s specification of uniform instructions that
allows for rapid execution times, yields high efficiency and throughput. The 604e’s rename buffers,
reservation stations, dynamic branch prediction, and completion unit increase instruction throughput,
guarantee in-order completion, and ensure a precise exception model. (Note that the PowerPC architecture
specification refers to all exceptions as interrupts.)

The 604e has separate memory management units (MMUs) and separate 32-Kbyte on-chip caches for
instructions and data. The 604e implements two 128-entry, two-way set associative translation lookaside
buffers (TLBs), one for instructions and one for data, and provides support for demand-paged virtual
memory address translation and variable-sized block translation. The TLBs and the cache use least-recently
used (LRU) replacement algorithms.

The 604e has a 64-bit external data bus and a 32-bit address bus. The 604e interface protocol allows multiple
masters to compete for system resources through a central external arbiter. Additionally, on-chip snooping
logic maintains data cache coherency for multiprocessor applications. The 604e supports single-beat and
burst data transfers for memory accesses and memory-mapped I/O accesses.

The 604e uses an advanced, 2.5-V CMOS process technology and is fully compatible with TTL devices.

1.2 Features

This section summarizes features of the 604e’s implementation of the Po werPC architecture. Major features
of the 604e are as follows:

• High-performance, superscalar microprocessor
— As many as four instructions can be issued per clock
— As many as seven instructions can start executing per clock (including three integer

instructions)

— Single-clock-cycle execution for most instructions

PRELIMINARY

• Seven independent execution units and two register files
— BPU featuring dynamic branch prediction

– Two-entry reservation station
– Out-of-order execution through two branches
– Shares dispatch bus with CRU

2 PID9v-604e Hardware Specifications

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

– 64-entry fully-associative branch target address cache (BTAC). In the 604e, the BTAC can

be disabled and invalidated.

– 512-entry branch history table (BHT) with two bits per entry for four levels of prediction—

not-taken, strongly not-taken, taken, strongly taken

— Condition register logical unit

– Two-entry reservation station
– Shares dispatch bus with BPU

— Two single-cycle IUs (SCIUs) and one multiple-cycle IU (MCIU)

– Instructions that execute in the SCIU take one cycle to execute; most instructions that

execute in the MCIU take multiple cycles to execute.
– Each SCIU has a two-entry reservation station to minimize stalls
– The MCIU has a single-entry reservation station and provides early exit (three c ycles) for

16- x 32-bit and overflow operations.
– Thirty-two GPRs for integer operands

— Three-stage floating-point unit (FPU)

– Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations
– Supports non-IEEE mode for time-critical operations
– Fully pipelined, single-pass double-precision design
– Hardware support for denormalized numbers
– Two-entry reservation station to minimize stalls
– Thirty-two 64-bit FPRs for single- or double-precision operands

— Load/store unit (LSU)

– Two-entry reservation station to minimize stalls
– Single-cycle, pipelined cache access
– Dedicated adder performs effective address (EA) calculations
– Performs alignment and precision conversion for floating-point data
– Performs alignment and sign extension for integer data
– Four-entry finish load queue (FLQ) provides load miss buffering
– Six-entry store queue
– Supports both big- and little-endian modes

• Rename buffers
— Twelve GPR rename buffers

PRELIMINARY

— Eight FPR rename buffers
— Eight condition register (CR) rename buffers

• Completion unit
— The completion unit retires an instruction from the 16-entry reorder buffer when all instructions

ahead of it have been completed and the instruction has finished execution.
— Guarantees sequential programming model (precise exception model)
— Monitors all dispatched instructions and retires them in order

PID9v-604e Hardware Specifications 3

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

— Tracks unresolved branches and flushes e xecuted, dispatched, and fetched instructions if branch

is mispredicted
— Retires as many as four instructions per clock

• Separate on-chip instruction and data caches (Harvard architecture)
— 32-Kbyte, four-way set-associative instruction and data caches
— LRU replacement algorithm
— 32-byte (eight-word) cache block size
— Physically indexed/physical tags (Note that the PowerPC architecture refers to physical address

space as real address space.)
— Cache write-back or write-through operation programmable on a per page or per block basis
— Instruction cache can provide four instructions per clock; data cache can provide two words per

clock
— Caches can be disabled in software
— Caches can be locked
— Parity checking performed on both caches
— Data cache coherency (MESI) maintained in hardware
— Secondary data cache support provided
— Instruction cache coherency maintained in software
— Data cache line-fill buffer forwarding. In the 604 only the critical double word of the cache

block was made available to the requesting unit at the time it w as burst into the line-fill buffer.

Subsequent data was unavailable until the cache block w as filled. On the 604e, subsequent data

is also made available as it arrives in the line-fill buffer.

• Separate memory management units (MMUs) for instructions and data
— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte

segment size
— Both TLBs are 128-entry and two-way set associative
— TLBs are hardware reloadable (that is, the page table search is performed in hardware)
— Separate IBATs and DBATs (four each) also defined as SPRs
— Separate instruction and data translation lookaside buffers (TLBs)
— LRU replacement algorithm
— 52-bit virtual address; 32-bit physical address

• Bus interface features
— Selectable processor-to-bus clock frequency ratios of 3:2, 2:1, 5:2, 3:1, 7:2, 4:1, 5:1, and 6:1

PRELIMINARY

— A 64-bit split-transaction external data bus with burst transfers
— Support for address pipelining and limited out-of-order bus transactions
— Four burst write queues—three for cache copyback operations and one for snoop push

operations
— Two single-beat write queues
— Additional signals and signal redefinition for direct-store operations
— Provides a data streaming mode that allows consecutive burst read data transfers to occur

without intervening dead cycles. This mode also disables data retry operations.

4 PID9v-604e Hardware Specifications

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

— No-DR

operations. This improves performance on read operations for systems that do not use the

DR

cycle sooner than if normal mode is used.

• Multiprocessing support features include the following:
— Hardware enforced, four-state cache coherency protocol (MESI) for data cache. Bits are

provided in the instruction cache to indicate only whether a cache block is valid or invalid.
— Separate port into data cache tags for bus snooping
— Load/store with reservation instruction pair for atomic memory references, semaphores, and

other multiprocessor operations

• Power management
— DOZE mode suspends instruction execution while allowing cache snooping
— NAP mode suspends all internal clocks except those required for decrementer, time base, and

interrupt logic

— Operating voltage of 2.5 ± 0.125 V

• Performance monitor can be used to help in debugging system designs and improving software
efficiency, especially in multiprocessor systems.

• In-system testability and debugging features through JTAG boundary-scan capability

TRY mode eliminates the DRTRY signal from the qualified bus grant and allows read

TRY signal. No-DRTRY mode makes read data available to the processor one bus clock

1.3 General Parameters

The following list provides a summary of the general parameters of the 604e:

Technology 0.35 µ m CMOS, five-layer metal
Die size 12.9 mm x 11.7 mm (148 mm
Transistor count 5.1 million
Logic design Fully-static
Package 255-lead ceramic ball grid array (CBGA)
Core power supply 2.5 V ± 5% V dc
I/O power supply 3.3 V ± 5% V dc

PRELIMINARY

2

)

PID9v-604e Hardware Specifications 5

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

° C

° C

1.4 Electrical and Thermal Characteristics

This section provides both the A C and DC electrical specifications and thermal characteristics for the 604e.

1.4.1 DC Electrical Characteristics

The tables in this section describe the 604e DC electrical characteristics. Table 1 provides the absolute
maximum ratings.

Table 1. Absolute Maximum Ratings

Characteristic Symbol Value Unit

Core supply voltage Vdd –0.3 to 2.75 V
PLL supply voltage AVdd –0.3 to 2.75 V
I/O supply voltage OVdd –0.3 to 3.6 V
Input voltage V
Storage temperature range T

Notes :

1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress
ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed
may affect device reliability or cause permanent damage to the device.

2. Caution : V

3. Caution : OVdd must not exceed Vdd/AVdd by more than 1.2 V at any time including during power-on reset.

4. Caution : Vdd/AVdd must not exceed OVdd by more than 0.4 V at any time including during power-on reset.

must not exceed OVdd by more than 2.5 V at all times including during power-on reset.

in

in

stg

Table 2 provides the recommended operating conditions for the 604e.

Table 2. Recommended Operating Conditions

Characteristic Symbol Value Unit

–0.3 to 5.5 V
–55 to 150

PRELIMINARY

Core supply voltage Vdd 2.375 to 2.625 V
PLL supply voltage AVdd 2.375 to 2.625 V
I/O supply voltage OVdd 3.135 to 3.465 V
Input voltage V

in

GND to 5.5 V

Die-junction temperature T

Note: These are the recommended and tested operating conditions. Proper device operation outside of these

conditions is not guaranteed.

6 PID9v-604e Hardware Specifications

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

j

0 to 105

Table 3 provides the thermal characteristics for the 604e.

Table 3. Thermal Characteristics

Characteristic Symbol Value Rating

°

°

µ

µ

CBGA package thermal resistance, die junction-to-top-of-die (typical) θ
CBGA package thermal resistance, die junction-to-ball (typical) θ

Note: Refer to Section 1.8, “System Design Information,” for more details about thermal management.

JC

JB

0.1

3.8

Table 4 provides the DC electrical characteristics for the 604e.

Table 4. DC Electrical Specifications

Vdd = AVdd = 2.5 ± 5% V dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 ≤ Tj ≤ 105 ° C

Characteristic Symbol Min Max Unit

Input high voltage (all inputs except SYSCLK) V
Input low voltage (all inputs except SYSCLK) V
SYSCLK input high voltage CV
SYSCLK input low voltage CV
Input leakage current, V

Hi-Z (off-state) leakage current, V

Output high voltage, I
Output low voltage, I
Capacitance, V

and AR
Capacitance, V

AR

TRY)

TRY)

=

in

=

in

= 3.465 V

in

V

= 5.5 V

in

= –9

OH

mA V

9

=

OL

0 V, f = 1 MHz

PRELIMINARY

0 V, f = 1 MHz

1

1

3.465 V

=

in

=

V

in

mA V

2

(excludes TS

2

(for TS

1

1

5.5

V

, ABB, DBB,

, ABB, DBB, and

I

in

I

in

I

TSI

I

TSI

C

C

IH

IL

IH

IL

OH

OL

in

in

2.0 5.5 V
GND 0.8 V

2.4 5.5 V
GND 0.4 V
—10
— 245

—10
— 245

2.4 — V
— 0.4 V
— 10.0 pF

— 15.0 pF

C/W
C/W

µ

A
A

µ

A
A

Notes:

1. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK) and JTAG signals.

2. Capacitance values are guaranteed by design and characterization, and are not tested.

PID9v-604e Hardware Specifications 7

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Table 5 provides the power consumption for the 604e.

Table 5. Power Consumption

Processor Core Frequency

CPU Clock:

SYSCLK

Full-On Mode

166

MHz

180

MHz

200

MHz

225

MHz

233

MHz

Unit

Typical
Maximum

Doze Mode

Typical
Maximum

Nap Mode

Typical
Maximum

Notes:

1. These values apply for all v alid PLL_CFG[0–3] settings and do not include output driver power (OVdd)
or analog supply power (AVdd). OVdd power is system dependent but is typically ≤ 10% of Vdd. Worst­case AVdd = 15 mW.

2. Typical power is an average value measured at Vdd = AVdd = 2.5 V, OVdd = 3.3 V, T
system executing typical applications and benchmark sequences. Typical power numbers should be
used in planning for proper thermal management.

3. Maximum power is measured at Vdd = AVdd = 2.625 V, OVdd = 3.465 V, T
instruction mix. These values should be used for power supply design.

12.4 13.5 14.5 15.9 16.7 W

13.3 14.3 15.7 17.4 18.0 W

1.1 1.1 1.1 1.1 1.2 W

1.2 1.2 1.3 1.3 1.3 W

0.8 0.8 0.9 0.9 0.9 W

1.1 1.1 1.1 1.1 1.1 W

= 25 °C in a

a

= 0 °C using a worst-case

j

1.4.2 AC Electrical Characteristics

PRELIMINARY

This section provides the AC electrical characteristics for the 604e. After fabrication, parts are sorted by
maximum processor core frequency as shown in Section 1.4.2.1, “Clock AC Specifications,” and tested for
conformance to the AC specifications for that frequency. These specifications are for 166.67, 180, 200, 225,
and 233 MHz processor core frequencies. The processor core frequency is determined by the bus
(SYSCLK) frequency and the settings of the PLL_CFG[0–3] signals. Parts are sold by maximum processor
core frequency; see Section 1.9, “Ordering Information.”

8 PID9v-604e Hardware Specifications

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

1.4.2.1 Clock AC Specifications

Table 6 provides the clock AC timing specifications as defined in Figure 1.

Table 6. Clock AC Timing Specifications

Vdd = AVdd = 2.5 ± 5% V dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 ≤ Tj ≤ 105 °C

166.67

Num Characteristic

Processor
frequency

VCO frequency 166 33 180 360 200 400 225 450 233 466 MHz 1
SYSCLK (bus)

frequency

1 SYSCLK cycle

time

2, 3 SYSCLK rise and

fall time

4 SYSCLK duty

cycle measured
at 1.4 V

SYSCLK jitter — ±150 — ±150 — ±150 ±150 ±150 ps 4
604e internal

PLL-relock time

Notes:

1. Caution: The SYSCLK frequency and PLL_CFG[0–3] settings must be chosen such that the resulting
SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective
maximum or minimum operating frequencies. Refer to the PLL_CFG[0–3] signal description in Section 1.8,
“System Design Information,” for valid PLL_CFG[0–3] settings.

2. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.

3. Timing is guaranteed by design and characterization, and is not tested.

4. The total input jitter (short term and long term combined) must be under ±150 ps to guarantee the input and
output timing shown in Section 1.4.2.2, “Input AC Specifications” and Section 1.4.2.3, “Output AC
Specifications.”

5. PLL-relock time is the maximum time required for PLL lock after a stable Vdd, OVdd, AVdd, and SYSCLK
are reached during the power-on reset sequence. Also note that HRESET
minimum of 255 bus clocks after the PLL-relock time (100 µs) during the power-on reset sequence.

6. AC timing specifications are tested up to the maximum SYSCLK frequency shown here. However, it is
theoretically possible to attain higher SYSCLK frequencies, if allowed f or b y system design or by using 604e
Fast Out mode (see Table 11 for details).

MHz

Min Max Min Max Min Max Min Max Min Max

83.3 166.7 90 180 100 200 112 225 116 233 MHz 1

25 66 25 66 25 66 25 75 25 75 MHz 1, 6

15 40 15 40 15 40 13 40 13 40 ns

1.0 2.0 1.0 2.0 1.0 2.0 1.0 2.0 1.0 2.0 ns 2

40 60 40 60 40 60 40 60 40 60 % 3

— 100 — 100 — 100 100 100 µs 3, 5

PRELIMINARY

180

MHz

200

MHz

225

MHz

must be held asserted for a

233

MHz

Unit Notes

PID9v-604e Hardware Specifications 9

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE