MOTOROLA PowerPC 604 User Manual

查询MPC604E9QEC供应商

G522-0319-00 (IBM Order Number)

MPC604E9QEC/D

(Motorola Order Number)

3/98

Advance Information

PowerPC

604e

RISC Microprocessor Family:

PID9q-604e Hardware SpeciÞcations

The PowerPC 604e microprocessor is an implementation of the PowerPC¨ family of reduced instruction set computing (RISC) microprocessors. In this document, the term Ô604Õ is used as an abbreviation for ÔPowerPC 604ª microprocessorÕ and the term Ô604eÕ is used as an abbreviation for ÔPowerPC 604e microprocessorÕ. The PowerPC 604e microprocessors are available from Motorola as MPC604e and from IBM as PPC604e. When ordering, note that PID9q-604e processors prior to revision 1.1 are referenced as the PID10q-604e. This document contains pertinent physical characteristics of the 604e.

This document contains the following topics:

Topic Page

Section 1.1, ÒOverviewÓ 2 Section 1.2, ÒFeaturesÓ 2 Section 1.3, ÒGeneral ParametersÓ 5 Section 1.4, ÒElectrical and Thermal CharacteristicsÓ 6 Section 1.5, ÒPin AssignmentsÓ 16 Section 1.6, ÒPinout ListingsÓ 17 Section 1.7, ÒPackage DescriptionÓ 19 Section 1.8, ÒSystem Design InformationÓ 20 Section 1.9, ÒOrdering Information 27

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To locate any published errata or updates for this document, refer to the website at http://www.mot.com/ SPS/PowerPC/ or at http://www.chips.ibm.com/products/ppc.

The PowerPC name is a registered trademark and the PowerPC logotype, PowerPC 604 and PowerPC 604e are trademarks Machines Corporation, used by Motorola under license from International Business Machines Corporation. FLOTHERM is a registered trademark of Flomerics Ltd., UK.

This document contains information on a new product under development by Motorola and IBM. Motorola and IBM reserve the right to discontinue this product without notice.

Portions hereof

of International Business

change or

PID9q-604e Hardware Specifications

1.1 Overview

The 604e is an implementation of the PowerPC family of reduced instruction set computing (RISC) microprocessors. The 604e implements the PowerPC architecture as it is speciÞed for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits, and ßoatingpoint data types of 32 and 64 bits (single-precision and double-precision). For 64-bit PowerPC implementations, the PowerPC architecture provides additional 64-bit integer data types, 64-bit addressing, and related features.

The 604e is a superscalar processor capable of issuing four instructions simultaneously. As many as seven instructions can Þnish execution in parallel. The 604e has seven execution units that can operate in parallelÑa ßoating-point unit (FPU), a branch processing unit (BPU), a condition register unit (CRU), a load/store unit (LSU), and three integer units (IUs)Ñtwo single-cycle integer units (SCIUs) and one multiple-cycle integer unit (MCIU).

This parallel design, combined with the PowerPC architectureÕs speciÞcation of uniform instructions that allows for rapid execution times, yields high efÞciency and throughput. The 604eÕs rename buffers, reservation stations, dynamic branch prediction, and completion unit increase instruction throughput, guarantee in-order completion, and ensure a precise exception model. (Note that the PowerPC architecture speciÞcation refers to all exceptions as interrupts.)

The 604e has separate memory management units (MMUs) and separate 32-Kbyte on-chip caches for instructions and data. The 604e implements two 128-entry, two-way set associative translation lookaside buffers (TLBs), one for instructions and one for data, and provides support for demand-paged virtual memory address translation and variable-sized block translation. The TLBs and the cache use least-recently used (LRU) replacement algorithms.

The 604e has a 64-bit external data bus and a 32-bit address bus. The 604e interface protocol allows multiple masters to compete for system resources through a central external arbiter. Additionally, on-chip snooping logic maintains data cache coherency for multiprocessor applications. The 604e supports single-beat and burst data transfers for memory accesses and memory-mapped I/O accesses.

The 604e uses an advanced, 1.9V CMOS process technology and is fully compatible with 3.3V TTL devices.

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1.2 Features

This section summarizes features of the 604eÕs implementation of the PowerPC architecture. Major features of the 604e are as follows:

¥ High-performance, superscalar microprocessor

Ñ As many as four instructions can be issued per clock

Ñ As many as seven instructions can start executing per clock (including three integer

instructions)

Ñ Single-clock-cycle execution for most instructions

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¥ Seven independent execution units and two register Þles

Ñ BPU featuring dynamic branch prediction

Ð Two-entry reservation station

Ð Out-of-order execution through two branches

Ð Shares dispatch bus with CRU

Ð 64-entry fully-associative branch target address cache (BTAC). In the 604e, the BTAC can

be disabled and invalidated.

Ð 512-entry branch history table (BHT) with two bits per entry for four levels of predictionÑ

not-taken, strongly not-taken, taken, strongly taken

Ñ Condition register logical unit

Ð Two-entry reservation station

Ð Shares dispatch bus with BPU

Ñ Two single-cycle IUs (SCIUs) and one multiple-cycle IU (MCIU)

Ð Instructions that execute in the SCIU take one cycle to execute; most instructions that

execute in the MCIU take multiple cycles to execute.

Ð Each SCIU has a two-entry reservation station to minimize stalls

Ð The MCIU has a single-entry reservation station and provides early exit (three cycles) for

16- x 32-bit and overßow operations.

Ð Thirty-two GPRs for integer operands

Ñ Three-stage ßoating-point unit (FPU)

Ð Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations

Ð Supports non-IEEE mode for time-critical operations

Ð Fully pipelined, single-pass double-precision design

Ð Hardware support for denormalized numbers

Ð Two-entry reservation station to minimize stalls

Ð Thirty-two 64-bit FPRs for single- or double-precision operands

Ñ Load/store unit (LSU)

Ð Two-entry reservation station to minimize stalls

Ð Single-cycle, pipelined cache access

Ð Dedicated adder performs effective address (EA) calculations

Ð Performs alignment and precision conversion for ßoating-point data

Ð Performs alignment and sign extension for integer data

Ð Four-entry Þnish load queue (FLQ) provides load miss buffering

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Ð Six-entry store queue

Ð Supports both big- and little-endian modes

¥ Rename buffers

Ñ Twelve GPR rename buffers

Ñ Eight FPR rename buffers

Ñ Eight condition register (CR) rename buffers

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¥ Completion unit

Ñ The completion unit retires an instruction from the 16-entry reorder buffer when all instructions

ahead of it have been completed and the instruction has Þnished execution.

Ñ Guarantees sequential programming model (precise exception model)

Ñ Monitors all dispatched instructions and retires them in order

Ñ Tracks unresolved branches and ßushes executed, dispatched, and fetched instructions if branch

is mispredicted

Ñ Retires as many as four instructions per clock

¥ Separate on-chip instruction and data caches (Harvard architecture)

Ñ 32-Kbyte, four-way set-associative instruction and data caches

Ñ LRU replacement algorithm

Ñ 32-byte (eight-word) cache block size

Ñ Physically indexed/physical tags. (Note that the PowerPC architecture refers to physical

address space as real address space.)

Ñ Cache write-back or write-through operation programmable on a per page or per block basis

Ñ Instruction cache can provide four instructions per clock; data cache can provide two words per

clock

Ñ Caches can be disabled in software

Ñ Caches can be locked

Ñ Parity checking performed on both caches

Ñ Data cache coherency (MESI) maintained in hardware

Ñ Secondary data cache support provided

Ñ Instruction cache coherency maintained in hardware

Ñ Data cache line-Þll buffer forwarding. In the 604 only the critical double word of the cache

block was made available to the requesting unit at the time it was burst into the line-Þll buffer. Subsequent data was unavailable until the cache block was Þlled. On the 604e, subsequent data is also made available as it arrives in the line-Þll buffer.

¥ Separate memory management units (MMUs) for instructions and data

Ñ Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte

segment size

Ñ Both TLBs are 128-entry and two-way set associative

Ñ TLBs are hardware reloadable (that is, the page table search is performed in hardware)

Ñ Separate IBATs and DBATs (four each) also deÞned as SPRs

Ñ Separate instruction and data translation lookaside buffers (TLBs)

Ñ LRU replacement algorithm

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Ñ 52-bit virtual address; 32-bit physical address

¥ Bus interface features include the following:

Ñ Selectable processor-to-bus clock frequency ratios (1:1, 3:2, 2:1, 5:2, 3:1, 7:2, 4:1, 9:2, 5:1,

11:2, 6:1, 13:2, and 7:1)

Ñ A 64-bit split-transaction external data bus with burst transfers

Ñ Support for address pipelining and limited out-of-order bus transactions

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Ñ Four burst write queuesÑthree for cache copyback operations and one for snoop push

operations

Ñ Two single-beat write queues

Ñ Additional signals and signal redeÞnition for direct-store operations

Ñ Provides a data streaming mode that allows consecutive burst read data transfers to occur

without intervening dead cycles. This mode also disables data retry operations.

Ñ No-DR

operations. This improves performance on read operations for systems that do not use the DR cycle sooner than if normal mode is used.

¥ Multiprocessing support features include the following:

Ñ Hardware enforced, four-state cache coherency protocol (MESI) for data cache. Bits are

provided in the instruction cache to indicate only whether a cache block is valid or invalid.

Ñ Separate port into data cache tags for bus snooping

Ñ Load/store with reservation instruction pair for atomic memory references, semaphores, and

other multiprocessor operations

¥ Power management

Ñ NAP mode supports full shut down and snooping

Ñ Operating voltage of 1.9 ± 100 mV

¥ Performance monitor can be used to help in debugging system designs and improving software

efÞciency, especially in multiprocessor systems.

¥ In-system testability and debugging features through JTAG boundary-scan capability

TRY mode eliminates the DRTRY signal from the qualiÞed bus grant and allows read

TRY signal. No-DRTRY mode makes read data available to the processor one bus clock

1.3 General Parameters

The following list provides a summary of the general parameters of the 604e:

Technology 0.25 µm CMOS, Þve-layer metal

Die size 6.97 mm x 6.75mm (47 mm

Transistor count 5.1 million

Logic design Fully-static

Package Surface mount 255-lead ceramic ball grid array (CBGA)

Core power supply 1.9 V ± 100 mV dc

I/O power supply 3.3 V ± 5% V dc

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)

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1.4 Electrical and Thermal Characteristics

This section provides both the AC and DC electrical speciÞcations and thermal characteristics for the 604e.

1.4.1 DC Electrical Characteristics

The tables in this section describe the 604e DC electrical characteristics. Table 1 provides the absolute maximum ratings.

Table 1. Absolute Maximum Ratings

Characteristic Symbol Value Unit

Core supply voltage Vdd Ð0.3 to 2.80 V

PLL supply voltage AVdd Ð0.3 to 2.80 V

I/O supply voltage OVdd Ð0.3 to 3.8 V

Input voltage V

Overshoot (with respect to system GND) V

Undershoot (with respect to system GND) V

Storage temperature range T

Notes :

1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.

Caution : Power up/down sequence must be adhered to to avoid device damage.

¥ The power-up sequence is GND, Vdd, OVdd

¥ The power-down sequence is OVdd, Vdd, GND

In either case the rule OVdd Ð Vdd

Caution : During system power-up, any 604e signal Ð VDDcore must not exceed 2.0V

Caution : 604e inputs are not 5V tolerant.

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2.0V must be followed.

ovs

uns

stg

Table 2 provides the recommended operating conditions for the 604e.

Table 2. Recommended Operating Conditions

Characteristic Symbol Value Unit

Ð0.3 to 3.3 V

4.0 V

-0.45 V

Ð55 to 150 ¡C

Core supply voltage Vdd 1.8 to 2.0 V

PLL supply voltage AVdd 1.8 to 2.0 V

I/O supply voltage OVdd 3.135 to 3.465 V

Input voltage V

Junction temperature T

Note: These are the recommended and tested operating conditions. Proper device operation outside of these

conditions is not guaranteed.

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GND to 3.3 V

0 to 105 ¡C

Table 3 provides the thermal characteristics for the 604e.

Table 3. Thermal Characteristics

Characteristic Symbol Value Rating

CBGA package thermal resistance, junction-to-top of die q

Note: Refer to Section 1.8, ÒSystem Design Information,Ó for more details about thermal management.

0.03 ¡C/W

Table 4 provides the DC electrical characteristics for the 604e.

Table 4. DC Electrical Specifications

Vdd = AVdd = 1.9 ±100 mV dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 £ Tj £ 105 ¡C

Characteristic Symbol Min Max Unit

Input high voltage (all inputs except SYSCLK) V

Input low voltage (all inputs except SYSCLK) V

SYSCLK input high voltage CV

SYSCLK input low voltage CV

Input leakage current, Vin = 3.3 V

Hi-Z (off-state) leakage current, V

Output high voltage, I

Output low voltage, I

Capacitance, V and AR

TRY)

Capacitance, V AR

TRY)

Output impedance

Normal mode (DRV_MOD[0Ð1] = 01) Strong mode (DRV_MOD[0Ð1] = 10) Herculean mode (DRV_MOD[0Ð1] = 11)

in =

= Ð2

0 V, f = 1 MHz

3.3 V

mA V

(excludes TS, ABB, DBB,

(for TS, ABB, DBB, and

TSI

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2.0 3.465 V

0.0 0.8 V

2.4 3.465 V

0.0 0.4 V

Ñ10µA

2.4 Ñ V

Ñ 0.4 V

Ñ 10.0 pF

Ñ 15.0 pF

56 42 30

84 57 30

Notes :

1. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK, and JTAG signals).

2. Capacitance values are guaranteed by design and characterization, and are not tested.

3. Output impedance is guaranteed by design and is not tested. Refer to IBIS simulation models for output impedance values based on Vdd and OVdd tolerances used in system.

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Table 5 provides the power consumption for the 604e.

Table 5. Power Consumption

CPU Clock:

SYSCLK

Full-On Mode

Typical

Maximum

Nap Mode

Typical

Maximum

Notes:

1. These values apply for all valid PLL_CFG[0Ð3] settings and do not include output driver power (OVdd) or analog supply power (AVdd). OVdd power is system dependent but is typically

2. Typical power is an average value estimated at Vdd = AVdd = 1.9 V, OVdd = 3.3 V, T 25 ¡C in a system executing typical applications and benchmark sequences. Typical power numbers should be used in planning for proper thermal management.

3. Maximum power is estimated at Vdd = AVdd = 2.0 V, OVdd = 3.465 V,T worst-case instruction mix. These values should be used for power supply design.

4. Nap mode power consumption is estimated, and assumes no snoop activity.

266 MHz 300 MHz 333 MHz

6.0 6.8 7.5 W

10.6 12.0 13.4 W

TBD TBD TBD W

0.78 0.80 0.82 W

Processor Core Frequency

10% of Vdd. Worst-case AVdd = 15 mW.

= 0 ¡C using a

Unit

1.4.2 AC Electrical Characteristics

This section provides the AC electrical characteristics for the 604e. These speciÞcations are for 266, 300, and 333 MHz processor core frequencies. The processor core frequency is determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0Ð3] signals. All timings are speciÞed respective to the rising edge of SYSCLK.

1.4.2.1 Clock AC SpeciÞcations

Table 6 provides the clock AC timing speciÞcations as deÞned in Figure 1.

Vdd = AVdd = 1.9 ±100 mV dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 £ T

Num Characteristic

Processor frequency 250 266 266 300 300 333 MHz 1

VCO frequency 500 532 532 600 600 666 MHz 1

SYSCLK frequency 35.7 100 38 100 42.9 100 MHz 1, 6

1 SYSCLK cycle time 10 35 10 28 10 25 ns

2, 3 SYSCLK rise and fall time 1.0 2.0 1.0 2.0 1.0 2.0 ns 2

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Table 6. Clock AC Timing Specifications

105 ¡C

266 MHz 300 MHz 333 MHz

Unit Notes

Min Max Min Max Min Max

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Table 6. Clock AC Timing Specifications (Continued)

Vdd = AVdd = 1.9 ±100 mV dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 £ Tj £ 105 ¡C

266 MHz 300 MHz 333 MHz

Num Characteristic

Min Max Min Max Min Max

Unit Notes

4 SYSCLK duty cycle

measured at 0.9 V

SYSCLK jitter Ñ ±150 Ñ ±150 Ñ ±150 ps 4

604e internal PLL relock time

Notes:

1. Caution: The SYSCLK frequency and PLL_CFG[0Ð3] settings must be chosen such that the

resulting SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0Ð3] signal description in Section 1.8, ÒSystem Design Information,Ó for valid PLL_CFG[0Ð3] settings, and to Section 1.9, ÒOrdering Information,Ó for available frequencies and part numbers.

2. Rise and fall times for the SYSCLK input are measured from 0.4 V to 1.8 V.

3. Timing is guaranteed by design and characterization, and is not tested.

4. Cycle-to-cycle jitter, and is guaranteed by design.

5. PLL-relock time is the maximum time required for PLL lock after a stable Vdd, OVdd, AVdd, and SYSCLK are reached during the power-on reset sequence. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time (100 ms) during the power-on reset sequence.

6. 604e processors are tested at the maximum SYSCLK frequencies shown in the AC timing speciÞcations. It is possible to attain higher SYSCLK frequencies through proper system design.

40 60 40 60 40 60 % 3

Ñ 100 Ñ 100 Ñ 100 ms 3, 5

Figure 1 provides the SYSCLK input timing diagram.

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SYSCLK

Figure 1. SYSCLK Input Timing Diagram

VM = Midpoint Voltage (0.9 V)

2 34

CVih

CVil

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