Motorola MTP75N06HD Datasheet
1
Motorola TMOS Power MOSFET Transistor Device Data
N–Channel Enhancement–Mode Silicon Gate
This advanced high–cell density HDTMOS E–FET is designed to
withstand high energy in the avalanche and commutation modes.
This new energy efficient design also o ffers a drain–to–source
diode w ith a f ast r ecovery t ime. Designed for l ow–voltage,
high–speed switching applications in power supplies, converters
and PWM m otor controls, a nd inductive loads. The a valanche
energy capability is specified to eliminate the guesswork in designs
where inductive loads are switched, and to offer additional safety
margin against unexpected voltage transients.
• Ultra Low R
DS(on)
, High–Cell Density, HDTMOS
• Diode is Characterized for Use in Bridge Circuits
• I
DSS
and V
DS(on)
Specified at Elevated Temperature
• Avalanche Energy Specified
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating Symbol Value Unit
Drain–Source Voltage V
DSS
60 Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ) V
DGR
60 Vdc
Gate–Source Voltage — Continuous
Gate–Source Voltage — Single Pulse
V
GS
± 20
± 30
Vdc
Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
I
D
I
D
I
DM
75
50
225
Adc
Apk
Total Power Dissipation
Derate above 25°C
P
D
150
1.0
Watts
W/°C
Operating and Storage Temperature Range TJ, T
stg
–55 to 175 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 75 Apk, L = 0.177 mH, RG = 25 Ω)
E
AS
500 mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
R
θJC
R
θJA
1.0
62.5
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T
L
260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET, Designer’s and HDTMOS are trademarks of Motorola, Inc.
TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
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by MTP75N06HD/D
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
TMOS POWER FET
75 AMPERES
R
DS(on)
= 10.0 mOHM
60 VOLTS
Motorola Preferred Device
D
S
G
CASE 221A–06, Style 5
TO–220AB
MTP75N06HD
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(TJ = 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage (Cpk ≥ 2.0) (3)
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V
(BR)DSS
60
—
68
60.4
—
—
Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125°C)
I
DSS
—
—
—
—
10
100
µAdc
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 V) I
GSS
— 5.0 100 nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage (Cpk ≥ 5.0) (3)
(VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (Negative)
V
GS(th)
2.0
—
3.0
8.38
4.0
—
Vdc
mV/°C
Static Drain–Source On–Resistance (Cpk ≥ 2.0) (3)
(VGS = 10 Vdc, ID = 37.5 Adc)
R
DS(on)
— 8.3 10
mΩ
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 75 Adc)
(ID = 37.5 Adc, TJ = 125°C)
V
DS(on)
—
—
0.7
0.53
0.9
0.8
Vdc
Forward Transconductance (VDS = 15 Vdc, ID = 37.5 Adc) g
FS
15 32 — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
— 2800 3920 pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
C
oss
— 928 1300
Reverse Transfer Capacitance
f = 1.0 MHz)
C
rss
— 180 252
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
t
d(on)
— 18 26 ns
Rise Time
t
r
— 218 306
Turn–Off Delay Time
VGS = 10 Vdc,
RG = 9.1 Ω)
t
d(off)
— 67 94
Fall Time
G
= 9.1 Ω)
t
f
— 125 175
Q
T
— 71 100 nC
DS
= 48 Vdc, ID = 75 Adc,
Q
1
— 16.3 —
(VDS = 48 Vdc, ID = 75 Adc,
VGS = 10 Vdc)
Q
2
— 31 —
Q
3
— 29.4 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 75 Adc, VGS = 0 Vdc)
(IS = 75 Adc, VGS = 0 Vdc, TJ = 125°C)
V
SD
—
—
0.97
0.88
1.1
—
Vdc
t
rr
— 56 —
S
= 75 Adc, VGS = 0 Vdc,
t
a
— 44 —
(IS = 75 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
t
b
— 12 —
Reverse Recovery Stored Charge Q
RR
— 0.103 — µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
L
D
— 3.5 —
nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
S
— 7.5 — nH
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Cpk =
Max limit – Typ
3 x SIGMA
Gate Charge
Reverse Recovery Time
(VDS = 30 Vdc, ID = 75 Adc,
(V
(I
ns
MTP75N06HD
3
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
I
DSS
, LEAKAGE (nA)
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)TJ, JUNCTION TEMPERATURE (°C)
ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
I
D
, DRAIN CURRENT (AMPS)
I
D
, DRAIN CURRENT (AMPS)
0 0.5 1
Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics
0 50 150
Figure 3. On–Resistance versus Drain Current
and Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
1
1000
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–To–Source Leakage
Current versus Voltage
VDS ≥ 10 V
TJ = –55°C
25°C
– 50 – 25 0 25 50 75 100 125 150 0 10 20 6040
VGS = 0 V
TJ = 125°C
TJ = 25°C
VGS = 10 V
ID = 37.5 A
100
30
9 V
TJ = 25°C
100°C
25 75
15 V
150
0
21.5
100°C
0.016
0.012
0.009
0.007
0.006
1.9
1.6
1.3
1
0.7
2 54 73 6 8
125
100
75
50
25
VGS = 10 V
8 V
7 V
6 V
5 V
150
0
125
100
75
50
25
0.014
0.012
0.010
0.008
0.006
0.004
100 125
TJ = 25°C
VGS = 10 V
TJ = 100°C
25°C
–55°C
VGS = 10 V
0.010
0.008
0 50 15025 75 100 125
10
50
25°C
0.011
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