Motorola MTB60N06HD Datasheet

1

Motorola TMOS Power MOSFET Transistor Device Data

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

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N–Channel Enhancement–Mode Silicon Gate

The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower R

DS(on)

capabilities. This advanced
high–cell density HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a drain–to–source diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in p ower supplies, converters and PWM m otor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.

• Avalanche Energy Specified

• Source–to–Drain Diode Recovery Time Comparable to a

Discrete Fast Recovery Diode

• Diode is Characterized for Use in Bridge Circuits

• I

DSS

and V

DS(on)

Specified at Elevated Temperature

• Short Heatsink Tab Manufactured — Not Sheared

• Specially Designed Leadframe for Maximum Power Dissipation

• Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4

Suffix to Part Number

MAXIMUM RATINGS

(TC = 25°C unless otherwise noted)

Rating

Symbol Value Unit

Drain–Source Voltage V

DSS

60 Vdc

Drain–Gate Voltage (RGS = 1.0 MΩ) V

DGR

60 Vdc

Gate–Source Voltage — Continuous

Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)

V

GS

V

GSM

± 20
± 30

Vdc
Vpk

Drain Current — Continuous

Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)

I

D

I

D

I

DM

60

42.3
180

Adc

Apk

Total Power Dissipation

Derate above 25°C

Total Power Dissipation @ TA = 25°C (1)

P

D

125

1.0

2.5

Watts

W/°C

Watts

Operating and Storage Temperature Range TJ, T

stg

– 55 to 150 °C

Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C

(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 60 Apk, L = 0.3 mH, RG = 25 Ω)

E

AS

540 mJ

Thermal Resistance — Junction to Case

Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient, when mounted with the minimum recommended pad size

R

θJC

R

θJA

R

θJA

1.0

62.5
50

°C/W

Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T

L

260 °C

(1) When mounted with the minimum recommended pad size.

Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.

E–FET, Designer’s and HDTMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Order this document

by MTB60N06HD/D

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SEMICONDUCTOR TECHNICAL DATA



TMOS POWER FET

60 AMPERES

60 VOLTS

R

DS(on)

= 0.014 OHM

Motorola Preferred Device



D

S

G

CASE 418B–02, Style 2

D2PAK

 Motorola, Inc. 1995

MTB60N06HD

2

Motorola TMOS Power MOSFET Transistor Device Data

ELECTRICAL CHARACTERISTICS

(TJ = 25°C unless otherwise noted)

Characteristic

Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain–to–Source Breakdown Voltage (Cpk ≥ 2.0) (3)

(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)

V

(BR)DSS

60
—

—
71

—
—

Vdc

mV/°C

Zero Gate Voltage Drain Current

(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125°C)

I

DSS

—
—

—
—

10

100

µAdc

Gate–Body Leakage Current

(VGS = ± 20 Vdc, VDS = 0 Vdc)

I

GSS

— — 100

nAdc

ON CHARACTERISTICS (1)

Gate Threshold Voltage (Cpk ≥ 3.0) (3)

(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)

V

GS(th)

2.0
—

3.0

7.0

4.0
—

Vdc

mV/°C

Static Drain–Source On–Resistance (Cpk ≥ 3.0) (3)

(VGS = 10 Vdc, ID = 30 Adc)

R

DS(on)

— 0.011 0.014

Ohm

Drain–Source On–Voltage (VGS = 10 Vdc)

(ID = 60 Adc)
(ID = 30 Adc, TJ =125°C)

V

DS(on)

—
—

—
—

1.0

0.9

Vdc

Forward Transconductance

(VDS = 4.0 Vdc, ID = 30 Adc)

g

FS

15 20 —

mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

C

iss

— 1950 2800 pF

Output Capacitance

(VDS = 25 Vdc, VGS = 0 Vdc,

f = 1.0 MHz)

C

oss

— 660 920

Transfer Capacitance

f = 1.0 MHz)

C

rss

— 147 300

SWITCHING CHARACTERISTICS (2)

Turn–On Delay Time

t

d(on)

— 14 26 ns

Rise Time

t

r

— 197 394

Turn–Off Delay Time

VGS = 10 Vdc,

RG = 9.1 Ω)

t

d(off)

— 50 102

Fall Time

G

= 9.1 Ω)

t

f

— 124 246

Q

T

— 51 71 nC

(See Figure 8)

DS

= 48 Vdc, ID = 60 Adc,

Q

1

— 12 —

(VDS = 48 Vdc, ID = 60 Adc,

VGS = 10 Vdc)

Q

2

— 24 —

Q

3

— 21 —

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage

(IS = 60 Adc, VGS = 0 Vdc)

(IS = 60 Adc, VGS = 0 Vdc, TJ = 125°C)

V

SD

—
—

0.99

0.89

1.0
—

Vdc

t

rr

— 60 —

(See Figure 15)

S

= 60 Adc, VGS = 0 Vdc,

t

a

— 36 —

(IS = 60 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/µs)

t

b

— 24 —

Reverse Recovery Stored Charge Q

RR

— 0.143 — µC

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from the drain lead 0.25″ from package to center of die)

L

D

— 4.5 — nH

Internal Source Inductance

(Measured from the source lead 0.25″ from package to source bond pad)

L

S

— 7.5 — nH

(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.

Cpk =

Max limit – Typ

3 x SIGMA

Gate Charge

Reverse Recovery Time

(VDD= 30 Vdc, ID = 60 Adc,

(V

(I

ns

MTB60N06HD

3

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

R

DS(on)

, DRAIN–TO–SOURCE RESISTANCE (OHMS)

ID, DRAIN CURRENT (AMPS)

TJ, JUNCTION TEMPERATURE (

°

C) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

I

DSS

, LEAKAGE (nA)

ID, DRAIN CURRENT (AMPS)

I

D

, DRAIN CURRENT (AMPS)

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

I

D

, DRAIN CURRENT (AMPS)

0

20

40

80

120

100

60

0 1.0 2.0 3.0 4.0 5.0

0

20

40

80

120

Figure 1. On–Region Characteristics

2.0 2.8 3.6 4.4 6.0 7.6

Figure 2. Transfer Characteristics

0 20 40 60 80 120

0.006

0.008

0.012

0.016

0.020

0.0100

0.0108

0.0116

0.0124

0.0132

Figure 3. On–Resistance versus Drain Current

and Temperature

Figure 4. On–Resistance versus Drain Current

and Gate Voltage

– 50

0.6

0.8

1.0

1.4

1.8

0 10 20 40 50 60

1

10

100

1000

Figure 5. On–Resistance Variation with

Temperature

Figure 6. Drain–to–Source Leakage

Current versus Voltage

– 25 0 25 50 75 100 125 150

100

60

0.5 1.5 2.5 3.5 4.5 6.8

0.018

0.014

0.010

100 0 20 40 60 80 120100

0.0128

0.0120

0.0112

0.0104

1.2

1.6

30

VGS = 10 V

9 V

8 V

100°C

25°C

TJ = – 55°C

TJ = 25°C

15 V

VGS = 10 V

VGS = 10 V

– 55°C

VGS = 0 V

TJ = 125°C

100°C

25°C

5 V

6 V

TJ = 25°C

7 V

10 30 50 70 90 110 10 30 50 70 90 110

VDS ≥ 10 V

5.2

VGS = 10 V
ID = 30 A

TJ = 100°C

25°C

, DRAIN–TO–SOURCE RESISTANCE (OHMS)

DS(on)

R

(NORMALIZED)

, DRAIN–TO–SOURCE RESISTANCE

DS(on)

R

MTB60N06HD

4

Motorola TMOS Power MOSFET Transistor Device Data

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter­mined by how fast the FET input capacitance can be charged
by current from the generator.

The published capacitance data is difficult to use for calculat­ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly , gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I

G(AV)

) can be made from a rudimentary analysis of

the drive circuit so that
t = Q/I

G(AV)

During the rise and fall time interval when switching a resis­tive load, VGS remains virtually constant at a level known as
the plateau voltage, V

SGP

. Therefore, rise and fall times may

be approximated by the following:
tr = Q2 x RG/(VGG – V

GSP

)

tf = Q2 x RG/V

GSP

where
VGG = the gate drive voltage, which varies from zero to V

GG

RG = the gate drive resistance
and Q2 and V

GSP

are read from the gate charge curve.

During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val­ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

t

d(on)

= RG C

iss

In [VGG/(VGG – V

GSP

)]

t

d(off)

= RG C

iss

In (VGG/V

GSP

)

The capacitance (C

iss

) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal­culating t

d(on)

and is read at a voltage corresponding to the

on–state when calculating t

d(off)

.

At high switching speeds, parasitic circuit elements com­plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func­tion of drain current, the mathematical solution is complex.
The M OSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea­sure and, consequently, is not specified.

The resistive switching time variation versus gate resis­tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op­erated into an inductive load; however, snubbing reduces
switching losses.

GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)

C, CAPACITANCE (pF)

0

1000

2000

3000

5000

Figure 7. Capacitance Variation

4000

10 0 10 15 20 25

V

GS

V

DS

5 5

VDS = 0 V

C

iss

C

rss

VGS = 0 V

TJ = 25°C

C

iss

C

oss

C

rss