SEMICONDUCTOR TECHNICAL DATA
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N–Channel Enhancement–Mode Silicon Gate
This advanced high voltage TMOS E–FET is designed to
withstand high energy in the avalanche mode and switch efficiently .
This new high energy device also offers a drain–to–source diode
with fast recovery time. Designed for high voltage, high speed
switching applications in power supplies, PWM motor controls and
other inductive loads, the avalanche energy capability is specified
to eliminate the guesswork in designs where inductive loads are
switched and offer additional safety margin against unexpected
voltage transients.
• Avalanche Energy Capability Specified at Elevated
Temperature
• Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
G
• Low Stored Gate Charge for Efficient Switching
• Internal Source–to–Drain Diode Designed to Replace External
Zener Transient Suppressor–Absorbs High Energy in the
Avalanche Mode
• ESD Protected. Designed to Typically Withstand 400 V
Machine Model and 4000 V Human Body Model.
MAXIMUM RATINGS
Drain–to–Source Voltage V
Drain–to–Gate Voltage (RGS = 1.0 MΩ) V
Gate–to–Source Voltage — Continuous
Gate–to–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
Drain Current — Continuous @ TC = 25°C
Drain Current — Continuous @ TC = 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
Total Power Dissipation @ TC = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
Operating and Storage Temperature Range TJ, T
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VDS = 60 Vdc, VGS = 10 Vdc, Peak IL = 55 Apk, L = 0.3 mH, RG = 25 Ω)
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
(TJ = 25°C unless otherwise noted)
Rating
D
S
TMOS POWER FET
55 AMPERES
60 VOLTS
R
CASE 418B–02, Style 2
Symbol Value Unit
DSS
DGR
V
GS
V
GSM
I
D
I
D
I
DM
P
D
stg
E
AS
R
θJC
R
θJC
R
θJA
L
= 18 mΩ
DS(on)
D2PAK
60 Vdc
60 Vdc
±20
±40
55
35.5
165
113
0.91
2.5
– 55 to 150 °C
454 mJ
1.1
62.5
50
260 °C
Vdc
Vpk
Adc
Apk
Watts
W/°C
°C/W
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E–FET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
REV 1
Motorola TMOS Power MOSFET Transistor Device Data
Motorola, Inc. 1997
1
MTB55N06Z
ELECTRICAL CHARACTERISTICS
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Cpk ≥ 2.0)
(VGS = 0 Vdc, ID = 250 µAdc)
T emperature Coef ficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) I
ON CHARACTERISTICS (1)
Gate Threshold Voltage (Cpk ≥ 2.0)
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
Static Drain–to–Source On–Resistance (Cpk ≥ 2.0)
(VGS = 10 Vdc, ID = 27.5 Adc)
Drain–to–Source On–Voltage (VGS = 10 Vdc)
(ID = 55 Adc)
(ID = 27.5 Adc, TJ = 125°C)
Forward Transconductance (VDS = 4.0 Vdc, ID = 27.5 Adc) g
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
Reverse Recovery Time
Reverse Recovery Stored Charge Q
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(T
= 25°C unless otherwise noted)
C
Characteristic
(VDS = 25 Vdc, VGS = 0 Vdc,
(IS = 55 Adc, VGS = 0 Vdc, TJ = 125°C)
f = 1.0 MHz
(VDD = 30 Vdc, ID = 55 Adc,
(VDS = 48 Vdc, ID = 55 Adc,
(IS = 55 Adc, VGS = 0 Vdc)
(IS = 55 Adc, VGS = 0 Vdc,
= 10 Vdc,
GS(on)
RG = 9.1 Ω)
VGS = 10 Vdc)
dIS/dt = 100 A/µs)
Symbol Min Typ Max Unit
V
(BR)DSS
I
DSS
GSS
V
GS(th)
R
DS(on)
V
DS(on)
FS
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
Q
3
V
SD
t
rr
t
a
t
b
RR
L
D
L
S
60
—
—
—
— — 100 nAdc
2.0
—
— 14 18
—
—
12 15 — Mhos
— 1390 1950 pF
— 520 730
— 119 238
— 27 54 ns
— 157 314
— 116 232
— 126 252
— 40 56 nC
— 7.0 —
— 18 —
— 15 —
—
—
— 57 —
— 32 —
— 25 —
— 0.11 — µC
—
—
— 7.5 —
—
53
—
—
3.0
6.0
0.825
0.74
0.93
0.82
3.5
4.5
—
—
1.0
10
4.0
—
1.2
1.0
1.1
—
—
—
mV/°C
mV/°C
Vdc
µAdc
Vdc
mΩ
Vdc
Vdc
ns
nH
2
Motorola TMOS Power MOSFET Transistor Device Data