Motorola MTB52N06VL Datasheet

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SEMICONDUCTOR TECHNICAL DATA

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N–Channel Enhancement–Mode Silicon Gate

TMOS V is a new technology designed to achieve an on–resistance

area product about one–half that of standard MOSFETs. This new

TMOS POWER FET

52 AMPERES

60 VOLTS

R

DS(on)

= 0.025 OHM

technology more than doubles the present cell density of our 50
and 60 volt TMOS devices. Just as with our TMOS E–FET designs,
TMOS V is designed to withstand high energy in the avalanche and
commutation modes. Designed for low voltage, high speed
switching applications in power supplies, converters and power

TM

motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas

D

are critical and offer additional safety margin against unexpected
voltage transients.

New Features of TMOS V

• On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low R

DS(on)

Technology

• Faster Switching than E–FET Predecessors

G

S

CASE 418B–02, Style 2

D2PAK

Features Common to TMOS V and TMOS E–FETs

• Avalanche Energy Specified

• I

DSS

and V

Specified at Elevated Temperature

DS(on)

• Static Parameters are the Same for both TMOS V and TMOS E–FET

• Surface Mount Package Available in 16 mm 13–inch/2500 Unit

Tape & Reel, Add T4 Suffix to Part Number

MAXIMUM RATINGS

Drain–to–Source Voltage V
Drain–to–Gate Voltage (RGS = 1.0 MΩ) V
Gate–to–Source Voltage — Continuous

Drain Current — Continuous

Total Power Dissipation

Derate above 25°C

Total Power Dissipation @ TA = 25°C (1)
Operating and Storage Temperature Range TJ, T
Single Pulse Drain–to–Source Avalanche Energy — STAR TING TJ = 25°C

(VDD = 25 Vdc, VGS = 5 Vdc, PEAK IL = 52 Apk, L = 0.3 mH, RG = 25 Ω)

Thermal Resistance — Junction to Case

Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 seconds T

(1) When surface mounted to an FR4 board using the minimum recommended pad size.

Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.

E–FET, Designer’s, and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.

Preferred devices are Motorola recommended choices for future use and best overall value.

(TC = 25°C unless otherwise noted)

— Non–Repetitive (tp ≤ 10 ms)

— Continuous @ 100°C
— Single Pulse (tp ≤ 10 µs)

— Junction to Ambient
— Junction to Ambient (1)

Rating

Symbol Value Unit

60 Vdc
60 Vdc

±15
±25

52
41

182
188

1.25

3.0

– 55 to 175 °C

406 mJ

0.8

62.5
50

260 °C

Vdc
Vpk

Adc

Apk

Watts

W/°C

Watts

°C/W

V

V

I

E

R
R
R

DSS

DGR

GS

GSM

I

D

I

D

DM
P

D

stg

AS

θJC
θJA
θJA

L

REV 3

Motorola TMOS Power MOSFET Transistor Device Data

 Motorola, Inc. 1996

1

MTB52N06VL

)

f = 1.0 MHz)

V

G

)

(

DS

,

D

,

(

S

,

GS

,

ELECTRICAL CHARACTERISTICS

OFF CHARACTERISTICS

Drain–to–Source Breakdown Voltage (Cpk ≥ 2.0) (3)

(VGS = 0 Vdc, ID = .25 mAdc)
T emperature Coef ficient (Positive)

Zero Gate Voltage Drain Current

(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)

Gate–Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) I

ON CHARACTERISTICS (1)

Gate Threshold Voltage (Cpk ≥ 2.0) (3)

(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)

Static Drain–to–Source On–Resistance (Cpk ≥ 2.0) (3)

(VGS = 5 Vdc, ID = 26 Adc)

Drain–to–Source On–Voltage

(VGS = 5 Vdc, ID = 52 Adc)
(VGS = 5 Vdc, ID = 26 Adc, TJ = 150°C)

Forward Transconductance (VDS = 6.3 Vdc, ID = 20 Adc) g

DYNAMIC CHARACTERISTICS

Input Capacitance
Output Capacitance

Transfer Capacitance

SWITCHING CHARACTERISTICS (2)

Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge

(See Figure 8)

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage

Reverse Recovery Time

Reverse Recovery Stored Charge Q

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)

Internal Source Inductance

(Measured from the source lead 0.25″ from package to source bond pad)

(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.

Cpk =

(T

= 25°C unless otherwise noted)

J

Characteristic

(VDS = 25 Vdc, VGS = 0 Vdc,

(IS = 52 Adc, VGS = 0 Vdc, TJ = 150 °C)

Max limit – Typ

3 x SIGMA

f = 1.0 MHz

(VDD = 30 Vdc, ID = 52 Adc,

(VDS = 48 Vdc, ID = 52 Adc,

(IS = 52 Adc, VGS = 0 Vdc)

(IS = 52 Adc, VGS = 0 Vdc,

= 5 Vdc,

GS

RG = 9.1 Ω)

VGS = 5 Vdc)

dIS/dt = 100 A/µs)

Symbol Min Typ Max Unit

V

(BR)DSS

I

DSS

GSS

V

GS(th)

R

DS(on)

V

DS(on)

FS

C

iss

C

oss

C

rss

t

d(on)

t

r

t

d(off)

t

f

Q

T

Q

1

Q

2

Q

3

V

SD

t

rr

t

a

t

b

RR

L

D

L

S

60
—

—
—

— — 100 nAdc

1.0
—

— 0.022 0.025

—
—

17 30 — Mhos

— 1900 2660 pF
— 550 770
— 170 340

— 15 30 ns
— 500 1000
— 100 200
— 200 400
— 62 90 nC
— 4.0 —
— 31 —
— 16 —

—
—

— 104 —
— 63 —
— 41 —
— 0.28 — µC

—
—

— 7.5 —

—
65

—
—

1.5

4.5

—
—

1.03

0.9

3.5

4.5

—
—

10

100

2.0
—

1.6

1.4

1.5
—

—
—

mV/°C

mV/°C

Vdc

µAdc

Vdc

Ohm

Vdc

Vdc

ns

nH

nH

2

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

MTB52N06VL

110
100

90
80
70
60
50
40

, DRAIN CURRENT (AMPS)

30

D

I

20
10

0

.070

.060

.050

.040

.030

.020

, DRAIN–TO–SOURCE RESIST ANCE (OHMS)

.010

DS(on)

0

R

VGS = 10 V

8 V
7 V

13579

VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

6 V

20 1.0 532.5

46810

TJ = 25°C

5 V

4 V

3 V

110
100

90
80
70
60
50
40

, DRAIN CURRENT (AMPS)

30

D

I

20
10

0

VDS ≥ 10 V

2461.5

VGS, GATE–T O–SOURCE VOLT AGE (VOLTS)

3.5 4.5 5.50.5

Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics

VGS = 5 V

200

TJ = 100°C

25°C

–55°C

3010 50 70 90 110

40 60 80 100

ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)

.040
.035
.030

.025
.020
.015
.010

, DRAIN–TO–SOURCE RESIST ANCE (OHMS)

.005

0

DS(on)

R

TJ = 25°C

VGS = 5 V

10 V

10 30 50 70 90

0

20 40 60 80 110

TJ = –55°C

100°C

25°C

100

Figure 3. On–Resistance versus Drain Current

and T emperature

1.8
VGS = 5 V

1.6

ID = 26 A

1.4

1.2

1

0.8

(NORMALIZED)

0.6

, DRAIN–TO–SOURCE RESIST ANCE

0.4

0.2

DS(on)

R

0

–50 –25 0 25 50 75 100 125 150

TJ, JUNCTION TEMPERATURE (

Figure 5. On–Resistance Variation with

Temperature

Figure 4. On–Resistance versus Drain Current

and Gate Voltage

1000

VGS = 0 V

TJ = 125°C

100

100°C

, LEAKAGE (nA)

10

DSS

I

1

175

°

C) VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

0102030405060

Figure 6. Drain–T o–Source Leakage

Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data

3