Motorola MTB50P03HDL Datasheet
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTB50P03HDL/D
# "
! !
P–Channel Enhancement–Mode Silicon Gate
The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower R
high–cell density HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a drain–to–source diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• I
DSS
and V
Specified at Elevated Temperature
DS(on)
• Short Heatsink Tab Manufactured — Not Sheared
• Specially Designed Leadframe for Maximum Power Dissipation
• Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4
Suffix to Part Number
capabilities. This advanced
DS(on)
G
Motorola Preferred Device
TMOS POWER FET
LOGIC LEVEL
50 AMPERES
30 VOLTS
R
D
CASE 418B–03, Style 2
S
DS(on)
= 0.025 OHM
D2PAK
MAXIMUM RATINGS
Drain–Source Voltage V
Drain–Gate Voltage (RGS = 1.0 MΩ) V
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TC = 25°C, when mounted with the minimum recommended pad size
Operating and Storage Temperature Range TJ, T
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 50 Apk, L = 1.0 mH, RG = 25 Ω)
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient, when mounted with the minimum recommended pad size
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s, E–FET, and HDTMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
(TC = 25°C unless otherwise noted)
Rating Symbol Value Unit
V
V
I
E
R
R
R
DSS
DGR
GS
GSM
I
D
I
D
DM
P
D
stg
AS
θJC
θJA
θJA
L
30 Vdc
30 Vdc
±15
± 20
50
31
150
125
1.0
2.5
– 55 to 150 °C
1250 mJ
1.0
62.5
50
260 °C
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
°C/W
REV 2
Motorola TMOS Power MOSFET Transistor Device Data
Motorola, Inc. 1997
1
MTB50P03HDL
)
f = 1.0 MHz)
V
G
)
(
DS
,
D
,
(
S
,
GS
,
ELECTRICAL CHARACTERISTICS
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Cpk ≥ 2.0) (3)
(VGS = 0 Vdc, ID = 250 µAdc)
T emperature Coef ficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 30 Vdc, VGS = 0 Vdc)
(VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current
(VGS = ±15 Vdc, VDS = 0 Vdc)
ON CHARACTERISTICS (1)
Gate Threshold Voltage (Cpk ≥ 3.0) (3)
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
Static Drain–Source On–Resistance (Cpk ≥ 3.0) (3)
(VGS = 5.0 Vdc, ID = 25 Adc)
Drain–Source On–Voltage (VGS = 5.0 Vdc)
(ID = 50 Adc)
(ID = 25 Adc, TJ =125°C)
Forward Transconductance
(VDS = 5.0 Vdc, ID = 25 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
Reverse Recovery Time
(See Figure 15)
Reverse Recovery Stored Charge Q
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Cpk =
(TJ = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
(VDS = 25 Vdc, VGS = 0 Vdc,
(IS = 50 Adc, VGS = 0 Vdc, TJ = 125°C)
Max limit – Typ
3 x SIGMA
f = 1.0 MHz
(VDD= 15 Vdc, ID = 50 Adc,
= 5.0 Vdc,
GS
RG = 2.3 Ω)
(VDS = 24 Vdc, ID = 50 Adc,
VGS = 5.0 Vdc)
(IS = 50 Adc, VGS = 0 Vdc)
(IS = 50 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
V
DS(on)
g
FS
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
Q
Q
Q
V
SD
t
rr
t
a
t
b
RR
L
D
L
S
30
—
—
—
— — 100
1.0
—
— 20.9 25
—
—
15 20 —
— 3500 4900 pF
— 1550 2170
— 550 770
— 22 30 ns
— 340 466
— 90 117
— 218 300
T
1
2
3
— 74 100 nC
— 13.6 —
— 44.8 —
— 35 —
—
—
— 106 —
— 58 —
— 48 —
— 0.246 — µC
— 3.5 — nH
— 7.5 — nH
—
26
—
—
1.5
4.0
0.83
—
2.39
1.84
—
—
1.0
10
2.0
—
1.5
1.3
3.0
—
Vdc
mV/°C
µAdc
nAdc
Vdc
mV/°C
mOhm
Vdc
mhos
Vdc
ns
2
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
MTB50P03HDL
100
TJ = 25°C
80
60
40
, DRAIN CURRENT (AMPS)
D
I
20
0
0 0.4 0.8 1.2 1.6 2.0
0.2 0.6 1.0 1.4 1.8 3.9
VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS) VGS, GATE–T O–SOURCE VOLT AGE (VOLTS)
4.5 V
VGS = 10 V
8 V
6 V
Figure 1. On–Region Characteristics
0.029
VGS = 5 V
0.027
0.025
0.023
0.021
TJ = 100°C
25°C
5 V
4 V
3.5 V
3 V
2.5 V
100
VDS ≥ 5 V
80
60
40
, DRAIN CURRENT (AMPS)
D
I
20
0
1.5 1.9 2.3 2.7 3.5 4.3
TJ = – 55°C
25°C
3.1
Figure 2. Transfer Characteristics
0.022
TJ = 25°C
0.021
0.020
0.019
0.018
VGS = 5 V
100°C
0.019
, DRAIN–TO–SOURCE RESIST ANCE (OHMS)
0.017
DS(on)
0.015
R
0 20406080100
ID, DRAIN CURRENT (AMPS)
–55°C
Figure 3. On–Resistance versus Drain Current
and T emperature
1.35
VGS = 5 V
ID = 25 A
1.25
1.15
1.05
(NORMALIZED)
, DRAIN–TO–SOURCE RESIST ANCE
0.95
DS(on)
R
0.85
–50
– 25 0 25 50 75 100 125 150
°
TJ, JUNCTION TEMPERATURE (
C) VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)
0.017
, DRAIN–TO–SOURCE RESIST ANCE (OHMS)
0.016
0.015
DS(on)
R
020406080100
ID, DRAIN CURRENT (AMPS)
10 V
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
1000
VGS = 0 V
TJ = 125°C
100
, LEAKAGE (nA)
DSS
I
100°C
10
0 5 10 20 25 30
15
Figure 5. On–Resistance Variation with
Temperature
Motorola TMOS Power MOSFET Transistor Device Data
Figure 6. Drain–to–Source Leakage
Current versus Voltage
3
MTB50P03HDL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly , gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I
) can be made from a rudimentary analysis of
G(A V)
the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, V
. Therefore, rise and fall times may
SGP
be approximated by the following:
tr = Q2 x RG/(VGG – V
tf = Q2 x RG/V
GSP
GSP
)
where
VGG = the gate drive voltage, which varies from zero to V
GG
RG = the gate drive resistance
and Q2 and V
are read from the gate charge curve.
GSP
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
t
d(off)
= RG C
= RG C
In [VGG/(VGG – V
iss
In (VGG/V
iss
GSP
)]
GSP
)
The capacitance (C
) is read from the capacitance curve at
iss
a voltage corresponding to the off–state condition when calculating t
on–state when calculating t
and is read at a voltage corresponding to the
d(on)
d(off)
.
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently , is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.
14000
VDS = 0 V
C
iss
12000
10000
8000
C
rss
6000
C, CAPACITANCE (pF)
4000
2000
0
10 0 10 15 20 25
55
V
GATE–T O–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
GS
VGS = 0 V
V
DS
C
iss
C
oss
C
rss
Figure 7. Capacitance Variation
TJ = 25°C
4
Motorola TMOS Power MOSFET Transistor Device Data
Loading...