Motorola MTB3N120E Datasheet
1
Motorola TMOS Power MOSFET Transistor Device Data
$ #
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N–Channel Enhancement–Mode Silicon Gate
The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower R
DS(on)
capabilities. This high voltage
MOSFET uses a n advanced t ermination scheme to p rovide
enhanced voltage–blocking capability without degrading performance over time. In addition, this advanced TMOS E–FET is
designed to withstand high energy in the avalanche and commutation modes. T his new e nergy e fficient design a lso offers a
drain–to–source diode with a fast recovery time. Designed for low
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
• Avalanche Energy Capability Specified at Elevated Temperature
• Low Stored Gate Charge for Efficient Switching
• Internal Source–to–Drain Diode Designed to Replace External Zener Transient Suppressor Absorbs High Energy in the
Avalanche Mode
• Source–to–Drain Diode Recovery time Comparable to Discrete Fast Recovery Diode
* See App. Note AN1327 – Very Wide Input Voltage Range; Off–line Flyback Switching Power Supply
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain–Source Voltage V
DSS
1200 Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ) V
DGR
1200 Vdc
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
V
GS
V
GSM
± 20
± 40
Vdc
Vpk
Drain Current — Continuous @ 25°C
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
I
D
I
D
I
DM
3.0
2.2
11
Adc
Apk
Total Power Dissipation @ TC = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
P
D
125
1.0
2.5
Watts
W/°C
Watts
Operating and Storage Temperature Range TJ, T
stg
– 55 to 150 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc, PEAK IL = 4.5 Apk, L = 10 mH, RG = 25 Ω)
E
AS
101
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
R
θJC
R
θJA
R
θJA
1.0
62.5
50
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T
L
260 °C
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
E–FET and Designer’s are trademarks of Motorola, Inc.
TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTB3N120E/D
Motorola, Inc. 1995
TMOS POWER FET
3.0 AMPERES
1200 VOLTS
R
DS(on)
= 5.0 OHM
CASE 418B–02, Style 2
D2PAK
Motorola Preferred Device
D
S
G
MTB3N120E
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V
(BR)DSS
1200
—
—
1.28
—
—
Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 1200 Vdc, VGS = 0 Vdc)
(VDS = 1200 Vdc, VGS = 0 Vdc, TJ = 125°C)
I
DSS
—
—
—
—
10
100
µAdc
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) I
GSS
— — 100 nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (Negative)
V
GS(th)
2.0
—
3.0
7.1
4.0
—
Vdc
mV/°C
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 1.5 Adc) R
DS(on)
— 4.0 5.0 Ohm
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 3.0 Adc)
(ID = 1.5 Adc, TJ = 125°C)
V
DS(on)
—
—
—
—
18.0
15.8
Vdc
Forward Transconductance (VDS = 15 Vdc, ID = 1.5 Adc) g
FS
2.5 3.1 — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
— 2130 2980 pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
C
oss
— 1710 2390
Reverse Transfer Capacitance
f = 1.0 MHz)
C
rss
— 932 1860
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
t
d(on)
— 13.6 30 ns
Rise Time
t
r
— 12.6 30
Turn–Off Delay Time
VGS = 10 Vdc,
RG = 9.1 Ω)
t
d(off)
— 35.8 70
Fall Time
G
= 9.1 Ω)
t
f
— 20.7 40
Q
T
— 31 40 nC
DS
= 600 Vdc, ID = 3.0 Adc,
Q
1
— 8.0 —
(VDS = 600 Vdc, ID = 3.0 Adc,
VGS = 10 Vdc)
Q
2
— 11 —
Q
3
— 14 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1)
(IS = 3.0 Adc, VGS = 0 Vdc)
(IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125°C)
V
SD
—
—
0.80
0.65
1.0
—
Vdc
t
rr
— 394 —
S
= 3.0 Adc, VGS = 0 Vdc,
t
a
— 118 —
(IS = 3.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
t
b
— 276 —
Reverse Recovery Stored Charge Q
RR
— 2.11 — µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
L
D
— 4.5 — nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
S
— 7.5 —
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
Gate Charge
Reverse Recovery Time
(VDD = 600 Vdc, ID = 3.0 Adc,
(V
(I
ns
MTB3N120E
3
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
10,000
1,000
100
10
1
0 400 600 1000 1200
100°C
25°C
2.5
2.0
1.5
1.0
0.5
0
–50 –25 0 25 50 75 100 125 150
VGS = 10 V
ID = 1.5 A
5.4
5.0
4.6
4.2
3.8
ID, DRAIN CURRENT (AMPS)
15 V
8
2
0
0 2 4 6531
6
0
0 6 12 18
24 30
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
I
D
, DRAIN CURRENT (AMPS)
I
D
, DRAIN CURRENT (AMPS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On–Resistance Variation with
Temperature
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 6. Drain–To–Source Leakage
Current versus Voltage
I
DSS
, LEAKAGE (nA)
VDS ≥ 10 V
TJ = 100°C
–55°C
TJ = 25°C
VGS = 10 V
VGS = 0 V
5
4
3
2
3 3.4 3.8 4.2 4.6 5.0 5.4 5.8 6.2
0 2 4 6531
TJ = 125°C
1
6
4
200
25°C
TJ = –55°C
100°C
25°C
4 V
5 V
6 V
VGS = 10 V
TJ = 25°C
6
0
5
4
3
2
1
800
VGS = 10 V
MTB3N120E
4
Motorola TMOS Power MOSFET Transistor Device Data
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly , gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I
G(AV)
) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, V
SGP
. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – V
GSP
)
tf = Q2 x RG/V
GSP
where
VGG = the gate drive voltage, which varies from zero to V
GG
RG = the gate drive resistance
and Q2 and V
GSP
are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= RG C
iss
In [VGG/(VGG – V
GSP
)]
t
d(off)
= RG C
iss
In (VGG/V
GSP
)
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off–state condition when calculating t
d(on)
and is read at a voltage corresponding to the
on–state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The M OSFET output capacitance also c omplicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.
10,000
1,000
10
10 100 1000
2400
2000
1600
1200
800
400
0
10 5 0 5 10 15 20 25
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
Figure 7a. Capacitance Variation
V
GS
V
DS
Figure 7b. High Voltage Capacitance
Variation
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
TJ = 25°C
C
iss
C
rss
VGS = 0 V
TJ = 25
°
C
C
iss
C
oss
C
rss
C
iss
C
oss
C
rss
100
2800
VDS = 0 V VGS = 0 V
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