Motorola MTB23P06V Datasheet
1
Motorola TMOS Power MOSFET Transistor Device Data
!
P–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resistance area product about one–half that of standard MOSFET s. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
New Features of TMOS V
• On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low R
DS(on)
Technology
• Faster Switching than E–FET Predecessors
Features Common to TMOS V and TMOS E–FETS
• Avalanche Energy Specified
• I
DSS
and V
DS(on)
Specified at Elevated Temperature
• Static Parameters are the Same for both TMOS V and TMOS E–FET
• Surface Mount Package Available in 16 mm 13–inch/2500 Unit Tape & Reel,
Add T4 Suffix to Part Number
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain–to–Source Voltage V
DSS
60 Vdc
Drain–to–Gate Voltage (RGS = 1.0 MΩ) V
DGR
60 Vdc
Gate–to–Source Voltage — Continuous
Gate–to–Source Voltage — Non–repetitive (tp ≤ 10 ms)
V
GS
V
GSM
± 15
± 25
Vdc
Vpk
Drain Current — Continuous @ 25°C
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
I
D
I
D
I
DM
23
15
81
Adc
Apk
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
P
D
90
0.60
3.0
Watts
W/°C
Operating and Storage Temperature Range TJ, T
stg
–55 to 175 °C
Single Pulse Drain–to–Source Avalanche Energy — STARTING TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, PEAK IL = 23 Apk, L = 3.0 mH, RG = 25 Ω)
E
AS
794 mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
R
θJC
R
θJA
R
θJA
1.67
62.5
50
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 seconds T
L
260 °C
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designer’s Data for “Worst Case” Conditions —The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET, Designer’s and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
Order this document
by MTB23P06V/D
SEMICONDUCTOR TECHNICAL DATA
TMOS POWER FET
23 AMPERES
60 VOLTS
R
DS(on)
= 0.120 OHM
Motorola Preferred Device
D
S
G
TM
CASE 418B–02, Style 2
D2PAK
Motorola, Inc. 1996
MTB23P06V
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
V
(BR)DSS
60
—
—
60.5
—
—
Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
I
DSS
—
—
—
—
10
100
µAdc
Gate–Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) I
GSS
— — 100 nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
V
GS(th)
2.0
—
2.8
5.3
4.0
—
Vdc
mV/°C
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 11.5 Adc) R
DS(on)
— 0.093 0.12 Ohm
Drain–Source On–Voltage
(VGS = 10 Vdc, ID = 23 Adc)
(VGS = 10 Vdc, ID = 11.5 Adc, TJ = 150°C)
V
DS(on)
—
—
2.1
—
3.3
3.2
Vdc
Forward Transconductance
(VDS = 10.9 Vdc, ID = 11.5 Adc)
g
FS
5.0 11.5 —
Mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
— 1160 1620 pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
C
oss
— 380 530
Transfer Capacitance
f = 1.0 MHz)
C
rss
— 105 210
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
t
d(on)
— 13.8 30 ns
Rise Time
t
r
— 98.3 200
Turn–Off Delay Time
VGS = 10 Vdc,
RG = 9.1 Ω)
t
d(off)
— 41 80
Fall Time
G
= 9.1 Ω)
t
f
— 62 120
Q
T
— 38 50 nC
(See Figure 8)
DS
= 48 Vdc, ID = 23 Adc,
Q
1
— 7.0 —
(VDS = 48 Vdc, ID = 23 Adc,
VGS = 10 Vdc)
Q
2
— 18 —
Q
3
— 14 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 23 Adc, VGS = 0 Vdc)
(IS = 23 Adc, VGS = 0 Vdc, TJ = 150°C)
V
SD
—
—
2.2
1.8
3.5
—
Vdc
t
rr
— 142 —
S
= 23 Adc, VGS = 0 Vdc,
t
a
— 100 —
(IS = 23 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
t
b
— 41 —
Reverse Recovery Stored Charge Q
RR
— 0.804 — µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
L
D
— 3.5
4.5
—
nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
S
— 7.5 — nH
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
Gate Charge
Reverse Recovery Time
(VDD = 30 Vdc, ID = 23 Adc,
(V
(I
ns
MTB23P06V
3
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
0 2 4 6 8 10
0
10
20
30
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
I
D
, DRAIN CURRENT (AMPS)
30
35
2 3 4 8
0
5
10
15
40
I
D
, DRAIN CURRENT (AMPS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
0 5 10 15 20 25
0.14
0.02
0.04
0.06
0.12
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
0 5 10 15 20 30
0.08
0.085
0.09
0.095
0.11
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and Temperature
ID, DRAIN CURRENT (AMPS)
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
–50
0
0.2
0.4
0.6
1.8
0 10 20 30 40
1
50
10
100
TJ, JUNCTION TEMPERATURE (
°
C)
Figure 5. On–Resistance Variation with
Temperature
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 6. Drain–To–Source Leakage
Current versus Voltage
I
DSS
, LEAKAGE (nA)
TJ = 125°C
15 V
–25 0 25 50 75 100 150
TJ = 25
°C
VDS ≥ 10 V
TJ = –55
°C
25
°C
100°C
TJ = 100
°C
25
°C
–55
°C
TJ = 25
°C
VGS = 0 V
VGS = 10V
VGS = 10 V
VGS = 10 V
VGS = 10 V
ID = 11.5 A
40
50
7 V
6 V
5 V
4 V
8 V
9 V
20
25
5 6 7
0.08
0.1
30
0.1
0.105
25
0.8
1
1.2
1.4
1.6
125
60
0.16
35 40 45 35 40 45 50
0.115
0.12
175
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