SEMICONDUCTOR TECHNICAL DATA
The MRFIC Line
!
Designed primarily for use in high efficiency Analog Cellular applications,
the MRFIC0912 is a two–stage power amplifier in Motorola’s proprietary
Power Flat Pack 16–lead package. This integrated circuit requires minimal
off-chip matching while allowing for the maximum in flexibility in optimizing
gain and efficiency. The design employs Motorola’s planar, self–aligned GaAs
MESFET IC process to give the highest efficiency possible.
• Usable Frequency Range = 800–1000 MHz, Specified for 824–905 MHz
• 30.8 dBm Minimum Output Power
• 470 mA Maximum Supply Current at 30.8 dBm Output
• 23.8 dB Minimum Gain
• Simple Off–chip Matching for Maximum Power/Efficiency Flexibility
• 4.6 Volt Supply
• 45 dB/Volt Typical Power Output Control
• Order MRFIC0912R2 for Tape and Reel Option.
R2 Suffix = 1,500 Units per 16 mm, 13 inch Reel.
• Device Marking = M0912
Order this document
by MRFIC0912/D
900 MHz
GaAs INTEGRATED
POWER AMPLIFIER
CASE 978–02
(PFP–16)
GND
V
N/C
V
D1
N/C
V
G1
RF IN
N/C
G2
1
2
3
4
5
6
7
8
Pin Connections and Functional Block Diagram
16
15
14
13
12
11
10
9
N/C
N/C
N/C
RF OUT/V
RF OUT/V
RF OUT/V
N/C
GND
D2
D2
D2
REV 1
Motorola, Inc. 1997
MOTOROLA RF DEVICE DATA
MRFIC0912
1
MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Ratings Symbol Limit Unit
Supply Voltage VD1, V
RF Input Power P
Gate Voltage VG1, VG2, V
Storage Temperature Range T
Operating Case Temperature T
Thermal Resistance, Junction to Case R
RF
stg
C
θJC
RECOMMENDED OPERATING RANGES
Parameter
RF Frequency f
Supply Voltage VD1, V
Gate Voltage VG1, V
Symbol Value Unit
RF
D2
D2
G2
GG
8 Vdc
20 dBm
–5 Vdc
– 65 to +150 °C
– 35 to +100 °C
18 °C/W
824–905 MHz
4.0–6.0 Vdc
–2.3 to –1.5 Vdc
ELECTRICAL CHARACTERISTICS (V
Circuit Shown in Figure 1)
Characteristic
RF Output Power 30.8 31.2 — dBm
Power Slump (VD1, VD2 = 4.0 V, TC = 100_C)
Load Mismatch Survival (VD1, VD2 = 7 V, Load VSWR = 10:1, all phases,
10 sec)
Spurious Output (VD1,VD2 = 0 to 7 V, Pin = 5 to 9 dBm, Load
VSWR = 10:1)
Input Return Loss — 10 — dB
Harmonic Output (P
2f
0
3f
0
4f
0
Noise Power (VDD = 0 to 7 V, 45 MHz Above fRF at 30 kHz BW) — — –93 dBm
Maximum Power Control Voltage Slope (Change in P
VD1)
Total Supply Current (VD1 set for P
VGG Required for I
Gate Current during RF Operation –2 — 2 mA
= 30.8 dBm)
out
out
= 200 mA –2.3 –2.0 –1.7 Vdc
D2Q
, VD2 = 4.6 V , TA = 25°C, fRF = 840 MHz, Pin = 7 dBm, VGG set for I
D1
Min Typ Max Unit
28.5 — — dBm
No Degradation
— — –60 dBc
—
—
—
for Change on
out
= 30.8 dBm) — 430 470 mA
— 45 — dB/V
—
—
—
= 200 mA, T ested in
D2Q
–25
–40
–40
dBc
DESIGN AND APPLICATIONS INFORMATION
The MRFIC0912 has been designed for high efficiency
900 MHz applications such as analog cellular and Industrial,
Medical and Scientific (ISM) equipment. The two stage MESFET design utilizes Motorola’s planar refractory gate process
to allow high performance GaAs to be applied to consumer
applications. The proprietary PFP–16 package assures good
grounding and low thermal resistance.
As shown in Figure 1, the gate voltage pins can be ganged
together and one voltage applied to both gates to set the
quiescent operating current. Alternatively , VG1 and VG2 can
be set separately. VD1 can be used as power control with a
45 dB per volt sensitivity. The placement of C3 in the V
D1
supply line can be varied to optimize RF performance since
T2 is part of a shunt L matching section. On the output, pins
MRFIC0912
2
11, 12 and 13, the placement of C11 is adjusted for best RF
performance.
Layout is important for amplifier stability and RF performance. Ground vias must be located as close to circuit
ground connections as possible. Power supply bypassing
C3, C6, C9, and C10 must be included to reduce out–of–
band gain and prevent spurious output.
Evaluation Boards
Evaluation boards are available for RF Monolithic Integrated Circuits by adding a “TF” suffix to the device type.
For a complete list of currently available boards and ones
in development for newly introduced product, please con tact your local Motorola Distributor or Sales Office.
MOTOROLA RF DEVICE DATA