Motorola MPC947FA Datasheet
SEMICONDUCTOR TECHNICAL DATA
1
REV 3
Motorola, Inc. 1997
1/97
!
The MPC947 is a 1:9 low voltage clock distribution chip. The device
features the capability to select between two LVTTL compatible inputs
and fans the signal out to 9 LVCMOS or LVTTL compatible outputs.
These 9 outputs were designed and optimized to drive 50Ω series
terminated transmission lines. With output–to–output skews of 500ps, the
MPC947 is ideal as a clock distribution chip for synchronous systems
which need a tight level of skew at a relatively low cost. For a similar
product targeted at a higher price/performance point, consult the
MPC948 data sheet.
• Clock Distribution for PowerPC 620 L2 Cache
• 2 Selectable LVCMOS/LVTTL Clock Inputs
• 500ps Maximum Output–to–Output Skew
• Drives Up to 18 Independent Clock Lines
• Maximum Output Frequency of 110MHz
• Synchronous Output Enable
• Tristatable Outputs
• 32–Lead TQFP Packaging
• 3.3V V
CC
Supply Voltage
With an output impedance of approximately 7Ω, in both the HIGH and
LOW logic states, the output buffers of the MPC947 are ideal for driving
series terminated transmission lines. More specifically, each of the 9
MPC947 outputs can drive two series terminated 50Ω transmission lines.
With this capability, the MPC947 has an effective fanout of 1:18 in
applications using point–to–point distribution schemes. With this level of
fanout, the MPC947 provides enough copies of low skew clocks for high
performance synchronous systems, including use as a clock distribution
chip for the L2 cache of a PowerPC 620 based system.
Two independent LVCMOS/LVTTL compatible clock inputs are available. Designers can take advantage of this feature to
provide redundant clock sources or the addition of a test clock into the system design. With the select input pulled HIGH, the
TTL_CLK1 input will be selected.
All of the control inputs are LVCMOS/LVTTL compatible. The MPC947 provides a synchronous output enable control to allow
for starting and stopping of the output clocks. A logic high on the Sync_OE pin will enable all of the outputs. Because this control
is synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. In addition, for board level test,
the outputs can be tristated via the tristate control pin. A logic LOW applied to the Tristate
input will force all of the outputs into
high impedance. Note that all of the MPC947 inputs have internal pullup resistors.
The MPC947 is fully 3.3V compatible. The 32–lead TQFP package was chosen to optimize performance, board space and
cost of the device. The 32–lead TQFP has a 7x7mm body size with a conservative 0.8mm pin spacing.
PowerPC is a trademark of International Business Machines Corporation.
FA SUFFIX
32–LEAD TQFP PACKAGE
CASE 873A–02
LOW VOLTAGE
1:9 CLOCK
DISTRIBUTION CHIP
MPC947
MOTOROLA TIMING SOLUTIONS
BR1333 — Rev 6
2
GND
Q2
VCCO
Q1
GND
Q0
VCCO
GND
GND
Q6
VCCO
Q7
GND
Q8
VCCO
GND
GND
Q3
VCCOQ4GND
Q5
VCCO
GND
GND
TTL_CLK1_Sel
TTL_CLK0
TTL_CLK1
Sync_OE
Tristate
VCCI
GND
25
26
27
28
29
30
31
32
15
14
13
12
11
10
9
12345678
24 23 22 21 20 19 18 17
16
MPC947
FUNCTION TABLES
TTL_CLK1_Sel Input
0
1
TTL_CLK0
TTL_CLK1
Sync_OE Outputs
0
1
Disabled
Enabled
Tristate Outputs
0
1
Tristate
Enabled
TTL_CLK
Figure 1. Logic Diagram
TTL_CLK1
Q0–Q8
TTL_CLK0
0
1
TTL_CLK1_Sel
Sync_OE
Tristate
9
DQ
Sync_OE
Q
Figure 2. 32–Lead Pinout (Top View)
Figure 3. Sync_OE Timing Diagram
Loading...