Motorola MPC940LFA Datasheet
SEMICONDUCTOR TECHNICAL DATA
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The MPC940L is a 1:18 low voltage clock distribution chip with 2.5V
LVCMOS output capabilities. The device features the capability to select
either a differential L VPECL or an L VTTL/ L VCMOS compatible input. The
18 outputs are 2.5V LVCMOS compatible and feature the drive strength
to drive 50Ω series or parallel terminated transmission lines. With
output–to–output skews of 150ps, the MPC940L is ideal as a clock
distribution chip for the most demanding of synchronous systems. The
2.5V outputs also make the device ideal for supplying clocks for a high
performance Pentium II microprocessor based design.
• LVPECL or LVCMOS/LVTTL Clock Input
• 2.5V LVCMOS Outputs for Pentium II Microprocessor Support
• 150ps Maximum Targeted Output–to–Output Skew
• Maximum Output Frequency of 250MHz
• 32–Lead TQFP Packaging
• Dual V
With a low output impedance (≈30Ω), in both the HIGH and LOW logic
states, the output buffers of the MPC940L are ideal for driving series
terminated transmission lines. With this drive capability, the MPC940L
provides enough copies of low skew clocks for most high performance
synchronous systems.
The differential LVPECL inputs of the MPC940L allow the device to interface directly with a LVPECL fanout buffer like the
MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS/LVTTL input
provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In
addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH
on the LVCMOS_CLK_Sel pin will select the TTL level clock input.
The MPC940L is a dual supply device. The core VCC power pins (VCCI) require 3.3V with the output VCC pins (VCCO)
requiring 2.5V. The 32–lead TQFP package was chosen to optimize performance, board space and cost of the device. The
32–lead TQFP has a 7x7mm body size with a conservative 0.8mm pin spacing.
Supply Voltage, 3.3V Core and 2.5V Output
CC
LOW VOLTAGE
1:18 CLOCK
DISTRIBUTION CHIP
FA SUFFIX
32–LEAD TQFP PACKAGE
CASE 873A–02
Pentium II is a trademark of Intel Corporation.
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
10/97
Motorola, Inc. 1997
1
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MPC940L
LOGIC DIAGRAM
GNDO
Q5
Q4
Q3
VCCO
PECL_CLK
PECL_CLK
LVCMOS_CLK
LVCMOS_CLK_Sel
0
1
Pinout: 32–Lead TQFP (Top View)
Q6
Q7
Q8
VCCIQ9Q10
24 23 22 21 20 19 18 17
25
26
27
28
29
MPC940L
Q0
16
Q1–Q16
Q17
Q11
GND
16
15
14
13
12
VCCO
Q12
Q13
Q14
GNDO
FUNCTION TABLE
LVCMOS_CLK_Sel Input
0
1
PECL_CLK
LVCMOS_CLK
Q2
Q1
Q0
30
31
32
12345678
GNDO
GNDI
PECL_CLK
LVCMOS_CLK
LVCMOS_CLK_Sel
VCCI
PECL_CLK
11
10
9
VCCO
Q15
Q16
Q17
POWER SUPPLY VOLTAGES
Supply Pin
VCCI
VCCO
V oltage Level
3.3V ± 5%
2.5V ± 5%
MOTOROLA TIMING SOLUTIONS
2
BR1333 — Rev 6
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