Motorola MPC932FA Datasheet

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SEMICONDUCTOR TECHNICAL DATA

1

REV 0

 Motorola, Inc. 1996

11/96

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The MPC932 is a 3.3V compatible PLL based clock driver device
targetted for zero delay applications. The device provides 6 outputs for
driving clock loads plus a single dedicated PLL feedback clock output.
The dedicated feedback output gives the user six choices of input
multiplcation factors: x1, x1.25, x1.5, x2, x2.5 and x3.

• 6 Low Skew Clock Outputs

• 1 Dedicated PLL Feedback Output

• Individual Output Enable Control

• Fully Integrated PLL

• Output Frequency Up TO 120MHz

• 32–lead TQFP Packaging

• 3.3V VCC

• ±100ps Cycle–Cycle Jitter

The MPC932 provides individual output enable control. The enables
are synchronized to the internal clock such that upon assertion the shut
down signals will hold the clocks LOW without generating a runt pulse on
the outputs. The shut down pins provide a means of powering down
certain portions of a system or a means of disabling outputs when the full
compliment are not required for a specific design. The shut down pins will
disable the outputs when driven LOW. A common shut down pin is
provided to disable all of the outputs (except the feedback output) with a
single control signal.

Two feedback select pins are provided to select the multiplication factor of the PLL. The MPC932 provides six multiplication
factors: x1, x1.25, x1.5, x2, x2.5 and x3. In the x1.25 and x2.5 modes, the QFB output will not provide a 50% duty cycle. The
phase detector of the MPC932 only monitors rising edges of its feedback signals, thus for this function a 50% duty cycle is not
required. As the QFB signal can also be used to drive other clocks in a system it is important the user understand that the duty
cycle will not be 50%. In the x1 and x1.5 modes the QFB output will produce 50% duty cycle signals.

The MPC932 provides two pins for use in system test and debug operations. The MR

/OE input will force all of the outputs into
a high impedance state to allow for back driving the outputs during system test. In addition the PLL_EN pin allows the user to
bypass the PLL and drive the outputs directly through the Ref_CLK input. Note the Ref_CLK signal will be routed through the
dividers so that it will take several transitions on the Ref_CLK input to create a transition on the outputs.

The MPC932 is fully 3.3V compatible and requires no external loop filter components. All of the inputs are LVCMOS/LVTTL
compatible and the outputs produce rail–to–rail 3.3V swings. For series terminated applications each output can drive two series
terminated 50Ω transmission lines. For parallel terminated lines the device can drive terminations of 50Ω into VCC/2. The device
is packaged in a 32–lead TQFP package to provide the optimum combination of performance, board density and cost.

This document contains information on a new product. Specifications and information herein are subject to
change without notice.

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LOW VOLTAGE

PLL CLOCK DRIVER

FA SUFFIX

TQFP PACKAGE

CASE 873A-02

MPC932

MOTOROLA TIMING SOLUTIONS

BR1333 — REV 5

2

FUNCTION TABLES

SDn, COM_SD Qn

0
1

Held LOW
Enabled

PLL_En PLL Status

0
1

Test Mode
PLL Enabled

Q1

VCCO

Q0

GNDO

MODE

VCCA

GND_QFB
QFB
VCCO_QFB
FB_In

GNDA

GNDOQ2VCCOQ3GNDOQ4VCCO

Q5

VCCI

REF_CLK

PLL_EN

FBSEL0

FBSEL1

COM_SD

GNDI

25
26
27
28
29
30
31
32

15
14
13
12
11
10

9

12345678

24 23 22 21 20 19 18 17

16

MPC932

Pinout: 32-Lead TQFP Package (Top View)

LOGIC DIAGRAM

MR/OE PLL Status

0
1

Disabled
Enabled

STOP

STOP

SD0:1

Q0

Q1

STOP

STOP

SD2

Q2

Q3

SD3

STOP

STOP

SD4

Q4

Q5

SD5

QFB

FBSEL0
FBSEL1

÷

4

÷

5

÷

6

PLL

200–480MHz

REF_CLK

FB_In

PLL_EN

MR/OE

COM_SD

MR/OE

MODE

0
0
0
0
1
1
1
1

FBSEL1

0
0
1
1
0
0
1
1

FBSEL0

0
1
0
1
0
1
0
1

Qn

VCO/4
VCO/4
VCO/4

NA
VCO/4
VCO/4
VCO/4

NA

QFB

VCO/8
VCO/10
VCO/12

NA
VCO/4
VCO/5
VCO/6

NA

÷

4

MODE

÷

2

SD3
SD4
SD5

SD2

SD0:1

MPC932

TIMING SOLUTIONS
BR1333 — REV 5

3 MOTOROLA

Figure 1. Timing Diagram

Qn

SDn

ABSOLUTE MAXIMUM RATINGS*

Symbol Parameter Min Max Unit

V

CC

Supply Voltage –0.3 4.6 V

V

I

Input Voltage –0.3 VDD + 0.3 V

I

IN

Input Current ±20 mA

T

Stor

Storage Temperature Range –40 125 °C

* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or

conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not
implied.

PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70°C)

Symbol Characteristic Min Max Unit Condition

tr, t

f

TCLK Input Rise/Falls 3.0 ns

f

ref

Reference Input Frequency Note 1. Note 1. MHz

f

refDC

Reference Input Duty Cycle 25 75 %

1. Maximum and Maximum input reference frequency is limited by the VCO lock range and the feedback divider .

DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)

Symbol Characteristic Min Typ Max Unit Condition

V

IH

Input HIGH Voltage 2.0 3.6 V

V

IL

Input LOW Voltage 0.8 V

V

OH

Output HIGH Voltage 2.4 V IOH = –20mA (Note 2.)

V

OL

Output LOW Voltage 0.5 V IOL = 20mA (Note 2.)

I

IN

Input Current ±120 µA Note 3.

I

CC

Maximum Core Supply Current 100 mA

I

CCPLL

Maximum PLL Supply Current 15 20 mA

C

IN

4 pF

C

pd

25 pF Per Output

2. The MPC932 outputs can drive series or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge (see Applications
Info section).

3. Inputs have pull–up/pull–down resistors which affect input current.