Page 1
MPC860 Overview
Memory Map
Hardware Interface Overview
PowerPC Core Overview
PowerPC Core Register Set
MPC860 Instruction Set
PowerPC Exceptions
Instruction and Data Caches
Memory Management Unit
Instruction Execution Timing
System Interface Unit
Reset
External Signals
MPC860 External Bus Interface
Clocks and Power Control
Memory Controller
PCMCIA Interface
Communications Processor Module and CPM Timers
Communications Processor
SDMA Channels and IDMA Emulation
Serial Interface
SCC Introduction
SCC UART Mode
SCC HDLC Mode
SCC AppleTalk Mode
SCC Asynchronous HDLC Mode and IrDA
SCC BISYNC Mode
SCC Ethernet Mode
SCC Transparent Mode
Serial Management Controller
Serial Peripheral Interface
2
I C Controller
Parallel Interface Port
Parallel I/O Port
CPM Interrupt Controller
Digital Signal Processing
System Development and Debugging
IEEE 1149.1 Test Access Port
Byte Ordering
Serial Communciation Performance
Register Quick Reference Guide
MPC860 Instruction Set
Glossary
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
A
B
C
D
GLO
IND
Page 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
A
B
C
D
GLO
IND
MPC860 Overview
Memory Map
Hardware Interface Overview
PowerPC Core Overview
PowerPC Core Register Set
MPC860 Instruction Set
PowerPC Exceptions
Instruction and Data Caches
Memory Management Unit
Instruction Execution Timing
System Interface Unit
Reset
External Signals
MPC860 External Bus Interface
Clocks and Power Control
Memory Controller
PCMCIA Interface
Communications Processor Module and CPM Timers
Communications Processor
SDMA Channels and IDMA Emulation
Serial Interface
SCC Introduction
SCC UART Mode
SCC HDLC Mode
SCC AppleTalk Mode
SCC Asynchronous HDLC Mode and IrDA
SCC BISYNC Mode
SCC Ethernet Mode
SCC Transparent Mode
Serial Management Controller
Serial Peripheral Interface
2
I C Controller
Parallel Interface Port
Parallel I/O Port
CPM Interrupt Controller
Digital Signal Processing
System Development and Debugging
IEEE 1149.1 Test Access Port
Byte Ordering
Serial Communciation Performance
Register Quick Reference Guide
MPC860 Instruction Set
Glossary
Index
Page 3
MPC860UM/AD
07/98
REV. 1
MPC860 PowerQUICCª
UserÕs Manual
Page 4
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without
notice. Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no
express or implied copyright licenses granted hereunder to design or fabricate PowerPC integrated circuits or integrated circuits based on the information
in this document.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product
or circuit, and speciÞcally disclaims any and all liability, including without limitation consequential or incidental damages. ÒTypicalÓ parameters can and do
vary in different applications. All operating parameters, including ÒTypicalsÓ must be validated for each customer application by customerÕs technical
experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized
for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other
application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use
Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its ofÞcers, employees, subsidiaries,
afÞliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent
regarding the design or manufacture of the part.
Motorola and are registered trademarks and QUICC and PowerQUICC are trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/
AfÞrmative Action Employer.
The PowerPC name, the PowerPC logotype, PowerPC 601, PowerPC 603, PowerPC 603e, PowerPC 604, and RS/6000 are trademarks of International
Business Machines Corporation used by Motorola under license from International Business Machines Corporation.
I2C is a registered trademark of Phillips Corporation.
© Motorola Inc. 1998. All rights reserved.
Portions hereof © International Business Machines Corp. 1991Ð1998. All rights reserved.
Page 5
CONTENTS
Paragraph
Number
Title
Page
Number
About This Book
Before Using this Manual ...................................................................................lxiii
Audience..............................................................................................................lxiii
Organization ........................................................................................................ lxiv
Suggested Reading ............................................................................................lxviii
MPC8xx Documentation.................................................................................. lxviii
PowerPC Documentation ................................................................................. lxviii
Conventions......................................................................................................... lxix
Acronyms and Abbreviations............................................................................... lxx
PowerPC Architecture Terminology Conventions............................................lxxiii
Intended Audience.............................................................................................. lxxv
Contents.............................................................................................................. lxxv
Conventions........................................................................................................ lxxv
Acronyms and Abbreviations............................................................................ lxxvi
Chapter 1
MPC860 Overview
1.1 Features ................................................................................................................1-1
1.2 Architecture Overview ......................................................................................... 1-5
1.3 Embedded PowerPC Core....................................................................................1-6
1.4 System Interface Unit (SIU)................................................................................. 1-7
1.5 PCMCIA Controller ............................................................................................. 1-7
1.6 Power Management.............................................................................................. 1-7
1.7 Communications Processor Module (CPM) ........................................................1-8
1.8 Software Compatibility Issues .............................................................................1-9
Chapter 2
Memory Map
Chapter 3
Hardware Interface Overview
3.1 System Bus Signals .............................................................................................. 3-3
3.2 System Bus Signals .............................................................................................. 3-3
MOTOROLA
Contents
v
Page 6
CONTENTS
Paragraph
Number
Title
Chapter 4
Page
Number
The PowerPC Core
4.1 PowerPC Architecture Overview .........................................................................4-1
4.1.1 Levels of the PowerPC Architecture ................................................................4-3
4.2 Features.................................................................................................................4-4
4.3 Basic Structure of the Core...................................................................................4-5
4.3.1 Instruction Flow................................................................................................4-6
4.3.2 Basic Instruction Pipeline.................................................................................4-7
4.3.3 Instruction Unit.................................................................................................4-7
4.3.3.1 Branch Operations........................................................................................4-7
4.3.3.2 Dispatching Instructions...............................................................................4-9
4.4 Register Set...........................................................................................................4-9
4.5 Execution Units ....................................................................................................4-9
4.5.1 Branch Processing Unit ..................................................................................4-10
4.5.2 Integer Unit.....................................................................................................4-10
4.5.3 Load/Store Unit ..............................................................................................4-10
4.5.3.1 Executing Load/Store Instructions .............................................................4-12
4.5.3.2 Serializing Load/Store Instructions ............................................................4-12
4.5.3.3 Store Accesses............................................................................................4-12
4.5.3.4 Nonspeculative Load Instructions ..............................................................4-12
4.5.3.5 Unaligned Accesses....................................................................................4-13
4.5.3.6 Atomic Update Primitives ..........................................................................4-13
4.6 The MPC860 and the PowerPC Architecture.....................................................4-14
Chapter 5
PowerPC Core Register Set
5.1 MPC860 Register Implementation .......................................................................5-1
5.1.1 PowerPC RegistersÑUser Registers................................................................5-2
5.1.1.1 PowerPC User-Level Register Bit Assignments ..........................................5-2
5.1.1.1.1 Condition Register (CR)...........................................................................5-2
5.1.1.1.2 Condition Register CR0 Field Definition.................................................5-3
5.1.1.1.3 XER..........................................................................................................5-3
5.1.1.1.4 Time Base Registers.................................................................................5-4
5.1.2 PowerPC RegistersÑSupervisor Registers......................................................5-4
5.1.2.1 DAR, DSISR, and BAR Operation ..............................................................5-5
5.1.2.2 Unsupported Registers .................................................................................5-6
5.1.2.3 PowerPC Supervisor-Level Register Bit Assignments ................................5-6
5.1.2.3.1 Machine State Register (MSR) ................................................................5-6
5.1.2.3.2 Processor Version Register ......................................................................5-8
5.1.3 MPC860-Specific SPRs....................................................................................5-8
vi
MPC860 PowerQUICC UserÕs Manual
MOTOROLA
Page 7
CONTENTS
Paragraph
Number
5.1.3.1 Accessing SPRs..........................................................................................5-11
5.2 Register Initialization at Reset ...........................................................................5-11
Title
Chapter 6
Page
Number
MPC860 Instruction Set
6.1 Operand Conventions...........................................................................................6-1
6.1.1 Data Organization in Memory and Data Transfers .......................................... 6-1
6.1.2 Aligned and Misaligned Accesses ...................................................................6-1
6.2 Instruction Set Summary......................................................................................6-2
6.2.1 Classes of Instructions......................................................................................6-3
6.2.1.1 Definition of Boundedly Undefined ............................................................6-4
6.2.1.2 Defined Instruction Class.............................................................................6-4
6.2.1.3 Illegal Instruction Class ...............................................................................6-4
6.2.1.4 Reserved Instruction Class...........................................................................6-5
6.2.2 Addressing Modes............................................................................................ 6-5
6.2.2.1 Memory Addressing..................................................................................... 6-5
6.2.2.2 Effective Address Calculation .....................................................................6-6
6.2.2.3 Synchronization ...........................................................................................6-6
6.2.2.3.1 Context Synchronization.......................................................................... 6-6
6.2.2.3.2 Execution Synchronization ...................................................................... 6-7
6.2.2.3.3 Instruction-Related Exceptions................................................................6-7
6.2.3 Instruction Set Overview..................................................................................6-7
6.2.4 PowerPC UISA Instructions ............................................................................6-8
6.2.4.1 Integer Instructions ......................................................................................6-8
6.2.4.1.1 Integer Arithmetic Instructions ................................................................ 6-8
6.2.4.1.2 Integer Compare Instructions................................................................... 6-9
6.2.4.1.3 Integer Logical Instructions ...................................................................6-10
6.2.4.1.4 Integer Rotate and Shift Instructions .....................................................6-10
6.2.4.2 Load and Store Instructions .......................................................................6-11
6.2.4.2.1 Integer Load and Store Address Generation ..........................................6-11
6.2.4.2.2 Register Indirect Integer Load Instructions ...........................................6-12
6.2.4.2.3 Integer Store Instructions.......................................................................6-13
6.2.4.2.4 Integer Load and Store with Byte-Reverse Instructions ........................ 6-13
6.2.4.2.5 Integer Load and Store Multiple Instructions ........................................6-14
6.2.4.2.6 Integer Load and Store String Instructions ............................................6-14
6.2.4.3 Branch and Flow Control Instructions ....................................................... 6-15
6.2.4.3.1 Branch Instruction Address Calculation ................................................6-15
6.2.4.3.2 Branch Instructions ................................................................................ 6-16
6.2.4.3.3 Condition Register Logical Instructions ................................................ 6-16
6.2.4.4 Trap Instructions ........................................................................................6-17
6.2.4.5 Processor Control Instructions ................................................................... 6-17
MOTOROLA
Contents
vii
Page 8
CONTENTS
Paragraph
Number
6.2.4.5.1 Move to/from Condition Register Instructions ......................................6-17
6.2.4.6 Memory Synchronization InstructionsÑUISA..........................................6-17
6.2.5 PowerPC VEA Instructions............................................................................6-19
6.2.5.1 Processor Control Instructions ...................................................................6-20
6.2.5.2 Memory Synchronization InstructionsÑVEA...........................................6-20
6.2.5.2.1 eieio Behavior ........................................................................................6-20
6.2.5.2.2 isync Behavior........................................................................................6-21
6.2.5.3 Memory Control InstructionsÑVEA.........................................................6-21
6.2.6 PowerPC OEA Instructions............................................................................6-22
6.2.6.1 System Linkage Instructions ......................................................................6-22
6.2.6.2 Processor Control InstructionsÑOEA .......................................................6-22
6.2.6.2.1 Move to/from Machine State Register Instructions ...............................6-22
6.2.6.2.2 Move to/from Special-Purpose Register Instructions ............................6-23
6.2.6.3 Memory Control InstructionsÑOEA.........................................................6-23
6.2.6.3.1 Supervisor-Level Cache Management Instruction .................................6-23
6.2.6.3.2 Translation Lookaside Buffer Management Instructions.......................6-23
6.2.7 Recommended Simplified Mnemonics ..........................................................6-24
Title
Chapter 7
Page
Number
Exceptions
7.1 Exceptions ............................................................................................................7-2
7.1.1 Exception Ordering ..........................................................................................7-3
7.1.2 PowerPC-Defined Exceptions ..........................................................................7-4
7.1.2.1 System Reset Interrupt (0x00100)................................................................7-5
7.1.2.2 Machine Check Interrupt (0x00200) ............................................................7-5
7.1.2.3 DSI Exception (0x00300).............................................................................7-6
7.1.2.4 ISI Exception (0x00400) ..............................................................................7-6
7.1.2.5 External Interrupt Exception (0x00500).......................................................7-6
7.1.2.6 Alignment Exception (0x00600) ..................................................................7-7
7.1.2.6.1 Integer Alignment Exceptions..................................................................7-8
7.1.2.7 Program Exception (0x00700) .....................................................................7-9
7.1.2.8 Decrementer Exception (0x00900) ............................................................7-10
7.1.2.9 System Call Exception (0x00C00) .............................................................7-10
7.1.2.10 Trace Exception (0x00D00) .......................................................................7-11
7.1.2.11 Floating-Point Assist Exception .................................................................7-12
7.1.3 Implementation-Specific Exceptions..............................................................7-12
7.1.3.1 Software Emulation Exception (0x01000) .................................................7-12
7.1.3.2 Instruction TLB Miss Exception (0x01100) ..............................................7-12
7.1.3.3 Data TLB Miss Exception (0x01200) ........................................................7-13
7.1.3.4 Instruction TLB Error Exception (0x01300)..............................................7-13
7.1.3.5 Data TLB Error Exception (0x014000)......................................................7-14
viii
MPC860 PowerQUICC UserÕs Manual
MOTOROLA
Page 9
CONTENTS
Paragraph
Number
7.1.3.6 Debug Exceptions (0x01C00Ð0x01F00).................................................... 7-15
7.1.4 Implementing the Precise Exception Model ..................................................7-16
7.1.5 Recoverability after an Exception..................................................................7-17
7.1.6 Exception Latency.......................................................................................... 7-18
7.1.7 Partially Completed Instructions.................................................................... 7-19
Title
Chapter 8
Page
Number
Instruction and Data Caches
8.1 Instruction Cache Organization............................................................................ 8-2
8.2 Data Cache Organization .....................................................................................8-5
8.3 Cache Control Registers....................................................................................... 8-6
8.3.1 Instruction Cache Control Registers ................................................................8-6
8.3.1.1 Reading Data and Tags within the Instruction Cache..................................8-8
8.3.1.2 IC_CST Commands ..................................................................................... 8-9
8.3.1.2.1 Instruction Cache Enable/Disable Commands.........................................8-9
8.3.1.2.2 Instruction Cache Load & Lock Cache Block Command......................8-10
8.3.1.2.3 Instruction Cache Unlock Cache Block Command ...............................8-11
8.3.1.2.4 Instruction Cache Unlock All Command............................................... 8-11
8.3.1.2.5 Instruction Cache Invalidate All Command...........................................8-11
8.3.2 Data Cache Control Registers ........................................................................ 8-11
8.3.2.1 Reading Data Cache Tags and Copyback Buffer.......................................8-14
8.3.2.2 DC_CST Commands..................................................................................8-15
8.3.2.2.1 Data Cache Enable/Disable Commands ................................................8-16
8.3.2.2.2 Data Cache Load & Lock Cache Block Command ...............................8-16
8.3.2.2.3 Data Cache Unlock Cache Block Command ......................................... 8-17
8.3.2.2.4 Data Cache Unlock All Command ........................................................8-17
8.3.2.2.5 Data Cache Invalidate All Command ....................................................8-17
8.3.2.2.6 Data Cache Flush Cache Block Command............................................8-17
8.4 PowerPC Cache Control Instructions................................................................. 8-18
icbi
8.4.1 Instruction Cache Block Invalidate (
dcbt
8.4.2 Data Cache Block Touch (
dcbtst
for Store (
8.4.3 Data Cache Block Zero (
8.4.4 Data Cache Block Store (
8.4.5 Data Cache Block Flush (
8.4.6 Data Cache Block Invalidate (
8.5 Instruction Cache Operations .............................................................................8-20
8.5.1 Instruction Cache Hit .....................................................................................8-22
8.5.2 Instruction Cache Miss................................................................................... 8-22
8.5.3 Instruction Fetching on a Predicted Path .......................................................8-23
8.5.4 Fetching Instructions from Caching-Inhibited Regions.................................8-23
) .......................................................................................8-18
) and Data Cache Block Touch
dcbz
) ......................................................................8-19
dcbst
) ....................................................................8-19
dcbf
)......................................................................8-20
dcbi
) ......................................................8-18
)............................................................... 8-20
MOTOROLA
Contents
ix
Page 10
CONTENTS
Paragraph
Number
8.5.5 Updating Code And Memory Region Attributes............................................8-24
8.6 Data Cache Operation.........................................................................................8-24
8.6.1 Data Cache Load Hit ......................................................................................8-25
8.6.2 Data Cache Read Miss....................................................................................8-25
8.6.3 Write-Through Mode......................................................................................8-26
8.6.3.1 Data Cache Store Hit in Write-Through Mode ..........................................8-26
8.6.3.2 Data Cache Store Miss in Write-Through Mode........................................8-26
8.6.4 Write-Back Mode ...........................................................................................8-26
8.6.4.1 Data Cache Store Hit in Write-Back Mode................................................8-26
8.6.4.2 Data Cache Store Miss in Write-Back Mode .............................................8-27
8.6.5 Data Accesses to Caching-Inhibited Memory Regions..................................8-27
8.6.6 Atomic Memory References...........................................................................8-28
8.7 Cache Initialization after Reset...........................................................................8-29
8.8 Debug Support....................................................................................................8-29
8.8.1 Instruction and Data Cache Operation in Debug Mode .................................8-29
8.8.2 Instruction and Data Cache Operation with a Software Monitor Debugger ..8-30
Title
Chapter 9
Page
Number
Memory Management Unit (MMU)
9.1 Features.................................................................................................................9-1
9.2 PowerPC Architecture Compliance......................................................................9-2
9.3 Address Translation..............................................................................................9-3
9.3.1 Translation Disabled.........................................................................................9-3
9.3.2 Translation Enabled..........................................................................................9-3
9.3.3 TLB Operation..................................................................................................9-5
9.4 Using Access Protection Groups ..........................................................................9-6
9.5 Protection Resolution Modes................................................................................9-7
9.6 Memory Attributes ...............................................................................................9-8
9.7 Translation Table Structure ..................................................................................9-9
9.7.1 Level-One Descriptor .....................................................................................9-13
9.7.2 Level-Two Descriptor ....................................................................................9-14
9.8 Programming Model...........................................................................................9-14
9.8.1 IMMU Control Register (MI_CTR)...............................................................9-16
9.8.2 DMMU Control Register (MD_CTR)............................................................9-17
9.8.3 IMMU/DMMU Effective Page Number Register (Mx_EPN) .......................9-18
9.8.4 IMMU Tablewalk Control Register (MI_TWC)............................................9-18
9.8.5 DMMU Tablewalk Control Register (MD_TWC).........................................9-19
9.8.6 IMMU Real Page Number Register (MI_RPN).............................................9-20
9.8.7 DMMU Real Page Number Register (MD_RPN)..........................................9-22
9.8.8 MMU Tablewalk Base Register (M_TWB) ...................................................9-23
9.8.9 MMU Current Address Space ID Register (M_CASID) ...............................9-23
x
MPC860 PowerQUICC UserÕs Manual
MOTOROLA
Page 11
CONTENTS
Paragraph
Number
9.8.10 MMU Access Protection Registers (MI_AP/MD_AP)..................................9-24
9.8.11 MMU Tablewalk Special Register (M_TW) .................................................9-24
9.8.12 MMU Debug Registers ..................................................................................9-25
9.8.12.1 IMMU CAM Entry Read Register (MI_CAM) .........................................9-25
9.8.12.2 IMMU RAM Entry Read Register 0 (MI_RAM0) ....................................9-26
9.8.12.3 IMMU RAM Entry Read Register 1 (MI_RAM1) ....................................9-27
9.8.12.4 DMMU CAM Entry Read Register (MD_CAM) ......................................9-28
9.8.12.5 DMMU RAM Entry Read Register 0 (MD_RAM0) .................................9-29
9.8.13 DMMU RAM Entry Read Register 1 (MD_RAM1) ..................................... 9-30
9.9 Memory Management Unit Exceptions .............................................................9-32
9.10 TLB Manipulation.............................................................................................. 9-32
9.10.1 TLB Reload....................................................................................................9-32
9.10.1.1 Translation Reload Examples ....................................................................9-33
9.10.2 Locking TLB Entries......................................................................................9-33
9.10.3 Loading Locked TLB Entries.........................................................................9-34
9.10.4 TLB Invalidation............................................................................................9-34
Title
Chapter 10
Page
Number
Instruction Execution Timing
10.1 Instruction Execution Timing Examples............................................................ 10-1
10.1.1 Data Cache Load with a Data Dependency....................................................10-1
10.1.2 Writeback Arbitration ....................................................................................10-2
10.1.3 Private Writeback Bus Load ..........................................................................10-3
10.1.4 Fastest External Load (Data Cache Miss)......................................................10-3
10.1.5 A Full Completion Queue .............................................................................. 10-4
10.1.6 Branch Instruction Handling ..........................................................................10-4
10.1.7 Branch Prediction........................................................................................... 10-5
10.2 Instruction Timing List.......................................................................................10-6
10.2.1 Load/Store Instruction Timing.......................................................................10-7
10.2.2 String Instruction Latency.............................................................................. 10-8
10.2.3 Accessing Off-Core SPRs ..............................................................................10-8
Chapter 11
System Interface Unit
11.1 Features ..............................................................................................................11-1
11.2 System Configuration and Protection ................................................................11-2
11.3 Multiplexing SIU Pins........................................................................................11-3
11.4 Programming the SIU.........................................................................................11-4
11.4.1 Internal Memory Map Register (IMMR) ....................................................... 11-4
11.4.2 SIU Module Configuration Register (SIUMCR) ........................................... 11-5
MOTOROLA
Contents
xi
Page 12
CONTENTS
Paragraph
Number
11.4.3 System Protection Control Register (SYPCR) ...............................................11-9
11.4.4 Transfer Error Status Register (TESR).........................................................11-10
11.4.5 Register Lock Mechanism............................................................................11-11
11.5 System Configuration.......................................................................................11-12
11.5.1 Interrupt Structure ........................................................................................11-12
11.5.2 Priority of Interrupt Sources.........................................................................11-14
11.5.3 SIU Interrupt Processing ..............................................................................11-15
11.5.3.1 Nonmaskable InterruptsÑIRQ0 and SWT ..............................................11-15
11.5.4 Programming the SIU Interrupt Controller ..................................................11-16
11.5.4.1 SIU Interrupt Pending Register (SIPEND) ..............................................11-16
11.5.4.2 SIU Interrupt Mask Register (SIMASK)..................................................11-17
11.5.4.3 SIU Interrupt Edge/Level Register (SIEL)...............................................11-18
11.5.4.4 SIU Interrupt Vector Register (SIVEC) ...................................................11-19
11.6 The Bus Monitor...............................................................................................11-20
11.7 The Software Watchdog Timer ........................................................................11-21
11.7.1 Software Service Register (SWSR)..............................................................11-22
11.8 The PowerPC Decrementer ..............................................................................11-23
11.8.1 Decrementer Register (DEC) .......................................................................11-23
11.9 The PowerPC Timebase ...................................................................................11-24
11.9.1 Timebase Register (TBU and TBL) .............................................................11-24
11.9.2 Timebase Reference Registers (TBREFA and TBREFB)............................11-25
11.9.3 Timebase Status and Control Register (TBSCR) .........................................11-26
11.10 The Real-Time Clock .......................................................................................11-27
11.10.1 Real-Time Clock Status and Control Register (RTCSC) .............................11-27
11.10.2 Real-Time Clock Register (RTC).................................................................11-28
11.10.3 Real-Time Clock Alarm Register (RTCAL) ................................................11-29
11.10.4 Real-Time Clock Alarm Seconds Register (RTSEC) ..................................11-29
11.11 The Periodic Interrupt Timer (PIT) ..................................................................11-30
11.11.1 Periodic Interrupt Status and Control Register (PISCR)..............................11-31
11.11.2 PIT Count Register (PITC)...........................................................................11-32
11.11.3 PIT Register (PITR) .....................................................................................11-33
11.12 General SIU Timers Operation.........................................................................11-33
11.12.1 Freeze Operation ..........................................................................................11-33
11.12.2 Low-Power Stop Operation..........................................................................11-34
Title
Page
Number
Chapter 12
Reset
12.1 Types of Reset ....................................................................................................12-1
12.1.1 Power-On Reset..............................................................................................12-2
12.1.2 External Hard Reset........................................................................................12-2
12.1.3 Internal Hard Reset.........................................................................................12-2
xii
MPC860 PowerQUICC UserÕs Manual
MOTOROLA
Page 13
CONTENTS
Paragraph
Number
12.1.3.1 PLL Loss of Lock ...................................................................................... 12-3
12.1.3.2 Software Watchdog Reset .......................................................................... 12-3
12.1.3.3 Checkstop Reset ......................................................................................... 12-3
12.1.4 Debug Port Hard or Soft Reset.......................................................................12-3
12.1.5 JTAG Reset .................................................................................................... 12-3
12.1.6 Power-On and Hard Reset Sequence .............................................................12-4
12.1.7 External Soft Reset......................................................................................... 12-4
12.1.8 Internal Soft Reset.......................................................................................... 12-4
12.1.9 Soft Reset Sequence.......................................................................................12-5
12.2 Reset Status Register (RSR)............................................................................... 12-5
12.3 MPC860 Reset Configuration ............................................................................ 12-6
12.3.1 Hard Reset......................................................................................................12-6
12.3.1.1 Hard Reset Configuration Word ................................................................12-9
12.3.2 Soft Reset .....................................................................................................12-11
Title
Chapter 13
Page
Number
External Signals
13.1 System Bus Signals ............................................................................................ 13-5
13.2 Active Pull-Up Buffers.....................................................................................13-21
13.3 Internal Pull-Up and Pull-Down Resistors...................................................... 13-22
13.4 Recommended Basic Pin Connections............................................................. 13-22
13.4.1 Reset Configuration .....................................................................................13-23
13.4.1.1 Bus Control Signals and Interrupts ..........................................................13-23
13.4.2 JTAG and Debug Ports ................................................................................13-23
13.4.3 Unused Inputs...............................................................................................13-24
13.4.4 Unused Outputs............................................................................................13-24
13.5 Signal States during Hardware Reset ...............................................................13-24
Chapter 14
MPC860 External Bus Interface
14.1 Features ..............................................................................................................14-1
14.2 Bus Transfer Overview ......................................................................................14-1
14.3 Bus Interface Signal Descriptions ......................................................................14-2
14.4 Bus Operations ................................................................................................... 14-6
14.4.1 Basic Transfer Protocol.................................................................................. 14-6
14.4.2 Single-Beat Transfer ......................................................................................14-7
14.4.2.1 Single-Beat Read Flow ..............................................................................14-7
14.4.2.2 Single-Beat Write Flow ............................................................................. 14-9
14.4.3 Burst Transfers .............................................................................................14-13
14.4.4 Burst Operations...........................................................................................14-14
MOTOROLA
Contents
xiii
Page 14
CONTENTS
Paragraph
Number
14.4.5 Alignment and Data Packing on Transfers...................................................14-23
14.4.6 Arbitration Phase ..........................................................................................14-25
14.4.6.1 Bus Request ..............................................................................................14-26
14.4.6.2 Bus Grant..................................................................................................14-26
14.4.6.3 Bus Busy...................................................................................................14-27
14.4.6.4 External Bus Parking................................................................................14-29
14.4.7 Address Transfer Phase-Related Signals......................................................14-29
14.4.7.1 Transfer Start ............................................................................................14-29
14.4.7.2 Address Bus..............................................................................................14-30
14.4.7.3 Transfer Attributes ...................................................................................14-30
14.4.7.3.1 Read/Write ...........................................................................................14-30
14.4.7.3.2 Burst Indicator ......................................................................................14-30
14.4.7.3.3 Transfer Size ........................................................................................14-30
14.4.7.3.4 Address Types ......................................................................................14-30
14.4.7.3.5 Burst Data in Progress (BDIP) .............................................................14-33
14.4.8 Termination Signals......................................................................................14-33
14.4.8.1 Transfer Acknowledge (TA) ....................................................................14-33
14.4.8.2 Burst Inhibit (BI) ......................................................................................14-33
14.4.8.3 Transfer Error Acknowledge (TEA) ........................................................14-33
14.4.8.4 Termination Signals Protocol ...................................................................14-33
14.4.9 Memory Reservation ....................................................................................14-34
14.4.9.1 Cancel Reservation (CR) ..........................................................................14-35
14.4.9.2 Kill Reservation (KR) ..............................................................................14-36
14.4.10 Bus Exception Control Cycles......................................................................14-37
14.4.10.1 RETRY .....................................................................................................14-38
Title
Page
Number
Chapter 15
Clocks and Power Control
15.1 Features...............................................................................................................15-1
15.2 The Clock Module..............................................................................................15-3
15.2.1 External Reference Clocks .............................................................................15-3
15.2.1.1 Off-Chip Oscillator Input (EXTCLK)........................................................15-4
15.2.1.2 Crystal Oscillator Support (EXTAL and XTAL) .......................................15-4
15.2.2 System PLL ....................................................................................................15-5
15.2.2.1 SPLL Reset Configuration .........................................................................15-6
15.2.2.2 SPLL Output Characteristics and Stability ................................................15-7
15.2.2.3 The System Phase-Locked Loop Pins (VDDSYN, VSSSYN,
VSSSYN1, XFC) ...................................................................................15-8
15.2.2.4 Disabling the SPLL ....................................................................................15-9
15.3 Clock Signals......................................................................................................15-9
15.3.1 Clocks Derived from the SPLL Output ..........................................................15-9
xiv
MPC860 PowerQUICC UserÕs Manual
MOTOROLA
Page 15
CONTENTS
Paragraph
Number
15.3.1.1 The Internal General System Clocks (GCLK1C, GCLK2C,
GCLK1, GCLK2) ................................................................................15-10
15.3.1.2 Memory Controller and External Bus Clocks (GCLK1_50,
GCLK2_50, CLKOUT) ....................................................................... 15-11
15.3.1.3 CLKOUT Special Considerations: 1:2:1 Mode .......................................15-14
15.3.1.4 The Baud Rate Generator Clock (BRGCLK) ..........................................15-14
15.3.1.5 The Synchronization Clock (SYNCCLK, SYNCCLKS) ........................ 15-14
15.3.2 The PIT and RTC Clock (PITRTCLK)........................................................ 15-15
15.3.3 The Time Base and Decrementer Clock (TMBCLK) .................................. 15-16
15.4 Power Distribution ...........................................................................................15-16
15.4.1 I/O Buffer Power (VDDH)...........................................................................15-17
15.4.2 Internal Logic Power (VDDL) .....................................................................15-18
15.4.3 Clock Synthesizer Power (VDDSYN, VSSSYN, VSSYN1).......................15-18
15.4.4 Keep-Alive Power (KAPWR)...................................................................... 15-18
15.5 Power Control (Low-Power Modes) ................................................................15-18
15.5.1 Normal High Mode ......................................................................................15-21
15.5.2 Normal Low Mode.......................................................................................15-21
15.5.3 Doze High Mode ..........................................................................................15-21
15.5.4 Doze Low Mode........................................................................................... 15-22
15.5.5 Sleep Mode...................................................................................................15-23
15.5.6 Deep-Sleep Mode......................................................................................... 15-23
15.5.7 Power-Down Mode ...................................................................................... 15-24
15.5.7.1 Software Initiation of Power-Down Mode, with Automatic Wake-up .... 15-24
15.5.7.2 Maintaining the Real-Time Clock (RTC) During Shutdown or
Power Failure ....................................................................................... 15-25
15.5.7.3 Register Lock Mechanism: Protecting SIU Registers in
Power-Down Mode..............................................................................15-26
15.5.8 TMIST: Facilitating Nesting of SIU Timer Interrupts.................................15-26
15.6 Clock and Power Control Registers .................................................................15-27
15.6.1 System Clock and Reset Control Register ...................................................15-27
15.6.2 PLL, Low-Power, and Reset Control Register (PLPRCR) ..........................15-29
Title
Page
Number
Chapter 16
Memory Controller
16.1 Features ..............................................................................................................16-1
16.2 Basic Architecture ..............................................................................................16-4
16.3 Chip-Select Programming Common to the GPCM and UPM ...........................16-6
16.3.1 Address Space Programming ......................................................................... 16-7
16.3.2 Register Programming Order ......................................................................... 16-7
16.3.3 Memory Bank Write Protection .....................................................................16-7
16.3.4 Address Type Protection ................................................................................16-7
MOTOROLA
Contents
xv
Page 16
CONTENTS
Paragraph
Number
Title
Page
Number
16.3.5 8-, 16-, and 32Bit Port Size Configuration.....................................................16-7
16.3.6 Parity Configuration .......................................................................................16-8
16.3.7 Memory Bank Protection Status.....................................................................16-8
16.3.8 UPM-Specific Registers .................................................................................16-8
16.3.9 GPCM-Specific Registers ..............................................................................16-8
16.4 Register Descriptions..........................................................................................16-8
16.4.1 Base Registers (BRx) .....................................................................................16-8
16.4.2 Option Registers (ORx)................................................................................16-10
16.4.3 Memory Status Register (MSTAT) ..............................................................16-13
16.4.4 Machine A Mode Register/Machine B Mode Registers (MxMR) ...............16-13
16.4.5 Memory Command Register (MCR)............................................................16-15
16.4.6 Memory Data Register (MDR).....................................................................16-16
16.4.7 Memory Address Register (MAR) ...............................................................16-17
16.4.8 Memory Periodic Timer Prescaler Register (MPTPR) ................................16-17
16.5 General-Purpose Chip-Select Machine (GPCM) .............................................16-18
16.5.1 Timing Configuration...................................................................................16-18
16.5.1.1 Chip-Select Assertion Timing ..................................................................16-19
16.5.1.2 Chip-Select and Write Enable Deassertion Timing .................................16-20
16.5.1.3 Relaxed Timing ........................................................................................16-22
16.5.1.4 Output Enable (OE) Timing .....................................................................16-25
16.5.1.5 Programmable Wait State Configuration .................................................16-25
16.5.1.6 Extended Hold Time on Read Accesses...................................................16-25
16.5.2 Boot Chip-Select Operation .........................................................................16-27
16.5.3 External Asynchronous Master Support.......................................................16-28
16.5.4 Special Case: Bursting with External Transfer Acknowledge: ....................16-29
16.6 User-Programmable Machines (UPMs) ...........................................................16-30
16.6.1 Requests........................................................................................................16-31
16.6.1.1 Internal/External Memory Access Requests ............................................16-31
16.6.1.2 UPM Periodic Timer Requests .................................................................16-32
16.6.1.3 Software RequestsÑMCR run Command ...............................................16-32
16.6.1.4 Exception Requests ..................................................................................16-32
16.6.2 Programming the UPM.................................................................................16-33
16.6.3 Clock Timing................................................................................................16-33
16.6.4 The RAM Array ...........................................................................................16-35
16.6.4.1 RAM Words .............................................................................................16-36
16.6.4.2 Chip-Select Signals (CxTx)......................................................................16-39
16.6.4.3 Byte-Select Signals (BxTx) ......................................................................16-39
16.6.4.4 General-Purpose Signals (GxTx, GOx)....................................................16-40
16.6.4.5 Loop Control (LOOP) ..............................................................................16-42
16.6.4.6 Exception Pattern Entry (EXEN) .............................................................16-43
16.6.4.7 Address Multiplexing (AMX) ..................................................................16-43
16.6.4.8 Transfer Acknowledge and Data Sample Control (UTA, DLT3) ............16-47
16.6.4.9 Disable Timer Mechanism (TODT) .........................................................16-48
xvi
MPC860 PowerQUICC UserÕs Manual
MOTOROLA
Page 17
CONTENTS
Paragraph
Number
16.6.4.10 The Last Word (LAST) ............................................................................16-48
16.6.4.11 The Wait Mechanism (WAEN) ...............................................................16-48
16.6.4.11.1 Internal and External Synchronous Masters ........................................16-48
16.6.4.11.2 External Asynchronous Masters ..........................................................16-49
16.7 Handling Devices with Slow or Variable Access Times .................................16-50
16.7.1 Hierarchical Bus Interface Example ............................................................16-51
16.7.2 Slow Devices Example ................................................................................16-51
16.8 External Master Support...................................................................................16-51
16.8.1 Synchronous External Masters..................................................................... 16-51
16.8.2 Asynchronous External Masters ..................................................................16-52
16.8.3 Special Case: Address Type Signals for External Masters .......................... 16-52
16.8.4 UPM Features Supporting External Masters................................................16-52
16.8.4.1 Address Incrementing for External Synchronous Bursting Masters........16-52
16.8.4.2 Handshake Mechanism for Asynchronous Bursting Masters ..................16-52
16.8.4.3 Special Signal for External Address Multiplexer Control .......................16-53
16.8.5 External Master Examples ...........................................................................16-53
16.8.5.1 External Masters and the GPCM ............................................................. 16-53
16.8.5.2 External Masters and the UPM ................................................................16-54
16.9 Memory System Interface Examples ...............................................................16-58
16.9.1 Page-Mode DRAM Interface Example........................................................16-59
16.9.2 Page Mode Extended Data-Out Interface Example .....................................16-70
Title
Chapter 17
Page
Number
PCMCIA Interface
17.1 System Configuration.........................................................................................17-1
17.2 PCMCIA Module Signal Definitions.................................................................17-1
17.2.1 PCMCIA Cycle Control Signals .................................................................... 17-3
17.2.2 PCMCIA Input Port Signals...........................................................................17-4
17.2.3 PCMCIA Output Port Signals (OP[0Ð4]) ......................................................17-5
17.2.4 Other PCMCIA Signals..................................................................................17-5
17.3 Operation Description ........................................................................................17-5
17.3.1 Memory-Only Cards ......................................................................................17-6
17.3.2 I/O Cards ........................................................................................................ 17-6
17.3.3 Interrupts ........................................................................................................17-6
17.3.4 Power Control ................................................................................................17-7
17.3.5 Reset and Three-State Control .......................................................................17-7
17.3.6 DMA ..............................................................................................................17-7
17.4 Programming Model ..........................................................................................17-8
17.4.1 PCMCIA Interface Input Pins Register (PIPR) .............................................17-8
17.4.2 PCMCIA Interface Status Changed Register (PSCR) ...................................17-9
17.4.3 PCMCIA Interface Enable Register (PER)..................................................17-10
MOTOROLA
Contents
xvii
Page 18
CONTENTS
Paragraph
Number
17.4.4 PCMCIA Interface General Control Register (PGCRx) ..............................17-12
17.4.5 PCMCIA Base Registers 0Ð7 (PBR0ÐPBR7) ..............................................17-12
17.4.6 PCMCIA Option Register 0Ð7 (POR0ÐPOR7) ............................................17-13
17.5 PCMCIA Controller Timing Examples............................................................17-16
Title
Chapter 18
Page
Number
Communications Processor Module and CPM Timers
18.1 Features...............................................................................................................18-1
18.2 CPM General-Purpose Timers............................................................................18-4
18.2.1 Features...........................................................................................................18-5
18.2.2 CPM Timer Operation....................................................................................18-5
18.2.2.1 Timer Clock Source....................................................................................18-6
18.2.2.2 Timer Reference Count ..............................................................................18-6
18.2.2.3 Timer Capture.............................................................................................18-6
18.2.2.4 Timer Gating ..............................................................................................18-6
18.2.2.5 Cascaded Mode ..........................................................................................18-7
18.2.3 CPM Timer Register Set ................................................................................18-8
18.2.3.1 Timer Global Configuration Register (TGCR) ..........................................18-8
18.2.3.2 Timer Mode Registers (TMR1ÐTMR4) .....................................................18-9
18.2.3.3 Timer Reference Registers (TRR1ÐTRR4) ..............................................18-10
18.2.3.4 Timer Capture Registers (TCR1ÐTCR4) .................................................18-10
18.2.3.5 Timer Counter Registers (TCN1ÐTCN4) .................................................18-10
18.2.3.6 Timer Event Registers (TER1ÐTER4) .....................................................18-11
18.2.4 Timer Initialization Examples ......................................................................18-12
Chapter 19
Communications Processor
19.1 Features...............................................................................................................19-1
19.2 Communicating with the Core............................................................................19-2
19.3 Communicating with the Peripherals .................................................................19-2
19.4 CP Microcode Revision Number........................................................................19-4
19.5 CP Register Set and CP Commands...................................................................19-4
19.5.1 RISC Controller Configuration Register (RCCR)..........................................19-4
19.5.2 CP Command Register (CPCR) .....................................................................19-6
19.5.3 CP Commands ................................................................................................19-7
19.5.3.1 CP Command Examples.............................................................................19-8
19.5.3.2 CP Command Execution Latency ..............................................................19-9
19.6 Dual-Port RAM ..................................................................................................19-9
19.6.1 System RAM and Microcode Packages .......................................................19-10
19.6.2 The Buffer Descriptor (BD) .........................................................................19-11
xviii
MPC860 PowerQUICC UserÕs Manual
MOTOROLA
Page 19
CONTENTS
Paragraph
Number
Title
Page
Number
19.6.3 Parameter RAM ...........................................................................................19-11
19.7 The RISC Timer Table.....................................................................................19-12
19.7.1 RISC Timer Table Scan Algorithm..............................................................19-12
19.7.2 The
SET TIMER
Command ............................................................................19-13
19.7.3 RISC Timer Table Parameter RAM and Timer Table Entries..................... 19-13
19.7.3.1 RISC Timer Command Register (TM_CMD) .........................................19-14
19.7.3.2 RISC Timer Table Entries........................................................................ 19-15
19.7.4 RISC Timer Event Register (RTER)/Mask Register (RTMR) ....................19-15
19.7.5 PWM Mode..................................................................................................19-15
19.7.6 RISC Timer Initialization............................................................................. 19-16
19.7.7 RISC Timer Interrupt Handling ...................................................................19-17
19.7.8 Using the RISC Timers to Track CP Loading .............................................19-17
Chapter 20
SDMA Channels and IDMA Emulation
20.1 SDMA Channels ................................................................................................20-1
20.1.1 SDMA Transfers ............................................................................................ 20-2
20.1.2 U-Bus Arbitration and the SDMA Channels .................................................20-2
20.2 SDMA Registers ............................................................................................... 20-3
20.2.1 SDMA Configuration Register (SDCR) ........................................................20-3
20.2.2 SDMA Status Register (SDSR) .....................................................................20-4
20.2.3 SDMA Mask Register (SDMR) .....................................................................20-5
20.2.4 SDMA Address Register (SDAR) .................................................................20-5
20.3 IDMA Emulation................................................................................................20-5
20.3.1 IDMA Features...............................................................................................20-6
20.3.2 IDMA Parameter RAM.................................................................................. 20-6
20.3.3 IDMA Registers .............................................................................................20-7
20.3.3.1 DMA Channel Mode Registers (DCMR) ..................................................20-7
20.3.3.2 IDMA Status Registers (IDSR1 and IDSR2).............................................20-8
20.3.3.3 IDMA Mask Registers (IDMR1 and IDMR2) ........................................... 20-9
20.3.4 IDMA Buffer Descriptors (BD) .....................................................................20-9
20.3.4.1 Function Code RegistersÑSFCR and DFCR ..........................................20-11
20.3.4.2 Auto-Buffering and Buffer-Chaining....................................................... 20-12
20.3.5 IDMA CP Commands ..................................................................................20-12
20.3.6 IDMA Channel Operation............................................................................ 20-12
20.3.6.1 Activating an IDMA Channel ..................................................................20-13
20.3.6.2 Suspending an IDMA Channel ................................................................20-13
20.3.7 IDMA Interface SignalsÑDREQ and SDACK...........................................20-13
20.3.7.1 IDMA Requests for Memory/Memory Transfers ....................................20-13
20.3.7.2 IDMA Requests for Peripheral/Memory Transfers ................................. 20-14
20.3.7.2.1 Level-Sensitive Requests .....................................................................20-14
MOTOROLA
Contents
xix
Page 20
CONTENTS
Paragraph
Number
20.3.7.2.2 Edge-Sensitive Requests ......................................................................20-14
20.3.8 IDMA TransfersÑDual-Address and Single-Address.................................20-15
20.3.8.1 Dual-Address (Dual-Cycle) Transfer .......................................................20-15
20.3.8.2 Single-Address (Single-Cycle) Transfer (Fly-By) ...................................20-15
20.3.9 Single-Buffer Mode on IDMA1ÑA Special Case.......................................20-18
20.3.9.1 IDMA1 Channel Mode Register (DCMR) (Single-Buffer Mode) ...........20-19
20.3.9.2 IDMA1 Status Register (IDSR1) (Single-Buffer Mode) .........................20-19
20.3.9.3 IDMA1 Mask Register (IDMR1) (Single-Buffer Mode) .........................20-20
20.3.9.4 Burst Timing (Single-Buffer Mode).........................................................20-20
20.3.10 External Recognition of an IDMA Transfer.................................................20-21
20.3.11 Interrupts During an IDMA Bus Transfer ....................................................20-22
Title
Chapter 21
Page
Number
Serial Interface
21.1 SI Features ..........................................................................................................21-3
21.2 The Time-Slot Assigner (TSA) ..........................................................................21-3
21.2.1 TSA Signals....................................................................................................21-7
21.2.2 Enabling Connections to the TSA ..................................................................21-8
21.2.3 SI RAM ..........................................................................................................21-8
21.2.3.1 Disabling and Reenabling the TSA ............................................................21-9
21.2.3.2 One TDM Channel with Static Frames ......................................................21-9
21.2.3.3 Two TDM Channels with Static Frames ..................................................21-10
21.2.3.4 SI RAM Dynamic Changes ......................................................................21-10
21.2.3.5 One TDM Channel with Dynamic Frames...............................................21-13
21.2.3.6 Two TDM Channels with Dynamic Frames ............................................21-13
21.2.3.7 Programming the SI RAM .......................................................................21-14
21.2.3.8 SI RAM Programming Example ..............................................................21-15
21.2.4 The SI Registers ...........................................................................................21-16
21.2.4.1 SI Global Mode Register (SIGMR)..........................................................21-16
21.2.4.2 SI Mode Register (SIMODE) ...................................................................21-17
21.2.4.3 SI Clock Route Register (SICR) ..............................................................21-23
21.2.4.4 SI Command Register (SICMR) ..............................................................21-24
21.2.4.5 SI Status Register (SISTR) .......................................................................21-25
21.2.4.6 SI RAM Pointer Register (SIRP) .............................................................21-26
21.2.5 IDL Bus Implementation..............................................................................21-28
21.2.5.1 ISDN Terminal Adaptor Application .......................................................21-28
21.2.5.2 Programming the IDL Interface ...............................................................21-31
21.2.6 GCI Bus Implementation..............................................................................21-32
21.2.6.1 GCI Activation/Deactivation....................................................................21-34
21.2.6.2 Programming the GCI Interface ...............................................................21-34
21.2.6.2.1 Normal Mode .......................................................................................21-34
xx
MPC860 PowerQUICC UserÕs Manual
MOTOROLA
Page 21
CONTENTS
Paragraph
Number
21.2.6.2.2 SCIT Mode........................................................................................... 21-34
21.2.6.3 GCI Interface (SCIT Mode) Programming Example...............................21-35
21.3 NMSI Configuration ........................................................................................21-36
21.4 Baud Rate Generators (BRGs) ......................................................................... 21-39
21.4.1 Baud Rate Generator Configuration Registers (BRGCn) ............................ 21-40
21.4.2 Autobaud Operation on a UART .................................................................21-41
21.4.3 UART Baud Rate Examples ........................................................................21-42
Title
Chapter 22
Page
Number
Serial Communications Controllers
22.1 Features ..............................................................................................................22-2
22.1.1 General SCC Mode Register (GSMR)...........................................................22-3
22.1.2 Protocol-Specific Mode Register (PSMR)................................................... 22-10
22.1.3 Data Synchronization Register (DSR) .........................................................22-10
22.1.4 Transmit-on-Demand Register (TODR) ......................................................22-10
22.2 SCC Buffer Descriptors (BDs)......................................................................... 22-11
22.3 SCC Parameter RAM.......................................................................................22-14
22.3.1 Function Code Registers (RFCR and TFCR)...............................................22-16
22.3.2 Handling SCC Interrupts.............................................................................. 22-16
22.3.3 Initializing the SCCs ....................................................................................22-17
22.3.4 Controlling SCC Timing with RTS, CTS, and CD......................................22-18
22.3.4.1 Synchronous Protocols.............................................................................22-18
22.3.4.2 Asynchronous Protocols .......................................................................... 22-21
22.3.5 Digital Phase-Locked Loop (DPLL) Operation...........................................22-22
22.3.5.1 Encoding Data with a DPLL .................................................................... 22-24
22.3.6 Clock Glitch Detection................................................................................. 22-25
22.3.7 Reconfiguring the SCCs............................................................................... 22-26
22.3.7.1 General Reconfiguration Sequence for an SCC Transmitter ...................22-26
22.3.7.2 Reset Sequence for an SCC Transmitter ..................................................22-27
22.3.7.3 General Reconfiguration Sequence for an SCC Receiver ....................... 22-27
22.3.7.4 Reset Sequence for an SCC Receiver ......................................................22-27
22.3.7.5 Switching Protocols .................................................................................22-27
22.3.8 Saving Power ...............................................................................................22-27
Chapter 23
SCC UART Mode
23.1 Features ..............................................................................................................23-2
23.2 Normal Asynchronous Mode .............................................................................23-3
23.3 Synchronous Mode.............................................................................................23-3
23.4 SCC UART Parameter RAM ............................................................................. 23-4
MOTOROLA
Contents
xxi
Page 22
CONTENTS
Paragraph
Number
23.5 Data-Handling Methods: Character- or Message-Based ....................................23-5
23.6 Error and Status Reporting .................................................................................23-6
23.7 SCC UART Commands .....................................................................................23-6
23.8 Multidrop Systems and Address Recognition ....................................................23-7
23.9 Receiving Control Characters.............................................................................23-7
23.10 Hunt Mode (Receiver) ........................................................................................23-9
23.11 Inserting Control Characters into the Transmit Data Stream .............................23-9
23.12 Sending a Break (Transmitter) .........................................................................23-10
23.13 Sending a Preamble (Transmitter)....................................................................23-10
23.14 Fractional Stop Bits (Transmitter)....................................................................23-11
23.15 Handling Errors in the SCC UART Controller ................................................23-12
23.16 UART Mode Register (PSMR) ........................................................................23-13
23.17 SCC UART Receive Buffer Descriptor (RxBD)..............................................23-15
23.18 SCC UART Transmit Buffer Descriptor (TxBD) ............................................23-18
23.19 SCC UART Event Register (SCCE) and Mask Register (SCCM)...................23-19
23.20 SCC UART Status Register (SCCS) ................................................................23-21
23.21 SCC UART Programming Example.................................................................23-22
23.22 S-Records Loader Application .........................................................................23-23
Title
Chapter 24
Page
Number
SCC HDLC Mode
24.1 SCC HDLC Features ..........................................................................................24-2
24.2 SCC HDLC Channel Frame Transmission.........................................................24-2
24.3 SCC HDLC Channel Frame Reception ..............................................................24-3
24.4 SCC HDLC Parameter RAM .............................................................................24-3
24.5 Programming the SCC in HDLC Mode .............................................................24-5
24.6 SCC HDLC Commands .....................................................................................24-5
24.7 Handling Errors in the SCC HDLC Controller ..................................................24-6
24.8 HDLC Mode Register (PSMR) ..........................................................................24-7
24.9 SCC HDLC Receive Buffer Descriptor (RxBD)................................................24-8
24.10 SCC HDLC Transmit Buffer Descriptor (TxBD) ............................................24-11
24.11 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) ......................24-12
24.12 SCC HDLC Status Register (SCCS) ................................................................24-14
24.13 SCC HDLC Programming Examples...............................................................24-14
24.13.1 SCC HDLC Programming Example #1 .......................................................24-15
24.13.2 SCC HDLC Programming Example #2 .......................................................24-16
24.14 HDLC Bus Mode with Collision Detection .....................................................24-16
24.14.1 HDLC Bus Features .....................................................................................24-19
24.14.2 Accessing the HDLC Bus.............................................................................24-19
24.14.3 Increasing Performance ................................................................................24-20
24.14.4 Delayed RTS Mode ......................................................................................24-21
xxii
MPC860 PowerQUICC UserÕs Manual
MOTOROLA
Page 23
CONTENTS
Paragraph
Number
24.14.5 Using the Time-Slot Assigner (TSA)........................................................... 24-22
24.14.6 HDLC Bus Protocol Programming .............................................................. 24-23
24.14.6.1 Programming GSMR and PSMR for the HDLC Bus Protocol................24-23
24.14.6.2 HDLC Bus Controller Programming Example ........................................ 24-23
Title
Chapter 25
Page
Number
SCC AppleTalk Mode
25.1 Operating the LocalTalk Bus .............................................................................25-1
25.2 Features ..............................................................................................................25-2
25.3 Connecting to AppleTalk ...................................................................................25-3
25.4 Programming the SCC in AppleTalk Mode.......................................................25-3
25.4.1 Programming the GSMR................................................................................25-3
25.4.2 Programming the PSMR ................................................................................25-4
25.4.3 Programming the TODR ................................................................................25-4
25.4.4 SCC AppleTalk Programming Example........................................................25-4
Chapter 26
SCC Asynchronous HDLC Mode and IrDA
26.1 Asynchronous HDLC Features ..........................................................................26-1
26.2 Asynchronous HDLC Frame Transmission Processing..................................... 26-2
26.3 Asynchronous HDLC Frame Reception Processing .......................................... 26-2
26.4 Transmitter Transparency Encoding .................................................................. 26-3
26.5 Receiver Transparency Decoding ......................................................................26-3
26.6 Exceptions to RFC 1549 ....................................................................................26-4
26.7 Asynchronous HDLC Channel Implementation ................................................26-5
26.8 Asynchronous HDLC Mode Parameter RAM ...................................................26-5
26.9 Configuring GSMR and DSR for Asynchronous HDLC................................... 26-6
26.9.1 General SCC Mode Register (GSMR)...........................................................26-6
26.9.2 Data Synchronization Register (DSR) ...........................................................26-7
26.10 Programming the Asynchronous HDLC Controller...........................................26-7
26.11 Asynchronous HDLC Commands...................................................................... 26-7
26.12 Handling Errors in the Asynchronous HDLC Controller...................................26-8
26.13 SCC Asynchronous HDLC Registers ................................................................26-9
26.13.1 Asynchronous HDLC Event Register (SCCE)/Asynchronous HDLC
Mask Register (SCCM).............................................................................. 26-9
26.13.2 SCC Asynchronous HDLC Status Register (SCCS).................................... 26-10
26.13.3 Asynchronous HDLC Mode Register (PSMR)............................................ 26-11
26.14 SCC Asynchronous HDLC RxBDs..................................................................26-11
26.15 SCC Asynchronous HDLC TxBDs.................................................................. 26-13
26.16 Differences between HDLC and Asynchronous HDLC ..................................26-14
MOTOROLA
Contents
xxiii
Page 24
CONTENTS
Paragraph
Number
26.17 SCC Asynchronous HDLC Programming Example ........................................26-14
26.18 IrDA Encoder/Decoder (SCC2 Only)...............................................................26-15
Title
Chapter 27
Page
Number
SCC BISYNC Mode
27.1 Features...............................................................................................................27-2
27.2 SCC BISYNC Channel Frame Transmission.....................................................27-2
27.3 SCC BISYNC Channel Frame Reception ..........................................................27-3
27.4 SCC BISYNC Parameter RAM..........................................................................27-4
27.5 SCC BISYNC Commands..................................................................................27-5
27.6 SCC BISYNC Control Character Recognition...................................................27-6
27.7 BISYNC SYNC Register (BSYNC)...................................................................27-7
27.8 SCC BISYNC DLE Register (BDLE)................................................................27-8
27.9 Sending and Receiving the Synchronization Sequence......................................27-9
27.10 Handling Errors in the SCC BISYNC ................................................................27-9
27.11 BISYNC Mode Register (PSMR).....................................................................27-10
27.12 SCC BISYNC Receive BD (RxBD).................................................................27-12
27.13 SCC BISYNC Transmit BD (TxBD) ...............................................................27-13
27.14 BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM) ..............27-15
27.15 SCC Status Registers (SCCS)...........................................................................27-16
27.16 Programming the SCC BISYNC Controller.....................................................27-17
27.17 SCC BISYNC Programming Example.............................................................27-18
Chapter 28
SCC Ethernet Mode
28.1 Ethernet on the MPC860 ....................................................................................28-2
28.2 Features...............................................................................................................28-3
28.3 Learning Ethernet on the MPC860.....................................................................28-4
28.4 Connecting the MPC860 to Ethernet..................................................................28-5
28.5 SCC Ethernet Channel Frame Transmission ......................................................28-6
28.6 SCC Ethernet Channel Frame Reception ...........................................................28-7
28.7 The Content-Addressable Memory (CAM) Interface ........................................28-8
28.7.1 Serial CAM Interface (SCC1 and SCC2 Only)..............................................28-9
28.7.2 Parallel CAM Interface.................................................................................28-10
28.8 SCC Ethernet Parameter RAM.........................................................................28-12
28.9 Programming the Ethernet Controller ..............................................................28-14
28.10 SCC Ethernet Commands.................................................................................28-14
28.11 SCC Ethernet Address Recognition .................................................................28-16
28.12 Hash Table Algorithm ......................................................................................28-17
28.13 Interpacket Gap Time .......................................................................................28-18
xxiv MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 25
CONTENTS
Paragraph
Number
28.14 Handling Collisions.......................................................................................... 28-18
28.15 Internal and External Loopback ....................................................................... 28-18
28.16 Full-Duplex Ethernet Support .......................................................................... 28-18
28.17 Handling Errors in the Ethernet Controller ......................................................28-19
28.18 Ethernet Mode Register (PSMR) .....................................................................28-19
28.19 SCC Ethernet Receive BD ...............................................................................28-21
28.20 SCC Ethernet Transmit Buffer Descriptor .......................................................28-23
28.21 SCC Ethernet Event Register (SCCE)/Mask Register (SCCM) ......................28-25
28.22 SCC Ethernet Programming Example..............................................................28-27
Title
Chapter 29
Page
Number
SCC Transparent Mode
29.1 Features ..............................................................................................................29-1
29.2 SCC Transparent Channel Frame Transmission Process...................................29-2
29.3 SCC Transparent Channel Frame Reception Process ........................................29-2
29.4 Achieving Synchronization in Transparent Mode .............................................29-3
29.4.1 Synchronization in NMSI Mode .................................................................... 29-3
29.4.1.1 In-Line Synchronization Pattern ................................................................29-3
29.4.1.2 External Synchronization Signals ..............................................................29-4
29.4.1.2.1 External Synchronization Example........................................................ 29-4
29.4.1.3 Transparent Mode without Explicit Synchronization ................................29-5
29.4.1.4 End of Frame Detection .............................................................................29-5
29.4.2 Synchronization and the TSA ........................................................................29-6
29.4.2.1 In-line Synchronization Pattern ................................................................. 29-6
29.4.2.2 Inherent Synchronization ...........................................................................29-6
29.5 CRC Calculation in Transparent Mode..............................................................29-6
29.6 SCC Transparent Parameter RAM.....................................................................29-6
29.7 SCC Transparent Commands.............................................................................29-7
29.8 Handling Errors in the Transparent Controller ..................................................29-8
29.9 Transparent Mode and the PSMR ...................................................................... 29-8
29.10 SCC Transparent Receive Buffer Descriptor (RxBD) ....................................... 29-9
29.11 SCC Transparent Transmit Buffer Descriptor (TxBD).................................... 29-10
29.12 SCC Transparent Event Register (SCCE)/Mask Register (SCCM)................. 29-12
29.13 SCC Status Register in Transparent Mode (SCCS) .........................................29-13
29.14 SCC2 Transparent Programming Example ......................................................29-13
MOTOROLA Contents xxv
Page 26
CONTENTS
Paragraph
Number
Title
Chapter 30
Page
Number
Serial Management Controllers
30.1 SMC Features .....................................................................................................30-2
30.2 Common SMC Settings and Configurations ......................................................30-3
30.2.1 SMC Mode Registers (SMCMRn) .................................................................30-3
30.2.2 SMC Buffer Descriptors (BDs) ......................................................................30-5
30.2.3 SMC Parameter RAM ....................................................................................30-5
30.2.3.1 SMC Function Code Registers (RFCR/TFCR) ..........................................30-7
30.2.4 Disabling SMCs On-the-Fly...........................................................................30-7
30.2.4.1 SMC Transmitter Full Sequence ................................................................30-8
30.2.4.2 SMC Transmitter Shortcut Sequence .........................................................30-8
30.2.4.3 SMC Receiver Full Sequence.....................................................................30-8
30.2.4.4 SMC Receiver Shortcut Sequence .............................................................30-8
30.2.4.5 Changing SMC Protocols ...........................................................................30-9
30.2.5 Saving Power..................................................................................................30-9
30.2.6 Handling Interrupts In the SMC .....................................................................30-9
30.3 SMC in UART Mode .........................................................................................30-9
30.3.1 SMC UART Features ...................................................................................30-10
30.3.2 SMC UART-Specific Parameter RAM ........................................................30-10
30.3.3 SMC UART Channel Transmission Process................................................30-11
30.3.4 SMC UART Channel Reception Process .....................................................30-11
30.3.5 Data Handling Modes: Character- and Message-Oriented...........................30-11
30.3.6 SMC UART Commands...............................................................................30-12
30.3.7 Sending a Break............................................................................................30-12
30.3.8 Sending a Preamble ......................................................................................30-13
30.3.9 Handling Errors in the SMC UART Controller ...........................................30-13
30.3.10 SMC UART Receive BD (RxBD) ...............................................................30-14
30.3.11 SMC UART Transmit BD (TxBD) ..............................................................30-16
30.3.12 SMC UART Event Register (SMCE)/Mask Register (SMCM)...................30-18
30.3.13 SMC UART Controller Programming Example ..........................................30-19
30.4 SMC in Transparent Mode ...............................................................................30-20
30.4.1 SMC Transparent Mode Features.................................................................30-21
30.4.2 SMC Transparent-Specific Parameter RAM................................................30-21
30.4.3 SMC Transparent Channel Transmission Process .......................................30-21
30.4.4 SMC Transparent Channel Reception Process.............................................30-22
30.4.5 Using SMSYN for Synchronization.............................................................30-22
30.4.6 Using TSA for Synchronization ...................................................................30-23
30.4.7 SMC Transparent Commands ......................................................................30-25
30.4.8 Handling Errors in the SMC Transparent Controller ...................................30-26
30.4.9 SMC Transparent Receive BD (RxBD) .......................................................30-26
30.4.10 SMC Transparent Transmit BD (TxBD)......................................................30-27
30.4.11 SMC Transparent Event Register (SMCE)/Mask Register (SMCM) ..........30-29
xxvi MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 27
CONTENTS
Paragraph
Number
30.4.12 SMC Transparent NMSI Programming Example ........................................30-30
30.4.13 SMC Transparent TSA Programming Example ..........................................30-31
30.5 SMC in GCI Mode ........................................................................................... 30-31
30.5.1 SMC GCI Parameter RAM .......................................................................... 30-32
30.5.2 Handling the GCI Monitor Channel............................................................. 30-32
30.5.2.1 SMC GCI Monitor Channel Transmission Process .................................30-32
30.5.2.1.1 SMC GCI Monitor Channel Reception Process ..................................30-33
30.5.3 Handling the GCI C/I Channel..................................................................... 30-33
30.5.3.1 SMC GCI C/I Channel Transmission Process .........................................30-33
30.5.3.2 SMC GCI C/I Channel Reception Process .............................................. 30-33
30.5.4 SMC GCI Commands ..................................................................................30-33
30.5.5 SMC GCI Monitor Channel RxBD.............................................................. 30-33
30.5.6 SMC GCI Monitor Channel TxBD ..............................................................30-34
30.5.7 SMC GCI C/I Channel RxBD...................................................................... 30-35
30.5.8 SMC GCI C/I Channel TxBD ......................................................................30-35
30.5.9 SMC GCI Event Register (SMCE)/Mask Register (SMCM) ......................30-36
Title
Chapter 31
Page
Number
Serial Peripheral Interface
31.1 Features ..............................................................................................................31-2
31.2 SPI Clocking and Signal Functions....................................................................31-2
31.3 Configuring the SPI Controller ..........................................................................31-3
31.3.1 The SPI as a Master Device ...........................................................................31-3
31.3.2 The SPI as a Slave Device .............................................................................31-5
31.3.3 The SPI in Multimaster Operation ................................................................. 31-5
31.4 SPI Registers ......................................................................................................31-7
31.4.1 SPI Mode Register (SPMODE) .....................................................................31-7
31.4.1.1 SPI Transfers with Different Clocking Modes .......................................... 31-8
31.4.1.2 SPI Examples with Different SPMODE[LEN] Values.............................. 31-9
31.4.2 SPI Event/Mask Registers (SPIE/SPIM) .....................................................31-10
31.4.3 SPI Command Register (SPCOM)............................................................... 31-10
31.5 SPI Parameter RAM......................................................................................... 31-11
31.5.1 Receive/Transmit Function Code Registers (RFCR/TFCR)........................ 31-12
31.6 SPI Commands.................................................................................................31-13
31.7 The SPI Buffer Descriptor (BD) Table ............................................................31-13
31.7.1 SPI Buffer Descriptors (BDs) ......................................................................31-14
31.7.1.1 SPI Receive BD (RxBD).......................................................................... 31-14
31.7.1.2 SPI Transmit BD (TxBD) ........................................................................31-15
31.8 SPI Master Programming Example.................................................................. 31-17
31.9 SPI Slave Programming Example ....................................................................31-18
31.10 Handling Interrupts in the SPI.......................................................................... 31-19
MOTOROLA Contents xxvii
Page 28
CONTENTS
Paragraph
Number
Title
Page
Number
Chapter 32
I2C Controller
32.1 I2C Features ........................................................................................................32-2
32.2 I
32.3 I
32.3.1 I
32.3.2 I
32.3.3 I
32.3.4 I
32.4 I
32.4.1 I
32.4.2 I
32.4.3 I
32.4.4 I
32.4.5 I
32.5 I
32.6 I
32.7 I
32.7.1 I
32.7.1.1 I
32.7.1.2 I
2
C Controller Clocking and Signal Functions...................................................32-2
2
C Controller Transfers .....................................................................................32-3
2
C Master Write (Slave Read).......................................................................32-3
2
C Loopback Testing ....................................................................................32-4
2
C Master Read (Slave Write).......................................................................32-4
2
C Multi-Master Considerations ...................................................................32-5
2
C Registers.......................................................................................................32-6
2
C Mode Register (I2MOD)..........................................................................32-6
2
C Address Register (I2ADD) ......................................................................32-7
2
C Baud Rate Generator Register (I2BRG) ..................................................32-7
2
C Event/Mask Registers (I2CER/I2CMR) ..................................................32-8
2
C Command Register (I2COM) ..................................................................32-8
2
C Parameter RAM ...........................................................................................32-9
2
C Commands .................................................................................................32-11
2
C Buffer Descriptor (BD) Tables ..................................................................32-11
2
C Buffer Descriptors (BDs).......................................................................32-12
2
C Receive Buffer Descriptor (RxBD) ...................................................32-12
2
C Transmit Buffer Descriptor (TxBD) ..................................................32-13
Chapter 33
Parallel Interface Port
33.1 Features...............................................................................................................33-1
33.2 Core Control vs. CP Control...............................................................................33-2
33.2.1 Core Control ...................................................................................................33-2
33.2.2 CP Control ......................................................................................................33-2
33.3 The PIP Parameter RAM....................................................................................33-3
33.3.1 PIP Transmitter Parameter RAM ...................................................................33-3
33.3.1.1 PIP Function Code Register (PFCR)..........................................................33-4
33.3.1.2 Status Mask Register (SMASK).................................................................33-4
33.3.2 PIP Receiver Parameter RAM........................................................................33-5
33.3.2.1 Control Character Table, RCCM, and RCCR ............................................33-6
33.4 The PIP Registers ...............................................................................................33-7
33.4.1 PIP Configuration Register (PIPC) ................................................................33-7
33.4.2 PIP Event Register (PIPE)..............................................................................33-9
33.4.3 PIP Mask Register ........................................................................................33-10
33.4.4 PIP Timing Parameters Register (PTPR) .....................................................33-10
33.4.5 The Port B Registers.....................................................................................33-10
xxviii MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 29
CONTENTS
Paragraph
Number
33.5 PIP Buffer Descriptors .....................................................................................33-11
33.5.1 The PIP Tx Buffer Descriptor (TxBD) ........................................................33-12
33.5.2 The PIP Rx Buffer Descriptor (RxBD)........................................................33-13
33.6 PIP CP Commands...........................................................................................33-14
33.7 Handshaking I/O Modes...................................................................................33-15
33.7.1 Interlocked Handshake Mode ......................................................................33-15
33.7.2 Pulsed Handshake Mode ..............................................................................33-16
33.7.2.1 The BUSY Signal..................................................................................... 33-17
33.7.2.2 Pulsed Handshake Timing ....................................................................... 33-17
33.8 Transparent Transfers....................................................................................... 33-19
33.9 Implementing Centronics ................................................................................. 33-19
33.9.1 PIP as a Centronics Transmitter...................................................................33-20
33.9.1.1 Centronics Tx Errors and the PIPE ..........................................................33-21
33.9.2 PIP as a Centronics Receiver .......................................................................33-22
33.9.2.1 Centronics Rx Errors and the PIPE ..........................................................33-22
Title
Chapter 34
Page
Number
Parallel I/O Ports
34.1 Features ..............................................................................................................34-2
34.2 Port A .................................................................................................................34-2
34.2.1 Port A Registers .............................................................................................34-3
34.2.1.1 Port A Open-Drain Register (PAODR) ..................................................... 34-3
34.2.1.2 Port A Data Register (PADAT) .................................................................34-4
34.2.1.3 Port A Data Direction Register (PADIR) .................................................. 34-4
34.2.1.4 Port A Pin Assignment Register (PAPAR) ................................................34-5
34.2.2 Port A Configuration Examples .....................................................................34-6
34.2.3 Port A Functional Block Diagrams ................................................................34-6
34.3 Port B .................................................................................................................34-8
34.3.1 The Port B Registers ......................................................................................34-9
34.3.1.1 Port B Open-Drain Register (PBODR) ...................................................... 34-9
34.3.1.2 Port B Data Register (PBDAT)................................................................34-10
34.3.1.3 Port B Data Direction Register (PBDIR) ................................................. 34-10
34.3.1.4 Port B Pin Assignment Register (PBPAR) ..............................................34-11
34.3.2 Port B Configuration Example..................................................................... 34-12
34.4 Port C ...............................................................................................................34-12
34.4.1 Port C Registers............................................................................................34-14
34.4.1.1 Port C Data Register (PCDAT)................................................................34-15
34.4.1.2 Port C Data Direction Register (PCDIR) ................................................. 34-15
34.4.1.3 Port C Pin Assignment Register (PCPAR) ..............................................34-15
34.4.1.4 Port C Special Options Register (PCSO) ................................................. 34-16
34.4.1.5 Port C Interrupt Control Register (PCINT).............................................. 34-17
MOTOROLA Contents xxix
Page 30
CONTENTS
Paragraph
Number
34.5 Port D................................................................................................................34-17
34.5.1 Port D Registers............................................................................................34-18
34.5.1.1 Port D Data Register.................................................................................34-18
34.5.1.2 Port D Data Direction Register (PDDIR) .................................................34-19
34.5.1.3 Port D Pin Assignment Register (PDPAR) ..............................................34-19
Title
Chapter 35
Page
Number
CPM Interrupt Controller
35.1 Features...............................................................................................................35-1
35.2 CPM Interrupt Source Priorities .........................................................................35-3
35.2.1 Programming Relative Priority (Grouping and Spreading)............................35-3
35.2.2 Highest Priority Interrupt ...............................................................................35-4
35.2.3 Nested Interrupts ............................................................................................35-4
35.3 Masking Interrupt Sources in the CPM ..............................................................35-4
35.4 Generating and Calculating Interrupt Vectors....................................................35-5
35.5 CPIC Registers ...................................................................................................35-6
35.5.1 CPM Interrupt Configuration Register (CICR)..............................................35-7
35.5.2 CPM Interrupt Pending Register (CIPR)........................................................35-8
35.5.3 CPM Interrupt Mask Register ........................................................................35-9
35.5.4 CPM Interrupt In-Service Register (CISR) ....................................................35-9
35.5.5 CPM Interrupt Vector Register (CIVR) .......................................................35-10
35.6 Interrupt Handler ExampleÑSingle-Event Interrupt Source ...........................35-10
35.7 Interrupt Handler ExampleÑMultiple-Event Interrupt Source........................35-11
Chapter 36
Digital Signal Processing
36.1 Features...............................................................................................................36-1
36.2 DSP Functionality...............................................................................................36-2
36.3 DSP Function Descriptors (FDs)........................................................................36-3
36.4 Data Representation............................................................................................36-4
36.5 Input and Output Buffers....................................................................................36-5
36.6 Buffer and Coefficient Base Pointers (CBASE, XPTR, XYPTR) .....................36-5
36.7 DSP Parameter RAM..........................................................................................36-5
36.8 DSP CP Commands............................................................................................36-6
36.9 DSP Function Priority within the CPM..............................................................36-6
36.10 DSP Event/Mask Registers (SDSR/SDMR).......................................................36-7
36.11 FIR Library Functions ........................................................................................36-7
36.11.1 FIR1ÐReal C, Real X, and Real Y..................................................................36-8
36.11.1.1 FIR1 Coefficient, Input, and Output Buffers .............................................36-8
36.11.1.2 FIR1 Function Descriptor...........................................................................36-9
xxx MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 31
CONTENTS
Paragraph
Number
36.11.1.3 FIR1 Applications ....................................................................................36-10
36.11.2 FIR2ÐReal C, Complex X, and Complex Y................................................. 36-10
36.11.2.1 FIR2 Coefficient, Input, and Output Buffers ...........................................36-10
36.11.2.2 FIR2 Function Descriptor ........................................................................36-11
36.11.2.3 FIR2 Applications ....................................................................................36-12
36.11.3 FIR3ÐComplex C, Complex X, and Real/Complex Y.................................36-12
36.11.3.1 FIR3 Coefficient, Input, and Output Buffers ...........................................36-13
36.11.3.2 FIR3 Function Descriptor ........................................................................36-14
36.11.3.3 FIR3 Applications ....................................................................................36-14
36.11.4 FIR5ÐComplex C, Complex X, and Complex Y .........................................36-15
36.11.4.1 FIR5 Coefficient, Input, and Output Buffers ...........................................36-15
36.11.4.2 FIR5 Function Descriptor ........................................................................36-16
36.11.4.3 FIR5 Applications ....................................................................................36-16
36.11.5 FIR6ÐComplex C, Real X, and Complex Y................................................. 36-17
36.11.5.1 FIR6 Coefficient, Input, and Output Buffers ...........................................36-17
36.11.5.2 FIR6 Function Descriptor ........................................................................36-18
36.12 IIRÐReal C, Real X, Real Y ............................................................................. 36-19
36.12.1 IIR Coefficient, Input, and Output Buffers .................................................. 36-19
36.12.2 IIR Function Descriptor ...............................................................................36-20
36.12.3 IIR Applications ...........................................................................................36-21
36.13 Modulation (MOD)ÐReal Sin, Real Cos, Complex X, and
Real/Complex Y........................................................................................... 36-21
36.13.1 Modulation Table, Input, and Output Buffers.............................................. 36-21
36.13.2 MOD Function Descriptor ...........................................................................36-22
36.13.3 MOD Applications .......................................................................................36-22
36.14 DEMODÐReal Sin; Real Cos, Real X, and Complex Y ..................................36-23
36.14.1 Modulation Table, Input and Output Buffers, and AGC Constant ..............36-23
36.14.2 DEMOD Function Descriptor ......................................................................36-24
36.14.3 DEMOD Applications.................................................................................. 36-25
36.15 LMS1ÐComplex Coefficients, Complex Samples, and
Real/Complex Scalar.................................................................................... 36-25
36.15.1 Coefficients and Input Buffers .....................................................................36-25
36.15.2 LMS1 Function Descriptor ..........................................................................36-26
36.15.3 LMS1 Applications ...................................................................................... 36-26
36.16 LMS2ÐComplex Coefficients and Samples, and Real/Complex Scalar ..........36-26
36.16.1 LMS2 Coefficients and Input Buffers.......................................................... 36-27
36.16.2 LMS2 Function Descriptor ..........................................................................36-27
36.16.3 LMS2 Applications ...................................................................................... 36-28
36.17 Weighted Vector Addition (WADD)ÐReal X and Real Y...............................36-28
36.17.1 WADD Coefficients and Input Buffers........................................................36-28
36.17.2 WADD Function Descriptor ........................................................................36-29
36.17.3 WADD Applications....................................................................................36-30
36.18 DSP Performance Using the Core Alone Versus Using the CPM ................... 36-30
Title
Page
Number
MOTOROLA Contents xxxi
Page 32
CONTENTS
Paragraph
Number
36.18.1 Tx Filter Example (Core Only) ....................................................................36-30
36.18.2 Tx Filter Example (Core and CPM) .............................................................36-31
36.19 DSP Function Execution Times and CPM Performance Calculation ..............36-33
Title
Chapter 37
Page
Number
System Development and Debugging
37.1 Tracking Program Flow......................................................................................37-1
37.1.1 Program Trace Functional Description ..........................................................37-2
37.1.2 Instruction Fetch Show Cycle Control ...........................................................37-3
37.1.3 Program Trace Signals ...................................................................................37-3
37.1.4 Program Trace Special Cases .........................................................................37-4
37.1.4.1 Queue Flush Information Special Case ......................................................37-4
37.1.4.2 Program Trace When In Debug Mode .......................................................37-5
37.1.4.3 Sequential Instructions Marked as Indirect Branch ...................................37-5
37.1.5 Reconstructing Program Trace .......................................................................37-5
37.1.5.1 Back Trace..................................................................................................37-5
37.1.5.2 Window Trace ............................................................................................37-6
37.1.5.2.1 Synchronizing the Trace Window to Internal Core Events....................37-6
37.1.5.3 Detecting the Trace Window Start Address ...............................................37-6
37.1.5.4 Detecting the Assertion/Negation of VSYNC............................................37-7
37.1.5.5 Detecting the Trace Window End Address ................................................37-7
37.1.5.6 Efficient Trace Information Capture ..........................................................37-7
37.2 Watchpoints and Breakpoints Support ...............................................................37-8
37.2.1 Key Features...................................................................................................37-9
37.2.2 Internal Watchpoints and Breakpoints Logic ...............................................37-10
37.2.3 Functional Description .................................................................................37-11
37.2.3.1 Instruction Support Detailed Description .................................................37-11
37.2.3.2 Load/Store Support Detailed Description ................................................37-12
37.2.3.3 The Counters ............................................................................................37-14
37.2.3.4 Trap Enable Programming .......................................................................37-15
37.2.4 Operation Details..........................................................................................37-15
37.2.4.1 Restrictions ...............................................................................................37-15
37.2.4.2 Byte and Half Word Working Modes ......................................................37-15
37.2.4.2.1 Examples ..............................................................................................37-16
37.2.4.3 Context Dependent Filter .........................................................................37-17
37.2.4.4 Ignore First Match ....................................................................................37-17
37.2.4.5 Generating Six Compare Types ...............................................................37-18
37.2.5 Load/Store Breakpoint Example ..................................................................37-18
37.3 Development System Interface.........................................................................37-19
37.3.1 Debug Mode Operation ................................................................................37-21
37.3.1.1 Debug Mode Enable vs. Debug Mode Disable ........................................37-22
xxxii MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 33
CONTENTS
Paragraph
Number
37.3.1.2 Entering Debug Mode .............................................................................. 37-23
37.3.1.3 Debug Mode Indication ........................................................................... 37-24
37.3.1.4 Checkstop State and Debug Mode ...........................................................37-24
37.3.1.5 Saving Machine State when Entering Debug Mode ................................37-25
37.3.1.6 Running in Debug Mode..........................................................................37-25
37.3.1.7 Exiting Debug Mode ................................................................................ 37-25
37.3.2 Development Port Communication.............................................................. 37-25
37.3.2.1 Development Port Pins............................................................................. 37-26
37.3.2.1.1 Development Serial Clock (DSCK) .....................................................37-26
37.3.2.1.2 Development Serial Data In (DSDI) ....................................................37-26
37.3.2.1.3 Development Serial Data Out (DSDO)................................................37-26
37.3.2.1.4 Freeze ................................................................................................... 37-26
37.3.2.2 Development Port Registers..................................................................... 37-27
37.3.2.2.1 Development Port Shift Register .........................................................37-27
37.3.2.2.2 Trap Enable Control Register (TECR)................................................. 37-27
37.3.2.2.3 Development Port Registers Decode ...................................................37-28
37.3.2.3 Development Port Serial CommunicationsÐClock Mode ........................ 37-28
37.3.2.3.1 Asynchronous Clocked ModeÑUsing DSCK..................................... 37-28
37.3.2.3.2 Synchronous Self-Clocked ModeÑUsing CLKOUT.......................... 37-29
37.3.2.3.3 Selection of Development Port Clock Mode .......................................37-29
37.3.2.4 Development Port Serial CommunicationsÐTrap Enable Mode ..............37-30
37.3.2.4.1 Serial Data Into Development Port ......................................................37-30
37.3.2.4.2 Serial Data Out of Development Port ..................................................37-31
37.3.2.5 Development Port Serial CommunicationsÐDebug Mode .......................37-32
37.3.2.5.1 Serial Data Into Development Port ......................................................37-32
37.3.2.5.2 Serial Data Out of Development Port ..................................................37-33
37.3.2.5.3 Fast Download Procedure ....................................................................37-34
37.4 Software Monitor Debugger Support...............................................................37-35
37.4.1 Freeze Indication..........................................................................................37-35
37.5 Development Support Programming Model ....................................................37-36
37.5.1 Development Support Registers................................................................... 37-37
37.5.1.1 Comparator AÐH Value Registers (CMPAÐCMPH) ...............................37-37
37.5.1.2 Breakpoint Address Register (BAR)........................................................ 37-38
37.5.1.3 Instruction Support Control Register (ICTRL) ........................................ 37-39
37.5.1.4 Load/Store Support Comparators Control Register (LCTRL1)...............37-40
37.5.1.5 Load/Store Support AND-OR Control Register (LCTRL2) ....................37-41
37.5.1.6 Breakpoint Counter Value and Control Registers
(COUNTA/COUNTB)......................................................................... 37-43
37.5.2 Debug Mode Registers.................................................................................37-44
37.5.2.1 Interrupt Cause Register (ICR) ................................................................37-44
37.5.2.2 Debug Enable Register (DER) ................................................................. 37-46
37.5.2.3 Development Port Data Register (DPDR) ...............................................37-47
Title
Page
Number
MOTOROLA Contents xxxiii
Page 34
CONTENTS
Paragraph
Number
Title
Chapter 38
Page
Number
IEEE 1149.1 Test Access Port
38.1 Overview ............................................................................................................38-1
38.2 TAP Controller ...................................................................................................38-2
38.3 Boundary Scan Register .....................................................................................38-3
38.4 Instruction Register.............................................................................................38-6
38.4.1 EXTEST .........................................................................................................38-6
38.4.2 SAMPLE/PRELOAD.....................................................................................38-6
38.4.3 BYPASS .........................................................................................................38-7
38.4.4 CLAMP ..........................................................................................................38-7
38.4.5 HIÐZ ...............................................................................................................38-7
38.5 TAP Usage Considerations.................................................................................38-7
38.6 Recommended TAP Configuration ....................................................................38-8
38.7 Motorola MPC860 BSDL Description...............................................................38-8
Appendix A
Byte Ordering
A.1 Byte Ordering Overview .....................................................................................A-1
A.2 MPC860 Byte-Ordering Mechanisms ................................................................A-1
A.3 BE Mode..............................................................................................................A-2
A.4 TLE Mode............................................................................................................A-2
A.4.1 TLE Mode System Examples ..........................................................................A-4
A.5 PPC-LE Mode......................................................................................................A-6
A.5.1 I/O Addressing in PPC-LE Mode ....................................................................A-8
A.6 Setting the Endian Mode Of Operation ...............................................................A-8
Appendix B
Serial Communications Performance
B.1 Serial Clocking (Peak Rate Limitation)............................................................... B-1
B.2 Bus Utilization ..................................................................................................... B-2
B.3 CPM Bandwidth (Average Rate Limitation) .......................................................B-2
B.3.1 Performance of Serial Channels ...................................................................... B-3
B.3.2 IDMA Considerations .....................................................................................B-4
B.3.3 Performance Calculations................................................................................ B-5
Appendix C
Register Quick Reference Guide
C.1 PowerPC RegistersÑUser Registers ...................................................................C-1
xxxiv MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 35
CONTENTS
Paragraph
Number
C.2 PowerPC RegistersÑSupervisor Registers......................................................... C-2
C.3 MPC860-Specific SPRs ...................................................................................... C-2
Title
Appendix D
Page
Number
MPC860 Instruction Set Listings
D.1 Instructions Sorted by Mnemonic ....................................................................... D-1
D.2 Instructions Sorted by Opcode ............................................................................ D-9
D.3 Instructions Grouped by Functional Categories................................................ D-17
D.4 Instructions Sorted by Form..............................................................................D-27
D.5 Instruction Set Legend ......................................................................................D-38
MOTOROLA Contents xxxv
Page 36
CONTENTS
Paragraph
Number
Title
Page
Number
xxxvi MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 37
ILLUSTRATIONS
Figure
Number
1-1 MPC860 Block Diagram...................................................................................... 1-5
3-1 MPC860 External Signals.................................................................................... 3-2
4-1 Block Diagram of the Core .................................................................................. 4-4
4-2 Instruction Flow Conceptual Diagram................................................................. 4-6
4-3 Basic Instruction Pipeline Timing ....................................................................... 4-7
4-4 Sequencer Data Path ............................................................................................ 4-8
4-5 LSU Functional Block Diagram ........................................................................ 4-11
5-1 Condition Register (CR) ...................................................................................... 5-2
5-2 XER Register ....................................................................................................... 5-3
5-3 Machine State Register (MSR) ............................................................................ 5-7
7-1 Exception Latency ............................................................................................. 7-18
8-1 Instruction Cache Organization ........................................................................... 8-3
8-2 Data Cache Organization ..................................................................................... 8-5
8-3 Instruction Cache Control and Status Register (IC_CST) ................................... 8-7
8-4 Instruction Cache Address Register (IC_ADR)................................................... 8-8
8-5 Instruction Cache Data Port Register (IC_DAT)................................................. 8-8
8-6 Data Cache Control and Status Register (DC_CST) ......................................... 8-12
8-7 Data Cache Address Register (DC_ADR)......................................................... 8-13
8-8 Data Cache Data Port Register (DC_DAT) ....................................................... 8-14
8-9 Instruction Cache Data Path............................................................................... 8-21
9-1 Read/Instruction Fetch Flow Diagram................................................................. 9-4
9-2 Flow of Load/Store Access.................................................................................. 9-5
9-3 Effective-to-Physical Address Translation for 4-Kbyte Pages
Block Diagram..................................................................................................... 9-6
9-4 Two-Level Translation Table (MD_CTR[TWAM] = 1)................................... 9-10
9-5 Two-Level Translation Table (MD_CTR[TWAM] = 0)................................... 9-12
9-6 IMMU Control Register (MI_CTR) .................................................................. 9-16
9-7 DMMU Control Register (MD_CTR) ............................................................... 9-17
9-8 IMMU/DMMU Effective Page Number Register (Mx_EPN)........................... 9-18
9-9 IMMU Tablewalk Control Register (MI_TWC) ............................................... 9-19
9-10 DMMU Tablewalk Control Register (MD_TWC) ............................................ 9-20
9-11 IMMU Real Page Number Register (MI_RPN) ................................................ 9-21
9-12 DMMU Real Page Number Register (MD_RPN) ............................................. 9-22
9-13 MMU Tablewalk Base Register (M_TWB) ...................................................... 9-23
9-14 MMU Current Address Space ID Register (M_CASID)................................... 9-23
9-15 MMU Access Protection Registers (MI_AP/MD_AP)...................................... 9-24
Title
Page
Number
MOTOROLA Illustrations xxxvii
Page 38
ILLUSTRATIONS
Figure
Number
9-16 MMU Tablewalk Special Register (M_TW) ..................................................... 9-24
9-17 IMMU CAM Entry Read Register (MI_CAM) ................................................. 9-25
9-18 IMMU RAM Entry Read Register 0 (MI_RAM0) ............................................ 9-26
9-19 IMMU RAM Entry Read Register 1 (MI_RAM1) ............................................ 9-27
9-20 DMMU CAM Entry Read Register (MD_CAM).............................................. 9-28
9-21 DMMU RAM Entry Read Register 0 (MD_RAM0)......................................... 9-29
9-22 DMMU RAM Entry Read Register 1 (MD_RAM1)......................................... 9-30
9-23 DTLB Reload Code Example ............................................................................ 9-33
9-24 ITLB Reload Code Example.............................................................................. 9-33
9-25 Configuring the TLB Replacement Counter...................................................... 9-34
10-1 Data Cache Load Timing ................................................................................... 10-2
10-2 Writeback Arbitration TimingÑExample 1 ...................................................... 10-2
10-3 Writeback Arbitration TimingÑExample 2 ...................................................... 10-2
10-4 Private Writeback Bus Load Timing ................................................................. 10-3
10-5 External Load Timing ........................................................................................ 10-3
10-6 Full Completion Queue Timing......................................................................... 10-4
10-7 Branch Folding Timing...................................................................................... 10-5
10-8 Branch Prediction Timing.................................................................................. 10-5
10-9 Bus Latency for String Instructions ................................................................... 10-8
11-1 System Configuration and Protection Logic...................................................... 11-3
11-2 Internal Memory Map Register (IMMR)........................................................... 11-5
11-3 SIU Module Configuration Register (SIUMCR)............................................... 11-6
11-4 System Protection Control Register (SYPCR) .................................................. 11-9
11-5 Transfer Error Status Register (TESR) ............................................................ 11-10
11-6 Register Lock Mechanism ............................................................................... 11-12
11-7 MPC860 Interrupt Structure ............................................................................ 11-13
11-8 SIU Interrupt Processing.................................................................................. 11-15
11-9 IRQ0 Logical Representation .......................................................................... 11-15
11-10 SIU Interrupt Pending Register (SIPEND) ...................................................... 11-17
11-11 SIU Interrupt Mask Register (SIMASK) ......................................................... 11-17
11-12 SIU Interrupt Edge/Level Register (SIEL) ...................................................... 11-18
11-13 SIU Interrupt Vector Register (SIVEC)........................................................... 11-19
11-14 Interrupt Table Handling Example .................................................................. 11-20
11-15 Software Watchdog Timer Service State Diagram.......................................... 11-21
11-16 Software Watchdog Timer Block Diagram ..................................................... 11-22
11-17 Software Service Register (SWSR) ................................................................. 11-22
11-18 Decrementer Register (DEC)........................................................................... 11-24
11-19 Timebase Upper Register (TBU) ..................................................................... 11-24
11-20 Timebase Lower Register (TBL) ..................................................................... 11-25
11-21 Timebase Reference Registers (TBREFA and TBREFB) ............................... 11-25
11-22 Timebase Status and Control Register (TBSCR)............................................. 11-26
11-23 Real-Time Clock Block Diagram .................................................................... 11-27
11-24 Real-Time Clock Status and Control Register (RTCSC) ................................ 11-27
Title
Page
Number
xxxviii MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 39
ILLUSTRATIONS
Figure
Number
11-25 Real-Time Clock Register (RTC) .................................................................... 11-28
11-26 Real-Time Clock Alarm Register (RTCAL).................................................... 11-29
11-27 Real-Time Clock Alarm Seconds Register (RTSEC)...................................... 11-30
11-28 Periodic Interrupt Timer Block Diagram......................................................... 11-31
11-29 Periodic Interrupt Status and Control Register (PISCR) ................................. 11-31
11-30 PIT Count Register (PITC) .............................................................................. 11-32
11-31 PIT Register (PITR)......................................................................................... 11-33
12-1 Power-On and Hard Reset Sequence ................................................................. 12-4
12-2 Soft Reset Sequence........................................................................................... 12-5
12-3 Reset Status Register (RSR) .............................................................................. 12-5
12-4 Data Bus Configuration Input Circuit................................................................ 12-7
12-5 Reset Configuration Sampling for Short PORESET Assertion......................... 12-8
12-6 Reset Configuration Sampling for Long PORESET Assertion ......................... 12-8
12-7 Reset Configuration Sampling Timing Requirements....................................... 12-9
12-8 Hard Reset Configuration Word ........................................................................ 12-9
13-1 MPC860 External Signals.................................................................................. 13-2
13-2 Signals and Pin Numbers (Part 1)...................................................................... 13-3
13-3 Signals and Pin Numbers (Part 2)...................................................................... 13-4
13-4 Three-State Buffers and Active Pull-Up Buffers............................................. 13-21
14-1 Input Sample Window .......................................................................................14-2
14-2 MPC860 Bus Signals ......................................................................................... 14-3
14-3 Basic Transfer Protocol...................................................................................... 14-6
14-4 Basic Flow Diagram of a Single-Beat Read Cycle............................................ 14-7
14-5 Single-Beat Read CycleÐBasic TimingÐZero Wait States................................. 14-8
14-6 Basic Timing: Single-Beat Read Cycle, One Wait State................................... 14-9
14-7 Basic Flow of a Single-Beat Write Cycle ........................................................ 14-10
14-8 Basic Timing: Single-Beat Write Cycle, Zero Wait States.............................. 14-11
14-9 Basic Timing: Single-Beat Write Cycle, One Wait State ................................ 14-12
14-10 Basic Timing: Single-Beat, 32-Bit Data Write Cycle, 16-Bit Port Size.......... 14-13
14-11 Basic Flow of a Burst-Read Cycle................................................................... 14-16
14-12 Burst-Read Cycle: 32-Bit Port Size, Zero Wait State...................................... 14-17
14-13 Burst-Read CycleÐ32-Bit Port SizeÐOne Wait State....................................... 14-18
14-14 Burst-Read CycleÐ32-Bit Port SizeÐWait States between Beats..................... 14-19
14-15 Burst-Read Cycle: One Wait State between Beats (16-Bit Port Size)............. 14-20
14-16 Basic Flow of a Burst Write Cycle .................................................................. 14-21
14-17 Burst-Write CycleÐ32-Bit Port SizeÐZero Wait States ................................... 14-22
14-18 Burst-Inhibit CycleÐ32-Bit Port Size............................................................... 14-23
14-19 Internal Operand Representation ..................................................................... 14-24
14-20 Interface to Different Port Size Devices .......................................................... 14-24
14-21 Bus Arbitration Flowchart ............................................................................... 14-26
14-22 Masters Signals Basic Connection................................................................... 14-27
14-23 Bus Arbitration Timing Diagram..................................................................... 14-28
14-24 Internal Bus Arbitration State Machine ........................................................... 14-29
Title
Page
Number
MOTOROLA Illustrations xxxix
Page 40
ILLUSTRATIONS
Figure
Number
14-25 Termination Signals Protocol Basic Connection ............................................. 14-34
14-26 Termination Signals Protocol Timing Diagram............................................... 14-34
14-27 Reservation On Local Bus ............................................................................... 14-36
14-28 Reservation on Multilevel Bus Hierarchy........................................................ 14-37
14-29 Retry Transfer TimingÐInternal Arbiter .......................................................... 14-38
14-30 Retry Transfer TimingÐExternal Arbiter ......................................................... 14-39
14-31 Retry on Burst Cycle........................................................................................ 14-40
15-1 Clock Source and Distribution........................................................................... 15-2
15-2 Clock Module Components ...............................................................................15-3
15-3 .Crystal Circuit Examples .................................................................................. 15-5
15-4 SPLL Block Diagram......................................................................................... 15-6
15-5 Clock Dividers ................................................................................................. 15-10
15-6 Low-power dividers for GCLKx ..................................................................... 15-11
15-7 Divided System Clocks (GCLKx) Timing Diagram ....................................... 15-11
15-8 Memory Controller and External Bus Clocks Timing Diagram for
EBDF=0 and EBDF=1..................................................................................... 15-12
15-9 Memory Controller and External Bus Clocks Timing Diagram for
(CSRC=0 and DFNH=1) or (CSRC=1 and DFNL=0) .................................... 15-13
15-10 BRGCLK Divider ............................................................................................ 15-14
15-11 SYNCCLK Divider.......................................................................................... 15-15
15-12 MPC860 Power Rails....................................................................................... 15-17
15-13 MPC860 Low-Power Mode Flowchart............................................................ 15-20
15-14 Software-initiated Power-down Configuration................................................ 15-25
15-15 SCCR ...............................................................................................................15-27
15-16 PLL, Low-Power, and Reset Control Register (PLPRCR).............................. 15-30
16-1 Memory Controller Block Diagram................................................................... 16-3
16-2 Memory Controller Machine Selection ............................................................. 16-4
16-3 Simple System Configuration............................................................................ 16-5
16-4 Basic Memory Controller Operation ................................................................. 16-6
16-5 Base Registers (BRx)......................................................................................... 16-9
16-6 BR0 Reset Defaults............................................................................................ 16-9
16-7 Option Registers (ORx) ................................................................................... 16-11
16-8 OR0 Reset Defaults.......................................................................................... 16-11
16-9 Memory Status Register (MSTAT) ................................................................. 16-13
16-10 Machine A Mode Register/Machine B Mode Registers (MxMR)................... 16-14
16-11 Memory Command Register (MCR) ............................................................... 16-15
16-12 Memory Data Register (MDR) ........................................................................ 16-16
16-13 Memory Address Register (MAR)................................................................... 16-17
16-14 Memory Periodic Timer Prescaler Register (MPTPR).................................... 16-17
16-15 GPCM-to-SRAM Configuration...................................................................... 16-18
16-16 GPCM Peripheral Device Interface ................................................................. 16-20
16-17 GPCM Peripheral Device Basic Timing (ACS = 1x and TRLX = 0).............. 16-20
16-18 GPCM Memory Device Interface.................................................................... 16-21
Title
Page
Number
xl MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 41
ILLUSTRATIONS
Figure
Number
16-19 GPCM Memory Device Basic Timing (ACS = 00, CSNT = 1,
TRLX = 0) ....................................................................................................... 16-21
16-20 GPCM Memory Device Basic Timing (ACS ¹ 00, CSNT = 1,
TRLX = 0) ....................................................................................................... 16-22
16-21 GPCM Relaxed Timing Read (ACS = 1x, SCY = 1, CSNT = 0, and
TRLX = 1) ....................................................................................................... 16-22
16-22 GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 0,
TRLX = 1) ....................................................................................................... 16-23
16-23 GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 1,
TRLX =1) ........................................................................................................ 16-24
16-24 GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1,
TRLX =1) ........................................................................................................ 16-24
16-25 GPCM Read Followed by Write (EHTR = 0) ................................................. 16-25
16-26 GPCM Write Followed by Read (EHTR = 1) ................................................. 16-26
16-27 GPCM Read Followed by Read from Different Banks (EHTR = 1)............... 16-26
16-28 GPCM Read Followed by Read from Same Bank (EHTR = 1) ...................... 16-27
16-29 Asynchronous External Master Configuration for GPCM-Handled
Memory Devices.............................................................................................. 16-28
16-30 Asynchronous External Master, GPCM-Handled Memory Access
Timing (TRLX = 0) ......................................................................................... 16-29
16-31 User-Programmable Machine Block Diagram................................................. 16-30
16-32 RAM Array Indexing....................................................................................... 16-31
16-33 Memory Periodic Timer Request Block Diagram ........................................... 16-32
16-34 UPM Clock Scheme One (Division Factor = 1) .............................................. 16-33
16-35 UPM Clock Scheme Two (Division Factor = 2) ............................................. 16-33
16-36 UPM Signals Timing Example One (Division Factor = 1, EBDF = 00) ......... 16-34
16-37 UPM Signals Timing Example Two (Division Factor = 2, EBDF = 01) ........ 16-35
16-38 RAM Array and Signal Generation ................................................................. 16-35
16-39 The RAM Word ............................................................................................... 16-36
16-40 .CS Signal Selection......................................................................................... 16-39
16-41 BS Signal Selection.......................................................................................... 16-40
16-42 Early GPL5 Control ......................................................................................... 16-41
16-43 Address Multiplex Timing............................................................................... 16-44
16-44 UPM Read Access Data Sampling .................................................................. 16-48
16-45 Wait Mechanism Timing for Internal and External Synchronous Masters ..... 16-49
16-46 Wait Mechanism Timing for an External Asynchronous Master .................... 16-50
16-47 Synchronous External Master Access.............................................................. 16-53
16-48 Asynchronous External Master Access ........................................................... 16-54
16-49 Synchronous External Master Interconnect Example...................................... 16-55
16-50 Synchronous External Master: Burst Read Access to Page Mode DRAM ..... 16-56
16-51 Asynchronous External Master Interconnect Example.................................... 16-57
16-52 Asynchronous External Master Timing Example............................................ 16-58
16-53 Page-Mode DRAM Interface Connection ....................................................... 16-59
Title
Page
Number
MOTOROLA Illustrations xli
Page 42
ILLUSTRATIONS
Figure
Number
16-54 Single-Beat Read Access to Page-Mode DRAM............................................. 16-61
16-55 Single-Beat Write Access to Page Mode DRAM ............................................ 16-62
16-56 Burst Read Access to Page-Mode DRAM (No LOOP)................................... 16-63
16-57 Burst Read Access to Page-Mode DRAM (LOOP)......................................... 16-64
16-58 Burst Write Access to Page-Mode DRAM (No LOOP).................................. 16-65
16-59 Burst Write Access to Page-Mode DRAM (LOOP)........................................ 16-66
16-60 Refresh Cycle (CAS before RAS) to Page-Mode DRAM............................... 16-67
16-61 Exception Cycle............................................................................................... 16-68
16-62 Optimized DRAM Burst Read Access ............................................................ 16-69
16-63 EDO DRAM Interface Connection.................................................................. 16-70
16-64 EDO DRAM Single-Beat Read Access........................................................... 16-72
16-65 EDO DRAM Single-Beat Write Access .......................................................... 16-73
16-66 EDO DRAM Burst Read Access ..................................................................... 16-74
16-67 EDO DRAM Burst Write Access .................................................................... 16-75
16-68 EDO DRAM Refresh Cycle (CAS before RAS) ............................................. 16-76
16-69 EDO DRAM Exception Cycle......................................................................... 16-77
16-70 Blank Work Sheet for a UPM.......................................................................... 16-78
17-1 System with Two PCMCIA Sockets.................................................................. 17-2
17-2 Internal DMA Request Logic............................................................................. 17-7
17-3 PCMCIA Interface Input Pins Register (PIPR) ................................................. 17-8
17-4 PCMCIA Interface Status Changed Register (PSCR) ....................................... 17-9
17-5 PCMCIA Interface Enable Register (PER)...................................................... 17-10
17-6 PCMCIA Interface General Control Register B (PGCRx) .............................. 17-12
17-7 PCMCIA Base Register (PBR)........................................................................ 17-13
17-8 PCMCIA Option Register 0Ð7 (POR0ÐPOR7)................................................ 17-13
17-9 PCMCIA Single-Beat Read Cycle PRS = 0 PSST = 1 PSL = 3 PSHT = 1..... 17-16
17-10 PCMCIA Single-Beat Read Cycle PRS = 0 PSST = 2 PSL = 4 PSHT = 1..... 17-17
17-11 PCMCIA Single-Beat Read Cycle PRS = 0 PSST = 1 PSL = 3 PSHT = 0..... 17-18
17-12 PCMCIA Single-Beat Write Cycle PRS = 2 PSST = 1 PSL = 3 PSHT = 1.... 17-19
17-13 PCMCIA Single-Beat Write Cycle PRS = 3 PSST = 1 PSL = 4 PSHT = 3.... 17-20
17-14 PCMCIA Single-Beat Write with Wait PRS = 3 PSST = 1 PSL = 3
PSHT = 0 ......................................................................................................... 17-21
17-15 PCMCIA Single-Beat Read with Wait PRS = 3 PSST = 1 PSL = 3
PSHT =1 .......................................................................................................... 17-22
17-16 PCMCIA I/O Read PPS = 1 PRS = 3 PSST = 1 PSL = 2 PSHT = 0............... 17-23
17-17 PCMCIA I/O Read PPS = 1 PRS = 3 PSST = 1 PSL = 2 PSHT = 0............... 17-24
17-18 PCMCIA DMA Read Cycle PRS = 4 PSST = 1 PSL = 3 PSHT = 0 .............. 17-25
18-1 CPM Block Diagram.......................................................................................... 18-2
18-2 MPC860 Application Design Example.............................................................. 18-4
18-3 CPM Timer Block Diagram............................................................................... 18-5
18-4 Timer Cascaded Mode Block Diagram.............................................................. 18-7
18-5 Timer Global Configuration Register (TGCR).................................................. 18-8
18-6 Timer Mode Registers (TMR1ÐTMR4)............................................................. 18-9
Title
Page
Number
xlii MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 43
ILLUSTRATIONS
Figure
Number
18-7 Timer Reference Registers (TRR1ÐTRR4) ..................................................... 18-10
18-8 Timer Capture Registers (TCR1ÐTCR4) ......................................................... 18-10
18-9 Timer Capture Registers (TCR1ÐTCR4) ......................................................... 18-11
18-10 Timer Event Registers (TER1ÐTER4)............................................................. 18-11
19-1 Communications Processor (CP) Block Diagram.............................................. 19-2
19-2 RISC Controller Configuration Register (RCCR) ............................................. 19-4
19-3 CP Command Register (CPCR)......................................................................... 19-6
19-4 Dual-Port RAM Block Diagram ........................................................................ 19-9
19-5 Dual-Port RAM Memory Map......................................................................... 19-10
19-6 RISC Timer Table RAM Usage....................................................................... 19-13
19-7 RISC Timer Command Register (TM_CMD) ................................................. 19-14
19-8 RISC Timer Event Register (RTER)/Mask Register (RTMR) ........................ 19-15
20-1 MPC860 SDMA Data Paths ..............................................................................20-1
20-2 SDMA U-Bus Arbitration (Cycle Steal)............................................................ 20-3
20-3 SDMA Configuration Register (SDCR) ............................................................ 20-4
20-4 SDMA Status Register (SDSR) ......................................................................... 20-4
20-5 DMA Channel Mode Register (DCMR)............................................................ 20-7
20-6 IDMA Status Registers (IDSR1/IDSR2) ........................................................... 20-8
20-7 IDMAx ChannelÕs BD Table ............................................................................. 20-9
20-8 IDMA Buffer Descriptor Structure.................................................................. 20-10
20-9 Function Code RegistersÑSFCR and DFCR.................................................. 20-11
20-10 SD
20-11 SD
20-12 SD
20-13 IDMA Channel Mode Register (DCMR) (Single-Buffer Mode) .................... 20-19
20-14 IDMA1 Status Register (IDSR1) (Single-Buffer Mode) ................................. 20-20
20-15 Single-Address IDMA1 Burst Timing (Single-Buffer Mode)......................... 20-21
21-1 MPC860 SI Block Diagram............................................................................... 21-2
21-2 Various Configurations of a TDM Channel....................................................... 21-5
21-3 Dual TDM Channel Example ............................................................................ 21-6
21-4 Enabling Connections through the SI ................................................................ 21-8
21-5 SI RAM Partitioning Using TDMa with Static Frames..................................... 21-9
21-6 SI RAMÑTwo TDMs with Static Frames ...................................................... 21-10
21-7 SI RAM Dynamic Changes with TDMa and TDMb ....................................... 21-12
21-8 SI RAM Partitioning Using TDMa with Dynamic Frames ............................. 21-13
21-9 SI RAM Partitioning Using Two TDMs with Dynamic Frames ..................... 21-13
21-10 SIRAM Entry................................................................................................... 21-14
21-11 Example Using SI RAMn[SWTR] .................................................................. 21-15
21-12 SI Global Mode Register (SIGMR) ................................................................. 21-17
21-13 SI Mode Register (SIMODE) .......................................................................... 21-18
ACK Timing Diagram: Single-Address
Peripheral Write, Externally-Generated T
ACK Timing Diagram: Single-Address
Peripheral Write, Internally-Generated T
ACK Timing Diagram: Single-Address
Peripheral Read, Internally-Generated T
Title
A..................................................... 20-16
A...................................................... 20-17
A....................................................... 20-18
Page
Number
MOTOROLA Illustrations xliii
Page 44
ILLUSTRATIONS
Figure
Number
21-14 One Clock Delay from Sync to Data (xFSD = 01) .......................................... 21-20
21-15 No Delay from Sync to Data (xFSD = 00) ...................................................... 21-20
21-16 Clock Edge (CE) Effect when DSC = 0 .......................................................... 21-21
21-17 Clock Edge (CE) Effect when DSC = 1 .......................................................... 21-21
21-18 Frame Transfers when xFSD = 0 and CE = 1.................................................. 21-22
21-19 CE = 0 and FE Interaction with xFSD = 0....................................................... 21-23
21-20 SI Clock Route Register (SICR) ...................................................................... 21-24
21-21 SI Command Register (SICMR)...................................................................... 21-25
21-22 SI Status Register (SISTR) .............................................................................. 21-25
21-23 SI RAM Pointer Register (SIRP)..................................................................... 21-26
21-24 Dual IDL Bus Application Example................................................................ 21-28
21-25 ISDN Terminal Adaptor Using IDL ................................................................ 21-29
21-26 IDL Bus Signals............................................................................................... 21-30
21-27 GCI Bus Signals............................................................................................... 21-33
21-28 Bank-of-Clocks Selection Logic for NMSI ..................................................... 21-37
21-29 Baud Rate Generator (BRG) Block Diagram .................................................. 21-39
21-30 Baud Rate Generator Configuration Registers (BRGCn)................................ 21-40
22-1 SCC Block Diagram .......................................................................................... 22-2
22-2 GSMR_HÑGeneral SCC Mode Register (High Order) ................................... 22-4
22-3 GSMR_LÑGeneral SCC Mode Register (Low Order)..................................... 22-6
22-4 Data Synchronization Register (DSR) ............................................................. 22-10
22-5 Transmit-on-Demand Register (TODR) .......................................................... 22-10
22-6 SCC Buffer Descriptors (BDs) ........................................................................ 22-12
22-7 SCC BD and Buffer Memory Structure........................................................... 22-13
22-8 Function Code Registers (RFCR and TFCR) ..................................................22-16
22-9 Output Delay from RTS Asserted for Synchronous Protocols ........................ 22-19
22-10 Output Delay from CTS Asserted for Synchronous Protocols ........................ 22-19
22-11 CTS Lost in Synchronous Protocols................................................................ 22-20
22-12 Using CD to Control Synchronous Protocol Reception .................................. 22-21
22-13 DPLL Receiver Block Diagram....................................................................... 22-22
22-14 DPLL Transmitter Block Diagram .................................................................. 22-23
22-15 DPLL Encoding Examples .............................................................................. 22-25
23-1 UART Character Format.................................................................................... 23-1
23-2 Two UART Multidrop Configurations .............................................................. 23-7
23-3 Control Character Table, RCCM, and RCCR.................................................... 23-8
23-4 Transmit Out-of-Sequence Register (TOSEQ)................................................ 23-10
23-5 Data Synchronization Register (DSR) ............................................................. 23-11
23-6 Protocol-Specific Mode Register for UART (PSMR) ..................................... 23-13
23-7 SCC UART Receiving using RxBDs .............................................................. 23-16
23-8 SCC UART RxBD........................................................................................... 23-17
23-9 SCC UART Transmit Buffer Descriptor (TxBD)............................................ 23-18
23-10 SCC UART Interrupt Event Example.............................................................. 23-20
23-11 SCC UART Event Register (SCCE) and Mask Register (SCCM) .................. 23-20
Title
Page
Number
xliv MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 45
ILLUSTRATIONS
Figure
Number
23-12 SCC Status Register for UART Mode (SCCS)................................................ 23-21
24-1 HDLC Framing Structure .................................................................................. 24-2
24-2 HDLC Address Recognition .............................................................................. 24-5
24-4 HDLC Mode Register (PSMR).......................................................................... 24-7
24-5 SCC HDLC Receive Buffer Descriptor (RxBD) ............................................... 24-8
24-6 SCC HDLC Receiving using RxBDs .............................................................. 24-10
24-7 SCC HDLC Transmit Buffer Descriptor (TxBD)............................................ 24-11
24-8 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) ..................... 24-12
24-9 SCC HDLC Interrupt Event Example.............................................................. 24-13
24-10 SCC HDLC Status Register (SCCS)................................................................ 24-14
24-11 Typical HDLC Bus Multimaster Configuration .............................................. 24-18
24-12 Typical HDLC Bus Single-Master Configuration ........................................... 24-19
24-13 Detecting an HDLC Bus Collision .................................................................. 24-20
24-14 Nonsymmetrical Tx Clock Duty Cycle for Increased Performance ................ 24-21
24-15 HDLC Bus Transmission Line Configuration ................................................. 24-21
24-16 Delayed RTS Mode.......................................................................................... 24-22
24-17 HDLC Bus TDM Transmission Line Configuration ....................................... 24-22
25-1 LocalTalk Frame Format ................................................................................... 25-1
25-2 Connecting the MPC860 to LocalTalk .............................................................. 25-3
26-1 Asynchronous HDLC Frame Structure.............................................................. 26-2
26-2 Receive Flowchart ............................................................................................. 26-4
26-3 TXCTL_TBL/RXCTL_TBL .............................................................................26-6
26-4 Asynchronous HDLC Event Register (SCCE)/Asynchronous HDLC
Mask Register (SCCM)...................................................................................... 26-9
26-5 SCC Status Register for Asynchronous HDLC Mode (SCCS) ....................... 26-10
26-6 Asynchronous HDLC Mode Register (PSMR)................................................ 26-11
26-7 SCC Asynchronous HDLC RxBDs ................................................................. 26-12
26-8 SCC Asynchronous HDLC TxBDs ................................................................. 26-13
26-9 Serial Infrared (SIR) Link................................................................................ 26-16
26-10 UART and IR Frames ...................................................................................... 26-16
27-1 Classes of BISYNC Frames............................................................................... 27-1
27-2 Control Character Table and RCCM ................................................................. 27-6
27-3 BISYNC SYNC (BSYNC) ................................................................................ 27-7
27-4 BISYNC DLE (BDLE) ...................................................................................... 27-8
27-5 Protocol-Specific Mode Register for BISYNC (PSMR) ................................. 27-10
27-6 SCC BISYNC RxBD ....................................................................................... 27-12
27-7 SCC BISYNC TxBD .......................................................................................27-14
27-8 BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM).............. 27-15
27-9 SCC Status Registers (SCCS).......................................................................... 27-16
28-1 Ethernet Frame Structure ................................................................................... 28-1
28-2 Ethernet Block Diagram .................................................................................... 28-2
28-3 Connecting the MPC860 to Ethernet ................................................................. 28-6
28-4 MPC860 Ethernet Serial CAM Interface......................................................... 28-10
Title
Page
Number
MOTOROLA Illustrations xlv
Page 46
ILLUSTRATIONS
Figure
Number
28-5 MPC860 Ethernet Parallel CAM Interface ...................................................... 28-11
28-6 Ethernet Address Recognition Flowchart ........................................................ 28-16
28-7 Ethernet Mode Register (PSMR) ..................................................................... 28-20
28-8 SCC Ethernet Receive RxBD .......................................................................... 28-21
28-9 Ethernet Receiving using RxBDs .................................................................... 28-23
28-10 SCC Ethernet TxBD ........................................................................................ 28-24
28-11 SCC Ethernet Event Register (SCCE)/Mask Register (SCCM) ...................... 28-25
28-12 Ethernet Interrupt Events Example.................................................................. 28-26
29-1 Sending Transparent Frames between MPC860................................................ 29-5
29-2 SCC Transparent Receive Buffer Descriptor (RxBD)....................................... 29-9
29-3 SCC Transparent Transmit Buffer Descriptor (TxBD) ................................... 29-11
29-4 SCC Transparent Event Register (SCCE)/Mask Register (SCCM) ................ 29-12
29-5 SCC Status Register in Transparent Mode (SCCS)......................................... 29-13
30-1 SMC Block Diagram.......................................................................................... 30-2
30-2 SMC Mode Registers (SMCMRn)..................................................................... 30-3
30-3 SMC Memory Structure..................................................................................... 30-5
30-4 SMC Function Code Registers (RFCR/TFCR).................................................. 30-7
30-5 SMC UART Frame Format ............................................................................. 30-10
30-6 SMC UART Receive BD (RxBD)................................................................... 30-14
30-7 SMC UART Receiving using RxBDs.............................................................. 30-16
30-8 SMC UART Transmit BD (TxBD).................................................................. 30-17
30-9 SMC UART Event Register (SMCE)/Mask Register (SMCM) ...................... 30-18
30-10 SMC UART Interrupts Example ..................................................................... 30-19
30-11 Synchronization with SMSYNx....................................................................... 30-23
30-12 Synchronization with the TSA......................................................................... 30-24
30-13 SMC Transparent Receive BD (RxBD)........................................................... 30-26
30-14 SMC Transparent Transmit BD (TxBD) ......................................................... 30-28
30-15 SMC Transparent Event Register (SMCE)/Mask Register (SMCM).............. 30-29
30-16 SMC GCI Monitor Channel RxBD.................................................................. 30-33
30-17 SMC GCI Monitor Channel TxBD.................................................................. 30-34
30-18 SMC C/I Channel RxBD ................................................................................. 30-35
30-19 SMC C/I Channel TxBD.................................................................................. 30-35
30-20 SMC GCI Event Register (SMCE)/Mask Register (SMCM) .......................... 30-36
31-1 SPI Block Diagram ............................................................................................ 31-1
31-2 Single-Master/Multi-Slave Configuration ......................................................... 31-4
31-3 Multimaster Configuration................................................................................. 31-6
31-4 SPI Mode Register (SPMODE) ......................................................................... 31-7
31-5 SPI Transfer Format with SPMODE[CP] = 0 ................................................... 31-8
31-6 SPI Transfer Format with SPMODE[CP] = 1 ................................................... 31-8
31-7 SPI Event/Mask Registers (SPIE/SPIM) ......................................................... 31-10
31-8 SPI Command Register (SPCOM)................................................................... 31-10
31-9 Receive/Transmit Function Code Registers (RFCR/TFCR)............................ 31-12
31-10 SPI Memory Structure ..................................................................................... 31-13
Title
Page
Number
xlvi MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 47
ILLUSTRATIONS
Figure
Number
31-11 SPI Receive BD (RxBD) ................................................................................. 31-14
31-12 SPI Transmit BD (TxBD) ................................................................................ 31-16
32-1 I2C Controller Block Diagram........................................................................... 32-1
32-2 I2C Master/Slave General Configuration .......................................................... 32-2
32-3 I2C Transfer Timing .......................................................................................... 32-3
32-4 I2C Master Write Timing................................................................................... 32-4
32-5 I2C Master Read Timing ................................................................................... 32-5
32-6 .I2C Mode Register (I2MOD)............................................................................ 32-6
32-7 I2C Address Register (I2ADD) ......................................................................... 32-7
32-8 I2C Baud Rate Generator Register (I2BRG) ..................................................... 32-7
32-9 I2C Event/Mask Registers (I2CER/I2CMR) ..................................................... 32-8
32-10 I2C Command Register (I2COM) ..................................................................... 32-9
32-11 I2C Function Code Registers (RFCR/TFCR).................................................. 32-11
32-12 I
32-13 I2C Receive Buffer Descriptor (RxBD) .......................................................... 32-13
32-14 I2C Transmit Buffer Descriptor (TxBD) ......................................................... 32-14
33-1 PIP Block Diagram ............................................................................................ 33-2
33-2 PIP Function Code Register (PFCR) .................................................................33-4
33-3 Status Mask Register (SMASK) ........................................................................ 33-4
33-4 Control Character Table, RCCM, and RCCR.................................................... 33-6
33-5 PIP Configuration Register (PIPC).................................................................... 33-8
33-6 PIP Event Register (PIPE) ................................................................................. 33-9
33-7 PIP Timing Parameters Register (PTPR)......................................................... 33-10
33-8 Port B General-Purpose I/O ............................................................................. 33-11
33-9 PIP Tx Buffer Descriptor (TxBD) ................................................................... 33-12
33-10 PIP Rx Buffer Descriptor (RxBD)................................................................... 33-13
33-11 Interlocked Handshake Mode Timing ............................................................. 33-15
33-12 Pulsed Handshake Full Cycle .......................................................................... 33-16
33-13 Pulsed Handshake BUSY Signal ..................................................................... 33-17
33-14 PIP Transmitter Timing Diagram .................................................................... 33-18
33-15 PIP Receiver TimingÑMode 0 ....................................................................... 33-18
33-16 PIP Receiver TimingÑMode 1 ....................................................................... 33-18
33-17 PIP Receiver TimingÑMode 2 ....................................................................... 33-18
33-18 PIP Receiver TimingÑMode 3 ....................................................................... 33-19
33-19 PIP Transparent Transfers................................................................................ 33-19
33-20 The PIP Centronics Interface Signals .............................................................. 33-20
33-21 PIP as a Centronics Transmitter....................................................................... 33-21
33-22 PIP as a Centronics Receiver ........................................................................... 33-22
34-1 Port A Open-Drain Register (PAODR) ............................................................. 34-3
34-2 Port A Data Register (PADAT) ......................................................................... 34-4
34-3 Port A Data Direction Register (PADIR) .......................................................... 34-5
34-4 Port A Pin Assignment Register (PAPAR)........................................................ 34-5
34-5 Block Diagram for PA15 (True for all Non-Open-Drain Port Signals)............. 34-7
2
C Memory Structure ..................................................................................... 32-12
Title
Page
Number
MOTOROLA Illustrations xlvii
Page 48
ILLUSTRATIONS
Figure
Number
34-6 Block Diagram for PA14 (True for all Open-Drain Port Signals)..................... 34-7
34-7 Port B Open-Drain Register (PBODR).............................................................. 34-9
34-8 Port B Data Register (PBDAT)........................................................................ 34-10
34-9 Port B Data Direction Register (PBDIR)......................................................... 34-11
34-10 Port B Pin Assignment Register (PBPAR) ...................................................... 34-11
34-11 Port C Data Register (PCDAT)........................................................................ 34-15
34-12 Port C Data Direction Register (PCDIR)......................................................... 34-15
34-13 Port C Pin Assignment Register (PCPAR) ...................................................... 34-16
34-14 Port C Special Options Register (PCSO)......................................................... 34-16
34-15 Port C Interrupt Control Register (PCINT) ..................................................... 34-17
34-16 Port D Data Register (PDDAT) ....................................................................... 34-19
34-17 Port D Data Direction Register (PDDIR) ........................................................ 34-19
34-18 Port D Pin Assignment Register (PDPAR)...................................................... 34-20
35-1 MPC860 Interrupt Structure .............................................................................. 35-2
35-2 Interrupt Request Masking................................................................................. 35-5
35-3 CPM Interrupt Configuration Register (CICR) ................................................. 35-7
35-4 CPM Interrupt Pending/Mask/In-Service Registers (CIPR/CIMR/CISR) ........ 35-8
35-5 CPM Interrupt Vector Register (CIVR)........................................................... 35-10
36-1 DSP Functionality Implementation.................................................................... 36-2
36-2 DSP Function Descriptor (FD) Chain Structure ................................................ 36-3
36-3 Function Descriptor (FD) Structure ................................................................... 36-3
36-4 Real Number Representation ............................................................................. 36-4
36-6 Circular Buffer ................................................................................................... 36-5
36-5 Complex Number Representation...................................................................... 36-5
36-7 DSP Event/Mask Registers (SDSR/SDMR)...................................................... 36-7
36-8 FIR1 Function .................................................................................................... 36-8
36-9 FIR1 Function Descriptor .................................................................................. 36-9
36-11 FIR2 Function .................................................................................................. 36-10
36-10 FIR1 Decimation Example .............................................................................. 36-10
36-12 FIR2 Function Descriptor ................................................................................ 36-11
36-13 FIR2 Filter Example ........................................................................................ 36-12
36-14 FIR3 Function .................................................................................................. 36-13
36-15 FIR3 Function Descriptor ................................................................................ 36-14
36-16 FIR3 Echo Cancellation Example.................................................................... 36-14
36-17 FIR5 Function .................................................................................................. 36-15
36-18 FIR5 Function Descriptor ................................................................................ 36-16
36-20 FIR6 Function .................................................................................................. 36-17
36-19 FIR5 Fractionally Spaced Equalizer Example................................................. 36-17
36-21 FIR6 Function Descriptor ................................................................................ 36-18
36-22 IIR Function..................................................................................................... 36-19
36-23 IIR Function Descriptor ................................................................................... 36-20
36-24 MOD Function................................................................................................. 36-21
36-25 MOD Function Descriptor ............................................................................... 36-22
Title
Page
Number
xlviii MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 49
ILLUSTRATIONS
Figure
Number
36-27 DEMOD Function............................................................................................ 36-23
36-26 MOD Modulation Example ............................................................................. 36-23
36-28 DEMOD Function Descriptor.......................................................................... 36-24
36-30 LMS1 Function ................................................................................................ 36-25
36-29 DEMOD Modulation Example ........................................................................ 36-25
36-32 LMS2 Function ................................................................................................ 36-26
36-31 LMS1 Function Descriptor .............................................................................. 36-26
36-33 LMS2 Function Descriptor .............................................................................. 36-27
36-34 WADD Function.............................................................................................. 36-28
36-35 WADD Function Descriptor ............................................................................ 36-29
36-36 Example DSP ApplicationÑTx Filter ............................................................. 36-30
36-37 Core and CPM Implementation of Filter Example .......................................... 36-32
37-1 Watchpoints and Breakpoint Support in the Core ............................................. 37-9
37-2 Instruction Support General Structure ............................................................. 37-12
37-3 Load/Store Support General Structure............................................................. 37-13
37-4 Partially Supported Watchpoints/Breakpoint Example ................................... 37-17
37-5 Functional Diagram of the MPC860 Debug Mode Support ............................ 37-20
37-6 Debug Mode Logic Diagram ........................................................................... 37-21
37-7 Debug Mode Reset Configuration Timing Diagram ....................................... 37-22
37-8 Development Port/BDM Connector Pinout Options ....................................... 37-27
37-9 Asynchronous Clocked Serial Communications ............................................. 37-28
37-10 Synchronous Self-Clocked Serial Communications........................................ 37-29
37-11 Enabling Clock Mode after Reset .................................................................... 37-30
37-12 Download Procedure Code Example ............................................................... 37-34
37-13 Fast and Slow Download Procedure Loops ..................................................... 37-35
37-14 Comparator AÐD Value Register (CMPAÐCMPD) ........................................ 37-37
37-15 Comparator EÐF Value Registers (CMPEÐCMPF) ......................................... 37-38
37-16 Comparator GÐH Value Registers (CMPGÐCMPH)....................................... 37-38
37-17 Breakpoint Address Register (BAR) ............................................................... 37-38
37-18 Instruction Support Control Register (ICTRL)................................................ 37-39
37-19 Load/Store Support Comparators Control Register (LCTRL1)....................... 37-40
37-20 Load/Store Support AND-OR Control Register (LCTRL2)............................ 37-41
37-21 Breakpoint Counter Value and Control Registers (COUNTA/COUNTB)...... 37-44
37-22 Interrupt Cause Register (ICR) ........................................................................ 37-44
37-23 Debug Enable Register (DER)......................................................................... 37-46
38-1 Test Logic Block Diagram................................................................................. 38-2
38-2 TAP Controller State Machine........................................................................... 38-3
38-3 Output Signal Boundary Scan Cell (Output Cell).............................................. 38-4
38-4 Observe-Only Input Signal Boundary Scan Cell (Input Cell) ........................... 38-4
38-5 Input/Output Control Boundary Scan Cell (I/O Control Cell)........................... 38-5
38-6 Bidirectional (I/O) Signal Boundary Scan Cell ................................................. 38-5
38-7 Bypass Register.................................................................................................. 38-7
A-1 TLE Mode Mechanisms..................................................................................... A-3
Title
Page
Number
MOTOROLA Illustrations xlix
Page 50
ILLUSTRATIONS
Figure
Number
A-2 Byte Swapping................................................................................................... A-4
A-3 PPC-LE Mode Mechanisms............................................................................... A-7
Title
Page
Number
l MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 51
TABLES
Tabl e
Number
i Acronyms and Abbreviated Terms.......................................................................... lxx
ii Terminology Conventions .................................................................................... lxxiii
iii Instruction Field Conventions .............................................................................. lxxiv
2-1 MPC860 Internal Memory Map .............................................................................. 2-1
3-1 Signal Descriptions.................................................................................................. 3-3
4-1 Static Branch Prediction .......................................................................................... 4-9
4-2 Bus Cycles Needed for Single-Register Load/Store Accesses.............................. 4-13
4-3 UISA-Level Features............................................................................................. 4-15
4-4 VEA-Level Features.............................................................................................. 4-16
4-5 OEA-Level Features.............................................................................................. 4-17
5-1 User-Level PowerPC Registers ............................................................................... 5-2
5-2 User-Level PowerPC SPRs ..................................................................................... 5-2
5-3 Bit Settings for CR0 Field of CR ............................................................................ 5-3
5-4 XER Field Definitions............................................................................................. 5-4
5-5 Supervisor-Level PowerPC Registers ..................................................................... 5-4
5-6 Supervisor-Level PowerPC SPRs............................................................................ 5-5
5-7 Value Summary of the DAR, BAR, and DSISR Registers ..................................... 5-6
5-8 MSR Field Descriptions .......................................................................................... 5-7
5-9 MPC860-Specific Supervisor-Level SPRs.............................................................. 5-9
5-10 MPC860-Specific Debug-Level SPRs .................................................................. 5-10
5-11 Addresses of SPRs Located Outside of the Core .................................................. 5-11
6-1 Memory Operands ................................................................................................... 6-2
6-2 Integer Arithmetic Instructions................................................................................ 6-8
6-3 Integer Compare Instructions ..................................................................................6-9
6-4 Integer Logical Instructions................................................................................... 6-10
6-5 Integer Rotate Instructions .................................................................................... 6-11
6-6 Integer Shift Instructions ....................................................................................... 6-11
6-7 Integer Load Instructions....................................................................................... 6-12
6-8 Integer Store Instructions ...................................................................................... 6-13
6-9 Integer Load and Store with Byte-Reverse Instructions........................................ 6-14
6-10 Integer Load and Store Multiple Instructions........................................................ 6-14
6-11 Integer Load and Store String Instructions............................................................ 6-14
6-12 Branch Instructions................................................................................................ 6-16
6-13 Condition Register Logical Instructions................................................................ 6-16
6-14 Trap Instructions.................................................................................................... 6-17
6-15 Move to/from Condition Register Instructions...................................................... 6-17
Title
Page
Number
MOTOROLA Contents li
Page 52
TABLES
Tabl e
Number
6-16 Memory Synchronization InstructionsÑUISA..................................................... 6-18
6-17 Move from Time Base Instruction ........................................................................ 6-20
6-18 Memory Synchronization InstructionsÑVEA ...................................................... 6-20
6-19 User-Level Cache Instructions ..............................................................................6-22
6-20 System Linkage Instructions ................................................................................. 6-22
6-21 Move to/from Machine State Register Instructions............................................... 6-22
6-22 Move to/from Special-Purpose Register Instructions............................................ 6-23
6-23 Supervisor-Level Cache Management Instruction ................................................ 6-23
6-24 Translation Lookaside Buffer Management Instructions ...................................... 6-24
7-1 Offset of First Instruction by Exception Type......................................................... 7-2
7-2 Instruction-Related Exception Detection Order ...................................................... 7-4
7-3 Exception Priority.................................................................................................... 7-4
7-4 Register Settings after a System Reset Interrupt Exception.................................... 7-5
7-5 Register Settings after a Machine Check Interrupt Exception ................................ 7-6
7-6 Register Settings after an External Interrupt ...........................................................7-7
7-7 Register Settings after an Alignment Exception ..................................................... 7-8
7-8 Register Settings after a Program Exception........................................................... 7-9
7-9 Register Settings after a Decrementer Exception.................................................. 7-10
7-10 Register Settings after a System Call Exception ................................................... 7-11
7-11 Register Settings after a Trace Exception ............................................................. 7-11
7-12 Register Settings after a Software Emulation Exception ...................................... 7-12
7-13 Register Settings after an Instruction TLB Miss Exception.................................. 7-13
7-14 Register Settings after a Data TLB Miss Exception.............................................. 7-13
7-15 Register Settings after an Instruction TLB Error Exception .................................7-14
7-16 Register Settings after a Data TLB Error Exception ............................................. 7-14
7-17 Register Settings after a Debug Exception............................................................ 7-15
7-18 Additional SPRs that Affect MSR Bits ................................................................. 7-17
7-19 Exception Latency ................................................................................................. 7-19
7-20 Before and After Exceptions .................................................................................7-20
8-1 Instruction Cache Control and Status RegisterÑIC_CST ...................................... 8-7
8-2 Instruction Cache Address RegisterÑIC_ADR...................................................... 8-8
8-3 Instruction Cache Data Port RegisterÑIC_DAT .................................................... 8-8
8-4 IC_ADR Fields for Cache Read Commands........................................................... 8-9
8-5 IC_DAT Format when Reading a Tag .................................................................... 8-9
8-6 Data Cache Control and Status RegisterÑDC_CST............................................. 8-12
8-7 Data Cache Address RegisterÑDC_ADR ............................................................ 8-14
8-8 Data Cache Data Port RegisterÑDC_DAT ..........................................................8-14
8-9 DC_ADR Fields for Cache Read Commands .......................................................8-14
8-10 DC_DAT Format when Reading a Tag................................................................. 8-15
8-11 Copyback Buffer Select Field (DC_CST[21Ð27]) Encoding................................ 8-15
9-1 Identical Entries Required in Level-One/Level-Two Tables ................................ 9-11
9-2 Number of Replaced EA Bits per Page Size .........................................................9-13
9-3 Level-One Segment Descriptor Format................................................................. 9-13
Title
Page
Number
lii MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 53
TABLES
Tabl e
Number
9-4 Level-Two (Page) Descriptor Format ................................................................... 9-14
9-5 MPC860-Specific MMU SPRs.............................................................................. 9-15
9-6 MI_CTR Field Descriptions .................................................................................. 9-16
9-7 MD_CTR Field Descriptions ................................................................................ 9-17
9-8 Mx_EPN Field Descriptions.................................................................................. 9-18
9-9 MI_TWC Field Descriptions................................................................................. 9-19
9-10 MD_TWC Field Descriptions ............................................................................... 9-20
9-11 MI_RPN Field Descriptions .................................................................................. 9-21
9-12 MD_RPN Field Descriptions ................................................................................ 9-22
9-13 M_TWB Field Descriptions .................................................................................. 9-23
9-14 M_CASID Field Descriptions ............................................................................... 9-24
9-15 MI_AP/MD_AP Field Descriptions ...................................................................... 9-24
9-16 MI_CAM Field Descriptions................................................................................. 9-25
9-17 MI_RAM0 Field Descriptions............................................................................... 9-26
9-18 MI_RAM1 Field Descriptions............................................................................... 9-27
9-19 MD_CAM Field Descriptions ............................................................................... 9-28
9-20 MD_RAM0 Field Descriptions ............................................................................. 9-29
9-21 MD_RAM1 Field Descriptions ............................................................................. 9-30
9-22 MPC860-Specific MMU Exceptions .................................................................... 9-32
10-1 Instruction Execution Timing................................................................................ 10-6
10-2 Load/Store Instructions Timing............................................................................. 10-7
11-1 Multiplexing Control ............................................................................................. 11-4
11-2 IMMR Field Descriptions...................................................................................... 11-5
11-3 SIUMCR Field Descriptions ................................................................................. 11-6
11-4 SYPCR Field Descriptions .................................................................................... 11-9
11-5 TESR Field Descriptions..................................................................................... 11-10
11-6 Key Registers....................................................................................................... 11-11
11-7 Priority of SIU Interrupt Sources ........................................................................ 11-14
11-8 IRQ0 Versus IRQx Operation .............................................................................11-16
11-9 SIPEND Field Descriptions................................................................................. 11-17
11-10 SIMASK Field Descriptions................................................................................ 11-18
11-11 SIEL Field Descriptions ...................................................................................... 11-19
11-12 SIVEC Field Descriptions ................................................................................... 11-19
11-13 SWSR Field Descriptions.................................................................................... 11-23
11-14 Decrementer Timeout Values.............................................................................. 11-23
11-15 DEC Field Descriptions....................................................................................... 11-24
11-16 TBU Field Descriptions....................................................................................... 11-25
11-17 TBL Field Descriptions ....................................................................................... 11-25
11-18 TBREFA/TBREFB Field Descriptions ............................................................... 11-26
11-19 TBSCR Field Descriptions .................................................................................. 11-26
11-20 RTCSC Field Descriptions .................................................................................. 11-28
11-21 RTC Field Description ........................................................................................ 11-28
11-22 RTCAL Field Descriptions.................................................................................. 11-29
Title
Page
Number
MOTOROLA Contents liii
Page 54
TABLES
Tabl e
Number
11-23 RTSEC Field Descriptions .................................................................................. 11-30
11-24 PISCR Field Descriptions.................................................................................... 11-32
11-25 PITC Field Descriptions ...................................................................................... 11-32
11-26 PITR Field Descriptions ...................................................................................... 11-33
12-1 MPC860 Reset Responses..................................................................................... 12-1
12-2 Reset Status Register Bit Settings ......................................................................... 12-6
12-3 Hard Reset Configuration Word Field Descriptions .............................................12-9
13-1 Signal Descriptions................................................................................................ 13-5
13-2 Active Pull-Up Resistors Enabled as Outputs ..................................................... 13-22
13-3 Signal States during Hardware Reset ..................................................................13-25
14-1 MPC860 Signal Overview..................................................................................... 14-3
14-2 Data Bus Requirements For Read Cycles ........................................................... 14-25
14-3 Data Bus Contents for Write Cycles ................................................................... 14-25
14-4 BURST/TSIZ Encoding ...................................................................................... 14-30
14-5 Address Types Definition.................................................................................... 14-31
14-6 Termination Signals Protocol .............................................................................. 14-41
15-1 Power-On Reset SPLL Configuration ................................................................... 15-7
15-2 XFC Capacitor Values Based on the MF Field ..................................................... 15-8
15-3 Functionality Summary of the Clocks................................................................... 15-9
15-4 PITRTCLK Configuration at PORESET ............................................................ 15-16
15-5 TMBCLK Configuration ..................................................................................... 15-16
15-6 MPC860 Modules vs. Power Rails...................................................................... 15-17
15-7 MPC860 Low-Power Modes............................................................................... 15-19
15-8 SCCR Field Descriptions .................................................................................... 15-27
15-9 PLPRCR Field Descriptions................................................................................ 15-30
15-10 PLPRCR[CSR] and DER[CHSTPE] Bit Combinations ..................................... 15-31
16-1 Memory Controller Register Usage....................................................................... 16-6
16-2 Access Granularities for Predefined Port Sizes..................................................... 16-7
16-3 BRx Field Descriptions ....................................................................................... 16-10
16-4 ORx Field Descriptions ....................................................................................... 16-12
16-5 MSTAT Field Descriptions ................................................................................. 16-13
16-6 MxMR Field Descriptions................................................................................... 16-14
16-7 MCR Field Descriptions...................................................................................... 16-16
16-8 MDR Field Descriptions...................................................................................... 16-17
16-9 MAR Field Description ....................................................................................... 16-17
16-10 MPTPR Field Descriptions.................................................................................. 16-18
16-11 GPCM Strobe Signal Behavior ........................................................................... 16-19
16-12 Boot Bank Field Values after Reset .................................................................... 16-28
16-13 RAM Word Bit Settings ...................................................................................... 16-36
16-14 Enabling Byte-Selects ......................................................................................... 16-40
16-15 GPL_X5 Signal Behavior.................................................................................... 16-41
16-16 MxMR Loop Field Usage.................................................................................... 16-43
16-17 Address Multiplexing .......................................................................................... 16-44
Title
Page
Number
liv MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 55
TABLES
Tabl e
Number
16-18 AMA/AMB Definition for DRAM Interface ......................................................16-45
16-19 UPMA Register Settings ..................................................................................... 16-60
16-20 UPMB Register Settings...................................................................................... 16-71
17-1 PCMCIA Cycle Control Cycles ............................................................................ 17-3
17-2 PCMCIA Input Port Signals.................................................................................. 17-4
17-3 PCMCIA Output Port Signals ............................................................................... 17-5
17-4 Other PCMCIA Signals......................................................................................... 17-5
17-5 Host Programming for Memory Cards.................................................................. 17-6
17-6 Host Programming For I/O Cards ......................................................................... 17-6
17-7 PCMCIA Registers................................................................................................ 17-8
17-8 PIPR Field Descriptions ........................................................................................ 17-8
17-9 PSCR Field Descriptions....................................................................................... 17-9
17-10 PER Field Descriptions ....................................................................................... 17-11
17-11 PGCRx Field Descriptions .................................................................................. 17-12
17-12 PBR Field Descriptions ....................................................................................... 17-13
17-13 POR Field Descriptions....................................................................................... 17-14
18-1 TGCR Field Descriptions ...................................................................................... 18-8
18-2 TMR1ÐTMR4 Field Descriptions ......................................................................... 18-9
18-3 TER Field Descriptions ....................................................................................... 18-11
19-1 Peripheral Prioritization......................................................................................... 19-3
19-2 CP Microcode Revision Number........................................................................... 19-4
19-3 RCCR Field Descriptions ...................................................................................... 19-5
19-4 CPCR Field Descriptions ...................................................................................... 19-6
19-5 CP Command Opcodes.......................................................................................... 19-7
19-6 CP Commands ....................................................................................................... 19-8
19-7 General BD Structure ..........................................................................................19-11
19-8 Parameter RAM Memory Map............................................................................ 19-11
19-9 RISC Timer Table Parameter RAM Memory Map............................................. 19-13
19-10 TM_CMD Field Descriptions.............................................................................. 19-14
19-11 PWM Channel Pin Assignments ......................................................................... 19-16
20-1 U-Bus Arbitration IDs ........................................................................................... 20-2
20-2 SDCR Bit Settings................................................................................................. 20-4
20-3 SDSR Field Descriptions....................................................................................... 20-5
20-4 IDMA Parameter RAM Memory Map .................................................................. 20-6
20-5 DCMR Field Descriptions..................................................................................... 20-8
20-6 IDSR1/IDSR2 Field Descriptions ......................................................................... 20-8
20-7 IDMA BD Status and Control Bits...................................................................... 20-10
20-8 SFCR and DFCR Field Descriptions.................................................................. 20-11
20-9 Single-Buffer Mode IDMA1 Parameter RAM Map ........................................... 20-18
20-10 DCMR Field Descriptions (Single-Buffer Mode)............................................... 20-19
21-1 TSA Signals........................................................................................................... 21-7
21-2 SIRAM Field Descriptions .................................................................................. 21-14
21-3 Example SI RAM Entry Settings for an IDL Bus ............................................... 21-16
Title
Page
Number
MOTOROLA Contents lv
Page 56
TABLES
Tabl e
Number
21-4 SIGMR Field Descriptions .................................................................................. 21-17
21-5 SIMODE Field Descriptions ............................................................................... 21-18
21-6 SICR Field Descriptions...................................................................................... 21-24
21-7 SICMR Field Descriptions .................................................................................. 21-25
21-8 SISTR Field Descriptions.................................................................................... 21-25
21-9 SIRP Field Descriptions ...................................................................................... 21-27
21-10 SIRP Pointer Values ............................................................................................ 21-27
21-11 SI RAM Settings for IDL Interface ..................................................................... 21-31
21-12 SI RAM Settings for GCI Interface (SCIT Mode) .............................................. 21-35
21-13 BRGCn Field Descriptions.................................................................................. 21-40
21-14 Typical Baud Rates for Asynchronous Communication ..................................... 21-42
22-1 GSMR_H Field Descriptions ................................................................................ 22-4
22-2 GSMR_L Field Descriptions................................................................................. 22-7
22-3 TODR Field Descriptions.................................................................................... 22-11
22-4 SCC Parameter RAM Map for All Protocols ...................................................... 22-14
22-5 RFCRx /TFCRx Field Descriptions .................................................................... 22-16
22-6 SCCx Event, Mask, and Status Registers............................................................ 22-17
22-7 Preamble Requirements....................................................................................... 22-24
22-8 DPLL Codings..................................................................................................... 22-25
23-1 UART-Specific SCC Parameter RAM Memory Map........................................... 23-4
23-2 Transmit Commands ............................................................................................. 23-6
23-3 Receive Commands ............................................................................................... 23-6
23-4 Control Character Table, RCCM, and RCCR Descriptions .................................. 23-8
23-5 TOSEQ Field Descriptions.................................................................................. 23-10
23-6 DSR Fields Descriptions ..................................................................................... 23-11
23-7 Transmission Errors............................................................................................. 23-12
23-8 Reception Errors.................................................................................................. 23-12
23-9 PSMR UART Field Descriptions ........................................................................ 23-13
23-10 SCC UART RxBD Status and Control Field Descriptions ................................. 23-17
23-11 SCC UART TxBD Status and Control Field Descriptions ................................. 23-18
23-12 SCCE/SCCM Field Descriptions for UART Mode............................................. 23-21
23-13 UART SCCS Field Descriptions ......................................................................... 23-22
23-14 UART Control Characters for S-Records Example ............................................ 23-24
24-1 HDLC-Specific SCC Parameter RAM Memory Map........................................... 24-4
24-2 Transmit Commands ............................................................................................. 24-5
24-3 Receive Commands ............................................................................................... 24-6
24-4 Transmit Errors...................................................................................................... 24-6
24-5 Receive Errors .......................................................................................................24-6
24-6 PSMR HDLC Field Descriptions .......................................................................... 24-7
24-7 SCC HDLC RxBD Status and Control Field Descriptions ................................... 24-9
24-8 SCC HDLC TxBD Status and Control Field Descriptions ................................. 24-11
24-9 SCCE/SCCM Field Descriptions ........................................................................ 24-12
24-10 HDLC SCCS Field Descriptions ......................................................................... 24-14
Title
Page
Number
lvi MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 57
TABLES
Tabl e
Number
26-1 Asynchronous HDLC-Specific SCC Parameter RAM Memory Map................... 26-5
26-2 Asynchronous HDLC-Specific GSMR Field Descriptions................................... 26-7
26-3 Transmit Commands ............................................................................................. 26-8
26-4 Receive Commands ............................................................................................... 26-8
26-5 Transmit Errors...................................................................................................... 26-8
26-6 Receive Errors .......................................................................................................26-9
26-7 SCCE/SCCM Field Descriptions ........................................................................ 26-10
26-8 Asynchronous HDLC SCCS Field Descriptions................................................. 26-11
26-9 PSMR Field Descriptions .................................................................................... 26-11
26-10 Asynchronous HDLC RxBD Status and Control Field Descriptions.................. 26-12
26-11 Asynchronous HDLC TxBD Status and Control Field Descriptions.................. 26-13
27-1 SCC BISYNC Parameter RAM Memory Map ..................................................... 27-4
27-2 Transmit Commands ............................................................................................. 27-5
27-3 Receive Commands ............................................................................................... 27-5
27-4 Control Character Table and RCCM Field Descriptions ...................................... 27-7
27-5 BSYNC Field Descriptions ................................................................................... 27-8
27-6 BDLE Field Descriptions ...................................................................................... 27-8
27-7 Receiver SYNC Pattern Lengths of the DSR ........................................................ 27-9
27-8 Transmit Errors...................................................................................................... 27-9
27-9 Receive Errors .....................................................................................................27-10
27-10 PSMR Field Descriptions .................................................................................... 27-11
27-11 SCC BISYNC RxBD Status and Control Field Descriptions ............................. 27-12
27-12 SCC BISYNC TxBD Status and Control Field Descriptions.............................. 27-14
27-13 SCCE/SCCM Field Descriptions ........................................................................ 27-16
27-14 SCCS Field Descriptions..................................................................................... 27-17
27-15 Control Characters............................................................................................... 27-18
28-1 SCC Ethernet Parameter RAM Memory Map..................................................... 28-12
28-2 Transmit Commands ........................................................................................... 28-15
28-3 Receive Commands ............................................................................................. 28-15
28-4 Transmission Errors............................................................................................. 28-19
28-5 Reception Errors.................................................................................................. 28-19
28-6 PSMR Field Descriptions .................................................................................... 28-20
28-7 SCC Ethernet Receive RxBD Status and Control Field Descriptions................. 28-21
28-8 SCC Ethernet Receive TxBD Status and Control Field Descriptions................. 28-24
28-9 SCCE/SCCM Field Descriptions ........................................................................ 28-25
29-1 Receiver SYNC Pattern Lengths of the DSR ........................................................ 29-3
29-2 SCC Transparent Parameter RAM Memory Map ................................................. 29-7
29-3 Transmit Commands ............................................................................................. 29-7
29-4 Receive Commands ............................................................................................... 29-8
29-5 Transmit Errors...................................................................................................... 29-8
29-6 Receive Errors .......................................................................................................29-8
29-7 SCC Transparent RxBD Status and Control Field Descriptions ........................... 29-9
29-8 SCC Transparent Tx BD Status and Control Field Descriptions ........................29-11
Title
Page
Number
MOTOROLA Contents lvii
Page 58
TABLES
Tabl e
Number
Title
Page
Number
29-9 SCCE/SCCM Field Descriptions ........................................................................ 29-12
29-10 SCCS Field Descriptions..................................................................................... 29-13
30-1 SMCMR Field Descriptions .................................................................................. 30-3
30-2 SMC UART and Transparent Parameter RAM Memory Map ............................. 30-6
30-3 RFCR/TFCR Field Descriptions ........................................................................... 30-7
30-4 SMC UART-Specific Parameter RAM Memory Map........................................ 30-10
30-5 Transmit Commands ........................................................................................... 30-12
30-6 Receive Commands ............................................................................................. 30-12
30-7 SMC UART Errors.............................................................................................. 30-13
30-8 SMC UART RxBD Status and Control Field Descriptions ................................ 30-14
30-9 SMC UART TxBD Status and Control Field Descriptions................................. 30-17
30-10 SMCE/SMCM Field Descriptions....................................................................... 30-18
30-11 SMC Transparent-Specific Parameter RAM Memory Map................................ 30-21
30-12 SMC Transparent Transmit Commands.............................................................. 30-25
30-13 SMC Transparent Receive Commands ............................................................... 30-26
30-14 SMC Transparent Error Conditions..................................................................... 30-26
30-15 SMC Transparent RxBD Field Descriptions....................................................... 30-27
30-16 SMC Transparent TxBD Field Descriptions ....................................................... 30-28
30-17 SMCE/SMCM Field Descriptions....................................................................... 30-29
30-18 SMC GCI Parameter RAM Memory Map .......................................................... 30-32
30-19 SMC GCI Commands.......................................................................................... 30-33
30-20 SMC Monitor Channel RxBD Field Descriptions............................................... 30-34
30-21 SMC Monitor Channel TxBD Field Descriptions............................................... 30-34
30-22 SMC C/I Channel RxBD Field Descriptions....................................................... 30-35
30-23 SMC C/I Channel TxBD Field Descriptions....................................................... 30-35
30-24 SMCE/SMCM Field Descriptions....................................................................... 30-36
31-1 SPMODE Field Descriptions ................................................................................ 31-7
31-2 Example Conventions............................................................................................ 31-9
31-3 SPIE/SPIM Field Descriptions ............................................................................ 31-10
31-4 SPCOM Field Descriptions ................................................................................. 31-11
31-5 SPI Parameter RAM Memory Map..................................................................... 31-11
31-6 RFCR/TFCR Field Descriptions ......................................................................... 31-12
31-7 SPI Commands .................................................................................................... 31-13
31-8 SPI RxBD Status and Control Field Descriptions............................................... 31-15
31-9 SPI TxBD Status and Control Field Descriptions ............................................... 31-16
32-1 I2MOD Field Descriptions .................................................................................... 32-6
32-2 I2ADD Field Descriptions..................................................................................... 32-7
32-3 I2BRG Field Descriptions ..................................................................................... 32-8
32-4 I2CER/I2CMR Field Descriptions ........................................................................ 32-8
32-5 I2COM Field Descriptions .................................................................................... 32-9
32-6 I
32-7 RFCR/TFCR Field Descriptions ......................................................................... 32-11
32-8 I
2
C Parameter RAM Memory Map ....................................................................... 32-9
2
C Transmit/Receive Commands....................................................................... 32-11
lviii MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 59
TABLES
Tabl e
Number
32-9 I2C RxBD Status and Control Bits...................................................................... 32-13
32-10 I2C TxBD Status and Control Bits...................................................................... 32-14
33-1 PIP Transmitter Parameter RAM Memory Map ...................................................33-3
33-2 PFCR Field Descriptions....................................................................................... 33-4
33-3 SMASK Field Descriptions................................................................................... 33-5
33-4 PIP Receiver Parameter RAM Memory Map........................................................ 33-5
33-5 Control Character Table, RCCM, and RCCR Descriptions .................................. 33-7
33-6 PIPC Field Descriptions ........................................................................................ 33-8
33-7 PIPE Field Descriptions ........................................................................................ 33-9
33-8 PTPR Field Descriptions ..................................................................................... 33-10
33-9 PIP TxBD Status and Control Field Descriptions ............................................... 33-12
33-10 PIP RxBD Status and Control Field Descriptions............................................... 33-13
33-11 PIP Transmit CP Commands............................................................................... 33-14
33-12 PIP Receive CP Commands ................................................................................ 33-14
33-13 Centronics Tx Errors ........................................................................................... 33-21
33-14 Centronics Rx Error............................................................................................. 33-22
34-1 Port A Pin Assignment .......................................................................................... 34-2
34-2 PAODR Bit Descriptions ...................................................................................... 34-4
34-3 PADAT Bit Descriptions....................................................................................... 34-4
34-4 PADIR Bit Descriptions ........................................................................................ 34-5
34-5 PAPAR Bit Descriptions ....................................................................................... 34-5
34-6 Port B Pin Assignment .......................................................................................... 34-8
34-7 PBODR Bit Descriptions..................................................................................... 34-10
34-8 PBDAT Bit Descriptions..................................................................................... 34-10
34-9 PBDIR Bit Descriptions ...................................................................................... 34-11
34-10 PBPAR Bit Descriptions ..................................................................................... 34-12
34-11 Port C Pin Assignment ........................................................................................ 34-12
34-12 PCDAT Bit Descriptions..................................................................................... 34-15
34-13 PCDIR Bit Descriptions ...................................................................................... 34-15
34-14 PCPAR Bit Descriptions ..................................................................................... 34-16
34-15 PCSO Bit Descriptions ........................................................................................ 34-16
34-16 PCINT Bit Descriptions ...................................................................................... 34-17
34-17 Port D Pin Assignment ........................................................................................ 34-18
34-18 PDDAT Bit Descriptions..................................................................................... 34-19
34-19 PDDIR Bit Descriptions ...................................................................................... 34-19
34-20 PDPAR Bit Descriptions ..................................................................................... 34-20
35-1 Prioritization of CPM Interrupt Sources................................................................ 35-3
35-2 Interrupt Vector Encodings ................................................................................... 35-6
35-3 CICR Field Descriptions ....................................................................................... 35-7
35-4 CIVR Field Descriptions ..................................................................................... 35-10
36-1 DSP Library Functions .......................................................................................... 36-2
36-2 FD Status and Control Bits.................................................................................... 36-4
36-3 DSPx Parameter RAM Memory Map ................................................................... 36-6
Title
Page
Number
MOTOROLA Contents lix
Page 60
TABLES
Tabl e
Number
36-4 DSP Opcodes......................................................................................................... 36-6
36-5 SDSR/SDMR Field Descriptions .......................................................................... 36-7
36-6 FIR Parameter Packet ............................................................................................ 36-8
36-7 FIR1 Coefficient, Input, and Output Buffers......................................................... 36-9
36-8 FIR1 Parameter Packet .......................................................................................... 36-9
36-9 FIR2 Coefficient, Input, and Output Buffers....................................................... 36-11
36-10 FIR2 Parameter Packet ........................................................................................ 36-12
36-11 FIR3 Coefficient, Input, and Output Buffers....................................................... 36-13
36-12 FIR3 Parameter Packet ........................................................................................ 36-14
36-13 FIR5 Coefficient, Input, and Output Buffers....................................................... 36-15
36-14 FIR5 Parameter Packet ........................................................................................ 36-16
36-15 FIR6 Coefficient, Input, and Output Buffers....................................................... 36-18
36-16 FIR6 Parameter Packet ........................................................................................ 36-18
36-17 IIR Coefficient, Input, and Output Buffers ......................................................... 36-20
36-18 IIR Parameter Packet........................................................................................... 36-20
36-19 MOD Table, Input, and Output Buffers .............................................................. 36-21
36-20 MOD Parameter Packet....................................................................................... 36-22
36-21 DEMOD Modulation Table, Input, and Output Buffers ..................................... 36-23
36-22 DEMOD Parameter Packet.................................................................................. 36-24
36-23 LMS1 Coefficients and Input Buffers ................................................................. 36-25
36-24 DEMOD Parameter Packet.................................................................................. 36-26
36-25 LMS2 Coefficients and Input Buffers ................................................................. 36-27
36-26 LMS2 Parameter Packet ...................................................................................... 36-28
36-27 WADD Modulation Table and Sample Data Buffers.......................................... 36-29
36-28 WADD Parameter Packet.................................................................................... 36-29
36-29 WADD Applications ...........................................................................................36-30
36-30 DSP Function Execution Times .......................................................................... 36-33
37-1 Fetch Show Cycles Control ................................................................................... 37-3
37-2 Status Pin Groupings ............................................................................................. 37-3
37-3 VF Pins Encoding: Instruction Queue Flushes...................................................... 37-4
37-4 VF Pins Encoding: Instruction Fetch Types.......................................................... 37-4
37-5 Detecting the Trace Buffer Start Point .................................................................. 37-7
37-6 Instruction Watchpoints Programming Options.................................................. 37-12
37-7 Load/Store Data Events....................................................................................... 37-14
37-8 Load/Store Watchpoints Programming Options ................................................. 37-14
37-9 Checkstop State and Debug Mode ...................................................................... 37-24
37-10 Trap Enable Data Shifted into Development Port Shift Register........................ 37-31
37-11 Debug Port Command Shifted Into Development Port Shift Register................ 37-31
37-12 Status/Data Shifted Out of Development Port Shift Register ............................. 37-32
37-13 Debug Instructions/Data Shifted Into Development Port Shift Register............. 37-33
37-14 MPC860-Specific Development Support and Debug SPRs................................ 37-36
37-15 Development Support/Debug Registers Protection............................................. 37-37
37-16 CMPAÐCMPD Field Descriptions ...................................................................... 37-37
Title
Page
Number
lx MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 61
TABLES
Tabl e
Number
37-17 CMPEÐCMPF Field Descriptions ....................................................................... 37-38
37-18 CMPGÐCMPH Field Descriptions ...................................................................... 37-38
37-19 BAR Field Descriptions ...................................................................................... 37-39
37-20 ICTRL Field Descriptions ................................................................................... 37-39
37-21 LCTRL1 Field Descriptions ................................................................................ 37-41
37-22 LCTRL2 Field Descriptions ................................................................................ 37-42
37-23 COUNTA/COUNTB Field Descriptions ............................................................ 37-44
37-24 ICR Field Descriptions ........................................................................................ 37-45
37-25 DER Field Descriptions....................................................................................... 37-46
38-1 Instruction Register Decoding............................................................................... 38-6
A-1 Byte-Ordering Parameters ...................................................................................... A-2
A-2 TLE 2-bit Munging................................................................................................. A-3
A-3 Little-Endian Program/Data Path Between the Register and 32-Bit Memory ....... A-5
A-4 Little-Endian Program/Data Path Between the Register and 16-Bit Memory ....... A-5
A-5 Little-Endian Program/Data Path between the Register and 8-Bit Memory.......... A-6
A-6 PPC-LE 3-bit Munging........................................................................................... A-7
B-1 MPC860/MPC860MH Serial Performance at 25 MHz ...........................................B-4
B-2 IDMA Performance at 25 MHz ...............................................................................B-5
C-1 User-Level PowerPC Registers ...............................................................................C-1
C-2 User-Level PowerPC SPRs .....................................................................................C-1
C-3 Supervisor-Level PowerPC Registers .....................................................................C-2
C-4 Supervisor-Level PowerPC SPRs............................................................................C-2
C-5 MPC860-Specific Supervisor-Level SPRs ..............................................................C-3
C-6 MPC860-Specific Debug-Level SPRs ....................................................................C-4
D-1 Complete Instruction List Sorted by Mnemonic .................................................... D-1
D-2 Complete Instruction List Sorted by Opcode ......................................................... D-9
D-3 Integer Arithmetic Instructions............................................................................. D-17
D-4 Integer Compare Instructions ............................................................................... D-18
D-5 Integer Logical Instructions.................................................................................. D-18
D-6 Integer Rotate Instructions ................................................................................... D-18
D-7 Integer Shift Instructions ...................................................................................... D-19
D-8 Floating-Point Arithmetic Instructions6............................................................... D-19
D-9 Floating-Point Multiply-Add Instructions6.......................................................... D-20
D-10 Floating-Point Rounding and Conversion Instructions6 ...................................... D-20
D-11 Floating-Point Compare Instructions6 ................................................................. D-20
D-12 Floating-Point Status and Control Register Instructions6 .................................... D-20
D-13 Integer Load Instructions...................................................................................... D-21
D-14 Integer Store Instructions ..................................................................................... D-22
D-15 Integer Load and Store with Byte-Reverse Instructions....................................... D-22
D-16 Integer Load and Store Multiple Instructions....................................................... D-22
D-17 Integer Load and Store String Instructions........................................................... D-23
D-18 Memory Synchronization Instructions ................................................................. D-23
D-19 Floating-Point Load Instructions6........................................................................ D-23
Title
Page
Number
MOTOROLA Contents lxi
Page 62
TABLES
Tabl e
Number
D-20 Floating-Point Store Instructions6........................................................................ D-24
D-21 Floating-Point Move Instructions6....................................................................... D-24
D-22 Branch Instructions............................................................................................... D-24
D-23 Condition Register Logical Instructions............................................................... D-24
D-24 System Linkage Instructions ................................................................................ D-25
D-25 Trap Instructions................................................................................................... D-25
D-26 Processor Control Instructions ............................................................................. D-25
D-27 Cache Management Instructions .......................................................................... D-26
D-28 Segment Register Manipulation Instructions ....................................................... D-26
D-29 Lookaside Buffer Management Instructions ........................................................ D-26
D-30 External Control Instructions ............................................................................... D-26
D-31 I-Form................................................................................................................... D-27
D-32 B-Form ................................................................................................................. D-27
D-33 SC-Form ............................................................................................................... D-27
D-34 D-Form ................................................................................................................. D-27
D-35 DS-Form ............................................................................................................... D-29
D-36 X-Form ................................................................................................................. D-29
D-37 XL-Form............................................................................................................... D-33
D-38 XFX-Form ............................................................................................................ D-34
D-39 XFL-Form............................................................................................................. D-34
D-40 XS-Form ............................................................................................................... D-34
D-41 XO-Form .............................................................................................................. D-34
D-42 A-Form ................................................................................................................. D-35
D-43 M-Form................................................................................................................. D-36
D-44 MD-Form.............................................................................................................. D-36
D-45 MDS-Form ........................................................................................................... D-37
D-46 Instruction Set Legend.......................................................................................... D-38
Title
Page
Number
lxii MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 63
About This Book
The primary objective of this manual is to help communications system designers build
systems using the Motorola MPC860 and to help software designers provide operating
systems and user-level applications to take fullest advantage of the MPC860.
Although this book describes aspects regarding the PowerPCª architecture that are critical
for understanding the MPC860 core, it does not contain a complete description of the
architecture. Where additional information might help the reader, references are made to
The PowerPC Microprocessor Family: The Programming Environments. Ordering
information for this book are provided in the section, ÒPowerPC Documentation.Ó
The information in this book is subject to change without notice, as described in the
disclaimers on the title page of this book. As with any technical documentation, it is the
readersÕ responsibility to be sure they are using the most recent version of the
documentation. For more information, contact your sales representative.
Before Using this Manual
Before using this manual, determine whether it is the latest revision and if there are errata
or addenda. To locate any published errata or updates for this document, refer to the worldwide web at http://www.motorola.com/SPS/RISC/netcomm.
Audience
This manual is intended for software and hardware developers and application
programmers who want to develop products for the MPC860. It is assumed that the reader
has a basic understanding of computer networking, OSI layers, and RISC architecture. In
addition, it is assumed that the reader has a basic understanding of the communications
protocols described here. Where it is considered useful, additional sources are provided that
provide in-depth discussions of such topics.
MOTOROLA About This Book lxiii
Page 64
Organization
Following is a summary and a brief description of the chapters of this manual:
¥ Part I, ÒOverview,Ó provides a high-level description of the MPC860, describing
general operation and listing basic features.
Ñ Chapter 1, ÒMPC860 Overview, Ó provides a high-level description of MPC860
functions and features. It roughly follows the structure of this book, summarizing
the relevant features and providing references for the reader who needs
additional information.
Ñ Chapter 2, ÒMemory Map,Ó presents a table showing where MPC860 registers
are mapped in memory. It includes cross references that indicate where the
registers are described in detail.
Ñ Chapter 3, ÒHardware Interface Overview,Ó provides an MPC860 pinout
diagram and signal listing.
¥ Part II, ÒPowerPC Microprocessor Module,Ó describes the PowerPC microprocessor
core embedded in the MPC860. These chapters provide details concerning the
processor core as an implementation of the PowerPC architecture.
Ñ Chapter 4, ÒThe PowerPC Core,Ó provides an overview of the MPC860 core,
summarizing topics described in further detail in subsequent chapters in Part II.
Ñ Chapter 5, ÒPowerPC Core Register Set,Ó describes the hardware registers
accessible to the MPC860 core. These include both architecturally-deÞned and
MPC860-speciÞc registers.
Ñ Chapter 6, ÒMPC860 Instruction Set,Ó describes the PowerPC instructions
implemented on the MPC860, including MPC860-speciÞc features.
Ñ Chapter 7, ÒExceptions,Ó describes the PowerPC exception model as it is
implemented on the MPC860.
Ñ Chapter 8, ÒInstruction and Data Caches,Ó describes the organization of the on-
chip instruction and data caches, cache control, various cache operations, and the
interaction between the caches, the load/store unit (LSU), the instruction
sequencer, and the system interface unit (SIU).
Ñ Chapter 9, ÒMemory Management Unit (MMU)Ó describes how the PowerPC
MMU model is implemented on the MPC860. Although the MPC860 MMU is
based on the PowerPC MMU model, it differs greatly in many respects, which
are described in this chapter.
Ñ Chapter 10, ÒInstruction Execution Timing,Ó describes the MPC860 instruction
unit, and provides ways to make greatest advantage of its RISC architecture
characteristics, such as pipelining and parallel execution. It includes a table of
instruction latencies and lists dependencies and potential bottlenecks.
lxiv MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 65
¥ Part III, ÒConÞguration,Ó describes start-up behavior of the MPC860.
Ñ Chapter 11, ÒSystem Interface Unit,Ó describes the SIU, which controls system
start-up, initialization and operation, protection, as well as the external system
bus.
Ñ Chapter 12, ÒReset,Ó describes the behavior of the MPC860 at reset and start-up.
¥ Part IV, ÒHardware Interface,Ó descibes external signals, clocking, memory control,
and power management of the MPC860.
Ñ Chapter 13, ÒExternal Signals,Ó provides a detailed description of the external
signals that comprise the MPC860 external interface.
Ñ Chapter 14, ÒMPC860 External Bus Interface,Ó describes the interaction
between signals described in the previous chapter, including numerous examples
and timing diagrams.
Ñ Chapter 15, ÒClocks and Power Control,Ó describes on-chip and external
devices, including the phase-locked loop circuitry and frequency dividers that
generate programmable clock timing for baud-rate generators, timers, and a
variety of low-power mode options.
Ñ Chapter 16, ÒMemory Controller,Ó describes the memory controller, which
controlling a maximum of eight memory banks shared between a generalpurpose chip-select machine (GPCM) and a pair of user-programmable
machines (UPMs).
Ñ Chapter 17, ÒPCMCIA Interface,Ó describes the PCMCIA host adapter module,
which provides all control logic for a PCMCIA socket interface and requires
only additional external analog power switching logic and buffering.
¥ Part V, ÒThe Communications Processor Module,Ó describes the conÞguration,
clocking, and operation of the various communications protocols supported by the
MPC860.
Ñ Chapter 18, ÒCommunications Processor Module and CPM Timers,Ó provides a
brief overview of the MPC860 CPM and a detailed discussion of the clocking
mechanisms supported.
Ñ Chapter 19, ÒCommunications Processor,Ó describes the RISC communications
processor (CP), which handles the low-level communications tasks, freeing the
core for higher-level tasks.
Ñ Chapter 20, ÒSDMA Channels and IDMA Emulation,Ó describes the two
physical serial DMA (SDMA) channels on the MPC860 with which the CP
implements sixteen virtual SDMA channels.
Ñ Chapter 21, ÒSerial Interface,Ó describes the serial interface (SI) in which the
physical interface to all SCCs and SMCs is implemented.
MOTOROLA About This Book lxv
Page 66
Ñ Chapter 22, ÒSerial Communications Controllers,Ó describes the four serial
communications controllers (SCC), which can be conÞgured independently to
implement different protocols for bridging functions, routers, and gateways, and
to interface with a wide variety of standard WANs, LANs, and proprietary
networks.
Ñ Chapter 23, ÒSCC UART Mode,Ó describes the MPC860 implementation of
universal asynchronous receiver transmitter (UART) protocol, used for sending
low-speed data between devices.
Ñ Chapter 24, ÒSCC HDLC Mode,Ó describes the MPC860 implementation of
HDLC protocol.
Ñ Chapter 25, ÒSCC AppleTalk Mode,Ó describes the MPC860 implementation of
AppleTalk, a set of protocols developed by Apple Computer, Inc. to provide a
LAN service between Macintosh computers and printers.
Ñ Chapter 26, ÒSCC Asynchronous HDLC Mode and IrDA,Ó describes the
asynchronous HDLC and IrDA use of HDLC framing techniques with UARTtype characters.
Ñ Chapter 27, ÒSCC BISYNC Mode,Ó describes the MPC860 implementation of
byte-oriented BISYNC protocol developed by IBM for use in networking
products.
Ñ Chapter 28, ÒSCC Ethernet Mode,Ó describes the MPC860 implementation of
Ethernet protocol.
Ñ Chapter 29, ÒSCC Transparent Mode,Ó describes the MPC860 implementation of
transparent mode (also called totally transparent mode), which provides a clear
channel on which the SCC can send or receive serial data without bit-level
manipulation.
Ñ Chapter 30, ÒSerial Management Controllers,Ó describes two serial management
controllers, full-duplex ports that can be conÞgured independently to support one
of three protocolsÑUART, transparent, or general-circuit interface (GCI).
Ñ Chapter 31, ÒSerial Peripheral Interface,Ó describes the serial peripheral
interface, which allows the MPC860 to exchange data between other MPC860
chips, the MC68360, the MC68302, the M68HC11 and M68HC05
microcontroller families, and peripheral devices such as EEPROMs, real-time
clocks, A/D converters, and ISDN devices.
Ñ Chapter 32, ÒI2C Controller,Ó describes the MPC860 implementation of the
inter-integrated circuit (I
2
other I
C devices, such as microcontrollers, EEPROMs, real-time clock devices,
2
C¨) controller, which allows data to be exchanged with
and A/D converters.
Ñ Chapter 33, ÒParallel Interface Port,Ó describes the MPC860 implementation of
the parallel interface port, which is multiplexed through the 18-bit port B parallel
I/O and allows data to be sent to and from the MPC860 over 8 or 16 parallel data
lines with two handshake control signals.
Ñ Chapter 34, ÒParallel I/O Ports,Ó describes the four general-purpose I/O
lxvi MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 67
portsÑA, B, C, and D. Each signal in the I/O ports can be conÞgured as a
general-purpose I/O signal or as a signal dedicated to supporting
communications devices, such as SMCs and SCCs.
Ñ Chapter 35, ÒCPM Interrupt Controller,Ó describes how the CPM interrupt
controller (CPIC) accepts and prioritizes the internal and external interrupt
requests from the CPM blocks and passes them to the system interface unit
(SIU). The CPIC also provides a vector during the core interrupt acknowledge
cycle.
Ñ Chapter 36, ÒDigital Signal Processing,Ó describes the CPMÕs hardware and
library functions that support DSP applications.
¥ Part VI, ÒDebug and Test,Ó describes how to use the MPC860 facilities for
debugging and system testing.
Ñ Chapter 37, ÒSystem Development and Debugging,Ó describes support provided
for program ßow tracking, internal watchpoint and breakpoint generation, and
emulation systems control.
Ñ Chapter 38, ÒIEEE 1149.1 Test Access Port,Ó describes the dedicated user-
accessible test access port (TAP), which is fully compatible with the IEEE
1149.1 Standard Test Access Port and Boundary Scan Architecture.
¥ Appendix A, ÒByte Ordering,Ó discusses the MPC860 implementation of little- and
big-endian byte mapping.
¥ Appendix B, ÒSerial Communications Performance,Óprovides insight in
maximizing performance of MPC860-based systems.
¥ Appendix C, ÒRegister Quick Reference Guide,Ó contains a quick reference guide to
the MPC860 registers.
¥ Appendix D, ÒMPC860 Instruction Set Listings,Ó contains tables of the PowerPC
instructions supported by the MPC860.
¥ This manual also includes a glossary and an index.
MOTOROLA About This Book lxvii
Page 68
Suggested Reading
This section lists additional reading that provides background for the information in this
manual as well as general information about the PowerPC architecture.
MPC8xx Documentation
Supporting documentation for the MPC860 can be accessed through the world-wide web
at http://www.motorola.com/SPS/RISC/netcomm. This documentation includes technical
speciÞcations, reference materials, and detailed applications notes.
PowerPC Documentation
The PowerPC documentation is organized in the following types of documents:
¥ UserÕs manualsÑThese books provide details about individual PowerPC
implementations and are intended to be used in conjunction with The Programming
Environments Manual. These include the following:
Ñ PowerPC 603eª RISC Microprocessor UserÕs Manual with Supplement for
PowerPC 603ª Microprocessor (Motorola order #: MPC603EUM/AD)
Ñ PowerPC 604ª RISC Microprocessor UserÕs Manual
(Motorola order #: MPC604UM/AD)
¥ Programming environments manualsÑThese books provide information about
resources deÞned by the PowerPC architecture that are common to PowerPC
processors. There are two versions, one that describes the functionality of the
combined 32- and 64-bit architecture models and one that describes only the 32-bit
model.
Ñ PowerPC Microprocessor Family: The Programming Environments, Rev 1
(Motorola order #: MPCFPE/AD)
Ñ PowerPC Microprocessor Family: The Programming Environments for 32-Bit
Microprocessors, Rev. 1 (Motorola order #: MPCFPE32B/AD)
¥ PowerPC Microprocessor Family: The Bus Interface for 32-Bit Microprocessors
(Motorola order #: MPCBUSIF/AD) provides a detailed functional description of
the 60x bus interface, as implemented on the PowerPC 601ª, 603, and 604 family
of PowerPC microprocessors. This document is intended to help system and chip set
developers by providing a centralized reference source to identify the bus interface
presented by the 60x family of PowerPC microprocessors.
¥ PowerPC Microprocessor Family: The ProgrammerÕs Reference Guide
(Motorola order #: MPCPRG/D) is a concise reference that includes the register
summary, memory control model, exception vectors, and the PowerPC instruction
set.
¥ PowerPC Microprocessor Family: The ProgrammerÕs Pocket Reference Guide
(Motorola order #: MPCPRGREF/D). This feedlot card provides an overview of the
PowerPC registers, instructions, and exceptions for 32-bit implementations.
lxviii MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 69
¥ Application notesÑThese short documents contain useful information about
speciÞc design issues useful to programmers and engineers working with PowerPC
processors.
For a current list of PowerPC documentation, refer to the world-wide web at
http://www.mot.com/SPS/PowerPC/.
Conventions
This document uses the following notational conventions:
Bold
Bold entries in Þgures and tables showing registers and parameter
RAM should be initialized by the user.
mnemonics Instruction mnemonics are shown in lowercase bold.
italics Italics indicate variable command parameters, for example, bcctrx.
Book titles in text are set in italics.
0x0 PreÞx to denote hexadecimal number
0b0 PreÞx to denote binary number
rA, rB Instruction syntax used to identify a source GPR
rD Instruction syntax used to identify a destination GPR
REG[FIELD] Abbreviations or acronyms for registers or buffer descriptors are
shown in uppercase text. SpeciÞc bits, Þelds, or numerical ranges
appear in brackets. For example, MSR[LE] refers to the little-endian
mode enable bit in the machine state register.
x In certain contexts, such as in a signal encoding or a bit Þeld,
indicates a donÕt care.
n Used to express an undeÞned numerical value
 NOT logical operator
& AND logical operator
| OR logical operator
MOTOROLA About This Book lxix
Page 70
Acronyms and Abbreviations
Table i contains acronyms and abbreviations used in this document. Note that the meanings
for some acronyms (such as SDR1 and DSISR) are historical, and the words for which an
acronym stands may not be intuitively obvious.
Table i. Acronyms and Abbreviated Terms
Term Meaning
A/D Analog-to-digital
ALU Arithmetic logic unit
ATM Asynchronous transfer mode
BD Buffer descriptor
BIST Built-in self test
BPU Branch processing unit
BRI Basic rate interface.
BUID Bus unit ID
CAM Content-addressable memory
CEPT Conference des administrations Europeanes des Postes et Telecommunications (European
CPM Communication processor module
CR Condition register
CRC Cyclic redundancy check
CTR Count register
DABR Data address breakpoint register
DAR Data address register
DEC Decrementer register
DMA Direct memory access
DPLL Digital phase-locked loop
DRAM Dynamic random access memory
DSISR Register used for determining the source of a DSI exception
DSP Digital signal processing
DTLB Data translation lookaside buffer
EA Effective address
EEST Enhanced Ethernet serial transceiver
EPROM Erasable programmable read-only memory
FPR Floating-point register
FPSCR Floating-point status and control register
Conference of Postal and Telecommunications Administrations).
lxx MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 71
Table i. Acronyms and Abbreviated Terms (Continued)
Term Meaning
FPU Floating-point unit
GCI General circuit interface
GPCM General-purpose chip-select machine
GPR General-purpose register
GUI Graphical user interface
HDLC High-level data link control
2
I
C Inter-integrated circuit
IDL Inter-chip digital link
IEEE Institute of Electrical and Electronics Engineers
IrDA Infrared Data Association
ISDN Integrated services digital network
ITLB Instruction translation lookaside buffer
IU Integer unit
JTAG Joint Test Action Group
LIFO Last-in-Þrst-out
LR Link register
LRU Least recently used
LSB Least-signiÞcant byte
lsb Least-signiÞcant bit
LSU Load/store unit
MAC Multiply accumulate
MESI ModiÞed/exclusive/shared/invalidÑcache coherency protocol
MMU Memory management unit
MSB Most-signiÞcant byte
msb Most-signiÞcant bit
MSR Machine state register
NaN Not a number
NIA Next instruction address
NMSI Nonmultiplexed serial interface
No-op No operation
OEA Operating environment architecture
OSI Open systems interconnection
MOTOROLA About This Book lxxi
Page 72
Table i. Acronyms and Abbreviated Terms (Continued)
Term Meaning
PCI Peripheral component interconnect
PCMCIA Personal Computer Memory Card International Association
PIR Processor identiÞcation register
PRI Primary rate interface
PVR Processor version register
RISC Reduced instruction set computing
RTOS Real-time operating system
RWITM Read with intent to modify
Rx Receive
SCC Serial communication controller
SCP Serial control port
SDLC Synchronous Data Link Control
SDMA Serial DMA
SI Serial interface
SIMM Signed immediate value
SIU System interface unit
SMC Serial management controller
SNA Systems network architecture
SPI Serial peripheral interface
SPR Special-purpose register
SPRGn Registers available for general purposes
SRAM Static random access memory
SRR0 Machine status save/restore register 0
SRR1 Machine status save/restore register 1
TAP Test access port
TB Time base register
TDM Time-division multiplexed
TLB Translation lookaside buffer
TSA Time-slot assigner
Tx Transmit
UART Universal asynchronous receiver/transmitter
UIMM Unsigned immediate value
lxxii MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 73
Table i. Acronyms and Abbreviated Terms (Continued)
Term Meaning
UISA User instruction set architecture
UPM User-programmable machine
USART Universal synchronous/asynchronous receiver/transmitter
VA Virtual address
VEA Vir tual environment architecture
XER Register used primarily for indicating conditions such as carries and overßows for integer operations
PowerPC Architecture Terminology Conventions
Table ii lists certain terms used in this manual that differ from the architecture terminology
conventions.
Table ii. Terminology Conventions
The Architecture SpeciÞcation This Manual
Data storage interrupt (DSI) DSI exception
Extended mnemonics SimpliÞed mnemonics
Instruction storage interrupt (ISI) ISI exception
Interrupt Exception
Privileged mode (or privileged state) Supervisor-level privilege
Problem mode (or problem state) User-level privilege
Real address Physical address
Relocation Translation
Storage (locations) Memory
Storage (the act of) Access
MOTOROLA About This Book lxxiii
Page 74
Table iii describes instruction Þeld notation conventions used in this manual.
Table iii. Instruction Field Conventions
The Architecture SpeciÞcation Equivalent to:
BA, BB, BT crbA, crbB, crbD (respectively)
BF, BFA crfD, crfS (respectively)
Dd
DS ds
FLM FM
FXM CRM
RA, RB, RT, RS rA, rB, rD, r S (respectively)
SI SIMM
U IMM
UI UIMM
/, //, /// 0...0 (shaded)
lxxiv MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 75
Part I
Overview
Intended Audience
Part I is intended for anyone who needs a high-level understanding of the MPC860.
Contents
Part I provides an overview of the features and functions of the MPC860.
It includes the following chapters:
¥ Chapter 1, ÒMPC860 Overview, Ó provides a high-level description of MPC860
functions and features. It roughly follows the structure of this book, summarizing the
relevant features and providing references for the reader who needs additional
information.
¥ Chapter 2, ÒMemory Map,Ó presents a table showing where MPC860 registers are
mapped in memory. It includes cross references that indicate where the registers are
described in detail.
¥ Chapter 3, ÒHardware Interface Overview,Ó provides an MPC860 pinout diagram
and signal listing.
Conventions
Part I uses the following notational conventions:
mnemonics Instruction mnemonics are shown in lowercase bold.
italics Italics indicate variable command parameters, for example, bcctrx.
Book titles in text are set in italics.
0x0 PreÞx to denote hexadecimal number
0b0 PreÞx to denote binary number
rA, rB Instruction syntax used to identify a source GPR
rD Instruction syntax used to identify a destination GPR
MOTOROLA Part I. Overview I-i
Page 76
Part I. Overview
REG[FIELD] Abbreviations or acronyms for registers or buffer descriptors are
shown in uppercase text. SpeciÞc bits, Þelds, or numerical ranges
appear in brackets. For example, MSR[LE] refers to the little-endian
mode enable bit in the machine state register.
x In certain contexts, such as in a signal encoding or a bit Þeld,
indicates a donÕt care.
n Indicates an undeÞned numerical value
Acronyms and Abbreviations
Table i contains acronyms and abbreviations that are used in this document.
Table iv. Acronyms and Abbreviated Terms
Term Meaning
BD Buffer descriptor
BPU Branch processing unit
CPM Communications processor module
DMA Direct memory access
DPLL Digital phase-locked loop
DRAM Dynamic random access memory
DSP Digital signal processing
DTLB Data translation lookaside buffer
EA Effective address
GPCM General-purpose chip-select machine
GPR General-purpose register
HDLC High-level data link control
2
I
C Inter-integrated circuit
IEEE Institute of Electrical and Electronics Engineers
IrDA Infrared Data Association
ISDN Integrated services digital network
ITLB Instruction translation lookaside buffer
IU Integer unit
JTAG Joint Test Action Group
LRU Least recently used (cache replacement algorithm)
LSU Load/store unit
MMU Memory management unit
MSR Machine state register
I-ii MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 77
Table iv. Acronyms and Abbreviated Terms (Continued)
Term Meaning
NMSI Nonmultiplexed serial interface
OEA Operating environment architecture
OSI Open systems interconnection
PCI Peripheral component interconnect
PCMCIA Personal Computer Memory Card International Association
RISC Reduced instruction set computing
RTOS Real-time operating system
Rx Receive
SCC Serial communication controller
SDLC Synchronous Data Link Control
SDMA Serial DMA
SI Serial interface
SIU System interface unit
SMC Serial management controller
SPI Serial peripheral interface
SPR Special-purpose register
SRAM Static random access memory
TB Time base register
TDM Time-division multiplexed
TLB Translation lookaside buffer
TSA Time-slot assigner
Tx Transmit
UART Universal asynchronous receiver/transmitter
UISA User instruction set architecture
UPM User-programmable machine
VEA Vir tual environment architecture
Part I. Overview
MOTOROLA Part I. Overview I-iii
Page 78
Part I. Overview
I-iv MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 79
Chapter 1
MPC860 Overview
10
10
The MPC860 PowerPCª Quad Integrated Communications Controller (PowerQUICCª)
is a versatile one-chip integrated microprocessor and peripheral combination that can be
used in a variety of controller applications. It particularly excels in both communications
and networking systems. Unless otherwise speciÞed, the PowerQUICC unit is referred to
as the MPC860 in this manual.
The MPC860 is a PowerPC architecture-based derivative of MotorolaÕs MC68360 Quad
Integrated Communications Controller (QUICCª). The CPU on the MPC860 is a 32-bit
PowerPC implementation that incorporates memory management units (MMUs) and
instruction and data caches. The communications processor module (CPM) from the
MC68360 QUICC has been enhanced by the addition of the inter-integrated controller
2
C) channel. Digital signal processing (DSP) functionality has been added to the CPM.
(I
The memory controller has been enhanced, enabling the MPC860 to support any type of
memory, including high-performance memories and new types of DRAMs. A PCMCIA
socket controller supports up to two sockets. A real-time clock has also been integrated.
The purpose of this manual is to describe the operation of all the MPC860 functionality
with concentration on the I/O functions. Additional information can be found in PowerPC
Microprocessor Family: The Programming Environments.
1.1 Features
The following list summarizes the key MPC860 features:
¥ Embedded PowerPC core
¥ Single issue, 32-bit version of the core (compatible the PowerPC architecture
deÞnition) with 32, 32-bit general-purpose registers (GPRs)
Ñ The core performs branch prediction with conditional prefetch, without
conditional execution
Ñ 4-Kbyte data cache and 4-Kbyte instruction cache
Ñ Instruction and data caches are two-way, set-associative, physical address, least
recently used (LRU) replacement, lockable on-line granularity
Ñ MMUs with 32 entry TLB, fully associative instruction and data TLBs
MOTOROLA Chapter 1. MPC860 Overview 1-1
Page 80
Part I. Overview
Ñ MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16
virtual address spaces and 16 protection groups
Ñ Advanced on-chip-emulation debug mode
¥ Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
¥ 32 address lines
¥ Complete static design
¥ Memory controller (eight banks)
Ñ Contains complete dynamic RAM (DRAM) controller
Ñ Each bank can be a chip select or RAS
to support a DRAM bank
Ñ Up to 30 wait states programmable per memory bank
Ñ Glueless interface to DRAM, SIMMS, SRAM, EPROMs, ßash EPROMs, and
other memory devices.
Ñ DRAM controller programmable to support most size and speed memory
interfaces
Ñ Four CAS
lines, four WE lines, one OE line
Ñ Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
Ñ Variable block sizes (32 KbyteÐ256 Mbyte)
Ñ Selectable write protection
Ñ On-chip bus arbitration logic
¥ General-purpose timers
Ñ Four 16-bit timers or two 32-bit timers
Ñ Gate mode can enable/disable counting
Ñ Interrupt can be masked on reference match and event capture
¥ System integration unit (SIU)
Ñ Bus monitor
Ñ Software watchdog
Ñ Periodic interrupt timer (PIT)
Ñ Low-power stop mode
Ñ Clock synthesizer
Ñ PowerPC decrementer and time base
Ñ Real-time clock (RTC)
Ñ Reset controller
Ñ IEEE 1149.1 test access port (JTAG)
1-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 81
Part I. Overview
¥ Interrupts
Ñ Seven external interrupt request (IRQ) lines
Ñ 12 port pins with interrupt capability
Ñ 23 internal interrupt sources
Ñ Programmable priority between SCCs
Ñ Programmable highest priority request
¥ Communications processor module (CPM)
Ñ RISC controller
Ñ Communication-speciÞc commands (for example,
ENTER HUNT MODE, and RESTART TRANSMIT)
GRACEFUL STOP TRANSMIT,
Ñ Up to 384 buffer descriptors (BDs)
Ñ Supports continuous mode transmission and reception on all serial channels
Ñ Up to 5 Kbytes of dual-port RAM
Ñ 16 serial DMA (SDMA) channels
Ñ Three parallel I/O registers with open-drain capability
¥ On-chip 16 x 16 multiply accumulate controller (MAC)
Ñ One operation per clock (two clock latency, one clock blockage)
Ñ MAC operates concurrently with other instructions
Ñ FIR loop: four clocks per four multiplies
¥ Four baud rate generators
Ñ Independent (can be connected to any SCC or SMC)
Ñ Allow changes during operation
Ñ Autobaud support option
¥ Four SCCs (serial communication controllers)
Ñ Ethernet/IEEE 802.3 optional on SCC1Ð4, supporting full 10-Mbps operation
(Available only on specially programmed devices)
Ñ HDLC/SDLC
Ñ HDLC bus (implements an HDLC-based local area network (LAN))
Ñ Asynchronous HDLC to support PPP (point-to-point protocol)
Ñ AppleTalk
Ñ Universal asynchronous receiver transmitter (UART)
Ñ Synchronous UART
Ñ Serial infrared (IrDA)
Ñ Binary synchronous communication (BISYNC)
Ñ Totally transparent (bit streams)
Ñ Totally transparent (frame based with optional cyclic redundancy check (CRC))
MOTOROLA Chapter 1. MPC860 Overview 1-3
Page 82
Part I. Overview
¥ Two SMCs (serial management channels)
Ñ UART
Ñ Transparent
Ñ General circuit interface (GCI) controller
Ñ Can be connected to the time-division multiplexed (TDM) channels
¥ One SPI (serial peripheral interface)
Ñ Supports master and slave modes
Ñ Supports multimaster operation on the same bus
¥ One I2C (inter-integrated circuit) port
Ñ Supports master and slave modes
Ñ Multiple-master environment support
¥ Time-slot assigner (TSA)
Ñ Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation
Ñ Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user
deÞned
Ñ 1- or 8-bit resolution
Ñ Allows independent transmit and receive routing, frame synchronization,
clocking
Ñ Allows dynamic changes
Ñ Can be internally connected to six serial channels (four SCCs and two SMCs)
¥ Parallel interface port (PIP)
Ñ Centronics interface support
Ñ Supports fast connection between compatible ports on MPC860 or MC68360
¥ PCMCIA interface
Ñ Master (socket) interface, release 2.1 compliant
Ñ Supports two independent PCMCIA sockets
Ñ 8 memory or I/O windows supported
¥ Low power support
Ñ Full onÑAll units fully powered
Ñ DozeÑCore functional units disabled except time base decrementer, PLL,
memory controller, RTC, and CPM in low-power standby
Ñ SleepÑAll units disabled except RTC, PIT, time base, and decrementer with
PLL active for fast wake up
Ñ Deep sleepÑAll units disabled including PLL except RTC, PIT, time base, and
decrementer.
Ñ Power down modeÑ All units powered down except PLL, RTC, PIT, time base
and decrementer
1-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 83
Part I. Overview
¥ Debug interface
Ñ Eight comparators: four operate on instruction address, two operate on data
address, and two operate on data
Ñ Supports Conditions: = ¹ < >
Ñ Each watchpoint can generate a break point internally
¥ 3.3 V operation with 5-V TTL compatibility
¥ 357-pin ball grid array (BGA) package
PowerPC
Processor
Core
Instruction
Bus
Load/Store
Bus
Parallel I/O
4 Baud Rate
Generators
Parallel Interface
Por t
SCC2 SMC1 SMC2 SPI I2C
SCC1 SCC3 SCC4
Serial Interface and Time-Slot Assigner (TSA)
4 K
Instruction Cache
Instruction MMU
32 Entry ITLB
4 K
Data Cache
Data MMU
32 Entry DTLB
4
Timers
Timers
Interrupt
Controllers
32-Bit RISC Controller
and Program
Figure 1-1. MPC860 Block Diagram
ROM
UniÞed
Bus
5 K Dual-Port
1
RAM
MAC
System Interface Unit (SIU)
Memory Controller
Internal
Bus Interface
Unit
System Functions
Real-Time Clock
PCMCIA-ATA Interface
16 Virtual
Serial
and
2
Independent
DMA
Channels
Serial Interface
External
Bus Interface
Unit
1.2 Architecture Overview
The MPC860 integrates an embedded PowerPC core with high-performance, low-power
peripherals to extend the Motorola Data Communications family of embedded processors
even farther into high-end communications and networking products.
The MPC860 is comprised of three modules that each use the 32-bit internal bus: the
PowerPC core, the system integration unit (SIU), and the communication processor module
(CPM). The MPC860 block diagram is shown in Figure 1-1.
MOTOROLA Chapter 1. MPC860 Overview 1-5
Page 84
Part I. Overview
1.3 Embedded PowerPC Core
The core is compliant with the UISA (user instruction set architecture) portion of the
PowerPC architecture. It is a fully static design that has an integer unit (IU) and a load/store
unit (LSU). It executes all integer and load/store operations in hardware. The core supports
integer operations on a 32-bit internal data path and 32-bit arithmetic hardware. The core
interface to the internal and external buses is 32 bits. The core can operate on 32-bit external
operands with one bus cycle.
The IU uses 32, 32-bit GPRs for source and target operands. Typically, it can execute one
integer instruction each clock cycle. Each element in the integer block is clocked only when
valid data is present in the data queue ready for operation. This assures that power
consumption of the device is held to the absolute minimum required for operation.
The core is integrated with MMUs as well as 4-Kbyte instruction and data caches. Each
MMU provides a 32 entry, fully associative instruction and data TLB, with multiple page
sizes of 4, 16, 512, and 256 Kbytes and 8 Mbytes. It supports 16 virtual address spaces with
8 protection groups. Three special scratch registers support software table walk and update.
The instruction cache is 4 Kbytes, two-way, set associative with physical addressing. It
allows single-cycle access on hits with no added latency for misses. It has four words per
block, supporting a four-beat burst line Þll using an LRU (least recently used) replacement
algorithm. The cache can be locked on a per cache block basis for application-critical
routines.
The data cache is 4 Kbytes, two-way, set associative with physical addressing. It allows
single-cycle accesses on hits with one added clock latency for misses. It has four words per
cache block, supporting burst line Þll using LRU replacement. The cache can be locked on
a per block basis for application critical routines. The data cache can be programmed to
support copy-back or write-through via the MMU. The inhibit mode can be programmed
per MMU page.
The core contains a much improved debug interface that provides superior debug
capabilities without causing any degradation in the speed of operation. This interface
supports six watchpoint pins that are used to detect software events. Internally it has eight
comparators, four of which operate on the effective address on the address bus. The
remaining four comparators are split, with two comparators operating on the effective
address on the data address bus, and two comparators operating on the data bus. The core
can compare using =, ¹, <, > conditions to generate watchpoints. Each watchpoint can then
generate a break point that can be programmed to trigger in a programmable number of
events.
1-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 85
Part I. Overview
1.4 System Interface Unit (SIU)
The SIU on the MPC860 integrates general-purpose features useful in almost any 32-bit
processor system, enhancing the performance provided by the system integration module
(SIM) on the MC68360 QUICC device.
Dynamic bus sizing is supported. Bus sizing allows 8-, 16-, and 32-bit peripherals and
memory to exist in the 32-bit system bus mode.
The SIU also provides power management functions, reset control, PowerPC decrementer,
PowerPC time base and the real-time clock.
The memory controller supports up to eight memory banks with glueless interfaces to
DRAM, SRAM, SSRAM, EPROM, ßash EPROM, SRDRAM, EDO and other peripherals
with two-clock access to external SRAM and bursting support. It provides variable block
sizes from 32 Kbytes to 256 Mbytes. The memory controller provides 0Ð30 wait states for
each bank of memory and can use address type matching to qualify each memory bank
access. It provides four byte enable signals, one output enable signal and one boot chip
select available at reset.
The DRAM interface supports port sizes of 8, 16, and 32 bits. Memory banks can be
deÞned in depths of 256 or 512 Kbytes or 1, 2, 4, 8, 16, 32, or 64 Mbytes for all port sizes.
In addition the memory depth can be deÞned as 64 Kbytes and 128 Kbytes for 8-bit memory
or 128 Mbytes and 256 Mbytes for 32-bit memory. The DRAM controller supports page
mode access for successive transfers within bursts. The MPC860 supports a glueless
interface to one bank of DRAM while external buffers are required for additional memory
banks. The refresh unit provides CAS
active during external reset, disable refresh mode, and stacking up to 7 refresh cycles. The
DRAM interface uses a programmable state machine to support almost any memory
interface.
before RAS, a programmable refresh timer, refresh
1.5 PCMCIA Controller
The PCMCIA interface is a master (socket) controller and is compliant with release 2.1.
The interface supports up to two independent PCMCIA sockets requiring only external
transceivers/buffers. The interface provides 8 memory or I/O windows where each window
can be allocated to a particular socket. If only one PCMCIA port is being used, the unused
PCMCIA port may be used as general-purpose input with interrupt capability.
1.6 Power Management
The MPC860 supports a wide range of power management features including full on, doze,
sleep, deep sleep, and low power stop. In full on mode the MPC860 processor is fully
powered with all internal units operating at the full speed of the processor. A gear mode is
provided which is determined by a clock divider, allowing the operating system to reduce
the operational frequency of the processor. Doze mode disables core functional units other
MOTOROLA Chapter 1. MPC860 Overview 1-7
Page 86
Part I. Overview
than the time base decrementer, PLL, memory controller, RTC, and then places the CPM
in low-power standby mode. Sleep mode disables everything except the RTC and PIT,
leaving the PLL active for quick wake-up. Deep sleep mode disables the PLL for lower
power but slower wake-up. Low-power stop disables all logic in the processor except the
minimum logic required to restart the device, providing the lowest power consumption but
requiring the longest wake-up time.
1.7 Communications Processor Module (CPM)
The MPC860 is the next generation MC68360 QUICC and like its predecessor implements
a dual-processor architecture. This dual-processor architecture provides both a
high-performance general purpose processor for application programming use as well as a
special purpose communication processor (CPM) uniquely designed for communications
needs.
The CPM contains features that allow the MPC860 to excel in communications and
networking products as did the MC68360 QUICC which preceded it. These features may
be divided into three sub-groups:
¥ Communications processor (CP)
¥ Sixteen independent DMA (SDMA) controllers
¥ Four general-purpose timers
The CP provides the communication features of the MPC860. Included are a RISC
processor, two serial communication controllers (SCC), four serial management controllers
(SMC), one serial peripheral interface (SPI), one I
2
C interface, 5 Kbytes of dual-port RAM,
an interrupt controller, a time-slot assigner, three parallel ports, a parallel interface port,
four independent baud rate generators, and sixteen serial DMA channels to support the
SCCs, SMCs, SPI, and I
2
C.
The SDMAs provide two channels of general-purpose DMA capability for each
communications channel. They offer high-speed transfers, 32-bit data movement, buffer
chaining, and independent request and acknowledge logic.
The four general-purpose timers on the CPM are identical to the timers found on the
MC68360 and still support the internal cascading of two timers to form a 32-bit timer.
The MPC860 maintains the best features of the MC68360 QUICC, while making changes
required to provide for the increased ßexibility, integration, and performance requested by
customers demanding the performance of the PowerPC architecture. The addition of a
multiply-and-accumulate (MAC) function on the CPM further enhances the MPC860,
enabling various modem and DSP applications. Because the CPM architectural approach
remains intact between the MPC860 and the MC68360 QUICC, a user of the MC68360
QUICC can easily become familiar with the MPC860.
1-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 87
Part I. Overview
1.8 Software Compatibility Issues
The following list summarizes the major software differences between the MC68360
QUICC and the MPC860:
¥ Since the MPC860 uses an embedded PowerPC core, code written for the MC68360
must be recompiled for the PowerPC instruction set. Code that accesses MC68360
peripherals requires only minor modiÞcations for use with the MPC860. Although
the functions performed by the PowerQUICC SIU are similar to those performed by
the QUICC SIM, the initialization sequence for the SIU is different and therefore
code that accesses the SIU must be rewritten. Many developers of 68K compilers
now provide compilers that also support the PowerPC architecture.
¥ The addition of the MAC function to the MPC860 CPM block to support the needs
of higher performance communication software is the only major difference
between the CPM on the MC68360 and that on the MPC860. Therefore, the registers
used to initialize the QUICC CPM are similar to the MPC860 CPM, but there are
some minor changes necessary for supporting the MAC function.
When porting code from the MC68360 CPM to the MPC860 CPM, the software writer has
new options for setting hardware break points on CPU commands, address, and serial
request which are useful for software debugging. Support for single-step operation with all
CPM registers visible further simpliÞes software development for the CPM.
MOTOROLA Chapter 1. MPC860 Overview 1-9
Page 88
Part I. Overview
1-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 89
Chapter 2
Memory Map
20
20
Each memory resource in the MPC860 is mapped within a contiguous block of 16 Kbyte
memory. The location of this block within the global 4-Gbyte physical memory space can
be mapped on 64-Kbyte resolution through an implementation-speciÞc special-purpose
register (SPR) called the internal memory map register (IMMR). See Section 11.4.1,
ÒInternal Memory Map Register (IMMR).Ó Table 2-1 deÞnes the internal memory map.
Table 2-1. MPC860 Internal Memory Map
Offset Name Size Section/Page
General System Interface Unit
000 SIUMCRÑSIU module conÞguration register 32 bits 11.4.2/11-5
004 SYPCRÑSystem protection control register 32 bits 11.4.3/11-9
008Ð00D Reserved 6 bytes Ñ
00E SWSRÑSoftware service register 16 bits 11.7.1/11-22
010 SIPENDÑSIU interrupt pending register 32 bits 11.5.4.1/11-16
014 SIMASKÑSIU interrupt mask register 32 bits 11.5.4.2/11-17
018 SIELÑSIU interrupt edge/level register 32 bits 11.5.4.3/11-18
01C SIVECÑSIU interrupt vector register 32 bits 11.5.4.4/11-19
020 TESRÑTransfer error status register 32 bits 11.4.4/11-10
024Ð02F Reserved 12 bytes Ñ
030 SDCRÑSDMA conÞguration register 32 bits 20.2.1/20-3
034Ð07F Reserved 76 bytes Ñ
PCMCIA
080 PBR0ÑPCMCIA interface base register 0 32 bits 17.4.5/17-12
084 POR0ÑPCMCIA interface option register 0 32 bits 17.4.6/17-13
088 PBR1ÑPCMCIA interface base register 1 32 bits 17.4.5/17-12
08C POR1ÑPCMCIA interface option register 1 32 bits 17.4.6/17-13
090 PBR2ÑPCMCIA interface base register 2 32 bits 17.4.5/17-12
094 POR2ÑPCMCIA interface option register 2 32 bits 17.4.6/17-13
098 PBR3ÑPCMCIA interface base register 3 32 bits 17.4.5/17-12
09C POR3ÑPCMCIA interface option register 3 32 bits 17.4.6/17-13
0A0 PBR4ÑPCMCIA interface base register 4 32 bits 17.4.5/17-12
MOTOROLA Chapter 2. Memory Map 2-1
Page 90
Part I. Overview
Table 2-1. MPC860 Internal Memory Map (Continued)
Offset Name Size Section/Page
0A4 POR4ÑPCMCIA interface option register 4 32 bits 17.4.6/17-13
0A8 PBR5ÑPCMCIA interface base register 5 32 bits 17.4.5/17-12
0AC POR5ÑPCMCIA interface option register 5 32 bits 17.4.6/17-13
0B0 PBR6ÑPCMCIA interface base register 6 32 bits 17.4.5/17-12
0B4 POR6ÑPCMCIA interface option register 6 32 bits 17.4.6/17-13
0B8 PBR7ÑPCMCIA interface base register 7 32 bits 17.4.5/17-12
0BC POR7ÑPCMCIA interface option register 7 32 bits 17.4.6/17-13
0C0Ð0DF Reserved 32 bytes Ñ
0E0 PGCRAÑPCMCIA interface general control
register A
0E4 PGCRBÑPCMCIA interface general control
register b
0E8 PSCRÑPCMCIA interface status changed
register
0ECÐ0EF Reserved 4 bytes Ñ
0F0 PIPRÑPCMCIA interface input pins register 32 bits 17.4.1/17-8
0F4Ð0F7 Reserved 4 bytes Ñ
0F8 PERÑPCMCIA interface enable register 32 bits 17.4.3/17-10
0FCÐ0FF Reserved 4 bytes Ñ
Memory Controller
100 BR0ÑBase register bank 0 32 bits 16.4.1/16-8
104 OR0ÑOption register bank 0 32 bits 16.4.2/16-10
108 BR1ÑBase register bank 1 32 bits 16.4.1/16-8
10C OR1ÑOption register bank 1 32 bits 16.4.2/16-10
110 BR2ÑBase register bank 2 32 bits 16.4.1/16-8
114 OR2ÑOption register bank 2 32 bits 16.4.2/16-10
118 BR3ÑBase register bank 3 32 bits 16.4.1/16-8
11C OR3ÑOption register bank 3 32 bits 16.4.2/16-10
120 BR4ÑBase register bank 4 32 bits 16.4.1/16-8
124 OR4ÑOption register bank 4 32 bits 16.4.2/16-10
128 BR5ÑBase register bank 5 32 bits 16.4.1/16-8
12C OR5ÑOption register bank 5 32 bits 16.4.2/16-10
130 BR6ÑBase register bank 6 32 bits 16.4.1/16-8
134 OR6ÑOption register bank 6 32 bits 16.4.2/16-10
138 BR7ÑBase register bank 7 32 bits 16.4.1/16-8
13C OR7ÑOption register bank 7 32 bits 16.4.2/16-10
140Ð163 Reserved 36 bytes Ñ
164 MARÑMemory address register 32 bits 16.4.7/16-17
168 MCRÑMemory command register 32 bits 16.4.5/16-15
32 bits 17.4.4/17-12
32 bits 17.4.4/17-12
32 bits 17.4.2/17-9
2-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 91
Table 2-1. MPC860 Internal Memory Map (Continued)
Offset Name Size Section/Page
16CÐ16F Reserved 4 bytes Ñ
170 MAMRÑMachine A mode register 32 bits 16.4.4/16-13
174 MBMRÑMachine B mode register 32 bits 16.4.4/16-13
178 MSTATÑMemor y status register 16 bits 16.4.3/16-13
17A MPTPRÑMemory periodic timer prescaler 16 bits 16.4.8/16-17
17C MDRÑMemory data register 32 bits 16.4.6/16-16
180Ð1FF Reserved 128
System Integration Timers
200 TBSCRÑTimebase status and control register 16 bits 11.9.3/11-26
202Ð203 Reserved 2 bytes Ñ
204 TBREFAÑTimebase reference register A 32 bits 11.9.2/11-25
208 TBREFLÑTimebase reference register B 32 bits
20CÐ21F Reserved 20 bytes Ñ
220 RTCSCÑReal-time clock status and control
register
222Ð223 Reserved 2 bytes Ñ
224 RTCÑReal-time clock register 32 bits 11.10.2/11-28
228 RTSECÑReal-time alarm seconds 32 bits 11.10.4/11-29
22C RTCALÑReal-time alarm register 32 bits 11.10.3/11-29
230Ð23F Reserved 16 bytes Ñ
240 PISCRÑPeriodic interrupt status and control
register
242Ð233 Reserved 2 bytes Ñ
244 PITCÑPeriodic interrupt count register 32 bits 11.11.2/11-32
248 PITRÑPeriodic interrupt timer register 32 bits 11.11.3/11-33
24CÐ27F Reserved 52 bytes Ñ
Clocks and Reset
280 SCCRÑSystem clock control register 32 bits 15.6.1/15-27
284 PLPRCRÑPLL, low-power, and reset control
register
288 RSRÑReset status register 32 bits 12.2/12-5
28CÐ2FF Reserved 116
System Integration Timers Keys
300 TBSCRKÑTimebase status and control register
key
304 TBREFAKÑTimebase reference register A key 32 bits 11.4.5/11-11
308 TBREFBKÑTimebase reference register B key 32 bits 11.4.5/11-11
30C TBKÑTimebase/decrementer register key 32 bits 11.4.5/11-11
Ñ
bytes
16 bits 11.10.1/11-27
16 bits 11.11.1/11-31
32 bits 15.6.2/15-29
Ñ
bytes
32 bits 11.4.5/11-11
Part I. Overview
MOTOROLA Chapter 2. Memory Map 2-3
Page 92
Part I. Overview
Table 2-1. MPC860 Internal Memory Map (Continued)
Offset Name Size Section/Page
310Ð31F Reserved 16 bytes Ñ
320 RTCSCKÑReal-time clock status and control
register key
324 RTCKÑReal-time clock register key 32 bits 11.4.5/11-11
328 RTSECKÑReal-time alarm seconds key 32 bits 11.4.5/11-11
32C RTCALKÑReal-time alarm register key 32 bits 11.4.5/11-11
330Ð33F Reserved 16 bytes Ñ
340 PISCRKÑPeriodic interrupt status and control
register key
344 PITCKÑPeriodic interrupt count register key 32 bits 11.4.5/11-11
348Ð37F Reserved 56 bytes Ñ
Clocks and Reset Keys
380 SCCRKÑSystem clock control key 32 bits 11.4.5/11-11
384 PLPRCRKÑPLL, low power and reset control
register key
388 RSRKÑReset status register key 32 bits 11.4.5/11-11
38CÐ85F Reserved 1236
I2C Controller
860 I2MODÑI2C mode register 8 bits 32.4.1/32-6
861Ð863 Reserved 3 bytes Ñ
864 I2ADDÑI2C address register 8 bits 32.4.2/32-7
865Ð867 Reserved 3 bytes Ñ
868 I2BRGÑI2C BRG register 8 bits 32.4.3/32-7
86C I2COMÑI2C command register 8 bits 32.4.5/32-8
86DÐ86F Reserved 3 bytes Ñ
870 I2CERÑI2C event register 8 bits 32.4.4/32-8
871Ð873 Reserved 3 bytes Ñ
874 I2CMRÑI2C mask register 8 bits 32.4.4/32-8
875Ð8FF Reserved 139
DMA
900Ð903 Reserved 4 bytes Ñ
904 SDARÑSDMA address register 32 bits 20.2.4/20-5
908 SDSRÑSDMA status register 8 bits 20.2.2/20-4
909Ð90B Reserved 3 bytes Ñ
90C SDMRÑSDMA mask register 8 bits 20.2.3/20-5
90DÐ90F Reserved 3 bytes Ñ
910 IDSR1ÑIDMA1 status register 8 bits 20.3.9.2/20-19
911Ð913 Reserved 3 bytes Ñ
32 bits 11.4.5/11-11
32 bits 11.4.5/11-11
32 bits 11.4.5/11-11
Ñ
bytes
Ñ
bytes
2-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 93
Table 2-1. MPC860 Internal Memory Map (Continued)
Offset Name Size Section/Page
914 IDMR1ÑIDMA1 mask register 8 bits 20.3.9.3/20-20
915Ð917 Reserved 3 bytes Ñ
918 IDSR2ÑIDMA2 status register 8 bits 20.3.9.2/20-19
919Ð91B Reserved 3 bytes Ñ
91C IDMR2ÑIDMA2 mask register 8 bits 20.3.9.3/20-20
91DÐ92F Reserved 19 bytes Ñ
Communications Processor Module Interrupt Control
930 CIVRÑCPM interrupt vector register 16 bits 35.5.5/35-10
932Ð93F Reserved 14 bytes Ñ
940 CICRÑCPM interrupt conÞguration register 32 bits 35.5.1/35-7
944 CIPRÑCPM interrupt pending register 32 bits 35.5.2/35-8
948 CIMRÑCPM interrupt mask register 32 bits 35.5.3/35-9
94C CISRÑCPM in-service register 32 bits 35.5.4/35-9
Input/Output Port
950 PADIRÑPort A data direction register 16 bits 34.2.1.3/34-4
952 PAPARÑPort A pin assignment register 16 bits 34.2.1.4/34-5
954 PAODRÑPort A open drain register 16 bits 34.2.1.1/34-3
956 PADATÑPort A data register 16 bits 34.2.1.2/34-4
958Ð95F Reserved 8 bytes Ñ
960 PCDIRÑPort C data direction register 16 bits 34.4.1.2/34-15
962 PCPARÑPort C pin assignment register 16 bits 34.4.1.3/34-15
964 PCSOÑPort C special options register 16 bits 34.4.1.4/34-16
966 PCDATÑPort C data register 16 bits 34.4.1.1/34-15
968 PCINTÑPort C interrupt control register 16 bits 34.4.1.5/34-17
96AÐ96F Reserved 6 bytes Ñ
970 PDDIRÑPort D data direction register 16 bits 34.5.1.2/34-19
972 PDPARÑPort D pin assignment register 16 bits 34.5.1.3/34-19
974 Reserved 2 bytes Ñ
976 PDDATÑPort D data register 16 bits 34.5.1.1/34-18
978Ð97F Reserved 8 bytes Ñ
CPM General-Purpose Timers
980 TGCRÑTimer global conÞguration register 16 bits 18.2.3.1/18-8
982Ð98F Reserved 14 bytes Ñ
990 TMR1ÑTimer 1 mode register 16 bits 18.2.3.2/18-9
992 TMR2ÑTimer 2 mode register 16 bits 18.2.3.2/18-9
994 TRR1ÑTimer 1 reference register 16 bits 18.2.3.3/18-10
996 TRR2ÑTimer 2 reference register 16 bits 18.2.3.3/18-10
998 TCR1ÑTimer 1 capture register 16 bits 18.2.3.4/18-10
Part I. Overview
MOTOROLA Chapter 2. Memory Map 2-5
Page 94
Part I. Overview
Table 2-1. MPC860 Internal Memory Map (Continued)
Offset Name Size Section/Page
99A TCR2ÑTimer 2 capture register 16 bits 18.2.3.4/18-10
99C TCN1ÑTimer 1 counter 16 bits 18.2.3.5/18-10
99E TCN2ÑTimer 2 counter 16 bits 18.2.3.5/18-10
9A0 TMR3ÑTimer 3 mode register 16 bits 18.2.3.2/18-9
9A2 TMR4ÑTimer 4 mode register 16 bits 18.2.3.2/18-9
9A4 TRR3ÑTimer 3 reference register 16 bits 18.2.3.3/18-10
9A6 TRR4ÑTimer 4 reference register 16 bits 18.2.3.3/18-10
9A8 TCR3ÑTimer 3 capture register 16 bits 18.2.3.4/18-10
9AA TCR4ÑTimer 4 capture register 16 bits 18.2.3.4/18-10
9AC TCN3ÑTimer 3 counter 16 bits 18.2.3.5/18-10
9AE TCN4ÑTimer 4 counter 16 bits 18.2.3.5/18-10
9B0 TER1ÑTimer 1 event register 16 bits 18.2.3.6/18-11
9B2 TER2ÑTimer 2 event register 16 bits 18.2.3.6/18-11
9B4 TER3ÑTimer 3 event register 16 bits 18.2.3.6/18-11
9B6 TER4ÑTimer 4 event register 16 bits 18.2.3.6/18-11
9B8Ð9BF Reserved 8 bytes Ñ
Communications Processor (CP)
9C0 CPCRÑCP command register 16 bits 19.5.2/19-6
9C2Ð9C3 Reserved 2 bytes Ñ
9C4 RCCRÑRISC controller conÞguration register 16 bits 19.5.1/19-4
9C6Ð9C8 Reserved 3 bytes Ñ
9CC RCTR1ÑRISC controller trap register 1 16 bits Used only by optional RAM microcode
9CE RCTR2ÑRISC controller trap register 2 16 bits Used only by optional RAM microcode
9D0 RCTR3ÑRISC controller trap register 3 16 bits Used only by optional RAM microcode
9D2 RCTR4ÑRISC controller trap register 4 16 bits Used only by optional RAM microcode
9D4Ð9D5 Reserved 2 bytes Ñ
9D6 RTERÑRISC timer event register 16 bits 19.7.4/19-15
9D8Ð9D9 Reserved 2 bytes Ñ
9DA RTMRÑRISC timers mask register 16 bits 19.7.4/19-15
9DCÐ9EF Reserved 20 bytes Ñ
Baud Rate Generators
9F0 BRGC1ÑBRG1 conÞguration register 32 bits 21.4.1/21-40
9F4 BRGC2ÑBRG2 conÞguration register 32 bits 21.4.1/21-40
9F8Ð9FF Reserved 8 bytes Ñ
SCC1
A00 GSMR_L1ÑSCC1 general mode register 32 bits 22.1.1/22-3
A04 GSMR_H1ÑSCC1 general mode register 32 bits 22.1.1/22-3
2-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 95
Table 2-1. MPC860 Internal Memory Map (Continued)
Offset Name Size Section/Page
A08 PSMR1ÑSCC1 protocol speciÞc mode register 16 bits 22.1.2/22-10
A0AÐA0B Reserved 2 bytes Ñ
A0C TODR1ÑSCC1 transmit-on-demand register 16 bits 22.1.4/22-10
A0E DSR1ÑSCC1 data synchronization register 16 bits 22.1.3/22-10
A10 SCCE1ÑSCC1 event register 16 bits 23.19/23-19 (UART)
A12ÐA13 Reserved 2 bytes
A14 SCCM1ÑSCC1 mask register 16 bits
A16 Reserved 1 byte Ñ
A17 SCCS1ÑSCC1 status register 8 bits 23.20/23-21 (UART)
A18ÐA1F Reserved 8 bytes Ñ
Serial Communication Controller 2 (SCC2)
A20 GSMR_L2ÑSCC2 general mode register 32 bits 22.1.1/22-3
A24 GSMR_H2ÑSCC2 general mode register 32 bits 22.1.1/22-3
A28 PSMR2ÑSCC2 protocol-speciÞc mode register 16 bits 22.1.2/22-10
A2A Reserved 16 bits Ñ
A2C TODR2ÑSCC2 transmit on demand register 16 bits 22.1.4/22-10
A2E DSR2ÑSCC2 data synchronization register 16 bits 22.1.3/22-10
A30 SCCE2ÑSCC2 event register 16 bits 23.20/23-21 (UART)
A32 Reserved 16 bits Ñ
A34 SCCM2ÑSCC2 mask register 16 bits 23.20/23-21 (UART)
A36 Reserved 8 bits Ñ
23.16/23-13 (UART)
26.13.3/26-11 (Asynchronous HDLC)
27.11/27-10 (BiSYNC)
28.18/28-19 (Ethernet)
29.9/29-8 (Transparent)
24.11/24-12 (HDLC)
26.13.1/26-9 (Asynchronous HDLC)
27.14/27-15 (BiSYNC)
28.21/28-25 (Ethernet)
29.12/29-12 (Transparent)
24.12/24-14 (HDLC)
26.13.2/26-10 (Asynchronous HDLC)
27.15/27-16 (BiSYNC)
29.13/29-13 (Transparent)
23.16/23-13 (UART)
26.13.3/26-11 (Asynchronous HDLC)
27.11/27-10 (BISYNC)
28.18/28-19 (Ethernet)
29.9/29-8 (Transparent)
24.11/24-12 (HDLC)
26.13.1/26-9 (Asynchronous HDLC)
27.15/27-16 (BISYNC)
29.13/29-13 (Transparent)
24.12/24-14 (HDLC)
26.13.3/26-11 (Asynchronous HDLC)
27.15/27-16 (BISYNC)
29.13/29-13 (Transparent)
Part I. Overview
MOTOROLA Chapter 2. Memory Map 2-7
Page 96
Part I. Overview
Table 2-1. MPC860 Internal Memory Map (Continued)
Offset Name Size Section/Page
A37 SCCS2ÑSCC2 status register 8 bits 23.20/23-21 (UART)
A38ÐA3F Reserved 8 bytes Ñ
Serial Communication Controller 3 (Where applicable)
A40 GSMR_L3ÑSCC3 general mode register 32 bits 22.1.1/22-3
A44 GSMR_H3ÑSCC3 general mode register 32 bits 22.1.1/22-3
A48 PSMR3ÑSCC3 protocol speciÞc mode register 16 bits 22.1.2/22-10
A4AÐA4B Reserved 2 bytes Ñ
A4C TODR3ÑSCC3 transmit on demand register 16 bits 22.1.4/22-10
A4E DSR3ÑSCC3 data synchronization register 16 bits 22.1.3/22-10
A50 SCCE3ÑSCC3 event register 16 bits 23.20/23-21 (UART)
A52ÐA53 Reserved 2 bytes
A54 SCCM3ÑSCC3 mask register 16 bits
A56 Reserved 1 byte Ñ
A57 SCCS3ÑSCC3 status register 8 bits 23.20/23-21 (UART)
A58ÐA5F Reserved 8 bytes Ñ
SCC4
A60 GSMR_L4ÑSCC4 general mode register 32 bits 22.1.1/22-3
A64 GSMR_H4ÑSCC4 general mode register 32 bits 22.1.1/22-3
A68 PSMR4ÑSCC4 protocol speciÞc mode register 16 bits 22.1.2/22-10 23.16/23-13 (UART)
A6AÐA6B Reserved 2 bytes Ñ
A6C TODR4ÑSCC4 transmit on demand register 16 bits 22.1.4/22-10
A6E DSR4ÑSCC4 data synchronization register 16 bits 22.1.3/22-10
A70 SCCE4ÑSCC4 event register 16 bits 23.20/23-21 (UART)
A72ÐA73 Reserved 2 bytes
A74 SCCM4ÑSCC4 mask register 16 bits
A76 Reserved 1 byte Ñ
24.12/24-14 (HDLC)
27.15/27-16 (BISYNC)
29.13/29-13 (Transparent)
23.16/23-13 (UART)
26.13.3/26-11 (Asynchronous HDLC)
27.11/27-10 (BISYNC)
28.18/28-19 (Ethernet)
29.9/29-8 (Transparent)
24.12/24-14 (HDLC)
26.13.3/26-11 (Asynchronous HDLC)
27.15/27-16 (BISYNC)
29.13/29-13 (Transparent)
24.12/24-14 (HDLC)
27.15/27-16 (BISYNC)
29.13/29-13 (Transparent)
26.13.3/26-11 (Asynchronous HDLC)
27.11/27-10 (BiSYNC)
28.18/28-19 (Ethernet)
29.9/29-8 (Transparent)
24.12/24-14 (HDLC)
26.13.3/26-11 (Asynchronous HDLC)
27.15/27-16 (BiSYNC)
29.13/29-13 (Transparent)
2-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 97
Table 2-1. MPC860 Internal Memory Map (Continued)
Offset Name Size Section/Page
A77 SCCS4ÑSCC4 status register 8 bits 23.20/23-21 (UART)
A78ÐA81 Reserved 4 bytes Ñ
Serial Management Controller 1 (SMC1)
A82 SMCMR1ÑSMC1 mode register 16 bits 30.2.1/30-3
A84ÐA85 Reserved 2 bytes Ñ
A86 SMCE1ÑSMC1 event register 8 bits 30.3.12/30-18 (UART)
A87ÐA89 Reserved 3 bytes Ñ
A8A SMCM1ÑSMC1 mask register 8 bits 30.3.12/30-18 (UART)
A8BÐA91 Reserved 7 bytes Ñ
Serial Management Controller 2 (SMC2)
A92 SMCMR2ÑSMC2 mode register 16 bits 30.2.1/30-3
A94ÐA95 Reserved 2 bytes Ñ
A96 SMCE2ÑSMC2 event register 8 bits 30.3.12/30-18 (UART)
A97ÐA99 Reserved 3 bytes Ñ
A9A SMCM2ÑSMC2 mask register 8 bits 30.3.12/30-18 (UART)
A9BÐA9F Reserved 5 bytes Ñ
Serial Peripheral Interface (SPI)
AA0 SPMODEÑSPI mode register 16 bits 31.4.1/31-7
AA2ÐAA5 Reserved 16 bits4
AA6 SPIEÑSPI event register 8 bits 31.4.2/31-10
AA7ÐAA9 Reserved 3 bytes Ñ
AAA SPIMÑSPI mask register 8 bits 31.4.2/31-10
AABÐAAC Reserved 2 bytes Ñ
AAD SPCOMÑSPI command register 8 bits 31.4.3/31-10
AAEÐAB1 Reserved 4 bytes Ñ
Parallel Interface Port(PIP)
AB2 PIPCÑPIP conÞguration register 16 bits 33.4.1/33-7
AB4ÐAB5 Reserved 2 bytes Ñ
AB6 PTPRÑPIP timing parameters register 16 bits 33.4.4/33-10
AB8 PBDIRÑPort B data direction register 32 bits 34.3.1.3/34-10
24.12/24-14 (HDLC)
27.15/27-16 (BiSYNC)
29.13/29-13 (Transparent)
30.4.11/30-29 (Transparent)
30.5.9/30-36 (GCI)
30.4.11/30-29 (Transparent)
30.5.9/30-36 (GCI)
30.4.11/30-29 (Transparent)
30.5.9/30-36 (GCI)
30.4.11/30-29 (Transparent)
30.5.9/30-36 (GCI)
Ñ
bytes
Part I. Overview
MOTOROLA Chapter 2. Memory Map 2-9
Page 98
Part I. Overview
Table 2-1. MPC860 Internal Memory Map (Continued)
Offset Name Size Section/Page
ABC PBPARÑPort B pin assignment register 32 bits 34.3.1.4/34-11
AC2 PBODRÑPort B open drain register 16 bits 34.3.1.1/34-9
AC4 PBDATÑPort B data register 32 bits 34.3.1.2/34-10
AC8ÐADF Reserved 24 bytes Ñ
Serial Interface
AE0 SIMODEÑSI mode register 32 bits 21.2.4.2/21-17
AE4 SIGMRÑSI global mode register 8 bits 21.2.4.1/21-16
AE5 Reserved 8 bits Ñ
AE6 SISTRÑSI status register 8 bits 21.2.4.5/21-25
AE7 SICMRÑSI command register 8 bits 21.2.4.4/21-24
AE8ÐAEB Reserved 4 bytes Ñ
AEC SICRÑSI clock route register 32 bits 21.2.4.3/21-23
AF0 SIRPÑSerial interface RAM pointer register 32 bits 21.2.4.6/21-26
AF4ÐBFF Reserved 268
Specialized RAM
C00ÐDFF SIRAMÑSI routing RAM 512
E00Ð1FFF Reserved 4,608
Dual-Ported RAM
2000Ð2FFF DPRAMÑDual-ported RAM 4,096
3000Ð3BFF DPRAMÑDual-ported RAM expansion (reserved) 3,072
3C00Ð3FFF PRAMÑParameter RAM 1,024
Ñ
bytes
21.2.3.7/21-14
bytes
Ñ
bytes
19.6/19-9
bytes
Ñ
bytes
19.6.3/19-11
bytes
2-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Page 99
Chapter 3
Hardware Interface Overview
30
30
This chapter provides a brief overview of the hardware interface. Detailed information
about the signals listed here and how they interact is provided in Part IV, ÒHardware
Interface.Ó
The MPC860 bus interface features are listed as follows:
¥ 32-bit address bus with transfer size indication
¥ 32-bit data bus
¥ TTL-compatible interface
¥ Compatible with PowerPC architecture
¥ Easy to interface to slave devices
¥ Bus is synchronous (all signals are referenced to rising edge of bus clock)
¥ Contains supports for data parity
The MPC860 bus interface signals are shown in Figure 3-1.
MOTOROLA Chapter 3. Hardware Interface Overview 3-1
Page 100
Part I. Overview
V
DDSYN/VSSSYN/VSSSYN1/VDDH/VDDL/VSS
TIN1/L1RCLKA/BRGO1/CLK1/PA7
BRGCLK1/T OUT1 /CLK2/PA6
TIN2/L1TCLKA/BRGO2/CLK3/PA5
BRGCLK2/L1RCLKB/T OUT3 /CLK6/PA2
CTS3 /SDACK2 /L1TSYNCB/PC7
CTS4 /SDACK1 /L1TSYNCA/PC5
TOUT2 /CLK4/PA4
TIN3/BRGO3/CLK5/PA3
TIN4/BRGO4/CLK7/PA1
L1TCLKB/T OUT4/CLK8/PA0
REJECT1 /SPISEL/PB31
SPICLK/PB30/
BRGO4/SPIMISO /PB28
BRGO1/I2CSDA/PB27
BRGO2/I2CSCL/PB26
SMSYN1 /SDACK1 /PB23
SMSYN2 /SDACK2 /PB22
SMTxD2/L1CLKOB/PB21
SMRxD2/L1CLKOA/PB20
L1ST1/R TS1/PB19
L1ST2/R TS2/PB18
L1ST3/L1RQB /PB17
L1ST4/L1RQA /PB16
L1ST1/R TS1/DREQ0 /PC15
L1ST2V/R TS2 /DREQ1 /PC14
L1ST3/L1RQB /PC13
L1ST4/L1RQA /PC12
TGATE1 /CD1/PC10
TGATE2 /CD2/PC8
CD3 /L1RSYNCB/PC6
CD4 /L1RSYNCA/PC4
L1TSYNCA/PD15
L1RSYNCA/PD14
L1TSYNCB/PD13
L1RSYNCB/PD12
/KAPWR
RxD1/PA15
TxD1/PA14
RxD2/PA13
TxD2/PA12
L1TxDB/PA11
L1RxDB/PA10
L1TxDA/PA9
L1RxDA/PA8
RSTRT2
SPIMOSI/PB29
SMTxD1/PB25
SMRxD1/PB24
BRGO3/PB15
RSTR T1/PB14
CTS1 /PC11
CTS2 /PC9
RxD3/PD11
TxD3/PD10
RxD4/PD9
TxD4/PD8
RTS3 /PD7
RTS4 /PD6
REJECT2 /PD5
REJECT3 /PD4
REJECT4 /PD3
TMS
DSDI/TDI
DSCK/TCK
TRST
DSDO/TDO
AS
129
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
MPC860
32
1
1
1
1
1
1
1
1
1
1
1
1
32
4
1
1
1
1
2
1
6
1
1
1
1
1
1
4
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
5
1
1
2
1
1
1
1
1
2
1
1
1
1
1
A[0Ð31]
TSIZ0/REG
TSIZ1
R/W
BURST
BDIP/GPL_B5
TS
TA
TEA
BI
IRQ2/RSV
IRQ4/KR/RETR Y/SPKROUT
/IRQ3
CR
D[0Ð31]
DP[0Ð3]/IRQ
BR
BG
BB
FRZ/IRQ6
IRQ[0Ð1]
IRQ7
CS[0Ð5]
CS6
CS7
WE0
WE1 /BS_B1 /IOWR
WE2 /BS_B2 /PCOE
WE3 /BS_B3 /PCWE
BS_A [0Ð3]
GPL_A0
OE/GPL_A1 /GPL_B1
GPL_A [2Ð3]/GPL_B[2Ð3]/CS[2Ð3]
UPWAITA/GPL_A4
UPWAITB/GPL_B4
GPL_A5
PORESET
RSTCONF
HRESET
SRESET
XTAL
EXTAL
XFC
CLKOUT
EXTCLK
TEXP
ALE_A
CE1_A
CE2_A
WAIT_A
IP_A[0Ð1]
IP_A2/IOIS16_A
IP_A[3Ð7]
ALE_B/DSCK/AT1
W
IP_B[0Ð1]/WP[0Ð1]/VFLS[0Ð1]
IP_B2/IOIS16_B
IP_B3/WP2/VF2
IP_B4/LWP0/VF0
IP_B5/LWP1/VF1
IP_B6/DSDI/AT0
IP_B7/PTR/VAT3
OP[0Ð1]
OP2/MODCK1/STS
OP3/MODCK2/DSDO
BADDR30/REG
BADDR[28Ð29]
/CE1_B
/CE2_B
/BS_B0 /IORD
/GPL_B0
AIT_B
[3Ð6]
/AT2
Figure 3-1. MPC860 External Signals
3-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Loading...