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Hardware Specification
MPC850ABEC/D
Rev. 1, 10/2002
MPC850 (Rev. A/B/C) Family
Communications Controller
Hardware Specifications
This document contains detailed information on power considerations, AC/DC electrical
characteristics, and AC timing specifications for revision A,B, and C of the MPC850 Family.
This document contains the following topics:
Topic Page
Part I, “Overview” 1
Part II, “Features” 3
Part III, “Electrical and Thermal Characteristics” 7
Part IV, “Thermal Characteristics” 9
Part V, “Power Considerations” 10
Part VI, “Bus Signal Timing” 12
Part VII, “IEEE 1149.1 Electrical Specifications” 42
Part VIII, “CPM Electrical Characteristics” 43
Part IX, “Mechanical Data and Ordering Information” 66
Part X, “Document Revision History” 72
Part I Overview
The MPC850 is a versatile, one-chip integrated microprocessor and peripheral
combination that can be used in a variety of controller applications, excelling
particularly in communications and networking products. The MPC850, which
includes support for Ethernet, is specifically designed for cost-sensitive,
remote-access, and telecommunications applications. It is provides functions
similar to the MPC860, with system enhancements such as universal serial bus
(USB) support and a larger (8-Kbyte) dual-port RAM.
In addition to a high-performance embedded MPC8xx core, the MPC850
integrates system functions, such as a versatile memory controller and a
communications processor module (CPM) that incorporates a specialized,
independent RISC communications processor (referred to as the CP). This
separate processor off-loads peripheral tasks from the embedded MPC8xx core.
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2
The CPM of the MPC850 supports up to seven serial channels, as follows:
• One or two serial communications controllers (SCCs). The SCCs support Ethernet,
ATM (MPC850SR and MPC850DSL), HDLC and a number of other protocols,
along with a transparent mode of operation.
• One USB channel
• Two serial management controllers (SMCs)
• One I
2
C port
• One serial peripheral interface (SPI).
Table 1-1 shows the functionality supported by the members of the MPC850 family.
Table 1-1. MPC850 Functionality Matrix
Number of
Part
MPC850 1 Yes - Yes - 1
MPC850DE 2 Yes - Yes - 1
MPC850SR 2 Yes Yes Yes Yes 1
MPC850DSL 2 Yes Yes Yes No 1
SCCs
Supported
Ethernet
Support
ATM Support USB Support
Multi-channel
HDLC Support
Number of
PCMCIA Slots
Supported
Additional documentation may be provided for parts listed in Table 1-1.
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Part II Features
Figure 2-1 is a block diagram of the MPC850, showing its major components and the
relationships among those components:
Embedded
MPC8xx
Core
Baud Rate
Generators
Parallel I/O
Ports
UTOPIA
(850SR & DSL)
2-Kbyte
I-Cache
Instruction
Bus
Load/Store
Bus
Four
Timers
32-Bit RISC Communications
Processor (CP) and Program ROM
Timer
Instruction
MMU
1-Kbyte
D-Cache
Data
MMU
Interrupt
Controller
Dual-Port
RAM
Unified Bus
Serial DMA
Peripheral Bus
20 Virtual
Channels
and
2 Virtual
IDMA
Channels
System Interface Unit
Memory Controller
Bus Interface Unit
System Functions
Real-Time Clock
PCMCIA Interface
Communications
Processor
Module
TDMa
SCC2
SCC3
Time Slot Assigner
SMC1 SMC2
USB
Non-Multiplexed Serial Interface
SPI
2
C
I
Figure 2-1. MPC850 Microprocessor Block Diagram
The following list summarizes the main features of the MPC850:
• Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC
architecture) with thirty-two 32-bit general-purpose registers (GPRs)
— Performs branch folding and branch prediction with conditional prefetch, but
without conditional execution
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— 2-Kbyte instruction cache and 1-Kbyte data cache (Harvard architecture)
– Caches are two-way, set-associative
– Physically addressed
– Cache blocks can be updated with a 4-word line burst
– Least-recently used (LRU) replacement algorithm
– Lockable one-line granularity
— Memory management units (MMUs) with 8-entry translation lookaside buffers
(TLBs) and fully-associative instruction and data TLBs
— MMUs support multiple page sizes of 4 Kbytes, 16 Kbytes, 256 Kbytes, 512
Kbytes, and 8 Mbytes; 16 virtual address spaces and eight protection groups
• Advanced on-chip emulation debug mode
• Data bus dynamic bus sizing for 8, 16, and 32-bit buses
— Supports traditional 68000 big-endian, traditional x86 little-endian and modified
little-endian memory systems
— Twenty-six external address lines
• Completely static design (0–80 MHz operation)
• System integration unit (SIU)
— Hardware bus monitor
— Spurious interrupt monitor
— Software watchdog
— Periodic interrupt timer
— Low-power stop mode
— Clock synthesizer
— Decrementer, time base, and real-time clock (RTC) from the PowerPC
architecture
— Reset controller
— IEEE 1149.1 test access port (JTAG)
• Memory controller (eight banks)
— Glueless interface to DRAM single in-line memory modules (SIMMs),
synchronous DRAM (SDRAM), static random-access memory (SRAM),
electrically programmable read-only memory (EPROM), flash EPROM, etc.
— Memory controller programmable to support most size and speed memory
interfaces
— Boot chip-select available at reset (options for 8, 16, or 32-bit memory)
— Variable block sizes, 32 Kbytes to 256 Mbytes
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— Selectable write protection
— On-chip bus arbiter supports one external bus master
— Special features for burst mode support
• General-purpose timers
— Four 16-bit timers or two 32-bit timers
— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture
• Interrupts
— Eight external interrupt request (IRQ) lines
— Twelve port pins with interrupt capability
— Fifteen internal interrupt sources
— Programmable priority among SCCs and USB
— Programmable highest-priority request
• Single socket PCMCIA-ATA interface
— Master (socket) interface, release 2.1 compliant
— Single PCMCIA socket
— Supports eight memory or I/O windows
• Communications processor module (CPM)
— 32-bit, Harvard architecture, scalar RISC communications processor (CP)
— Protocol-specific command sets (for example,
GRACEFUL
STOP
TRANSMIT
transmission after the current frame is finished or immediately if no frame is
being sent and
CLOSE
RXBD
closes the receive buffer descriptor)
— Supports continuous mode transmission and reception on all serial channels
— Up to 8 Kbytes of dual-port RAM
— Twenty serial DMA (SDMA) channels for the serial controllers, including eight
for the four USB endpoints
— Three parallel I/O registers with open-drain capability
• Four independent baud-rate generators (BRGs)
stops
— Can be connected to any SCC, SMC, or USB
— Allow changes during operation
— Autobaud support option
• Two SCCs (serial communications controllers)
— Ethernet/IEEE 802.3, supporting full 10-Mbps operation
— HDLC/SDLC™
(all channels supported at 2 Mbps)
— HDLC bus (implements an HDLC-based local area network (LAN))
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— Asynchronous HDLC to support PPP (point-to-point protocol)
®
— AppleTalk
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC))
• QUICC multichannel controller (QMC) microcode features
— Up to 64 independent communication channels on a single SCC
— Arbitrary mapping of 0–31 channels to any of 0–31 TDM time slots
— Supports either transparent or HDLC protocols for each channel
— Independent TxBDs/Rx and event/interrupt reporting for each channel
• One universal serial bus controller (USB)
— Supports host controller and slave modes at 1.5 Mbps and 12 Mbps
• Two serial management controllers (SMCs)
— UART
— Transparent
— General circuit interface (GCI) controller
— Can be connected to the time-division-multiplexed (TDM) channel
• One serial peripheral interface (SPI)
— Supports master and slave modes
— Supports multimaster operation on the same bus
2
• One I
®
C
(interprocessor-integrated circuit) port
— Supports master and slave modes
— Supports multimaster environment
• Time slot assigner
— Allows SCCs and SMCs to run in multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate,
user-defined
— 1- or 8-bit resolution
— Allows independent transmit and receive routing, frame syncs, clocking
— Allows dynamic changes
— Can be internally connected to four serial channels (two SCCs and two SMCs)
• Low-power support
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— Full high: all units fully powered at high clock frequency
— Full low: all units fully powered at low clock frequency
— Doze: core functional units disabled except time base, decrementer, PLL,
memory controller, real-time clock, and CPM in low-power standby
— Sleep: all units disabled except real-time clock and periodic interrupt timer . PLL
is active for fast wake-up
— Deep sleep: all units disabled including PLL, except the real-time clock and
periodic interrupt timer
— Low-power stop: to provide lower power dissipation
— Separate power supply input to operate internal logic at 2.2 V when operating at
or below 25 MHz
— Can be dynamically shifted between high frequency (3.3 V internal) and low
frequency (2.2 V internal) operation
• Debug interface
— Eight comparators: four operate on instruction address, two operate on data
address, and two operate on data
— The MPC850 can compare using the =,
watchpoints
— Each watchpoint can generate a breakpoint internally
• 3.3-V operation with 5-V TTL compatibility on all general purpose I/O pins.
≠
, <, and > conditions to generate
Part III Electrical and Thermal
Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics
for the MPC850. Table 3-2 provides the maximum ratings.
MOTOROLA
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1
Table 3-2. Maximum Ratings
(GND = 0V)
Rating Symbol Value Unit
Supply voltage VDDH -0.3 to 4.0 V
VDDL -0.3 to 4.0 V
KAPWR -0.3 to 4.0 V
VDDSYN -0.3 to 4.0 V
Input voltage
Junction temperature
V
in
2
T
j
GND-0.3 to VDDH + 2.5 V V
0 to 95 (standard)
-40 to 95 (extended)
˚C
Storage temperature range T
1
Functional operating conditions are provided with the DC electrical specifications in Table 4-5. Absolute maximum
ratings are stress ratings only; functional oper ation at the maxima is not guaranteed. Stress beyond those listed may
affect device reliability or cause permanent damage to the device.
CAUTION: All inputs that tolerate 5 V cannot be more than 2.5 V greater than the supply voltage. This restriction
applies to power-up and normal operation (that is, if the MPC850 is unpowered, v oltage greater than 2.5 V must not
be applied to its inputs).
2
The MPC850, a high-frequency device in a BGA package, does not provide a guaranteed maximum ambient
temperature. Only maximum junction temperature is guar anteed. It is the responsibility of the user to consider power
dissipation and thermal management. Junction temperature ratings are the same regardless of frequency rating of
the device.
stg
-55 to +150 ˚C
This device contains circuitry protecting against damage due to high-static voltage or
electrical fields; howev er , it is advised that normal precautions be taken to av oid application
of any voltages higher than maximum-rated voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage
level (for example, either GND or V
). Table 4-3 provides the package thermal
CC
characteristics for the MPC850.
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1
1
2
Part IV Thermal Characteristics
Table 4-3 shows the thermal characteristics for the MPC850.
Table 4-3. Thermal Characteristics
Characteristic Symbol Value Unit
Thermal resistance for BGA
Thermal Resistance for BGA (junction-to-case)
1
For more information on the design of thermal vias on multilayer boards and BGA layout considerations in
general, refer to AN-1231/D,
office.
2
Assumes natural convection and a single layer board (no thermal vias).
3
Assumes natural convection, a multilayer board with thermal vias
temperature rise of 20
4
Assumes natural convection, a multilayer board with thermal vias
temperature rise of 13
T
= T
J
A
P
= (V
D
where:
P
is the power dissipation on pins
I/O
+ (P
DD
D
•
°
C above ambient.
)
θ
JA
•
I
) + P
DD
I/O
Plastic Ball Grid Array Application Note
°
C above ambient.
θ
JA
θ
JA
θ
JA
θ
JC
available from your local Motorola sales
4
, 1 watt MPC850 dissipation, and a board
4
, 1 watt MPC850 dissipation, and a board
40
31
24
2
3
4
8
°
C/W
°
C/W
C/W
°
°
C/W
Table 4-4 provides power dissipation information.
Table 4-4. Power Dissipation (P
Characteristic Frequency (MHz) Typical
Power Dissipation
All Revisions
(1:1) Mode
1
Typical power dissipation is measured at 3.3V
2
Maximum power dissipation is measured at 3.65 V
33 TBD 515 mW
40 TBD 590 mW
50 TBD 725 mW
)
D
Maximum
Table 4-5 provides the DC electrical characteristics for the MPC850.
Table 4-5. DC Electrical Specifications
Characteristic Symbol Min Max Unit
Operating voltage at 40 MHz or less VDDH, VDDL,
KAPWR, VDDSYN
Operating voltage at 40 MHz or higher VDDH, VDDL,
KAPWR, VDDSYN
Input high voltage (address bus, data bus, EXTAL, EXTCLK,
and all bus control/status signals)
VIH 2.0 3.6 V
3.135 3.465 V
Unit
3.0 3.6 V
Input high voltage (all general purpose I/O and peripheral pins) VIH 2.0 5.5 V
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Table 4-5. DC Electrical Specifications (continued)
Characteristic Symbol Min Max Unit
Input low voltage VIL GND 0.8 V
EXTAL, EXTCLK input high voltage VIHC 0.7*(VCC) VCC+0.3 V
Input leakage current, Vin = 5.5 V (Except TMS, TRST
and DSDI pins)
, DSCK
I
in
— 100 µA
Input leakage current, Vin = 3.6V (Except TMS, TRST
and DSDI pins)
Input leakage current, Vin = 0V (Except TMS, TRST
DSDI pins)
Input capacitance C
Output high voltage, IOH = -2.0 mA, VDDH = 3.0V
except XTAL, XFC, and open-drain pins
Output low voltage
IOL = 2.0 mA CLKOUT
IOL = 3.2 mA
IOL = 5.3 mA
IOL = 7.0 mA PA[14]/USBOE, PA[12]/TXD2
IOL = 8.9 mA TS
1
A[6:31], TSIZ0/REG, TSIZ1, D[0:31], DP[0:3]/IRQ[3:6], RD/WR, BURST, RSV/IRQ2, IP_B[0:1]/IWP[0:1]/VFLS[0:1],
IP_B2/IOIS16_B
PA[15]/USBRXD, PA[13]/RXD2, PA[9]/L1TXDA/SMRXD2, PA[8]/L1RXDA/SMTXD2,
PA[7]/CLK1/TIN1/L1RCLKA/BRGO1, PA[6]/CLK2/T
PA[4]/CLK4/T
PB[28]/SPIMISO/BRGO3, PB[27]/I2CSDA/BRGO1, PB[26]/I2CSCL/BRGO2, PB[25]/SMTXD1/TXD3,
PB[24]/SMRXD1/RXD3, PB[23]/SMSYN1
PB[18]/R
PC[13]/L1ST7/R
PC[8]/CD2
PD[15], PD[14], PD[13], PD[12], PD[11], PD[10], PD[9], PD[8], PD[7], PD[6], PD[5], PD[4], PD[3]
1
2
, T A, TEA, BI, BB, HRESET, SRESET
/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/VF1, IP_B6/DSDI/AT0, IP_B7/PTR/AT3,
OUT2/TIN4, PB[31]/SPISEL, PB[30]/SPICLK/TXD3, PB[29]/SPIMOSI /RXD3,
/SDACK1, PB[22]/SMSYN2/SDACK2, PB[19]/L1ST1,
TS2/L1ST2, PB[17]/L1ST3, PB[16]/L1RQa/L1ST4, PC[15]/DREQ0/L1ST5, PC[14]/DREQ1/RTS2/L1ST6,
TS3, PC[12]/L1RQa/L1ST8, PC[11]/USBRXP, PC[10]/TGATE1/USBRXN, PC[9]/CTS2,
/TGATE1, PC[7]/USBTXP, PC[6]/USBTXN, PC[5]/CTS3/L1TSYNCA/SDACK1, PC[4]/CD3/L1RSYNCA,
, DSCK
, DSCK and
OUT1/TIN3, PA[5]/CLK3/TIN2/L1TCLKA/BRGO2,
I
In
I
In
in
VOH 2.4 — V
VOL — 0.5 V
—10µA
—10µA
—20pF
2
BDIP/GPL_B5, BR, BG, FRZ/IRQ6, CS[0:5], CS6/CE1_B, CS7/CE2_B, WE0/BS_AB0/IORD, WE1/BS_AB1/IOWR,
WE2
/BS_AB2/PCOE, WE3/BS_AB3/PCWE, GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1,
GPL_A
[2:3]/GPL_B[2:3]/CS[2:3], UPWAITA/GPL_A4/AS, UPWAITB/GPL_B4, GPL_A5, ALE_B/DSCK/AT1,
OP2/MODCK1/STS
, OP3/MODCK2/DSDO
Part V Power Considerations
The average chip-junction temperature
T
= T
A
+ (P
J
θ
) (1)
•
D
JA
where
T
= Ambient temperature
A
θ
= Package thermal resistance
JA
MPC850 (Rev . A/B/C) Har dware Specifications MOT OROLA
,
,
T
,
in
°
C can be obtained from the equation:
J
C
°
,
junction to ambient
,
°
C/W
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Layout Practices
P
D
= P
+ P
P
P
INT
INT
I/O
I/O
= I
DD
x V
,
watts—chip internal power
DD
= Power dissipation on input and output pins—user determined
For most applications P
< 0.3
I/O
approximate relationship between P
P
= K
÷
(T
+ 273
°
D
J
C) (2)
•
D
P
and can be neglected. If P
INT
and T
is:
J
is neglected
I/O
,
an
Solving equations (1) and (2) for K gives:
K = P
•
(T
+ 273
D
A
°
C) +
θ
JA
• P
2
(3)
D
where K is a constant pertaining to the particular part. K can be determined from equation
(3) by measuring P
P
and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA.
D
(at equilibrium) for a known TA. Using this value of K, the values of
D
5.1 Layout Practices
Each VCC pin on the MPC850 should be provided with a low-impedance path to the board’s
supply. Each GND pin should likewise be provided with a low-impedance path to ground.
The power supply pins driv e distinct groups of logic on chip. The V
be bypassed to ground using at least four 0.1 µF by-pass capacitors located as close as
possible to the four sides of the package. The capacitor leads and associated printed circuit
traces connecting to chip V
and GND should be kept to less than half an inch per capacitor
CC
lead. A four-layer board is recommended, employing two inner layers as V
planes.
power supply should
CC
and GND
CC
All output pins on the MPC850 have fast rise and fall times. Printed circuit (PC) trace
interconnection length should be minimized in order to minimize undershoot and
reflections caused by these fast output switching times. This recommendation particularly
applies to the address and data busses. Maximum PC trace lengths of six inches are
recommended. Capacitance calculations should consider all device loads as well as
parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing
becomes especially critical in systems with higher capacitive loads because these loads
create higher transient currents in the V
and GND circuits. Pull up all unused inputs or
CC
signals that will be inputs during reset. Special care should be taken to minimize the noise
levels on the PLL supply pins.
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Layout Practices
Part VI Bus Signal Timing
Table 6-6 provides the bus operation timing for the MPC850 at 50 MHz, 66 MHz, and 80
MHz. Timing information for other bus speeds can be interpolated by equation using the
MPC850 Electrical Specifications Spreadsheet found at http://www.mot.com/netcomm.
The maximum bus speed supported by the MPC850 is 50 MHz. Higher-speed parts must
be operated in half-speed bus mode (for example, an MPC850 used at 66 MHz must be
configured for a 33 MHz bus).
The timing for the MPC850 bus shown assumes a 50-pF load. This timing can be derated
by 1 ns per 10 pF . Derating calculations can also be performed using the MPC850 Electrical
Specifications Spreadsheet.
Table 6-6. Bus Operation Timing 1
50 MHz 66 MHz 80 MHz
Num Characteristic
Min Max Min Max Min Max
B1 CLKOUT period 20 — 30.30 — 25 — — — ns
B1a EXTCLK to CLKOUT phase
skew (EXTCLK > 15 MHz and
MF <= 2)
B1b EXTCLK to CLKOUT phase
skew (EXTCLK > 10 MHz and
MF < 10)
B1c CLKOUT phase jitter (EXTCLK
> 15 MHz and MF <= 2)
B1d CLKOUT phase jitter
B1e CLKOUT frequency jitter (MF <
B1f CLKOUT frequency jitter (10 <
B1g CLKOUT frequency jitter (MF >
B1h Frequency jitter on EXTCLK
B2 CLKOUT pulse width low 8.00 — 12.12 — 10.00 — — 50.00 ns
2
10)
MF < 500)
2
500)
2
2
2
-0.90 0.90 -0.90 0.90 -0.90 0.90 — 50.00 ns
-2.30 2.30 -2.30 2.30 -2.30 2.30 — 50.00 ns
-0.60 0.60 -0.60 0.60 -0.60 0.60 — 50.00 ns
-2.00 2.00 -2.00 2.00 -2.00 2.00 — 50.00 ns
— 0.50 — 0.50 — 0.50 — 50.00 %
— 2.00 — 2.00 — 2.00 — 50.00 %
— 3.00 — 3.00 — 3.00 — 50.00 %
3
— 0.50 — 0.50 — 0.50 — 50.00 %
FFACT
Cap Load
(default
50 pF)
Unit
B3 CLKOUT width high 8.00 — 12.12 — 10.00 — — 50.00 ns
B4 CLKOUT rise time — 4.00 — 4.00 — 4.00 — 50.00 ns
B5 CLKOUT fall time — 4.00 — 4.00 — 4.00 — 50.00 ns
B7 CLKOUT to A[6–31],
RD/WR
DP[0–3] invalid
B7a CLKOUT to TSIZ[0–1], REG
RSV
, BURST, D[0–31],
, AT[0–3], BDIP, PTR invalid
5.00 — 7.58 — 6.25 — 0.250 50.00 ns
,
5.00 — 7.58 — 6.25 — 0.250 50.00 ns
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Table 6-6. Bus Operation Timing 1 (continued)
Layout Practices
Num Characteristic
B7b CLKOUT to BR, BG, FRZ,
VFLS[0–1], VF[0–2] IWP[0–2],
LWP[0–1], STS
invalid
4
B8 CLKOUT to A[6–31],
RD/WR
, BURST, D[0–31],
DP[0–3] valid
B8a CLKOUT to TSIZ[0–1], REG
RSV
, AT[0–3] BDIP, PTR valid
B8b CLKOUT to BR
VF[0–2], IWP[0–2], FRZ,
LWP[0–1], STS
, BG, VFLS[0–1],
4
valid
B9 CLKOUT to A[6–31] RD/WR
B
URST, D[0–31], DP[0–3],
TSIZ[0–1], REG
PTR
high-Z
B11 CLKOUT to TS
B11a CLKOUT to T
, RSV, AT[0–3],
, BB assertion 5.00 11.00 7.58 13.58 6.25 12.25 0.250 50.00 ns
A, BI assertion,
(When driven by the memory
controller or PCMCIA interface)
50 MHz 66 MHz 80 MHz
FFACT
Min Max Min Max Min Max
Cap Load
(default
50 pF)
5.00 — 7.58 — 6.25 — 0.250 50.00 ns
5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns
,
5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns
5.00 11.74 7.58 14.33 6.25 13.00 0.250 50.00 ns
5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns
,
2.50 9.25 2.50 9.25 2.50 9.25 — 50.00 ns
Unit
B12 CLKOUT to TS
B12a CLKOUT to T
, BB negation 5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns
A, BI negation
(when driven by the memory
controller or PCMCIA interface)
B13 CLKOUT to TS
B13a CLKOUT to T
, BB high-Z 5.00 19.00 7.58 21.58 6.25 20.25 0.250 50.00 ns
A, BI high-Z, (when
driven by the memory controller
or PCMCIA interface)
B14 CLKOUT to TEA
B15 CLKOUT to TEA
B16 T
B16a TEA
A, BI valid to CLKOUT(setup
5
time)
, KR, RETRY, valid to
CLKOUT (setup time
B16b BB
, BG, BR valid to CLKOUT
(setup time)
B17 CLKOUT to T
BR
valid (Hold time).
B17a CLKOUT to KR
TEA
valid (hold time)
assertion 2.50 10.00 2.50 10.00 2.50 10.00 — 50.00 ns
high-Z 2.50 15.00 2.50 15.00 2.50 15.00 — 50.00 ns
) 5
6
A, TEA, BI, BB, BG,
5
, RETRY, except
B18 D[0–31], DP[0–3] valid to
CLKOUT rising edge (setup
7
time)
2.50 11.00 2.50 11.00 2.50 11.00 — 50.00 ns
2.50 15.00 2.50 15.00 2.50 15.00 — 50.00 ns
9.75 — 9.75 — 9.75 — — 50.00 ns
10.00 — 10.00 — 10.00 — — 50.00 ns
8.50 — 8.50 — 8.50 — — 50.00 ns
1.00 — 1.00 — 1.00 — — 50.00 ns
2.00 — 2.00 — 2.00 — — 50.00 ns
6.00 — 6.00 — 6.00 — — 50.00 ns
MOTOROLA MPC850 (Rev . A/B/C) Har dware Specifications 13
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Layout Practices
Table 6-6. Bus Operation Timing 1 (continued)
Num Characteristic
B19 CLKOUT rising edge to D[0–31],
DP[0–3] valid (hold time)
B20 D[0–31], DP[0–3] valid to
CLKOUT falling edge (setup
8
time)
B21 CLKOUT falling edge to
D[0–31], DP[0–3] valid (hold
8
time)
B22 CLKOUT rising edge to CS
asserted GPCM ACS = 00
B22a CLKOUT falling edge to CS
asserted GPCM ACS = 10,
TRLX = 0,1
B22b CLKOUT falling edge to CS
asserted GPCM ACS = 11,
TRLX = 0, EBDF = 0
B22c CLKOUT falling edge to CS
asserted GPCM ACS = 11,
TRLX = 0, EBDF = 1
B23 CLKOUT rising edge to CS
negated GPCM read access,
GPCM write access ACS = 00,
TRLX = 0 & CSNT = 0
B24 A[6–31] to CS
ACS = 10, TRLX = 0.
asserted GPCM
7
50 MHz 66 MHz 80 MHz
FFACT
Min Max Min Max Min Max
1.00 — 1.00 — 1.00 — — 50.00 ns
4.00 — 4.00 — 4.00 — — 50.00 ns
2.00 — 2.00 — 2.00 — — — —
5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns
— 8.00 — 8.00 — 8.00 — 50.00 ns
5.00 11.75 7.58 14.33 6.25 13.00 0.250 50.00 ns
7.00 14.00 11.00 18.00 9.00 16.00 0.375 50.00 ns
2.00 8.00 2.00 8.00 2.00 8.00 — 50.00 ns
3.00 — 6.00 — 4.00 — 0.250 50.00 ns
Cap Load
(default
50 pF)
Unit
B24a A[6–31] to CS
ACS = 11, TRLX = 0
B25 CLKOUT rising edge to OE
WE[0–3]
B26 CLKOUT rising edge to OE
negated
B27 A[6–31] to CS
ACS = 10, TRLX = 1
B27a A[6–31] to CS
ACS = 11, TRLX = 1
B28 CLKOUT rising edge to WE[0–3]
negated GPCM write access
CSNT = 0
B28a CLKOUT falling edge to
WE[0–3]
access TRLX = 0,1 CSNT = 1,
EBDF = 0
asserted GPCM
,
asserted
asserted GPCM
asserted GPCM
negated GPCM write
8.00 — 13.00 — 11.00 — 0.500 50.00 ns
— 9.00 — 9.00 — 9.00 — 50.00 ns
2.00 9.00 2.00 9.00 2.00 9.00 — 50.00 ns
23.00 — 36.00 — 29.00 — 1.250 50.00 ns
28.00 — 43.00 — 36.00 — 1.500 50.00 ns
— 9.00 — 9.00 — 9.00 — 50.00 ns
5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns
14 MPC850 (Rev . A/B/C) Har dware Specifications MOT OROLA
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Table 6-6. Bus Operation Timing 1 (continued)
Layout Practices
Num Characteristic
B28b CLKOUT falling edge to CS
negated GPCM write access
TRLX = 0,1 CSNT = 1, ACS = 10
or ACS = 11, EBDF = 0
B28c CLKOUT falling edge to
WE[0–3]
access TRLX = 0,1 CSNT = 1
write access TRLX = 0, CSNT =
1, EBDF = 1
B28d CLKOUT falling edge to CS
negated GPCM write access
TRLX = 0,1 CSNT = 1, ACS = 10
or ACS = 11, EBDF = 1
B29 WE[0–3]
DP[0–3] high-Z GPCM write
access, CSNT = 0
B29a WE[0–3]
DP[0–3] high-Z GPCM write
access, TRLX = 0 CSNT = 1,
EBDF = 0
B29b CS
DP[0–3], high-Z GPCM write
access, ACS = 00, TRLX = 0 &
CSNT = 0
B29c CS
high-Z GPCM write access,
TRLX = 0, CSNT = 1, ACS = 10
or ACS = 11, EBDF = 0
B29d WE[0–3]
DP[0–3] high-Z GPCM write
access, TRLX = 1, CSNT = 1,
EBDF = 0
B29e CS
high-Z GPCM write access,
TRLX = 1, CSNT = 1, ACS = 10
or ACS = 11, EBDF = 0
B29f WE[0–3]
DP[0–3] high-Z GPCM write
access TRLX = 0, CSNT = 1,
EBDF = 1
B29g CS
high-Z GPCM write access
TRLX = 0, CSNT = 1, ACS = 10
or ACS = 11, EBDF = 1
negated GPCM write
negated to D[0–31],
negated to D[0–31],
negated to D[0–31],
negated to D[0–31], DP[0–3]
negated to D[0–31],
negated to D[0–31], DP[0–3]
negated to D[0–31],
negated to D[0–31], DP[0–3]
50 MHz 66 MHz 80 MHz
FFACT
Min Max Min Max Min Max
— 12.00 — 14.00 — 13.00 0.250 50.00 ns
7.00 14.00 11.00 18.00 9.00 16.00 0.375 50.00 ns
— 14.00 — 18.00 — 16.00 0.375 50.00 ns
3.00 — 6.00 — 4.00 — 0.250 50.00 ns
8.00 — 13.00 — 11.00 — 0.500 50.00 ns
3.00 — 6.00 — 4.00 — 0.250 50.00 ns
8.00 — 13.00 — 11.00 — 0.500 50.00 ns
28.00 — 43.00 — 36.00 — 1.500 50.00 ns
28.00 — 43.00 — 36.00 — 1.500 50.00 ns
5.00 — 9.00 — 7.00 — 0.375 50.00 ns
5.00 — 9.00 — 7.00 — 0.375 50.00 ns
Cap Load
(default
50 pF)
Unit
MOTOROLA MPC850 (Rev . A/B/C) Har dware Specifications 15
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Layout Practices
Table 6-6. Bus Operation Timing 1 (continued)
Num Characteristic
B29h WE[0–3] negated to D[0–31],
DP[0–3] high-Z GPCM write
access TRLX = 0, CSNT = 1,
EBDF = 1
B29i CS
B30 CS
B30a WE[0–3]
B30b WE[0–3]
B30c WE[0–3]
B30d WE[0–3]
B31 CLKOUT falling edge to CS
negated to D[0–31], DP[0–3]
high-Z GPCM write access,
TRLX = 1, CSNT = 1, ACS = 10
or ACS = 11, EBDF = 1
, WE[0–3] negated to A[6–31]
invalid
GPCM write access
negated to A[6–31]
invalid
GPCM write access, TRLX = 0,
CSNT = 1, CS
A[6–31] invalid GPCM write
access TRLX = 0, CSNT =1,
ACS = 10 or ACS = 11, EBDF =
0
negated to A[6–31]
invalid
GPCM write access, TRLX = 1,
CSNT = 1. CS
A[6–31] Invalid GPCM write
access TRLX = 1, CSNT = 1,
ACS = 10 or ACS = 11, EBDF =
0
negated to A[6–31]
invalid
GPCM write access, TRLX = 0,
CSNT = 1. CS
A[6–31] invalid GPCM write
access, TRLX = 0, CSNT = 1,
ACS = 10 or ACS = 11, EBDF =
1
negated to A[6–31]
invalid GPCM write access
TRLX = 1, CSNT =1, CS
negated to A[6–31] invalid
GPCM write access TRLX = 1,
CSNT = 1, ACS = 10 or ACS =
11, EBDF = 1
- as requested by control bit
CST4 in the corresponding word
in the UPM
9
negated to
negated to
negated to
valid
50 MHz 66 MHz 80 MHz
FFACT
Min Max Min Max Min Max
25.00 — 39.00 — 31.00 — 1.375 50.00 ns
25.00 — 39.00 — 31.00 — 1.375 50.00 ns
3.00 — 6.00 — 4.00 — 0.250 50.00 ns
8.00 — 13.00 — 11.00 — 0.500 50.00 ns
28.00 — 43.00 — 36.00 — 1.500 50.00 ns
5.00 — 8.00 — 6.00 — 0.375 50.00 ns
25.00 — 39.00 — 31.00 — 1.375 50.00 ns
1.50 6.00 1.50 6.00 1.50 6.00 — 50.00 ns
Cap Load
(default
50 pF)
Unit
16 MPC850 (Rev . A/B/C) Har dware Specifications MOT OROLA
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Table 6-6. Bus Operation Timing 1 (continued)
Layout Practices
Num Characteristic
B31a CLKOUT falling edge to CS valid
- as requested by control bit
CST1 in the corresponding word
in the UPM
B31b CLKOUT rising edge to CS
- as requested by control bit
CST2 in the corresponding word
in the UPM
B31c CLKOUT rising edge to CS
- as requested by control bit
CST3 in the corresponding word
in the UPM
B31d CLKOUT falling edge to CS
- as requested by control bit
CST1 in the corresponding word
in the UPM EBDF = 1
B32 CLKOUT falling edge to BS
- as requested by control bit
BST4 in the corresponding word
in the UPM
B32a CLKOUT falling edge to BS
- as requested by control bit
BST1 in the corresponding word
in the UPM, EBDF = 0
B32b CLKOUT rising edge to BS
- as requested by control bit
BST2 in the corresponding word
in the UPM
B32c CLKOUT rising edge to BS
- as requested by control bit
BST3 in the corresponding word
in the UPM
B32d CLKOUT falling edge to BS
- as requested by control bit
BST1 in the corresponding word
in the UPM, EBDF = 1
B33 CLKOUT falling edge to GPL
valid - as requested by control
bit GxT4 in the corresponding
word in the UPM
B33a CLKOUT rising edge to GPL
valid - as requested by control
bit GxT3 in the corresponding
word in the UPM
valid
valid
valid
valid
valid
valid
valid
valid
50 MHz 66 MHz 80 MHz
FFACT
Min Max Min Max Min Max
5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns
1.50 8.00 1.50 8.00 1.50 8.00 — 50.00 ns
5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns
9.00 14.00 13.00 18.00 11.00 16.00 0.375 50.00 ns
1.50 6.00 1.50 6.00 1.50 6.00 — 50.00 ns
5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns
1.50 8.00 1.50 8.00 1.50 8.00 — 50.00 ns
5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns
9.00 14.00 13.00 18.00 11.00 16.00 0.375 50.00 ns
1.50 6.00 1.50 6.00 1.50 6.00 — 50.00 ns
5.00 12.00 8.00 14.00 6.00 13.00 0.250 50.00 ns
Cap Load
(default
50 pF)
Unit
MOTOROLA MPC850 (Rev . A/B/C) Har dware Specifications 17
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Layout Practices
Table 6-6. Bus Operation Timing 1 (continued)
Num Characteristic
B34 A[6–31] and D[0–31] to CS valid
- as requested by control bit
CST4 in the corresponding word
in the UPM
B34a A[6–31] and D[0–31] to CS
- as requested by control bit
CST1 in the corresponding word
in the UPM
B34b A[6–31] and D[0–31] to CS
- as requested by CST2 in the
corresponding word in UPM
B35 A[6–31] to CS
requested by control bit BST4 in
the corresponding word in UPM
B35a A[6–31] and D[0–31] to BS
- as requested by BST1 in the
corresponding word in the UPM
B35b A[6–31] and D[0–31] to BS
- as requested by control bit
BST2 in the corresponding word
in the UPM
B36 A[6–31] and D[0–31] to GPL
valid - as requested by control
bit GxT4 in the corresponding
word in the UPM
valid - as
valid
valid
valid
valid
50 MHz 66 MHz 80 MHz
FFACT
Min Max Min Max Min Max
3.00 — 6.00 — 4.00 — 0.250 50.00 ns
8.00 — 13.00 — 11.00 — 0.500 50.00 ns
13.00 — 21.00 — 17.00 — 0.750 50.00 ns
3.00 — 6.00 — 4.00 — 0.250 50.00 ns
8.00 — 13.00 — 11.00 — 0.500 50.00 ns
13.00 — 21.00 — 17.00 — 0.750 50.00 ns
3.00 — 6.00 — 4.00 — 0.250 50.00 ns
Cap Load
(default
50 pF)
Unit
B37 UPWAIT valid to CLK OUT falling
B38 CLKOUT falling edge to
B39 AS
B40 A[6–31], TSIZ[0–1], RD/WR
B41 TS
B42 CLKOUT rising edge to TS
B43 AS
10
edge
UPWAIT valid
valid to CLK OUT rising edge
11
B
URST, valid to CLKOUT rising
edge.
valid to CLK OUT rising edge
(setup time)
(hold time)
negation to memory
controller signals negation
10
valid
,
6.00 — 6.00 — 6.00 — — 50.00 ns
1.00 — 1.00 — 1.00 — — 50.00 ns
7.00 — 7.00 — 7.00 — — 50.00 ns
7.00 — 7.00 — 7.00 — — 50.00 ns
7.00 — 7.00 — 7.00 — — 50.00 ns
2.00 — 2.00 — 2.00 — — 50.00 ns
— TBD — TBD TBD — — 50.00 ns
18 MPC850 (Rev . A/B/C) Har dware Specifications MOT OROLA
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Layout Practices
1
The minima provided assume a 0 pF load, whereas maxima assume a 50pF load. For frequencies not marked on the
part, new bus timing must be calculated for all frequency-dependent AC parameters. Frequency-dependent AC
parameters are those with an entry in the FFactor column. AC parameters without an FFactor entry do not need to
be calculated and can be taken directly from the frequency column corresponding to the frequency marked on the
part. The following equations should be used in these calculations.
For a frequency F, the following equations should be applied to each one of the above parameters:
For minima:
FFACTOR x 1000
D =
F
- 20 x FFACTOR)
(D
50
+
For maxima:
FFACTOR x 1000
D =
F
-20 x FFACTOR)
(D
50
++
1ns(CAP LOAD - 50) / 10
where:
D is the parameter value to the frequency required in ns
F is the operation frequency in MHz
D
is the parameter value defined for 50 MHz
50
CAP LOAD is the capacitance load on the signal in question.
FFACTOR is the one defined for each of the parameters in the table.
2
Phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed value.
3
If the rate of change of the frequency of EXTAL is slow (i.e. it does not jump between the minimum and maximum
values in one cycle) or the frequency of the jitter is fast (i.e., it does not sta y at an e xtreme v alue f or a long time) then
the maximum allowed jitter on EXTAL can be up to 2%.
4
The timing for BR output is relev ant when the MPC850 is selected to work with external bus arbiter . The timing for BG
output is relevant when the MPC850 is selected to work with internal bus arbiter.
5
The setup times required for TA, TEA, and BI are relevant only when they are supplied b y an external de vice (and not
when the memory controller or the PCMCIA interface drives them).
6
The timing required for BR input is relevant when the MPC850 is selected to work with the internal bus arbiter. The
timing for BG
7
The D[0–31] and DP[0–3] input timings B20 and B21 refer to the rising edge of the CLKOUT in which the TA input
input is relevant when the MPC850 is selected to work with the external bus arbiter.
signal is asserted.
8
The D[0:31] and DP[0:3] input timings B20 and B21 refer to the falling edge of CLKOUT. This timing is valid only for
read accesses controlled by chip-selects controlled by the UPM in the memory controller, f or data beats where DLT3
= 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.
9
The timing B30 refers to CS when ACS = '00' and to WE[0:3] when CSNT = '0'.
10
The signal UPWAIT is considered asynchronous to CLKOUT and synchronized internally. The timings specified in
B37 and B38 are specified to enable the freeze of the UPM output signals.
11
The AS signal is considered asynchronous to CLKOUT.
Figure 6-2 is the control timing diagram.
MOTOROLA MPC850 (Rev . A/B/C) Har dware Specifications 19
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Layout Practices
CLKOUT
Outputs
Outputs
Inputs
Inputs
2.0 V
B
2.0 V
0.8 V
0.8 V
A
B
2.0 V
0.8 V
2.0 V
0.8 V
C
2.0 V
0.8 V
0.8 V
A
D
2.0 V
0.8 V
2.0 V
2.0 V
0.8 V
2.0 V
0.8 V
D
C
2.0 V
0.8 V
A Maximum output delay specification
B Minimum output hold time
C Minimum input setup time specification
D Minimum input hold time specification
Figure 6-2. Control Timing
20 MPC850 (Rev . A/B/C) Har dware Specifications MOT OROLA
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Figure 6-3 provides the timing for the external clock.
CLKOUT
Layout Practices
B1
B1
B4
B3
Figure 6-3. External Clock Timing
Figure 6-4 provides the timing for the synchronous output signals.
CLKOUT
B8
B7 B9
Output
Signals
B8a
B9B7a
Output
Signals
B8b
B7b
B2
B5
Output
Signals
Figure 6-4. Synchronous Output Signals Timing
MOTOROLA MPC850 (Rev . A/B/C) Har dware Specifications 21
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Layout Practices
Figure 6-5 provides the timing for the synchronous active pull-up and open-drain output
signals.
CLKOUT
B13
B12B11
TS
, BB
B13a
B11a
TA, BI
B14
TEA
B12a
B15
Figure 6-5. Synchronous Active Pullup and Open-Drain Outputs Signals Timing
Figure 6-6 provides the timing for the synchronous input signals.
CLKOUT
B16
B17
T
A, BI
B16a
B17a
TEA, KR,
RETR
Y
B16b
B17
BB, BG, BR
Figure 6-6. Synchronous Input Signals Timing
22 MPC850 (Rev . A/B/C) Har dware Specifications MOT OROLA
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Layout Practices
Figure 6-7 provides normal case timing for input data.
CLKOUT
B16
B17
T
A
B18
B19
D[0:31],
DP[0:3]
Figure 6-7. Input Data Timing in Normal Case
Figure 6-8 provides the timing for the input data controlled by the UPM in the memory
controller.
CLKOUT
T
A
B20
B21
D[0:31],
DP[0:3]
Figure 6-8. Input Data Timing when Controlled by UPM in the Memory Controller
MOTOROLA MPC850 (Rev . A/B/C) Har dware Specifications 23
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Layout Practices
Figure 6-9 through Figure 6-12 provide the timing for the external bus read controlled by
various GPCM factors.
CLKOUT
B11 B12
TS
B8
A[6:31]
B22
CSx
B25
OE
B28
WE[0:3]
B18
D[0:31],
DP[0:3]
B23
B26
B19
Figure 6-9. External Bus Read Timing (GPCM Controlled—ACS = 00)
24 MPC850 (Rev . A/B/C) Har dware Specifications MOT OROLA
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CLKOUT
TS
A[6:31]
Layout Practices
B11 B12
B8
B22a
CSx
B25B24
OE
D[0:31],
DP[0:3]
B23
B26
B19B18
Figure 6-10. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10)
CLKOUT
B11 B12
TS
B8
A[6:31]
B22b
B23
B19B18
CSx
OE
D[0:31],
DP[0:3]
B22c
B24a
B25 B26
Figure 6-11. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11)
MOTOROLA MPC850 (Rev . A/B/C) Har dware Specifications 25
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Layout Practices
CLKOUT
TS
A[6:31]
B11 B12
B8
B23
B26
B19B18
CSx
OE
D[0:31],
DP[0:3]
B22a
B27
B27a
B22bB22c
Figure 6-12. External Bus Read Timing (GPCM Controlled—TRLX = 1, ACS = 10,
ACS = 11)
26 MPC850 (Rev . A/B/C) Har dware Specifications MOT OROLA
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Layout Practices
Figure 6-13 through Figure 6-15 provide the timing for the external bus write controlled by
various GPCM factors.
CLKOUT
TS
A[6:31]
CSx
WE[0:3]
OE
D[0:31],
DP[0:3]
B11
B8
B22 B23
B26
B12
B8 B9
B30
B28B25
B29
B29a
Figure 6-13. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 0)
MOTOROLA MPC850 (Rev . A/B/C) Har dware Specifications 27
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Layout Practices
CLKOUT
TS
A[6:31]
CSx
WE[0:3]
OE
D[0:31],
DP[0:3]
B11
B8
B22
B26
B8
B12
B28b
B25
B28a
B28d
B28c
B9
B30a
B23
B29c
B29aB29f
B30c
B29g
Figure 6-14. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1)
28 MPC850 (Rev . A/B/C) Har dware Specifications MOT OROLA
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CLKOUT
TS
Layout Practices
B12B11
B8
A[6:31]
B28b
CSx
B25
WE[0:3]
B26
OE
B28a
D[0:31],
DP[0:3]
B28d
B29eB29i
B29d
B28c
B30dB30b
B23B22
B29
B9B8
Figure 6-15. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1)
Figure 6-16 provides the timing for the external bus controlled by the UPM.
MOTOROLA MPC850 (Rev . A/B/C) Har dware Specifications 29
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Layout Practices
CLKOUT
A[6:31]
CSx
BS_A
[0:3],
BS_B
[0:3]
B8
B34
B34b
B31
B34a
B32
B31a
B31d
B32aB32d
B31c
B31b
B32c
B32b
B36
B35
GPL_A[0—5],
GPL_B
[0—5]
B35a
B35b
B33
B33a
Figure 6-16. External Bus Timing (UPM Controlled Signals)
Figure 6-17 provides the timing for the asynchronous asserted UPWAIT signal controlled
by the UPM.
30 MPC850 (Rev . A/B/C) Har dware Specifications MOT OROLA
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Layout Practices
CLKOUT
B37
UPWAIT
B38
CSx
BS_A[0:3],
BS_B
[0:3]
[0—5],
GPL_A
GPL_B
[0—5]
Figure 6-17. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles
Timing
Figure 6-18 provides the timing for the asynchronous negated UPWAIT signal controlled
by the UPM.
CLKOUT
B37
UPWAIT
B38
CSx
BS_A[0:3],
BS_B
[0:3]
GPL_A
[0—5],
GPL_B
[0—5]
Figure 6-18. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles
Timing
Figure 6-19 provides the timing for the synchronous external master access controlled by
the GPCM.
MOTOROLA MPC850 (Rev . A/B/C) Har dware Specifications 31
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Layout Practices
CLKOUT
B41 B42
TS
B40
A[6:31],
TSIZ[0:1],
R/W
, BURST
B22
CSx
Figure 6-19. Synchronous External Master Access Timing (GPCM Handled ACS =
00)
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Layout Practices
Figure 6-20 provides the timing for the asynchronous external master memory access
controlled by the GPCM.
CLKOUT
B39
AS
B40
A[6:31],
TSIZ[0:1],
R/W
B22
CSx
Figure 6-20. Asynchronous External Master Memory Access Timing (GPCM
Controlled—ACS = 00)
Figure 6-21 provides the timing for the asynchronous external master control signals
negation.
AS
B43
CSx, WE[0:3],
OE
, GPLx,
BS
[0:3]
Figure 6-21. Asynchronous External Master—Control Signals Negation Timing
Table 6-7 provides interrupt timing for the MPC850.
Table 6-7. Interrupt Timing
Num Characteristic
I39 IRQx
I40 IRQx hold time after CLKOUT. 2.00 — 2.00 — 2.00 — ns
I41 IRQx
I42 IRQx
I43 IRQx edge-to-edge time 80.00 — 121.0 — 100.0 — ns
valid to CLKOUT rising edge (set up time) 6.00 — 6.00 — 6.00 — ns
pulse width low 3.00 — 3.00 — 3.00 — ns
pulse width high 3.00 — 3.00 — 3.00 — ns
1
50 MHz 66MHz 80 MHz
Unit
Min Max Min Max Min Max
MOTOROLA MPC850 (Rev . A/B/C) Har dware Specifications 33
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Layout Practices
1
The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as
level sensitive. The IRQ
to the CLKOUT.
The timings I41, I42, and I43 are specified to allow the correct function of the IRQ
direct relation with the total system interrupt latency that the MPC850 is able to support
lines are synchronized internally and do not have to be asserted or negated with reference
lines detection circuitry, and has no
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Layout Practices
Figure 6-22 provides the interrupt detection timing for the external level-sensitive lines.
CLKOUT
I39
I40
IRQx
Figure 6-22. Interrupt Detection Timing for External Level Sensitive Lines
Figure 6-23 provides the interrupt detection timing for the external edge-sensitive lines.
CLKOUT
I39
I41 I42
IRQx
I43
I43
Figure 6-23. Interrupt Detection Timing for External Edge Sensitive Lines
Table 6-8 shows the PCMCIA timing for the MPC850.
Table 6-8. PCMCIA Timing
50MHz 66MHz 80 MHz
Num Characteristic
Min Max Min Max Min Max
P44
P45 A[6–31], REG
P46 CLKOUT to REG
P47 CLKOUT to REG
P48 CLKOUT to CE1, CE2 asserted. 5.00 13.00 8.00 16.00 6.00 14.00 0.250
P49 CLKOUT to CE1
P50
A[6–31], REG
asserted.
CLKOUT to PCOE
assert time.
valid to PCMCIA strobe
1
valid to ALE negation.
valid 5.00 13.00 8.00 16.00 6.00 14.00 0.250 ns
Invalid. 6.00 — 9.00 — 7.00 — 0.250 ns
, CE2 negated. 5.00 13.00 8.00 16.00 6.00 14.00 0.250 ns
, IORD, PCWE, IO WR
13.00 — 21.00 — 17.00 — 0.750 ns
1
18.00 — 28.00 — 23.00 — 1.000 ns
— 11.00 — 11.00 — 11.00 — ns
FFACTOR Unit
P51
P52 CLKOUT to ALE assert time 5.00 13.00 8.00 16.00 6.00 14.00 0.250 ns
CLKOUT to PCOE
negate time.
, IORD, PCWE, IO WR
2.00 11.00 2.00 11.00 2.00 11.00 — ns
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Layout Practices
Table 6-8. PCMCIA Timing (continued)
50MHz 66MHz 80 MHz
Num Characteristic
Min Max Min Max Min Max
P53 CLKOUT to ALE negate time — 13.00 — 16.00 — 14.00 0.250 ns
P54
, IOWR negated to D[0–31]
PCWE
1
invalid.
3.00 — 6.00 — 4.00 — 0.250 ns
FFACTOR Unit
P55 W
P56 CLKOUT rising edge to W
1
PSST = 1. Otherwise add PSST times cycle time.
PSHT = 0. Otherwise add PSHT times cycle time.
These synchronous timings define when the W
current cycle. The W
See PCMCIA Interface in the MPC850 PowerQUICC User’s Manual.
AIT_B valid to CLKOUT rising edge.18.00 — 8.00 — 8.00 — — ns
AIT_B invalid.12.00 — 2.00 — 2.00 — — ns
AIT_B signal is detected in order to freeze (or relieve) the PCMCIA
AIT_B assertion will be effective only if it is detected 2 cycles before the PSL timer expiration.
Figure 6-24 provides the PCMCIA access cycle timing for the external bus read.
CLKOUT
TS
P44
A[6:31]
P46 P45
P47
REG
P48 P49
CE1/CE2
P51P50
PCOE, IORD
P53P52 P52
ALE
B19B18
D[0:31]
Figure 6-24. PCMCIA Access Cycles Timing External Bus Read
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Layout Practices
Figure 6-25 provides the PCMCIA access cycle timing for the external bus write.
CLKOUT
TS
P44
A[6:31]
P46 P45
REG
P48 P49
CE1/CE2
PCWE, IOWR
P53P52 P52
ALE
D[0:31]
Figure 6-25. PCMCIA Access Cycles Timing External Bus Write
Figure 6-26 provides the PCMCIA WAIT signals detection timing.
P47
P51P50
P54
B9B8
CLKOUT
P55
P56
W
AIT_B
Figure 6-26. PCMCIA WAIT Signal Detection Timing
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Layout Practices
Table 6-9 shows the PCMCIA port timing for the MPC850.
Table 6-9. PCMCIA Port Timing
50 MHz 66 MHz 80 MHz
Num Characteristic
Min Max Min Max Min Max
P57 CLKOUT to OPx valid — 19.00 — 19.00 — 19.00 ns
P58 HRESET
P59 IP_Xx valid to CLKOUT rising edge 5.00 — 5.00 — 5.00 — ns
P60 CLKOUT rising edge to IP_Xx invalid 1.00 — 1.00 — 1.00 — ns
1
OP2 and OP3 only.
negated to OPx drive
1
18.00 — 26.00 — 22.00 — ns
Figure 6-27 provides the PCMCIA output port timing for the MPC850.
CLKOUT
P57
Unit
Output
Signals
HRESET
P58
OP2, OP3
Figure 6-27. PCMCIA Output Por t Timing
Figure 6-28 provides the PCMCIA output port timing for the MPC850.
CLKOUT
P59
P60
Input
Signals
Figure 6-28. PCMCIA Input Por t Timing
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Layout Practices
Table 6-10 shows the debug port timing for the MPC850.
Table 6-10. Debug Port Timing
50 MHz 66 MHz 80 MHz
Num Characteristic
Min Max Min Max Min Max
D61 DSCK cycle time 60.00 — 91.00 — 75.00 — ns
D62 DSCK clock pulse width 25.00 — 38.00 — 31.00 — ns
D63 DSCK rise and fall times 0.00 3.00 0.00 3.00 0.00 3.00 ns
D64 DSDI input data setup time 8.00 — 8.00 — 8.00 — ns
D65 DSDI data hold time 5.00 — 5.00 — 5.00 — ns
D66 DSCK low to DSDO data valid 0.00 15.00 0.00 15.00 0.00 15.00 ns
D67 DSCK low to DSDO invalid 0.00 2.00 0.00 2.00 0.00 2.00 ns
Figure 6-29 provides the input timing for the debug port clock.
DSCK
Unit
D61
D63
D62
Figure 6-29. Debug Port Clock Input Timing
Figure 6-30 provides the timing for the debug port.
DSCK
D64
DSDI
D66
D67
DSDO
Figure 6-30. Debug Port Timings
D62
D63
D65
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Layout Practices
Table 6-11 shows the reset timing for the MPC850.
Table 6-11. Reset Timing
50 MHz 66MHz 80 MHz
Num Characteristic
Min Max Min Max Min Max
FFACTOR Unit
R69 CLKOUT to HRESET
R70 CLKOUT to SRESET
R71 RSTCONF
R72 —————— —
Configuration data to HRESET
R73
edge set up time
Configuration data to RSTCONF
R74
edge set up time
Configuration data hold time after
R75
RSTCONF
Configuration data hold time after
R76
HRESET
HRESET
R77
data out drive
RSTCONF
R78
impedance.
CLKOUT of last rising edge before chip
R79
tristates HRESET
impedance.
R80 DSDI, DSCK set up 60.00 — 90.00 — 75.00 — 3.000 ns
pulse width 340.00 — 515.00 — 425.00 — 17.000 ns
negation
negation
and RSTCONF asserted to
negated to data out high
high impedance — 20.00 — 20.00 — 20.00 — ns
high impedance — 20.00 — 20.00 — 20.00 — ns
rising
rising
to data out high
350.00 — 505.00 — 425.00 — 15.000 ns
350.00 — 350.00 — 350.00 — — ns
0.00 — 0.00 — 0.00 — — ns
0.00 — 0.00 — 0.00 — — ns
— 25.00 — 25.00 — 25.00 — ns
— 25.00 — 25.00 — 25.00 — ns
— 25.00 — 25.00 — 25.00 — ns
R81 DSDI, DSCK hold time 0.00 — 0.00 — 0.00 — — ns
SRESET
R82
edge for DSDI and DSCK sample
negated to CLKOUT rising
160.00 — 242.00 — 200.00 — 8.000 ns
Figure 6-31 shows the reset timing for the data bus configuration.
HRESET
R71
R76
RSTCONF
R73
R74
D[0:31] (IN)
Figure 6-31. Reset Timing—Configuration from Data Bus
R75
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Layout Practices
Figure 6-32 provides the reset timing for the data bus weak drive during configuration.
CLKOUT
R69
HRESET
R79
RSTCONF
R77 R78
D[0:31] (OUT)
(Weak)
Figure 6-32. Reset Timing—Data Bus Weak Drive during Configuration
Figure 6-33 provides the reset timing for the debug port configuration.
CLKOUT
SRESET
DSCK, DSDI
R70
R82
R80R80
R81
R81
Figure 6-33. Reset Timing—Debug Port Configuration
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Layout Practices
Part VII IEEE 1149.1 Electrical
Specifications
Table 7-12 provides the JTAG timings for the MPC850 as shown in Figure 7-34 to
Figure 7-37.
Table 7-12. JTAG Timing
50 MHz 66MHz 80 MHz
Num Characteristic
Min Max Min Max Min Max
J82 TCK cycle time 100.00 — 100.00 — 100.00 — ns
J83 TCK clock pulse width measured at 1.5 V 40.00 — 40.00 — 40.00 — ns
J84 TCK rise and fall times 0.00 10.00 0.00 10.00 0.00 10.00 ns
J85 TMS, TDI data setup time 5.00 — 5.00 — 5.00 — ns
J86 TMS, TDI data hold time 25.00 — 25.00 — 25.00 — ns
J87 TCK low to TDO data valid — 27.00 — 27.00 — 27.00 ns
Unit
J88 TCK low to TDO data invalid 0.00 — 0.00 — 0.00 — ns
J89 TCK low to TDO high impedance — 20.00 — 20.00 — 20.00 ns
J90 TRST
J91 TRST
J92 TCK falling edge to output valid — 50.00 — 50.00 — 50.00 ns
J93
J94 TCK falling edge to output high impedance — 50.00 — 50.00 — 50.00 ns
J95 Boundary scan input valid to TCK rising edge 50.00 — 50.00 — 50.00 — ns
J96 TCK rising edge to boundary scan input invalid 50.00 — 50.00 — 50.00 — ns
assert time 100.00 — 100.00 — 100.00 — ns
setup time to TCK low 40.00 — 40.00 — 40.00 — ns
TCK falling edge to output valid out of high
impedance
TCK
J82 J83
J82 J83
J84
— 50.00 — 50.00 — 50.00 ns
J84
Figure 7-34. JTAG Test Clock Input Timing
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TCK
TMS, TDI
TDO
TCK
Layout Practices
J85
J86
J87
J88 J89
Figure 7-35. JTAG Test Access Port Timing Diagram
J91
J90
TRST
TCK
Output
Signals
Output
Signals
Input
Signals
Figure 7-36. JTAG TRST Timing Diagram
J92 J94
J93
J95 J96
Figure 7-37. Boundary Scan (JTAG) Timing Diagram
Part VIII CPM Electrical Characteristics
This section provides the AC and DC electrical specifications for the communications
processor module (CPM) of the MPC850.
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PIO AC Electrical Specifications
8.1 PIO AC Electrical Specifications
Table 8-13 provides the parallel I/O timings for the MPC850 as shown in Figure 8-38.
Table 8-13. Parallel I/O Timing
All Frequencies
Num Characteristic
Min Max
29 Data-in setup time to clock high 15 — ns
30 Data-in hold time from clock high 7.5 — ns
31 Clock low to data-out valid (CPU writes data, control, or direction) — 25 ns
CLKOUT
29
30
DATA-IN
Unit
31
DATA-OUT
Figure 8-38. Parallel I/O Data-In/Data-Out Timing Diagram
8.2 IDMA Controller AC Electrical Specifications
Table 8-14 provides the IDMA controller timings as shown in Figure 8-39 to Figure 8-42.
Table 8-14. IDMA Controller Timing
All Frequencies
Num Characteristic
Min Max
40 DREQ
41 DREQ hold time from clock high 3.00 — ns
42 SD
43 SD
44 SDACK negation delay from TA low — 20.00 ns
45 SD
46 T
setup time to clock high 7.00 — ns
ACK assertion delay from clock high — 12.00 ns
ACK negation delay from clock low — 12.00 ns
ACK negation delay from clock high — 15.00 ns
A assertion to falling edge of the clock setup time (applies to external TA) 7.00 — ns
Unit
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CLKOUT
(Output)
DREQ
(Input)
CLKOUT
(Output)
TS
(Output)
R/W
(Output)
IDMA Controller AC Electrical Specifications
41
40
Figure 8-39. IDMA External Requests Timing Diagram
DATA
T
(Output)
SDACK
42
A
43
46
Figure 8-40. SDACK Timing Diagram—Peripheral Write, TA Sampled Low at the
Falling Edge
of the Clock
MOTOROLA MPC850 (Rev . A/B/C) Har dware Specifications 45
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IDMA Controller AC Electrical Specifications
CLKOUT
(Output)
TS
(Output)
R/W
(Output)
42 44
DATA
A
T
(Output)
SDACK
Figure 8-41. SDACK Timing Diagram—Peripheral Write, TA Sampled High at the
Falling Edge
of the Clock
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CLKOUT
(Output)
TS
(Output)
R/W
(Output)
DATA
A
T
(Output)
Baud Rate Generator AC Electrical Specifications
42 45
SDACK
Figure 8-42. SDACK Timing Diagram—Peripheral Read
8.3 Baud Rate Generator A C Electrical Specifications
Table 8-15 provides the baud rate generator timings as shown in Figure 8-43.
Table 8-15. Baud Rate Generator Timing
All Frequencies
BRGOn
Num Characteristic
Min Max
50 BRGO rise and fall time — 10.00 ns
51 BRGO duty cycle 40.00 60.00 %
52 BRGO cycle 40.00 — ns
50
50
Unit
51
52
51
Figure 8-43. Baud Rate Generator Timing Diagram
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Timer AC Electrical Specifications
8.4 Timer AC Electrical Specifications
Table 8-16 provides the baud rate generator timings as shown in Figure 8-44.
Num Characteristic
T able 8-16. Timer Timing
All Frequencies
Unit
Min Max
CLKOUT
TIN/TGA
(Input)
TOUT
(Output)
61 TIN/TGA
62 TIN/TGA
63 TIN/TGA
64 TIN/TGA
65 CLKO high to T
TE
TE rise and fall time 10.00 — ns
TE low time 1.00 — clk
TE high time 2.00 — clk
TE cycle time 3.00 — clk
OUT valid 3.00 25.00 ns
61
65
64
Figure 8-44. CPM General-Purpose Timers Timing Diagram
626361
8.5 Serial Interface AC Electrical Specifications
Table 8-17 provides the serial interface timings as shown in Figure 8-45 to Figure 8-49.
Table 8-17. SI Timing
All Frequencies
Num Characteristic
Min Max
1, 2
70 L1RCLK, L1TCLK frequency (DSC = 0)
71 L1RCLK, L1TCLK width low (DSC = 0)
71a L1RCLK, L1TCLK width high (DSC = 0)
72 L1TXD, L1STn, L1RQ
73 L1RSYNC, L1TSYNC valid to L1xCLK edge Edge
(SYNC setup time)
, L1xCLKO rise/fall time — 15.00 ns
— SYNCCLK/2.5MHz
2
3
P + 10 — ns
P + 10 — ns
20.00 — ns
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Table 8-17. SI Timing (continued)
Num Characteristic
Serial Interface AC Electrical Specifications
All Frequencies
Unit
Min Max
74 L1xCLK edge to L1RSYNC, L1TSYNC, invalid
35.00 — ns
(SYNC hold time)
75 L1RSYNC, L1TSYNC rise/fall time — 15.00 ns
76 L1RXD valid to L1xCLK edge (L1RXD setup time) 17.00 — ns
77 L1xCLK edge to L1RXD invalid (L1RXD hold time) 13.00 — ns
78 L1xCLK edge to L1STn valid
4
10.00 45.00 ns
78A L1SYNC valid to L1STn valid 10.00 45.00 ns
79 L1xCLK edge to L1STn invalid 10.00 45.00 ns
80 L1xCLK edge to L1TXD valid 10.00 55.00 ns
80A L1TSYNC valid to L1TXD valid
4
10.00 55.00 ns
81 L1xCLK edge to L1TXD high impedance 0.00 42.00 ns
82 L1RCLK, L1TCLK frequency (DSC =1) — 16.00 or
MHz
SYNCCLK/2
83 L1RCLK, L1TCLK width low (DSC =1) P + 10 — ns
83A L1RCLK, L1TCLK width high (DSC = 1)
3
P + 10 — ns
84 L1CLK edge to L1CLKO valid (DSC = 1) — 30.00 ns
85 L1RQ
valid before falling edge of L1TSYNC
86 L1GR setup time
2
4
1.00 — L1TCLK
42.00 — ns
87 L1GR hold time 42.00 — ns
88 L1xCLK edge to L1SYNC valid (FSD = 00) CNT =
— 0.00 ns
0000, BYT = 0, DSC = 0)
1
The ratio SyncCLK/L1RCLK must be greater than 2.5/1.
2
These specs are valid for IDL mode only.
3
Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns.
4
These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC,
whichever is later.
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Serial Interface AC Electrical Specifications
L1RCLK
(FE=0, CE=0)
(Input)
71 70
72
L1RCLK
(FE=1, CE=1)
(Input)
RFSD=1
75
L1RSYNC
(Input)
73
71a
7774
L1RxD
(Input)
76
L1STn
(Output)
BIT0
78
79
Figure 8-45. SI Receive Timing Diagram with Normal Clocking (DSC = 0)
50 MPC850 (Rev . A/B/C) Har dware Specifications MOT OROLA
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L1RCLK
(FE=1, CE=1)
(Input)
L1RCLK
(FE=0, CE=0)
(Input)
L1RSYNC
(Input)
82
72
RFSD=1
75
73
74 77
Serial Interface AC Electrical Specifications
83a
L1RXD
(Input)
76
L1ST(4-1)
(Output)
L1CLKO
(Output)
BIT0
84
78
79
Figure 8-46. SI Receive Timing with Double-Speed Clocking (DSC = 1)
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Serial Interface AC Electrical Specifications
L1TCLK
(FE=0, CE=0)
(Input)
71
L1TCLK
(FE=1, CE=1)
(Input)
73
L1TSYNC
(Input)
70
72
TFSD=0
75
74
8180a
L1TxD
(Output)
L1STn
(Output)
80
78
BIT0
79
Figure 8-47. SI T ransmit Timing Diagram
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L1RCLK
(FE=0, CE=0)
(Input)
L1RCLK
(FE=1, CE=1)
(Input)
L1RSYNC
(Input)
73
75
74
72
82
TFSD=0
Serial Interface AC Electrical Specifications
83a
81
L1TXD
(Output)
L1ST(4-1)
(Output)
L1CLKO
(Output)
BIT0
80
84
78a
78
79
Figure 8-48. SI Transmit Timing with Double Speed Clocking (DSC = 1)
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Serial Interface AC Electrical Specifications
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12345678910 11 12 13 14 15 16 17 18 19 20
(Input)
L1RCLK
73
71
L1RSYNC
71
80
(Input)
72
B17 B16 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 MB15
(Input)
L1RXD
76
74
B17 B16 B15 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 M
L1TXD
(Output)
77
Figure 8-49. IDL Timing
78
(Output)
L1ST(4-1)
85
L1RQ
(Output)
86
87
L1GR
(Input)
54 MPC850 (Rev . A/B/C) Har dware Specifications MOT OROLA
SCC in NMSI Mode Electrical Specifications
8.6 SCC in NMSI Mode Electrical Specifications
Table 8-18 provides the NMSI external clock timing.
Num Characteristic
100 RCLKx and TCLKx frequency
table)
101 RCLKx and TCLKx width low 1/SYNCCLK +5 — ns
102 RCLKx and TCLKx rise/fall time — 15.00 ns
103 TXDx active delay (from TCLKx falling edge) 0.00 50.00 ns
104 RTSx active/inactive delay (from TCLKx falling edge) 0.00 50.00 ns
105 CTSx
setup time to TCLKx rising edge 5.00 — ns
106 RXDx setup time to RCLKx rising edge 5.00 — ns
107 RXDx hold time from RCLKx rising edge
108 CDx
1
The ratios SyncCLK/RCLKx and SyncCLK/TCLKx must be greater than or equal to 2.25/1.
2
Also applies to CD and CTS hold time when they are used as an external sync signal.
setup time to RCLKx rising edge 5.00 — ns
Table 8-18. NMSI External Clock Timing
All Frequencies
Min Max
1
(x = 2, 3 for all specs in this
2
1/SYNCCLK — ns
5.00 — ns
Unit
Table 8-19 provides the NMSI internal clock timing.
Num Characteristic
100 RCLKx and TCLKx frequency
102 RCLKx and TCLKx rise/fall time — — ns
103 TXDx active delay (from TCLKx falling edge) 0.00 30.00 ns
104 RTSx active/inactive delay (from TCLKx falling edge) 0.00 30.00 ns
105 CTSx
setup time to TCLKx rising edge 40.00 — ns
106 RXDx setup time to RCLKx rising edge 40.00 — ns
107 RXDx hold time from RCLKx rising edge
108 CDx
1
The ratios SyncCLK/RCLKx and SyncCLK/TCLK1x must be greater or equal to 3/1.
2
Also applies to CD and CTS hold time when they are used as an external sync signals.
setup time to RCLKx rising edge 40.00 — ns
Table 8-19. NMSI Internal Clock Timing
All Frequencies
Min Max
1
(x = 2, 3 for all specs in this table)
2
0.00 SYNCCLK/3 MHz
0.00 — ns
Unit
MOTOROLA MPC850 (Rev . A/B/C) Har dware Specifications 55
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SCC in NMSI Mode Electrical Specifications
Figure 8-50 through Figure 8-52 show the NMSI timings.
RCLKx
RXDx
(Input)
CDx
(Input)
CDx
(SYNC Input)
TCLKx
102
106
102 101
100
107
Figure 8-50. SCC NMSI Receive Timing Diagram
102
102 101
100
108
107
TXDx
(Output)
RTSx
(Output)
CTSx
(Input)
CTSx
(SYNC Input)
103
105
104
Figure 8-51. SCC NMSI Transmit Timing Diagram
104
107
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TCLKx
Ethernet Electrical Specifications
102
TXDx
(Output)
RTSx
(Output)
CTSx
(Echo Input)
102 101
103
104
105
100
104107
Figure 8-52. HDLC Bus Timing Diagram
8.7 Ethernet Electrical Specifications
Table 8-20 provides the Ethernet timings as shown in Figure 8-53 to Figure 8-55.
Table 8-20. Ethernet Timing
All Frequencies
Num Characteristic
Min Max
120 CLSN width high 40.00 — ns
121 RCLKx rise/fall time (x = 2, 3 for all specs in this table) — 15.00 ns
122 RCLKx width low 40.00 — ns
123 RCLKx clock period
124 RXDx setup time 20.00 — ns
125 RXDx hold time 5.00 — ns
126 RENA active delay (from RCLKx rising edge of the last data bit) 10.00 — ns
127 RENA width low 100.00 — ns
128 TCLKx rise/fall time — 15.00 ns
129 TCLKx width low 40.00 — ns
130 TCLKx clock period
131 TXDx active delay (from TCLKx rising edge) 10.00 50.00 ns
132 TXDx inactive delay (from TCLKx rising edge) 10.00 50.00 ns
1
1
80.00 120.00 ns
99.00 101.00 ns
Unit
MOTOROLA MPC850 (Rev . A/B/C) Har dware Specifications 57
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Ethernet Electrical Specifications
Table 8-20. Ethernet Timing (continued)
Num Characteristic
133 TENA active delay (from TCLKx rising edge) 10.00 50.00 ns
134 TENA inactive delay (from TCLKx rising edge) 10.00 50.00 ns
138 CLKOUT low to SD
139 CLKOUT low to SD
1
The ratios SyncCLK/RCLKx and SyncCLK/TCLKx must be greater or equal to 2/1.
2
SDACK is asserted whenever the SDMA writes the incoming frame destination address into memory.
CLSN(CTSx)
(Input)
ACK asserted
ACK negated
Figure 8-53. Ethernet Collision Timing Diagram
All Frequencies
Unit
Min Max
2
2
120
— 20.00 ns
— 20.00 ns
RCLKx
RXDx
(Input)
RENA(CDx)
(Input)
121
121
124 123
125
122
126
Last Bit
Figure 8-54. Ethernet Receive Timing Diagram
127
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TCLKx
SMC Transparent AC Electrical Specifications
TxDx
(Output)
TENA(RTSx)
(Input)
RENA(CDx)
(Input)
(NOTE 2)
128
131 130
133 134
NOTES:
Transmit clock invert (TCI) bit in GSMR is set.
1.
If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the
2.
CSL bit is set in the buffer descriptor at the end of the frame transmission.
128
129
132
Figure 8-55. Ethernet T ransmit Timing Diagram
8.8 SMC Transparent AC Electrical Specifications
Figure 8-21 provides the SMC transparent timings as shown in Figure 8-56.
Table 8-21. Serial Management Controller Timing
All Frequencies
Num Characteristic
Min Max
150 SMCLKx clock period
151 SMCLKx width low 50.00 — ns
151a SMCLKx width high 50.00 — ns
152 SMCLKx rise/fall time — 15.00 ns
153 SMTXDx active delay (from SMCLKx falling edge) 10.00 50.00 ns
154 SMRXDx/SMSYNx
155 SMRXDx/SMSYNx
1
The ratio SyncCLK/SMCLKx must be greater or equal to 2/1.
1
setup time 20.00 — ns
hold time 5.00 — ns
100.00 — ns
Unit
MOTOROLA MPC850 (Rev . A/B/C) Har dware Specifications 59
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SPI Master AC Electrical Specifications
SMCLKx
152
SMTXDx
(Output)
SMSYNx
SMRXDx
(Input)
NOTE:
This delay is equal to an integer number of character-length clocks.1.
152 151
NOTE
154 153
155
154
155
151a
150
Figure 8-56. SMC T ransparent Timing Diagram
8.9 SPI Master AC Electrical Specifications
Table 8-22 provides the SPI master timings as shown in Figure 8-57 and Figure 8-58.
Table 8-22. SPI Master Timing
All Frequencies
Num Characteristic
Min Max
160 MASTER cycle time 4 1024 t
161 MASTER clock (SCK) high or low time 2 512 t
162 MASTER data setup time (inputs) 50.00 — ns
163 Master data hold time (inputs) 0.00 — ns
164 Master data valid (after SCK edge) — 20.00 ns
165 Master data hold time (outputs) 0.00 — ns
166 Rise time output — 15.00 ns
167 Fall time output — 15.00 ns
Unit
cyc
cyc
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SPICLK
(CI=0)
(Output)
SPICLK
(CI=1)
(Output)
163
161 160
162
166
SPI Master AC Electrical Specifications
166167161
167
SPIMISO
(Input)
SPIMOSI
(Output)
SPICLK
(CI=0)
(Output)
SPICLK
(CI=1)
(Output)
SPIMISO
(Input)
msb Data lsb msb
165 164
167 166
msb lsb msb
Data
Figure 8-57. SPI Master (CP = 0) Timing Diagram
166167161
161 160
162
163
166
msb Data lsb msb
167
165 164
167 166
SPIMOSI
(Output)
msb lsb msb
Data
Figure 8-58. SPI Master (CP = 1) Timing Diagram
MOTOROLA MPC850 (Rev . A/B/C) Har dware Specifications 61
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SPI Slave AC Electrical Specifications
8.10 SPI Slave AC Electrical Specifications
Table 8-23 provides the SPI slave timings as shown in Figure 8-59 and Figure 8-60.
Table 8-23. SPI Slave Timing
All Frequencies
Num Characteristic
Min Max
Unit
170 Slave cycle time 2 — t
171 Slave enable lead time 15.00 — ns
172 Slave enable lag time 15.00 — ns
173 Slave clock (SPICLK) high or low time 1 — t
174 Slave sequential transfer delay (does not require deselect) 1 — t
175 Slave data setup time (inputs) 20.00 — ns
176 Slave data hold time (inputs) 20.00 — ns
177 Slave access time — 50.00 ns
178 Slave SPI MISO disable time — 50.00 ns
179 Slave data valid (after SPICLK edge) — 50.00 ns
180 Slave data hold time (outputs) 0.00 — ns
181 Rise time (input) — 15.00 ns
182 Fall time (input) — 15.00 ns
cyc
cyc
cyc
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SPISEL
(Input)
SPICLK
(CI=0)
(Input)
SPICLK
(CI=1)
(Input)
181182173
173 170
177 182
181
180
SPI Slave AC Electrical Specifications
171172
174
178
SPIMISO
(Output)
SPIMOSI
(Input)
Datamsb lsb msbUndef
175 179
176 182
msb lsb msb
Data
181
Figure 8-59. SPI Slave (CP = 0) Timing Diagram
MOTOROLA MPC850 (Rev . A/B/C) Har dware Specifications 63
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I2C AC Electrical Specifications
SPISEL
(Input)
171 170
SPICLK
(CI=0)
(Input)
173
173
SPICLK
(CI=1)
(Input)
177 182
180
172
174
181182
181
178
SPIMISO
(Output)
175 179
SPIMOSI
(Input)
msb
176 182
msb lsb
Data
181
Data
lsbUndef
Figure 8-60. SPI Slave (CP = 1) Timing Diagram
8.11 I2C AC Electrical Specifications
Table 8-24 provides the I2C (SCL < 100 KHz) timings.
Table 8-24. I2C Timing (SCL < 100 KHZ)
Num Characteristic
200 SCL clock frequency (slave) 0.00 100.00 KHz
200 SCL clock frequency (master)
202 Bus free time between transmissions 4.70 — µs
1
msb
msb
All Frequencies
Unit
Min Max
1.50 100.00 KHz
203 Low period of SCL 4.70 — µs
204 High period of SCL 4.00 — µs
205 Start condition setup time 4.70 — µs
206 Start condition hold time 4.00 — µs
207 Data hold time 0.00 — µs
64 MPC850 (Rev . A/B/C) Har dware Specifications MOT OROLA
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I2C AC Electrical Specifications
Table 8-24. I2C Timing (SCL < 100 KHZ) (CONTINUED)
All Frequencies
Num Characteristic
Min Max
208 Data setup time 250.00 — ns
209 SDL/SCL rise time — 1.00 µs
210 SDL/SCL fall time — 300.00 ns
211 Stop condition setup time 4.70 — µs
1
SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) * pre_scaler * 2).
The ratio SyncClk/(BRGCLK/pre_scaler) must be greater or equal to 4/1.
Unit
Table 8-25 provides the I2C (SCL > 100 KHz) timings.
Table 8-25. I2C Timing (SCL > 100 KHZ)
All Frequencies
Num Characteristic Expression
Min Max
200 SCL clock frequency (slave) fSCL 0 BRGCLK/48 Hz
200 SCL clock frequency (master)
202 Bus free time between transmissions 1/(2.2 * fSCL) — s
1
fSCL BRGCLK/16512 BRGCLK/48 Hz
Unit
203 Low period of SCL 1/(2.2 * fSCL) — s
204 High period of SCL 1/(2.2 * fSCL) — s
205 Start condition setup time 1/(2.2 * fSCL) — s
206 Start condition hold time 1/(2.2 * fSCL) — s
207 Data hold time 0 — s
208 Data setup time 1/(40 * fSCL) — s
209 SDL/SCL rise time — 1/(10 * fSCL) s
210 SDL/SCL fall time — 1/(33 * fSCL) s
211 Stop condition setup time 1/2(2.2 * fSCL) — s
1
SCL frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) * pre_scaler * 2).
The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1.
MOTOROLA MPC850 (Rev . A/B/C) Har dware Specifications 65
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I2C AC Electrical Specifications
Figure 8-61 shows the I2C bus timing.
SDA
202
205
SCL
206 209 211210
203
207
204
208
Figure 8-61. I2C Bus Timing Diagram
Part IX Mechanical Data and Ordering
Information
Table 9-26 provides information on the MPC850 derivative devices.
Table 9-26. MPC850 Family Derivatives
32-Channel HDLC
Device Ethernet Support Number of SCCs
MPC850 N/A One N/A N/A
1
Support
64-Channel HDLC
Support
2
MPC850DE Yes Two N/A N/A
MPC850SR Y es T wo N/A Y es
MPC850DSL Yes Two No No
1
Serial Communication Controller (SCC)
2
50 MHz version supports 64 time slots on a time division multiplexed line using one SCC
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Pin Assignments and Mechanical Dimensions of the PBGA
Table 9-27 identifies the packages and operating frequencies available for the MPC850.
Table 9-27. MPC850 Package/Frequency/Availability
Package Type Frequency (MHz) Temperature (Tj) Order Number
256-Lead Plastic Ball Grid Array
(ZT suffix)
256-Lead Plastic Ball Grid Array
(CZT suffix)
50 0°C to 95°C XPC850ZT50BU
XPC850DEZT50BU
XPC850SRZT50BU
XPC850DSLZT50BU
66 0°C to 95°C XPC850ZT66BU
XPC850DEZT66BU
XPC850SRZT66BU
80 0°C to 95°C XPC850ZT80BU
XPC850DEZT80BU
XPC850SRZT80BU
50 -40°C to 95°C XPC850CZT50BU
XPC850DECZT50BU
XPC850SRCZT50BU
XPC850DSLCZT50BU
66 XPC850CZT66BU
XPC850DECZT66BU
XPC850SRCZT66BU
80 XPC850CZT80B
XPC850DECZT80B
XPC850SRCZT80B
9.1 Pin Assignments and Mechanical Dimensions of
the PBGA
The original pin numbering of the MPC850 conformed to a Motorola proprietary pin
numbering scheme that has since been replaced by the JEDEC pin numbering standard for
this package type. To support customers that are currently using the non-JEDEC pin
numbering scheme, two sets of pinouts, JEDEC and non-JEDEC, are presented in this
document.
67 MPC850 (Rev . A/B/C) Har dware Specifications MOT OROLA
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Pin Assignments and Mechanical Dimensions of the PBGA
Figure 9-62 shows the non-JEDEC pinout of the PBGA package as viewed from the top
surface.
PC14 PB28 PB27
PC15 PA14 PA13 PA12
PA15 PB30 PB29 PC13 TRST
A8 A7 PB31 TDO
A11 A9 A12
A15 A14 A13
A27 A19 A16
VDDL A20 A21
A29 A23 A25
A28 A30 A22
A31 TSIZ0 A26
WE1
TSIZ1
WE0 WE2 GPLA3
GPLA1 GPLA2 CS6
CS4
CS7 CS2
N/C CS3 CS1 BDIP
16 15
PC12
TCK PB24 PB23 PA8 PA7 VDDL PA5 PC7 PC4 PD14 PD10 PD8
TDI PC11
TMS
PB26
PB25 PA9 PC8
A6
A10
A17
N/C
A24
A18
WE3
GPLA0
N/C
CS5
CS0
GPLA4
WR
GPLB4
14 13 12 11 10 9
TEA BG IPB5 IPB1 IPB6
GPLA5
BI
BR
BB IRQ6 IPB3 IPB0 VDDL
T
A
PC9
PB22
N/C
PC10 PA6 PB18 PC5 PD13 PD9 PD4 PD5
N/CN/C
GND
TS IRQ2 IPB7 IPB2
BURST IPB4 ALEB IRQ4
PB19 PA4 PB16 PD15
PB17 PC6 PD11 PD3 IRQ7
VDDH
MODCK1
TEXP
N/C
RSTCONF
HRESET
MODCK2
EXTCLKEXTAL
876
54321
SRESET
D12 D13
D23
D17
D15 D14
D22
D25
D28 D24
D26
DP1
WAITB
PORESET
KAPWR
XTAL
PD12
D27
D10
D18
D20
D31
DP2
DP0
VSSSYN1VSSSYN
PD7 PD6
N/C
IRQ1 IRQ0
D8 D0
D4
D1
D11
D9
D2 D3
D16
D5
D19
VDDL
D21 D6
D29
D7
D30 CLKOUT
DP3
N/C
XFC VDDSYN
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
Figure 9-62. Pin Assignments for the PBGA (Top View)—non-JEDEC Standard
68 MPC850 (Rev . A/B/C) Har dware Specifications MOT OROLA
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Pin Assignments and Mechanical Dimensions of the PBGA
Figure 9-63 shows the JEDEC pinout of the PBGA package as viewed from the top surface.
PC14 PB28 PB27
PC15 PA14 PA13 PA12
PA15 PB30 PB29 PC13 TRST
A8 A7 PB31 TDO
A11 A9 A12
A15 A14 A13
A27 A19 A16
VDDL A20 A21
A29 A23 A25
A28 A30 A22
A31 TSIZ0 A26
WE1
TSIZ1
WE0 WE2 GPLA3
GPLA2
GPLA1
CS4 CS7 CS2
N/C CS3 CS1 BDIP
17 16
PC12
TCK PB24 PB23 PA8 PA7 VDDL PA5 PC7 PC4 PD14 PD10 PD8
TDI PC11
TMS
PB26
PB25 PA9 PC8
A6
A10
A17
N/C
A24
A18
WE3
GPLA0
N/C
CS5
WR
CS6
GPLB4
15 14 13 12 11 10
GPLA4
CS0
TEA BG IPB5 IPB1 IPB6
GPLA5
BI
BR
BB IRQ6 IPB3 IPB0 VDDL
A
T
PC9
PB22
N/C
PC10 PA6 PB18 PC5 PD13 PD9 PD4 PD5
N/CN/C
GND
TS IRQ2 IPB7 IPB2
BURST IPB4 ALEB IRQ4
PB19 PA4 PB16 PD15
PB17 PC6 PD11 PD3 IRQ7
VDDH
MODCK1
TEXP
N/C
RSTCONF
HRESET
MODCK2
EXTCLKEXTAL
987
65432
SRESET
D12 D13
D23
D17
D15 D14
D22
D25
D28 D24
D26
DP1
WAITB
PORESET
KAPWR
XTAL
PD12
D27
D10
D18
D20
D31
DP2
DP0
VSSSYN1VSSSYN
PD7 PD6
N/C
IRQ1 IRQ0
D8 D0
D4
D1
D11
D9
D2 D3
D16
D5
D19
VDDL
D21 D6
D29
D7
D30 CLKOUT
DP3
N/C
VDDSYN
XFC
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
Figure 9-63. Pin Assignments for the PBGA (Top View)—JEDEC Standard
For more information on the printed circuit board layout of the PBGA package, including
thermal via design and suggested pad layout, please refer to AN-1231/D, Plastic Ball Grid
Array Application Note available from your local Motorola sales office.
MOTOROLA MPC850 (Rev . A/B/C) Har dware Specifications 69
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Pin Assignments and Mechanical Dimensions of the PBGA
Figure 9-64 shows the non-JEDEC package dimensions of the PBGA.
A1
A
C
256X
SEATING
PLANE
SIDE VIEW
0.20 C
0.35 C
A2
A3
4X
(E1)
0.20
A
D
D2
E
E2
TOP VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM
SOLDER BALL DIAMETER, PARALLEL TO PRIMARY
DATUM C.
4. PRIMARY DATUM C AND THE SEATING PLANE ARE
DEFINED BY THE SPHERICAL CROWNS OF THE
SOLDER BALLS.
MILLIMETERS
DIM MIN MAX
A 1.91 2.35
A1 0.50 0.70
A2 1.12 1.22
A3 0.29 0.43
b 0.60 0.90
D 23.00 BSC
D1 19.05 REF
D2
19.00 20.00
E 23.00 BSC
E1 19.05 REF
E2 19.00 20.00
e 1.27 BSC
B
(D1)
15X
e
T
R
P
N
15X
e
4X
/2
e
654321
7 8 9 10 11 12 13 14 15
256X
b
0.30 C
BOTTOM VIEW
0.15 C
M
L
K
J
H
G
F
E
D
C
B
A
16
M
AB
M
Figure 9-64. Package Dimensions for the Plastic Ball Grid Array
(PBGA)—non-JEDEC Standard
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Pin Assignments and Mechanical Dimensions of the PBGA
Figure 9-65 shows the JEDEC package dimensions of the PBGA.
A1
A
C
256X
SEATING
PLANE
SIDE VIEW
0.20 C
0.35 C
A2
A3
4X
(E1)
0.20
A
D
D2
E
E2
TOP VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM
SOLDER BALL DIAMETER, PARALLEL TO PRIMARY
DATUM C.
4. PRIMARY DATUM C AND THE SEATING PLANE ARE
DEFINED BY THE SPHERICAL CROWNS OF THE
SOLDER BALLS.
MILLIMETERS
DIM MIN MAX
A 1.91 2.35
A1 0.50 0.70
A2 1.12 1.22
A3 0.29 0.43
b 0.60 0.90
D 23.00 BSC
D1 19.05 REF
D2
19.00 20.00
E 23.00 BSC
E1 19.05 REF
E2 19.00 20.00
e 1.27 BSC
B
(D1)
15X
e
U
T
R
P
15X
e
4X
/2
e
765432
8 9 10 11 12 13 14 15 16
256X
b
0.30 C
BOTTOM VIEW
0.15 C
N
M
L
K
J
H
G
F
E
D
C
B
17
M
AB
M
CASE 1130-01
ISSUE B
Figure 9-65. Package Dimensions for the Plastic Ball Grid Array (PBGA)—JEDEC
Standard
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Pin Assignments and Mechanical Dimensions of the PBGA
Part X Document Revision History
Table 10-28 lists significant changes between revisions of this document.
Table 10-28. Document Revision History
Revision Date Change
0.1 11/2001 Removed reference to 5 Volt tolerance capability on peripheral interface pins.
Replaced SI and IDL timing diagrams with better images. Updated to new
template, added this revision table.
0.2 04/2002 Updated power numbers and added Rev. C
1 10/2002 Added MPC850DSL. Corrected Figure 6-25 on page 37.
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HOME PAGE:
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Information in this document is provided solely to enable system and software implementers to use
Motorola products. There are no express or implied cop yright licenses granted hereunder to design
or fabricate any integrated circuits or integrated circuits based on the inf ormation in this document.
Motorola reserves the right to make changes without further notice to any products herein.
Motorola makes no warranty, representation or guarantee regarding the suitability of its products
for any particular purpose, nor does Motorola assume any liability arising out of the application or
use of any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters which may be provided in
Motorola data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated
for each customer application by customer’s technical experts. Motorola does not convey any
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application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office.
digital dna is a trademark of Motorola, Inc. All other product or service names are the property of
their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
© Motorola, Inc. 2002
MPC850ABEC/D
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