Motorola MPC8260 User Manual

MPC8260UM/D

4/1999

Rev. 0

MPC8260 PowerQUICC II

UserÕs Manual

ª

ª

PowerQUICC II, Mfax, and DigitalDNA are trademarks of Motorola, Inc.
The PowerPC name, the PowerPC logotype, PowerPC 601, PowerPC 603, PowerPC 603e, PowerPC 604, PowerPC 604e, and RS/6000 are trademarks of

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C is a registered trademark of Philips Semiconductors

I

Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or implied
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© Motorola, Inc., 1999. All rights reserved.

Overview

PowerPC Processor Core

Memory Map

System Interface Unit (SIU)

Reset

External Signals

60x Signals

The 60x Bus

Clocks and Power Control

Memory Controller

Secondary (L2) Cache Support

IEEE 1149.1 Test Access Port

Communications Processor Module Overview

Serial Interface with Time-Slot Assigner

CPM Multiplexing

Baud-Rate Generators (BRGs)

Timers

SDMA Channels and IDMA Emulation

Serial Communications Controllers (SCCs)

SCC UART Mode
SCC HDLC Mode

SCC BISYNC Mode

SCC Transparent Mode

SCC Ethernet Mode

SCC AppleTalk Mode

Serial Management Controllers (SMCs)

Multi-Channel Controllers (MCCs)

Fast Communications Controllers

ATM Controller

Fast Ethernet Controller

FCC HDLC Controller

FCC Transparent Controller

Serial Peripheral Interface (SPI)

2

I

C Controller

Parallel I/O Ports

Register Quick Reference Guide

Glossary

Index

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

35

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IND

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35

A

GLO

IND

Overview
PowerPC Processor Core
Memory Map
System Interface Unit (SIU)

Reset
External Signals

60x Signals
The 60x Bus
Clocks and Power Control
Memory Controller
Secondary (L2) Cache Support
IEEE 1149.1 Test Access Port
Communications Processor Module Overview
Serial Interface with Time-Slot Assigner
CPM Multiplexing
Baud-Rate Generators (BRGs)
Timers
SDMA Channels and IDMA Emulation
Serial Communications Controllers (SCCs)
SCC UART Mode
SCC HDLC Mode
SCC BISYNC Mode
SCC Transparent Mode
SCC Ethernet Mode
SCC AppleTalk Mode
Serial Management Controllers (SMCs)
Multi-Channel Controllers (MCCs)
Fast Communications Controllers

ATM Controller
Fast Ethernet Controller
FCC HDLC Controller
FCC Transparent Controller
Serial Peripheral Interface (SPI)

2

I

C Controller

Parallel I/O Ports

Register Quick Reference Guide
Glossary
Index

CONTENTS

Paragraph
Number

Title

Page

Number

About This Book

Before Using this ManualÑImportant Note.......................................................... lv

Audience ................................................................................................................ lv

Organization.......................................................................................................... lvi

Suggested Reading................................................................................................ lix

MPC8xx Documentation .............................................................................. lix

PowerPC Documentation ............................................................................. lix

Conventions ........................................................................................................... lx

Acronyms and Abbreviations ............................................................................... lxi

PowerPC Architecture Terminology Conventions ............................................. lxiv

Chapter 1

Overview

1.1 Features................................................................................................................ 1-1

1.2 MPC8260Õs Architecture Overview .................................................................... 1-4

1.2.1 MPC603e Core ................................................................................................ 1-5

1.2.2 System Interface Unit (SIU) ............................................................................ 1-6

1.2.3 Communications Processor Module (CPM) .................................................... 1-6

1.3 Software Compatibility Issues ............................................................................. 1-7

1.3.1 Signals.............................................................................................................. 1-7

1.4 Differences between MPC860 and MPC8260..................................................... 1-9

1.5 Serial Protocol Table............................................................................................ 1-9

1.6 MPC8260 Configurations .................................................................................. 1-10

1.6.1 Pin Configurations ......................................................................................... 1-10

1.6.2 Serial Performance......................................................................................... 1-10

1.7 MPC8260 Application Examples ...................................................................... 1-11

1.7.1 Examples of Communication Systems .......................................................... 1-11

1.7.1.1 Remote Access Server ............................................................................... 1-11

1.7.1.2 Regional Office Router.............................................................................. 1-12

1.7.1.3 LAN-to-WAN Bridge Router .................................................................... 1-13

1.7.1.4 Cellular Base Station ................................................................................. 1-14

1.7.1.5 Telecommunications Switch Controller ....................................................1-14

1.7.1.6 SONET Transmission Controller .............................................................. 1-15

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CONTENTS

Paragraph
Number

1.7.2 Bus Configurations.........................................................................................1-15

1.7.2.1 Basic System ..............................................................................................1-15

1.7.2.2 High-Performance Communication ...........................................................1-16

1.7.2.3 High-Performance System Microprocessor ...............................................1-17

Title

Chapter 2

Page

Number

PowerPC Processor Core

2.1 Overview ..............................................................................................................2-1

2.2 PowerPC Processor Core Features ......................................................................2-3

2.2.1 Instruction Unit.................................................................................................2-5

2.2.2 Instruction Queue and Dispatch Unit ...............................................................2-5

2.2.3 Branch Processing Unit (BPU).........................................................................2-6

2.2.4 Independent Execution Units ...........................................................................2-6

2.2.4.1 Integer Unit (IU)...........................................................................................2-6

2.2.4.2 Load/Store Unit (LSU).................................................................................2-7

2.2.4.3 System Register Unit (SRU) ........................................................................2-7

2.2.5 Completion Unit ...............................................................................................2-7

2.2.6 Memory Subsystem Support ............................................................................2-8

2.2.6.1 Memory Management Units (MMUs) .........................................................2-8

2.2.6.2 Cache Units ..................................................................................................2-8

2.3 Programming Model.............................................................................................2-8

2.3.1 Register Set.......................................................................................................2-8

2.3.1.1 PowerPC Register Set ..................................................................................2-9

2.3.1.2 MPC8260-Specific Registers .....................................................................2-11

2.3.1.2.1 Hardware Implementation-Dependent Register 0 (HID0) .....................2-11

2.3.1.2.2 Hardware Implementation-Dependent Register 1 (HID1) .....................2-14

2.3.1.2.3 Hardware Implementation-Dependent Register 2 (HID2) .....................2-15

2.3.1.2.4 Processor Version Register (PVR).........................................................2-16

2.3.2 PowerPC Instruction Set and Addressing Modes...........................................2-16

2.3.2.1 Calculating Effective Addresses ................................................................2-16

2.3.2.2 PowerPC Instruction Set ............................................................................2-16

2.3.2.3 MPC8260 Implementation-Specific Instruction Set ..................................2-18

2.4 Cache Implementation........................................................................................2-18

2.4.1 PowerPC Cache Model...................................................................................2-18

2.4.2 MPC8260 Implementation-Specific Cache Implementation..........................2-19

2.4.2.1 Data Cache .................................................................................................2-19

2.4.2.2 Instruction Cache........................................................................................2-21

2.4.2.3 Cache Locking............................................................................................2-21

2.4.2.3.1 Entire Cache Locking.............................................................................2-21

2.4.2.3.2 Way Locking ..........................................................................................2-21

2.5 Exception Model.................................................................................................2-22

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Paragraph
Number

2.5.1 PowerPC Exception Model ............................................................................ 2-22

2.5.2 MPC8260 Implementation-Specific Exception Model..................................2-23

2.5.3 Exception Priorities........................................................................................2-26

2.6 Memory Management ........................................................................................2-26

2.6.1 PowerPC MMU Model ..................................................................................2-27

2.6.2 MPC8260 Implementation-Specific MMU Features ..................................... 2-28

2.7 Instruction Timing.............................................................................................. 2-29

2.8 Differences between the MPC8260Õs Core and the PowerPC 603e

Microprocessor............................................................................................... 2-30

Title

Chapter 3

Page

Number

Memory Map

Chapter 4

System Interface Unit (SIU)

4.1 System Configuration and Protection ..................................................................4-2

4.1.1 Bus Monitor .....................................................................................................4-3

4.1.2 Timers Clock....................................................................................................4-4

4.1.3 Time Counter (TMCNT).................................................................................. 4-4

4.1.4 Periodic Interrupt Timer (PIT) ......................................................................... 4-5

4.1.5 Software Watchdog Timer ............................................................................... 4-6

4.2 Interrupt Controller ..............................................................................................4-7

4.2.1 Interrupt Configuration ....................................................................................4-8

4.2.2 Interrupt Source Priorities ................................................................................ 4-9

4.2.2.1 SCC, FCC, and MCC Relative Priority .....................................................4-12

4.2.2.2 PIT, TMCNT, and IRQ Relative Priority ..................................................4-12

4.2.2.3 Highest Priority Interrupt ........................................................................... 4-13

4.2.3 Masking Interrupt Sources ............................................................................. 4-13

4.2.4 Interrupt Vector Generation and Calculation.................................................4-14

4.2.4.1 Port C External Interrupts ..........................................................................4-16

4.3 Programming Model ..........................................................................................4-17

4.3.1 Interrupt Controller Registers ........................................................................4-17

4.3.1.1 SIU Interrupt Configuration Register (SICR)............................................4-17

4.3.1.2 SIU Interrupt Priority Register (SIPRR)....................................................4-18

4.3.1.3 CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L) .................4-19

4.3.1.4 SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L).....................4-21

4.3.1.5 SIU Interrupt Mask Registers (SIMR_H and SIMR_L) ............................4-22

4.3.1.6 SIU Interrupt Vector Register (SIVEC).....................................................4-23

4.3.1.7 SIU External Interrupt Control Register (SIEXR).....................................4-24

4.3.2 System Configuration and Protection Registers ............................................4-25

4.3.2.1 Bus Configuration Register (BCR) ........................................................... 4-25

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CONTENTS

Paragraph
Number

4.3.2.2 60x Bus Arbiter Configuration Register (PPC_ACR) ...............................4-28

4.3.2.3 60x Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL) .............4-28

4.3.2.4 Local Bus Arbiter Configuration Register (LCL_ACR)............................4-29

4.3.2.5 Local Bus Arbitration Level Registers (LCL_ALRH and LCL_ACRL)...4-30

4.3.2.6 SIU Module Configuration Register (SIUMCR) .......................................4-31

4.3.2.7 Internal Memory Map Register (IMMR) ...................................................4-34

4.3.2.8 System Protection Control Register (SYPCR)...........................................4-35

4.3.2.9 Software Service Register (SWSR)............................................................4-36

4.3.2.10 60x Bus Transfer Error Status and Control Register 1 (TESCR1).............4-36

4.3.2.11 60x Bus Transfer Error Status and Control Register 2 (TESCR2).............4-37

4.3.2.12 Local Bus Transfer Error Status and Control Register 1 (L_TESCR1) .....4-38

4.3.2.13 Local Bus Transfer Error Status and Control Register 2 (L_TESCR2) .....4-39

4.3.2.14 Time Counter Status and Control Register (TMCNTSC) ..........................4-40

4.3.2.15 Time Counter Register (TMCNT)..............................................................4-41

4.3.2.16 Time Counter Alarm Register (TMCNTAL) .............................................4-41

4.3.3 Periodic Interrupt Registers............................................................................4-42

4.3.3.1 Periodic Interrupt Status and Control Register (PISCR)............................4-42

4.3.3.2 Periodic Interrupt Timer Count Register (PITC) .......................................4-43

4.3.3.3 Periodic Interrupt Timer Register (PITR) ..................................................4-44

4.4 SIU Pin Multiplexing..........................................................................................4-44

Title

Chapter 5

Page

Number

Reset

5.1 Reset Causes.........................................................................................................5-1

5.1.1 Reset Actions....................................................................................................5-2

5.1.2 Power-On Reset Flow.......................................................................................5-2

5.1.3

5.1.4

5.2 Reset Status Register (RSR).................................................................................5-4

5.3 Reset Mode Register (RMR) ................................................................................5-5

5.4 Reset Configuration..............................................................................................5-6

5.4.1 Hard Reset Configuration Word.......................................................................5-8

5.4.2 Hard Reset Configuration Examples ................................................................5-9

5.4.2.1 Single MPC8260 with Default Configuration..............................................5-9

5.4.2.2 Single MPC8260 Configured from Boot EPROM.....................................5-10

5.4.2.3 Multiple MPC8260s Configured from Boot EPROM................................5-10

5.4.2.4 Multiple MPC8260s in a System with No EPROM...................................5-12

viii

HRESET
SRESET

Flow .................................................................................................5-3

Flow...................................................................................................5-3

Chapter 6

MPC8260 PowerQUICC II UserÕs Manual

MOTOROLA

CONTENTS

Paragraph
Number

Title

Page

Number

External Signals

6.1 Functional Pinout .................................................................................................6-1

6.2 Signal Descriptions ..............................................................................................6-2

Chapter 7

60x Signals

7.1 Signal Configuration ............................................................................................7-2

7.2 Signal Descriptions ..............................................................................................7-3

7.2.1 Address Bus Arbitration Signals......................................................................7-3

7.2.1.1 Bus Request (BR)ÑOutput .........................................................................7-3

7.2.1.1.1 Address Bus Request (BR)ÑOutput .......................................................7-3

7.2.1.1.2 Address Bus Request (BR)ÑInput..........................................................7-4

7.2.1.2 Bus Grant (BG) ............................................................................................7-4

7.2.1.2.1 Bus Grant (BG)ÑInput............................................................................7-4

7.2.1.2.2 Bus Grant (BG)ÑOutput.........................................................................7-5

7.2.1.3 Address Bus Busy (ABB) ............................................................................7-5

7.2.1.3.1 Address Bus Busy (ABB)ÑOutput ......................................................... 7-5

7.2.1.3.2 Address Bus Busy (ABB)ÑInput............................................................ 7-6

7.2.2 Address Transfer Start Signal ..........................................................................7-6

7.2.2.1 Transfer Start (TS) .......................................................................................7-6

7.2.2.1.1 Transfer Start (TS)ÑOutput .................................................................... 7-6

7.2.2.2 Transfer Start (TS)ÑInput...........................................................................7-6

7.2.3 Address Transfer Signals .................................................................................7-7

7.2.3.1 Address Bus (A[0Ð31]) ................................................................................7-7

7.2.3.1.1 Address Bus (A[0Ð31])ÑOutput.............................................................7-7

7.2.3.1.2 Address Bus (A[0Ð31])ÑInput................................................................7-7

7.2.4 Address Transfer Attribute Signals..................................................................7-7

7.2.4.1 Transfer Type (TT[0Ð4]).............................................................................. 7-8

7.2.4.1.1 Transfer Type (TT[0Ð4])ÑOutput...........................................................7-8

7.2.4.1.2 Transfer Type (TT[0Ð4])ÑInput .............................................................7-8

7.2.4.2 Transfer Size (TSIZ[0Ð3]) ...........................................................................7-8

7.2.4.3 Transfer Burst (TBST) ................................................................................. 7-8

7.2.4.4 Global (GBL) ...............................................................................................7-9

7.2.4.4.1 Global (GBL)ÑOutput............................................................................7-9

7.2.4.4.2 Global (GBL)ÑInput...............................................................................7-9

7.2.4.5 Caching-Inhibited (CI)ÑOutput..................................................................7-9

7.2.4.6 Write-Through (WT)ÑOutput ....................................................................7-9

7.2.5 Address Transfer Termination Signals...........................................................7-10

7.2.5.1 Address Acknowledge (AACK) ................................................................7-10

7.2.5.1.1 Address Acknowledge (AACK)ÑOutput .............................................7-10

7.2.5.1.2 Address Acknowledge (AACK)ÑInput................................................7-10

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CONTENTS

Paragraph
Number

7.2.5.2 Address Retry (ARTRY)............................................................................7-11

7.2.5.2.1 Address Retry (ARTRY)ÑOutput.........................................................7-11

7.2.5.2.2 Address Retry (ARTRY)ÑInput ...........................................................7-11

7.2.6 Data Bus Arbitration Signals..........................................................................7-12

7.2.6.1 Data Bus Grant (DBG) ...............................................................................7-12

7.2.6.1.1 Data Bus Grant (DBG)ÑInput ..............................................................7-12

7.2.6.1.2 Data Bus Grant (DBG)ÑOutput............................................................7-12

7.2.6.2 Data Bus Busy (DBB) ................................................................................7-13

7.2.6.2.1 Data Bus Busy (DBB)ÑOutput.............................................................7-13

7.2.6.2.2 Data Bus Busy (DBB)ÑInput................................................................7-13

7.2.7 Data Transfer Signals .....................................................................................7-13

7.2.7.1 Data Bus (D[0Ð63]) ....................................................................................7-13

7.2.7.1.1 Data Bus (D[0Ð63])ÑOutput.................................................................7-14

7.2.7.1.2 Data Bus (D[0Ð63])ÑInput ...................................................................7-14

7.2.7.2 Data Bus Parity (DP[0Ð7]) .........................................................................7-14

7.2.7.2.1 Data Bus Parity (DP[0Ð7])ÑOutput ......................................................7-14

7.2.7.2.2 Data Bus Parity (DP[0Ð7])ÑInput.........................................................7-15

7.2.8 Data Transfer Termination Signals ................................................................7-15

7.2.8.1 Transfer Acknowledge (TA) ......................................................................7-15

7.2.8.1.1 Transfer Acknowledge (TA)ÑInput......................................................7-15

7.2.8.1.2 Transfer Acknowledge (TA)ÑOutput ...................................................7-16

7.2.8.2 Transfer Error Acknowledge (TEA) ..........................................................7-16

7.2.8.2.1 Transfer Error Acknowledge (TEA)ÑInput..........................................7-16

7.2.8.2.2 Transfer Error Acknowledge (TEA)ÑOutput .......................................7-17

7.2.8.3 Partial Data Valid Indication (PSDVAL)...................................................7-17

7.2.8.3.1 Partial Data Valid (PSDVAL)ÑInput ...................................................7-17

7.2.8.3.2 Partial Data Valid (PSDVAL)ÑOutput.................................................7-18

Title

Page

Number

Chapter 8

The 60x Bus

8.1 Terminology .........................................................................................................8-1

8.2 Bus Configuration.................................................................................................8-2

8.2.1 Single MPC8260 Bus Mode.............................................................................8-2

8.2.2 60x-Compatible Bus Mode...............................................................................8-3

8.3 60x Bus Protocol Overview..................................................................................8-4

8.3.1 Arbitration Phase ..............................................................................................8-5

8.3.2 Address Pipelining and Split-Bus Transactions ...............................................8-7

8.4 Address Tenure Operations ..................................................................................8-7

8.4.1 Address Arbitration ..........................................................................................8-7

8.4.2 Address Pipelining............................................................................................8-9

8.4.3 Address Transfer Attribute Signals ................................................................8-10

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Paragraph
Number

8.4.3.1 Transfer Type Signal (TT[0Ð4]) Encoding ................................................8-10

8.4.3.2 Transfer Code Signals TC[0Ð2] .................................................................8-13

8.4.3.3 TBST and TSIZ[0Ð3] Signals and Size of Transfer................................... 8-13

8.4.3.4 Burst Ordering During Data Transfers.......................................................8-14

8.4.3.5 Effect of Alignment on Data Transfers......................................................8-14

8.4.3.6 Effect of Port Size on Data Transfers ........................................................8-16

8.4.3.7 60x-Compatible Bus ModeÑSize Calculation..........................................8-19

8.4.3.8 Extended Transfer Mode............................................................................ 8-20

8.4.4 Address Transfer Termination .......................................................................8-23

8.4.4.1 Address Retried with ARTRY ...................................................................8-23

8.4.4.2 Address Tenure Timing Configuration ...................................................... 8-25

8.4.5 Pipeline Control .............................................................................................8-26

8.5 Data Tenure Operations .....................................................................................8-26

8.5.1 Data Bus Arbitration ......................................................................................8-26

8.5.2 Data Streaming Mode ....................................................................................8-27

8.5.3 Data Bus Transfers and Normal Termination ................................................ 8-27

8.5.4 Effect of ARTRY Assertion on Data Transfer and Arbitration .....................8-28

8.5.5 Port Size Data Bus Transfers and PSDVAL Termination .............................8-28

8.5.6 Data Bus Termination by Assertion of TEA.................................................. 8-30

8.6 Memory CoherencyÑMEI Protocol..................................................................8-31

8.7 Processor State Signals.......................................................................................8-32

8.7.1 Support for the lwarx/stwcx. Instruction Pair ................................................8-33

8.7.2 TLBISYNC Input........................................................................................... 8-33

8.8 Little-Endian Mode ............................................................................................8-33

Title

Page

Number

Chapter 9

Clocks and Power Control

9.1 Clock Unit ............................................................................................................9-1

9.2 Clock Configuration.............................................................................................9-2

9.3 External Clock Inputs........................................................................................... 9-5

9.4 Main PLL .............................................................................................................9-5

9.4.1 PLL Block Diagram ......................................................................................... 9-5

9.4.2 Skew Elimination ............................................................................................. 9-6

9.5 Clock Dividers......................................................................................................9-6

9.6 The MPC8260Õs Internal Clock Signals...............................................................9-6

9.6.1 General System Clocks ....................................................................................9-7

9.7 PLL Pins...............................................................................................................9-7

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Paragraph
Number

9.8 System Clock Control Register (SCCR) ..............................................................9-8

9.9 System Clock Mode Register (SCMR) ................................................................9-9

9.10 Basic Power Structure ........................................................................................9-10

Title

Chapter 10

Page

Number

Memory Controller

10.1 Features...............................................................................................................10-3

10.2 Basic Architecture ..............................................................................................10-5

10.2.1 Address and Address Space Checking ...........................................................10-8

10.2.2 Page Hit Checking..........................................................................................10-9

10.2.3 Error Checking and Correction (ECC) ...........................................................10-9

10.2.4 Parity Generation and Checking.....................................................................10-9

10.2.5 Transfer Error Acknowledge (TEA) Generation............................................10-9

10.2.6 Machine Check Interrupt (MCP) Generation .................................................10-9

10.2.7 Data Buffer Controls (BCTLx) ....................................................................10-10

10.2.8 Atomic Bus Operation..................................................................................10-10

10.2.9 Data Pipelining ............................................................................................10-10

10.2.10 External Memory Controller Support...........................................................10-11

10.2.11 External Address Latch Enable Signal (ALE)..............................................10-11

10.2.12 ECC/Parity Byte Select (PBSE) ...................................................................10-11

10.2.13 Partial Data Valid Indication (PSDVAL).....................................................10-12

10.3 Register Descriptions........................................................................................10-13

x

10.3.1 Base Registers (BR

10.3.2 Option Registers (ORx)................................................................................10-16

10.3.3 60x SDRAM Mode Register (PSDMR) .......................................................10-21

10.3.4 Local Bus SDRAM Mode Register (LSDMR) ............................................10-24

10.3.5 Machine A/B/C Mode Registers (MxMR) ...................................................10-26

10.3.6 Memory Data Register (MDR).....................................................................10-28

10.3.7 Memory Address Register (MAR) ...............................................................10-29

10.3.8 60x Bus-Assigned UPM Refresh Timer (PURT).........................................10-30

10.3.9 Local Bus-Assigned UPM Refresh Timer (LURT)......................................10-30

10.3.10 60x Bus-Assigned SDRAM Refresh Timer (PSRT) ....................................10-31

10.3.11 Local Bus-Assigned SDRAM Refresh Timer (LSRT).................................10-32

10.3.12 Memory Refresh Timer Prescaler Register (MPTPR) .................................10-32

10.3.13 60x Bus Error Status and Control Registers (TESCRx)...............................10-33

10.3.14 Local Bus Error Status and Control Registers (L_TESCRx) .......................10-33

10.4 SDRAM Machine.............................................................................................10-33

10.4.1 Supported SDRAM Configurations .............................................................10-35

10.4.2 SDRAM Power-On Initialization .................................................................10-35

10.4.3 JEDEC-Standard SDRAM Interface Commands.........................................10-35

10.4.4 Page-Mode Support and Pipeline Accesses .................................................10-36

) ...................................................................................10-14

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10.4.5 Bank Interleaving ........................................................................................ 10-36

10.4.5.1 SDRAM Address Multiplexing (SDAM and BSMA) .............................10-37

10.4.6 SDRAM Device-Specific Parameters .......................................................... 10-38

10.4.6.1 Precharge-to-Activate Interval ................................................................. 10-38

10.4.6.2 Activate to Read/Write Interval ...............................................................10-39

10.4.6.3 Column Address to First Data OutÑCAS Latency .................................10-40

10.4.6.4 Last Data Out to Precharge ......................................................................10-40

10.4.6.5 Last Data In to PrechargeÑWrite Recovery ...........................................10-41

10.4.6.6 Refresh Recovery Interval (RFRC).......................................................... 10-41

10.4.6.7 External Address Multiplexing Signal ..................................................... 10-41

10.4.6.8 External Address and Command Buffers (BUFCMD) ............................10-42

10.4.7 SDRAM Interface Timing............................................................................10-42

10.4.8 SDRAM Read/Write Transactions............................................................... 10-46

10.4.9 SDRAM Mode-Set Command Timing ........................................................10-46

10.4.10 SDRAM Refresh .......................................................................................... 10-47

10.4.11 SDRAM Refresh Timing .............................................................................10-47

10.4.12 SDRAM Configuration Examples ...............................................................10-48

10.4.12.1 SDRAM Configuration Example (Page-Based Interleaving) .................. 10-48

10.4.13 SDRAM Configuration Example (Bank-Based Interleaving) .....................10-50

10.5 General-Purpose Chip-Select Machine (GPCM) ............................................. 10-51

10.5.1 Timing Configuration...................................................................................10-52

10.5.1.1 Chip-Select Assertion Timing..................................................................10-53

10.5.1.2 Chip-Select and Write Enable Deassertion Timing .................................10-54

10.5.1.3 Relaxed Timing........................................................................................10-55

10.5.1.4 Output Enable (OE) Timing.....................................................................10-57

10.5.1.5 Programmable Wait State Configuration ................................................. 10-57

10.5.1.6 Extended Hold Time on Read Accesses ..................................................10-57

10.5.2 External Access Termination ....................................................................... 10-60

10.5.3 Boot Chip-Select Operation ......................................................................... 10-61

10.5.4 Differences between MPC8xxÕs GPCM and MPC8260Õs GPCM............... 10-62

10.6 User-Programmable Machines (UPMs) ........................................................... 10-62

10.6.1 Requests .......................................................................................................10-64

10.6.1.1 Memory Access Requests ........................................................................10-65

10.6.1.2 UPM Refresh Timer Requests .................................................................10-65

10.6.1.3 Software RequestsÑrun Command .........................................................10-66

10.6.1.4 Exception Requests ..................................................................................10-66

10.6.2 Programming the UPMs............................................................................... 10-66

10.6.3 Clock Timing ...............................................................................................10-67

10.6.4 The RAM Array ........................................................................................... 10-69

10.6.4.1 RAM Words ............................................................................................. 10-70

10.6.4.1.1 Chip-Select Signals (CxTx) .................................................................10-74

10.6.4.1.2 Byte-Select Signals (BxTx) .................................................................10-75

10.6.4.1.3 General-Purpose Signals (GxTx, GOx) ...............................................10-76

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10.6.4.1.4 Loop Control ........................................................................................10-76

10.6.4.1.5 Repeat Execution of Current RAM Word (REDO) ............................10-76

10.6.4.2 Address Multiplexing ...............................................................................10-77

10.6.4.3 Data Valid and Data Sample Control .......................................................10-77

10.6.4.4 Signals Negation.......................................................................................10-78

10.6.4.5 The Wait Mechanism ...............................................................................10-78

10.6.4.6 Extended Hold Time on Read Accesses ..................................................10-79

10.6.5 UPM DRAM Configuration Example..........................................................10-79

10.6.6 Differences between MPC8xx UPM and MPC8260 UPM ..........................10-80

10.7 Memory System Interface Example Using UPM .............................................10-81

10.7.0.1 EDO Interface Example ...........................................................................10-92

10.8 Handling Devices with Slow or Variable Access Times................................10-100

10.8.1 Hierarchical Bus Interface Example...........................................................10-100

10.8.2 Slow Devices Example...............................................................................10-100

10.9 External Master Support (60x-Compatible Mode).........................................10-101

10.9.1 60x-Compatible External Masters..............................................................10-101

10.9.2 MPC8260-Type External Masters..............................................................10-101

10.9.3 Extended Controls in 60x-Compatible Mode.............................................10-101

10.9.4 Using BNKSEL SIgnals in Single-MPC8260 Bus Mode ..........................10-102

10.9.5 Address Incrementing for External Bursting Masters ................................10-102

10.9.6 External Masters Timing ............................................................................10-102

10.9.6.1 Example of External Master Using the SDRAM Machine ....................10-104

Title

Chapter 11

Page

Number

Secondary (L2) Cache Support

11.1 L2 Cache Configurations....................................................................................11-1

11.1.1 Copy-Back Mode............................................................................................11-1

11.1.2 Write-Through Mode......................................................................................11-2

11.1.3 ECC/Parity Mode ...........................................................................................11-4

11.2 L2 Cache Interface Parameters...........................................................................11-7

11.3 System Requirements When Using the L2 Cache Interface...............................11-7

11.4 L2 Cache Operation............................................................................................11-7

11.5 Timing Example .................................................................................................11-8

Chapter 12

IEEE 1149.1 Test Access Port

12.1 Overview ............................................................................................................12-1

12.2 TAP Controller ...................................................................................................12-2

12.3 Boundary Scan Register .....................................................................................12-3

12.4 Instruction Register...........................................................................................12-28

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12.5 MPC8260 Restrictions .....................................................................................12-30

12.6 Nonscan Chain Operation ................................................................................12-30

Title

Chapter 13

Page

Number

Communications Processor Module Overview

13.1 Features ..............................................................................................................13-1

13.2 MPC8260

13.3 Communications Processor (CP) .......................................................................13-4

13.3.1 Features ..........................................................................................................13-4

13.3.2 CP Block Diagram .........................................................................................13-4

13.3.3 PowerPC Core Interface................................................................................. 13-6

13.3.4 Peripheral Interface ........................................................................................ 13-6

13.3.5 Execution from RAM..................................................................................... 13-7

13.3.6 RISC Controller Configuration Register (RCCR) .........................................13-7

13.3.7 RISC Time-Stamp Control Register (RTSCR) .............................................. 13-9

13.3.8 RISC Time-Stamp Register (RTSR)............................................................13-10

13.3.9 RISC Microcode Revision Number .............................................................13-10

13.4 Command Set ................................................................................................... 13-11

13.4.1 CP Command Register (CPCR) ................................................................... 13-11

13.4.1.1 CP Commands.......................................................................................... 13-13

13.4.2 Command Register Example........................................................................13-15

13.4.3 Command Execution Latency ...................................................................... 13-15

13.5 Dual-Port RAM................................................................................................13-15

13.5.1 Buffer Descriptors (BDs) ............................................................................. 13-17

13.5.2 Parameter RAM ...........................................................................................13-17

13.6 RISC Timer Tables...........................................................................................13-18

13.6.1 RISC Timer Table Parameter RAM............................................................. 13-19

13.6.2 RISC Timer Command Register (TM_CMD) .............................................13-20

13.6.3 RISC Timer Table Entries............................................................................ 13-21

13.6.4 RISC Timer Event Register (RTER)/Mask Register (RTMR) ....................13-21

13.6.5 set timer Command ......................................................................................13-22

13.6.6 RISC Timer Initialization Sequence ............................................................13-22

13.6.7 RISC Timer Initialization Example .............................................................13-22

13.6.8 RISC Timer Interrupt Handling ...................................................................13-23

13.6.9 RISC Timer Table Scan Algorithm..............................................................13-23

13.6.10 Using the RISC Timers to Track CP Loading .............................................13-24

Serial Configurations ........................................................................ 13-3

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Chapter 14

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Serial Interface with Time-Slot Assigner

14.1 Features...............................................................................................................14-3

14.2 Overview ............................................................................................................14-4

14.3 Enabling Connections to TSA ............................................................................14-7

14.4 Serial Interface RAM..........................................................................................14-8

14.4.1 One Multiplexed Channel with Static Frames................................................14-9

14.4.2 One Multiplexed Channel with Dynamic Frames ..........................................14-9

14.4.3 Programming SIx RAM Entries ...................................................................14-10

14.4.4 SIx RAM Programming Example ................................................................14-13

14.4.5 Static and Dynamic Routing.........................................................................14-14

14.5 Serial Interface Registers..................................................................................14-17

14.5.1 SI Global Mode Registers (SIxGMR) ..........................................................14-17

14.5.2 SI Mode Registers (SIxMR).........................................................................14-17

14.5.3 SIx RAM Shadow Address Registers (SIxRSR)..........................................14-23

14.5.4 SI Command Register (SIxCMDR)..............................................................14-24

14.5.5 SI Status Registers (SIxSTR) .......................................................................14-25

14.6 Serial Interface IDL Interface Support .............................................................14-25

14.6.1 IDL Interface Example .................................................................................14-26

14.6.2 IDL Interface Programming .........................................................................14-29

14.7 Serial Interface GCI Support ............................................................................14-31

14.7.1 SI GCI Activation/Deactivation Procedure ..................................................14-33

14.7.2 Serial Interface GCI Programming...............................................................14-33

14.7.2.1 Normal Mode GCI Programming.............................................................14-33

14.7.2.2 SCIT Programming ..................................................................................14-33

Chapter 15

CPM Multiplexing

15.1 Features...............................................................................................................15-2

15.2 Enabling Connections to TSA or NMSI.............................................................15-3

15.3 NMSI Configuration...........................................................................................15-4

15.4 CMX Registers ...................................................................................................15-6

15.4.1 CMX UTOPIA Address Register (CMXUAR)..............................................15-7

15.4.2 CMX SI1 Clock Route Register (CMXSI1CR) ...........................................15-10

15.4.3 CMX SI2 Clock Route Register (CMXSI2CR) ...........................................15-11

15.4.4 CMX FCC Clock Route Register (CMXFCR).............................................15-12

15.4.5 CMX SCC Clock Route Register (CMXSCR).............................................15-14

15.4.6 CMX SMC Clock Route Register (CMXSMR)...........................................15-17

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Chapter 16

Page

Number

Baud-Rate Generators (BRGs)

16.1 BRG Configuration Registers 1Ð8 (BRGCx)..................................................... 16-2

16.2 Autobaud Operation on a UART .......................................................................16-4

16.3 UART Baud Rate Examples ..............................................................................16-5

Chapter 17

Timers

17.1 Features ..............................................................................................................17-2

17.2 General-Purpose Timer Units.............................................................................17-2

17.2.1 Cascaded Mode .............................................................................................. 17-3

17.2.2 Timer Global Configuration Registers (TGCR1 and TGCR2) ...................... 17-4

17.2.3 Timer Mode Registers (TMR1ÐTMR4)......................................................... 17-6

17.2.4 Timer Reference Registers (TRR1ÐTRR4).................................................... 17-7

17.2.5 Timer Capture Registers (TCR1ÐTCR4) .......................................................17-8

17.2.6 Timer Counters (TCN1ÐTCN4).....................................................................17-8

17.2.7 Timer Event Registers (TER1ÐTER4) ........................................................... 17-8

Chapter 18

SDMA Channels and IDMA Emulation

18.1 SDMA Bus Arbitration and Bus Transfers ........................................................18-2

18.2 SDMA Registers ................................................................................................18-3

18.2.1 SDMA Status Register (SDSR) .....................................................................18-3

18.2.2 SDMA Mask Register (SDMR) ..................................................................... 18-4

18.2.3 SDMA Transfer Error Address Registers (PDTEA and LDTEA).................18-4

18.2.4 SDMA Transfer Error MSNUM Registers (PDTEM and LDTEM) .............18-4

18.3 IDMA Emulation................................................................................................18-5

18.4 IDMA Features................................................................................................... 18-5

18.5 IDMA Transfers ................................................................................................. 18-6

18.5.1 Memory-to-Memory Transfers ......................................................................18-6

18.5.1.1 External Request Mode .............................................................................. 18-8

18.5.1.2 Normal Mode .............................................................................................18-9

18.5.2 Memory to/from Peripheral Transfers ...........................................................18-9

18.5.2.1 Dual-Address Transfers ...........................................................................18-10

18.5.2.1.1 Peripheral to Memory ..........................................................................18-10

18.5.2.1.2 Memory to Peripheral ..........................................................................18-10

18.5.2.2 Single Address (Fly-By) Transfers ..........................................................18-11

18.5.2.2.1 Peripheral-to-Memory Fly-By Transfers .............................................18-11

18.5.2.2.2 Memory-to-Peripheral Fly-By Transfers .............................................18-11

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18.5.3 Controlling 60x Bus Bandwidth...................................................................18-12

18.6 IDMA Priorities................................................................................................18-12

18.7 IDMA Interface Signals....................................................................................18-12

18.7.1 DREQx and DACKx ....................................................................................18-13

18.7.1.1 Level-Sensitive Mode...............................................................................18-13

18.7.1.2 Edge-Sensitive Mode ...............................................................................18-13

18.7.2 DONEx .........................................................................................................18-14

18.8 IDMA Operation...............................................................................................18-14

18.8.1 Auto Buffer and Buffer Chaining.................................................................18-15

18.8.2 IDMAx Parameter RAM ..............................................................................18-16

18.8.2.1 DMA Channel Mode (DCM) ...................................................................18-18

18.8.2.2 Data Transfer Types as Programmed in DCM .........................................18-20

18.8.2.3 Programming DTS and STS.....................................................................18-20

18.8.3 IDMA Performance ......................................................................................18-22

18.8.4 IDMA Event Register (IDSR) and Mask Register (IDMR).........................18-22

18.8.5 IDMA BDs ...................................................................................................18-23

18.9 IDMA Commands ............................................................................................18-26

18.9.1 start_idma Command....................................................................................18-26

18.9.2 stop_idma Command....................................................................................18-26

18.10 IDMA Bus Exceptions......................................................................................18-27

18.10.1 Externally Recognizing IDMA Operand Transfers......................................18-27

18.11 Programming the Parallel I/O Registers...........................................................18-28

18.12 IDMA Programming Examples........................................................................18-29

18.12.1 Peripheral-to-Memory Mode (60x Bus to Local Bus)ÑIDMA2.................18-29

18.12.2 Memory-to-Peripheral Fly-By Mode (Both on 60x Bus)ÑIDMA3 ............18-30

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Chapter 19

Serial Communications Controllers (SCCs)

19.1 Features...............................................................................................................19-2

19.1.1 The General SCC Mode Registers (GSMR1ÐGSMR4) .................................19-3

19.1.2 Protocol-Specific Mode Register (PSMR) .....................................................19-9

19.1.3 Data Synchronization Register (DSR)............................................................19-9

19.1.4 Transmit-on-Demand Register (TODR).........................................................19-9

19.2 SCC Buffer Descriptors (BDs) .........................................................................19-10

19.3 SCC Parameter RAM .......................................................................................19-13

19.3.1 SCC Base Addresses ....................................................................................19-15

19.3.2 Function Code Registers (RFCR and TFCR)...............................................19-15

19.3.3 Handling SCC Interrupts ..............................................................................19-16

19.3.4 Initializing the SCCs.....................................................................................19-17

19.3.5 Controlling SCC Timing with RTS, CTS, and CD ......................................19-18

19.3.5.1 Synchronous Protocols .............................................................................19-18

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19.3.5.2 Asynchronous Protocols .......................................................................... 19-21

19.3.6 Digital Phase-Locked Loop (DPLL) Operation...........................................19-22

19.3.6.1 Encoding Data with a DPLL .................................................................... 19-24

19.3.7 Clock Glitch Detection................................................................................. 19-26

19.3.8 Reconfiguring the SCCs............................................................................... 19-26

19.3.8.1 General Reconfiguration Sequence for an SCC Transmitter ...................19-26

19.3.8.2 Reset Sequence for an SCC Transmitter .................................................. 19-27

19.3.8.3 General Reconfiguration Sequence for an SCC Receiver ....................... 19-27

19.3.8.4 Reset Sequence for an SCC Receiver ......................................................19-27

19.3.8.5 Switching Protocols .................................................................................19-27

19.3.9 Saving Power ...............................................................................................19-27

Title

Chapter 20

Page

Number

SCC UART Mode

20.1 Features ..............................................................................................................20-2

20.2 Normal Asynchronous Mode .............................................................................20-3

20.3 Synchronous Mode.............................................................................................20-3

20.4 SCC UART Parameter RAM ............................................................................. 20-4

20.5 Data-Handling Methods: Character- or Message-Based.................................... 20-5

20.6 Error and Status Reporting.................................................................................20-6

20.7 SCC UART Commands .....................................................................................20-6

20.8 Multidrop Systems and Address Recognition....................................................20-7

20.9 Receiving Control Characters ............................................................................20-8

20.10 Hunt Mode (Receiver)...................................................................................... 20-10

20.11 Inserting Control Characters into the Transmit Data Stream...........................20-10

20.12 Sending a Break (Transmitter) ......................................................................... 20-11

20.13 Sending a Preamble (Transmitter)....................................................................20-11

20.14 Fractional Stop Bits (Transmitter)....................................................................20-11

20.15 Handling Errors in the SCC UART Controller ................................................ 20-12

20.16 UART Mode Register (PSMR) ........................................................................20-13

20.17 SCC UART Receive Buffer Descriptor (RxBD) .............................................20-15

20.18 SCC UART Transmit Buffer Descriptor (TxBD) ............................................ 20-18

20.19 SCC UART Event Register (SCCE) and Mask Register (SCCM) ..................20-19

20.20 SCC UART Status Register (SCCS)................................................................20-21

20.21 SCC UART Programming Example ................................................................20-22

20.22 S-Records Loader Application .........................................................................20-23

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Chapter 21

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SCC HDLC Mode

21.1 SCC HDLC Features ..........................................................................................21-2

21.2 SCC HDLC Channel Frame Transmission.........................................................21-2

21.3 SCC HDLC Channel Frame Reception ..............................................................21-3

21.4 SCC HDLC Parameter RAM .............................................................................21-3

21.5 Programming the SCC in HDLC Mode .............................................................21-5

21.6 SCC HDLC Commands .....................................................................................21-5

21.7 Handling Errors in the SCC HDLC Controller ..................................................21-6

21.8 HDLC Mode Register (PSMR) ..........................................................................21-7

21.9 SCC HDLC Receive Buffer Descriptor (RxBD)................................................21-8

21.10 SCC HDLC Transmit Buffer Descriptor (TxBD) ............................................21-11

21.11 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) ......................21-12

21.12 SCC HDLC Status Register (SCCS) ................................................................21-14

21.13 SCC HDLC Programming Examples...............................................................21-14

21.13.1 SCC HDLC Programming Example #1 .......................................................21-15

21.13.2 SCC HDLC Programming Example #2 .......................................................21-16

21.14 HDLC Bus Mode with Collision Detection .....................................................21-17

21.14.1 HDLC Bus Features .....................................................................................21-19

21.14.2 Accessing the HDLC Bus.............................................................................21-19

21.14.3 Increasing Performance ................................................................................21-20

21.14.4 Delayed RTS Mode ......................................................................................21-21

21.14.5 Using the Time-Slot Assigner (TSA) ...........................................................21-22

21.14.6 HDLC Bus Protocol Programming ..............................................................21-23

21.14.6.1 Programming GSMR and PSMR for the HDLC Bus Protocol ................21-23

21.14.6.2 HDLC Bus Controller Programming Example ........................................21-23

Chapter 22

SCC BISYNC Mode

22.1 Features...............................................................................................................22-2

22.2 SCC BISYNC Channel Frame Transmission.....................................................22-2

22.3 SCC BISYNC Channel Frame Reception ..........................................................22-3

22.4 SCC BISYNC Parameter RAM..........................................................................22-3

22.5 SCC BISYNC Commands..................................................................................22-5

22.6 SCC BISYNC Control Character Recognition...................................................22-6

22.7 BISYNC SYNC Register (BSYNC)...................................................................22-7

22.8 SCC BISYNC DLE Register (BDLE)................................................................22-8

22.9 Sending and Receiving the Synchronization Sequence......................................22-9

22.10 Handling Errors in the SCC BISYNC ................................................................22-9

22.11 BISYNC Mode Register (PSMR).....................................................................22-10

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22.12 SCC BISYNC Receive BD (RxBD) ................................................................22-12

22.13 SCC BISYNC Transmit BD (TxBD)...............................................................22-14

22.14 BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM) .............. 22-15

22.15 SCC Status Registers (SCCS) ..........................................................................22-16

22.16 Programming the SCC BISYNC Controller ....................................................22-17

22.17 SCC BISYNC Programming Example ............................................................22-18

Title

Chapter 23

Page

Number

SCC Transparent Mode

23.1 Features ..............................................................................................................23-1

23.2 SCC Transparent Channel Frame Transmission Process...................................23-2

23.3 SCC Transparent Channel Frame Reception Process ........................................23-2

23.4 Achieving Synchronization in Transparent Mode .............................................23-3

23.4.1 Synchronization in NMSI Mode .................................................................... 23-3

23.4.1.1 In-Line Synchronization Pattern ................................................................23-3

23.4.1.2 External Synchronization Signals ..............................................................23-4

23.4.1.2.1 External Synchronization Example........................................................ 23-4

23.4.1.3 Transparent Mode without Explicit Synchronization ................................23-5

23.4.2 Synchronization and the TSA ........................................................................23-5

23.4.2.1 Inline Synchronization Pattern ...................................................................23-6

23.4.2.2 Inherent Synchronization ...........................................................................23-6

23.4.3 End of Frame Detection .................................................................................23-6

23.5 CRC Calculation in Transparent Mode..............................................................23-6

23.6 SCC Transparent Parameter RAM.....................................................................23-6

23.7 SCC Transparent Commands.............................................................................23-7

23.8 Handling Errors in the Transparent Controller ..................................................23-8

23.9 Transparent Mode and the PSMR ...................................................................... 23-9

23.10 SCC Transparent Receive Buffer Descriptor (RxBD) ....................................... 23-9

23.11 SCC Transparent Transmit Buffer Descriptor (TxBD).................................... 23-10

23.12 SCC Transparent Event Register (SCCE)/Mask Register (SCCM)................. 23-12

23.13 SCC Status Register in Transparent Mode (SCCS) .........................................23-13

23.14 SCC2 Transparent Programming Example ......................................................23-13

Chapter 24

SCC Ethernet Mode

24.1 Ethernet on the MPC8260..................................................................................24-2

24.2 Features ..............................................................................................................24-3

24.3 Connecting the MPC8260 to Ethernet ...............................................................24-4

24.4 SCC Ethernet Channel Frame Transmission...................................................... 24-5

24.5 SCC Ethernet Channel Frame Reception ...........................................................24-6

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24.6 The Content-Addressable Memory (CAM) Interface ........................................24-7

24.7 SCC Ethernet Parameter RAM...........................................................................24-8

24.8 Programming the Ethernet Controller ..............................................................24-10

24.9 SCC Ethernet Commands.................................................................................24-10

24.10 SCC Ethernet Address Recognition .................................................................24-11

24.11 Hash Table Algorithm ......................................................................................24-13

24.12 Interpacket Gap Time .......................................................................................24-13

24.13 Handling Collisions ..........................................................................................24-13

24.14 Internal and External Loopback .......................................................................24-14

24.15 Full-Duplex Ethernet Support ..........................................................................24-14

24.16 Handling Errors in the Ethernet Controller ......................................................24-14

24.17 Ethernet Mode Register (PSMR)......................................................................24-15

24.18 SCC Ethernet Receive BD................................................................................24-17

24.19 SCC Ethernet Transmit Buffer Descriptor .......................................................24-19

24.20 SCC Ethernet Event Register (SCCE)/Mask Register (SCCM).......................24-21

24.21 SCC Ethernet Programming Example..............................................................24-23

Title

Chapter 25

Page

Number

SCC AppleTalk Mode

25.1 Operating the LocalTalk Bus..............................................................................25-1

25.2 Features...............................................................................................................25-2

25.3 Connecting to AppleTalk....................................................................................25-3

25.4 Programming the SCC in AppleTalk Mode .......................................................25-3

25.4.1 Programming the GSMR................................................................................25-3

25.4.2 Programming the PSMR.................................................................................25-4

25.4.3 Programming the TODR ................................................................................25-4

25.4.4 SCC AppleTalk Programming Example ........................................................25-4

Chapter 26

Serial Management Controllers (SMCs)

26.1 Features...............................................................................................................26-2

26.2 Common SMC Settings and Configurations ......................................................26-3

26.2.1 SMC Mode Registers (SMCMR1/SMCMR2) ...............................................26-3

26.2.2 SMC Buffer Descriptor Operation .................................................................26-5

26.2.3 SMC Parameter RAM ....................................................................................26-6

26.2.3.1 SMC Function Code Registers (RFCR/TFCR) ..........................................26-8

26.2.4 Disabling SMCs On-the-Fly...........................................................................26-9

26.2.4.1 SMC Transmitter Full Sequence ................................................................26-9

26.2.4.2 SMC Transmitter Shortcut Sequence .........................................................26-9

26.2.4.3 SMC Receiver Full Sequence.....................................................................26-9

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Number

Title

Page

Number

26.2.4.4 SMC Receiver Shortcut Sequence ...........................................................26-10

26.2.4.5 Switching Protocols .................................................................................26-10

26.2.5 Saving Power ...............................................................................................26-10

26.2.6 Handling Interrupts in the SMC...................................................................26-10

26.3 SMC in UART Mode ....................................................................................... 26-10

26.3.1 Features ........................................................................................................26-11

26.3.2 SMC UART Channel Transmission Process ...............................................26-11

26.3.3 SMC UART Channel Reception Process..................................................... 26-12

26.3.4 Programming the SMC UART Controller ................................................... 26-12

26.3.5 SMC UART Transmit and Receive Commands .......................................... 26-12

26.3.6 Sending a Break ...........................................................................................26-13

26.3.7 Sending a Preamble...................................................................................... 26-13

26.3.8 Handling Errors in the SMC UART Controller ........................................... 26-13

26.3.9 SMC UART RxBD ......................................................................................26-14

26.3.10 SMC UART TxBD ......................................................................................26-16

26.3.11 SMC UART Event Register (SMCE)/Mask Register (SMCM) ..................26-18

26.3.12 SMC UART Controller Programming Example.......................................... 26-19

26.4 SMC in Transparent Mode...............................................................................26-20

26.4.1 Features ........................................................................................................26-21

26.4.2 SMC Transparent Channel Transmission Process ....................................... 26-21

26.4.3 SMC Transparent Channel Reception Process ............................................26-22

26.4.4 Using SMSYN for Synchronization.............................................................26-22

26.4.5 Using the Time-Slot Assigner (TSA) for Synchronization..........................26-23

26.4.6 SMC Transparent Commands ...................................................................... 26-25

26.4.7 Handling Errors in the SMC Transparent Controller...................................26-25

26.4.8 SMC Transparent RxBD .............................................................................. 26-26

26.4.9 SMC Transparent TxBD ..............................................................................26-27

26.4.10 SMC Transparent Event Register (SMCE)/Mask Register (SMCM) .......... 26-28

26.4.11 SMC Transparent NMSI Programming Example ........................................ 26-29

26.5 The SMC in GCI Mode....................................................................................26-30

26.5.1 SMC GCI Parameter RAM .......................................................................... 26-30

26.5.2 Handling the GCI Monitor Channel............................................................. 26-31

26.5.2.1 SMC GCI Monitor Channel Transmission Process .................................26-31

26.5.2.2 SMC GCI Monitor Channel Reception Process ...................................... 26-31

26.5.3 Handling the GCI C/I Channel..................................................................... 26-31

26.5.3.1 SMC GCI C/I Channel Transmission Process .........................................26-31

26.5.3.2 SMC GCI C/I Channel Reception Process .............................................. 26-31

26.5.4 SMC GCI Commands ..................................................................................26-32

26.5.5 SMC GCI Monitor Channel RxBD.............................................................. 26-32

26.5.6 SMC GCI Monitor Channel TxBD .............................................................. 26-32

26.5.7 SMC GCI C/I Channel RxBD...................................................................... 26-33

26.5.8 SMC GCI C/I Channel TxBD ...................................................................... 26-33

26.5.9 SMC GCI Event Register (SMCE)/Mask Register (SMCM) ......................26-34

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Title

Chapter 27

Page

Number

Multi-Channel Controllers (MCCs)

27.1 Features...............................................................................................................27-1

27.2 MCC Data Structure Organization .....................................................................27-2

27.3 Global MCC Parameters.....................................................................................27-3

27.4 Channel Extra Parameters ..................................................................................27-5

27.5 Super-Channel Table ..........................................................................................27-5

27.6 Channel-Specific HDLC Parameters..................................................................27-8

27.6.1 Internal Transmitter State (TSTATE) ............................................................27-9

27.6.2 Interrupt Mask (INTMSK) .............................................................................27-9

27.6.3 Channel Mode Register (CHAMR)..............................................................27-10

27.6.4 Internal Receiver State (RSTATE)...............................................................27-11

27.7 Channel-Specific Transparent Parameters........................................................27-12

27.7.1 Channel Mode Register (CHAMR)ÑTransparent Mode ............................27-13

27.8 MCC Configuration Registers (MCCFx) .........................................................27-15

27.9 MCC Commands ..............................................................................................27-16

27.10 MCC Exceptions...............................................................................................27-17

27.10.1 MCC Event Register (MCCE)/Mask Register (MCCM) .............................27-18

27.10.1.1 Interrupt Table Entry ................................................................................27-19

27.11 MCC Buffer Descriptors ..................................................................................27-21

27.11.1 Receive Buffer Descriptor (RxBD) ..............................................................27-21

27.11.2 Transmit Buffer Descriptor (TxBD).............................................................27-23

27.12 MCC Initialization and Start/Stop Sequence....................................................27-24

27.12.1 Single-Channel Initialization........................................................................27-25

27.12.2 Super Channel Initialization .........................................................................27-26

27.13 MCC Latency and Performance .......................................................................27-26

Chapter 28

Fast Communications Controllers (FCCs)

28.1 Overview ............................................................................................................28-2

28.2 General FCC Mode Registers (GFMRx)............................................................28-3

28.3 FCC Protocol-Specific Mode Registers (FPSMRx)...........................................28-7

28.4 FCC Data Synchronization Registers (FDSRx) .................................................28-7

28.5 FCC Transmit-on-Demand Registers (FTODRx) ..............................................28-7

28.6 FCC Buffer Descriptors......................................................................................28-8

28.7 FCC Parameter RAM .......................................................................................28-10

28.7.1 FCC Function Code Registers (FCRx).........................................................28-13

28.8 Interrupts from the FCCs..................................................................................28-13

28.8.1 FCC Event Registers (FCCEx).....................................................................28-14

28.8.2 FCC Mask Registers (FCCMx) ....................................................................28-14

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Number

28.8.3 FCC Status Registers (FCCSx) .................................................................... 28-14

28.9 FCC Initialization.............................................................................................28-14

28.10 FCC Interrupt Handling ...................................................................................28-15

28.11 FCC Timing Control ........................................................................................28-15

28.12 Disabling the FCCs On-the-Fly........................................................................28-19

28.12.1 FCC Transmitter Full Sequence................................................................... 28-20

28.12.2 FCC Transmitter Shortcut Sequence............................................................ 28-20

28.12.3 FCC Receiver Full Sequence .......................................................................28-20

28.12.4 FCC Receiver Shortcut Sequence ................................................................ 28-21

28.12.5 Switching Protocols .....................................................................................28-21

28.13 Saving Power....................................................................................................28-21

Title

Chapter 29

Page

Number

ATM Controller

29.1 Features ..............................................................................................................29-2

29.2 ATM Controller Overview................................................................................. 29-4

29.2.1 Transmitter Overview ....................................................................................29-5

29.2.1.1 AAL5 Transmitter Overview .....................................................................29-5

29.2.1.2 AAL1 Transmitter Overview .....................................................................29-5

29.2.1.3 AAL0 Transmitter Overview .....................................................................29-6

29.2.1.4 Transmit External Rate and Internal Rate Modes ...................................... 29-6

29.2.2 Receiver Overview......................................................................................... 29-6

29.2.2.1 AAL5 Receiver Overview ......................................................................... 29-7

29.2.2.2 AAL1 Receiver Overview ......................................................................... 29-7

29.2.2.3 AAL0 Receiver Overview ......................................................................... 29-8

29.2.3 Performance Monitoring ................................................................................ 29-8

29.2.4 ABR Flow Control ......................................................................................... 29-8

29.3 ATM Pace Control (APC) Unit.......................................................................... 29-8

29.3.1 APC Modes and ATM Service Types............................................................ 29-8

29.3.2 APC Unit Scheduling Mechanism .................................................................29-9

29.3.3 Determining the Scheduling Table Size....................................................... 29-10

29.3.3.1 Determining the Cells Per Slot (CPS) in a Scheduling Table .................. 29-10

29.3.3.2 Determining the Number of Slots in a Scheduling Table ........................29-11

29.3.4 Determining the Time-Slot Scheduling Rate of a Channel.......................... 29-11

29.3.5 ATM Traffic Type........................................................................................29-11

29.3.5.1 Peak Cell Rate Traffic Type..................................................................... 29-11

29.3.5.2 Determining the PCR Traffic Type Parameters ....................................... 29-11

29.3.5.3 Peak and Sustain Traffic Type (VBR) .....................................................29-12

29.3.5.3.1 Example for Using VBR Traffic Parameters .......................................29-12

29.3.5.3.2 Handling the Cell Loss Priority (CLP)ÑVBR Type 1 and 2 ..............29-13

29.3.5.4 Peak and Minimum Cell Rate Traffic Type (UBR+)...............................29-13

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Number

29.3.6 Determining the Priority of an ATM Channel .............................................29-13

29.4 VCI/VPI Address Lookup Mechanism.............................................................29-14

29.4.1 External CAM Lookup .................................................................................29-14

29.4.2 Address Compression...................................................................................29-15

29.4.2.1 VP-Level Address Compression Table (VPLT) ......................................29-17

29.4.2.2 VC-Level Address Compression Tables (VCLTs) ..................................29-18

29.4.3 Misinserted Cells ..........................................................................................29-18

29.4.4 Receive Raw Cell Queue..............................................................................29-19

29.5 Available Bit Rate (ABR) Flow Control ..........................................................29-20

29.5.1 The ABR Model ...........................................................................................29-20

29.5.1.1 ABR Flow Control Source End-System Behavior ...................................29-21

29.5.1.2 ABR Flow Control Destination End-System Behavior............................29-21

29.5.1.3 ABR Flowcharts .......................................................................................29-22

29.5.2 RM Cell Structure.........................................................................................29-25

29.5.2.1 RM Cell Rate Representation ...................................................................29-26

29.5.3 ABR Flow Control Setup .............................................................................29-27

29.6 OAM Support ...................................................................................................29-27

29.6.1 ATM-Layer OAM Definitions .....................................................................29-27

29.6.2 Virtual Path (F4) Flow Mechanism..............................................................29-28

29.6.3 Virtual Channel (F5) Flow Mechanism........................................................29-28

29.6.4 Receiving OAM F4 or F5 Cells....................................................................29-28

29.6.5 Transmitting OAM F4 or F5 Cells ...............................................................29-29

29.6.6 Performance Monitoring ..............................................................................29-29

29.6.6.1 Running a Performance Block Test..........................................................29-30

29.6.6.2 PM Block Monitoring ..............................................................................29-30

29.6.6.3 PM Block Generation ...............................................................................29-31

29.6.6.4 BRC Performance Calculations................................................................29-32

29.7 User-Defined Cells (UDC) ...............................................................................29-32

29.7.1 UDC Extended Address Mode (UEAD) ......................................................29-33

29.8 ATM Layer Statistics........................................................................................29-33

29.9 ATM-to-TDM Interworking.............................................................................29-34

29.9.1 Automatic Data Forwarding .........................................................................29-34

29.9.2 Using Interrupts in Automatic Data Forwarding..........................................29-35

29.9.3 Timing Issues................................................................................................29-36

29.9.4 Clock Synchronization (SRTS and Adaptive FIFOs) ..................................29-36

29.9.5 Mapping TDM Time Slots to VCs ...............................................................29-36

29.9.6 CAS Support.................................................................................................29-36

29.9.7 Trunk Condition ...........................................................................................29-37

29.9.8 ATM-to-ATM Data Forwarding ..................................................................29-37

29.10 ATM Memory Structure...................................................................................29-37

29.10.1 Parameter RAM............................................................................................29-37

29.10.1.1 Determining UEAD_OFFSET (UEAD Mode Only) ...............................29-40

29.10.1.2 VCI Filtering (VCIF)................................................................................29-40

Title

Page

Number

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29.10.1.3 Global Mode Entry (GMODE) ................................................................29-41

29.10.2 Connection Tables (RCT, TCT, and TCTE)................................................29-41

29.10.2.1 ATM Channel Code .................................................................................29-42

29.10.2.2 Receive Connection Table (RCT) ............................................................29-43

29.10.2.2.1 AAL5 Protocol-Specific RCT.............................................................. 29-46

29.10.2.2.2 AAL5-ABR Protocol-Specific RCT ....................................................29-47

29.10.2.2.3 AAL1 Protocol-Specific RCT.............................................................. 29-48

29.10.2.2.4 AAL0 Protocol-Specific RCT.............................................................. 29-50

29.10.2.3 Transmit Connection Table (TCT) .......................................................... 29-51

29.10.2.3.1 AAL5 Protocol-Specific TCT .............................................................. 29-54

29.10.2.3.2 AAL1 Protocol-Specific TCT .............................................................. 29-54

29.10.2.3.3 AAL0 Protocol-Specific TCT .............................................................. 29-55

29.10.2.3.4 VBR Protocol-Specific TCTE .............................................................29-56

29.10.2.3.5 UBR+ Protocol-Specific TCTE ...........................................................29-57

29.10.2.3.6 ABR Protocol-Specific TCTE .............................................................29-58

29.10.3 OAM Performance Monitoring Tables ........................................................ 29-60

29.10.4 APC Data Structure...................................................................................... 29-61

29.10.4.1 APC Parameter Tables .............................................................................29-62

29.10.4.2 APC Priority Table................................................................................... 29-63

29.10.4.3 APC Scheduling Tables ...........................................................................29-63

29.10.5 ATM Controller Buffer Descriptors (BDs)..................................................29-64

29.10.5.1 Transmit Buffer Operations .....................................................................29-64

29.10.5.2 Receive Buffers Operation ....................................................................... 29-65

29.10.5.2.1 Static Buffer Allocation .......................................................................29-65

29.10.5.2.2 Global Buffer Allocation .....................................................................29-66

29.10.5.2.3 Free Buffer Pools .................................................................................29-67

29.10.5.2.4 Free Buffer Pool Parameter Tables ...................................................... 29-68

29.10.5.3 ATM Controller Buffers ..........................................................................29-69

29.10.5.4 AAL5 RxBD ............................................................................................29-69

29.10.5.5 AAL1 RxBD ............................................................................................29-71

29.10.5.6 AAL0 RxBD ............................................................................................29-72

29.10.5.7 AAL5, AAL1 User-Defined CellÑRxBD Extension.............................. 29-73

29.10.5.8 AAL5 TxBDs ........................................................................................... 29-74

29.10.5.9 AAL1 TxBDs ........................................................................................... 29-76

29.10.5.10 AAL0 TxBDs ........................................................................................... 29-77

29.10.5.11 AAL5, AAL1 User-Defined CellÑTxBD Extension .............................. 29-78

29.10.6 AAL1 Sequence Number (SN) Protection Table (AAL1 Only)..................29-78

29.10.7 UNI Statistics Table ..................................................................................... 29-78

29.11 ATM Exceptions ..............................................................................................29-79

29.11.1 Interrupt Queues........................................................................................... 29-79

29.11.2 Interrupt Queue Entry ..................................................................................29-80

29.11.3 Interrupt Queue Parameter Tables ...............................................................29-81

29.12 The UTOPIA Interface..................................................................................... 29-82

Title

Page

Number

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Paragraph
Number

29.12.1 UTOPIA Interface Master Mode..................................................................29-82

29.12.1.1 UTOPIA Master Multiple PHY Operation ..............................................29-83

29.12.2 UTOPIA Interface Slave Mode ....................................................................29-83

29.12.2.1 UTOPIA Slave Multiple PHY Operation.................................................29-84

29.12.2.2 UTOPIA Clocking Modes........................................................................29-84

29.12.2.3 UTOPIA Loop-Back Modes ....................................................................29-85

29.13 ATM Registers .................................................................................................29-85

29.13.1 General FCC Mode Register (GFMR) .........................................................29-85

29.13.2 FCC Protocol-Specific Mode Register (FPSMR) ........................................29-85

29.13.3 ATM Event Register (FCCE)/Mask Register (FCCM)................................29-87

29.13.4 FCC Transmit Internal Rate Registers (FTIRRx) ........................................29-88

29.14 ATM Transmit Command ................................................................................29-90

29.15 SRTS Generation and Clock Recovery Using External Logic.........................29-91

29.16 Configuring the ATM Controller for Maximum CPM Performance ...............29-92

29.16.1 Using Transmit Internal Rate Mode .............................................................29-92

29.16.2 APC Configuration.......................................................................................29-93

29.16.3 Buffer Configuration ....................................................................................29-93

Title

Chapter 30

Page

Number

Fast Ethernet Controller

30.1 Fast Ethernet on the MPC8260...........................................................................30-2

30.2 Features...............................................................................................................30-3

30.3 Connecting the MPC8260 to Fast Ethernet ........................................................30-4

30.4 Ethernet Channel Frame Transmission...............................................................30-5

30.5 Ethernet Channel Frame Reception....................................................................30-7

30.6 Flow Control.......................................................................................................30-8

30.7 CAM Interface....................................................................................................30-8

30.8 Ethernet Parameter RAM ...................................................................................30-9

30.9 Programming Model.........................................................................................30-12

30.10 Ethernet Command Set.....................................................................................30-12

30.11 RMON Support.................................................................................................30-14

30.12 Ethernet Address Recognition ..........................................................................30-15

30.13 Hash Table Algorithm ......................................................................................30-17

30.14 Interpacket Gap Time .......................................................................................30-18

30.15 Handling Collisions ..........................................................................................30-18

30.16 Internal and External Loopback .......................................................................30-18

30.17 Ethernet Error-Handling Procedure..................................................................30-19

30.18 Fast Ethernet Registers .....................................................................................30-19

30.18.1 FCC Ethernet Mode Register (FPSMR).......................................................30-20

30.18.2 Ethernet Event Register (FCCE)/Mask Register (FCCM) ...........................30-21

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Paragraph
Number

30.19 Ethernet RxBDs................................................................................................30-23

30.20 Ethernet TxBDs................................................................................................ 30-26

Title

Chapter 31

Page

Number

FCC HDLC Controller

31.1 Key Features....................................................................................................... 31-2

31.2 HDLC Channel Frame Transmission Processing...............................................31-2

31.3 HDLC Channel Frame Reception Processing....................................................31-3

31.4 HDLC Parameter RAM...................................................................................... 31-4

31.5 Programming Model ..........................................................................................31-5

31.5.1 HDLC Command Set ..................................................................................... 31-5

31.5.2 HDLC Error Handling....................................................................................31-6

31.6 HDLC Mode Register (FPSMR)........................................................................ 31-7

31.7 HDLC Receive Buffer Descriptor (RxBD)........................................................31-9

31.8 HDLC Transmit Buffer Descriptor (TxBD).....................................................31-12

31.9 HDLC Event Register (FCCE)/Mask Register (FCCM)..................................31-14

31.10 FCC Status Register (FCCS)............................................................................ 31-16

Chapter 32

FCC Transparent Controller

32.1 Features ..............................................................................................................32-2

32.2 Transparent Channel Operation .........................................................................32-2

32.3 Achieving Synchronization in Transparent Mode .............................................32-2

32.3.1 In-Line Synchronization Pattern ....................................................................32-3

32.3.2 External Synchronization Signals ..................................................................32-3

32.3.3 Transparent Synchronization Example ..........................................................32-4

Chapter 33

Serial Peripheral Interface (SPI)

33.1 Features ..............................................................................................................33-2

33.2 SPI Clocking and Signal Functions....................................................................33-2

33.3 Configuring the SPI Controller ..........................................................................33-3

33.3.1 The SPI as a Master Device ...........................................................................33-3

33.3.2 The SPI as a Slave Device .............................................................................33-4

33.3.3 The SPI in Multimaster Operation ................................................................. 33-4

33.4 Programming the SPI Registers .........................................................................33-6

33.4.1 SPI Mode Register (SPMODE) .....................................................................33-6

33.4.1.1 SPI Examples with Different SPMODE[LEN] Values.............................. 33-8

33.4.2 SPI Event/Mask Registers (SPIE/SPIM) .......................................................33-9

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Number

33.4.3 SPI Command Register (SPCOM) .................................................................33-9

33.5 SPI Parameter RAM .........................................................................................33-10

33.5.1 Receive/Transmit Function Code Registers (RFCR/TFCR) ........................33-12

33.6 SPI Commands .................................................................................................33-12

33.7 The SPI Buffer Descriptor (BD) Table.............................................................33-13

33.7.1 SPI Buffer Descriptors (BDs).......................................................................33-13

33.7.1.1 SPI Receive BD (RxBD) ..........................................................................33-14

33.7.1.2 SPI Transmit BD (TxBD).........................................................................33-15

33.8 SPI Master Programming Example ..................................................................33-16

33.9 SPI Slave Programming Example ....................................................................33-17

33.10 Handling Interrupts in the SPI ..........................................................................33-18

Chapter 34

2

I

C Controller

34.1 Features...............................................................................................................34-2

34.2 I

34.3 I

34.3.1 I

34.3.2 I

34.3.3 I

34.3.4 I

34.4 I

34.4.1 I

34.4.2 I

34.4.3 I

34.4.4 I

34.4.5 I

34.5 I

34.6 I

34.7 The I

34.7.1 I

34.7.1.1 I

34.7.1.2 I

2

C Controller Clocking and Signal Functions...................................................34-2

2

C Controller Transfers.....................................................................................34-3

2

C Master Write (Slave Read) ......................................................................34-4

2

C Loopback Testing ....................................................................................34-4

2

C Master Read (Slave Write) ......................................................................34-4

2

C Multi-Master Considerations ...................................................................34-5

2

C Registers.......................................................................................................34-6

2

C Mode Register (I2MOD) .........................................................................34-6

2

C Address Register (I2ADD) ......................................................................34-7

2

C Baud Rate Generator Register (I2BRG) ..................................................34-7

2

C Event/Mask Registers (I2CER/I2CMR) ..................................................34-8

2

C Command Register (I2COM) ..................................................................34-8

2

C Parameter RAM ...........................................................................................34-9

2

C Commands .................................................................................................34-11

2

C Buffer Descriptor (BD) Table.............................................................34-12

2

C Buffer Descriptors (BDs).......................................................................34-12

2

C Receive Buffer Descriptor (RxBD) ...................................................34-13

2

C Transmit Buffer Descriptor (TxBD)..................................................34-14

Chapter 35

Parallel I/O Ports

35.1 Features...............................................................................................................35-1

35.2 Port Registers......................................................................................................35-2

35.2.1 Port Open-Drain Registers (PODRAÐPODRD).............................................35-2

35.2.2 Port Data Registers (PDATAÐPDATD).........................................................35-2

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35.2.3 Port Data Direction Registers (PDIRAÐPDIRD)...........................................35-3

35.2.4 Port Pin Assignment Register (PPAR)........................................................... 35-4

35.2.5 Port Special Options Registers AÐD (PSORAÐPSORD)...............................35-4

35.3 Port Block Diagram............................................................................................ 35-6

35.4 Port Pins Functions ............................................................................................35-6

35.4.1 General Purpose I/O Pins ............................................................................... 35-7

35.4.2 Dedicated Pins................................................................................................ 35-7

35.5 Ports Tables........................................................................................................35-7

35.6 Interrupts from Port C ......................................................................................35-19

Title

Appendix A

Page

Number

Register Quick Reference Guide

A.1 PowerPC RegistersÑUser Registers ..................................................................A-1

A.2 PowerPC RegistersÑSupervisor Registers......................................................... A-2

A.3 MPC8260-Specific SPRs ....................................................................................A-3

Glossary

Index

MOTOROLA Contents xxxi

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Number

Title

Page

Number

xxxii MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

ILLUSTRATIONS

Figure
Number

1-1 MPC8260 Block Diagram ......................................................................................... 1-5

1-2 MPC8260 External Signals........................................................................................ 1-8

1-3 Remote Access Server Configuration...................................................................... 1-11

1-4 Regional Office Router Configuration .................................................................... 1-12

1-5 LAN-to-WAN Bridge Router Configuration........................................................... 1-13

1-6 Cellular Base Station Configuration........................................................................ 1-14

1-7 Telecommunications Switch Controller Configuration........................................... 1-14

1-8 SONET Transmission Controller Configuration ..................................................... 1-15

1-9 Basic System Configuration ....................................................................................1-16

1-10 High-Performance Communication......................................................................... 1-16

1-11 High-Performance System Microprocessor Configuration .....................................1-17

2-1 MPC8260 Integrated Processor Core Block Diagram............................................... 2-2

2-2 MPC8260 Programming ModelÑRegisters............................................................ 2-10

2-3 Hardware Implementation Register 0 (HID0) ......................................................... 2-11

2-4 Hardware Implementation Register 1 (HID1) ......................................................... 2-15

2-5 Hardware Implementation-Dependent Register 2 (HID2) ...................................... 2-15

2-6 Data Cache Organization......................................................................................... 2-20

4-1 .SIU Block Diagram .................................................................................................. 4-1

4-2 System Configuration and Protection Logic.............................................................. 4-3

4-3 Timers Clock Generation........................................................................................... 4-4

4-4 TMCNT Block Diagram............................................................................................ 4-5

4-5 PIT Block Diagram.................................................................................................... 4-5

4-6 Software Watchdog Timer Service State Diagram.................................................... 4-6

4-7 Software Watchdog Timer Block Diagram ............................................................... 4-7

4-8 MPC8260 Interrupt Structure ....................................................................................4-8

4-9 Interrupt Request Masking ...................................................................................... 4-14

4-10 SIU Interrupt Configuration Register (SICR).......................................................... 4-17

4-11 SIU Interrupt Priority Register (SIPRR).................................................................. 4-18

4-12 CPM High Interrupt Priority Register (SCPRR_H) ................................................ 4-19

4-13 CPM Low Interrupt Priority Register (SCPRR_L) ................................................. 4-20

4-14 SIPNR_H Fields ...................................................................................................... 4-21

4-15 SIPNR_L Fields....................................................................................................... 4-21

4-16 SIMR_H Register .................................................................................................... 4-22

4-17 SIMR_L Register..................................................................................................... 4-23

4-18 SIU Interrupt Vector Register (SIVEC) .................................................................. 4-23

4-19 Interrupt Table Handling Example .......................................................................... 4-24

Title

Page

Number

MOTOROLA Illustrations xxxiii

ILLUSTRATIONS

Figure
Number

4-20 SIU External Interrupt Control Register (SIEXR)................................................... 4-25

4-21 Bus Configuration Register (BCR).......................................................................... 4-26

4-22 PPC_ACR ................................................................................................................ 4-28

4-23 PPC_ALRH ............................................................................................................. 4-29

4-24 PPC_AALRL........................................................................................................... 4-29

4-25 LCL_ACR................................................................................................................ 4-29

4-26 LCL_ALRH............................................................................................................. 4-30

4-27 LCL_ALRL ............................................................................................................. 4-31

4-28 SIU Model Configuration Register (SIUMCR)....................................................... 4-31

4-29 Internal Memory Map Register (IMMR)................................................................. 4-34

4-30 System Protection Control Register (SYPCCR)...................................................... 4-35

4-31 The 60x Bus Transfer Error Status and Control Register 1 (TESCR1)................... 4-36

4-32 60x Bus Transfer Error Status and Control Register 2 (TESCR2).......................... 4-37

4-33 Local Bus Transfer Error Status and Control Register 1 (L_TESCR1) .................. 4-38

4-34 Local Bus Transfer Error Status and Control Register 2 (L_TESCR2) .................. 4-39

4-35 Time Counter Status and Control Register (TMCNTSC) ....................................... 4-40

4-36 Time Counter Register (TCMCNT) ........................................................................ 4-41

4-37 Time Counter Alarm Register (TMCNTAL) .......................................................... 4-42

4-38 Periodic Interrupt Status and Control Register (PISCR) ......................................... 4-42

4-39 Periodic interrupt Timer Count Register (PITC) ..................................................... 4-43

4-40 Periodic Interrupt Timer Register (PITR)................................................................ 4-44

5-1 Reset Status Register (RSR) ...................................................................................... 5-4

5-2 Reset Mode Register (RMR) .....................................................................................5-5

5-3 Hard Reset Configuration Word................................................................................ 5-8

5-4 Single Chip with Default Configuration.................................................................. 5-10

5-5 Configuring a Single Chip from EPROM ............................................................... 5-10

5-6 Configuring Multiple Chips..................................................................................... 5-11

6-1 MPC8260 External Signals........................................................................................ 6-2

7-1 PowerPC Signal Groupings ....................................................................................... 7-2

8-1 Single MPC8260 Bus Mode ...................................................................................... 8-3

8-2 60x-Compatible Bus Mode........................................................................................ 8-4

8-3 Basic Transfer Protocol ............................................................................................. 8-5

8-4 Address Bus Arbitration with External Bus Master ..................................................8-9

8-5 Address Pipelining................................................................................................... 8-10

8-6 Interface to Different Port Size Devices.................................................................. 8-17

8-7 Retry Cycle .............................................................................................................. 8-24

8-8 Single-Beat and Burst Data Transfers ..................................................................... 8-28

8-9 128-Bit Extended Transfer to 32-Bit Port Size........................................................ 8-29

8-10 Burst Transfer to 32-Bit Port Size ...........................................................................8-30

8-11 Data Tenure Terminated by Assertion of TEA........................................................ 8-31

8-12 MEI Cache Coherency ProtocolÑState Diagram (WIM = 001)............................. 8-32

9-1 System PLL Block Diagram...................................................................................... 9-5

9-2 PLL Filtering Circuit ................................................................................................. 9-8

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9-3 System Clock Control Register (SCCR).................................................................... 9-8

9-4 System Clock Mode Register (SCMR)...................................................................... 9-9

9-5 Relationships of SCMR Parameters ........................................................................ 9-10

10-1 Dual-Bus Architecture ............................................................................................. 10-3

10-2 Memory Controller Machine Selection ...................................................................10-6

10-3 Simple System Configuration.................................................................................. 10-7

10-4 Basic Memory Controller Operation .......................................................................10-8

10-5 Partial Data Valid for 32-Bit Port Size Memory, Double-Word Transfer ............ 10-13

10-6 Base Registers (BRx) ............................................................................................ 10-14

10-7 Option Registers (ORx)ÑSDRAM Mode ............................................................ 10-16

10-8 ORx ÑGPCM Mode............................................................................................. 10-18

10-9 ORxÑUPM Mode................................................................................................. 10-20

10-10 60x/Local SDRAM Mode Register (PSDMR/LSDMR) ....................................... 10-21

10-11 Machine x Mode Registers (MxMR)..................................................................... 10-26

10-12 Memory Data Register (MDR).............................................................................. 10-29

10-13 Memory Address Register (MAR) ........................................................................ 10-29

10-14 60x Bus-Assigned UPM Refresh Timer (PURT) .................................................. 10-30

10-15 Local Bus-Assigned UPM Refresh Timer (LURT)............................................... 10-30

10-16 60x Bus-Assigned SDRAM Refresh Timer (PSRT) .............................................10-31

10-17 Local Bus-Assigned SDRAM Refresh Timer (LSRT).......................................... 10-32

10-18 Memory Refresh Timer Prescaler Register (MPTPR)........................................... 10-32

10-19 128-Mbyte SDRAM (Eight-Bank Configuration, Banks 1 and 8 Shown)............ 10-34

10-20 PRETOACT = 2 (2 Clock Cycles) ........................................................................ 10-39

10-21 ACTTORW = 2 (2 Clock Cycles) ......................................................................... 10-39

10-22 CL = 2 (2 Clock Cycles)........................................................................................ 10-40

10-23 LDOTOPRE = 2 (-2 Clock Cycles)....................................................................... 10-40

10-24 WRC = 2 (2 Clock Cycles).................................................................................... 10-41

10-25 RFRC = 4 (6 Clock Cycles)................................................................................... 10-41

10-26 EAMUX = 1 .......................................................................................................... 10-42

10-27 BUFCMD = 1 ........................................................................................................ 10-42

10-28 SDRAM Single-Beat Read, Page Closed, CL = 3................................................. 10-43

10-29 SDRAM Single-Beat Read, Page Hit, CL = 3....................................................... 10-43

10-30 SDRAM Two-Beat Burst Read, Page Closed, CL = 3 .......................................... 10-43

10-31 SDRAM Four-Beat Burst Read, Page Miss, CL = 3 ............................................. 10-44

10-32 SDRAM Single-Beat Write, Page Hit ...................................................................10-44

10-33 SDRAM Three-Beat Burst Write, Page Closed .................................................... 10-44

10-34 SDRAM Read-after-Read Pipeline, Page Hit, CL = 3 .......................................... 10-45

10-35 SDRAM Write-after-Write Pipelined, Page Hit.................................................... 10-45

10-36 SDRAM Read-after-Write Pipelined, Page Hit..................................................... 10-45

10-37 SDRAM Mode-Set Command Timing.................................................................. 10-46

10-38 Mode Data Bit Settings.......................................................................................... 10-47

10-39 SDRAM Bank-Staggered CBR Refresh Timing ................................................... 10-48

10-40 GPCM-to-SRAM ConÞguration............................................................................ 10-52

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10-41 GPCM Peripheral Device Interface ....................................................................... 10-53

10-42 GPCM Peripheral Device Basic Timing (ACS = 1x and TRLX = 0) ................... 10-53

10-43 GPCM Memory Device Interface.......................................................................... 10-54

10-44 GPCM Memory Device Basic Timing (ACS = 00, CSNT = 1, TRLX = 0) ......... 10-54

10-45 GPCM Memory Device Basic Timing (ACS ¹ 00, CSNT = 1, TRLX = 0) ......... 10-55

10-46 GPCM Relaxed Timing Read (ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1) ....... 10-55

10-47 GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 0,TRLX = 1)....... 10-56

10-48 GPCM Relaxed-Timing Write (ACS = 10, SCY = 0, CSNT = 1, TRLX = 1)...... 10-56

10-49 GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1)...... 10-57

10-50 GPCM Read Followed by Read (ORx[29Ð30] = 0x, Fastest Timing) .................. 10-58

10-51 GPCM Read Followed by Read (ORx[29Ð30] = 01) ............................................ 10-59

10-52 GPCM Read Followed by Write (ORx[29Ð30] = 01) ........................................... 10-59

10-53 GPCM Read Followed by Read (ORx[29Ð30] = 10) ............................................ 10-60

10-54 External Termination of GPCM Access ................................................................ 10-61

10-55 User-Programmable Machine Block Diagram ...................................................... 10-63

10-56 RAM Array Indexing............................................................................................. 10-64

10-57 Memory Refresh Timer Request Block Diagram.................................................. 10-66

10-58 Memory Controller UPM Clock Scheme for Integer Clock Ratios ...................... 10-67

10-59 Memory Controller UPM Clock Scheme for Non-Integer (2.5:1/3.5:1)

Clock Ratios ........................................................................................................ 10-68

10-60 UPM Signals Timing Example.............................................................................. 10-69

10-61 RAM Array and Signal Generation ....................................................................... 10-70

10-62 The RAM Word..................................................................................................... 10-70

10-63 CS Signal Selection ............................................................................................... 10-75

10-64 BS Signal Selection ............................................................................................... 10-75

10-65 UPM Read Access Data Sampling ........................................................................10-78

10-66 Wait Mechanism Timing for Internal and External Synchronous Masters ........... 10-79

10-67 DRAM Interface Connection to the 60x Bus (64-Bit Port Size) ........................... 10-82

10-68 Single-Beat Read Access to FPM DRAM............................................................. 10-83

10-69 Single-Beat Write Access to FPM DRAM............................................................ 10-84

10-70 Burst Read Access to FPM DRAM (No LOOP) ................................................... 10-85

10-71 Burst Read Access to FPM DRAM (LOOP)......................................................... 10-86

10-72 Burst Write Access to FPM DRAM (No LOOP) .................................................. 10-87

10-73 Refresh Cycle (CBR) to FPM DRAM................................................................... 10-88

10-74 Exception Cycle..................................................................................................... 10-89

10-75 FPM DRAM Burst Read Access (Data Sampling on Falling Edge of CLKIN) ... 10-91

10-76 MPC8260/EDO Interface Connection to the 60x Bus........................................... 10-92

10-77 Single-Beat Read Access to EDO DRAM............................................................. 10-93

10-78 Single-Beat Write Access to EDO DRAM............................................................ 10-94

10-79 Single-Beat Write Access to EDO DRAM Using REDO to Insert Three

Wait States........................................................................................................... 10-95

10-80 Burst Read Access to EDO DRAM....................................................................... 10-96

10-81 Burst Write Access to EDO DRAM...................................................................... 10-97

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10-82 Refresh Cycle (CBR) to EDO DRAM................................................................... 10-98

10-83 Exception Cycle For EDO DRAM ........................................................................ 10-99

10-84 Pipelined Bus Operation and Memory Access in 60x-Compatible Mode........... 10-103

10-85 External Master Access (GPCM) ........................................................................ 10-104

10-86 External Master Configuration with SDRAM Device......................................... 10-105

11-1 L2 Cache in Copy-Back Mode ................................................................................11-2

11-2 External L2 Cache in Write-Through Mode............................................................ 11-4

11-3 External L2 Cache in ECC/Parity Mode ................................................................. 11-6

11-4 Read Access with L2 Cache ....................................................................................11-9

12-1 Test Logic Block Diagram....................................................................................... 12-2

12-2 TAP Controller State Machine ................................................................................ 12-3

12-3 Output Pin Cell (O.Pin) ........................................................................................... 12-4

12-4 Observe-Only Input Pin Cell (I.Obs)....................................................................... 12-4

12-5 Output Control Cell (IO.CTL)................................................................................. 12-5

12-6 General Arrangement of Bidirectional Pin Cells..................................................... 12-5

13-1 MPC8260 CPM Block Diagram.............................................................................. 13-3

13-2 Communications Processor (CP) Block Diagram ................................................... 13-5

13-3 RISC Controller Configuration Register (RCCR)................................................... 13-8

13-4 RISC Time-Stamp Control Register (RTSCR)........................................................ 13-9

13-5 RISC Time-Stamp Register (RTSR) ..................................................................... 13-10

13-6 CP Command Register (CPCR)............................................................................. 13-11

13-7 Dual-Port RAM Block Diagram............................................................................ 13-15

13-8 Dual-Port RAM Memory Map .............................................................................. 13-16

13-9 RISC Timer Table RAM Usage ............................................................................ 13-19

13-10 RISC Timer Command Register (TM_CMD)....................................................... 13-20

13-11 TM_CMD Field Descriptions................................................................................ 13-21

13-12 RISC Timer Event Register (RTER)/Mask Register (RTMR).............................. 13-21

14-1 SI Block Diagram ....................................................................................................14-2

14-2 Various Configurations of a Single TDM Channel ................................................. 14-5

14-3 Dual TDM Channel Example .................................................................................. 14-6

14-4 Enabling Connections to the TSA ........................................................................... 14-8

14-5 One TDM Channel with Static Frames and Independent Rx and Tx Routes.......... 14-9

14-6 One TDM Channel with Shadow RAM for Dynamic Route Change ...................14-10

14-7 SIx RAM Entry Fields ........................................................................................... 14-10

14-8 Using the SWTR Feature....................................................................................... 14-12

14-9 Example: SIx RAM Dynamic Changes, TDMa and b, Same SIx RAM Size ....... 14-16

14-10 SI Global Mode Registers (SIxGMR) ................................................................... 14-17

14-11 SI Mode Registers (SIxMR) .................................................................................. 14-18

14-12 One-Clock Delay from Sync to Data (xFSD = 01)................................................ 14-20

14-13 No Delay from Sync to Data (xFSD = 00) ............................................................ 14-20

14-14 Falling Edge (FE) Effect When CE = 1 and xFSD = 01 ....................................... 14-21

14-15 Falling Edge (FE) Effect When CE = 0 and xFSD = 01 ....................................... 14-21

14-16 Falling Edge (FE) Effect When CE = 1 and xFSD = 00 ....................................... 14-22

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14-17 Falling Edge (FE) Effect When CE = 0 and xFSD = 00 ....................................... 14-23

14-18 SIx RAM Shadow Address Registers (SIxRSR) ................................................... 14-24

14-19 SI Command Register (SIxCMDR)....................................................................... 14-24

14-20 SI Status Registers (SIxSTR)................................................................................. 14-25

14-21 Dual IDL Bus Application Example...................................................................... 14-26

14-22 IDL Terminal Adaptor........................................................................................... 14-27

14-23 IDL Bus Signals..................................................................................................... 14-28

14-24 GCI Bus Signals .................................................................................................... 14-32

15-1 CPM Multiplexing Logic (CMX) Block Diagram .................................................. 15-2

15-2 Enabling Connections to the TSA ........................................................................... 15-4

15-3 Bank of Clocks ........................................................................................................ 15-5

15-4 CMX UTOPIA Address Register (CMXUAR)....................................................... 15-7

15-5 Connection of the Master Address .......................................................................... 15-8

15-6 Connection of the Slave Address............................................................................. 15-9

15-7 Multi-PHY Receive Address Multiplexing ...........................................................15-10

15-8 CMX SI1 Clock Route Register (CMXSI1CR)..................................................... 15-11

15-9 CMX SI2 Clock Route Register (CMXSI2CR)..................................................... 15-12

15-10 CMX FCC Clock Route Register (CMXFCR)...................................................... 15-13

15-11 CMX SCC Clock Route Register (CMXSCR)...................................................... 15-15

15-12 CMX SMC Clock Route Register (CMXSMR) .................................................... 15-18

16-1 Baud-Rate Generator (BRG) Block Diagram.......................................................... 16-1

16-2 Baud-Rate Generator Configuration Registers (BRGCx) ....................................... 16-2

17-1 Timer Block Diagram .............................................................................................. 17-1

17-2 Timer Cascaded Mode Block Diagram ................................................................... 17-4

17-3 Timer Global Configuration Register 1 (TGCR1)................................................... 17-4

17-4 Timer Global Configuration Register 2 (TGCR2)................................................... 17-5

17-5 Timer Mode Registers (TMR1ÐTMR4) .................................................................. 17-6

17-6 Timer Reference Registers (TRR1ÐTRR4) .............................................................17-7

17-7 Timer Capture Registers (TCR1ÐTCR4)................................................................. 17-8

17-8 Timer Counter Registers (TCN1ÐTCN4) ................................................................ 17-8

17-9 Timer Event Registers (TER1ÐTER4)..................................................................... 17-8

18-1 SDMA Data Paths.................................................................................................... 18-1

18-2 SDMA Bus Arbitration (Transaction Steal) ............................................................18-3

18-3 SDMA Status Register (SDSR) ............................................................................... 18-3

18-4 SDMA Transfer Error MSNUM Registers (PDTEM/LDTEM).............................. 18-4

18-5 IDMA Transfer Buffer in the Dual-Port RAM........................................................ 18-7

18-6 Example IDMA Transfer Buffer States for a Memory-to-Memory Transfer

(Size = 128 Bytes) ................................................................................................. 18-8

18-7 IDMAx ChannelÕs BD Table................................................................................. 18-15

18-8 DCM Parameters ................................................................................................... 18-18

18-9 IDMA Event/Mask Registers (IDSR/IDMR) ........................................................ 18-23

18-10 IDMA BD Structure .............................................................................................. 18-23

19-1 SCC Block Diagram ................................................................................................19-2

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19-2 GSMR_HÑGeneral SCC Mode Register (High Order) .........................................19-3

19-3 GSMR_LÑGeneral SCC Mode Register (Low Order) .......................................... 19-6

19-4 Data Synchronization Register (DSR)..................................................................... 19-9

19-5 Transmit-on-Demand Register (TODR).................................................................. 19-9

19-6 SCC Buffer Descriptors (BDs) .............................................................................. 19-11

19-7 SCC BD and Buffer Memory Structure................................................................. 19-12

19-8 Function Code Registers (RFCR and TFCR) ........................................................ 19-15

19-9 Output Delay from RTS Asserted for Synchronous Protocols.............................. 19-18

19-10 Output Delay from CTS Asserted for Synchronous Protocols.............................. 19-19

19-11 CTS Lost in Synchronous Protocols...................................................................... 19-20

19-12 Using CD to Control Synchronous Protocol Reception ........................................19-21

19-13 DPLL Receiver Block Diagram............................................................................. 19-22

19-14 DPLL Transmitter Block Diagram ........................................................................ 19-23

19-15 DPLL Encoding Examples ....................................................................................19-25

20-1 UART Character Format ......................................................................................... 20-1

20-2 Two UART Multidrop Configurations.................................................................... 20-8

20-3 Control Character Table .......................................................................................... 20-9

20-4 Transmit Out-of-Sequence Register (TOSEQ)...................................................... 20-10

20-5 Asynchronous UART Transmitter......................................................................... 20-11

20-6 Protocol-Specific Mode Register for UART (PSMR)........................................... 20-14

20-7 SCC UART Receiving using RxBDs ....................................................................20-16

20-8 SCC UART Receive Buffer Descriptor (RxBD)................................................... 20-17

20-9 SCC UART Transmit Buffer Descriptor (TxBD) ................................................. 20-18

20-10 SCC UART Interrupt Event Example ................................................................... 20-20

20-11 SCC UART Event Register (SCCE) and Mask Register (SCCM)........................ 20-20

20-12 SCC Status Register for UART Mode (SCCS) ..................................................... 20-21

21-1 HDLC Framing Structure ........................................................................................21-2

21-2 HDLC Address Recognition.................................................................................... 21-5

21-3 HDLC Mode Register (PSMR) ............................................................................... 21-7

21-4 SCC HDLC Receive Buffer Descriptor (RxBD)..................................................... 21-8

21-5 SCC HDLC Receiving Using RxBDs ................................................................... 21-10

21-6 SCC HDLC Transmit Buffer Descriptor (TxBD) ................................................. 21-11

21-7 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) ........................... 21-12

21-8 SCC HDLC Interrupt Event Example ................................................................... 21-13

21-9 SCC HDLC Status Register (SCCS) ..................................................................... 21-14

21-10 Typical HDLC Bus Multimaster Configuration .................................................... 21-18

21-11 Typical HDLC Bus Single-Master Configuration................................................. 21-19

21-12 Detecting an HDLC Bus Collision ........................................................................21-20

21-13 Nonsymmetrical Tx Clock Duty Cycle for Increased Performance...................... 21-21

21-14 HDLC Bus Transmission Line Configuration....................................................... 21-21

21-15 Delayed RTS Mode ............................................................................................... 21-22

21-16 HDLC Bus TDM Transmission Line Configuration ............................................. 21-22

22-1 Classes of BISYNC Frames..................................................................................... 22-1

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22-2 Control Character Table and RCCM ....................................................................... 22-6

22-3 BISYNC SYNC (BSYNC) ...................................................................................... 22-7

22-4 BISYNC DLE (BDLE)............................................................................................ 22-8

22-5 Protocol-Specific Mode Register for BISYNC (PSMR) ....................................... 22-10

22-6 SCC BISYNC RxBD............................................................................................. 22-12

22-7 SCC BISYNC Transmit BD (TxBD) .................................................................... 22-14

22-8 BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM).................... 22-15

22-9 SCC Status Registers (SCCS)................................................................................ 22-16

23-1 Sending Transparent Frames between MPC8260s .................................................. 23-5

23-2 SCC Transparent Receive Buffer Descriptor (RxBD)............................................. 23-9

23-3 SCC Transparent Transmit Buffer Descriptor (TxBD) .........................................23-11

23-4 SCC Transparent Event Register (SCCE)/Mask Register (SCCM) ......................23-12

23-5 SCC Status Register in Transparent Mode (SCCS)............................................... 23-13

24-1 Ethernet Frame Structure......................................................................................... 24-1

24-2 Ethernet Block Diagram ..........................................................................................24-2

24-3 Connecting the MPC8260 to Ethernet..................................................................... 24-5

24-4 Ethernet Address Recognition Flowchart.............................................................. 24-12

24-5 Ethernet Mode Register (PSMR)........................................................................... 24-15

24-6 SCC Ethernet Receive RxBD ................................................................................ 24-17

24-7 Ethernet Receiving using RxBDs .......................................................................... 24-19

24-8 SCC Ethernet TxBD ..............................................................................................24-20

24-9 SCC Ethernet Event Register (SCCE)/Mask Register (SCCM)............................ 24-21

24-10 Ethernet Interrupt Events Example........................................................................ 24-22

25-1 LocalTalk Frame Format ......................................................................................... 25-1

25-2 Connecting the MPC8260 to LocalTalk .................................................................. 25-3

26-1 SMC Block Diagram ............................................................................................... 26-2

26-2 SMC Mode Registers (SMCMR1/SMCMR2)......................................................... 26-3

26-3 SMC Memory Structure .......................................................................................... 26-5

26-4 SMC Function Code Registers (RFCR/TFCR) ....................................................... 26-8

26-5 SMC UART Frame Format ...................................................................................26-11

26-6 SMC UART RxBD................................................................................................ 26-14

26-7 RxBD Example...................................................................................................... 26-16

26-8 SMC UART TxBD ................................................................................................ 26-17

26-9 SMC UART Event Register (SMCE)/Mask Register (SMCM)............................ 26-18

26-10 SMC UART Interrupts Example ...........................................................................26-19

26-11 Synchronization with SMSYNx.................................................................... 26-23

26-12 Synchronization with the TSA............................................................................... 26-24

26-13 SMC Transparent RxBD........................................................................................ 26-26

26-14 SMC Transparent Event Register (SMCE)/Mask Register (SMCM).................... 26-28

26-15 SMC Monitor Channel RxBD ...............................................................................26-32

26-16 SMC Monitor Channel TxBD ............................................................................... 26-32

26-17 SMC C/I Channel RxBD .......................................................................................26-33

26-18 SMC C/I Channel TxBD ....................................................................................... 26-33

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26-19 SMC GCI Event Register (SMCE)/Mask Register (SMCM)................................ 26-34

27-1 BD Structure for One MCC..................................................................................... 27-3

27-2 Super Channel Table Entry...................................................................................... 27-5

27-3 Transmitter Super Channel Example....................................................................... 27-6

27-4 Receiver Super Channel with Slot Synchronization Example ................................ 27-7

27-5 Receiver Super Channel without Slot Synchronization Example ........................... 27-7

27-6 TSTATE High Byte................................................................................................. 27-9

27-7 INTMSK Mask Bits............................................................................................... 27-10

27-8 Channel Mode Register (CHAMR) ....................................................................... 27-10

27-9 Rx Internal State (RSTATE) High Byte................................................................ 27-12

27-10 Channel Mode Register (CHAMR)ÑTransparent Mode...................................... 27-14

27-11 SI MCC Configuration Register (MCCF) ............................................................. 27-15

27-12 Interrupt Circular Table ......................................................................................... 27-17

27-13 MCC Event Register (MCCE)/Mask Register (MCCM) ...................................... 27-18

27-14 Interrupt Circular Table Entry ...............................................................................27-20

27-15 MCC Receive Buffer Descriptor (RxBD) ............................................................. 27-21

27-16 MCC Transmit Buffer Descriptor (TxBD) ............................................................ 27-23

28-1 FCC Block Diagram ................................................................................................28-3

28-2 General FCC Mode Register (GFMR) .................................................................... 28-3

28-3 FCC Memory Structure ........................................................................................... 28-9

28-4 Buffer Descriptor Format ........................................................................................ 28-9

28-5 Function Code Register (FCRx) ............................................................................ 28-13

28-6 Output Delay from RTS Asserted.......................................................................... 28-16

28-7 Output Delay from CTS Asserted.......................................................................... 28-17

28-8 CTS Lost................................................................................................................ 28-18

28-9 Using CD to Control Reception............................................................................. 28-19

29-1 APC Scheduling Table Mechanism....................................................................... 29-10

29-2 VBR Pacing Using the GCRA (Leaky Bucket Algorithm) ................................... 29-12

29-3 External CAM Data Input Fields........................................................................... 29-14

29-4 External CAM Output Fields................................................................................. 29-14

29-5 Address Compression Mechanism ........................................................................ 29-16

29-6 General VCOFFSET Formula for Contiguous VCLTs ......................................... 29-17

29-7 VP Pointer Address Compression ......................................................................... 29-18

29-8 VC Pointer Address Compression ......................................................................... 29-18

29-9 ATM Address Recognition Flowchart................................................................... 29-19

29-10 MPC8260Õs ABR Basic Model ............................................................................. 29-20

29-11 ABR Transmit Flow .............................................................................................. 29-22

29-12 ABR Transmit Flow (Continued) .......................................................................... 29-23

29-13 ABR Transmit Flow (Continued) .......................................................................... 29-24

29-14 ABR Receive Flow ................................................................................................ 29-25

29-15 Rate Format for RM Cells ..................................................................................... 29-26

29-16 Rate Formula for RM Cells ................................................................................... 29-26

29-17 Performance Monitoring Cell Structure (FMCs and BRCs) ................................. 29-29

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29-18 FMC, BRC Insertion.............................................................................................. 29-32

29-19 Format of User-Defined Cells ............................................................................... 29-33

29-20 External CAM Address in UDC Extended Address Mode ................................... 29-33

29-21 ATM-to-TDM Interworking.................................................................................. 29-35

29-22 VCI Filtering Enable Bits ...................................................................................... 29-40

29-23 Global Mode Entry (GMODE).............................................................................. 29-41

29-24 Example of a 1024-Entry Receive Connection Table ........................................... 29-43

29-25 Receive Connection Table (RCT) Entry................................................................ 29-44

29-26 AAL5 Protocol-Specific RCT ............................................................................... 29-46

29-27 AAL5-ABR Protocol-Specific RCT...................................................................... 29-47

29-28 AAL1 Protocol-Specific RCT ............................................................................... 29-48

29-29 AAL0 Protocol-Specific RCT ............................................................................... 29-50

29-30 Transmit Connection Table (TCT) Entry ..............................................................29-51

29-31 AAL5 Protocol-Specific TCT................................................................................ 29-54

29-32 AAL1 Protocol-Specific TCT................................................................................ 29-54

29-33 AAL0 Protocol-Specific TCT................................................................................ 29-55

29-34 Transmit Connection Table Extension (TCTE)ÑVBR Protocol-Specific ........... 29-56

29-35 UBR+ Protocol-Specific TCTE............................................................................. 29-57

29-36 ABR Protocol-Specific TCTE ............................................................................... 29-58

29-37 OAM Performance Monitoring Table ...................................................................29-60

29-38 ATM Pace Control Data Structure ........................................................................ 29-62

29-39 The APC Scheduling Table Structure.................................................................... 29-63

29-40 Control Slot............................................................................................................ 29-63

29-41 Transmit Buffers and BD Table Example .............................................................29-65

29-42 Receive Static Buffer Allocation Example............................................................ 29-66

29-43 Receive Global Buffer Allocation Example .......................................................... 29-67

29-44 Free Buffer Pool Structure..................................................................................... 29-67

29-45 Free Buffer Pool Entry........................................................................................... 29-68

29-46 AAL5 RxBD.......................................................................................................... 29-69

29-47 AAL1 RxBD.......................................................................................................... 29-71

29-48 AAL0 RxBD.......................................................................................................... 29-72

29-49 User-Defined CellÑRxBD Extension................................................................... 29-74

29-50 AAL5 TxBD .......................................................................................................... 29-74

29-51 AAL1 TxBD .......................................................................................................... 29-76

29-52 AAL0 TxBDs......................................................................................................... 29-77

29-53 User-Defined CellÑTxBD Extension................................................................... 29-78

29-54 AAL1 Sequence Number (SN) Protection Table .................................................. 29-78

29-55 Interrupt Queue Structure ......................................................................................29-80

29-56 Interrupt Queue Entry ............................................................................................ 29-80

29-57 UTOPIA Master Mode Signals ............................................................................. 29-82

29-58 UTOPIA Slave Mode Signals................................................................................ 29-83

29-59 FCC ATM Mode Register (FPSMR)..................................................................... 29-86

29-60 ATM Event Register (FCCE)/FCC Mask Register (FCCM) ................................ 29-88

Title

Page

Number

xlii MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

ILLUSTRATIONS

Figure
Number

Title

Page

Number

29-62 FCC Transmit Internal Rate Clocking................................................................... 29-89

29-61 FCC Transmit Internal Rate Registers (FTIRRx).................................................. 29-89

29-63 COMM_INFO Field .............................................................................................. 29-90

29-64 AAL1 SRTS Generation Using External Logic .................................................... 29-91

29-65 AAL1 SRTS Clock Recovery Using External Logic ............................................29-92

30-1 Ethernet Frame Structure......................................................................................... 30-1

30-2 Ethernet Block Diagram .........................................................................................30-3

30-3 Connecting the MPC8260 to Ethernet..................................................................... 30-5

30-4 Ethernet Address Recognition Flowchart.............................................................. 30-16

30-5 FCC Ethernet Mode Registers (FPSMR) .............................................................. 30-20

30-6 Ethernet Event Register (FCCE)/Mask Register (FCCM) .................................... 30-22

30-7 Ethernet Interrupt Events Example........................................................................ 30-23

30-8 Fast Ethernet Receive Buffer (RxBD)................................................................... 30-24

30-9 Ethernet Receiving Using RxBDs .........................................................................30-26

30-10 Fast Ethernet Transmit Buffer (TxBD).................................................................. 30-27

31-1 HDLC Framing Structure ........................................................................................31-2

31-2 HDLC Address Recognition Example..................................................................... 31-5

31-3 HDLC Mode Register (FPSMR) .............................................................................31-8

31-4 FCC HDLC Receiving Using RxBDs ................................................................... 31-10

31-5 FCC HDLC Receive Buffer Descriptor (RxBD)................................................... 31-11

31-6 FCC HDLC Transmit Buffer Descriptor (TxBD) ................................................. 31-12

31-7 HDLC Event Register (FCCE)/Mask Register (FCCM) ....................................... 31-14

31-8 HDLC Interrupt Event Example............................................................................ 31-16

31-9 FCC Status Register (FCCS) .................................................................................31-16

32-1 In-Line Synchronization Pattern.............................................................................. 32-3

32-2 Sending Transparent Frames between MPC8260s .................................................. 32-4

33-1 SPI Block Diagram .................................................................................................. 33-1

33-2 Single-Master/Multi-Slave Configuration ............................................................... 33-3

33-3 Multimaster Configuration ...................................................................................... 33-5

33-4 SPMODEÑSPI Mode Register............................................................................... 33-6

33-5 SPI Transfer Format with SPMODE[CP] = 0 ......................................................... 33-7

33-6 SPI Transfer Format with SPMODE[CP] = 1 ......................................................... 33-7

33-7 SPIE/SPIMÑSPI Event/Mask Registers................................................................. 33-9

33-8 SPCOMÑSPI Command Register ........................................................................ 33-10

33-9 RFCR/TFCRÑFunction Code Registers .............................................................. 33-12

33-10 SPI Memory Structure ........................................................................................... 33-13

33-11 SPI RxBD .............................................................................................................. 33-14

33-12 SPI TxBD............................................................................................................... 33-15

34-1 I
34-2 I
34-3 I
34-4 I
34-5 I

2

C Controller Block Diagram................................................................................. 34-1

2

C Master/Slave General Configuration ................................................................ 34-2

2

C Transfer Timing ................................................................................................34-3

2

C Master Write Timing......................................................................................... 34-4

2

C Master Read Timing ......................................................................................... 34-5

MOTOROLA Illustrations xliii

ILLUSTRATIONS

Figure
Number

2

34-6 I
34-7 I
34-8 I

34-9 I2C Event/Mask Registers (I2CER/I2CMR) ........................................................... 34-8

34-10 I
34-11 I
34-12 I
34-13 I
34-14 I

C Mode Register (I2MOD)................................................................................... 34-6

2

C Address Register (I2ADD) ............................................................................... 34-7

2

C Baud Rate Generator Register (I2BRG) ...........................................................34-7

2

C Command Register (I2COM) ........................................................................... 34-9

2

C Function Code Registers (RFCR/TFCR) ........................................................ 34-11

2

C Memory Structure ........................................................................................... 34-12

2

C RxBD .............................................................................................................. 34-13

2

C TxBD............................................................................................................... 34-14

Title

Page

Number

35-1 Port Open-Drain Registers (PODRAÐPODRD)...................................................... 35-2

35-2 Port Data Registers (PDATAÐPDATD).................................................................. 35-3

35-3 Port Data Direction Register (PDIR)....................................................................... 35-3

35-4 Port Pin Assignment Register (PPARAÐPPARD) .................................................. 35-4

35-5 Special Options Registers (PSORAÐPOSRD)......................................................... 35-5

35-6 Port Functional Operation........................................................................................ 35-6

35-7 Primary and Secondary Option Programming......................................................... 35-8

xliv MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

TABLES

Tabl e
Number

i Acronyms and Abbreviated Terms............................................................................. lxi

ii Terminology Conventions ....................................................................................... lxiv

iii Instruction Field Conventions ................................................................................... lxv

iv Acronyms and Abbreviated Terms ...................................................................... I-lxviii

1-1 MPC8260 Serial Protocols ........................................................................................ 1-9

1-2 MPC8260 Serial Performance ................................................................................. 1-10

2-1 HID0 Field Descriptions.......................................................................................... 2-12

2-2 HID1 Field Descriptions.......................................................................................... 2-15

2-3 HID2 Field Descriptions.......................................................................................... 2-15

2-4 Exception Classifications for the Processor Core.................................................... 2-24

2-5 Exceptions and Conditions ......................................................................................2-24

2-6 Integer Divide Latency ............................................................................................2-30

2-7 Major Differences between MPC8260Õs Core and the MPC603e UserÕs

Manual.................................................................................................................. 2-30

3-1 Internal Memory Map................................................................................................ 3-1

v Acronyms and Abbreviated Terms ........................................................................... II-ii

4-1 System Configuration and Protection Functions ....................................................... 4-2

4-2 Interrupt Source Priority Levels ................................................................................ 4-9

4-3 Encoding the Interrupt Vector .................................................................................4-14

4-4 SICR Field Descriptions .......................................................................................... 4-18

4-5 SIPRR Field Descriptions........................................................................................ 4-19

4-6 SCPRR_H Field Descriptions.................................................................................. 4-20

4-7 SCPRR_L Field Descriptions .................................................................................. 4-20

4-8 SIEXR Field Descriptions ....................................................................................... 4-25

4-9 BCR Field Descriptions........................................................................................... 4-26

4-10 PPC_ACR Field Descriptions.................................................................................. 4-28

4-11 LCL_ACR Field Descriptions ................................................................................. 4-30

4-12 SIUMCR Register Field Descriptions .....................................................................4-32

4-13 IMMR Field Descriptions........................................................................................ 4-34

4-14 SYPCR Field Descriptions ......................................................................................4-35

4-15 TESCR1 Field Descriptions .................................................................................... 4-36

4-16 TESCR2 Field Descriptions .................................................................................... 4-38

4-17 L_TESCR1 Field Descriptions ................................................................................ 4-39

4-18 L_TESCR2 Field Descriptions ................................................................................ 4-40

4-19 TMCNTSC Field Descriptions ................................................................................ 4-40

4-20 TMCNTAL Field Descriptions................................................................................ 4-42

Title

Page

Number

MOTOROLA Tables xlv

TABLES

Tabl e
Number

4-21 PISCR Field Descriptions........................................................................................ 4-43

4-22 PITC Field Descriptions ..........................................................................................4-44

4-23 PITR Field Descriptions ..........................................................................................4-44

4-24 SIU Pins Multiplexing Control................................................................................ 4-45

5-1 Reset Causes .............................................................................................................. 5-1

5-2 Reset Actions for Each Reset Source ........................................................................ 5-2

5-3 RSR Field Descriptions ............................................................................................. 5-4

5-4 RMR Field Descriptions ............................................................................................ 5-5

5-5 RSTCONF Connections in Multiple-MPC8260 Systems ......................................... 5-6

5-6 Configuration EPROM Addresses............................................................................. 5-7

5-7 Hard Reset Configuration Word Field Descriptions ................................................. 5-8

vi Acronyms and Abbreviated Terms .........................................................................III-iii

6-1 External Signals ......................................................................................................... 6-3

7-1 DP[0Ð7] Signal Assignments................................................................................... 7-15

8-1 Terminology .............................................................................................................. 8-1

8-2 Transfer Type Encoding ..........................................................................................8-10

8-3 Transfer Code Encoding .......................................................................................... 8-13

8-4 Transfer Size Signal Encoding ................................................................................ 8-13

8-5 Burst Ordering .........................................................................................................8-14

8-6 Aligned Data Transfers............................................................................................ 8-15

8-7 Unaligned Data Transfer Example (4-Byte Example)............................................. 8-16

8-8 Data Bus Requirements For Read Cycle .................................................................8-18

8-9 Data Bus Contents for Write Cycles........................................................................ 8-19

8-10 Address and Size State Calculations........................................................................ 8-20

8-11 Data Bus Contents for Extended Write Cycles........................................................ 8-21

8-12 Data Bus Requirements for Extended Read Cycles ................................................ 8-21

8-13 Address and Size State for Extended Transfers....................................................... 8-22

9-1 Clock Default Modes................................................................................................. 9-2

9-2 Clock Configuration Modes ...................................................................................... 9-2

9-3 Dedicated PLL Pins ................................................................................................... 9-7

9-4 SCCR Field Descriptions........................................................................................... 9-8

9-5 SCMR Field Descriptions.......................................................................................... 9-9

10-1 Number of PSDVAL Assertions Needed for TA Assertion.................................. 10-12

10-2 60x Bus Memory Controller Registers .................................................................. 10-13

10-3 BRx Field Descriptions.......................................................................................... 10-14

10-4 ORx Field Descriptions (SDRAM Mode) ............................................................. 10-16

10-5 ORxÑGPCM Mode Field Descriptions................................................................ 10-18

10-6 Option Register (ORx)ÑUPM Mode.................................................................... 10-20

10-7 PSDMR Field Descriptions ................................................................................... 10-21

10-8 LSDMR Field Descriptions ................................................................................... 10-24

10-9 Machine x Mode Registers (MxMR)..................................................................... 10-27

10-10 MDR Field Descriptions........................................................................................ 10-29

10-11 MAR Field Description ......................................................................................... 10-30

Title

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Number

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Number

10-12 60x Bus-Assigned UPM Refresh Timer (PURT) .................................................. 10-30

10-13 Local Bus-Assigned UPM Refresh Timer (LURT)............................................... 10-31

10-14 60x Bus-Assigned SDRAM Refresh Timer (PSRT) .............................................10-31

10-15 LSRT Field Descriptions ....................................................................................... 10-32

10-16 MPTPR Field Descriptions.................................................................................... 10-32

10-17 SDRAM Interface Signals ..................................................................................... 10-33

10-18 SDRAM Interface Commands............................................................................... 10-35

10-19 SDRAM Address Multiplexing (A0ÐA15)............................................................ 10-37

10-20 SDRAM Address Multiplexing (A16ÐA31).......................................................... 10-38

10-21 60x Address Bus Partition .....................................................................................10-48

10-22 SDRAM Device Address Port during activate Command .................................... 10-49

10-23 SDRAM Device Address Port during read/write Command................................. 10-49

10-24 Register Settings (Page-Based Interleaving........................................................... 10-49

10-25 60x Address Bus Partition .....................................................................................10-50

10-26 SDRAM Device Address Port during activate Command .................................... 10-50

10-27 SDRAM Device Address Port during read/write Command................................. 10-50

10-28 Register Settings (Bank-Based Interleaving)......................................................... 10-51

10-29 GPCM Interfaces Signals ...................................................................................... 10-51

10-30 GPCM Strobe Signal Behavior.............................................................................. 10-52

10-31 TRLX and EHTR Combinations ...........................................................................10-58

10-32 Boot Bank Field Values after Reset....................................................................... 10-62

10-33 UPM Interfaces Signals ......................................................................................... 10-62

10-34 UPM Routines Start Addresses ............................................................................. 10-65

10-35 RAM Word Bit Settings ........................................................................................ 10-71

10-36 MxMR Loop Field Usage...................................................................................... 10-76

10-37 UPM Address Multiplexing................................................................................... 10-77

10-38 60x Address Bus Partition .....................................................................................10-80

10-39 DRAM Device Address Port during an activate command................................... 10-80

10-40 Register Settings .................................................................................................... 10-80

10-41 UPMs Attributes Example..................................................................................... 10-82

10-42 UPMs Attributes Example..................................................................................... 10-90

10-43 EDO Connection Field Value Example................................................................. 10-92

12-1 TAP Signals ............................................................................................................. 12-2

12-2 Boundary Scan Bit Definition ................................................................................. 12-6

12-3 Instruction Decoding ............................................................................................. 12-29

vii Acronyms and Abbreviated Terms.......................................................................... IV-v

13-1 Possible MPC8260 Applications ............................................................................. 13-3

13-2 Peripheral Prioritization........................................................................................... 13-6

13-3 RISC Controller Configuration Register Field Descriptions................................... 13-8

13-4 RTSCR Field Descriptions ....................................................................................13-10

13-5 RISC Microcode Revision Number....................................................................... 13-10

13-6 CP Command Register Field Descriptions ............................................................ 13-11

13-7 CP Command Opcodes.......................................................................................... 13-13

Title

Page

Number

MOTOROLA Tables xlvii

TABLES

Tabl e
Number

13-8 Command Descriptions ......................................................................................... 13-14

13-9 Buffer Descriptor Format ...................................................................................... 13-17

13-10 Parameter RAM ..................................................................................................... 13-18

13-11 RISC Timer Table Parameter RAM ......................................................................13-20

14-1 SIx RAM Entry (MCC = 0) ................................................................................... 14-11

14-2 SIx RAM Entry (MCC = 1) ................................................................................... 14-13

14-3 SIx RAM Entry Descriptions................................................................................. 14-14

14-4 SIxGMR Field Descriptions ..................................................................................14-17

14-5 SIxMR Field Descriptions ..................................................................................... 14-18

14-6 SIxRSR Field Descriptions.................................................................................... 14-24

14-7 SIxCMDR Field Description ................................................................................. 14-25

14-8 SIxSTR Field Descriptions .................................................................................... 14-25

14-9 IDL Signal Descriptions ........................................................................................14-27

14-10 SIx RAM Entries for an IDL Interface .................................................................. 14-30

14-11 GCI Signals............................................................................................................ 14-31

14-12 SIx RAM Entries for a GCI Interface (SCIT Mode) ............................................. 14-34

15-1 Clock Source Options .............................................................................................. 15-6

15-2 CMXUAR Field Descriptions ................................................................................. 15-7

15-3 CMXSI1CR Field Descriptions............................................................................. 15-11

15-4 CMXSI2CR Field Descriptions............................................................................. 15-12

15-5 CMXFCR Field Descriptions ................................................................................15-13

15-6 CMXSCR Field Descriptions ................................................................................15-15

15-7 CMXSMR Field Descriptions ............................................................................... 15-18

16-1 BRGCx Field Descriptions ...................................................................................... 16-3

16-2 BRG External Clock Source Options ......................................................................16-4

16-3 Typical Baud Rates for Asynchronous Communication .........................................16-5

17-1 TGCR1 Field Descriptions ......................................................................................17-4

17-2 TGCR2 Field Descriptions ......................................................................................17-5

17-3 TMRIÐTMR4 Field Descriptions ............................................................................17-6

17-4 TER Field Descriptions ........................................................................................... 17-9

18-1 SDSR Field Descriptions......................................................................................... 18-3

18-2 PDTEM and LDTEM Field Descriptions................................................................ 18-4

18-3 IDMA Transfer Parameters ..................................................................................... 18-7

18-4 IDMAx Parameter RAM ....................................................................................... 18-16

18-5 DCM Field Descriptions........................................................................................ 18-18

18-6 IDMA Channel Data Transfer Operation ..............................................................18-20

18-7 Valid Memory-to-Memory STS/DTS Values ....................................................... 18-21

18-8 Valid STS/DTS Values for Peripherals ................................................................. 18-21

18-9 IDSR/IDMR Field Descriptions ............................................................................18-23

18-10 IDMA BD Field Descriptions................................................................................ 18-24

18-11 IDMA Bus Exceptions........................................................................................... 18-27

18-12 Parallel I/O Register ProgrammingÑPort C ......................................................... 18-28

18-13 Parallel I/O Register ProgrammingÑPort A......................................................... 18-28

Title

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Number

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TABLES

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Number

18-14 Parallel I/O Register ProgrammingÑPort D......................................................... 18-29

18-15 Example: Peripheral-to-Memory ModeÑIDMA2 ................................................ 18-29

18-16 Example: Memory-to-Peripheral Fly-By Mode (on 60x)ÐIDMA3 ....................... 18-30

19-1 GSMR_H Field Descriptions................................................................................... 19-4

19-2 GSMR_L Field Descriptions ................................................................................... 19-6

19-3 TODR Field Descriptions ...................................................................................... 19-10

19-4 SCC Parameter RAM Map for All Protocols ........................................................19-13

19-5 Parameter RAMÑSCC Base Addresses ...............................................................19-15

19-6 RFCRx /TFCRx Field Descriptions....................................................................... 19-16

19-7 SCCx Event, Mask, and Status Registers ............................................................. 19-16

19-8 Preamble Requirements ......................................................................................... 19-24

19-9 DPLL Codings ....................................................................................................... 19-25

20-1 UART-Specific SCC Parameter RAM Memory Map ............................................. 20-4

20-2 Transmit Commands................................................................................................ 20-6

20-3 Receive Commands .................................................................................................20-7

20-4 Control Character Table, RCCM, and RCCR Descriptions ....................................20-9

20-5 TOSEQ Field Descriptions .................................................................................... 20-10

20-6 DSR Fields Descriptions........................................................................................ 20-12

20-7 Transmission Errors............................................................................................... 20-12

20-8 Reception Errors .................................................................................................... 20-13

20-9 PSMR UART Field Descriptions .......................................................................... 20-14

20-10 SCC UART RxBD Status and Control Field Descriptions ................................... 20-17

20-11 SCC UART TxBD Status and Control Field Descriptions.................................... 20-18

20-12 SCCE/SCCM Field Descriptions for UART Mode............................................... 20-21

20-13 UART SCCS Field Descriptions ...........................................................................20-22

20-14 UART Control Characters for S-Records Example............................................... 20-24

21-1 HDLC-Specific SCC Parameter RAM Memory Map ............................................. 21-4

21-2 Transmit Commands................................................................................................ 21-5

21-3 Receive Commands ................................................................................................21-6

21-4 Transmit Errors ...................................................................................................... 21-6

21-5 Receive Errors ......................................................................................................... 21-6

21-6 PSMR HDLC Field Descriptions ............................................................................ 21-7

21-7 SCC HDLC RxBD Status and Control Field Descriptions ..................................... 21-9

21-8 SCC HDLC TxBD Status and Control Field Descriptions.................................... 21-11

21-9 SCCE/SCCM Field Descriptions........................................................................... 21-12

21-10 HDLC SCCS Field Descriptions ...........................................................................21-14

22-1 SCC BISYNC Parameter RAM Memory Map........................................................ 22-4

22-2 Transmit Commands................................................................................................ 22-5

22-3 Receive Commands .................................................................................................22-5

22-4 Control Character Table and RCCM Field Descriptions......................................... 22-7

22-5 BSYNC Field Descriptions...................................................................................... 22-8

22-6 BDLE Field Descriptions ........................................................................................ 22-9

22-7 Receiver SYNC Pattern Lengths of the DSR ..........................................................22-9

Title

Page

Number

MOTOROLA Tables xlix

TABLES

Tabl e
Number

22-8 Transmit Errors...................................................................................................... 22-10

22-9 Receive Errors ....................................................................................................... 22-10

22-10 PSMR Field Descriptions ......................................................................................22-11

22-11 SCC BISYNC RxBD Status and Control Field Descriptions................................ 22-12

22-12 SCC BISYNC TxBD Status and Control Field Descriptions................................ 22-14

22-13 SCCE/SCCM Field Descriptions........................................................................... 22-16

22-14 SCCS Field Descriptions ....................................................................................... 22-17

22-15 Control Characters ................................................................................................. 22-18

23-1 Receiver SYNC Pattern Lengths of the DSR ..........................................................23-3

23-2 SCC Transparent Parameter RAM Memory Map ...................................................23-7

23-3 Transmit Commands................................................................................................ 23-7

23-4 Receive Commands .................................................................................................23-8

23-5 Transmit Errors........................................................................................................ 23-8

23-6 Receive Errors ......................................................................................................... 23-8

23-7 SCC Transparent RxBD Status and Control Field Descriptions .............................23-9

23-8 SCC Transparent TxBD Status and Control Field Descriptions ........................... 23-11

23-9 SCCE/SCCM Field Descriptions........................................................................... 23-12

23-10 SCCS Field Descriptions ....................................................................................... 23-13

24-1 SCC Ethernet Parameter RAM Memory Map......................................................... 24-8

24-2 Transmit Commands.............................................................................................. 24-10

24-3 Receive Commands ...............................................................................................24-11

24-4 Transmission Errors............................................................................................... 24-14

24-5 Reception Errors .................................................................................................... 24-15

24-6 PSMR Field Descriptions ......................................................................................24-16

24-7 SCC Ethernet Receive RxBD Status and Control Field Descriptions................... 24-17

24-8 SCC Ethernet Transmit TxBD Status and Control Field Descriptions.................. 24-20

24-9 SCCE/SCCM Field Descriptions........................................................................... 24-21

26-1 SMCMR1/SMCMR2 Field Descriptions ................................................................ 26-4

26-2 SMC UART and Transparent Parameter RAM Memory Map................................ 26-6

26-3 RFCR/TFCR Field Descriptions.............................................................................. 26-8

26-4 Transmit Commands.............................................................................................. 26-12

26-5 Receive Commands ...............................................................................................26-13

26-6 SMC UART Errors ................................................................................................ 26-13

26-7 SMC UART RxBD Field Descriptions ................................................................. 26-14

26-8 SMC UART TxBD Field Descriptions.................................................................. 26-17

26-9 SMCE/SMCM Field Descriptions......................................................................... 26-18

26-10 SMC Transparent Transmit Commands ................................................................ 26-25

26-11 SMC Transparent Receive Commands.................................................................. 26-25

26-12 SMC Transparent Error Conditions....................................................................... 26-25

26-13 SMC Transparent RxBD Field Descriptions ......................................................... 26-26

26-14 SMC Transparent TxBD........................................................................................ 26-27

26-15 SMC Transparent TxBD Field Descriptions ......................................................... 26-27

26-16 SMCE/SMCM Field Descriptions......................................................................... 26-28

Title

Page

Number

l MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

TABLES

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Number

26-17 SMC GCI Parameter RAM Memory Map............................................................. 26-30

26-18 SMC GCI Commands............................................................................................ 26-32

26-19 SMC Monitor Channel RxBD Field Descriptions................................................. 26-32

26-20 SMC Monitor Channel TxBD Field Descriptions ................................................. 26-33

26-21 SMC C/I Channel RxBD Field Descriptions......................................................... 26-33

26-22 SMC C/I Channel TxBD Field Descriptions ......................................................... 26-34

26-23 SMCE/SMCM Field Descriptions......................................................................... 26-34

27-1 Global Multiple-Channel Parameters ......................................................................27-3

27-2 Channel Extra Parameters........................................................................................ 27-5

27-3 Channel-Specific Parameters for HDLC .................................................................27-8

27-4 TSTATE High-Byte Field Descriptions .................................................................. 27-9

27-5 CHAMR Field Descriptions ..................................................................................27-10

27-6 RSTATE High-Byte Field Descriptions................................................................ 27-12

27-7 Channel-Specific Parameters for Transparent Operation ...................................... 27-12

27-8 CHAMR Field DescriptionsÑTransparent Mode................................................. 27-14

27-9 MCCF Field Descriptions...................................................................................... 27-15

27-10 Group Channel Assignments ................................................................................. 27-16

27-11 Transmit Commands.............................................................................................. 27-16

27-12 Receive Commands ...............................................................................................27-17

27-13 MCCE/MCCM Register Field Descriptions.......................................................... 27-19

27-14 Interrupt Circular Table Entry Field Descriptions................................................. 27-20

27-15 RxBD Field Descriptions....................................................................................... 27-21

27-16 TxBD Field Descriptions....................................................................................... 27-23

28-1 GFMR Register Field Descriptions .........................................................................28-4

28-2 FCC Data Synchronization Register (FDSR) .......................................................... 28-7

28-3 FCC Transmit-on-Demand Register (TODR) .........................................................28-8

28-4 TODR Field Descriptions ........................................................................................ 28-8

28-5 FCC Parameter RAM Common to All Protocols ..................................................28-11

28-6 FCRx Field Descriptions ....................................................................................... 28-13

29-1 ATM Service Types................................................................................................. 29-9

29-2 External CAM Input and Output Field Descriptions............................................. 29-15

29-3 Field Descriptions for Address Compression ........................................................ 29-16

29-4 VCOFFSET Calculation Examples for Contiguous VCLTs ................................. 29-17

29-5 VP-Level Table Entry Address Calculation Example ........................................... 29-17

29-6 VC-Level Table Entry Address Calculation Example........................................... 29-18

29-7 Fields and their Positions in RM Cells ..................................................................29-26

29-8 Pre-Assigned Header Values at the UNI ...............................................................29-27

29-9 Pre-Assigned Header Values at the NNI ...............................................................29-28

29-10 Performance Monitoring Cell Fields .....................................................................29-30

29-11 ATM Parameter RAM Map................................................................................... 29-38

29-12 UEAD_OFFSETs for Extended Addresses in the UDC Extra Header ................. 29-40

29-13 VCI Filtering Enable Field Descriptions ............................................................... 29-40

29-14 GMODE Field Descriptions ..................................................................................29-41

Title

Page

Number

MOTOROLA Tables li

TABLES

Tabl e
Number

29-15 Receive and Transmit Connection Table Sizes .....................................................29-42

29-16 RCT Field Descriptions ......................................................................................... 29-45

29-17 RCT Settings (AAL5 Protocol-Specific)............................................................... 29-47

29-18 ABR Protocol-Specific RCT Field Descriptions................................................... 29-48

29-19 AAL1 Protocol-Specific RCT Field Descriptions................................................. 29-49

29-20 AAL0-Specific RCT Field Descriptions ............................................................... 29-50

29-21 TCT Field Descriptions ......................................................................................... 29-52

29-22 AAL5-Specific TCT Field Descriptions................................................................ 29-54

29-23 AAL1-Specific TCT Field Descriptions................................................................ 29-55

29-24 AAL0-Specific TCT Field Descriptions................................................................ 29-56

29-25 VBR-Specific TCTE Field Descriptions ...............................................................29-56

29-26 UBR+ Protocol-Specific TCTE Field Descriptions .............................................. 29-57

29-27 ABR-Specific TCTE Field Descriptions ...............................................................29-58

29-28 OAMÑPerformance Monitoring Table Field Descriptions.................................. 29-61

29-29 APC Parameter Table ............................................................................................29-62

29-30 APC Priority Table Entry ...................................................................................... 29-63

29-31 Control Slot Field Description............................................................................... 29-64

29-32 Free Buffer Pool Entry Field Descriptions ............................................................ 29-68

29-33 Free Buffer Pool Parameter Table ......................................................................... 29-68

29-34 Receive and Transmit Buffers ...............................................................................29-69

29-35 AAL5 RxBD Field Descriptions ........................................................................... 29-70

29-36 AAL1 RxBD Field Descriptions ........................................................................... 29-72

29-37 AAL0 RxBD Field Descriptions ........................................................................... 29-73

29-38 AAL5 TxBD Field Descriptions............................................................................ 29-75

29-39 AAL1 TxBD Field Descriptions............................................................................ 29-76

29-40 AAL0 TxBD Field Descriptions............................................................................ 29-77

29-41 UNI Statistics Table............................................................................................... 29-79

29-42 Interrupt Queue Entry Field Description ............................................................... 29-81

29-43 Interrupt Queue Parameter Table........................................................................... 29-81

29-44 UTOPIA Master Mode Signal Descriptions.......................................................... 29-82

29-45 UTOPIA Slave Mode Signals................................................................................ 29-84

29-46 UTOPIA Loop-Back Modes.................................................................................. 29-85

29-47 FCC ATM Mode Register (FPSMR)..................................................................... 29-86

29-48 FCCE/FCCM Field Descriptions........................................................................... 29-88

29-49 FTIRRx Field Descriptions.................................................................................... 29-89

29-50 COMM_INFO Field Descriptions......................................................................... 29-90

30-1 Flow Control Frame Structure ................................................................................. 30-8

30-2 Ethernet-Specific Parameter RAM .......................................................................... 30-9

30-3 Transmit Commands.............................................................................................. 30-12

30-4 Receive Commands ...............................................................................................30-13

30-5 RMON Statistics and Counters.............................................................................. 30-14

30-6 Transmission Errors............................................................................................... 30-19

30-7 Reception Errors .................................................................................................... 30-19

Title

Page

Number

lii MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

TABLES

Tabl e
Number

Title

Page

Number

30-8 FPSMR Ethernet Field Descriptions ..................................................................... 30-20

30-9 FCCE/FCCM Field Descriptions........................................................................... 30-22

30-10 RxBD Field Descriptions....................................................................................... 30-24

30-11 Ethernet TxBD Field Definitions........................................................................... 30-27

31-1 FCC HDLC-Specific Parameter RAM Memory Map ............................................. 31-4

31-2 Transmit Commands................................................................................................ 31-5

31-3 Receive Commands .................................................................................................31-6

31-4 HDLC Transmission Errors..................................................................................... 31-6

31-5 HDLC Reception Errors .........................................................................................31-7

31-6 FPSMR Field Descriptions ...................................................................................... 31-8

31-7 RxBD field Descriptions........................................................................................ 31-11

31-8 HDLC TxBD Field Descriptions .......................................................................... 31-13

31-9 FCCE/FCCM Field Descriptions........................................................................... 31-15

31-10 FCCS Register Field Descriptions......................................................................... 31-17

33-1 SPMODE Field Descriptions................................................................................... 33-6

33-2 Example Conventions.............................................................................................. 33-8

33-3 SPIE/SPIM Field Descriptions ................................................................................33-9

33-4 SPCOM Field Descriptions ................................................................................... 33-10

33-5 SPI Parameter RAM Memory Map ....................................................................... 33-10

33-6 RFCR/TFCR Field Descriptions............................................................................ 33-12

33-7 SPI Commands ...................................................................................................... 33-12

33-8 SPI RxBD Status and Control Field Descriptions ................................................. 33-14

33-9 SPI TxBD Status and Control Field Descriptions ................................................. 33-15

34-1 I2MOD Field Descriptions ......................................................................................34-6

34-2 I2ADD Field Descriptions....................................................................................... 34-7

34-3 I2BRG Field Descriptions ....................................................................................... 34-8

34-4 I2CER/I2CMR Field Descriptions .......................................................................... 34-8

34-5 I2COM Field Descriptions ...................................................................................... 34-9

34-6 I

34-7 RFCR/TFCR Field Descriptions............................................................................ 34-11

34-8 I

34-9 I2C RxBD Status and Control Bits........................................................................ 34-13

34-10 I

2

C Parameter RAM Memory Map ......................................................................... 34-9

2

C Transmit/Receive Commands......................................................................... 34-11

2

C TxBD Status and Control Bits ........................................................................ 34-14

35-1 PODRx Field Descriptions .....................................................................................35-2

35-2 PDIR Field Descriptions.......................................................................................... 35-3

35-3 PPAR Field Descriptions......................................................................................... 35-4

35-4 PSORx Field Descriptions....................................................................................... 35-5

35-5 Port AÑDedicated Pin Assignment (PPARA = 1) ................................................. 35-8

35-6 Port B Dedicated Pin Assignment (PPARB = 1)................................................... 35-12

35-7 Port C Dedicated Pin Assignment (PPARC = 1)................................................... 35-14

35-8 Port D Dedicated Pin Assignment (PPARD = 1) ................................................ 35-17

A-1 User-Level PowerPC Registers (Non-SPRs)............................................................ A-1

A-2 User-Level PowerPC SPRs....................................................................................... A-1

MOTOROLA Tables liii

TABLES

Tabl e
Number

A-3 Supervisor-Level PowerPC Registers (Non-SPR).................................................... A-2

A-4 Supervisor-Level PowerPC SPRs............................................................................. A-2

A-5 MPC8260-Specific Supervisor-Level SPRs ............................................................. A-3

Title

Page

Number

liv MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

About This Book

The primary objective of this manual is to help communications system designers build
systems using the Motorola MPC8260 and to help software designers provide operating
systems and user-level applications to take fullest advantage of the MPC8260.

Although this book describes aspects regarding the PowerPCª architecture that are critical
for understanding the MPC8260 core, it does not contain a complete description of the
architecture. Where additional information might help the reader, references are made to
The PowerPC Microprocessor Family: The Programming Environments. Ordering
information for this book are provided in the section, ÒPowerPC Documentation.Ó

The information in this book is subject to change without notice, as described in the
disclaimers on the title page of this book. As with any technical documentation, it is the
readersÕ responsibility to be sure they are using the most recent version of the
documentation. For more information, contact your sales representative.

Before Using this ManualÑImportant Note

Before using this manual, determine whether it is the latest revision and if there are errata
or addenda. To locate any published errata or updates for this document, refer to the world­wide web at http://www.motorola.com/netcomm.

Audience

This manual is intended for software and hardware developers and application
programmers who want to develop products for the MPC8260. It is assumed that the reader
has a basic understanding of computer networking, OSI layers, and RISC architecture. In
addition, it is assumed that the reader has a basic understanding of the communications
protocols described here. Where it is considered useful, additional sources are provided that
provide in-depth discussions of such topics.

MOTOROLA About This Book lv

Organization

Following is a summary and a brief description of the chapters of this manual:

¥ Part I, ÒOverview,Ó provides a high-level description of the MPC8260, describing

general operation and listing basic features.

Ñ Chapter 1, ÒOverview,Ó provides a high-level description of MPC8260 functions

and features. It roughly follows the structure of this book, summarizing the
relevant features and providing references for the reader who needs additional
information.

Ñ Chapter 2, ÒPowerPC Processor Core,Ó provides an overview of the MPC8260

core, summarizing topics described in further detail in subsequent chapters.

Ñ Chapter 3, ÒMemory Map,Ó presents a table showing where MPC8260 registers

are mapped in memory. It includes cross references that indicate where the
registers are described in detail.

¥ Part II, ÒConÞguration and Reset,Ó describes start-up behavior of the MPC8260

Ñ Chapter 4, ÒSystem Interface Unit (SIU),Ó describes the system conÞguration

and protection functions which provide various monitors and timers, and the 60x
bus conÞguration.

Ñ Chapter 5, ÒReset,Ó describes the behavior of the MPC8260 at reset and start-up.

¥ Part III, ÒThe Hardware Interface,Ó describes external signals, clocking, memory

control, and power management of the MPC8260.

Ñ Chapter 6, ÒExternal Signals,Ó shows a functional pinout of the MPC8260 and

describes the MPC8260 signals.

Ñ Chapter 7, Ò60x Signals,Ó describes signals on the 60x bus.

Ñ Chapter 8, ÒThe 60x Bus,Ó describes the operation of the bus used by PowerPC

processors.

Ñ Chapter 9, ÒClocks and Power Control,Ó describes the clocking architecture of

the MPC8260.

Ñ Chapter 10, ÒMemory Controller,Ó describes the memory controller, which

controlling a maximum of eight memory banks shared between a general­purpose chip-select machine (GPCM) and three user-programmable machines
(UPMs).

Ñ Chapter 11, ÒSecondary (L2) Cache Support,Ó provides information about

implementation and conÞguration of a level-2 cache.

Ñ Chapter 12, ÒIEEE 1149.1 Test Access Port,Ó describes the dedicated user-

accessible test access port (TAP), which is fully compatible with the IEEE

1149.1 Standard Test Access Port and Boundary Scan Architecture.

¥ Part IV, ÒCommunications Processor Module,Ó describes the conÞguration,

clocking, and operation of the various communications protocols supported by the
MPC8260.

lvi MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

Ñ Chapter 13, ÒCommunications Processor Module Overview,Ó provides a brief

overview of the MPC8260 CPM.

Ñ Chapter 14, ÒSerial Interface with Time-Slot Assigner,Ó describes the SIU, which

controls system start-up, initialization and operation, protection, as well as the
external system bus.

Ñ Chapter 15, ÒCPM Multiplexing,Ó describes the CPM multiplexing logic (CMX)

which connects the physical layerÑUTOPIA, MII, modem lines,

Ñ Chapter 16, ÒBaud-Rate Generators (BRGs),Ó describes the eight independent,

identical baud-rate generators (BRGs) that can be used with the FCCs, SCCs,
and SMCs.

Ñ Chapter 17, ÒTimers,Ó describes the MPC8260 timer implementation, which can

be conÞgured as four identical 16-bit or two 32-bit general-purpose timers.

Ñ Chapter 18, ÒSDMA Channels and IDMA Emulation,Ó describes the two

physical serial DMA (SDMA) channels on the MPC8260.

Ñ Chapter 19, ÒSerial Communications Controllers (SCCs),Ó describes the four

serial communications controllers (SCC), which can be conÞgured
independently to implement different protocols for bridging functions, routers,
and gateways, and to interface with a wide variety of standard WANs, LANs, and
proprietary networks.

Ñ Chapter 20, ÒSCC UART Mode,Ó describes the MPC8260 implementation of

universal asynchronous receiver transmitter (UART) protocol that is used for
sending low-speed data between devices.

Ñ Chapter 21, ÒSCC HDLC Mode,Ó describes the MPC8260 implementation of

HDLC protocol.

Ñ Chapter 22, ÒSCC BISYNC Mode,Ó describes the MPC8260 implementation of

byte-oriented BISYNC protocol developed by IBM for use in networking
products.

Ñ Chapter 23, ÒSCC Transparent Mode,Ó describes the MPC8260 implementation

of transparent mode (also called totally transparent mode), which provides a
clear channel on which the SCC can send or receive serial data without bit-level
manipulation.

Ñ Chapter 24, ÒSCC Ethernet Mode,Ó describes the MPC8260 implementation of

Ethernet protocol.

Ñ Chapter 25, ÒSCC AppleTalk Mode,Ó describes the MPC8260 implementation of

AppleTalk.

Ñ Chapter 26, ÒSerial Management Controllers (SMCs),Ó describes two serial

management controllers, full-duplex ports that can be conÞgured independently
to support one of three protocolsÑUART, transparent, or general-circuit
interface (GCI).

MOTOROLA About This Book lvii

Ñ Chapter 27, ÒMulti-Channel Controllers (MCCs),Ó describes the MPC8260Õs

multi-channel controller (MCC), which handles up to 128 serial, full-duplex data
channels.

Ñ Chapter 28, ÒFast Communications Controllers (FCCs),Ó describes the

MPC8260Õs fast communications controllers (FCCs), which are SCCs optimized
for synchronous high-rate protocols.

Ñ Chapter 29, ÒATM Controller,Ó describes the MPC8260 ATM controller, which

provides the ATM and AAL layers of the ATM protocol. The ATM controller
performs segmentation and reassembly (SAR) functions of AAL5, AAL1, and
AAL0, and most of the common parts convergence sublayer (CP-CS) of these
protocols.

Ñ Chapter 30, ÒFast Ethernet Controller,Ó describes the MPC8260Õs

implementation of the Ethernet IEEE 802.3 protocol.

Ñ Chapter 31, ÒFCC HDLC Controller,Ó describes the FCC implementation of the

HDLC protocol.

Ñ Chapter 32, ÒFCC Transparent Controller,Ó describes the FCC implementation

of the transparent protocol.

Ñ Chapter 33, ÒSerial Peripheral Interface (SPI),Ó describes the serial peripheral

interface, which allows the MPC8260 to exchange data between other MPC8260
chips, the MC68360, the MC68302, the M68HC11, and M68HC05
microcontroller families, and peripheral devices such as EEPROMs, real-time
clocks, A/D converters, and ISDN devices.

Ñ Chapter 34, ÒI2C Controller,Ó describes the MPC8260 implementation of the

2

inter-integrated circuit (I

2

C devices, such as microcontrollers, EEPROMs, real-time clock devices,

other I

C¨) controller, which allows data to be exchanged with

and A/D converters.

Ñ Chapter 35, ÒParallel I/O Ports,Ó describes the four general-purpose I/O

ports AÐD. Each signal in the I/O ports can be conÞgured as a general-purpose
I/O signal or as a signal dedicated to supporting communications devices, such
as SMCs, SCCs. MCCs, and FCCs.

¥ Appendix A, ÒRegister Quick Reference Guide,Ó provides a quick reference to the

registers incorporated in the PowerPC core.

¥ This book also includes an index and a glossary.

lviii MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

Suggested Reading

This section lists additional reading that provides background for the information in this
manual as well as general information about the PowerPC architecture.

MPC8xx Documentation

Supporting documentation for the MPC8260 can be accessed through the world-wide web
at http://www.mot.com/netcomm. This documentation includes technical speciÞcations,
reference materials, and detailed applications notes.

PowerPC Documentation

The PowerPC documentation is organized in the following types of documents:

¥ UserÕs manualsÑThese books provide details about individual PowerPC

implementations and are intended to be used in conjunction with The Programming
Environments Manual. These include the following:

Ñ PowerPC MPC603eª & EC603e RISC Microprocessor UserÕs Manual

(Motorola order #: MPC603EUM/AD, Rev. 1)

Ñ PowerPC 604ª RISC Microprocessor UserÕs Manual

(Motorola order #: MPC604UM/AD)

¥ Programming environments manualsÑThese books provide information about

resources deÞned by the PowerPC architecture that are common to PowerPC
processors. There are two versions, one that describes the functionality of the
combined 32- and 64-bit architecture models and one that describes only the 32-bit
model.

Ñ PowerPC Microprocessor Family: The Programming Environments, Rev 1

(Motorola order #: MPCFPE/AD)

Ñ PowerPC Microprocessor Family: The Programming Environments for 32-Bit

Microprocessors, Rev. 1 (Motorola order #: MPCFPE32B/AD)

¥ PowerPC Microprocessor Family: The Bus Interface for 32-Bit Microprocessors

(Motorola order #: MPCBUSIF/AD) provides a detailed functional description of
the 60x bus interface, as implemented on the PowerPC MPC601ª, MPC603e,
MPC604, and MPC750 family of PowerPC microprocessors. This document is
intended to help system and chip set developers by providing a centralized reference
source to identify the bus interface presented by the 60x family of PowerPC
microprocessors.

¥ PowerPC Microprocessor Family: The ProgrammerÕs Reference Guide

(Motorola order #: MPCPRG/D) is a concise reference that includes the register
summary, memory control model, exception vectors, and the PowerPC instruction
set.

¥ PowerPC Microprocessor Family: The ProgrammerÕs Pocket Reference Guide

(Motorola order #: MPCPRGREF/D). This feedlot card provides an overview of the
PowerPC registers, instructions, and exceptions for 32-bit implementations.

MOTOROLA About This Book lix

¥ Application notesÑThese short documents contain useful information about

speciÞc design issues useful to programmers and engineers working with PowerPC
processors.

For a current list of PowerPC documentation, refer to the world-wide web at
http://www.mot.com/PowerPC.

Conventions

This document uses the following notational conventions:

Bold

Bold entries in Þgures and tables showing registers and parameter
RAM should be initialized by the user.

mnemonics Instruction mnemonics are shown in lowercase bold.

italics Italics indicate variable command parameters, for example, bcctrx.

Book titles in text are set in italics.

0x0 PreÞx to denote hexadecimal number

0b0 PreÞx to denote binary number

rA, rB Instruction syntax used to identify a source GPR

rD Instruction syntax used to identify a destination GPR

REG[FIELD] Abbreviations or acronyms for registers or buffer descriptors are

shown in uppercase text. SpeciÞc bits, Þelds, or numerical ranges
appear in brackets. For example, MSR[LE] refers to the little-endian
mode enable bit in the machine state register.

x In certain contexts, such as in a signal encoding or a bit Þeld,

indicates a donÕt care.

n Used to express an undeÞned numerical value

 NOT logical operator

& AND logical operator

| OR logical operator

lx MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

Acronyms and Abbreviations

Table i contains acronyms and abbreviations used in this document. Note that the meanings
for some acronyms (such as SDR1 and DSISR) are historical, and the words for which an
acronym stands may not be intuitively obvious.

Table i. Acronyms and Abbreviated Terms

Term Meaning

A/D Analog-to-digital

ALU Arithmetic logic unit

ATM Asynchronous transfer mode

BD Buffer descriptor

BIST Built-in self test

BPU Branch processing unit

BRI Basic rate interface.

BUID Bus unit ID

CAM Content-addressable memory

CEPT Conference des administrations Europeanes des Postes et Telecommunications (European

CMX CPM multiplexing logic

CPM Communication processor module

CR Condition register

CRC Cyclic redundancy check

CTR Count register

DABR Data address breakpoint register

DAR Data address register

DEC Decrementer register

DMA Direct memory access

DPLL Digital phase-locked loop

DRAM Dynamic random access memory

DSISR Register used for determining the source of a DSI exception

DTLB Data translation lookaside buffer

EA Effective address

EEST Enhanced Ethernet serial transceiver

EPROM Erasable programmable read-only memory

FPR Floating-point register

FPSCR Floating-point status and control register

Conference of Postal and Telecommunications Administrations).

MOTOROLA About This Book lxi

Table i. Acronyms and Abbreviated Terms (Continued)

Term Meaning

FPU Floating-point unit

GCI General circuit interface

GPCM General-purpose chip-select machine

GPR General-purpose register

GUI Graphical user interface

HDLC High-level data link control

2

I

C Inter-integrated circuit

IDL Inter-chip digital link

IEEE Institute of Electrical and Electronics Engineers

IrDA Infrared Data Association

ISDN Integrated services digital network

ITLB Instruction translation lookaside buffer

IU Integer unit

JTAG Joint Test Action Group

LIFO Last-in-Þrst-out

LR Link register

LRU Least recently used

LSB Least-signiÞcant byte

lsb Least-signiÞcant bit

LSU Load/store unit

MAC Multiply accumulate

MESI ModiÞed/exclusive/shared/invalidÑcache coherency protocol

MMU Memory management unit

MSB Most-signiÞcant byte

msb Most-signiÞcant bit

MSR Machine state register

NaN Not a number

NIA Next instruction address

NMSI Nonmultiplexed serial interface

No-op No operation

OEA Operating environment architecture

OSI Open systems interconnection

lxii MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

Table i. Acronyms and Abbreviated Terms (Continued)

Term Meaning

PCI Peripheral component interconnect

PCMCIA Personal Computer Memory Card International Association

PIR Processor identiÞcation register

PRI Primary rate interface

PVR Processor version register

RISC Reduced instruction set computing

RTOS Real-time operating system

RWITM Read with intent to modify

Rx Receive

SCC Serial communication controller

SCP Serial control por t

SDLC Synchronous Data Link Control

SDMA Serial DMA

SI Serial interface

SIMM Signed immediate value

SIU System interface unit

SMC Serial management controller

SNA Systems network architecture

SPI Serial peripheral interface

SPR Special-purpose register

SPRGn Registers available for general purposes

SRAM Static random access memory

SRR0 Machine status save/restore register 0

SRR1 Machine status save/restore register 1

TAP Test access port

TB Time base register

TDM Time-division multiplexed

TLB Translation lookaside buffer

TSA Time-slot assigner

Tx Transmit

UART Universal asynchronous receiver/transmitter

UIMM Unsigned immediate value

MOTOROLA About This Book lxiii

Table i. Acronyms and Abbreviated Terms (Continued)

Term Meaning

UISA User instruction set architecture

UPM User-programmable machine

USART Universal synchronous/asynchronous receiver/transmitter

USB Universal serial bus

VA Virtual address

VEA Virtual environment architecture

XER Register used primarily for indicating conditions such as carries and overßows for integer operations

PowerPC Architecture Terminology Conventions

Table ii lists certain terms used in this manual that differ from the architecture terminology
conventions.

Table ii. Terminology Conventions

The Architecture SpeciÞcation This Manual

Data storage interrupt (DSI) DSI exception

Extended mnemonics SimpliÞed mnemonics

Instruction storage interrupt (ISI) ISI exception

Interrupt Exception

Privileged mode (or privileged state) Supervisor-level privilege

Problem mode (or problem state) User-level privilege

Real address Physical address

Relocation Translation

Storage (locations) Memory

Storage (the act of) Access

lxiv MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

Table iii describes instruction Þeld notation conventions used in this manual.

Table iii. Instruction Field Conventions

The Architecture SpeciÞcation Equivalent to:

BA, BB, BT crbA, crbB, crbD (respectively)

BF, BFA crfD, crfS (respectively)

Dd

DS ds

FLM FM

FXM CRM

RA, RB, RT, RS rA, rB, rD, rS (respectively)

SI SIMM

U IMM

UI UIMM

/, //, /// 0...0 (shaded)

MOTOROLA About This Book lxv

lxvi MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

Part I

Overview

Intended Audience

Part I is intended for readers who need a high-level understanding of the MPC8260.

Contents

Part I provides a high-level description of the MPC8260, describing general operation and
listing basic features.

¥ Chapter 1, ÒOverview,Ó provides a high-level description of MPC8260 functions

and features. It roughly follows the structure of this book, summarizing the relevant
features and providing references for the reader who needs additional information.

¥ Chapter 2, ÒPowerPC Processor Core,Ó provides an overview of the MPC8260 core.

¥ Chapter 3, ÒMemory Map,Ó presents a table showing where MPC8260 registers are

mapped in memory. It includes cross references that indicate where the registers are
described in detail.

Conventions

Part I uses the following notational conventions:

mnemonics Instruction mnemonics are shown in lowercase bold.

italics Italics indicate variable command parameters, for example, bcctrx.

Book titles in text are set in italics.

0x0 PreÞx to denote hexadecimal number

0b0 PreÞx to denote binary number

rA, rB Instruction syntax used to identify a source GPR

rD Instruction syntax used to identify a destination GPR

MOTOROLA Part I. Overview Part I-lxvii

Part I. Overview

REG[FIELD] Abbreviations or acronyms for registers or buffer descriptors are

shown in uppercase text. SpeciÞc bits, Þelds, or numerical ranges
appear in brackets. For example, MSR[LE] refers to the little-endian
mode enable bit in the machine state register.

x In certain contexts, such as in a signal encoding or a bit Þeld,

indicates a donÕt care.

n Indicates an undeÞned numerical value

Acronyms and Abbreviations

Table iv contains acronyms and abbreviations that are used in this document.

Table iv. Acronyms and Abbreviated Terms

Term Meaning

ATM Asynchronous Mode

BD Buffer descriptor

BPU Branch processing unit

COP Common on-chip processor

CP Communications processor

CPM Communications processor module

CRC Cyclic redundancy check

CTR Count register

DABR Data address breakpoint register

DAR Data address register

DEC Decrementer register

DMA Direct memory access

DPLL Digital phase-locked loop

DRAM Dynamic random access memory

DTLB Data translation lookaside buffer

EA Effective address

FCCÔ Fast communications controller

FPR Floating-point register

GPCM General-purpose chip-select machine

GPR General-purpose register

HDLC High-level data link control

2

I

C Inter-integrated circuit

IEEE Institute of Electrical and Electronics Engineers

Part I-lxviii MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

Table iv. Acronyms and Abbreviated Terms (Continued)

Term Meaning

ISDN Integrated services digital network

ITLB Instruction translation lookaside buffer

IU Integer unit

JTAG Joint Test Action Group

LRU Least recently used (cache replacement algorithm)

LSU Load/store unit

MCC Multi-channel controller

MII Media-independent interface

MMU Memory management unit

MSR Machine state register

NMSI Nonmultiplexed serial interface

OEA Operating environment architecture

OSI Open systems interconnection

PCI Peripheral component interconnect

RISC Reduced instruction set computing

RTC Real-time clock

RTOS Real-time operating system

Rx Receive

SCC Serial communications controller

SDLC Synchronous data link control

SDMA Serial DMA

SI Serial interface

SIU System interface unit

SMC Serial management controller

SPI Serial peripheral interface

SPR Special-purpose register

SRAM Static random access memory

TAP Test access port

TB Time base register

TDM Time-division multiplexed

TLB Translation lookaside buffer

TSA Time-slot assigner

Part I. Overview

MOTOROLA Part I. Overview Part I-lxix

Part I. Overview

Table iv. Acronyms and Abbreviated Terms (Continued)

Term Meaning

Tx Transmit

UART Universal asynchronous receiver/transmitter

UISA User instruction set architecture

UPM User-programmable machine

VEA Virtual environment architecture

Part I-lxx MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

Chapter 1
Overview

10
10

The MPC8260 PowerQUICC IIª is a versatile communications processor that integrates
on one chip a high-performance PowerPCª RISC microprocessor, a very ßexible system
integration unit, and many communications peripheral controllers that can be used in a
variety of applications, particularly in communications and networking systems.

The core is an embedded variant of the PowerPC MPC603eª microprocessor with 16
Kbytes of instruction cache and 16 Kbytes of data cache and no ßoating-point unit (FPU).
The system interface unit (SIU) consists of a ßexible memory controller that interfaces to
almost any user-deÞned memory system, and many other peripherals making this device a
complete system on a chip.

The communications processor module (CPM) includes all the peripherals found in the
MPC860, with the addition of three high-performance communication channels that
support new emerging protocols (for example, 155-Mbps ATM and Fast Ethernet).
MPC8260 has dedicated hardware that can handle up to 256 full-duplex, time-division­multiplexed logical channels

This document describes the functional operation of MPC8260, with an emphasis on
peripheral functions. Chapter 2, ÒPowerPC Processor Core,Ó is an overview of the PowerPC
microprocessor core; detailed information about the core can be found in the MPC603e &
EC603e RISC Microprocessors UserÕs Manual (order number: MPC603EUM/AD).

1.1 Features

The following is an overview of the MPC8260 feature set:

¥ PowerPC dual-issue integer core

Ñ A core version of the MPC603e microprocessor

Ñ System core microprocessor supporting frequencies of 100Ð200 MHz

Ñ Separate 16-Kbyte data and instruction caches:

Ð Four-way set associative

Ð Physically addressed

Ð LRU replacement algorithm

MOTOROLA Chapter 1. Overview 1-1

Part I. Overview

Ñ PowerPC architecture-compliant memory management unit (MMU)

Ñ Common on-chip processor (COP) test interface

Ñ Supports bus snooping for cache coherency

Ñ No ßoating-point unit (FPU). Floating-point arithmetic is not supported.

Ñ Support for ßoating-point loads and stores.

Ñ Support for cache locking.

¥ Low-power (less than 2.5 W when fully operational at 133 MHz, 2-V internal and

3.3-V I/O)

¥ Separate power supply for internal logic (2 V) and for I/O (3.3 V)

¥ Separate PLLs for PowerPC core and for the CPM

Ñ PowerPC core and CPM can run at different frequencies for power/performance

optimization

Ñ Internal PowerPC core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1,

3.5:1, 4:1, 5:1, 6:1 ratios

Ñ Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1,

6:1 ratios

¥ 64-bit data and 32-bit address 60x bus

Ñ Bus supports multiple master designs

Ñ Supports single transfers and burst transfers

Ñ 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller

Ñ Supports data parity or ECC and address parity

¥ 32-bit data and 18-bit address local bus

Ñ Single-master bus, supports external slaves

Ñ Eight-beat burst transfers

Ñ 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller

¥ System interface unit (SIU)

Ñ Clock synthesizer

Ñ Reset controller

Ñ Real-time clock (RTC) register

Ñ Periodic interrupt timer

Ñ Hardware bus monitor and software watchdog timer

Ñ IEEE 1149.1 JTAG test access port

¥ Twelve-bank memory controller

Ñ Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and

other user-deÞnable peripherals

1-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

Part I. Overview

Ñ Byte write enables and selectable parity generation

Ñ 32-bit address decodes with programmable bank size

Ñ Three user programmable machines, general-purpose chip-select machine, and

page mode pipeline SDRAM machine

Ñ Byte selects for 64-bit bus width (60x) and for 32-bit bus width (local)

Ñ Dedicated interface logic for SDRAM

¥ Disable CPU mode

¥ Communications processor module (CPM)

Ñ Embedded 32-bit communications processor (CP) uses a RISC architecture for

ßexible support for communications peripherals

Ñ Interfaces to PowerPC core through on-chip 24-Kbyte dual-port RAM and DMA

controller

Ñ Serial DMA channels for receive and transmit on all serial channels

Ñ Parallel I/O registers with open-drain and interrupt capability

Ñ Virtual DMA functionality executing memory to memory and memory to I/O

transfers

Ñ Three fast communication controllers (FCCs) supporting the following protocols

Ð 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media

independent interface (MII)

Ð ATMÑfull-duplex SAR at 155 Mbps, UTOPIA interface, AAL5, AAL1,

AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR trafÞc types, up to 64 K
external connections

Ð Transparent

Ð HDLCÑup to T3 rates (clear channel)

Ñ Two multichannel controllers (MCCs)

Ð Two 128 serial full-duplex data channels (for a total of 256 64 Kbps channels).

Each MCC can be split into four subgroups of 32 channels each.

Ð Almost any combination of subgroups can be multiplexed to single or

multiple TDM interfaces

Ñ Four serial communications controllers (SCCs) identical to those on the

MPC860, supporting the digital portions of the following protocols:

Ð Ethernet/IEEE 802.3 CDMA/CS

Ð HDLC/SDLC and HDLC bus

Ð Universal asynchronous receiver transmitter (UART)

Ð Synchronous UART

Ð Binary synchronous (BiSync) communications

Ð Transparent

MOTOROLA Chapter 1. Overview 1-3

Part I. Overview

Ñ Two serial management controllers (SMCs), identical to those of the MPC860

Ð Provide management for BRI devices as general-circuit interface (GCI)

controllers in time- division-multiplexed (TDM) channels

Ð Transparent

Ð UART (low-speed operation)

Ñ One serial peripheral interface identical to the MPC860 SPI

2

Ñ One I

C controller (identical to the MPC860 I2C controller)

Ð Microwire compatible

Ð Multiple-master, single-master, and slave modes

Ñ Up to eight TDM interfaces

Ð Supports two groups of four TDM channels for a total of eight TDMs

Ð 2,048 bytes of SI RAM

Ð Bit or byte resolution

Ð Independent transmit and receive routing, frame synchronization.

Ð Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN

basic rate, ISDN primary rate, Motorola interchip digital link (IDL), general
circuit interface (GCI), and user-deÞned TDM serial interfaces

Ñ Eight independent baud rate generators and 20 input clock pins for supplying

clocks to FCC, SCC, and SMC serial channels

Ñ Four independent 16-bit timers that can be interconnected as two 32-bit timers

1.2 MPC8260Õs Architecture Overview

The MPC8260 has two external buses to accommodate bandwidth requirements from the
high-speed system core and the very fast communications channels. As shown in
Figure 1-1, the MPC8260 has three major functional blocks:

¥ A 64-bit PowerPC core derived from the MPC603e with MMUs and cache

¥ A system interface unit (SIU)

¥ A communications processor module (CPM)

1-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

MPC603e

PowerPC

Core

16-Kbyte

Instruction Cache

IMMU

16-Kbyte

Data Cache

DMMU

Part I. Overview

60x Bus

60x -to-Local Bus Bridge

Memory Controller

Local
Bus

Timers

Parallel I/O

Baud Rate Gen.

MCC MCC FCC FCC FCC SCC SCC SCC SCC SMC SMC

Interrupt

Controller

32-Bit RISC Communications

Processor (CP) and

24-Kbyte Dual

Port RAM

Program ROM

Time Slot Assigner

Serial Interface

8 TDMs 2 UTOPIA 3 MIIs Non-Multiplexed I/O

Serial DMAs

4 Virtual
IDMAs

Bus Interface Unit

Clock Counter

System Functions

SPI

2

I

C

Figure 1-1. MPC8260 Block Diagram

Both the system core and the CPM have an internal PLL, which allows independent
optimization of the frequencies at which they run. The system core and CPM are both
connected to the 60x bus.

1.2.1 MPC603e Core

The MPC603e core is derived from the PowerPC MPC603e microprocessor without the
ßoating-point unit and with power management modiÞcations. The core is a high­performance low-power implementation of the PowerPC family of reduced instruction set
computer (RISC) microprocessors. The MPC603e core implements the 32-bit portion of
the PowerPC architecture, which provides 32-bit effective addresses, integer data types of
8, 16, and 32 bits. The MPC603e cache provides snooping to ensure data coherency with
other masters. This helps ensure coherency between the CPM and system core.

The core includes 16 Kbytes of instruction cache and 16 Kbytes of data cache. It has a 64­bit split-transaction external data bus, which is connected directly to the external MPC8260
pins.

MOTOROLA Chapter 1. Overview 1-5

Part I. Overview

The MPC603e core has an internal common on-chip (COP) debug processor. This
processor allows access to internal scan chains for debugging purposes. It is also used as a
serial connection to the core for emulator support.

The MPC603e core performance for the SPEC 95 benchmark for integer operations ranges
between 4.4 and 5.1 at 200 MHz. In Dhrystone 2.1 MIPS, the MPC603e is 280 MIPS at
200 MHz (compared to 86 MIPS of the MPC860 at 66 MHz).

The MPC603e core can be disabled. In this mode, the MPC8260 functions as a slave
peripheral to an external core or to another MPC8260 device with its core enabled.

1.2.2 System Interface Unit (SIU)

The SIU consists of the following:

¥ A 60x-compatible parallel system bus conÞgurable to 64-bit data width. The

MPC8260 supports 64-, 32-, 16-, and 8-bit port sizes. The MPC8260 internal arbiter
arbitrates between internal components that can access the bus (system core, CPM,
and one external master). This arbiter can be disabled, and an external arbiter can be
used if necessary.

¥ A local (32-bit data, 32-bit internal and 18-bit external address) bus. This bus is used

to enhance the operation of the very high-speed communication controllers. Without
requiring extensive manipulation by the core, the bus can be used to store connection
tables for ATM or buffer descriptors (BDs) for the communication channels or raw
data that is transmitted between channels. The local bus is synchronous to the 60x
bus and runs at the same frequency.

¥ Memory controller supporting 12 memory banks that can be allocated for either the

system or the local bus. The memory controller is an enhanced version of the
MPC860 memory controller. It supports three user-programmable machines.
Besides all MPC860 features, the memory controller also supports SDRAM with
page mode and address data pipeline.

¥ Supports JTAG controller IEEE 1149.1 test access port (TAP).

¥ A bus monitor that prevents 60x bus lock-ups, a real-time clock, a periodic interrupt

timer, and other system functions useful in embedded applications.

¥ Glueless interface to L2 cache (MPC2605) and 4-/16-K-entry CAM (MCM69C232/

MCM69C432).

1.2.3 Communications Processor Module (CPM)

The CPM contains features that allow the MPC8260 to excel in a variety of applications
targeted mainly for networking and telecommunication markets.

The CPM is a superset of the MPC860 PowerQUICC CPM, with enhancements on the CP
performance and additional hardware and microcode routines that support high bit rate
protocols like ATM (up to 155 Mbps full-duplex) and Fast Ethernet (100-Mbps full­duplex).

1-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

Part I. Overview

The following list summarizes the major features of the CPM:

¥ The CP is an embedded 32-bit RISC controller residing on a separate bus (CPM

local bus) from the 60x bus (used by the system core). With this separate bus, the CP
does not affect the performance of the PowerPC core. The CP handles the lower
layer tasks and DMA control activities, leaving the PowerPC core free to handle
higher layer activities. The CP has an instruction set optimized for communications,
but can also be used for general-purpose applications, relieving the system core of
small often repeated tasks.

¥ Two serial DMA (SDMA) that can do simultaneous transfers, optimized for burst

transfers to the 60x bus and to the local bus.

¥ Three full-duplex, serial fast communications controllers (FCCs) supporting ATM

(155 Mbps) protocol through UTOPIA2 interface (there are two UTOPIA interfaces
on the MPC8260), IEEE 802.3 and Fast Ethernet protocols, HDLC up to E3 rates
(45 Mbps) and totally transparent operation. Each FCC can be conÞgured to transmit
fully transparent and receive HDLC or vice-versa.

¥ Two multichannel controllers (MCCs) that can handle an aggregate of 256 X 64

Kbps HDLC or transparent channels, multiplexed on up to eight TDM interfaces.
The MCC also supports super-channels of rates higher than 64 Kbps and
subchanneling of the 64-Kbps channels.

¥ Four full-duplex serial communications controllers (SCCs) supporting IEEE802.3/

Ethernet, high- level synchronous data link control, HDLC, local talk, UART,
synchronous UART, BISYNC, and transparent.

¥ Two full-duplex serial management controllers (SMC) supporting GCI, UART, and

transparent operations

2

¥ Serial peripheral interface (SPI) and I

C bus controllers

¥ Time-slot assigner (TSA) that supports multiplexing of data from any of the four

SCCs, three FCCs, and two SMCs.

1.3 Software Compatibility Issues

As much as possible, the MPC8260 CPM features were made similar to those of the
previous devices (MPC860). The code ßow ports easily from previous devices to the
MPC8260, except for new protocols supported by the MPC8260.

Although many registers are new, most registers retain the old status and event bits, so an
understanding of the programming models of the MC68360, MPC860, or MPC85015 is
helpful. Note that the MPC8260 initialization code requires changes from the MPC860
initialization code (Motorola provides reference code).

1.3.1 Signals

Figure 1-2 shows MPC8260 signals grouped by function. Note that many of these signals
are multiplexed and this Þgure does not indicate how these signals are multiplexed.

MOTOROLA Chapter 1. Overview 1-7

Part I. Overview

NOTE

A bar over a signal name indicates that the signal is active
lowÑfor example, BB

(bus busy). Active-low signals are
referred to as asserted (active) when they are low and negated
when they are high. Signals that are not active low, such as
TSIZ[0Ð3] (transfer size signals) are referred to as asserted
when they are high and negated when they are low.

VCCSYN/GNDSYN/VCCSYN1//VDDH/VDD/

SMI/FRAME/

CKSTOP_OUT/IRDY/

CORE_SRESET/RST/

AD[0–31]/

LBS[0Ð3]/LSDDQM[0Ð3]/LWE[0Ð3] <¾¾¾ 4

C/BE[0–3]/

LGPL0/LSDA10 <¾¾¾ 11<¾¾> IRQ5/DP5/TBEN/EXT_DBG3

LGPL1/LSDWE <¾¾¾ 11<¾¾> IRQ6/DP6/CSE0

LGPL2/LSDRAS

LPBS/LGPL4/LUPWAIT/LGTA <¾¾> 11<¾¾> TA

BNKSEL[0]/TC[0]/AP[1]/MODCK1<¾¾> 1
BNKSEL[1]/TC[1]/AP[2]/MODCK2
BNKSEL[2]/TC[2]/AP[3]/MODCK3<¾¾> 11<¾¾- TCK

LGPL3/LSDCAS <¾¾¾ 11<¾¾> PSDVAL

VSS

PAR/

L_A14 <¾¾> 1
L_A15 <¾¾> 14<¾¾> TSIZ[0Ð3]

TRDY/

L_A16 <¾¾> 11<¾¾> TBST
L_A17 <¾¾> 11<¾¾> GBL/IRQ1

STOP/

L_A18 <¾¾> 11<¾¾> CI/BADDR29/IRQ2

DEVSEL/

L_A19 <¾¾> 11<¾¾> WT/BADDR30/IRQ3

IDSEL/

L_A20 <¾¾> 11<¾¾¾ L2_HIT/IRQ4

PERR/

L_A21 <¾¾> 11<¾¾> CPU_BG/BADDR31/IRQ5

SERR/

L_A22 <¾¾> 11<¾¾> BR

REQ0/

L_A23 <¾¾> 11<¾¾> BG

REQ1/

L_A24 <¾¾> 11<¾¾> ABB/IRQ2

GNT0/

L_A25 <¾¾> 11<¾¾> TS

GNT1/

L_A26 <¾¾¾ 11<¾¾> AACK

CLK/

L_A27 <¾¾> 11<¾¾> ARTRY
L_A28 <¾¾> 11<¾¾> DBG

INTA/

L_A29 <¾¾> 11<¾¾> DBB/IRQ3

LOCK/

L_A30 <¾¾> 164<¾¾> D[0Ð63]

L_A31 <¾¾> 11<¾¾> NC/DP0/RSRV/EXT_BR2
LCL_D[0Ð31] <¾¾> 32 1 <¾¾> IRQ1/DP1/EXT_BG2
LCL_DP[0Ð3] <¾¾> 41<¾¾> IRQ2/DP2/TLBISYNC/EXT_DBG2

/LOE <¾¾¾ 11<¾¾> IRQ7/DP7/CSE1

LGPL5 <¾¾> 11<¾¾> TEA

LWR <¾¾> 11<¾¾> IRQ0/NMI_OUT
PA[0Ð31] <¾¾> 32
PB[4Ð31] <¾¾> 28
PC[0Ð31] <¾¾> 32 1 <¾¾> CS[10]/BCTL1/DBG_DIS
PD[4Ð31] <¾¾> 28 1 <¾¾> CS
PORESET¾¾¾> 1

RSTCONF¾¾¾> 11¾¾¾> ALE

HRESET<¾¾> 11¾¾¾> BCTL0
SRESET<¾¾> 18¾¾¾> PWE[0Ð7]/PSDDQM[0Ð7]/PBS[0Ð7]

QREQ<¾¾¾ 11¾¾¾> PSDA10/PGPL0

XFC¾¾¾> 11¾¾¾> POE/PSDRAS/PGPL2

CLKIN¾¾¾> 11<¾¾> PGTA/PUPMWAIT/PGPL4/PPBS

TRIS¾¾¾> 11¾¾¾> PSDAMUX/PGPL5

TERM[0Ð1] ¾¾¾> 21<¾¾- TRST

NC ¾¾¾> 41-¾¾> TDO

¾¾¾>100

32 <¾¾> A[0Ð31]

5 <¾¾> TT[0Ð4]

L
O
C
A

L

P

B
U

O

S

W

E
R
Q

M
E

U

M
C

I

C

P

I

C

1 ¾¾¾> CPU_DBG
1 ¾¾¾> CPU_BR

6
0
x

B
U

S

1 <¾¾> IRQ3/DP3/CKSTP_OUT/EXT_BR3
1 <¾¾> IRQ4/DP4/CORE_SRESET/EXT_BG3

1 <¾¾> IRQ7/INT_OUT/APE

10 ¾¾¾> CS[0Ð9]

O

2 ¾¾¾> BADDR[27Ð28]

M

II

R
S

T

E
M
C

1 ¾¾¾> PSDWE/PGPL1

1 ¾¾¾> PSDCAS

C

L

<¾¾> 11<¾¾¾ TDI

K

1 <¾¾- TMS

J

T
A
G

[11]/AP[0]

/PGPL3

Figure 1-2. MPC8260 External Signals

1-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

Part I. Overview

1.4 Differences between MPC860 and MPC8260

The following MPC860 features are not included in the MPC8260.

¥ On-chip crystal oscillators (must use external oscillator)

¥ 4-MHz oscillator (input clock must be at the bus speed)

¥ Low power (stand-by) modes

¥ Battery-backup real-time clock (must use external battery-backup clock)

¥ BDM (COP offers most of the same functionality)

¥ True little-endian mode

¥ PCMCIA interface

¥ Infrared (IR) port

¥ QMC protocol in SCC (256 HDLC channels are supported by the MCCs)

¥ Multiply and accumulate (MAC) block in the CPM

¥ Centronics port (PIP)

¥ Asynchronous HDLC protocol (optional RAM microcode)

¥ Pulse-width modulated outputs

¥ SCC Ethernet controller option to sample 1 byte from the parallel port when a

receive frame is complete

¥ Parallel CAM interface for SCC (Ethernet)

1.5 Serial Protocol Table

Table 1-1 summarizes available protocols for each serial port.

Table 1-1. MPC8260 Serial Protocols

Port

FCC SCC MCC SMC

ATM (Utopia) Ö

100BaseT Ö

10BaseT ÖÖ

HDLC ÖÖÖ

HDLC_BUS Ö

Transparent ÖÖÖÖ

UART ÖÖ

DPLL Ö

Multichannel Ö

MOTOROLA Chapter 1. Overview 1-9

Port

Part I. Overview

1.6 MPC8260 ConÞgurations

The MPC8260 offers ßexibility in conÞguring the device for speciÞc applications. The
functions mentioned in the above sections are all available in the device, but not all of them
can be used at the same time. This does not imply that the device is not fully activated in
any given implementation: The CPM architecture has the advantage of using common
hardware resources for many different protocols, and applications. Two physical factors
limit the functionality in any given systemÑpinout and performance.

1.6.1 Pin ConÞgurations

Some pins have multiple functions. Choosing one function may preclude the use of another.
Information about multiplexing constraints can be found in Chapter 15, ÒCPM
Multiplexing,Ó and Chapter 35, ÒParallel I/O Ports.Ó

1.6.2 Serial Performance

Serial performance depends on a number of factors:

¥ Serial rate versus CPM clock frequency for adequate sampling on serial channels

¥ Serial rate and protocol versus CPM clock frequency for CP protocol handling

¥ Serial rate and protocol versus bus bandwidth

¥ Serial rate and protocol versus system core clock for adequate protocol handling

The second item above is addressed in this sectionÑthe CPÕs ability to handle high bit-rate
protocols in parallel. Slow bit-rate protocols do not signiÞcantly affect those numbers.

Table 1-2 describes a few options to conÞgure the fast communications channels on the
MPC8260. The frequency speciÞed is the minimum CPM frequency necessary to run the
mentioned protocols concurrently at full-duplex.

Table 1-2. MPC8260 Serial Performance

FCC1 FCC2 FCC3 MCC CPM Clock 60x Bus Clock

155-Mbps ATM 100 BaseT 100 BaseT 133 MHz 66 MHz

100 BaseT 100 BaseT 100 BaseT 133 MHz 66 MHz

155-Mbps ATM 128 * 64 Kbps channels 133 MHz 66 MHz

100 BaseT 100 BaseT 128 * 64 Kbps channels 133 MHz 66 MHz

155-Mbps ATM 256 * 64 Kbps channels 166 MHz 66 MHz

100 BaseT 256 * 64 Kbps channels 133 MHz 66 MHz

45-Mbps HDLC 256 * 64 Kbps 133 MHz 66 MHz

45-Mbps HDLC 100 BaseT 256 * 64 Kbps 166 MHz 66 MHz

100 BaseT 16 * 576 Kbps 166 MHz 66 MHz

1-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

Part I. Overview

MPC8260

FCCs can also be used to run slower HDLC or 10 BaseT, for example. The CPÕs RISC
architecture has the advantage of using common hardware resources for all FCCs.

1.7 MPC8260 Application Examples

The MPC8260 can be conÞgured to meet many system application needs, as shown in the
following sections.

1.7.1 Examples of Communication Systems

Communication examples:

¥ Remote access server
¥ Regional ofÞce router
¥ LAN-to-WAN bridge router
¥ Cellular base station
¥ Telecom switch controller
¥ SONET transmission controller

1.7.1.1 Remote Access Server

See Figure 1-3 for remote access server conÞguration.

Quad

T1

Framer

155 Mbps

PHYATM

MII

Transceiver

Framer

Slow

Comm

PHY

or

or

TDM0

TDM7

UTOPIA Multi PHY

10/100BaseT

E3 clear channel
(takes one TDM)

2

SMC/I

C/SPI/SCC

60x Bus

Local Bus

SDRAM/DRAM/SRAM

Channelized Data

(up to 256 channels)

SDRAM/DRAM/SRAM

ATM

Connection Tables

(optional)

DSP Bank

Slaves

on

Local

Bus

Figure 1-3. Remote Access Server Configuration

MOTOROLA Chapter 1. Overview 1-11

Part I. Overview

In this application, eight TDM ports are connected to external framers. In the MPC8260,
each group of four ports support up to 128 channels. One TDM interface can support 32Ð
128 channels. The MPC8260 receives and transmits data in transparent or HDLC mode,
and stores or retrieves the channelized data from memory. The data can be stored either in
memory residing on the 60x bus or in memory residing on the local bus.

The main trunk can be conÞgured as 155 Mbps full-duplex ATM, using the UTOPIA
interface, or as 10/100 BaseT Fast Ethernet with MII interface, or as a high-speed serial
channel (up to 45 Mbps). In ATM mode, there may be a need to store connection tables in
external memory on the local bus; for example, 128 active internal connections require 8
Kbytes of dual-port RAM. The need for local bus depends on the total throughput of the
system. The MPC8260 supports automatic (without software intervention) cross connect
between ATM and MCC, routing ATM AAL1 frames to MCC slots.

The local bus can be used as an interface to a bank of DSPs that can run code that performs
analog modem signal modulation. Data to and from the DSPs can be transferred through
the parallel bus with the internal virtual IDMA.

The MPC8260 memory controller supports many types of memories, including EDO
DRAM and page-mode, pipeline SDRAM for efÞcient burst transfers.

1.7.1.2 Regional OfÞce Router

Figure 1-4 shows a regional ofÞce router conÞguration.

MPC8260

Quad

T1

Framer

MII

Transceiver

Slow

Comm

PHY

TDM0

TDM3

10/100BaseT

10/100BaseT

2

C/SPI/SCC

SMC/I

60x Bus

SDRAM/DRAM/SRAM

Channelized Data

(up to 128 channels)

Figure 1-4. Regional Office Router Configuration

1-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

Part I. Overview

In this application, the MPC8260 is connected to four TDM interfaces channalizing up to
128 channels. Each TDM port supports 32Ð128 channels. If 128 channels are needed, each
TDM port can be conÞgured to support 32 channels. This example has two MII ports for
10/100 BaseT LAN connections. In all the examples, the SCC ports can be used for
management.

1.7.1.3 LAN-to-WAN Bridge Router

Figure 1-5 shows a LAN-to-WAN router conÞguration, which is similar to the previous
example.

MPC8260

MII

Transceiver

155 Mbps

PHYATM

155 Mbps

PHYATM

MII

Transceiver

Slow

Comm

PHY

or

10/100BaseT

UTOPIA Multi PHY

UTOPIA Multi PHY

10/100BaseT

SMC/I2C/SPI/SCC

60x Bus

Local Bus

Figure 1-5. LAN-to-WAN Bridge Router Configuration

SDRAM/DRAM/SRAM

Data

SDRAM/DRAM/SRAM

ATM Connection
Tables (optional)

MOTOROLA Chapter 1. Overview 1-13

Part I. Overview

1.7.1.4 Cellular Base Station

Figure 1-6 shows a cellular base station conÞguration.

MPC8260

Framer

TDM0

60x Bus

TDM1

SDRAM/DRAM/SRAM

Channelized Data

(up to 256 channels)

DSP Bank

Slow

Comm

PHY

SMC/I2C/SPI/SCC

Local Bus

Slaves

on

Local

Bus

Figure 1-6. Cellular Base Station Configuration

Here the MPC8260 channelizes two E1s (up to 256, 16-Kbps channels).

The local bus can control a bank of DSPs. Data to and from the DSPs can be transferred
through the parallel bus to the host port of the DSPs with the internal virtual IDMA.

The slow communication ports (SCCs, SMCs, I2C, SPI) can be used for management and
debug functions.

1.7.1.5 Telecommunications Switch Controller

Figure 1-7 shows a telecommunications switch controller conÞguration.

MPC8260

155 Mbps

ATM

MII

Transceiver

PHY

UTOPIA Multi PHY

10/100BaseT

10/100BaseT

SDRAM/DRAM/SRAM

60x Bus

SDRAM/DRAM/SRAM

ATM

Connection

Tables

Slow

Comm

PHY

2

SMC/I

C/SPI/SCC

(10BaseT)

Local Bus

Figure 1-7. Telecommunications Switch Controller Configuration

1-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

Part I. Overview

The MPC8260 CPM supports a total aggregate throughput of 710 Mbps at 133 MHz. This
includes two full-duplex 100 BaseT and one full-duplex 155 Mbps for ATM. The MPC603e
core can operate at a different (higher) speed, if the application requires it.

1.7.1.6 SONET Transmission Controller

Figure 1-8 shows a SONET transmission controller conÞguration.

MPC8260

576 Kbps

SONET

Transceivers

MII

Transceiver

Slow

Comm

PHY

TDM0

TDM3

10/100BaseT

2

SMC/I

C/SPI/SCC

(10BaseT)

60x Bus

Local Bus

SDRAM/DRAM/SRAM

Channelized Data

(up to 16 channels)

SDRAM/DRAM/SRAM

ATM

Connection

Tables

Figure 1-8. SONET Transmission Controller ConÞguration

In this application, the MPC8260 implements super channeling with the MCC. Nine 64­Kbps channels are combined to form a 576-Kbps channel. The MPC8260 at 133 MHz can
support up to sixteen 576-Kbps superchannels. The MPC8260 also supports subchanneling
(under 64 Kbps) with its MCC.

1.7.2 Bus ConÞgurations

The following sections describe the following possible bus conÞgurations:

¥ Basic system

¥ High-performance communication system

¥ High-performance system core

1.7.2.1 Basic System

In the basic system conÞguration., shown in Figure 1-9, the MPC8260 core is enabled and
uses the 64-bit 60x data bus. The 32-bit local bus data is needed to store connection tables
for many active ATM connections. The local bus may also be used to store data that does

MOTOROLA Chapter 1. Overview 1-15

Part I. Overview

not need to be heavily processed by the core. The CP can store large data frames in the local
memory without interfering with the operation of the system core.

SDRAM/SRAM/DRAM/Flash

SDRAM/SRAM/DRAM

Connection Tables

PHY

155 Mbps

ATM

PHY

MPC8260

Communication
Channels

UTOPIA

60x Bus

Local Bus

Figure 1-9. Basic System Configuration

1.7.2.2 High-Performance Communication

Figure 1-10 shows a high-performance communication conÞguration.

PHY

155 Mbps

ATM

PHY

MPC8260 A

Communication
Channels

UTOPIA

Local Bus

60x Bus

SDRAM/SRAM/DRAM

Connection Tables

SDRAM/SRAM/DRAM/Flash

ATM

ATM

MPC8260 B

(master/slave)

PHY

155 Mbps

ATM

PHY

Communication
Channels

UTOPIA

Local Bus

SDRAM/SRAM/DRAM

ATM

Connection Tables

Figure 1-10. High-Performance Communication

1-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

Part I. Overview

Serial throughput is enhanced by connecting one MPC8260 in master or slave mode (with
system core enabled or disabled) to another MPC8260 in master mode with the core
enabled. The core in MPC8260 A can access the memory on the local bus of MPC8260 B.

1.7.2.3 High-Performance System Microprocessor

Figure 1-11 shows a conÞguration with a high-performance system microprocessor
(MPC750).

MPC750

Backside

Cache

SDRAM/SRAM/DRAM

PHY

155 Mbps

ATM

PHY

MPC8260 (slave)

Communication
Channels

UTOPIA

32-Kbyte I cache

32-Kbyte D cache

60x Bus

Local Bus

SDRAM/SRAM/DRAM

ATM

Connection Tables

Figure 1-11. High-Performance System Microprocessor Configuration

In this system, the MPC603e core internal is disabled and an external high-performance
microprocessor is connected to the 60x bus.

MOTOROLA Chapter 1. Overview 1-17

Part I. Overview

1-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

Chapter 2
PowerPC Processor Core

20
20

The MPC8260 contains an embedded version of the PowerPC 603eª processor. This
chapter provides an overview of the basic functionality of the processor core. For detailed
information regarding the processor refer to the following:

¥ MPC603e & EC603e UserÕs Manual (Those chapters that describe the

programming model, cache model, memory management model, exception model,
and instruction timing)

¥ PowerPCª Microprocessor Family: The Programming Environments for 32-Bit

Microprocessors

This section describes the details of the processor core, provides a block diagram showing
the major functional units, and describes brießy how those units interact.

The signals associated with the processor core are described individually in Chapter 7, Ò60x
Signals.Ó Chapter 8, ÒThe 60x Bus,Ó describes how those signals interact.

2.1 Overview

The processor core is a low-power implementation of the PowerPC microprocessor family
of reduced instruction set computing (RISC) microprocessors. The processor core
implements the 32-bit portion of the PowerPC architecture, which supports 32-bit effective
addresses.

Figure 2-1 is a block diagram of the processor core.

MOTOROLA Chapter 2. PowerPC Processor Core 2-1

Part I. Overview

64 Bit

Integer

Unit

+*/

XER

Completion

Unit

Power

Dissipation

Control

JTAG/COP

Interface

GPR File

GPR

Rename

Registers

Time Base

Counter/

Decrementer

Clock

Multiplier

Sequential

Fetcher

64 Bit

Instruction

Queue

Dispatch Unit

64 Bit

Load/Store

Unit

+

Data MMU

SRs

DBAT

DTLB

Tags

Array

16-Kbyte
D Cache

32 Bit

64 Bit32 Bit

64 Bit

64 Bit

Branch

Processing

Unit

CTR

CR

LR

Instruction Unit

FPR File

FPR

Rename

Registers

64 Bit

System

Register

Unit

+

Instruction MMU

SRs

IBAT
Array

ITLB

16-Kbyte

Tags

I Cache

Touch Load Buffer

Copyback Buffer

32-Bit Address Bus

64-Bit Data Bus

60x Bus
Interface

Figure 2-1. MPC8260 Integrated Processor Core Block Diagram

The processor core is a superscalar processor that can issue and retire as many as three
instructions per clock. Instructions can execute out of order for increased performance;
however, the processor core makes completion appear sequential.

2-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

Part I. Overview

The processor core integrates four execution unitsÑan integer unit (IU), a branch
processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU). The
ability to execute four instructions in parallel and the use of simple instructions with rapid
execution times yield high efÞciency and throughput. Most integer instructions execute in
one clock cycle.

The processor core supports integer data types of 8, 16, and 32 bits, and ßoating-point data
types of 32 and 64 bits. Note that although the MPC8260 does not implement a ßoating­point arithmetic unit, it does retain the 32 architecturally-deÞned ßoating point registers
(FPRs), which can be used to hold 32, 64-bit operands that can in turn be transferred to and
from the 32 general-purpose registers (GPRs), which can hold 32, 32-bit operands.

The processor core provides separate on-chip, 16-Kbyte, four-way set-associative,
physically addressed caches for instructions and data and on-chip instruction and data
memory management units (MMUs). The MMUs contain 64-entry, two-way set­associative, data and instruction translation lookaside buffers (DTLB and ITLB) that
provide support for demand-paged virtual memory address translation and variable-sized
block translation. The TLBs and caches use a least recently used (LRU) replacement
algorithm. The processor core also supports block address translation through the use of
two independent instruction and data block address translation (IBAT and DBAT) arrays of
four entries each. Effective addresses are compared simultaneously with all four entries in
the BAT array during block translation. In accordance with the PowerPC architecture, if an
effective address hits in both the TLB and BAT array, the BAT translation takes priority.

As an added feature to the MPC603e core, the MPC8260 can lock the contents of 1Ð3 ways
in the instruction and data cache (or an entire cache). For example, this allows embedded
applications to lock interrupt routines or other important (time-sensitive) instruction
sequences into the instruction cache. It allows data to be locked into the data cache, which
may be important to code that must have deterministic execution.

The processor core has a 60x bus that incorporates a 64-bit data bus and a 32-bit address
bus. The processor core supports single-beat and burst data transfers for memory accesses
and supports memory-mapped I/O operations.

2.2 PowerPC Processor Core Features

This section describes the major features of the processor core:

¥ High-performance, superscalar microprocessor

Ñ As many as three instructions issued and retired per clock cycle

Ñ As many as four instructions in execution per clock cycle

Ñ Single-cycle execution for most instructions

MOTOROLA Chapter 2. PowerPC Processor Core 2-3

Part I. Overview

¥ Four independent execution units and two register Þles

Ñ BPU featuring static branch prediction
Ñ A 32-bit IU
Ñ LSU for data transfer between data cache and GPRs and FPRs
Ñ SRU that executes condition register (CR), special-purpose register (SPR), and

integer add/compare instructions
Ñ Thirty-two GPRs for integer operands
Ñ Thirty-two FPRs. These can be used for operands for ßoating-point load and

store operands,

¥ High instruction and data throughput

Ñ Zero-cycle branch capability (branch folding)
Ñ Programmable static branch prediction on unresolved conditional branches
Ñ BPU that performs CR lookahead operations
Ñ Instruction fetch unit capable of fetching two instructions per clock from the

instruction cache
Ñ A six-entry instruction queue that provides lookahead capability
Ñ Independent pipelines with feed-forwarding that reduces data dependencies in

hardware
Ñ 16-Kbyte data cacheÑfour-way set-associative, physically addressed; LRU

replacement algorithm
Ñ 16-Kbyte instruction cacheÑfour-way set-associative, physically addressed;

LRU replacement algorithm
Ñ Cache write-back or write-through operation programmable on a per page or per

block basis
Ñ Address translation facilities for 4-Kbyte page size, variable block size, and

256-Mbyte segment size
Ñ A 64-entry, two-way set-associative ITLB
Ñ A 64-entry, two-way set-associative DTLB
Ñ Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte

blocks
Ñ Software table search operations and updates supported through fast trap

mechanism
Ñ 52-bit virtual address; 32-bit physical address

¥ Facilities for enhanced system performance

Ñ A 32- or 64-bit, split-transaction external data bus with burst transfers
Ñ Support for one-level address pipelining and out-of-order bus transactions
Ñ Hardware support for misaligned little-endian accesses
Ñ Added bus multipliers of 4.5x, 5x, 5.5x, 6x, 6.5x 7x, 7.5x, 8x. See Figure 2-3.

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Part I. Overview

¥ Integrated power management

Ñ Three power-saving modes: doze, nap, and sleep
Ñ Automatic dynamic power reduction when internal functional units are idle

¥ Deterministic behavior and debug features

Ñ On-chip cache locking options for the instruction and data caches (1Ð3 ways or

the entire cache contents can be locked)
Ñ In-system testability and debugging features through JTAG and boundary-scan

capability

Figure 2-1 shows how the execution unitsÑIU, BPU, LSU, and SRUÑoperate
independently and in parallel. Note that this is a conceptual diagram and does not attempt
to show how these features are physically implemented on the chip.

The processor core provides address translation and protection facilities, including an
ITLB, DTLB, and instruction and data BAT arrays. Instruction fetching and issuing is
handled in the instruction unit. The MMUs translate addresses for cache or external
memory accesses.

2.2.1 Instruction Unit

As shown in Figure 2-1, the instruction unit, which contains a fetch unit, instruction queue,
dispatch unit, and the BPU, provides centralized control of instruction ßow to the execution
units. The instruction unit determines the address of the next instruction to be fetched based
on information from the sequential fetcher and from the BPU.

The instruction unit fetches the instructions from the instruction cache into the instruction
queue. The BPU extracts branch instructions from the fetcher and uses static branch
prediction on unresolved conditional branches to allow the instruction unit to fetch
instructions from a predicted target instruction stream while a conditional branch is
evaluated. The BPU folds out branch instructions for unconditional branches or conditional
branches unaffected by instructions in progress in the execution pipeline.

Instructions issued beyond a predicted branch do not complete execution until the branch
is resolved, preserving the programming model of sequential execution. If any of these
instructions are to be executed in the BPU, they are decoded but not issued. Instructions to
be executed by the IU, LSU, and SRU are issued and allowed to complete up to the register
write-back stage. Write-back is allowed when a correctly predicted branch is resolved, and
instruction execution continues without interruption on the predicted path. If branch
prediction is incorrect, the instruction unit ßushes all predicted path instructions, and
instructions are issued from the correct path.

2.2.2 Instruction Queue and Dispatch Unit

The instruction queue (IQ), shown in Figure 2-1, holds as many as six instructions and
loads up to two instructions from the instruction unit during a single cycle. The instruction
fetch unit continuously loads as many instructions as space in the IQ allows. Instructions

MOTOROLA Chapter 2. PowerPC Processor Core 2-5

Part I. Overview

are dispatched to their respective execution units from the dispatch unit at a maximum rate
of two instructions per cycle. Reservation stations at the IU, LSU, and SRU facilitate
instruction dispatch to those units. The dispatch unit checks for source and destination
register dependencies, determines dispatch serializations, and inhibits subsequent
instruction dispatching as required. Section 2.7, ÒInstruction Timing,Ó describes instruction
dispatch in detail.

2.2.3 Branch Processing Unit (BPU)

The BPU receives branch instructions from the fetch unit and performs CR lookahead
operations on conditional branches to resolve them early, achieving the effect of a zero­cycle branch in many cases.

The BPU uses a bit in the instruction encoding to predict the direction of the conditional
branch. Therefore, when an unresolved conditional branch instruction is encountered,
instructions are fetched from the predicted target stream until the conditional branch is
resolved.

The BPU contains an adder to compute branch target addresses and three user-control
registersÑthe link register (LR), the count register (CTR), and the CR. The BPU calculates
the return pointer for subroutine calls and saves it into the LR for certain types of branch
instructions. The LR also contains the branch target address for the Branch Conditional to
Link Register (bclrx) instruction. The CTR contains the branch target address for the
Branch Conditional to Count Register (bcctrx) instruction. The contents of the LR and
CTR can be copied to or from any GPR. Because the BPU uses dedicated registers rather
than GPRs or FPRs, execution of branch instructions is largely independent from execution
of other instructions.

2.2.4 Independent Execution Units

The PowerPC architectureÕs support for independent execution units allows
implementation of processors with out-of-order instruction execution. For example,
because branch instructions do not depend on GPRs or FPRs, branches can often be
resolved early, eliminating stalls caused by taken branches.

In addition to the BPU, the processor core provides three other execution units and a
completion unit, which are described in the following sections.

2.2.4.1 Integer Unit (IU)

The IU executes all integer instructions. The IU executes one integer instruction at a time,
performing computations with its arithmetic logic unit (ALU), multiplier, divider, and XER
register. Most integer instructions are single-cycle instructions. Thirty-two general-purpose
registers are provided to support integer operations. Stalls due to contention for GPRs are
minimized by the automatic allocation of rename registers. The processor core writes the
contents of the rename registers to the appropriate GPR when integer instructions are
retired by the completion unit.

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Part I. Overview

2.2.4.2 Load/Store Unit (LSU)

The LSU executes all load and store instructions and provides the data transfer interface
between the GPRs, FPRs, and the cache/memory subsystem. The LSU calculates effective
addresses, performs data alignment, and provides sequencing for load/store string and
multiple instructions.

Load and store instructions are issued and translated in program order; however, the actual
memory accesses can occur out of order. Synchronizing instructions are provided to
enforce strict ordering where needed.

Cacheable loads, when free of data dependencies, execute in an out-of-order manner with
a maximum throughput of one per cycle and a two-cycle total latency. Data returned from
the cache is held in a rename register until the completion logic commits the value to a GPR
or FPR. Store operations do not occur until a predicted branch is resolved. They remain in
the store queue until the completion logic signals that the store operation is deÞnitely to be
completed to memory.

The processor core executes store instructions with a maximum throughput of one per cycle
and a three-cycle total latency. The time required to perform the actual load or store
operation varies depending on whether the operation involves the cache, system memory,
or an I/O device.

2.2.4.3 System Register Unit (SRU)

The SRU executes various system-level instructions, including condition register logical
operations and move to/from special-purpose register instructions, and also executes
integer add/compare instructions. Because SRU instructions affect modes of processor
operation, most SRU instructions are completion-serialized. That is, the instruction is held
for execution in the SRU until all prior instructions issued have completed. Results from
completion-serialized instructions executed by the SRU are not available or forwarded for
subsequent instructions until the instruction completes.

2.2.5 Completion Unit

The completion unit tracks instructions from dispatch through execution, and then retires,
or completes them in program order. Completing an instruction commits the processor core
to any architectural register changes caused by that instruction. In-order completion ensures
the correct architectural state when the processor core must recover from a mispredicted
branch or any exception.

Instruction state and other information required for completion is kept in a Þrst-in-Þrst-out
(FIFO) queue of Þve completion buffers. A single completion buffer is allocated for each
instruction once it enters the dispatch unit. An available completion buffer is a required
resource for instruction dispatch; if no completion buffers are available, instruction
dispatch stalls. A maximum of two instructions per cycle are completed in order from the
queue.

MOTOROLA Chapter 2. PowerPC Processor Core 2-7

Part I. Overview

2.2.6 Memory Subsystem Support

The processor core supports cache and memory management through separate instruction
and data MMUs (IMMU and DMMU). The processor core also provides dual 16-Kbyte
instruction and data caches, and an efÞcient processor bus interface to facilitate access to
main memory and other bus subsystems. The memory subsystem support functions are
described in the following subsections.

2.2.6.1 Memory Management Units (MMUs)

The processor coreÕs MMUs support up to 4 Petabytes (252) of virtual memory and
4 Gbytes (2
speciÞcation) for instructions and data. The MMUs also control access privileges for these
spaces on block and page granularities. Referenced and changed status is maintained by the
processor for each page to assist implementation of a demand-paged virtual memory
system. A key bit is implemented to provide information about memory protection
violations prior to page table search operations.

The LSU calculates effective addresses for data loads and stores, performs data alignment
to and from cache memory, and provides the sequencing for load and store string and
multiple word instructions. The instruction unit calculates the effective addresses for
instruction fetching.

The MMUs translate effective addresses and enforce the protection hierarchy programmed
by the operating system in relation to the supervisor/user privilege level of the access and
in relation to whether the access is a load or store.

32

) of physical memory (referred to as real memory in the PowerPC architecture

2.2.6.2 Cache Units

The processor core provides independent 16-Kbyte, four-way set-associative instruction
and data caches. The cache block size is 32 bytes. The caches are designed to adhere to a
write-back policy, but the processor core allows control of cacheability, write policy, and
memory coherency at the page and block levels. The caches use a least recently used (LRU)
replacement algorithm.

The load/store and instruction fetch units provide the caches with the address of the data or
instruction to be fetched. In the case of a cache hit, the cache returns two words to the
requesting unit.

2.3 Programming Model

The following subsections describe the PowerPC instruction set and addressing modes in
general.

2.3.1 Register Set

This section describes the register organization in the processor core as deÞned by the three
programming environments of the PowerPC architectureÑthe user instruction set
architecture (UISA), the virtual environment architecture (VEA), and the operating

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Part I. Overview

environment architecture (OEA), as well as the MPC8260 core implementation-speciÞc
registers. Full descriptions of the basic register set deÞned by the PowerPC architecture are
provided in Chapter 2, ÒPowerPC Register Set,Ó in The Programming Environments
Manual.

The PowerPC architecture deÞnes register-to-register operations for all arithmetic
instructions. Source data for these instructions is accessed from the on-chip registers or is
provided as an immediate value embedded in the opcode. The three-register instruction
format allows speciÞcation of a target register distinct from the two source registers, thus
preserving the original data for use by other instructions and reducing the number of
instructions required for certain operations. Data is transferred between memory and
registers with explicit load and store instructions only.

Figure 2-2 shows the complete MPC8260 register set and the programming environment to
which each register belongs. This Þgure includes both the PowerPC register set and the
MPC8260-speciÞc registers.

Note that there may be registers common to other PowerPC processors that are not
implemented in the MPC8260Õs processor core. Unsupported SPR values are treated as
follows:

¥Any mtspr with an invalid SPR executes as a no-op.

¥Any mfspr with an invalid SPR cause boundedly undeÞned results in the target

register.

Conversely, some SPRs in the processor core may not be implemented in other PowerPC
processors, or may not be implemented in the same way in other PowerPC processors.

2.3.1.1 PowerPC Register Set

The PowerPC UISA registers, shown in Figure 2-2, can be accessed by either user- or
supervisor-level instructions. The general-purpose registers (GPRs) and ßoating-point
registers (FPRs) are accessed through instruction operands. Access to registers can be
explicit (that is, through the use of speciÞc instructions for that purpose such as the mtspr
and mfspr instructions) or implicit as part of the execution (or side effect) of an instruction.
Some registers are accessed both explicitly and implicitly.

The number to the right of the register name indicates the number that is used in the syntax
of the instruction operands to access the register (for example, the number used to access
the XER is one). For more information on the PowerPC register set, refer to Chapter 2,
ÒPowerPC Register Set,Ó in The Programming Environments Manual.

Note that the reset value of the MSR exception preÞx bit (MSR[IP]), described in the
MPC603e UserÕs Manual, is determined by the CIP bit in the hard reset conÞguration word
in the MPC8260. This is described in Section 5.4.1, ÒHard Reset ConÞguration Word.Ó

MOTOROLA Chapter 2. PowerPC Processor Core 2-9

Part I. Overview

USER MODEL

UISA

General-Purpose
Registers

GPR0

GPR1

GPR31

Floating-Point
Registers

FPR0

FPR1

FPR31

Condition Register

CR

XER

XER

Link Register

LR

Count Register

CTR

2

SPR 1

SPR 8

SPR 9

SUPERVISOR MODELÑOEA

Hardware
Implementation
Registers

1

Configuration Registers

Machine State
Register

SPR 1008HID0

SPR 1009HID1

SPR 1011HID2

MSR

Memory Management Registers

Instruction BAT
Registers

SPR 528IBAT0U

IBAT0L

IBAT1U

IBAT1L

IBAT2U

IBAT2L

IBAT3U

IBAT3L

SPR 529

SPR 530

SPR 531

SPR 532

SPR 533

SPR 534

SPR 535

SDR1

SPR 25SDR1

Data BAT Registers

Exception Handling Registers

Data Address Register

DAR

SPR 19

SPRGs

SPR 272SPRG0

SPRG1

SPRG2

SPRG3

SPR 273

SPR 274

SPR 275

Processor Version
Register

Software Table
Search Registers

SPR 536DBAT0U

SPR 537DBAT0L

SPR 538DBAT1U

SPR 539DBAT1L

SPR 540DBAT2U

SPR 541DBAT2L

SPR 542DBAT3U

SPR 543DBAT3L

Segment Registers

DSISR

Save and Restore Registers

SRR0

SRR1

SPR 287PVR

1

SPR 976DMISS

SPR 977DCMP

SPR 978HASH1

SPR 979HASH2

SPR 980IMISS

SPR 981ICMP

SPR 982RPA

SR0

SR1

SR15

SPR 18DSISR

SPR 26

SPR 27

USER MODEL

VEA

Time Base Facility
(For Reading)

TBR 268

TBL

TBU

TBR 269

1

These implementationÐspecific registers may not be supported by other PowerPC processors or processor cores.

2

Although the MPC8260 does not implement an FPU, the LSU can access FPRs if MSR[FP] = 1.

.

Miscellaneous Registers

Time Base Facility
(For Writing)

SPR 284TBL

SPR 285

TBU

Instruction Address
Breakpoint Register

SPR 1010IABR

Decrementer

SPR 22

DEC

1

External Address
Register (Optional)

SPR 282

EAR

Figure 2-2. MPC8260 Programming ModelÑRegisters

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Part I. Overview

Although the MPC8260 does not support ßoating-point arithmetic instructions, the FPRs
are provided to support ßoating-point load and store instructions, which can be executed by
the LSU. For these instructions to execute, the FPRs must be enabled (MSR[FP] = 1);
otherwise, a ßoating-point unavailable exception is taken. It is recommended that the FPRs
be enabled only when there is a need to access the FPRs, for example, to handle ßash
memory updates. Otherwise, the processor should run in default mode, with FPRs disabled
(MSR[FP] = 0).

2.3.1.2 MPC8260-SpeciÞc Registers

The set of registers speciÞc to the MPC603e are also shown in Figure 2-2. Most of these
are described in the MPC603e UserÕs Manual and are implemented in the MPC8260 as
follows:

¥ MMU software table search registers: DMISS, DCMP, HASH1, HASH2, IMISS,

ICMP, and RPA. These registers facilitate the software required to search the page
tables in memory.

¥ IABR. This register facilitates the setting of instruction breakpoints.

The hardware implementation-dependent registers (HIDx) are implemented differently in
the MPC8260, and they are described in the following subsections.

2.3.1.2.1 Hardware Implementation-Dependent Register 0 (HID0)

The processor coreÕs implementation of HID0 differs from the MPC603e UserÕs Manual as
follows:

¥ Bit 5, HID0[EICE], has been removed. There is no support for pipeline tracking.
¥ Bit 24, HID0[IFEM], instruction fetch enable M, has been added.
¥ Bit 28, HID0[ABE], address broadcast enable, has been added.

Figure 2-3 shows the MPC8260 implementation of HID0.

EMCP DOZE SLEEP ILOCK

EBDEBA PAR NAP DPM NHR ICE DCE DCFI

ÑÑ

0 1 2 3 4 6 7 8 9 10 11 12 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Ñ

DLOCK

ICFI

IFEM

Ñ Ñ Ñ

Figure 2-3. Hardware Implementation Register 0 (HID0)

MOTOROLA Chapter 2. PowerPC Processor Core 2-11

ABE

FBIOB NOOPTI

Part I. Overview

Table 2-1 shows the bit deÞnitions for HID0.

Table 2-1. HID0 Field Descriptions

Bits Name Description

0 EMCP Enable machine check input pin

1 Ñ Reserved

2 EBA Enable/disable 60x bus address parity checking

3 EBD Enable 60x bus data parity checking

4Ð6 Ñ Reserved

7 PAR Disable precharge of AR

8 DOZE Doze mode enable. Operates in conjunction with MSR[POW].

9 NAP Nap mode enable. Operates in conjunction with MSR[POW].

10 SLEEP Sleep mode enable. Operates in conjunction with MSR[POW].

0 The asser tion of the MCP
1 Enables the entry into a machine check exception based on assertion of the MCP

detection of a Cache Parity Error, detection of an address parity error, or detection of a data

parity error.
Note that the machine check exception is further affected by MSR[ME], which speciÞes whether
the processor checkstops or continues processing.

0 Prevents address parity checking.
1 Allows a address parity error to cause a checkstop if MSR[ME] = 0 or a machine check

exception if MSR[ME] = 1.
EBA and EBD let the processor operate with memory subsystems that do not generate parity.

0 Parity checking is disabled.
1 Allows a data parity error to cause a checkstop if MSR[ME] = 0 or a machine check exception

if MSR[ME] = 1.
EBA and EBD let the processor operate with memory subsystems that do not generate parity.

0 Precharge of AR
1 Alters bus protocol slightly by preventing the processor from driving AR

state, allowing multiple AR

restore the signals to the high state.

0 Doze mode disabled.
1 Doze mode enabled. Doze mode is invoked by setting MSR[POW] after this bit is set. In doze

mode, the PLL, time base, and snooping remain active.

0 Nap mode disabled.
1 Nap mode enabled. Nap mode is invoked by setting MSR[POW] while this bit is set. When this

occurs, the processor asserts QREQ

system logic determines that the processor may enter nap mode, the quiesce acknowledge

signal, QA

processor enters nap mode after several processor clocks. Because bus snooping is disabled

for nap and sleep modes, this serves as a hardware mechanism for ensuring data coherency.

In nap mode, the PLL and the time base remain active.

0 Sleep mode disabled.
1 Sleep mode enabled. Sleep mode is invoked by setting MSR[POW] while this bit is set. When

this occurs, the processor asserts QREQ

system logic determines that the processor may enter sleep mode, the quiesce acknowledge

signal, QA

processor enters sleep mode after several processor clocks. At this point, the system logic

may turn off the PLL by Þrst conÞguring PLL_CFG[0Ð3] to PLL bypass mode, and then

disabling SYSCLK.

CK, is asserted back to the processor. Once QACK assertion is detected, the

CK, is asserted back to the processor. Once QACK assertion is detected, the

does not cause a machine check exception.

TRY.

TRY enabled

TRY signals to be tied together. If this is done, the system must

to indicate that it is ready to enter nap mode. If the

to indicate that it is ready to enter sleep mode. If the

input,

TRY to high (negated)

1

1

1

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