Motorola MPC8240 User Manual

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MPC8240 Integrated Processor

User’s Manual

MPC8240UM/D

Rev 1, 1/2001

™

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used by Motorola under license from International Business Machines Corporation. I2C is a registered trademark of Philips Semiconductors

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Overview

Signal Descriptions and Clocking

Address Maps

Configuration Registers

PowerPC Processor Core

MPC8240 Memory Interface

PCI Bus Interface

DMA Controller

Message Unit (I

C Interface

Embedded Programmable Interrupt Controller (EPIC)

Central Control Unit

Error Handling

Power Management

2 3 4 5 6 7 8

9 10 11 12 13 14

Debug Features

Programmable I/O and Watchpoint

Address Map A

Bit and Byte Ordering

Initialization Example

PowerPC Instruction Set

Processor Core Register Summary

Glossary of Terms and Abbreviations

Index

15 15 16

A B C D E

GLO

IND

Overview

2 3 4 5 6 7 8

9 10 11 12 13

Signal Descriptions and Clocking Address Maps Configuration Registers PowerPC Processor Core MPC8240 Memory Interface PCI Bus Interface DMA Controller

Message Unit (I

C Interface

Embedded Programmable Interrupt Controller (EPIC) Central Control Unit Error Handling

14 15

A B C D E

GLO

IND

Power Management Debug Features Programmable I/O and Watchpoint

Address Map A Bit and Byte Ordering Initialization Example PowerPC Instruction Set Processor Core Register Summary Glossary of Terms and Abbreviations Index

CONTENTS

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Title

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About This Book

Chapter 1

Overview

1.1 MPC8240 Integrated Processor Overview.......................................................... 1-1

1.1.1 MPC8240 Integrated Processor Features........................................................ 1-3

1.1.2 MPC8240 Integrated Processor Applications................................................. 1-5

1.2 Processor Core Overview ................................................................................... 1-7

1.3 Peripheral Logic Bus......................................................................................... 1-10

1.4 Peripheral Logic Overview............................................................................... 1-11

1.4.1 Peripheral Logic Features............................................................................. 1-11

1.4.2 Peripheral Logic Functional Units................................................................ 1-12

1.4.3 Memory System Interface............................................................................. 1-13

1.4.4 Peripheral Component Interconnect (PCI) Interface .................................... 1-14

1.4.4.1 PCI Bus Arbitration Unit.......................................................................... 1-14

1.4.4.2 Address Maps and Translation ................................................................. 1-14

1.4.4.3 Byte Ordering ........................................................................................... 1-15

1.4.4.4 PCI Agent Capability................................................................................ 1-15

1.4.5 DMA Controller............................................................................................ 1-15

1.4.6 Message Unit (MU)...................................................................................... 1-15

1.4.6.1 Doorbell Registers .................................................................................... 1-15

1.4.6.2 Inbound and Outbound Message Registers .............................................. 1-16

1.4.6.3 Intelligent Input/Output Controller (I

1.4.7 Inter-Integrated Circuit (I

1.4.8 Embedded Programmable Interrupt Controller (EPIC)................................ 1-16

1.4.9 Integrated PCI Bus and SDRAM Clock Generation .................................... 1-17

1.5 Power Management .......................................................................................... 1-18

1.5.1 Programmable Processor Power Management Modes ................................. 1-18

1.5.2 Programmable Peripheral Logic Power Management Modes...................... 1-18

1.6 Programmable I/O Signals with Watchpoint.................................................... 1-19

1.7 Debug Features ................................................................................................. 1-19

1.7.1 Memory Attribute and PCI Attribute Signals............................................... 1-20

1.7.2 Memory Debug Address............................................................................... 1-20

1.7.3 Memory Interface Valid (MIV

C) Controller....................................................... 1-16

).................................................................... 1-20

O) ................................................. 1-16

Contents

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1.7.4 Error Injection/Capture on Data Path ........................................................... 1-20

1.7.5 IEEE 1149.1 (JTAG)/Test Interface............................................................. 1-20

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Chapter 2

Signal Descriptions and Clocking

2.1 Signal Overview.................................................................................................. 2-1

2.1.1 Signal Cross Reference................................................................................... 2-4

2.1.2 Output Signal States during Reset.................................................................. 2-6

2.2 Detailed Signal Descriptions............................................................................... 2-7

2.2.1 PCI Interface Signals...................................................................................... 2-7

2.2.1.1 PCI Bus Request (REQ

2.2.1.1.1 PCI Bus Request (REQ

2.2.1.1.2 PCI Bus Request (REQ

2.2.1.2 PCI Bus Grant (GNT

2.2.1.2.1 PCI Bus Grant (GNT

2.2.1.2.2 PCI Bus Grant (GNT

2.2.1.3 PCI Address/Data Bus (AD[31:0])............................................................. 2-9

2.2.1.3.1 Address/Data (AD[31:0])—Output........................................................ 2-9

2.2.1.3.2 Address/Data (AD[31:0])—Input........................................................... 2-9

2.2.1.4 Parity (PAR) ............................................................................................. 2-10

2.2.1.4.1 Parity (PAR)—Output.......................................................................... 2-10

2.2.1.4.2 Parity (PAR)—Input............................................................................. 2-10

2.2.1.5 Command/Byte Enable (C/BE

2.2.1.5.1 Command/Byte Enable (C/BE

2.2.1.5.2 Command/Byte Enable (C/BE

2.2.1.6 Device Select (DEVSEL

2.2.1.6.1 Device Select (DEVSEL

2.2.1.6.2 Device Select (DEVSEL

2.2.1.7 Frame (FRAME

2.2.1.7.1 Frame (FRAME

2.2.1.7.2 Frame (FRAME

2.2.1.8 Initiator Ready (IRD

2.2.1.8.1 Initiator Ready (IRD

2.2.1.8.2 Initiator Ready (IRD

2.2.1.9 Lock (LOCK

2.2.1.10 Target Ready (TRD

2.2.1.10.1 Target Ready (TRD

2.2.1.10.2 Target Ready (TRD

2.2.1.11 Parity Error (PERR

2.2.1.11.1 Parity Error (PERR

2.2.1.11.2 Parity Error (PERR

)—Input............................................................................... 2-13

[4:0])—Input......................................................... 2-8

[4:0])—Internal Arbiter Enabled ...................... 2-8

[4:0])—Internal Arbiter Disabled ..................... 2-8

[4:0])—Output.......................................................... 2-8

[4:0])—Internal Arbiter Enabled.......................... 2-8

[4:0])—Internal Arbiter Disabled......................... 2-9

[3:0])......................................................... 2-10

[3:0])—Output ..................................... 2-10

[3:0])—Input........................................ 2-11

) ......................................................................... 2-11

)—Output...................................................... 2-11

)—Input......................................................... 2-12

)....................................................................................... 2-12

)—Output ................................................................... 2-12

)—Input...................................................................... 2-12

Y)............................................................................. 2-12

Y)—Output.......................................................... 2-12

Y)—Input............................................................. 2-13

Y) .............................................................................. 2-13

Y)—Output........................................................... 2-13

Y)—Input.............................................................. 2-14

).................................................................................. 2-14

)—Output .............................................................. 2-14

)—Input................................................................. 2-14

MPC8240 Integrated Processor User’s Manual

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2.2.1.12 System Error (SERR) ............................................................................... 2-14

2.2.1.12.1 System Error (SERR

2.2.1.12.2 System Error (SERR

2.2.1.13 Stop (ST

2.2.1.13.1 Stop (ST

2.2.1.13.2 Stop (ST

OP).............................................................................................. 2-15

OP)—Output .......................................................................... 2-15

OP)—Input............................................................................. 2-15

2.2.1.14 Interrupt Request (INT

2.2.1.15 ID Select (IDSEL

)—Output ............................................................ 2-15

)—Input............................................................... 2-15

A)—Output........................................................... 2-15

)—Input........................................................................ 2-16

2.2.2 Memory Interface Signals............................................................................. 2-16

2.2.2.1 Row Address Strobe (RAS

2.2.2.2 Column Address Strobe (CAS

2.2.2.3 SDRAM Command Select (CS

[0:7])—Output............................................... 2-16

[0:7])—Output.......................................... 2-17

[0:7])—Output ........................................ 2-17

2.2.2.4 SDRAM Data Input/Output Mask (DQM[0:7])—Output........................ 2-17

2.2.2.5 Write Enable (WE

)—Output.................................................................... 2-18

2.2.2.6 SDRAM Address (SDMA[11:0])—Output.............................................. 2-18

2.2.2.7 SDRAM Address 12 (SDMA12)—Output............................................... 2-18

2.2.2.8 SDRAM Internal Bank Select 0–1 (SDBA0, SDBA1)—Output ............. 2-18

2.2.2.9 Memory Data Bus (MDH[0:31], MDL[0:31]) ......................................... 2-19

2.2.2.9.1 Memory Data Bus (MDH[0:31], MDL[0:31])—Output...................... 2-20

2.2.2.9.2 Memory Data Bus (MDH[0:31], MDL[0:31])—Input......................... 2-20

2.2.2.10 Data Parity/ECC (PAR[0:7]) .................................................................... 2-20

2.2.2.10.1 Data Parity (PAR[0:7])—Output.......................................................... 2-20

2.2.2.10.2 Data Parity (PAR[0:7])—Input............................................................. 2-21

2.2.2.11 ROM Address 19:12 (AR[19:12])—Output............................................. 2-21

2.2.2.12 SDRAM Clock Enable (CKE)—Output................................................... 2-21

2.2.2.13 SDRAM Row Address Strobe (SDRAS

2.2.2.14 SDRAM Column Address Strobe (SDCAS

2.2.2.15 ROM Bank 0 Select (RCS0

2.2.2.16 ROM Bank 1 Select (RCS1

2.2.2.17 Flash Output Enable (FOE

2.2.2.18 Address Strobe (AS

)—Output...................................................... 2-22

)—Output....................................................... 2-23

)—Output.................................................................. 2-23

)—Output .................................. 2-21

)—Output............................. 2-22

2.2.3 EPIC Control Signals.................................................................................... 2-23

2.2.3.1 Discrete Interrupt 0:4 (IRQ[0:4])—Input................................................. 2-23

2.2.3.2 Serial Interrupt Mode Signals................................................................... 2-24

2.2.3.2.1 Serial Interrupt Stream (S_INT)—Input............................................... 2-24

2.2.3.2.2 Serial Interrupt Clock (S_CLK)—Output ............................................ 2-24

2.2.3.2.3 Serial Interrupt Reset (S_RST)—Output.............................................. 2-24

2.2.3.2.4 Serial Interrupt Frame (S_FRAME

2.2.3.3 Local Interrupt (L_INT

2.2.4 I

C Interface Control Signals........................................................................ 2-25

)—Output ............................................................ 2-24

)—Output...................................... 2-24

2.2.4.1 Serial Data (SDA)..................................................................................... 2-25

2.2.4.1.1 Serial Data (SDA)—Output.................................................................. 2-25

2.2.4.1.2 Serial Data (SDA)—Input .................................................................... 2-25

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2.2.4.2 Serial Clock (SCL) ................................................................................... 2-25

2.2.4.2.1 Serial Clock (SCL)—Output ................................................................ 2-25

2.2.4.2.2 Serial Clock (SCL)—Input................................................................... 2-25

2.2.5 System Control and Power Management Signals......................................... 2-25

2.2.5.1 Hard Reset ................................................................................................ 2-26

2.2.5.1.1 Hard Reset (Processor) (HRST_CPU)—Input..................................... 2-26

2.2.5.1.2 Hard Reset (Peripheral Logic) (HRST_CTRL)—Input ....................... 2-26

2.2.5.2 Soft Reset (SRESET)—Input ................................................................... 2-26

2.2.5.3 Machine Check (MCP)—Output.............................................................. 2-27

2.2.5.4 Nonmaskable Interrupt (NMI)—Input ..................................................... 2-27

2.2.5.5 System Management Interrupt (SMI)—Input .......................................... 2-28

2.2.5.6 Checkstop In (CHKSTOP_IN)—Input..................................................... 2-28

2.2.5.7 Time Base Enable (TBEN)—Input .......................................................... 2-28

2.2.5.8 Quiesce Acknowledge (QACK)—Output................................................ 2-28

2.2.5.9 Watchpoint Trigger Signals...................................................................... 2-29

2.2.5.9.1 Watchpoint Trigger In (TRIG_IN)—Input........................................... 2-29

2.2.5.9.2 Watchpoint Trigger Out (TRIG_OUT)—Output ................................. 2-29

2.2.5.10 Debug Signals........................................................................................... 2-29

2.2.5.10.1 Memory Address Attributes (MAA[0:2])—Output.............................. 2-30

2.2.5.10.2 PCI Address Attributes (PMAA[0:2])—Output................................... 2-30

2.2.5.10.3 Debug Address (DA[0:15])—Output ................................................... 2-30

2.2.5.10.4 Memory Interface Valid (MIV)—Output............................................. 2-31

2.2.6 Test and Configuration Signals..................................................................... 2-31

2.2.6.1 PLL Configuration (PLL_CFG[0:4])—Input........................................... 2-31

2.2.6.2 JTAG Test Clock (TCK)—Input.............................................................. 2-31

2.2.6.3 JTAG Test Data Input (TDI)—Input........................................................ 2-32

2.2.6.4 JTAG Test Data Output (TDO)—Output................................................. 2-32

2.2.6.5 JTAG Test Mode Select (TMS)—Input ................................................... 2-32

2.2.6.6 JTAG Test Reset (TRST)—Input............................................................. 2-32

2.2.7 Clock Signals................................................................................................ 2-32

2.2.7.1 System Clock Input (OSC_IN)—Input .................................................... 2-33

2.2.7.2 PCI Clock (PCI_CLK[0:4])—Output....................................................... 2-33

2.2.7.3 PCI Clock Synchronize Out (PCI_SYNC_OUT)—Output...................... 2-33

2.2.7.4 PCI Feedback Clock (PCI_SYNC_IN)—Input........................................ 2-33

2.2.7.5 SDRAM Clock Outputs (SDRAM_CLK[0:3])—Output......................... 2-33

2.2.7.6 SDRAM Clock Synchronize Out (SDRAM_SYNC_OUT)—Output...... 2-33

2.2.7.7 SDRAM Feedback Clock (SDRAM_SYNC_IN)—Input........................ 2-33

2.2.7.8 Debug Clock (CKO)—Output.................................................................. 2-34

2.3 Clocking ........................................................................................................... 2-34

2.3.1 Clocking Method .......................................................................................... 2-34

2.3.2 DLL Operation and Locking......................................................................... 2-35

2.3.3 Clock Synchronization.................................................................................. 2-36

2.3.4 Clocking System Solution Examples............................................................ 2-37

2.4 Configuration Signals Sampled at Reset........................................................... 2-38

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MPC8240 Integrated Processor User’s Manual

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Chapter 3

Address Maps

3.1 Address Map B ................................................................................................... 3-1

3.2 Address Map B Options...................................................................................... 3-7

3.2.1 Processor Compatibility Hole and Alias Space.............................................. 3-7

3.2.2 PCI Compatibility Hole and Alias Space ....................................................... 3-9

3.3 Address Translation.......................................................................................... 3-11

3.3.1 Inbound PCI Address Translation................................................................. 3-11

3.3.2 Outbound PCI Address Translation.............................................................. 3-13

3.3.3 Address Translation Registers...................................................................... 3-14

3.3.3.1 Local Memory Base Address Register (LMBAR) ................................... 3-15

3.3.3.2 Inbound Translation Window Register (ITWR)....................................... 3-15

3.3.3.3 Outbound Memory Base Address Register (OMBAR)............................ 3-16

3.3.3.4 Outbound Translation Window Register (OTWR)................................... 3-17

3.4 Embedded Utilities Memory Block (EUMB)................................................... 3-18

3.4.1 Processor Core Control and Status Registers ............................................... 3-18

3.4.2 Peripheral Control and Status Registers ....................................................... 3-19

Chapter 4

Configuration Registers

4.1 Configuration Register Access ........................................................................... 4-1

4.1.1 Configuration Register Access in Little-Endian Mode................................... 4-2

4.1.2 Configuration Register Access in Big-Endian Mode ..................................... 4-3

4.1.3 Configuration Register Summary................................................................... 4-5

4.1.3.1 Processor-Accessible Configuration Registers........................................... 4-5

4.1.3.2 PCI-Accessible Configuration Registers.................................................... 4-8

4.2 PCI Interface Configuration Registers.............................................................. 4-10

4.2.1 PCI Command Register—Offset 0x04......................................................... 4-11

4.2.2 PCI Status Register—Offset 0x06................................................................ 4-12

4.2.3 Programming Interface—Offset 0x09.......................................................... 4-14

4.2.4 PCI Base Class Code—Offset 0x0B............................................................. 4-14

4.2.5 PCI Cache Line Size—Offset 0x0C ............................................................. 4-14

4.2.6 Latency Timer—Offset 0x0D....................................................................... 4-14

4.2.7 PCI Base Address Registers—LMBAR and PCSRBAR ............................. 4-15

4.2.8 PCI Interrupt Line—Offset 0x3C................................................................. 4-16

4.2.9 PCI Arbiter Control Register (PACR)—Offset 0x46................................... 4-16

4.3 Peripheral Logic Power Management Configuration Registers (PMCRs)....... 4-17

4.3.1 Power Management Configuration Register 1 (PMCR1)—Offset 0x70...... 4-17

4.3.2 Power Management Configuration Register 2 (PMCR2)—Offset 0x72...... 4-18

4.4 Output/Clock Driver and Miscellaneous I/O Control Registers....................... 4-20

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4.5 Embedded Utilities Memory Block Base Address Register—0x78................. 4-22

4.6 Memory Interface Configuration Registers...................................................... 4-23

4.6.1 Memory Boundary Registers........................................................................ 4-23

4.6.2 Memory Bank Enable Register—0xA0........................................................ 4-27

4.6.3 Memory Page Mode Register—0xA3 .......................................................... 4-28

4.7 Processor Interface Configuration Registers .................................................... 4-29

4.8 Error Handling Registers .................................................................................. 4-33

4.8.1 ECC Single-Bit Error Registers.................................................................... 4-33

4.8.2 Error Enabling and Detection Registers ....................................................... 4-34

4.9 Address Map B Options Register—0xE0......................................................... 4-41

4.10 Memory Control Configuration Registers........................................................ 4-42

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Chapter 5

PowerPC Processor Core

5.1 Overview............................................................................................................. 5-1

5.2 PowerPC Processor Core Features...................................................................... 5-3

5.2.1 Instruction Unit............................................................................................... 5-5

5.2.2 Instruction Queue and Dispatch Unit.............................................................. 5-6

5.2.3 Branch Processing Unit (BPU)....................................................................... 5-6

5.2.4 Independent Execution Units.......................................................................... 5-6

5.2.4.1 Integer Unit (IU)......................................................................................... 5-7

5.2.4.2 Floating-Point Unit (FPU).......................................................................... 5-7

5.2.4.3 Load/Store Unit (LSU) ............................................................................... 5-7

5.2.4.4 System Register Unit (SRU)....................................................................... 5-8

5.2.5 Completion Unit ............................................................................................. 5-8

5.2.6 Memory Subsystem Support........................................................................... 5-8

5.2.6.1 Memory Management Units (MMUs)........................................................ 5-8

5.2.6.2 Cache Units................................................................................................. 5-9

5.2.6.3 Peripheral Logic Bus Interface................................................................... 5-9

5.2.6.3.1 Peripheral Logic Bus Protocol................................................................ 5-9

5.2.6.3.2 Peripheral Logic Bus Data Transfers...................................................... 5-9

5.2.6.3.3 Peripheral Logic Bus Frequency .......................................................... 5-10

5.3 Programming Model......................................................................................... 5-10

5.3.1 Register Set................................................................................................... 5-10

5.3.1.1 PowerPC Register Set............................................................................... 5-11

5.3.1.2 MPC8240-Specific Registers.................................................................... 5-13

5.3.1.2.1 Hardware Implementation-Dependent Register 0 (HID0) ................... 5-13

5.3.1.2.2 Hardware Implementation-Dependent Register 1 (HID1) ................... 5-16

5.3.1.2.3 Hardware Implementation-Dependent Register 2 (HID2) ................... 5-17

5.3.1.2.4 Processor Version Register (PVR) ....................................................... 5-17

5.3.2 PowerPC Instruction Set and Addressing Modes......................................... 5-18

MPC8240 Integrated Processor User’s Manual

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5.3.2.1 Calculating Effective Addresses............................................................... 5-18

5.3.2.2 PowerPC Instruction Set........................................................................... 5-18

5.3.2.3 MPC8240 Implementation-Specific Instruction Set................................. 5-20

5.4 Cache Implementation...................................................................................... 5-20

5.4.1 PowerPC Cache Model................................................................................. 5-20

5.4.2 MPC8240 Implementation-Specific Cache Implementation........................ 5-21

5.4.2.1 Data Cache................................................................................................ 5-21

5.4.2.2 Instruction Cache...................................................................................... 5-23

5.4.2.3 Cache Locking.......................................................................................... 5-23

5.4.2.3.1 Entire Cache Locking........................................................................... 5-23

5.4.2.3.2 Way Locking ........................................................................................ 5-23

5.4.3 Cache Coherency.......................................................................................... 5-24

5.4.3.1 CCU Responses to Processor Transactions.............................................. 5-24

5.4.3.2 Processor Responses to PCI-to-Memory Transactions............................. 5-25

5.5 Exception Model............................................................................................... 5-26

5.5.1 PowerPC Exception Model........................................................................... 5-26

5.5.2 MPC8240 Implementation-Specific Exception Model................................. 5-27

5.5.3 Exception Priorities....................................................................................... 5-30

5.6 Memory Management....................................................................................... 5-30

5.6.1 PowerPC MMU Model................................................................................. 5-30

5.6.2 MPC8240 Implementation-Specific MMU Features.................................... 5-31

5.7 Instruction Timing ............................................................................................ 5-32

5.8 Differences between the MPC8240 Core

and the PowerPC 603e Microprocessor........................................................ 5-34

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Chapter 6

MPC8240 Memory Interface

6.1 Memory Interface Signal Summary.................................................................... 6-3

6.2 SDRAM Interface Operation.............................................................................. 6-6

6.2.1 Supported SDRAM Organizations ................................................................. 6-9

6.2.2 SDRAM Address Multiplexing.................................................................... 6-10

6.2.3 SDRAM Memory Data Interface.................................................................. 6-13

6.2.4 SDRAM Power-On Initialization ................................................................. 6-16

6.2.5 MPC8240 Interface Functionality for JEDEC SDRAMs............................. 6-17

6.2.6 SDRAM Burst and Single-Beat Transactions .............................................. 6-18

6.2.7 SDRAM Page Mode..................................................................................... 6-19

6.2.7.1 SDRAM Paging in Sleep Mode................................................................ 6-21

6.2.8 SDRAM Interface Timing............................................................................ 6-21

6.2.8.1 SDRAM Mode-Set Command Timing..................................................... 6-26

6.2.9 SDRAM Parity and RMW Parity ................................................................. 6-26

6.2.9.1 RMW Parity Latency Considerations....................................................... 6-27

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6.2.10 SDRAM In-Line ECC .................................................................................. 6-27

6.2.11 SDRAM Registered DIMM Mode ............................................................... 6-29

6.2.12 SDRAM Refresh........................................................................................... 6-31

6.2.12.1 SDRAM Refresh Timing.......................................................................... 6-33

6.2.12.2 SDRAM Refresh and Power Saving Modes............................................. 6-33

6.2.13 Processor-to-SDRAM Transaction Examples.............................................. 6-36

6.2.14 PCI-to-SDRAM Transaction Examples........................................................ 6-42

6.3 FPM or EDO DRAM Interface Operation........................................................ 6-46

6.3.1 Supported FPM or EDO DRAM Organizations........................................... 6-48

6.3.2 FPM or EDO DRAM Address Multiplexing................................................ 6-50

6.3.2.1 Row Bit Multiplexing During The Row Phase (RAS)............................. 6-50

6.3.2.2 Column Bit Multiplexing During the Column Phase (CAS).................... 6-51

6.3.2.3 Graphical View of the Row and Column Bit Multiplexing...................... 6-51

6.3.3 FPM or EDO Memory Data Interface .......................................................... 6-54

6.3.4 FPM or EDO DRAM Initialization .............................................................. 6-55

6.3.5 FPM or EDO DRAM Interface Timing........................................................ 6-56

6.3.6 DMA Burst Wrap.......................................................................................... 6-61

6.3.7 FPM or EDO DRAM Page Mode Retention................................................ 6-61

6.3.8 FPM or EDO DRAM Parity and RMW Parity............................................. 6-61

6.3.8.1 RMW Parity Latency Considerations....................................................... 6-62

6.3.9 FPM or EDO ECC........................................................................................ 6-62

6.3.9.1 FPM or EDO DRAM Interface Timing with ECC................................... 6-64

6.3.10 FPM or EDO DRAM Refresh ...................................................................... 6-66

6.3.10.1 FPM or EDO Refresh Timing................................................................... 6-66

6.3.11 FPM or EDO DRAM Power Saving Modes................................................. 6-67

6.3.11.1 Configuration Parameters for DRAM Power Saving Modes ................... 6-67

6.3.11.2 DRAM Self-Refresh in Sleep Mode......................................................... 6-68

6.3.12 PCI-to-DRAM Transaction Examples.......................................................... 6-69

6.4 ROM/Flash Interface Operation ....................................................................... 6-73

6.4.1 ROM/Flash Address Multiplexing................................................................ 6-77

6.4.2 64 or 32-Bit ROM/Flash Interface Timing................................................... 6-78

6.4.3 8-Bit ROM/Flash Interface Timing .............................................................. 6-81

6.4.4 ROM/Flash Interface Write Operations........................................................ 6-83

6.4.5 ROM/Flash Interface Write Timing ............................................................. 6-84

6.4.6 PCI-to-ROM/Port X Transaction Example................................................... 6-84

6.4.7 Port X Interface............................................................................................. 6-89

Title

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Chapter 7

PCI Bus Interface

7.1 PCI Interface Overview ...................................................................................... 7-1

7.1.1 The MPC8240 as a PCI Initiator..................................................................... 7-2

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7.1.2 The MPC8240 as a PCI Target....................................................................... 7-3

7.1.3 PCI Signal Output Hold Timing..................................................................... 7-3

7.2 PCI Bus Arbitration ............................................................................................ 7-4

7.2.1 Internal Arbitration for PCI Bus Access......................................................... 7-4

7.2.1.1 Processor-Initiated Transactions to PCI Bus.............................................. 7-5

7.2.1.2 DMA-Initiated Transactions to the PCI Bus .............................................. 7-5

7.2.2 PCI Bus Arbiter Operation ............................................................................. 7-6

7.2.3 PCI Bus Parking.............................................................................................. 7-7

7.2.4 Power-Saving Modes and the PCI Arbiter ..................................................... 7-8

7.2.5 Broken Master Lock-Out................................................................................ 7-8

7.3 PCI Bus Protocol................................................................................................ 7-8

7.3.1 Basic Transfer Control.................................................................................... 7-9

7.3.2 PCI Bus Commands........................................................................................ 7-9

7.3.3 Addressing.................................................................................................... 7-11

7.3.3.1 Memory Space Addressing....................................................................... 7-12

7.3.3.2 I/O Space Addressing ............................................................................... 7-12

7.3.3.3 Configuration Space Addressing.............................................................. 7-13

7.3.4 Device Selection........................................................................................... 7-13

7.3.5 Byte Alignment............................................................................................. 7-13

7.3.6 Bus Driving and Turnaround........................................................................ 7-14

7.4 PCI Bus Transactions........................................................................................ 7-14

7.4.1 PCI Read Transactions.................................................................................. 7-14

7.4.2 PCI Write Transactions................................................................................. 7-16

7.4.3 Transaction Termination............................................................................... 7-17

7.4.3.1 Master-Initiated Termination.................................................................... 7-17

7.4.3.2 Target-Initiated Termination .................................................................... 7-18

7.4.4 Fast Back-to-Back Transactions................................................................... 7-21

7.4.5 Configuration Cycles.................................................................................... 7-21

7.4.5.1 The PCI Configuration Space Header ...................................................... 7-21

7.4.5.2 Accessing the PCI Configuration Space................................................... 7-23

7.4.5.2.1 Type 0 Configuration Translation ........................................................ 7-25

7.4.5.2.2 Type 1 Configuration Translation ........................................................ 7-27

7.4.6 Other Bus Transactions................................................................................. 7-27

7.4.6.1 Interrupt-Acknowledge Transactions ....................................................... 7-27

7.4.6.2 Special-Cycle Transactions ...................................................................... 7-28

7.5 Exclusive Access .............................................................................................. 7-29

7.5.1 Starting an Exclusive Access........................................................................ 7-29

7.5.2 Continuing an Exclusive Access................................................................... 7-29

7.5.3 Completing an Exclusive Access.................................................................. 7-30

7.5.4 Attempting to Access a Locked Target......................................................... 7-30

7.5.5 Exclusive Access and the MPC8240............................................................ 7-30

7.6 PCI Error Functions.......................................................................................... 7-30

7.6.1 PCI Parity...................................................................................................... 7-31

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7.6.2 Error Reporting............................................................................................. 7-32

7.7 PCI Host and Agent Modes .............................................................................. 7-32

7.7.1 PCI Initialization Options............................................................................. 7-32

7.7.2 Accessing the MPC8240 Configuration Space............................................. 7-33

7.7.3 PCI Configuration Cycle Retry Capability in Agent Mode.......................... 7-34

7.7.4 PCI Address Translation Support................................................................. 7-34

7.7.4.1 Inbound PCI Address Translation ............................................................ 7-34

7.7.4.2 Outbound PCI Address Translation.......................................................... 7-34

7.7.4.3 Initialization Code Translation in Agent Mode........................................ 7-35

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Chapter 8

DMA Controller

8.1 DMA Overview .................................................................................................. 8-1

8.2 DMA Register Summary .................................................................................... 8-2

8.3 DMA Operation.................................................................................................. 8-3

8.3.1 DMA Direct Mode.......................................................................................... 8-4

8.3.2 DMA Chaining Mode..................................................................................... 8-5

8.3.2.1 Basic Chaining Mode Initialization............................................................ 8-5

8.3.2.2 Periodic DMA Feature................................................................................ 8-6

8.3.3 DMA Operation Flow..................................................................................... 8-7

8.3.4 DMA Coherency............................................................................................. 8-8

8.3.5 DMA Performance.......................................................................................... 8-8

8.4 DMA Transfer Types.......................................................................................... 8-9

8.4.1 PCI to PCI....................................................................................................... 8-9

8.4.2 PCI to Local Memory..................................................................................... 8-9

8.4.3 Local Memory to PCI..................................................................................... 8-9

8.4.4 Local Memory to Local Memory.................................................................... 8-9

8.5 Address Map Interactions................................................................................. 8-10

8.5.1 Attempted Writes to Local ROM/Port X Space ........................................... 8-10

8.5.2 Host Mode Interactions................................................................................. 8-10

8.5.2.1 PCI Master Abort when PCI Bus Specified for Lower 2-Gbyte Space.... 8-10

8.5.2.2 Address Alias to Lower 2-Gbyte Space.................................................... 8-10

8.5.2.3 Attempted Reads from ROM on the PCI Bus—Host Mode..................... 8-11

8.5.2.4 Attempted Reads from ROM on the Memory Bus................................... 8-11

8.5.3 Agent Mode Interactions .............................................................................. 8-11

8.5.3.1 Agent Mode DMA Transfers for PCI....................................................... 8-11

8.5.3.2 Accesses to Outbound Memory Window

that Overlaps 0xFE00_00 – 0xFEEF_FFFF .........................................8-11

8.5.3.3 Attempted Accesses to Local ROM when ROM is on PCI...................... 8-11

8.5.3.4 Attempted Access to ROM on the PCI Bus—Agent Mode ..................... 8-12

8.6 DMA Descriptors for Chaining Mode.............................................................. 8-12

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8.6.1 Descriptors in Big-Endian Mode.................................................................. 8-14

8.6.2 Descriptors in Little-Endian Mode............................................................... 8-14

8.7 DMA Register Descriptions.............................................................................. 8-15

8.7.1 DMA Mode Registers (DMRs)..................................................................... 8-15

8.7.2 DMA Status Registers (DSRs) ..................................................................... 8-18

8.7.3 Current Descriptor Address Registers (CDARs).......................................... 8-19

8.7.4 Source Address Registers (SARs) ................................................................ 8-20

8.7.5 Destination Address Registers (DARs) ........................................................ 8-21

8.7.6 Byte Count Registers (BCRs)....................................................................... 8-21

8.7.7 DAR and BCR Values—Double PCI Write................................................. 8-22

8.7.8 Next Descriptor Address Registers (NDARs) .............................................. 8-23

Chapter 9

Message Unit (with I

9.1 Message Unit (MU) Overview............................................................................ 9-1

9.2 Message and Doorbell Register Programming Model........................................ 9-2

9.2.1 Message and Doorbell Register Summary...................................................... 9-2

9.2.2 Message Register Descriptions....................................................................... 9-3

9.2.3 Doorbell Register Descriptions....................................................................... 9-3

9.3 I

9.3.1 PCI Configuration Identification.................................................................... 9-5

9.3.2 I

9.3.3 FIFO Descriptions........................................................................................... 9-6

9.3.3.1 Inbound FIFOs............................................................................................ 9-7

9.3.3.1.1 Inbound Free_List FIFO......................................................................... 9-8

9.3.3.1.2 Inbound Post_List FIFO......................................................................... 9-8

9.3.3.2 Outbound FIFOs......................................................................................... 9-8

9.3.3.2.1 Outbound Free_List FIFO ...................................................................... 9-8

9.3.3.2.2 Outbound Post_List FIFO ...................................................................... 9-9

9.3.4 I

9.3.4.1 PCI-Accessible I

9.3.4.1.1 Outbound Message Interrupt Status Register (OMISR)......................... 9-9

9.3.4.1.2 Outbound Message Interrupt Mask Register (OMIMR) ...................... 9-10

9.3.4.1.3 Inbound FIFO Queue Port Register (IFQPR)....................................... 9-11

9.3.4.1.4 Outbound FIFO Queue Port Register (OFQPR)................................... 9-12

9.3.4.2 Processor-Accessible I

9.3.4.2.1 Inbound Message Interrupt Status Register (IMISR)........................... 9-12

9.3.4.2.2 Inbound Message Interrupt Mask Register (IMIMR)........................... 9-14

9.3.4.2.3 Inbound Free_FIFO Head Pointer Register (IFHPR)........................... 9-15

9.3.4.2.4 Inbound Free_FIFO Tail Pointer Register (IFTPR) ............................. 9-16

9.3.4.2.5 Inbound Post_FIFO Head Pointer Register (IPHPR)........................... 9-16

O Interface ....................................................................................................... 9-5

O Register Summary.................................................................................... 9-5

O Register Descriptions............................................................................... 9-9

O Registers..................................................................... 9-9

O Registers ......................................................... 9-12

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9.3.4.2.6 Inbound Post_FIFO Tail Pointer Register (IPTPR) ............................. 9-17

9.3.4.2.7 Outbound Free_FIFO Head Pointer Register (OFHPR)....................... 9-18

9.3.4.2.8 Outbound Free_FIFO Tail Pointer Register (OFTPR)......................... 9-18

9.3.4.2.9 Outbound Post_FIFO Head Pointer Register (OPHPR)....................... 9-19

9.3.4.2.10 Outbound Post_FIFO Tail Pointer Register (OPTPR) ......................... 9-19

9.3.4.2.11 Messaging Unit Control Register (MUCR).......................................... 9-20

9.3.4.2.12 Queue Base Address Register (QBAR)................................................ 9-21

10.1 I2C Interface Overview..................................................................................... 10-1

10.1.1 I2C Unit Features.......................................................................................... 10-1

10.1.2 I2C Interface Signal Summary...................................................................... 10-2

10.1.3 I2C Register Summary.................................................................................. 10-2

10.1.4 I2C Block Diagram ....................................................................................... 10-3

10.2 I2C Protocol ...................................................................................................... 10-3

10.2.1 START Condition......................................................................................... 10-4

10.2.2 Slave Address Transmission......................................................................... 10-4

10.2.3 Data Transfer ................................................................................................ 10-5

10.2.4 Repeated START Condition......................................................................... 10-5

10.2.5 STOP Condition............................................................................................ 10-5

10.2.6 Arbitration Procedure ................................................................................... 10-5

10.2.7 Clock Synchronization.................................................................................. 10-6

10.2.8 Handshaking ................................................................................................. 10-7

10.2.9 Clock Stretching ........................................................................................... 10-7

10.3 I2C Register Descriptions ................................................................................. 10-7

10.3.1 I2C Address Register (I2CADR) .................................................................. 10-7

10.3.2 I2C Frequency Divider Register (I2CFDR).................................................. 10-8

10.3.3 I2C Control Register (I2CCR) .................................................................... 10-10

10.3.4 I2C Status Register (I2CSR)....................................................................... 10-11

10.3.5 I2C Data Register (I2CDR)......................................................................... 10-13

10.4 Programming Guidelines................................................................................ 10-13

10.4.1 Initialization Sequence................................................................................ 10-14

10.4.2 Generation of START................................................................................. 10-14

10.4.3 Post-Transfer Software Response............................................................... 10-14

10.4.4 Generation of STOP.................................................................................... 10-15

10.4.5 Generation of Repeated START................................................................. 10-15

10.4.6 Generation of SCK when SDA Low........................................................... 10-15

10.4.7 Slave Mode Interrupt Service Routine........................................................ 10-16

10.4.7.1 Slave Transmitter and Received Acknowledge...................................... 10-16

10.4.7.2 Loss of Arbitration and Forcing of Slave Mode..................................... 10-16

10.4.8 Interrupt Service Routine Flowchart........................................................... 10-16

Title

Chapter 10

C Interface

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Chapter 11

Embedded Programmable Interrupt Controller (EPIC) Unit

11.1 EPIC Unit Overview......................................................................................... 11-1

11.1.1 EPIC Features Summary............................................................................... 11-2

11.1.2 EPIC Interface Signal Description................................................................ 11-2

11.1.3 EPIC Block Diagram.................................................................................... 11-3

11.2 EPIC Register Summary................................................................................... 11-4

11.3 EPIC Unit Interrupt Protocol............................................................................ 11-7

11.3.1 Interrupt Source Priority............................................................................... 11-7

11.3.2 Processor Current Task Priority.................................................................... 11-7

11.3.3 Interrupt Acknowledge................................................................................. 11-8

11.3.4 Nesting of Interrupts..................................................................................... 11-8

11.3.5 Spurious Vector Generation.......................................................................... 11-8

11.3.6 Internal Block Diagram Description............................................................. 11-9

11.3.6.1 Interrupt Pending Register (IPR)—Non-programmable .......................... 11-9

11.3.6.2 Interrupt Selector (IS)............................................................................... 11-9

11.3.6.3 Interrupt Request Register (IRR)............................................................ 11-10

11.3.6.4 In-Service Register (ISR) ....................................................................... 11-10

11.4 EPIC Pass-Through Mode .............................................................................. 11-10

11.5 EPIC Direct Interrupt Mode............................................................................ 11-11

11.6 EPIC Serial Interrupt Interface ....................................................................... 11-11

11.6.1 Sampling of Serial Interrupts...................................................................... 11-11

11.6.2 Serial Interrupt Timing Protocol................................................................. 11-12

11.6.3 Edge/Level Sensitivity of Serial Interrupts................................................. 11-12

11.7 EPIC Timers.................................................................................................... 11-13

11.8 Programming Guidelines................................................................................ 11-13

11.9 Register Definitions........................................................................................ 11-16

11.9.1 Feature Reporting Register (FRR).............................................................. 11-16

11.9.2 Global Configuration Register (GCR)........................................................ 11-16

11.9.3 EPIC Interrupt Configuration Register (EICR).......................................... 11-17

11.9.4 EPIC Vendor Identification Register (EVI)................................................ 11-18

11.9.5 Processor Initialization Register (PI).......................................................... 11-19

11.9.6 Spurious Vector Register (SVR)................................................................. 11-19

11.9.7 Global Timer Registers............................................................................... 11-20

11.9.7.1 Timer Frequency Reporting Register (TFRR)........................................ 11-20

11.9.7.2 Global Timer Current Count Registers (GTCCRs) ................................ 11-21

11.9.7.3 Global Timer Base Count Registers (GTBCRs)..................................... 11-21

11.9.7.4 Global Timer Vector/Priority Registers (GTVPRs) ............................... 11-22

11.9.7.5 Global Timer Destination Registers (GTDRs) ....................................... 11-23

11.9.8 External (Direct and Serial), and Internal Interrupt Registers.................... 11-24

11.9.8.1 Direct & Serial Interrupt Vector/Priority Registers (IVPRs, SVPRs).... 11-24

11.9.8.2 Direct & Serial Interrupt Destination Registers (IDRs, SDRs) .............. 11-25

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11.9.8.3 Internal (I2C, DMA, MU) Interrupt Vector/Priority Registers (IIVPRs) 11-26

11.9.8.4 Internal (I

11.9.9 Processor-Related Registers ....................................................................... 11-27

11.9.9.1 Processor Current Task Priority Register (PCTPR) ............................... 11-27

11.9.9.2 Processor Interrupt Acknowledge Register (IACK)............................... 11-27

11.9.10 Processor End-of-Interrupt Register (EOI)................................................. 11-28

C, DMA or MU) Interrupt Destination Registers (IIDRs).... 11-26

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Chapter 12

Central Control Unit

12.1 Internal Buffers................................................................................................. 12-1

12.1.1 Processor Core/Local Memory Buffers........................................................ 12-2

12.1.2 Processor/PCI Buffers................................................................................... 12-3

12.1.2.1 Processor-to-PCI-Read Buffer (PRPRB).................................................. 12-4

12.1.2.2 Processor-to-PCI-Write Buffers (PRPWBs)............................................. 12-5

12.1.3 PCI/Local Memory Buffers.......................................................................... 12-6

12.1.3.1 PCI to Local Memory Read Buffering ..................................................... 12-7

12.1.3.1.1 PCI-to-Local-Memory-Read Buffers (PCMRBs)................................. 12-7

12.1.3.1.2 Speculative PCI Reads from Local Memory........................................ 12-8

12.1.3.2 PCI-to-Local-Memory-Write Buffers (PCMWBs)................................... 12-8

12.2 Internal Arbitration ........................................................................................... 12-9

12.2.1 Arbitration Between PCI and DMA Accesses to Local Memory................. 12-9

12.2.1.1 DMA Transaction Boundaries for Memory/Memory Transfers ............ 12-10

12.2.1.2 DMA Transaction Boundaries for Memory to PCI Transfers................ 12-10

12.2.1.3 DMA Transaction Boundaries for PCI–Memory Transfers ................... 12-11

12.2.1.4 PCI and DMA Reads from Slow Memory/Port X.................................. 12-11

12.2.2 Internal Arbitration Priorities...................................................................... 12-11

12.2.3 Guaranteeing Minimum PCI Access Latency to Local Memory ............... 12-13

Chapter 13

Error Handling

13.1 Overview........................................................................................................... 13-1

13.1.1 Error Handling Block Diagram..................................................................... 13-2

13.1.2 Priority of Externally Generated Errors and Exceptions .............................. 13-2

13.2 Exceptions and Error Signals............................................................................ 13-3

13.2.1 System Reset................................................................................................. 13-3

13.2.2 Processor Core Error Signal (mcp) .............................................................. 13-3

13.2.3 PCI Bus Error Signals................................................................................... 13-4

13.2.3.1 System Error (SERR

13.2.3.2 Parity Error (PERR

13.2.3.3 Nonmaskable Interrupt (NMI).................................................................. 13-5

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13.3 Error Reporting................................................................................................. 13-5

13.3.1 Processor Interface Errors............................................................................. 13-6

13.3.1.1 Processor Transaction Error ..................................................................... 13-6

13.3.1.2 Flash Write Error ...................................................................................... 13-7

13.3.1.3 Processor Write Parity Error..................................................................... 13-7

13.3.2 Memory Interface Errors .............................................................................. 13-7

13.3.2.1 Memory Read Data Parity Error............................................................... 13-8

13.3.2.2 Memory ECC Error .................................................................................. 13-8

13.3.2.3 Memory Select Error ................................................................................ 13-9

13.3.2.4 Memory Refresh Overflow Error ............................................................. 13-9

13.3.3 PCI Interface Errors...................................................................................... 13-9

13.3.3.1 PCI Address Parity Error.......................................................................... 13-9

13.3.3.2 PCI Data Parity Error.............................................................................. 13-10

13.3.3.3 PCI Master-Abort Transaction Termination........................................... 13-10

13.3.3.4 Received PCI Target-Abort Error........................................................... 13-10

13.3.3.5 NMI (Nonmaskable Interrupt)................................................................ 13-11

13.3.4 Message Unit Error Events......................................................................... 13-11

13.4 Exception Latencies........................................................................................ 13-11

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Chapter 14

Power Management

14.1 Overview........................................................................................................... 14-1

14.2 Processor Core Power Management................................................................. 14-1

14.2.1 Dynamic Power Management....................................................................... 14-2

14.2.2 Programmable Power Modes on Processor Core ......................................... 14-2

14.2.3 Processor Power Management Modes—Details........................................... 14-4

14.2.3.1 Full-Power Mode with DPM Disabled..................................................... 14-4

14.2.3.2 Full-Power Mode with DPM Enabled ...................................................... 14-4

14.2.3.3 Processor Doze Mode............................................................................... 14-4

14.2.3.4 Processor Nap Mode................................................................................. 14-5

14.2.3.5 Processor Sleep Mode............................................................................... 14-6

14.2.4 Power Management Software Considerations.............................................. 14-6

14.3 Peripheral Logic Power Management............................................................... 14-7

14.3.1 MPC8240 Peripheral Power Mode Transitions............................................ 14-7

14.3.2 Peripheral Power Management Modes......................................................... 14-9

14.3.2.1 Peripheral Logic Full Power Mode........................................................... 14-9

14.3.2.2 Peripheral Logic Doze Mode.................................................................... 14-9

14.3.2.3 Peripheral Logic Nap Mode...................................................................... 14-9

14.3.2.3.1 PCI Transactions During Nap Mode .................................................. 14-10

14.3.2.3.2 PLL Operation During Nap Mode...................................................... 14-10

14.3.2.4 Peripheral Logic Sleep Mode ................................................................. 14-10

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14.3.2.4.1 System Memory Refresh during Sleep Mode..................................... 14-11

14.3.2.4.2 Disabling the PLL during Sleep Mode............................................... 14-11

14.3.2.4.3 SDRAM Paging during Sleep Mode .................................................. 14-11

14.4 Example Code Sequence for Entering Processor

and Peripheral Logic Sleep Modes ............................................................. 14-11

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Chapter 15

Debug Features

15.1 Debug Register Summary................................................................................. 15-1

15.2 Address Attribute Signals................................................................................. 15-2

15.2.1 Memory Address Attribute Signals (MAA[0:2]).......................................... 15-2

15.2.2 Memory Address Attribute Signal Timing................................................... 15-3

15.2.3 PCI Address Attribute Signals...................................................................... 15-3

15.2.4 PCI Address Attribute Signal Timing........................................................... 15-4

15.3 Memory Debug Address................................................................................... 15-5

15.3.1 Enabling Debug Address.............................................................................. 15-5

15.3.2 Debug Address Signal Definitions ............................................................... 15-6

15.3.3 Physical Address Mappings.......................................................................... 15-6

15.3.4 RAS

15.3.5 Debug Address Timing................................................................................. 15-8

15.4 Memory Interface Valid (MIV

15.4.1 MIV

15.5 Memory Data Path Error Injection/Capture.................................................... 15-17

15.5.1 Memory Data Path Error Injection Mask Registers.................................... 15-17

15.5.1.1 DH Error Injection Mask Register.......................................................... 15-17

15.5.1.2 DL Error Injection Mask Register .......................................................... 15-18

15.5.1.3 Parity Error Injection Mask Register...................................................... 15-18

15.5.2 Memory Data Path Error Capture Monitor Registers................................. 15-19

15.5.2.1 DH Error Capture Monitor Register....................................................... 15-19

15.5.2.2 DL Error Capture Monitor Register ....................................................... 15-20

15.5.2.3 Parity Error Capture Monitor Register ................................................... 15-20

15.6 JTAG/Testing Support.................................................................................... 15-21

15.6.1 JTAG Signals.............................................................................................. 15-21

15.6.2 JTAG Registers and Scan Chains............................................................... 15-22

15.6.2.1 Bypass Register ...................................................................................... 15-22

15.6.2.2 Boundary-Scan Registers........................................................................ 15-22

15.6.2.3 Instruction Register................................................................................. 15-22

15.6.2.4 TAP Controller ....................................................................................... 15-22

Encoding .............................................................................................. 15-7

)........................................................................ 15-8

Signal Timing....................................................................................... 15-9

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Chapter 16

Programmable I/O and Watchpoint

16.1 Watchpoint Interface Signal Description.......................................................... 16-2

16.2 Watchpoint Registers........................................................................................ 16-3

16.2.1 Watchpoint Register Address Map............................................................... 16-3

16.2.2 Watchpoint Trigger Registers....................................................................... 16-4

16.2.3 Watchpoint Mask Registers.......................................................................... 16-6

16.2.4 Watchpoint Control Register (WP_CONTROL).......................................... 16-8

16.3 State and Block Diagrams............................................................................... 16-12

16.4 Watchpoint Trigger Applications ................................................................... 16-13

Appendix A

Address Map A

A.1 Address Space for Map A.................................................................................. A-1

A.2 Configuration Accesses Using Direct Method .................................................. A-5

Appendix B

Bit and Byte Ordering

B.1 Byte Ordering Overview..................................................................................... B-1

B.2 Byte-Ordering Mechanisms................................................................................ B-1

B.3 Big-Endian Mode................................................................................................ B-2

B.4 Little-Endian Mode............................................................................................. B-5

B.4.1 I/O Addressing in Little-Endian Mode......................................................... B-15

B.5 Setting the Endian Mode of Operation ............................................................. B-15

Appendix C

Initialization Example

Appendix D

PowerPC Instruction Set Listings

D.1 Instructions Sorted by Mnemonic...................................................................... D-1

D.2 Instructions Sorted by Opcode........................................................................... D-9

D.3 Instructions Grouped by Functional Categories .............................................. D-17

D.4 Instructions Sorted by Form............................................................................. D-27

D.5 Instruction Set Legend..................................................................................... D-38

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Appendix E

Processor Core Register Summary

E.1 PowerPC Register Set......................................................................................... E-1

E.1.1 PowerPC Register Set—UISA........................................................................ E-2

E.1.1.1 General-Purpose Registers (GPRs)............................................................. E-4

E.1.1.2 Floating-Point Registers (FPRs)................................................................. E-4

E.1.1.3 Condition Register (CR)............................................................................. E-4

E.1.1.3.1 Condition Register CR0 Field Definition............................................... E-4

E.1.1.3.2 Condition Register CR1 Field Definition............................................... E-5

E.1.1.3.3 Condition Register CRn Field—Compare Instruction ........................... E-5

E.1.1.4 Floating-Point Status and Control Register (FPSCR) ................................ E-6

E.1.1.5 XER Register (XER) .................................................................................. E-8

E.1.1.6 Link Register (LR)...................................................................................... E-9

E.1.1.7 Count Register (CTR)................................................................................. E-9

E.1.2 PowerPC VEA Register Set—Time Base .................................................... E-10

E.1.2.1 Reading the Time Base............................................................................. E-10

E.1.2.2 Computing Time of Day from the Time Base.......................................... E-11

E.1.3 PowerPC OEA Register Set.......................................................................... E-11

E.1.3.1 Machine State Register (MSR)................................................................. E-13

E.1.3.2 Processor Version Register (PVR) ........................................................... E-15

E.1.3.3 BAT Registers .......................................................................................... E-15

E.1.3.4 SDR1......................................................................................................... E-17

E.1.3.5 Segment Registers .................................................................................... E-18

E.1.3.6 SPRG0–SPRG3 ........................................................................................ E-18

E.1.3.7 DSISR....................................................................................................... E-19

E.1.3.8 Machine Status Save/Restore Register 0 (SRR0)..................................... E-19

E.1.3.9 Time Base Facility (TB)—OEA; Writing to the Time Base.................... E-19

E.1.3.10 Decrementer Register (DEC).................................................................... E-19

E.1.3.11 External Access Register (EAR) .............................................................. E-20

E.2 Implementation-Specific Registers from 603e ................................................. E-20

E.2.1 Data and Instruction TLB Miss Address Registers (DMISS and IMISS) .... E-21

E.2.2 Data and Instruction TLB Compare Registers (DCMP and ICMP) ............. E-21

E.2.3 Primary and Secondary Hash Address Registers (HASH1 and HASH2) .... E-22

E.2.4 Required Physical Address Register (RPA) ................................................. E-22

E.2.5 Instruction Address Breakpoint Register (IABR)......................................... E-23

E.3 MPC8240-Specific Registers............................................................................ E-23

E.3.1 Hardware Implementation-Dependent Register 0 (HID0)............................ E-24

E.3.2 Hardware Implementation-Dependent Register 1 (HID1)............................ E-27

E.3.3 Hardware Implementation-Dependent Register 2 (HID2)............................ E-28

xxii

MPC8240 Integrated Processor User’s Manual

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1-1 MPC8240 Integrated Processor Functional Block Diagram......................................... 1-2

1-2 System Using an Integrated MPC8240 as a Host Processor.........................................1-5

1-3 Embedded System Using an MPC8240 as a Peripheral Processor............................... 1-6

1-4 Embedded System Using an MPC8240 as a Distributed Processor.............................1-7

1-5 MPC8240 Integrated Processor Core Block Diagram.................................................. 1-9

1-6 MPC8240 Peripheral Logic Block Diagram............................................................... 1-11

2-1 MPC8240 Signal Groupings......................................................................................... 2-3

2-2 Clock Subsystem Block Diagram............................................................................... 2-34

2-3 Timing Diagram (1X, 1.5X, 2X, 2.5X, and 3X examples)......................................... 2-35

2-4 System Clocking with External PLL .......................................................................... 2-37

2-5 Clocking Solution—Small Load Requirements..........................................................2-38

2-6 Clocking Solution—High Clock Fanout Required..................................................... 2-38

3-1 Processor Core Address Map B in Host Mode............................................................. 3-4

3-2 PCI Memory Master Address Map B in Host Mode .................................................... 3-5

3-3 PCI I/O Master Address Map B.................................................................................... 3-6

3-4 Address Map B Processor Options in Host Mode........................................................3-9

3-5 Address Map B PCI Options in Host Mode................................................................3-10

3-6 Inbound PCI Address Translation............................................................................... 3-12

3-7 Outbound PCI Address Translation............................................................................ 3-13

3-8 Local Memory Base Address Register (LMBAR)—0x10..........................................3-15

3-9 Inbound Translation Window Register (ITWR)......................................................... 3-15

3-10 Outbound Memory Base Address Register (OMBAR)—0x0_2300..........................3-16

3-11 Outbound Translation Window Register (OTWR)—0x0_2308................................. 3-17

3-12 Embedded Utilities Memory Block Mapping to Local Memory................................ 3-19

3-13 Embedded Utilities Memory Block Mapping to PCI Memory................................... 3-20

4-1 Processor Accessible Configuration Space................................................................... 4-8

4-2 PCI Accessible Configuration Space.......................................................................... 4-10

4-3 PCI Command Register—0x04 .................................................................................. 4-11

4-4 PCI Status Register—0x06.........................................................................................4-13

4-5 Power Management Configuration Register 1 (PMCR1)—0x70...............................4-17

4-6 Power Management Configuration Register 2 (PMCR2)—0x72...............................4-19

4-7 Memory Starting Address Register 1—0x80.............................................................. 4-23

4-8 Memory Starting Address Register 2—0x84.............................................................. 4-24

4-9 Extended Memory Starting Address Register 1—0x88..............................................4-24

4-10 Extended Memory Starting Address Register 2—0x8C.............................................4-24

4-11 Memory Ending Address Register 1—0x90............................................................... 4-25

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4-12 Memory Ending Address Register 2—0x94............................................................... 4-25

4-13 Extended Memory Ending Address Register 1—0x98............................................... 4-26

4-14 Extended Memory Ending Address Register 2—0x9C.............................................. 4-26

4-15 Memory Bank Enable Register—0xA0...................................................................... 4-27

4-16 Memory Page Mode Register—0xA3 ........................................................................ 4-28

4-17 Processor Interface Configuration Register 1 (PICR1)—0xA8..................................4-29

4-18 Processor Interface Configuration Register 2 (PICR2)—0xAC.................................4-31

4-19 ECC Single-Bit Error Counter Register—0xB8......................................................... 4-33

4-20 ECC Single-Bit Error Trigger Register—0xB9..........................................................4-34

4-21 Error Enabling Register 1 (ErrEnR1)—0xC0............................................................. 4-35

4-22 Error Detection Register 1 (ErrDR1)—0xC1.............................................................4-36

4-23 Internal Processor Bus Error Status Register—0xC3................................................. 4-37

4-24 Error Enabling Register 2 (ErrEnR2)—0xC4............................................................. 4-37

4-25 Error Detection Register 2 (ErrDR2)—0xC5.............................................................4-39

4-26 PCI Bus Error Status Register—0xC7........................................................................4-40

4-27 Processor/PCI Error Address Register—0xC8........................................................... 4-40

4-28 Address Map B Options Register (AMBOR)—0xE0................................................. 4-41

4-29 Memory Control Configuration Register 1 (MCCR1)—0xF0 ................................... 4-43

4-30 Memory Control Configuration Register 2 (MCCR2)—0xF4 ................................... 4-45

4-31 Memory Control Configuration Register 3 (MCCR3)—0xF8 ................................... 4-48

4-32 Memory Control Configuration Register 4 (MCCR4)—0xFC................................... 4-51

5-1 MPC8240 Integrated Processor Core Block Diagram.................................................. 5-2

5-2 MPC8240 Programming Model—Registers............................................................... 5-12

5-3 Hardware Implementation Register 0 (HID0) ............................................................ 5-13

5-4 Hardware Implementation Register 1 (HID1) ............................................................ 5-16

5-5 Hardware Implementation-Dependent Register 2 (HID2).......................................... 5-17

5-6 Data Cache Organization............................................................................................ 5-22

6-1 Block Diagram for Memory Interface .......................................................................... 6-3

6-2 SDRAM Memory Interface Block Diagram................................................................. 6-6

6-3 Example 512-MByte SDRAM Configuration With Parity........................................... 6-8

6-4 SDRAM Flow-Through Memory Interface................................................................ 6-14

6-5 SDRAM Registered Memory Interface......................................................................6-15

6-6 . SDRAM In-line ECC/Parity Memory Interface.......................................................6-15

6-7 PGMAX Parameter Setting for SDRAM Interface .................................................... 6-20

6-8 SDRAM Single-Beat Read Timing (SDRAM Burst Length = 4) .............................. 6-23

6-9 SDRAM Four-Beat Burst Read Timing Configuration—64-Bit Mode ..................... 6-23

6-10 SDRAM Eight-Beat Burst Read Timing Configuration—32-Bit Mode .................... 6-24

6-11 SDRAM Single Beat Write Timing (SDRAM Burst Length = 4).............................. 6-24

6-12 SDRAM Four-Beat Burst Write Timing—64-Bit Mode............................................ 6-25

6-13 SDRAM Eight-Beat Burst Write Timing—32-Bit Mode...........................................6-25

6-14 SDRAM Mode Register Set Timing........................................................................... 6-26

6-15 Registered SDRAM DIMM Single-Beat Write Timing............................................. 6-30

6-16 Registered SDRAM DIMM Burst-Write Timing....................................................... 6-30

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6-17 SDRAM Refresh Period ............................................................................................. 6-31

6-18 SDRAM Bank Staggered CBR Refresh Timing......................................................... 6-33

6-19 SDRAM Self Refresh Entry........................................................................................6-35

6-20 SDRAM Self Refresh Exit.......................................................................................... 6-35

6-21 Processor Burst Reads from SDRAM.........................................................................6-37

6-22 Processor Single-Beat Reads from SDRAM .............................................................. 6-38

6-23 Processor Burst Writes to SDRAM ............................................................................ 6-39

6-24 Processor Single-Beat Writes to SDRAM.................................................................. 6-40

6-25 Processor Single-Beat Reads followed by Writes to SDRAM................................... 6-41

6-26 PCI Reads from SDRAM-Speculative Reads Enabled............................................... 6-43

6-27 PCI Reads from SDRAM-Speculative Reads Disabled..............................................6-44

6-28 PCI Writes to SDRAM ............................................................................................... 6-45

6-29 FPM or EDO DRAM Memory Interface Block Diagram .......................................... 6-46

6-30 Example 16-Mbyte DRAM System with Parity—64-Bit Mode.................................6-47

6-31 DRAM Memory Organization....................................................................................6-48

6-32 DRAM Address Multiplexing SDMA[12:0]—32 Bit Mode...................................... 6-52

6-33 DRAM Address Multiplexing SDMA[12:0]—64 Bit Mode...................................... 6-53

6-34 FPM-EDO Flow-through Memory Interface.............................................................. 6-55

6-35 DRAM Single-Beat Read Timing (No ECC) ............................................................. 6-58

6-36 DRAM Four-Beat Burst Read Timing (No ECC)—64-Bit Mode.............................. 6-58

6-37 DRAM Eight-Beat Burst Read Timing Configuration—32-Bit Mode.......................6-59

6-38 DRAM Single-Beat Write Timing (No ECC) ............................................................ 6-59

6-39 DRAM Four-Beat Burst Write Timing (No ECC)—64-Bit Mode.............................6-60

6-40 DRAM Eight-beat Burst Write Timing (No ECC)—32 Bit Mode............................. 6-60

6-41 FPM DRAM Burst Read with ECC............................................................................ 6-65

6-42 EDO DRAM Burst Read Timing with ECC............................................................... 6-65

6-43 DRAM Single-Beat Write Timing with RMW or ECC Enabled ............................... 6-66

6-44 DRAM Bank Staggered CBR Refresh Timing Configuration ................................... 6-67

6-45 DRAM Self-Refresh Timing Configuration............................................................... 6-68

6-46 PCI Reads from DRAM-Speculative Reads Enabled.................................................6-70

6-47 PCI Reads from DRAM-Speculative Reads Disabled................................................ 6-71

6-48 PCI Writes to DRAM..................................................................................................6-72

6-49 ROM Memory Interface Block Diagram....................................................................6-73

6-50 16-Mbyte ROM System Including Parity Paths to DRAM—64-Bit Mode................ 6-74

6-51 2-Mbyte Flash Memory System Including Parity Paths to DRAM—8-Bit Mode ..... 6-75

6-52 ROM/Flash Address Multiplexing—8-Bit Mode....................................................... 6-77

6-53 ROM/Flash Address Multiplexing—32-Bit Mode..................................................... 6-78

6-54 ROM/Flash Address Multiplexing—64-Bit Mode..................................................... 6-78

6-55 Read Access Timing for Non-Burst ROM/Flash Devices in 32- or 64-Bit Mode......6-80

6-56 Read Access Timing (Cache Block) for Burst ROM/Flash Devices in 64-Bit Mode 6-80 6-57 Read Access Timing (Cache Block) for Burst ROM/Flash Devices in 32-Bit Mode 6-81

6-58 8-Bit ROM/Flash Interface—Single-Byte Read Timing............................................ 6-82

6-59 8-Bit ROM/Flash Interface—Two-Byte Read Timing............................................... 6-82

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Figure Number

6-60 8-Bit ROM/Flash Interface—Cache-Line Read Timing.............................................6-83

6-61 8-, 32-, or 64-Bit Flash Write Access Timing ............................................................ 6-84

6-62 PCI Read from ROM/Port X 64-Bit ........................................................................... 6-85

6-63 PCI Read from ROM/Port X 8-Bit (Part 1 of 4).........................................................6-86

6-63 Figure 6-63. (Continued) PCI Reads from ROM/Port X 8-Bit (Part 2 of 4)..............6-87

6-63 Figure 6-63. (Continued) PCI Reads from ROM/Port X 8-Bit (Part 3 of 4)..............6-88

6-63 Figure 6-63. (Continued) PCI Reads from ROM/Port X 8-Bit (Part 4 of 4)..............6-89

6-64 Port X Peripheral Interface Block Diagram................................................................ 6-90

6-65 Example of Port X Peripheral Connected to the MPC8240 ....................................... 6-91

6-66 Example of Port X Peripheral Connected to the MPC8240 ....................................... 6-92

6-67 Port X Example Read Access Timing ........................................................................ 6-92

6-68 Port X Example Write Access Timing........................................................................6-93

7-1 Internal Processor-DMA Arbitration for PCI Bus........................................................ 7-5

7-2 PCI Arbitration Example .............................................................................................. 7-7

7-3 PCI Single-Beat Read Transaction ............................................................................. 7-15

7-4 PCI Burst Read Transaction........................................................................................7-16

7-5 PCI Single-Beat Write Transaction ............................................................................ 7-16

7-6 PCI Burst Write Transaction....................................................................................... 7-17

7-7 PCI Target-Initiated Terminations..............................................................................7-20

7-8 Standard PCI Configuration Header........................................................................... 7-22

7-9 CONFIG_ADDR Register Format ............................................................................. 7-24

7-10 Type 0 Configuration Translation............................................................................... 7-25

7-11 PCI Parity Operation................................................................................................... 7-31

8-1 DMA Controller Block Diagram..................................................................................8-2

8-2 DMA Controller General Flow.....................................................................................8-7

8-3 Chaining of DMA Descriptors in Memory.................................................................8-13

8-4 DMA Mode Register (DMR)...................................................................................... 8-15

8-5 DMA Status Register (DSR)....................................................................................... 8-18

8-6 Current Descriptor Address Register (CDAR)...........................................................8-20

8-7 Source Address Register (SAR)..................................................................................8-21

8-8 Destination Address Register (DAR)..........................................................................8-21

8-9 Byte Count Register (BCR)........................................................................................8-22

8-10 Next Descriptor Address Register (NDAR) ............................................................... 8-23

9-1 Message Registers (IMRs and OMRs) ......................................................................... 9-3

9-2 Inbound Doorbell Register (IDBR) .............................................................................. 9-3

9-3 Outbound Doorbell Register (ODBR)..........................................................................9-4

9-4 I

9-5 Outbound Message Interrupt Status Register (OMISR)............................................. 9-10

9-6 Outbound Message Interrupt Mask Register (OMIMR)............................................. 9-11

9-7 Inbound FIFO Queue Port Register (IFQPR)............................................................. 9-11

9-8 Outbound FIFO Queue Port Register (OFQPR).........................................................9-12

9-9 Inbound Message Interrupt Status Register (IMISR) ................................................. 9-13

9-10 Inbound Message Interrupt Mask Register (IMIMR).................................................9-14

O Message Queue Example....................................................................................... 9-7

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9-11 Inbound Free_FIFO Head Pointer Register (IFHPR)................................................. 9-15

9-12 Inbound Free_FIFO Tail Pointer Register (IFTPR)....................................................9-16

9-13 Inbound Post_FIFO Head Pointer Register (IPHPR) ................................................. 9-17

9-14 Inbound Post_FIFO Tail Pointer Register (IPTPR).................................................... 9-17

9-15 Outbound Free_FIFO Head Pointer Register (OFHPR).............................................9-18

9-16 Outbound Free_FIFO Tail Pointer Register (OFTPR) ............................................... 9-18

9-17 Outbound Post_FIFO Head Pointer Register (OPHPR)............................................. 9-19

9-18 Outbound Post_FIFO Tail Pointer Register (OPTPR)................................................9-20

9-19 Messaging Unit Control Register (MUCR)................................................................ 9-20

9-20 Queue Base Address Register (QBAR)...................................................................... 9-21

10-1 I 10-2 I 10-3 I 10-4 I 10-5 I 10-6 I 10-7 I 10-8 Example I

C Interface Block Diagram...................................................................................... 10-3

C Interface Transaction Protocol ............................................................................. 10-4

C Address Register (I2CADR) ................................................................................ 10-7

C Frequency Divider Register (I2CFDR)................................................................ 10-8

C Control Register (I2CCR) .................................................................................. 10-10

C Status Register (I2CSR) .....................................................................................10-11

C Data Register (I2CDR).......................................................................................10-13

C Interrupt Service Routine Flowchart...................................................10-17

11-1 EPIC Unit Block Diagram..........................................................................................11-3

11-2 EPIC Interrupt Generation Block Diagram—Non-programmable Registers............. 11-9

11-3 Serial Interrupt Interface Protocol ............................................................................ 11-12

11-4 Feature Reporting Register (FRR)............................................................................ 11-16

11-5 Global Configuration Register (GCR)...................................................................... 11-16

11-6 EPIC Interrupt Configuration Register (EICR) ........................................................ 11-17

11-7 EPIC Vendor Identification Register (EVI).............................................................. 11-18

11-8 Processor Initialization Register (PI)........................................................................ 11-19

11-9 Spurious Vector Register (SVR)............................................................................... 11-19

11-10 Timer Frequency Reporting Register (TFRR)..........................................................11-20

11-11 Global Timer Current Count Register (GTCCR)......................................................11-21

11-12 Global Timer Base Count Register (GTBCR).......................................................... 11-22

11-13 Global Timer Vector/Priority Register (GTVPR).....................................................11-22

11-14 Global Timer Destination Register (GTDR).............................................................11-24

11-15 Direct and Serial Interrupt Vector/Priority Registers (IVPR and SVPR)................. 11-25

11-16 Direct and Serial Destination Registers (IDR and SDR).......................................... 11-26

11-17 Processor Current Task Priority Register (PCTPR)..................................................11-27

11-18 Processor Interrupt Acknowledge Register (IACK)................................................. 11-28

11-19 Processor End of Interrupt Register (EOI)................................................................11-28

12-1 MPC8240 Internal Buffer Organization .................................................................... 12-2

12-2 Processor/Local Memory Buffers............................................................................... 12-3

12-3 Processor/PCI Buffers................................................................................................. 12-4

12-4 PCI/Local Memory Buffers ........................................................................................ 12-6

12-5 PCI/DMA Arbitration for Local Memory Accesses...................................................12-9

13-1 Internal Error Management Block Diagram...............................................................13-2

Illustrations xxvii

ILLUSTRATIONS

Figure Number

14-1 MPC8240 Peripheral Logic Power States...................................................................14-7

15-1 Example PCI Address Attribute Signal Timing for Burst Read Operations .............. 15-4

15-2 Example PCI Address Attribute Signal Timing for Burst Write Operations..............15-5

15-3 64-Bit Mode, DRAM and SDRAM Physical Address for Debug.............................. 15-6

15-4 32-Bit Mode, DRAM and SDRAM Physical Address for Debug.............................. 15-7

15-5 64-Bit Mode, ROM and Flash Physical Address for Debug ...................................... 15-7

15-6 32-Bit Mode, ROM and Flash Physical Address for Debug ...................................... 15-7

15-7 8-Bit Mode, ROM and Flash Physical Address for Debug ........................................ 15-7

15-8 Example FPM Debug Address, MIV, and MAA Timings for Burst Read Operation 15-9 15-9 Example FPM Debug Address, MIV, and MAA Timings for Burst Write Operation15-10 15-10 Example EDO Debug Address, MIV, and MAA Timings for Burst Read Operation15-11 15-11 Example EDO Debug Address, MIV, and MAA Timings for Burst Write Operation15-12 15-12 Example SDRAM Debug Address, MIV,

and MAA Timings for Burst Read Operation...........................................................15-13

15-13 Example SDRAM Debug Address, MIV,

and MAA Timings for Burst Write Operation.......................................................... 15-14

15-14 Example ROM Debug Address, MIV, and MAA Timings For Burst Read............. 15-15

15-15 Example Flash Debug Address, MIV, and MAA Timings For Single-Byte Read... 15-16

15-16 Example Flash Debug Address, MIV, and MAA Timings for Write Operation......15-16

15-17 Functional Diagram of Memory Data Path Error Injection...................................... 15-17

15-18 DH Error Injection Mask (MDP_ERR_INJ_MASK_DH)—

Offsets 0xF_F000, 0xF00 ......................................................................................... 15-17

15-19 DL Error Injection Mask (MDP_ERR_INJ_MASK_DL)—

Offsets 0xF_F004, 0xF04 ......................................................................................... 15-18

15-20 Parity Error Injection Mask (MDP_ERR_INJ_MASK_PAR)—

Offsets 0xF_F008, 0xF08 ......................................................................................... 15-18

15-21 DH Error Capture Monitor (MDP_ERR_CAP_MON_DH)—

Offsets 0xF_F00C, 0xF0C........................................................................................ 15-19

15-22 DL Error Capture Monitor (MDP_ERR_CAP_MON_DL)—

Offsets 0xF_F010, 0xF10 ......................................................................................... 15-20

15-23 Parity Error Capture Monitor (MDP_ERR_CAP_MON_PAR)—

Offsets 0xF_F014, 0xF14 ......................................................................................... 15-20

15-24 JTAG Interface Block Diagram................................................................................ 15-21

16-1 Watchpoint Facility Signal Interface..........................................................................16-1

16-2 Watchpoint #1 Control Trigger Register (WP1_CNTL_TRIG)—

Offsets 0xF_F018, 0xF18 ........................................................................................... 16-4

16-3 Watchpoint #1 Control Trigger Register (WP1_CNTL_TRIG)—

Offsets 0xF_F030, 0xF30 ........................................................................................... 16-4

16-4 Watchpoint #1 Address Trigger Register (WP1_ADDR_TRIG)—

Offsets 0xF_F01C, 0xF1C.......................................................................................... 16-5

16-5 Watchpoint #2 Address Trigger Register (WP2_ADDR_TRIG)—

Offsets 0xF_F034, 0xF34 ........................................................................................... 16-5

16-6 Bit Match Generation for Watchpoint Trigger Bit Settings........................................16-6

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16-7 Watchpoint #1 Control Mask Register (WP1_CNTL_MASK)—

Offsets 0xF_F020, 0xF20 ........................................................................................... 16-6

16-8 Watchpoint #2 Control Mask Register (WP2_CNTL_MASK)—

Offsets 0xF_F038, 0xF38 ........................................................................................... 16-7

16-9 Watchpoint #1 Address Mask Register (WP1_ADDR_MASK)—

Offsets 0xF_F024, 0xF24 ........................................................................................... 16-8

16-10 Watchpoint #2 Address Mask Register (WP2_ADDR_MASK)—

Offsets 0xF_F03C, 0xF3C.......................................................................................... 16-8

16-11 Watchpoint Control Register (WP_CONTROL)—

Offsets 0xF_F048, 0xF48 ........................................................................................... 16-9

16-12 Watchpoint Facility State Diagram........................................................................... 16-12

16-13 Watchpoint Facility Block Diagram......................................................................... 16-13

A-1 Processor Core Address Map ...................................................................................... A-3

A-2 PCI Memory Master Address Map ............................................................................. A-4

A-3 PCI I/O Master Address Map ..................................................................................... A-5

A-4 Direct-Access PCI Configuration Transaction ............................................................ A-6

B-1 Four-Byte Transfer to PCI Memory Space—Big-Endian Mode ..................................B-3

B-2 . Big-Endian Memory Image in Local Memory ...........................................................B-4

B-3 Big-Endian Memory Image in Big-Endian PCI Memory Space ..................................B-5

B-4 Munged Memory Image in Local Memory ..................................................................B-7

B-5 Little-Endian Memory Image in Little-Endian PCI Memory Space ............................B-8

B-6 One-Byte Transfer to PCI Memory Space—Little-Endian Mode ................................B-9

B-7 Two-Byte Transfer to PCI Memory Space—Little-Endian Mode .............................B-10

B-8 Four-Byte Transfer to PCI Memory Space—Little-Endian Mode .............................B-11

B-9 One-Byte Transfer to PCI I/O Space—Little-Endian Mode.......................................B-12

B-10 Two-Byte Transfer to PCI I/O Space—Little-Endian Mode......................................B-13

B-11 Four-Byte Transfer to PCI I/O Space—Little-Endian Mode......................................B-14

E-1 MPC8240 Processor Programming Model—Registers................................................E-3

E-2 General-Purpose Registers (GPRs)...............................................................................E-4

E-3 Floating-Point Registers (FPRs)...................................................................................E-4

E-4 Condition Register (CR)...............................................................................................E-4

E-5 Floating-Point Status and Control Register (FPSCR)...................................................E-6

E-6 XER Register................................................................................................................E-8

E-7 Link Register (LR)........................................................................................................E-9

E-8 Count Register (CTR)...................................................................................................E-9

E-9 Time Base (TB)...........................................................................................................E-10

E-10 Machine State Register (MSR) ...................................................................................E-13

E-11 Processor Version Register (PVR)..............................................................................E-15

E-12 Upper BAT Register ...................................................................................................E-16

E-13 Lower BAT Register...................................................................................................E-16

E-14 SDR1 Register Format................................................................................................E-17

E-15 Segment Register Format (T = 0) ...............................................................................E-18

E-16 SPRG0–SPRG3 ..........................................................................................................E-18

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E-17 DSISR .........................................................................................................................E-19

E-18 Machine Status Save/Restore Register 0 (SRR0)

Machine Status Save/Restore Register 1 (SRR1).......................................................E-19

E-19 Machine Status Save/Restore Register 1 (SRR1) .......................................................E-19

E-20 Decrementer Register (DEC)......................................................................................E-20

E-21 External Access Register (EAR).................................................................................E-20

E-22 DMISS and IMISS Registers......................................................................................E-21

E-23 DCMP and ICMP Registers........................................................................................E-21

E-24 HASH1 and HASH2 Registers ...................................................................................E-22

E-25 Required Physical Address Register (RPA) ...............................................................E-22

E-26 Instruction Address Breakpoint Register (IABR).......................................................E-23

E-27 Hardware Implementation Register 0 (HID0) ............................................................E-24

E-28 Hardware Implementation Register 1 (HID1) ............................................................E-27

E-29 Hardware Implementation-Dependent Register 2 (HID2)..........................................E-28

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TABLES

Table Number

1-1 Programmable Processor Power Modes .................................................................... 1-18

1-2 Peripheral Logic Power Modes Summary................................................................. 1-19

2-1 MPC8240 Signal Cross Reference................................................................................2-4

2-2 Output Signal States During System Reset................................................................... 2-7

2-3 PCI Command Encodings........................................................................................... 2-11

2-4 Memory Data Bus Byte Lane Assignments................................................................ 2-19

2-5 MPC8240 Reset Configuration Signals...................................................................... 2-39

3-1 Address Map B—Processor View in Host Mode.........................................................3-2

3-2 Address Map B—PCI Memory Master View in Host Mode........................................ 3-2

3-3 Address Map B—PCI Memory Master View in Agent Mode ..................................... 3-3

3-4 Address Map B—PCI I/O Master View....................................................................... 3-3

3-5 Address Map B—Processor View in Host Mode Options............................................3-8

3-6 Address Map B—PCI Memory Master View in Host Mode Options.......................... 3-9

3-7 ATU Register Summary ............................................................................................. 3-14

3-8 Bit Settings for LMBAR—0x10.................................................................................3-15

3-9 Bit Settings for ITWR—0x0_2310.............................................................................3-16

3-10 Bit Settings for OMBAR—0x0_2300 ........................................................................ 3-17

3-11 Bit Settings for OTWR—0x0_2308 ........................................................................... 3-17

3-12 Embedded Utilities Local Memory Register Summary.............................................. 3-19

3-13 Embedded Utilities Peripheral Control and Status Register Summary ...................... 3-20

4-1 Internal Register Access Port Locations....................................................................... 4-1

4-2 MPC8240 Configuration Registers Accessible from the Processor Core .................... 4-5

4-3 MPC8240 Configuration Registers Accessible from the PCI Bus ............................... 4-9

4-4 PCI Configuration Space Header Summary...............................................................4-10

4-5 Bit Settings for PCI Command Register—0x04.........................................................4-12

4-6 Bit Settings for PCI Status Register—0x06................................................................ 4-13

4-7 Programming Interface—0x09 ................................................................................... 4-14

4-8 PCI Base Class Code—0x0B...................................................................................... 4-14

4-9 Cache Line Size Register—0x0C ............................................................................... 4-14

4-10 Latency Timer Register—0x0D.................................................................................. 4-14

4-11 Local Memory Base Address Register Bit Definitions—0x10...................................4-15

4-12 PCSR Base Address Register Bit Definitions—0x14................................................. 4-15

4-13 Interrupt Line Register—0x3C...................................................................................4-16

4-14 PCI Arbiter Control Register Bit Definitions—0x46 ................................................. 4-16

4-15 Bit Settings for Power Management Configuration Register 1—0x70......................4-17

4-16 Power Management Configuration Register 2—0x72................................................ 4-19

Title

Page

Number

Tables xxxi

TABLES

Table Number

4-17 Output Driver Control Register Bit Definitions—0x73..............................................4-20

4-18 CLK Driver Control Register Bit Definitions—0x74................................................. 4-22

4-19 Embedded Utilities Memory Base Address Register—0x78......................................4-23

4-20 Bit Settings for Memory Starting Address Registers 1 and 2.....................................4-24

4-21 Bit Settings for Extended Memory Starting Address Registers 1 and 2..................... 4-25

4-22 Bit Settings for Memory Ending Address Registers 1 and 2...................................... 4-25

4-23 Bit Settings for Extended Memory Ending Address Registers 1 and 2......................4-26

4-24 Bit Settings for Memory Bank Enable Register—0xA0.............................................4-27

4-25 Bit Settings for Memory Page Mode Register—0xA3............................................... 4-28

4-26 Bit Settings for PICR1—0xA8 ................................................................................... 4-29

4-27 Bit Settings for PICR2—0xAC................................................................................... 4-32

4-28 Bit Settings for ECC Single-Bit Error Counter Register—0xB8................................4-33

4-29 Bit Settings for ECC Single-Bit Error Trigger Register—0xB9 ................................ 4-34

4-30 Bit Settings for Error Enabling Register 1 (ErrEnR1)—0xC0 ................................... 4-35

4-31 Bit Settings for Error Detection Register 1 (ErrDR1)—0xC1.................................... 4-36

4-32 Bit Settings for Internal Processor Bus Error Status Register—0xC3........................ 4-37

4-33 Bit Settings for Error Enabling Register 2 (ErrEnR2)—0xC4 ................................... 4-38

4-34 Bit Settings for Error Detection Register 2 (ErrDR2)—0xC5.................................... 4-39

4-35 Bit Settings for PCI Bus Error Status Register—0xC7 .............................................. 4-40

4-36 Bit Settings for Processor/PCI Error Address Register—0xC8.................................. 4-40

4-37 Bit Settings for the AMBOR—0xE0.......................................................................... 4-41

4-38 Bit Settings for MCCR1—0xF0 ................................................................................. 4-43

4-39 Bit Settings for MCCR2—0xF4 ................................................................................. 4-46

4-40 Bit Settings for MCCR3—0xF8 ................................................................................. 4-49

4-41 Bit Settings for MCCR4—0xFC................................................................................. 4-52

5-1 HID0 Field Descriptions............................................................................................. 5-13

5-2 HID0[BCLK] and HID0[ECLK] CKO Signal Configuration.................................... 5-16

5-3 HID1 Field Descriptions............................................................................................. 5-17

5-4 HID2 Field Descriptions............................................................................................. 5-17

5-5 CCU Responses to Processor Transactions ................................................................ 5-24

5-6 Transactions Reflected to the Processor for Snooping...............................................5-25

5-7 Exception Classifications for the Processor Core.......................................................5-28

5-8 Exceptions and Conditions ......................................................................................... 5-28

5-9 Integer Divide Latency ............................................................................................... 5-33

5-10 Major Differences between MPC8240’s Core and the MPC603e User’s Manual..... 5-34

6-1 Memory Interface Signal Summary.............................................................................. 6-3

6-2 Memory Address Signal Mappings .............................................................................. 6-5

6-3 SDRAM Data Bus Lane Assignments..........................................................................6-7

6-4 Unsupported Multiplexed Row and Column Address Bits...........................................6-9

6-5 Supported SDRAM Device Configurations................................................................6-10

6-6 SDRAM Address Multiplexing SDBA[1:0] and SDMA[12:0]—32-Bit Mode.........6-11

6-7 SDRAM Address Multiplexing SDBA[1:0]and SDMA[12:0]—64-Bit Mode..........6-12

6-8 Memory Data Path Parameters ................................................................................... 6-13

Title

Page

Number

xxxii MPC8240 Integrated Processor User’s Manual

TABLES

Table Number

Title

Page

Number

6-9 SDRAM System Configurations.................................................................................6-14

6-10 MPC8240 SDRAM Interface Commands .................................................................. 6-18

6-11 SDRAM Interface Timing Intervals ........................................................................... 6-22

6-12 The MPC8240 SDRAM ECC Syndrome Encoding (Data Bits 0:31) ........................ 6-28

6-13 The MPC8240 SDRAM ECC Syndrome Encoding (Data Bits 32:63) ...................... 6-29

6-14 SDRAM Controller Power Saving Configurations.....................................................6-34

6-15 SDRAM Power Saving Modes Refresh Configuration..............................................6-34

6-16 Unsupported Multiplexed Row and Column Address Bits.........................................6-49

6-17 Supported FPM or EDO DRAM Device Configurations...........................................6-49

6-18 SDMA[11:8] Encodings for 32- and 64-Bit Bus Modes............................................6-51

6-19 FPM or EDO Memory Parameters ............................................................................. 6-54

6-20 FPM or EDO System Configurations.........................................................................6-54

6-21 Memory Interface Configuration Register Fields....................................................... 6-55

6-22 FPM or EDO Timing Parameters ............................................................................... 6-57

6-23 The MPC8240 FPM or EDO ECC Syndrome Encoding (Data bits 0:31).................. 6-63

6-24 The MPC8240 FPM or EDO ECC Syndrome Encoding (Data bits 32:63)................ 6-63

6-25 FPM or EDO DRAM Power Saving Modes Refresh Configuration..........................6-68

6-26 Reset Configurations of ROM/Flash Controller......................................................... 6-76

7-1 PCI Arbiter Control Register Parking Mode Bits......................................................... 7-8

7-2 PCI Bus Commands....................................................................................................7-10

7-3 Supported Combinations of AD[1:0].......................................................................... 7-12

7-4 PCI Configuration Space Header Summary...............................................................7-22

7-5 CONFIG_ADDR Register Fields...............................................................................7-24

7-6 Type 0 Configuration—Device Number to IDSEL Translation................................. 7-26

7-7 Special-Cycle Message Encodings.............................................................................7-28

7-8 Initialization Options for PCI Controller.................................................................... 7-33

8-1 DMA Register Summary .............................................................................................. 8-3

8-2 DMA Descriptor Summary......................................................................................... 8-12

8-3 DMR Field Descriptions—Offsets 0x100, 0x200 ...................................................... 8-16

8-4 DSR Field Descriptions—Offsets 0x104, 0x204........................................................ 8-19

8-5 CDAR Field Descriptions—Offsets 0x108, 0x208 .................................................... 8-20

8-6 SAR Field Description—Offsets 0x110, 0x210 ......................................................... 8-21

8-7 DAR Field Description—Offsets 0x118, 0x218......................................................... 8-21

8-8 BCR Field Descriptions—Offsets 0x120, 0x220........................................................8-22

8-9 NDAR Field Descriptions—Offsets 0x124, 0x224....................................................8-23

9-1 Message Register Summary.......................................................................................... 9-2

9-2 Doorbell Register Summary ......................................................................................... 9-2

9-3 IMR and OMR Field Descriptions—Offsets 0x050–0x05C, 0x0_0050–0x0_005C.... 9-3

9-4 IDBR Field Descriptions—Offsets 0x068, 0x0_0068.................................................. 9-4

9-5 ODBR Field Descriptions—Offsets 0x060, 0x0_0060 ................................................ 9-4

9-6 I 9-7 I

O PCI Configuration Identification Register Settings ............................................... 9-5

O Register Summary..................................................................................................9-5

9-8 Queue Starting Address ................................................................................................ 9-7

Tables xxxiii

TABLES

Table Number

Title

Page

Number

9-9 OMISR Field Descriptions—Offset 0x030 ................................................................ 9-10

9-10 OMIMR Field Descriptions—Offset 0x034............................................................... 9-11

9-11 IFQPR Field Descriptions—Offset 0x040.................................................................. 9-12

9-12 OFQPR Field Descriptions—Offset 0x044................................................................9-12

9-13 IMISR Field Descriptions—Offset 0x0_0100............................................................ 9-13

9-14 IMIMR Field Descriptions—Offset 0x0_0104........................................................... 9-15

9-15 IFHPR Field Descriptions—Offset 0x0_0120............................................................ 9-16

9-16 IFTPR Field Descriptions—Offset 0x0_0128............................................................9-16

9-17 IPHPR Field Descriptions—Offset 0x0_0130............................................................ 9-17

9-18 IPTPR Field Descriptions—Offset 0x0_0138............................................................9-17

9-19 OFHPR Field Descriptions—Offset 0x0_0140..........................................................9-18

9-20 OFTPR Field Descriptions—Offset 0x0_0148........................................................... 9-19

9-21 OPHPR Field Descriptions—Offset 0x0_0150..........................................................9-19

9-22 OPTPR Field Descriptions— Offset 0x0_0158.......................................................... 9-20

9-23 MUCR Field Descriptions— Offset 0x0_0164 .......................................................... 9-20

9-24 QBAR Field Descriptions— Offset 0x0_0170........................................................... 9-21

10-1 I 10-2 I

C Interface Signal Description.................................................................................10-2

C Register Summary................................................................................................ 10-2

10-3 I2CADR Field Descriptions—Offset 0x0_3000......................................................... 10-8

10-4 I2CFDR Field Descriptions—Offset 0x0_3004 ......................................................... 10-8

10-5 Serial Bit Clock Frequency Divider Selections..........................................................10-9

10-6 I2CCR Field Descriptions—Offset 0x0_3008.......................................................... 10-10

10-7 I2CSR Field Descriptions—Offset 0x0_300C..........................................................10-12

10-8 I2CDR Field Descriptions—Offset 0x0_3010..........................................................10-13

11-1 EPIC Interface Signal Description.............................................................................. 11-2

11-2 EPIC Register Address Map—Global and Timer Registers....................................... 11-4

11-3 EPIC Register Address Map—Interrupt Source Configuration Registers.................. 11-5

11-4 EPIC Register Address Map—Processor-Related Registers...................................... 11-7

11-5 FRR Field Descriptions—Offset 0x4_1000..............................................................11-16

11-6 GCR Field Descriptions—Offset 0x4_1020.............................................................11-17

11-7 EICR Field Descriptions—Offset 0x4_1030............................................................ 11-18

11-8 EVI Register Field Descriptions—Offset 0x4_1080................................................ 11-18

11-9 PI Register Field Descriptions—Offset 0x4_1090...................................................11-19

11-10 SVR Field Descriptions—Offset 0x4_10E0.............................................................11-20

11-11 TFRR Field Descriptions—Offset 0x4_10F0...........................................................11-20

11-12 EUMBBAR Offsets for GTCCRs............................................................................. 11-21

11-13 GTCCR Field Descriptions....................................................................................... 11-21

11-14 EUMBBAR Offsets for GTBCRs............................................................................. 11-21

11-15 GTBCR Field Descriptions....................................................................................... 11-22

11-16 EUMBBAR Offsets for GTVPRs.............................................................................11-22

11-17 GTVPR Field Descriptions....................................................................................... 11-23

11-18 EUMBBAR Offsets for GTDRs............................................................................... 11-23

11-19 GTDR Field Descriptions.........................................................................................11-24

xxxiv MPC8240 Integrated Processor User’s Manual

TABLES

Table Number

11-20 EUMBBAR Offsets for IVPRs and SVPRs..............................................................11-24

11-21 IVPR and SVPR Field Descriptions.........................................................................11-25

11-22 EUMBBAR Offsets for IDRs and SDRs.................................................................. 11-26

11-23 IDR and SDR Field Descriptions.............................................................................. 11-26

11-24 PCTPR Field Descriptions—Offset 0x6_0080.........................................................11-27

11-25 IACK Field Descriptions—Offset 0x6_00A0 .......................................................... 11-28

11-26 EOI Field Descriptions—Offset 0x6_00B0.............................................................. 11-28

12-1 Snooping Behavior Caused by a Hit in an Internal Buffer......................................... 12-7

12-2 Internal Arbitration Priorities.................................................................................... 12-12

13-1 MPC8240 Error Priorities........................................................................................... 13-2

13-2 Processor Write Parity Checking................................................................................ 13-7

14-1 Programmable Processor Power Modes ..................................................................... 14-3

14-2 Peripheral Logic Power Modes Summary................................................................. 14-8

15-1 Memory Data Path Diagnostic Register Offsets.........................................................15-2

15-2 Address Attribute Signal Summary............................................................................15-2

15-3 Memory Address Attribute Signal Encodings............................................................ 15-2

15-4 PCI Attribute Signal Encodings.................................................................................. 15-3

15-5 Memory Debug Address Signal Definitions............................................................... 15-6

15-6 Example of RAS Encoding For 568-Mbyte Memory System.................................... 15-8

15-7 Memory Interface Valid Signal Definition................................................................. 15-9

15-8 DH Error Injection Mask Bit Field Definitions........................................................ 15-18

15-9 DL Error Injection Mask Bit Field Definitions.........................................................15-18

15-10 Parity Error Injection Mask Bit Field Definitions .................................................... 15-19

15-11 DH Error Capture Monitor Bit Field Definitions ..................................................... 15-19

15-12 DL Error Capture Monitor Bit Field Definitions......................................................15-20

15-13 Parity Error Capture Monitor Bit Field Definitions.................................................. 15-20

16-1 Watchpoint Signal Summary...................................................................................... 16-2

16-2 Watchpoint Register Offsets....................................................................................... 16-3

16-3 Watchpoint Control Trigger Register Bit Field Definitions.......................................16-4

16-4 Watchpoint Address Trigger Register Bit Field Definitions ...................................... 16-6

16-5 Watchpoint Control Mask Register Bit Field Definitions .......................................... 16-7

16-6 Watchpoint Address Mask Register Bit Field Definitions ......................................... 16-8

16-7 Watchpoint Control Register Bit Field Definitions....................................................16-9

16-8 Watchpoint Mode Select (WP_CONTROL[WP_MODE])...................................... 16-11

A-1 Address Map A—Processor View............................................................................... A-1

A-2 Map A—PCI Memory Master View............................................................................ A-2

A-3 Address Map A—PCI I/O Master View...................................................................... A-2

B-1 Byte Lane Translation in Big-Endian Mode.................................................................B-2

B-2 Processor Address Modification for Individual Aligned Scalars .................................B-6

B-3 MPC8240 Address Modification for Individual Aligned Scalars.................................B-6

B-4 Byte Lane Translation in Little-Endian Mode..............................................................B-6

D-1 Complete Instruction List Sorted by Mnemonic.......................................................... D-1

D-2 Complete Instruction List Sorted by Opcode............................................................... D-9

Title

Page

Number

Tables xxxv

TABLES

Table Number

D-3 Integer Arithmetic Instructions.................................................................................. D-17

D-4 Integer Compare Instructions..................................................................................... D-18

D-5 Integer Logical Instructions....................................................................................... D-18

D-6 Integer Rotate Instructions......................................................................................... D-18

D-7 Integer Shift Instructions............................................................................................ D-19

D-8 Floating-Point Arithmetic Instructions7.................................................................... D-19

D-9 Floating-Point Multiply-Add Instructions7 ............................................................... D-20

D-10 Floating-Point Rounding and Conversion Instructions7............................................D-20

D-11 Floating-Point Compare Instructions7....................................................................... D-20

D-12 Floating-Point Status and Control Register Instructions7......................................... D-20

D-13 Integer Load Instructions........................................................................................... D-21

D-14 Integer Store Instructions........................................................................................... D-21

D-15 Integer Load and Store with Byte-Reverse Instructions............................................ D-22

D-16 Integer Load and Store Multiple Instructions............................................................ D-22

D-17 Integer Load and Store String Instructions................................................................ D-22

D-18 Memory Synchronization Instructions......................................................................D-22

D-19 Floating-Point Load Instructions7............................................................................. D-23

D-20 Floating-Point Store Instructions7............................................................................. D-23

D-21 Floating-Point Move Instructions7............................................................................ D-23

D-22 Branch Instructions.................................................................................................... D-24

D-23 Condition Register Logical Instructions.................................................................... D-24

D-24 System Linkage Instructions...................................................................................... D-24

D-25 Trap Instructions........................................................................................................ D-24

D-26 Processor Control Instructions................................................................................... D-24

D-27 Cache Management Instructions................................................................................ D-25

D-28 Segment Register Manipulation Instructions............................................................. D-25

D-29 Lookaside Buffer Management Instructions..............................................................D-25

D-30 External Control Instructions..................................................................................... D-26

D-31 I-Form........................................................................................................................ D-27

D-32 B-Form....................................................................................................................... D-27

D-33 SC-Form.....................................................................................................................D-27

D-34 D-Form.......................................................................................................................D-27

D-35 DS-Form.................................................................................................................... D-29

D-36 X-Form.......................................................................................................................D-29

D-37 XL-Form.................................................................................................................... D-33

D-38 XFX-Form..................................................................................................................D-34

D-39 XFL-Form.................................................................................................................. D-34

D-40 XS-Form.................................................................................................................... D-34

D-41 XO-Form.................................................................................................................... D-34

D-42 A-Form.......................................................................................................................D-35

D-43 M-Form...................................................................................................................... D-36

D-44 MD-Form................................................................................................................... D-36

D-45 MDS-Form................................................................................................................. D-37

Title

Page

Number

Tables xxxvi

TABLES

Table Number

D-46 PowerPC Instruction Set Legend............................................................................... D-38

E-1 Bit Settings for CR0 Field of CR..................................................................................E-4

E-2 Bit Settings for CR1 Field of CR..................................................................................E-5

E-3 CRn Field Bit Settings for Compare Instructions.........................................................E-5

E-4 FPSCR Bit Settings.......................................................................................................E-6

E-5 Floating-Point Result Flags in FPSCR .........................................................................E-8

E-6 XER Bit Definitions......................................................................................................E-8

E-7 BO Operand Encodings ...............................................................................................E-9

E-8 MSR Bit Settings ........................................................................................................E-13

E-9 Floating-Point Exception Mode Bits ..........................................................................E-15

E-10 BAT Registers—Field and Bit Descriptions...............................................................E-16

E-11 BAT Area Lengths .....................................................................................................E-17

E-12 SDR1 Bit Settings.......................................................................................................E-17

E-13 Segment Register Bit Settings (T = 0) ........................................................................E-18

E-14 Conventional Uses of SPRG0–SPRG3.......................................................................E-18

E-15 External Access Register (EAR) Bit Settings.............................................................E-20

E-16 DCMP and ICMP Bit Settings....................................................................................E-21

E-17 HASH1 and HASH2 Bit Settings ...............................................................................E-22

E-18 RPA Bit Settings.........................................................................................................E-23

E-19 Instruction Address Breakpoint Register Bit Settings ................................................E-23

E-20 HID0 Field Descriptions.............................................................................................E-24

E-21 HID0[BCLK] and HID0[ECLK] CKO Signal Configuration....................................E-27

E-22 HID1 Field Descriptions.............................................................................................E-27

E-23 HID2 Field Descriptions.............................................................................................E-28

Title

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Number

Tables xxxvii

TABLES

Table Number

Title

Page

Number

xviii MPC8240 Integrated Processor User’s Manual

About This Book

The primary objective of this user’s manual is to deﬁne the functionality of the MPC8240 PowerPC™ integrated processor. The MPC8240 has a processor core based on the PowerPC 603e™ low-power microprocessor; it also performs many peripheral functions on-chip.

The MPC603e implements the full 32-bit portion of the PowerPC™ architecture. It is important to note that this book is intended as a companion to the following publications:

• The MPC603e & EC603e RISC Microprocessor User’s Manual

• The PowerPC Microprocessor Family: The Programming Environments, (referred to as The Programming Environments Manual)

Contact your local sales representative to obtain a copy. Because the PowerPC architecture is designed to support a broad range of processors, The Programming Environments Manual provides a general description of features that are common to Po werPC processors and indicates those features that are optional or may be implemented differently in the design of each processor.

The information is subject to change without notice, as described in the disclaimers on the title page of this book. As with an y technical documentation, it is the reader’ s responsibility to use the most recent version of the documentation. For more information, contact your sales representative.

Audience

This manual is intended for system software and hardware developers and applications programmers who want to develop products using the MPC8240 inte grated processor. It is assumed that the reader understands operating systems, microprocessor system design, the basic principles of RISC processing, and details of the PowerPC architecture.

About This Book xxxix

Organization

Following is a list describing the major sections of this manual:

• Chapter 1, “Overview,” is for readers who want a general understanding of the features and functions of the MPC8240 device and its component parts.

• Chapter 2, “Signal Descriptions and Clocking,” provides descriptions of the MPC8240’s external signals. It describes each signal’s behavior when the signal is asserted and negated and when the signal is an input or an output.

• Chapter 3, “Address Maps, ” describes ho w the MPC8240 in host mode supports the address map B conﬁguration.

• Chapter 4, “Conﬁguration Registers,” describes the programmable conﬁguration registers of the MPC8240.

• Chapter 5, “PowerPC Processor Core,” provides an overview of the basic functionality of the G2 processor core.

• Chapter 6, “MPC107 Memory Interface,” describes the memory interface of the MPC8240 and how it controls the processor and PCI interactions to main memory.

• Chapter 7, “PCI Bus Interface,” provides a rudimentary description of PCI bus operations. The speciﬁc emphasis is directed at how the MPC8240 implements the PCI bus.

• Chapter 8, “DMA Controller,” describes how the DMA controller operates on the MPC8240.

• Chapter 9, “Message Unit (with I2O),” describes a mechanism to facilitate communications between host and peripheral processors.

• Chapter 10, “I2C Interface,” describes the I the MPC8240.

• Chapter 11, “Embedded Programmable Interrupt Controller (EPIC) Unit,” provides a description of a general purpose interrupt controller solution using the EPIC module of the MPC8240.

• Chapter 12, “Central Control Unit,” describes the internal buf fering and arbitration logic of the MPC8240 central control unit (CCU).

• Chapter 13, “Error Handling,” describes ho w the MPC8240 handles dif ferent error conditions.

• Chapter 14, “Power Management,” describes the many hardware support features provided by the MPC8240 for power management.

• Chapter 15, “Debug Features,” describes the MPC8240 features that aid in the process of system bring-up and debug.

C (inter-integrated circuit) interface on

xl MPC8240 Integrated Processor User’s Manual

1.1 MPC8240 Integrated Processor Overview

The MPC8240 integrated processor is comprised of a peripheral logic block and a 32-bit superscalar PowerPC processor core, as shown in Figure 1-1.

Chapter 1. Overview 1-1

MPC8240 Integrated Processor Overview

MPC8240

Additional features:

• Prog I/O with Watchpoint

• JTAG/COP Interface

• Power Management

5 IRQs/

16 Serial

Interrupts

Processor Core Block

Processor

PLL

System

Unit

(SRU)

Peripheral Logic Block

Address

Message

Unit

(with I

DMA

Controller

EPIC

Interrupt

Controller

/Timers

(32 bit)

Address

Translator

Branch

Processing

Unit

(BPU)

Integer

Unit (IU)

Data (64 bit)

Central Control

Unit

Configuration

PCI Bus

Interface Unit

PCI

Arbiter

(64 bit) Two-instruction Fetch

Instruction Unit

(64-bit) T wo-instruction Dispatch

Load/Store

Unit

(LSU)

Data Instruction

16-Kbyte

Data

Cache

Peripheral Logic

Bus

Data Path

ECC Controller

Memory

Controller

Registers

Peripheral Logic

PLL

DLL

Fanout Buffers

Floating-

Point

Unit

(FPU)

64 bit

ROM/Flash/Port X

MMUMMU

16-Kbyte

Instruction

Cache

Data Bus

(32- or 64-bit)

with 8-bit Parity

or ECC

Address/Control DRAM/SDRAM/

SDRAM Sync In SDRAM Sync Out

SDRAM Clocks

PCI Clock In

PCI Bus Clocks

32-Bit OSC InFive

PCI Interface

Request/Grant

Pairs

Figure 1-1. MPC8240 Integrated Processor Functional Block Diagram

The peripheral logic integrates a PCI bridge, memory controller, DMA controller, EPIC interrupt controller, a message unit (and I

O controller), and an I2C controller. The

processor core is a full-featured, high-performance processor with ﬂoating-point support,

1-2 MPC8240 Integrated Processor User’s Manual

MPC8240 Integrated Processor Overview

memory management, 16-Kbyte instruction cache, 16-Kbyte data cache, and power management features. The integration reduces the overall packaging requirements and the number of discrete devices required for an embedded system.

The MPC8240 contains an internal peripheral logic bus that interfaces the processor core to the peripheral logic. The core can operate at a variety of frequencies, allowing the designer to trade off performance for power consumption. The processor core is clocked from a separate PLL, which is referenced to the peripheral logic PLL. This allows the microprocessor and the peripheral logic block to operate at different frequencies, while maintaining a synchronous bus interface. The interface uses a 64- or 32-bit data bus (depending on memory data bus width) and a 32-bit address bus along with control signals that enable the interface between the processor and peripheral logic to be optimized for performance. PCI accesses to the MPC8240’s memory space are passed to the processor bus for snooping when snoop mode is enabled.

The processor core and peripheral logic are general-purpose in order to serve a variety of embedded applications. The MPC8240 can be used as either a PCI host or PCI agent controller.

1.1.1 MPC8240 Integrated Processor Features

This section summarizes the features of the MPC8240. Major features of the MPC8240 are as follows:

• Peripheral logic — Memory interface

– Programmable timing supporting either FPM DRAM, EDO DRAM or

SDRAM – High-bandwidth bus (32-/64-bit data bus) to DRAM – Supports one to eight banks of 4-, 16-, 64-, or 128-Mbit memory devices – Supports 1-Mbyte to 1-Gbyte DRAM memory – 16 Mbytes of ROM space – 8-, 32-, or 64-bit ROM – Write buffering for PCI and processor accesses – Supports normal parity, read-modify-write (RMW), or ECC – Data-path buffering between memory interface and processor – Low-voltage TTL logic (LVTTL) interfaces – Port X: 8-, 32-, or 64-bit general-purpose I/O port using ROM controller

interface with programmable address strobe timing

— 32-bit PCI interface operating up to 66 MHz

– PCI 2.1-compliant

Chapter 1. Overview 1-3

MPC8240 Integrated Processor Overview

– PCI 5.0-V tolerance – Support for PCI locked accesses to memory – Support for accesses to PCI memory, I/O, and conﬁguration spaces – Selectable big- or little-endian operation – Store gathering of processor-to-PCI write and PCI-to-memory write accesses – Memory prefetching of PCI read accesses – Selectable hardware-enforced coherency – PCI bus arbitration unit (ﬁve request/grant pairs) – PCI agent mode capability – Address translation unit – Some internal conﬁguration registers accessible from PCI

— Two-channel integrated DMA controller (writes to ROM/Port X not supported)

– Supports direct mode or chaining mode (automatic linking of DMA transfers) – Supports scatter gathering—read or write discontinuous memory – Interrupt on completed segment, chain, and error – Local-to-local memory – PCI-to-PCI memory – PCI-to-local memory – PCI memory-to-local memory

— Message unit

– Two doorbell registers – Two inbound and two outbound messaging registers

O message controller

–I

C controller with full master/slave support (except broadcast all)

—I — Embedded programmable interrupt controller (EPIC)

– Five hardware interrupts (IRQs) or 16 serial interrupts – Four programmable timers

— Integrated PCI bus and SDRAM clock generation — Programmable PCI bus and memory interface output drivers

• Dynamic power management—Supports 60x nap, doze, and sleep modes

• Programmable input and output signals with watchpoint capability

• Built-in PCI bus performance monitor facility — Debug features

– Memory attribute and PCI attribute signals – Debug address signals

1-4 MPC8240 Integrated Processor User’s Manual

MPC8240 Integrated Processor Overview

– MIV signal: Marks valid address and data bus cycles on the memory bus. – Error injection/capture on data path – IEEE 1149.1 (JTAG)/test interface

• Processor core — High-performance, superscalar processor core — Integer unit (IU), ﬂoating-point unit (FPU) (software enabled or disabled),

load/store unit (LSU), system register unit (SRU), and a branch processing unit

(BPU) — 16-Kbyte instruction cache — 16-Kbyte data cache — Lockable L1 cache—entire cache or on a per-way basis

1.1.2 MPC8240 Integrated Processor Applications

The MPC8240 can be used for control processing in applications such as routers, switches, multi-channel modems, network storage, image display systems, enterprise I/O processor, Internet access device (IAD), disk controller for RAID systems, and copier/printer board control. Figure 1-2 shows the MPC8240 in the role of host processor.

MPC8240

DMA

MU(I2O)

I2C EPIC

Processor Core

PCI Bus

Peripheral 1 Peripheral 2

Peripheral

Logic

Peripheral 3

CTRL

ROM / Port X

PCI-to-PCI

Bridge

Data

PCI Bus

Figure 1-2. System Using an Integrated MPC8240 as a Host Processor

Figure 1-3 shows the MPC8240 in a peripheral processor application.

Local Memory: DRAM, EDO, SDRAM

Chapter 1. Overview 1-5

MPC8240 Integrated Processor Overview

Host Processor

Peripheral

MPC8240

Processor Core

PCI Bus

Host Bridge

Peripheral 2

CTRL

ROM / Port X

Peripheral PCI-to-PCI

Data

Host Memory

System

I/O

Controller

Local Memory: DRAM, EDO, SDRAM

Bridge

PCI Bus

Figure 1-3. Embedded System Using an MPC8240 as a Peripheral Processor

Figure 1-4 shows the MPC8240 as a distributed I/O processing device. The PCI-to-PCI bridge shown could be of the PCI type 0 variety. The MPC8240 would not be part of the system conﬁguration map. This conﬁguration is useful in applications such as RAID controllers, where the I/O devices shown are SCSI controllers, or multi-port network controllers where the devices shown are Ethernet controllers.

1-6 MPC8240 Integrated Processor User’s Manual

Processor Core Overview

Host Processor

Host Bridge

PCI Bus

Peripheral Peripheral

1 3

Peripheral 2

Local PCI bus

MPC8240

DMA MU(I2O)

I2C

EPIC

Processor Core

PCI-to-PCI

Bridge

Peripheral

Logic

I/O I/O

CTRL

ROM / Port X

Data

Host Memory

DeviceDevice

Local Memory: DRAM, EDO, SDRAM

System

I/O

Controller

Figure 1-4. Embedded System Using an MPC8240 as a Distributed Processor

1.2 Processor Core Overview

The MPC8240 contains an embedded version of the PowerPC 603e™ processor. For detailed information regarding the processor refer to the following:

• MPC603e & EC603e User’s Manual (Those chapters that describe the programming model, cache model, memory management model, exception model, and instruction timing)

• PowerPC Microprocessor Family: The Programming Environments for 32-Bit Microprocessors

This section is an overview of the processor core, provides a block diagram showing the major functional units, and describes brieﬂy how those units interact. For more information, refer to Chapter 2, “PowerPC Processor Core.”

The processor core is a low-power implementation of the PowerPC microprocessor family of reduced instruction set computing (RISC) microprocessors. The processor core implements the 32-bit portion of the PowerPC architecture, which provides 32-bit ef fectiv e addresses, integer data types of 8, 16, and 32 bits, and ﬂoating-point data types of 32 and 64 bits.

Chapter 1. Overview 1-7

Processor Core Overview

The processor core is a superscalar processor that can issue and retire as many as three instructions per clock. Instructions can execute out of order for increased performance; however, the processor core makes completion appear sequential.

The processor core integrates ﬁve execution units—an integer unit (IU), a ﬂoating-point unit (FPU), a branch processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU). The ability to execute ﬁve instructions in parallel and the use of simple instructions with rapid execution times yield high efﬁciency and throughput. Most integer instructions execute in one clock cycle. On the processor core, the FPU is pipelined so a single-precision multiply-add instruction can be issued and completed every clock cycle.

The processor core supports integer data types of 8, 16, and 32 bits, and ﬂoating-point data types of 32 and 64 bits.

The processor core provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed caches for instructions and data and on-chip instruction and data memory management units (MMUs). The MMUs contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers (DTLB and ITLB) that provide support for demand-paged virtual memory address translation and variable-sized block translation. The TLBs and caches use a least recently used (LRU) replacement algorithm. The processor also supports block address translation through the use of two independent instruction and data block address translation (IBAT and DBAT) arrays of four entries each. Effective addresses are compared simultaneously with all four entries in the BAT array during block translation. In accordance with the PowerPC architecture, if an effective address hits in both the TLB and BAT array, the BAT translation takes priority.

As an added feature to the processor core, the MPC8240 can lock the contents of one to three ways in the instruction and data cache (or an entire cache). For example, this allows embedded applications to lock interrupt routines or other important (time-sensitive) instruction sequences into the instruction cache. It allows data to be locked into the data cache, which may be important to code that must have deterministic execution.

The processor core has a selectable 32- or 64-bit data bus and a 32-bit address bus. The processor core supports single-beat and burst data transfers for memory accesses, and supports memory-mapped I/O operations.

Figure 1-5 provides a block diagram of the MPC8240 processor core that shows how the execution units (IU, FPU, BPU, LSU, and SR U) operate independently and in parallel. Note that this is a conceptual diagram and does not attempt to show how these features are physically implemented on the chip.

1-8 MPC8240 Integrated Processor User’s Manual

Processor Core Overview

64 Bit

SYSTEM

UNIT

INTEGER

UNIT

+*/

XER

COMPLETION

UNIT

Power

Dissipation

Control

JTAG/COP

Interface

GPR File

GP Rename

Registers

Time Base

Counter/

Decrementer

Clock

Multiplier

SEQUENTIAL

FETCHER

64 Bit

INSTRUCTION

QUEUE

Dispatch Unit

64 Bit

LOAD/STORE

UNIT

32 Bit

D MMU

SRs

DBAT

Array

DTLB

16Kbyte

1.3 Peripheral Logic Bus

The MPC8240 contains an internal peripheral logic bus that interfaces the processor core to the peripheral logic. The core can operate at a variety of frequencies allowing the designer to balance performance and power consumption. The processor core is clocked from a separate PLL, which is referenced to the peripheral logic PLL. This allows the microprocessor and the peripheral logic to operate at different frequencies while maintaining a synchronous bus interface.

The processor core-to-peripheral logic interface includes a 32-bit address bus, a 32- or 64-bit data bus as well as control and information signals. The peripheral logic bus allows for internal address-only transactions as well as address and data transactions. The processor core control and information signals include the address arbitration, address start, address transfer, transfer attribute, address termination, data arbitration, data transfer, data termination, and processor state signals. Test and control signals provide diagnostics for selected internal circuits.

The peripheral logic interface supports bus pipelining, which allows the address tenure of one transaction to overlap the data tenure of another . PCI accesses to the memory space are monitored by the peripheral logic bus to allow the processor to snoop these accesses (when snooping not explicitly disabled).

As part of the peripheral logic bus interface, the processor core’s data bus is conﬁgured at power-up to either a 32- or 64-bit width. When the processor is conﬁgured with a 32-bit data bus, memory accesses on the peripheral logic bus interface allow transfer sizes of 8, 16, 24, or 32 bits in one bus clock cycle. Data transfers occur in either single-beat transactions, or two-beat or eight-beat burst transactions, with a single-beat transaction transferring as many as 32 bits. Single- or double-beat transactions are caused by noncached accesses that access memory directly (that is, reads and writes when caching is disabled, caching-inhibited accesses, and stores in write-through mode). Eight-beat burst transactions, which always transfer an entire cache line (32 bytes), are initiated when a line is read from or written to memory.

When the peripheral logic bus interface is conﬁgured with a 64-bit data bus, memory accesses allow transfer sizes of 8, 16, 24, 32, or 64 bits in one bus clock cycle. Data transfers occur in either single-beat transactions or four-beat burst transactions. Single-beat transactions are caused by noncached accesses that access memory directly (that is, reads and writes when caching is disabled, caching-inhibited accesses, and stores in write-through mode). Four-beat burst transactions, which always transfer an entire cache line (32 bytes), are initiated when a block is read from or written to memory.

1-10 MPC8240 Integrated Processor User’s Manual

Peripheral Logic Overview

1.4 Peripheral Logic Overview

The peripheral logic block integrates a PCI bridge, memory controller, DMA controller, EPIC interrupt controller/timers, a message unit with an Intelligent Input/Output (I message controller, and an Inter-Inte grated Circuit (I

C) controller. The integration reduces the overall packaging requirements and the number of discrete devices required for an embedded system.

Figure 1-6 shows the major functional units within the peripheral logic block. Note that this is a conceptual block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented.

Peripheral Logic

Bus

Peripheral Logic Block

Data (64-Bit)

Central Control

Unit

Configuration

PCI Bus

Interface Unit

PCI

Arbiter

Registers

Peripheral Logic

Five Request/Grant Pairs

Data Path

ECC Controller

Memory

Controller

PLL

I2C

5 IRQs/

16 Serial

Interrupts

Message

Unit

(with I

DMA

Controller

EPIC

Interrupt

Controller

/Timers

Address (32-Bit)

Address

Translator

32-Bit

PCI Interface

Figure 1-6. MPC8240 Peripheral Logic Block Diagram

1.4.1 Peripheral Logic Features

Major features of the peripheral logic are as follows:

• Peripheral logic bus — Supports various operating frequencies and bus divider ratios — 32-bit address bus, 64-bit data bus — Supports full memory coherency

DLL

Fanout Buffers

OSC_IN

Data Bus (32- or 64-bit) with 8-bit Parity or ECC

Memory/ROM/ Port X Control/Address

SDRAM_SYNC_IN SDRAM Clocks

PCI_SYNC_IN

PCI Bus

Clocks

Chapter 1. Overview 1-11

Peripheral Logic Overview

— Decoupled address and data buses for pipelining of peripheral logic bus accesses — Store gathering on peripheral logic bus-to-PCI writes

• Memory interface — 1 Gbyte of RAM space, 16 Mbytes of ROM space — High-bandwidth, 64-bit data bus (72 bits including parity or ECC) — Supports fast page mode DRAMs, extended data out (EDO) DRAMs, or

synchronous DRAMs (SDRAMs)

— Supports 1 to 8 banks of DRAM/EDO/SDRAM with sizes ranging from 1 to

128 Mbytes per bank — Supports page mode SDRAMs—four open pages simultaneously — DRAM/EDO conﬁgurations support parity or error checking and correction

(ECC); SDRAM conﬁgurations support ECC — ROM space may be split between the PCI bus and the memory bus (8 Mbytes

each) — Supports 8-bit asynchronous ROM, or 32- or 64-bit burst-mode ROM — Supports writing to ﬂash ROM — Conﬁgurable data path — Programmable interface timing

• PCI interface — Compatible with PCI Local Bus Speciﬁcation, Revision 2.1 — Supports PCI locked accesses to memory using the LOCK

signal and protocol — Supports accesses to all PCI address spaces — Selectable big- or little-endian operation — Store gathering on PCI writes to memory — Selectable memory prefetching of PCI read accesses — Interface operates at up to 66 MHz — Parity support

• Supports concurrent transactions on peripheral logic bus and PCI buses

1.4.2 Peripheral Logic Functional Units

The peripheral logic consists of the following major functional units:

• Peripheral logic bus interface

• Memory interface

• PCI interface — PCI bus arbitration unit — Address maps and translation

1-12 MPC8240 Integrated Processor User’s Manual

Peripheral Logic Overview

— Big-and little-endian modes — PCI agent capability — PCI bus clock buffers and bus ratios

• DMA controller

• Message unit — Doorbell registers — Message registers

O support (circular queues)

—I

• Embedded programmable interrupt controller (EPIC) with four timers

•I

C interface

1.4.3 Memory System Interface

The MPC8240 memory interface controls processor and PCI interactions to main memory . It supports a variety of DRAM, and Flash or ROM conﬁgurations as main memory. The MPC8240 supports fast page mode (FPM), extended data out (EDO) and synchronous DRAM (SDRAM). The maximum supported memory size is 1 Gbyte of DRAM or SDRAM and 16 Mbytes of ROM/Flash. SDRAM must comply with the JEDEC SDRAM speciﬁcation.

The MPC8240 implements Port X, a memory bus interface that facilitates the connection of general-purpose I/O devices. The Port X functionality allows the designer to connect external registers, communication devices, and other such devices directly to the MPC8240. Some devices may require a small amount of external logic to generate properly address strobes, chip selects, and other signals.

The MPC8240 is designed to control a 32- or 64-bit data path to main memory DRAM or SDRAM. For a 32-bit data path, the MPC8240 can be conﬁgured to check and generate byte parity using four parity bits. For a 64-bit data path, the MPC8240 can be conﬁgured to support parity or ECC checking and generation with eight parity/syndrome bits checked and generated. Note that the data bus width (32- or 64-bit) chosen at reset for the 60x bus interface is also used for the memory interface.

The MPC8240 supports DRAM or SDRAM bank sizes from 1 to 128 Mbytes and provides bank start address and end address conﬁguration registers. Note that the MPC8240 does not support mixed DRAM/SDRAM conﬁgurations. The MPC8240 can be conﬁgured so that appropriate row and column address multiplexing occurs according to the accessed memory bank. Addresses are provided to DRAM and SDRAM through a 13-bit interface for DRAM and a 14-bit interface for SDRAM.

Two chip selects, one write enable, one output enable, and up to 21 address signals are provided for ROM/Flash systems.

Chapter 1. Overview 1-13

Peripheral Logic Overview

1.4.4 Peripheral Component Interconnect (PCI) Interface

The PCI interface for the MPC8240 is compliant with the Peripheral Component Interconnect Speciﬁcation Revision 2.1. The PCI interface provides mode-selectable, big-

to little-endian conversion. The MPC8240 provides an interface to the PCI bus running at speeds up to 66 MHz.

The MPC8240’s PCI interface can be conﬁgured as host or agent. In host mode, the interface acts as the main memory controller for the system and responds to all host memory transactions.

In agent mode, the MPC8240 can be conﬁgured to respond to a programmed window of PCI memory space. A variety of initialization modes are provided to boot the device.

1.4.4.1 PCI Bus Arbitration Unit

The MPC8240 contains a PCI bus arbitration unit, which eliminates the need for an external unit, thus lowering system complexity and cost. It has the following features:

• Five external arbitration signal pairs. The MPC8240 is the sixth member of the arbitration pool.

• The bus arbitration unit allows fairness as well as a priority mechanism.

• A two-level round-robin scheme is used in which each device can be programmed within a pool of a high- or low-priority arbitration. One member of the low-priority pool is promoted to the high-priority pool. As soon as it is granted the b us, it returns to the low-priority pool.

• The unit can be disabled to allow a remote arbitration unit to be used.

1.4.4.2 Address Maps and Translation

The MPC8240’s processor bus supports memory-mapped accesses. The address space is divided between memory and PCI according to one of two allowable address maps—map A and map B. Note that the support of map A is pro vided for backw ard compatibility only. It is strongly recommended that new designs use map B because map A may not be supported in future devices.

An inbound and outbound PCI address translation mechanism is provided to support the use of the MPC8240 in agent mode. Note that address translation is supported only for agent mode; it is not supported when the MPC8240 is operating in host mode. Also note that since agent mode is supported only for address map B, address translation is supported only for address map B.

When the MPC8240 is conﬁgured to be a PCI agent, the amount of local memory visible to the system is programmable. In addition, it may be necessary to map the local memory to a different system memory address space. The address translation unit handles the mapping of both inbound and outbound transactions for these cases.

1-14 MPC8240 Integrated Processor User’s Manual

Peripheral Logic Overview

1.4.4.3 Byte Ordering

The MPC8240 allows the processor to run in either big- or little-endian mode (except for the initial boot code which must run in big-endian mode).

1.4.4.4 PCI Agent Capability

In certain applications, the embedded system architecture dictates that the MPC8240 act as a peripheral processor. In this case, the peripheral logic must not act like a host bridge for the PCI bus. Instead it functions as a conﬁgurable device that is accessed by a host bridge. This capability allows multiple MPC8240 devices to coexist with other PCI peripheral devices on a single PCI bus. The MPC8240 has PCI 2.1- compliant conﬁguration capabilities.

1.4.5 DMA Controller

The integrated DMA controller contains two independent units. Note that the DMA writing capability for local memory is available for DRAM and SDRAM, but writing is not available for the ROM/Port X interface. Each DMA unit is capable of performing the following types of transfers:

• PCI-to-local memory

• Local-to-PCI memory

• PCI-to-PCI memory

• Local-to-local memory

The DMA controller allows chaining through local memory-mapped chain descriptors. Transfers can be scatter-gathered and misaligned. Interrupts are provided on completed segment, chain, and error conditions.

1.4.6 Message Unit (MU)

Many embedded applications require handshake algorithms to pass control, status, and data information from one owner to another. This is made easier with doorbell and message registers. The MPC8240 has a message unit (MU) that implements doorbell and message registers as well as an I and it uses the EPIC unit to signal external interrupts to the PCI interface and internal interrupts to the processor core.

1.4.6.1 Doorbell Registers

The MPC8240 MU contains one 32-bit inbound doorbell register and one 32-bit outbound doorbell register . The inbound doorbell re gister allo ws a remote processor to set a bit in the register from the PCI bus. This, in turn, generates an interrupt to the processor core.

The processor core can write to the outbound register, causing the outbound interrupt signal INT

A to assert, thus interrupting a host processor on PCI. When INTA is generated, it can be cleared only by the host processor by writing ones to the bits that are set in the outbound doorbell register.

O interface. The MU has many conditions that can cause interrupts,

Chapter 1. Overview 1-15

Peripheral Logic Overview

1.4.6.2 Inbound and Outbound Message Registers

The MPC8240 contains two 32-bit inbound message registers and two 32-bit outbound message registers. The inbound registers allo w a remote host or PCI master to write a 32-bit value, causing an interrupt to the processor core. The outbound registers allow the processor core to write an outbound message which causes the outbound interrupt signal INT

A to assert.

1.4.6.3 Intelligent Input/Output Controller (I2O)

The intelligent I/O speciﬁcation is an open standard that deﬁnes an abstraction layer interface between the OS and subsystem drivers. Messages are passed between the message abstraction layer from one device to another.

The I

O speciﬁcation describes a system as being made up of host processors and

input/output platforms (IOPs). The host processor is a single processor or a collection of processors working together to execute a homogenous operating system. An IOP consists of a processor, memory, and I/O interfaces. The IOP functions separately from other processors within the system to handle system I/O functions.

The I

O controller of the MU enhances communication between hosts and IOPs within a

system. There are two paths for messages—an inbound queue is used to transfer messages from a remote host or IOP to the processor core, and an outbound queue is used to transfer messages from the processor core to the remote host. Each queue is implemented as a pair of FIFOs. The inbound and outbound message queues each consists of a free_list FIFO and a post_list FIFO.

Messages are transferred between the host and the IOP using PCI memory-mapped registers. The MPC8240’s I

O controller facilitates moving the messages to and from the

inbound and outbound registers and local IOP memory. Interrupts signal the host and IOP to indicate the arrival of new messages.

1.4.7 Inter-Integrated Circuit (I2C) Controller

The I2C serial interface has become an industry de facto standard for communicating with low-speed peripherals. Typically, it is used for system management functions and EEPROM support. The MPC8240 contains an I

C controller with full master and slave

functionality.

1.4.8 Embedded Programmable Interrupt Controller (EPIC)

The integrated embedded programmable interrupt controller (EPIC) of the MPC8240 reduces the overall component count in embedded applications. The EPIC unit is designed to collect external and internal hardware interrupts, prioritize them, and deliv er them to the processor core.

1-16 MPC8240 Integrated Processor User’s Manual

Peripheral Logic Overview

The module operates in one of three modes:

• In direct mode, ﬁve level- or edge-triggered interrupts can be connected directly to an MPC8240.

• In pass-through mode, interrupts detected at the IRQ0 input are passed directly to the processor core. Also in this case, interrupts generated by the I controllers are passed to the L_INT

output signal.

O, I2C, and DMA

• The MPC8240 provides a serial delivery mechanism when more than ﬁve external interrupt sources are needed. The serial mechanism allows for up to 16 interrupts to be serially scanned into the MPC8240. This mechanism increases the number of interrupts without increasing the number of pins.

The outbound interrupt request signal, L_INT

, is used to signal interrupts to the host processor when the MPC8240 is conﬁgured for agent mode. The MPC8240 EPIC includes four programmable timers that can be used for system timing or for generating periodic interrupts.

1.4.9 Integrated PCI Bus and SDRAM Clock Generation

There are two PCI bus clocking solutions directed towards different system requirements. For systems where the MPC8240 is the host controller with a minimum number of clock loads, ﬁve clock fanout buffers are provided on-chip.

For systems requiring more clock fan out or where the MPC8240 is an agent device, external clock buffers may be used.

The MPC8240 provides an on-chip delay-locked loop (DLL) that supplies the external memory bus clock signals to SDRAM banks. The memory bus clock signals are of the same frequency and synchronous with the internal peripheral bus clock.

The four SDRAM clock outputs are generated by the internal DLL and can account for the trace length between SDRAM_SYNC_OUT signal and the SDRAM_SYNC_IN signal.

The MPC8240 requires a single clock input signal, PCI_SYNC_IN, which can be driven by the PCI clock fan-out buffers—speciﬁcally the PCI_SYNC_OUT output. PCI_SYNC_IN can also be driven by an external clock driver.

PCI_SYNC_IN is driven by the PCI bus frequenc y . An internal PLL, using PCI_SYNC_IN as a reference, generates an internal sys-logic-clk signal that is used for the internal logic. The peripheral bus clock frequency is conﬁgured at reset (by the MPC8240 PLL conﬁguration signals (PLL_CFG[0:4])) to be a multiple of the PCI_SYNC_IN frequency.

The internal clocking of the processor core is generated from and synchronized to the internal peripheral bus clock by means of a second PLL. The core’ s PLL provides multiples of the internal processor core clock rates as speciﬁed in the MPC8240 Hardware Speciﬁcation.

Chapter 1. Overview 1-17

Power Management

1.5 Power Management

TheMPC8240 provides both automatic and program-controllable power reduction modes for progressive reduction of power consumption.

The MPC8240 has independent power management functionality for both the processor core and the peripheral logic.The MPC8240 provides hardware support for three levels of programmable power reduction for both the processor and the peripheral logic. Doze, nap, and sleep modes are invoked by register programming—HID0 in the case of the processor core and conﬁguration registers in the case of the peripheral logic block.

The processor and peripheral logic blocks are both fully static, allowing internal logic states to be preserved during all power-saving modes. The following sections describe the programmable power modes.

1.5.1 Programmable Processor Power Management Modes

Table 1-1 summarizes the programmable power-saving modes for the processor core. These are very similar to those available in the MPC603e device.

Table 1-1. Programmable Processor Power Modes

PM Mode Functioning Units Activation Method Full-Power Wake Up Method

Full power All units active — — Full power

(with DPM) Doze Bus snooping

Nap Decrementer timer Controlled by software

Sleep None Controlled by software

Requested logic by demand

Data cache as needed Decrementer timer

By instruction dispatch —

Controlled by software

(write to HID0)

(write to HID0) and qualiﬁed with QA from peripheral logic

External asynchronous exceptions

(assertion of SMI Decrementer exception Hard or soft reset Machine check exception (mcp

External asynchronous exceptions

(assertion of SMI Decrementer exception Negation of QA Hard or soft reset Machine check exception (mcp

External asynchronous exceptions

(assertion of SMI Negation of QA Hard or soft reset Machine check exception (mcp

or int),

)

, or int)

CK by peripheral logic

)

, or int)

CK by peripheral logic

)

1.5.2 Programmable Peripheral Logic Power Management Modes

The following subsections describe the power management modes of the peripheral logic. Table 1-2 summarizes the programmable power-saving modes for the peripheral logic block.

1-18 MPC8240 Integrated Processor User’s Manual

Programmable I/O Signals with Watchpoint

Mode

Full power

Doze PCI address decoding and bus arbiter

Nap PCI address decoding and bus arbiter

Sleep PCI bus arbiter

1 2

All units active — —

System RAM refreshing Processor bus request and NMI monitoring EPIC unit I PLL

System RAM refreshing (can be disabled) Processor bus request and NMI monitoring EPIC unit I PLL (can be disabled)

Programmable option based on value of PICR1[MCP_EN] = 1 A PCI access to memory in nap mode does not cause QACK to negate; consequently, it does not wake up the

processor core, and the processor core won’t snoop this access. After servicing the PCI access, the peripheral logic automatically returns to the nap mode.

Table 1-2. Peripheral Logic Power Modes Summary

Functioning Units Activation Method

Controlled by software (write to PMCR1)

C unit

Controlled by software (write to PMCR1) and processor core in nap or

C unit

sleep mode (QREQ asserted)

Controlled by software (write to PMCR1) and processor core in nap or sleep mode (QREQ asserted)

Full-Power W ake Up

Method

PCI access to memory Processor bus request Assertion of NMI Interrupt to EPIC Hard Reset

Processor bus request Assertion of NMI Interrupt to EPIC Hard Reset

1.6 Programmable I/O Signals with Watchpoint

The MPC8240 programmable I/O facility allows the system designer to monitor the peripheral logic bus. Up to two watchpoints and their respecti ve 4-bit countdown v alues can be programmed. When the programmed threshold of the selected watchpoint is reached, an external trigger signal is generated.

1.7 Debug Features

The MPC8240 includes the following debug features:

• Memory attribute and PCI attribute signals

• Debug address signals

• MIV

• Error injection/capture on data path

• IEEE 1149.1 (JTAG)/test interface

signal: Marks valid address and data bus cycles on the memory bus.

Chapter 1. Overview 1-19

Debug Features

1.7.1 Memory Attribute and PCI Attribute Signals

The MPC8240 provides additional information corresponding to memory and PCI activity on several signals to assist with system debugging. The two types of attribute signals are described as follows:

• The memory attribute signals are associated with the memory interface and provide information concerning the source of the memory operation being performed by the MPC8240.

• The PCI attribute signals are associated with the PCI interface and provide information concerning the source of the PCI operation being performed by the MPC8240.

1.7.2 Memory Debug Address

When enabled, the debug address provides software disassemblers a simple way to reconstruct the 30-bit physical address for a memory bus transaction to DRAM and SDRAM, ROM, FLASH, or PortX. For DRAM or SDRAM, these 16 deb ug address signals are sampled with the column address and chip-selects. For ROMs, FLASH, and PortX devices, the debug address pins are sampled at the same time as the ROM address and can be used to recreate the 24-bit physical address in conjunction with ROM address. The granularity of the reconstructed physical address is limited by the bus width of the interface; double-words for 64-bit interfaces, words for 32-bit interfaces, and bytes for 8-bit interfaces.

1.7.3 Memory Interface Valid (MIV)

The memory interface valid signal, MIV, is asserted whenever FPM, EDO, SDRAM, FLASH, or ROM addresses or data are present on the external memory bus. It is intended to help reduce the number of bus cycles that logic analyzers must store in memory during a debug trace.

1.7.4 Error Injection/Capture on Data Path

The MPC8240 provides hardware to exercise and debug the ECC and parity logic by allowing the user to inject multi-bit stuck-at faults onto the peripheral logic or memory data/parity buses and to capture the data/parity output on receipt of an ECC or parity error .

1.7.5 IEEE 1149.1 (JTAG)/Test Interface

The processor core provides IEEE 1149.1 functions for facilitating board testing and debugging. The IEEE 1149.1 test interface provides a means for boundary-scan testing the processor core and the board to which it is attached.

1-20 MPC8240 Integrated Processor User’s Manual

Chapter 2 Signal Descriptions and Clocking

This chapter provides descriptions of the MPC8240’s external signals. It describes each signal’s beha vior when the signal is asserted and neg ated and when the signal is an input or an output.

NOTE:

A bar over a signal name indicates that the signal is active low—for example, AS referred to as asserted (active) when they are low and negated when they are high. Signals that are not active low, such as NMI (nonmaskable interrupt), are referred to as asserted when they are high and negated when they are low.

Internal signals are depicted as lower case and in italics. For example, sys_logic_clk is an internal signal. These are referenced only as necessary for understanding of the external functionality of the device.

The chapter is organized into the following sections:

• Overview of signals and complete cross-reference for signals that serve multiple functions. Includes listing of output signal states at reset.

• Signal description section that provides a detailed description of each signal, listed by functional block

• A complete section on the operation of the many input and output clock signals on the MPC8240, and the interactions between these signals

• A listing of the reset conﬁguration signals and the modes they deﬁne

(address strobe). Active-low signals are

2.1 Signal Overview

The MPC8240’s signals are grouped as follows:

• PCI interface signals

• Memory interface signals

• EPIC control signals

•I

C interface signals

Chapter 2. Signal Descriptions and Clocking 2-1

Signal Overview

• System control, power management, and debug signals

• Test/conﬁguration signals

• Clock signals

Figure 2-1 illustrates the external signals of the MPC8240, showing how the signals are grouped. Refer to the MPC8240 Hardware Speciﬁcation for a pinout diagram showing actual pin numbers and a listing of all the electrical and mechanical speciﬁcations.

2-2 MPC8240 Integrated Processor User’s Manual

PCI Interface

Memory Interface

EPIC Control

REQ[3:0]

/DA4*

REQ4 GNT

[3:0]

GNT4

/DA5*

AD[31:0]

PAR C/BE[3:0] DEVSEL

FRAME IRDY LOCK TRDY

PERR SERR STOP INTA IDSEL

RAS

[0:7]/CS[0:7]

CAS

[0:7]/DQM[0:7] WE SDMA[11:0] SDMA12/SDBA1 SDBA0 MDH[0:31] MDL[0:31] PAR[0:7]/AR[19:12] CKE SDRAS SDCAS RCS0 RCS1 FOE

AS IRQ0/S_INT

IRQ1/S_CLK IRQ2/S_RST IRQ3/S_FRAME IRQ4/L_INT

4 1

32 1 4 1 1 1 1 1 1 1 1

1 1

8 8 1 12 1 1 32 32 8 1 1 1 1 1 1 1

1 1 1 1 1

PCI_CLK[0:4]/DA3*

PCI_SYNC_OUT

PCI_SYNC_IN

SDRAM_CLK[0:3]

SDRAM_SYNC_OUT

SDRAM_SYNC_IN

CKO/DA1*

OSC_IN

HRST_CTRL

HRST_CPU

SRESET

MCP

NMI

SMI

CHKST

1 1 1 1

3 3 6 1

5 1 1 1 1 1

1 1

OP_IN

TBEN

CK/DA[0]*

QA TRIG_IN

TRIG_OUT

MAA[0:2] PMAA[0:2] DA[15:11], DA2 MIV

PLL_CFG[0:4]/DA[10:6]* TCK TDI TDO TMS TRST

SDA SCL

* Reference Table 15-5 Memory Debug

Address Signal Deﬁnitions

Signal Overview

Clock

System Control & Power Management

Debug

Test/ Configuration

I2C Control

Figure 2-1. MPC8240 Signal Groupings

Chapter 2. Signal Descriptions and Clocking 2-3

Signal Overview

2.1.1 Signal Cross Reference

The following sections are intended to provide a quick summary of signal functions. T able 2-1 provides an alphabetical cross-reference to the signals of the MPC8240. It details the signal name, interface, alternate functions, number of signals, whether the signal is an input, output, or bidirectional, and ﬁnally a pointer to the section in this chapter where the signal is described.

Table 2-1. MPC8240 Signal Cross Reference

Signal Signal Name Interface

AD[31:0] Address/data PCI — 32 I/O 2.2.1.3 AR[19:12] ROM address 19–12 Memory PAR[0:7] 8 O 2.2.2.11

[0:7] Column address strobe

CAS

C/BE

[3:0] Command/byte enable PCI — 4 I/O 2.2.1.5

OP_IN Checkstop in System Control — 1 I 2.2.5.6

CHKST

CKE CKO Debug clock Clock DA1 1 O 2.2.7.8

[0:7] SDRAM chip select Memory RAS[0:7] 8 O 2.2.2.3

CS DA[15:11], DA2 Debug addr [15:11, 2] Debug — 6 O 2.2.5.10.3 DA[10:6] Debug addr [10:6] Debug PLL_CFG[0:4] 5 O 2.2.5.10.3 DA5

DA4 DA3 DA1 DA0

DEVSEL DQM[0:7] SDRAM data qualiﬁer Memory CAS

FOE FRAME

[3:0]

GNT GNT4

HRST_CPU HRST_CTRL

IDSEL ID select PCI — 1 I 2.2.1.15 INTA Interrupt request PCI — 1 O 2.2.1.14 IRD IRQ0 Interrupt 0 EPIC Control S_INT 1 I 2.2.3.1 IRQ1 Interrupt 1 EPIC Control S_CLK 1 I/O 2.2.3.1

/DA5

Y Initiator ready PCI — 1 I/O 2.2.1.8

Address strobe Memory — 1 O 2.2.2.18

0–7

SDRAM clock enable Memory — 1 O 2.2.2.12

Debug addr 5 Debug addr 4 Debug addr 3 Debug addr 1 Debug addr 0

Device select PCI — 1 I/O 2.2.1.6

Flash output enable Memory — 1 O 2.2.2.17 Frame PCI — 1 I/O 2.2.1.7 PCI bus grant PCI GNT0: PCI bus

Hard reset (processor) System Control — 1 I 2.2.5.1.1 Hard reset (peripheral

logic)

Memory DQM[0:7] 8 O 2.2.2.2

Debug GNT4

System Control — 1 I 2.2.5.1.2

Alternate

Function (s)

REQ4

PCI_CLK4

CKO

[0:7] 8 O 2.2.2.4

request

GNT4

: DA5

Pins I/O Section #

5 O 2.2.5.10.3

5 O 2.2.1.2

2-4 MPC8240 Integrated Processor User’s Manual

Table 2-1. MPC8240 Signal Cross Reference (Continued)

Signal Overview

Signal Signal Name Interface

Alternate

Function (s)

Pins I/O Section #

IRQ2 Interrupt 2 EPIC Control S_RST 1 I/O 2.2.3.1 IRQ3 Interrupt 3 EPIC Control S_FRAME IRQ4 Interrupt 4 EPIC Control L_INT L_INT LOCK MAA[0:2]

MCP

Local interrupt EPIC Control IRQ4 1 I/O 2.2.3.3 Lock PCI — 1 I 2.2.1.9 Memory addr attributes Debug — 3 O 2.2.5.10.1 Machine check System Control — 1 O 2.2.5.3

1 I/O 2.2.3.1 1 I/O 2.2.3.1

MDH[0:31] Data bus high Memory — 32 I/O 2.2.2.9 MDL[0:31]

MDL0 MIV

Data bus low Memory — 32 I/O 2.2.2.9

Memory interface valid Debug — 1 O 2.2.5.10.4

NMI Nonmaskable interrupt System Control — 1 I 2.2.5.4 OSC_IN System clock input Clock — 1 I 2.2.7.1 PAR Parity PCI — 1 I/O 2.2.1.4 PAR[0:7] Data parity 0–7 Memory AR[19:12] 8 I/O 2.2.2.10 PCI_CLK[0:3]

PCI_CLK4/DA3

PCI clock outputs Clock PCI_CLK4:

DA3

5 O 2.2.7.2

PCI_SYNC_OUT PCI clock output Clock — 1 O 2.2.7.3 PCI_SYNC_IN PCI clock input Clock — 1 I 2.2.7.4 PERR PLL_CFG[0:4]

Parity error PCI — 1 I/O 2.2.1.11 PLL conﬁguration Test/Conﬁgurati

DA[10:6] 5 I 2.2.6.1

PCI addr. attributes Debug — 3 O 2.2.5.10.2 Quiesce acknowledge Power

DA0 1 O 2.2.5.8

PMAA[0:2] QA

Management

RAS

[0:7] Row address strobe 0–7 Memory CS[0:7] 8 O 2.2.2.1 RCS0 RCS1 REQ

REQ4

[3:0]

/DA4

ROM/bank 0 select Memory — 1 O 2.2.2.15 ROM/bank 1 select Memory — 1 O 2.2.2.16

REQ4

: PCI bus

grant

: DA4

I/O

2.2.1.1

PCI bus request PCI REQ0

S_CLK Serial interrupt clock EPIC Control IRQ1 1 I/O 2.2.3.2.2

SCL Serial clock I SDA Serial data I SDBA0 SDRAM bank select 0 Memory SDBA1 SDRAM bank select 1 Memory 1 O 2.2.2.8 SDCAS

SDRAM column access

C Control — 1 I/O 2.2.4.2

C Control — 1 I/O 2.2.4.1

1 O 2.2.2.8

See Table 6-2

Memory — 1 O 2.2.2.14

strobe

Chapter 2. Signal Descriptions and Clocking 2-5

Signal Overview

Table 2-1. MPC8240 Signal Cross Reference (Continued)

Signal Signal Name Interface

SDMA12 SDRAM address 12 Memory SDMA[11:0] SDRAM address 11–0 Memory 12 O 2.2.2.6 SDRAM_CLK[0:3] SDRAM clock outputs Clock — 4 O 2.2.7.5 SDRAM_SYNC_OUT SDRAM clock output Clock — 1 O 2.2.7.6 SDRAM_SYNC_IN SDRAM feedback clock Clock — 1 I 2.2.7.7 SDRAS

SERR S_FRAME S_INT Serial interrupt stream EPIC Control IRQ0 1 I 2.2.3.2.1 SMI

S_RST Serial interrupt reset EPIC Control IRQ2 1 I/O 2.2.3.2.3 SRESET Soft reset System Control — 1 I 2.2.5.2

OP Stop PCI — 1 I/O 2.2.1.13

ST TBEN Time base enable System Control — 1 I 2.2.5.7 TCK JTAG test clock Test — 1 I 2.2.6.2 TDO JTAG test data output Test — 1 O 2.2.6.4 TDI JTAG test data Input Test — 1 I 2.2.6.3 TMS JTAG test mode select Test — 1 I 2.2.6.5

Y Target ready PCI — 1 I/O 2.2.1.10

TRD TRIG_IN Watchpoint trigger in System Control 1 I 2.2.5.9.1 TRIG_OUT Watchpoint trigger out System Control 1 O 2.2.5.9.2 TRST WE

The MPC8240 samples these signals at the negation of reset to determine the reset conﬁguration. After they are sampled, they assume their normal functions. See Section 2.4, “Conﬁguration Signals Sampled at Reset,” for more information about their function during reset.

SDRAM row address strobe

System error PCI — 1 I/O 2.2.1.12 Serial interrupt frame EPIC Control IRQ3 1 I/O 2.2.3.2.4

System management interrupt

JTAG test reset Test — 1 I 2.2.6.6 Write enable Memory — 1 O 2.2.2.5

Memory — 1 O 2.2.2.13

System Control — 1 I 2.2.5.5

Alternate

Function (s)

See Table 6-2

Pins I/O Section #

1 O 2.2.2.7

2.1.2 Output Signal States during Reset

When a system reset is recognized (assertion of HRST_CPU and HRST_CTRL), the MPC8240 aborts all current internal and external transactions, and releases all bidirectional I/O signals to a high-impedance state. See Section 13.2.1, “System Reset,” for a complete description of the reset functionality.

There are 19 signals that serve alternate functions as reset conﬁguration input signals during system reset. Their default values and the interpretation of their v oltage levels during reset are described in Section 2.4, “Conﬁguration Signals Sampled at Reset.”

2-6 MPC8240 Integrated Processor User’s Manual

Detailed Signal Descriptions

During reset, the MPC8240 ignores most input signals (except for PCI_SYNC_IN and the reset conﬁguration signals), and drives most of the output signals to an inactive state. T able 2-2 shows the states of the output-only signals that are not used as reset conﬁguration signals during system reset.

Table 2-2. Output Signal States During System Reset

Interface Signal State During System Reset

PCI GNT

Memory CAS/

Clock PCI_CLK[0:4]

System control TRIG_OUT High impedance Debug DA[15:11], DA2 Driven high Test/Conﬁguration TDO Negated

[3:0]

INT

DQM[0:7] Driven high

/CS[0:7]

RAS RCS1 SDRAS SDCAS WE

PAR[0:7]/AR[19:12], SDMA[11:0] SDMA12/SDBA1 SDBA0

PCI_SYNC_OUT SDRAM_CLK[0:3] SDRAM_SYNC_OUT CKO

High impedance

Negated

High impedance

Driven

2.2 Detailed Signal Descriptions

The following subsections describe the MPC8240 input and output signals, the meaning of their different states, and relative timing information for assertion and negation. In cases where signals serve multiple functions (and have multiple names), they are described individually for each function.

2.2.1 PCI Interface Signals

This section provides descriptions of the PCI interface signals on the MPC8240. Note that throughout this manual, signals and bits of the PCI interface are referenced in little-endian format. For more information on the operation of the MPC8240 PCI interface, see Chapter 7, “PCI Bus Interface. ” Refer to the PCI Local Bus Speciﬁcation, Revision 2.1 for a thorough description of the PCI local bus and speciﬁc signal-to-signal timing relationships for the PCI bus.

Chapter 2. Signal Descriptions and Clocking 2-7

Detailed Signal Descriptions

2.2.1.1 PCI Bus Request (REQ[4:0])—Input

The PCI bus request signals (REQ[4:0]) are inputs on the MPC8240, and they have a different meaning depending on whether the MPC8240 PCI arbiter is enabled or disabled. The PCI REQ

n signals are point-to-point, and every master has its own REQn signal.

2.2.1.1.1 PCI Bus Request (REQ

[4:0])—Internal Arbiter Enabled

The MPC8240 PCI arbiter is enabled by a low value on the reset conﬁguration pin MAA2 or by the setting of bit 15 of the PCI arbitration control register. In this case, the REQ signals are used in conjunction with the GNT masters. Following is the state meaning for the REQ

[4:0] signals as the arbiter for up to ﬁve PCI

[4:0] input signals in this case.

[4:0]

State Meaning Asserted—External devices are requesting control of the PCI bus.

The MPC8240 acts on the requests as described in Section 7.2, “PCI Bus Arbitration. ”

Negated—Indicates that no external devices are requesting the use of the PCI bus.

2.2.1.1.2 PCI Bus Request (REQ

[4:0])—Internal Arbiter Disabled

The MPC8240 PCI arbiter is disabled by a high value on the reset conﬁguration pin MAA2 or by the clearing of bit 15 of the PCI arbitration control register. In this case, the REQ0 becomes the PCI bus grant input for the MPC8240, and it is asserted when the external arbiter is granting the use of the PCI bus to the MPC8240. Note that if the REQ0 signal is asserted prior to the need to run a PCI transaction, then the MPC8240 GNT0

input

signal

will not assert (the bus is parked) when a PCI transaction is to be run. The REQ

the state meaning of the REQ0 State Meaning Asserted—The REQ0

[4:1] input signals are ignored when the internal arbiter is disabled. Following is

signal when the internal arbiter is disabled.

signal indicates that the MPC8240 is granted

control of the PCI bus. If REQ0

is asserted before the MPC8240 has a transaction to perform (that is, the MPC8240 is parked), the MPC8240 drives AD[31:0], C/BE

[3:0], and PAR to stable (but

meaningless) states until they are needed for a legitimate transaction. Negated—REQ0

is negated when the MPC8240 is not granted

control of the PCI bus.

2.2.1.2 PCI Bus Grant (GNT[4:0])—Output

The PCI bus grant (GNT[4:0]) signals are outputs on the MPC8240 and they have a different meaning depending on whether the MPC8240 PCI arbiter is enabled or disabled. The PCI GNT

2.2.1.2.1 PCI Bus Grant (GNT

The MPC8240 PCI arbiter is enabled by a low value on the reset conﬁguration pin MAA2 or by the setting of bit 15 of the PCI arbitration control register . In this case, the GNT

2-8 MPC8240 Integrated Processor User’s Manual

n signals are point-to-point; every master has its own GNTn signal.

[4:0])—Internal Arbiter Enabled

[4:0]

Detailed Signal Descriptions

signals are used in conjunction with the REQ[4:0] signals as the arbiter for up to ﬁve PCI masters. Following is the state meaning for the GNT

[4:0] input signals in this case.

State Meaning Asserted—The MPC8240 has granted control of the PCI bus to a

requesting master, using the priority scheme described in Section 7.2, “PCI Bus Arbitration.” The MPC8240 will assert only one GNT

n signal during any clock cycle.

Negated—Indicates that the MPC8240 has not granted control of the PCI bus and external devices may not initiate a PCI transaction.

2.2.1.2.2 PCI Bus Grant (GNT

[4:0])—Internal Arbiter Disabled

The MPC8240 PCI arbiter is disabled by a high value on the reset conﬁguration pin MAA2 or by the clearing of bit 15 of the PCI arbitration control register. In this case, the GNT0 becomes the PCI bus request output for the MPC8240 and is asserted when the MPC8240 needs to run a PCI transaction. If the REQ0 a PCI transaction, then the GNT0

signal will not assert (the bus is parked) when a PCI

transaction is to be run. Following is the state meaning for the GNT

input signal is asserted prior to the need to run

[4:0] input signals when

the internal arbiter is disabled. State Meaning Asserted—The MPC8240 asserts the GNT0

request output signal. GNT Negated—The GNT

mode. GNT0

is negated when the MPC8240 is not requesting control

[4:1] signals do not assert in this case.

[4:1] signals are driven high (negated) in this

signal as the PCI bus

of the PCI bus or the bus is parked on the MPC8240.

2.2.1.3 PCI Address/Data Bus (AD[31:0])

The PCI address/data bus (AD[31:0]) consists of 32 signals that are both input and output signals on the MPC8240.

2.2.1.3.1 Address/Data (AD[31:0])—Output

Following is the state meaning for AD[31:0] as outputs. State Meaning Asserted/Negated—Represents the physical address during the

address phase of a PCI transaction. During a data phase of a PCI transaction, AD[31:0] contain data being written.

The AD[7:0] signals deﬁne the least-signiﬁcant byte and AD[31:24] the most-signiﬁcant byte.

2.2.1.3.2 Address/Data (AD[31:0])—Input

Following is the state meaning for AD[31:0] as inputs. State Meaning Asserted/Negated—Represents the address to be decoded as a check

for device select during an address phase of a PCI transaction or data being received during a data phase of a PCI transaction.

Chapter 2. Signal Descriptions and Clocking 2-9

Detailed Signal Descriptions

2.2.1.4 Parity (PAR)

The PCI parity (PAR) signal is both an input and output signal on the MPC8240. See Section 7.6.1, “PCI Parity,” for more information on PCI parity.

2.2.1.4.1 Parity (PAR)—Output

Following is the state meaning for PAR as an output signal. State Meaning Asserted—This signal is driven by the MPC8240 to indicate odd

parity across the AD[31:0] and C/BE

[3:0] signals (driven by the

MPC8240) during the address and data phases of a transaction. Negated—Indicates even parity across the AD[31:0] and

C/BE

[3:0] signals driven by the MPC8240 during address and data

phases.

2.2.1.4.2 Parity (PAR)—Input

Following is the state meaning for PAR as an input signal. State Meaning Asserted—Indicates odd parity driven by another PCI master or the

PCI target during read data phases. Negated—Indicates even parity dri v en by another PCI master or the

PCI target during read data phases.

2.2.1.5 Command/Byte Enable (C/BE[3:0])

The four command/byte enable (C/BE[3:0]) signals are both input and output signals on the MPC8240.

2.2.1.5.1 Command/Byte Enable (C/BE

Following is the state meaning for C/BE State Meaning Asserted/Negated—During the address phase, C/BE

[3:0])—Output

[3:0] as output signals.

[3:0] deﬁne the bus command of the transaction initiated by the MPC8240 as a PCI master. Table 2-3 summarizes the PCI bus command encodings. See Section 7.3.2, “PCI Bus Commands,” for more detailed information on the bus commands.

During the data phase, C/BE

[3:0] are used as byte enables. Byte enables determine which byte lanes carry meaningful data. The C/BE0

signal applies to the least-signiﬁcant byte.

2-10 MPC8240 Integrated Processor User’s Manual

Table 2-3. PCI Command Encodings

C/BE[3:0] PCI Command

0000 Interrupt acknowledge 0001 Special cycle 0010 I/O read 0011 I/O write 0100 Reserved 0101 Reserved 0110 Memory read 0111 Memory write 1000 Reserved 1001 Reserved 1010 Conﬁguration read 1011 Conﬁguration write 1100 Memory read multiple 1101 Dual address cycle 1110 Memory read line 1111 Memory write and invalidate

The MPC8240 does not generate this command or the reserved commands.

Detailed Signal Descriptions

2.2.1.5.2 Command/Byte Enable (C/BE[3:0])—Input

Following is the state meaning for C/BE State Meaning Asserted/Negated—During the address phase, C/BE

[3:0] as input signals.

[3:0] indicate the command that another master is sending. The MPC8240 uses the value on these signals (in addition to the address) to determine whether it is a target for a transaction. T able 2-3 summarizes the PCI bus command encodings. See Section 7.3.3, “ Addressing,” for more information.

During the data phase, C/BE

[3:0] indicate which byte lanes are valid.

2.2.1.6 Device Select (DEVSEL)

The device select (DEVSEL) signal is both an input and output on the MPC8240.

2.2.1.6.1 Device Select (DEVSEL

Following is the state meaning for DEVSEL State Meaning Asserted—Indicates that the MPC8240 has decoded the address of a

PCI transaction, and it is the target of the current access. Negated—Indicates that the MPC8240 has decoded the address and

is not the target of the current access.

Chapter 2. Signal Descriptions and Clocking 2-11

)—Output

as an output.

Detailed Signal Descriptions

2.2.1.6.2 Device Select (DEVSEL)—Input

Following is the state meaning for DEVSEL

as an input signal.

State Meaning Asserted—Indicates that some PCI target (other than the MPC8240)

has decoded its address as the target of the current access. This is useful to the MPC8240 when it is the initiator of a PCI transaction.

Negated—Indicates that no PCI target has been selected.

2.2.1.7 Frame (FRAME)

The frame (FRAME) signal is both an input and output on the MPC8240.

2.2.1.7.1 Frame (FRAME

Following is the state meaning for FRAME State Meaning Asserted—Indicates that the MPC8240, acting as a PCI master, is

initiating a bus transaction. While FRAME may continue.

Negated—If IRD in the ﬁnal data phase. If IRD bus is idle.

2.2.1.7.2 Frame (FRAME

Following is the state meaning for FRAME State Meaning Asserted—Indicates that another PCI master is initiating a bus

transaction and causes the MPC8240 to decode the address and the command signals to see if it is the target of the transaction.

Negated—Indicates that the transaction is in the ﬁnal data phase or that the bus is idle.

)—Output

as an output.

is asserted, data transfers

Y is asserted, indicates that the PCI transaction is

Y is negated, it indicates that the PCI

)—Input

as an input signal.

2.2.1.8 Initiator Ready (IRDY)

The initiator ready (IRDY) signal is both an input and output on the MPC8240.

2.2.1.8.1 Initiator Ready (IRD

Following is the state meaning for IRD State Meaning Asserted—Indicates that the MPC8240, acting as a PCI master, can

complete the current data phase of a PCI transaction. During a write, the MPC8240 asserts IRD AD[31:0]. During a read, the MPC8240 asserts IRD it is prepared to accept data.

Negated—Indicates that the PCI target needs to wait before the MPC8240, acting as a PCI master, can complete the current data phase. During a write, the MPC8240 negates IRD

2-12 MPC8240 Integrated Processor User’s Manual

Y)—Output

Y as an output.

Y to indicate that valid data is present on

Y to indicate that

Y to insert a wait

Detailed Signal Descriptions

cycle when it cannot provide valid data to the target. During a read, the MPC8240 negates IRD

Y to insert a wait cycle when it cannot

accept data from the target.

2.2.1.8.2 Initiator Ready (IRD

Following is the state meaning for IRD

Y)—Input

Y as an input signal.

State Meaning Asserted—Indicates another PCI master is able to complete the

current data phase of a transaction. Negated—If FRAME

is asserted, it indicates a wait cycle from another master. This is used by the MPC8240 to insert wait cycles when it is a target of a PCI transaction. If FRAME

is negated, it

indicates the PCI bus is idle.

2.2.1.9 Lock (LOCK)—Input

The lock (LOCK) signal is an input on the MPC8240. See Section 7.5, “Exclusive Access,” for more information. Following is the state meaning for the LOCK

input signal.

State Meaning Asserted—Indicates that a master is requesting exclusive access to

memory, which may require multiple transactions to complete. Negated—Indicates that a normal operation is occurring on the bus,

or an access to a locked target is occurring.

2.2.1.10 Target Ready (TRDY)

The target ready (TRDY) signal is both an input and output signal on the MPC8240.

2.2.1.10.1 Targ et Ready (TRD

Following is the state meaning for TRD State Meaning Asserted—Indicates that the MPC8240, acting as a PCI target, can

complete the current data phase of a PCI transaction. During a read, the MPC8240 asserts TRD AD[31:0]. During a write, the MPC8240 asserts TRD that it is prepared to accept data.

Negated—Indicates that the PCI initiator needs to wait before the MPC8240, acting as a PCI target, can complete the current data phase. During a read, the MPC8240 negates TRD cycle when it cannot provide valid data to the initiator. During a write, the MPC8240 negates TRD cannot accept data from the initiator.

Y)—Output

Y as an output signal.

Y to indicate that valid data is present on

Y to indicate

Y to insert a wait

Y to insert a wait cycle when it

Chapter 2. Signal Descriptions and Clocking 2-13

Detailed Signal Descriptions

2.2.1.10.2 Targ et Ready (TRDY)—Input

Following is the state meaning for TRD

Y as an input signal.

State Meaning Asserted—Indicates another PCI target is able to complete the

current data phase of a transaction. If the MPC8240 is the initiator of the transaction, it latches the data (on a read) or cycles the data on a write.

Negated—Indicates a wait cycle needed by a target. If the MPC8240 is the initiator of the transaction, it waits to latch the data (on a read) or continues to drive the data (on a write).

2.2.1.11 Parity Error (PERR)

The PCI parity error (PERR) signal is both an input and output signal on the MPC8240. See Section 13.2.3.2, “Parity Error (PERR), ” and Section 4.8.2, “Error Enabling and Detection Registers, ” for more information on ho w the MPC8240 is set up to report parity errors. The PCI initiator drives PERR operations.

2.2.1.11.1 Parity Error (PERR

Following is the state meaning for PERR State Meaning Asserted—Indicates that the MPC8240, acting as a PCI agent,

2.2.1.11.2 Parity Error (PERR

on read operations; the PCI target drives PERR on write

)—Output

as an output signal.

detected a data parity error. Negated—Indicates no error.

)—Input

Following is the state meaning for PERR

as an input signal.

State Meaning Asserted—Indicates that another PCI agent detected a data parity

error while the MPC8240 was sourcing data (the MPC8240 was acting as the PCI initiator during a write, or was acting as the PCI target during a read).

Negated—Indicates no error.

2.2.1.12 System Error (SERR)

The PCI system error (SERR) signal is both an input and output signal on the MPC8240. It is an open-drain signal and can be driven by multiple devices on the PCI bus. Refer to Section 13.2.3.1, “System Error (SERR),” and Section 4.8.2, “Error Enabling and Detection Registers, ” for more information on how the MPC8240 dri ves and reports system errors.

2-14 MPC8240 Integrated Processor User’s Manual

2.2.1.12.1 System Error (SERR)—Output

Detailed Signal Descriptions

Following is the state meaning for SERR

as an output signal.

State Meaning Asserted—Indicates that an address parity error, a target-abort (when

the MPC8240 is acting as the initiator), or some other system error (where the result is a catastrophic error) was detected.

Negated—Indicates no error.

2.2.1.12.2 System Error (SERR

Following is the state meaning for SERR

)—Input

as an input signal.

State Meaning Asserted—Indicates that a target (other than the MPC8240) has

detected a catastrophic error. Negated—Indicates no error.

2.2.1.13 Stop (STOP)

The stop (STOP) signal is both an input and output signal on the MPC8240. Refer to Section 7.4.3.2, “Target-Initiated Termination,” for more information on the use of the ST

OP signal.

2.2.1.13.1 Stop (ST

Following is the state meaning for ST State Meaning Asserted—Indicates that the MPC8240, acting as a PCI target, is

OP)—Output

OP as an output signal.

requesting that the initiator stop the current transaction. Negated—Indicates that the current transaction can continue.

2.2.1.13.2 Stop (ST

Following is the state meaning for ST

OP)—Input

OP as an input signal.

State Meaning Asserted—Indicates that when the MPC8240 is acting as a PCI

initiator, it is receiving a request from the target to stop the current transaction.

Negated—Indicates that the current transaction can continue.

2.2.1.14 Interrupt Request (INTA)—Output

Following is the state meaning for INTA. This signal is primarily used when the MPC8240 is programmed in agent mode.

State Meaning Asserted—Indicates that the MPC8240 is requesting an interrupt on

the PCI bus. These interrupts are caused by the on-chip DMA controller and the message unit.

Negated—Indicates that the MPC8240 is not requesting an interrupt on the PCI bus.

Chapter 2. Signal Descriptions and Clocking 2-15

Detailed Signal Descriptions

2.2.1.15 ID Select (IDSEL)—Input

Following is the state meaning for IDSEL. See Section 7.3.3.3, “Conﬁguration Space Addressing, ” for more information about the role of the IDSEL signal in PCI conﬁguration transactions.

State Meaning Asserted—When the C/BE

[3:0] encoding is set to conﬁguration read/write, IDSEL indicates that the PCI conﬁguration registers on the MPC8240 are being accessed.

Negated—Indicates that there is no conﬁguration access for this device in progress.

Note that the MPC8240 must not issue PCI conﬁguration transactions to itself (that is, for PCI conﬁguration transactions initiated by the MPC8240, its IDSEL signal must not be asserted). The MPC8240 must use the method described in Section 4.1, “Conﬁguration Register Access,” to access its own conﬁguration registers. If the MPC8240 is in host mode and other PCI agents do not need to access the MPC8240’s conﬁguration space, then it is recommended that this signal be pulled down.

2.2.2 Memory Interface Signals

The memory interface supports either standard DRAMs, extended data out DRAMs (EDO DRAMs), or synchronous DRAMs (SDRAMs) and either standard ROM or Flash de vices. Some of the memory interface signals perform different functions (and are described by an alternate name) depending on the RAM and ROM conﬁgurations. This section provides a brief description of the memory interface signals on the MPC8240, listed individually by both their primary and alternate names, describing the relevant function in each section. F or more information on the operation of the memory interface, see Chapter 6, “MPC8240 Memory Interface.”

2.2.2.1 Row Address Strobe (RAS[0:7])—Output

The eight row address strobe (RAS[0:7]) signals are outputs on the MPC8240. Following are the state meaning and timing comments for the RAS

State Meaning Asserted—Indicates that the memory row address is valid and selects

one of the rows in the selected bank for DRAM memory. Negated—Indicates DRAM precharge period.

Timing Comments Assertion—The MPC8240 asserts the RAS

memory cycle. All other memory interface signal timings are referenced to RAS

2-16 MPC8240 Integrated Processor User’s Manual

n output signals.

n signal to begin a

Detailed Signal Descriptions

2.2.2.2 Column Address Strobe (CAS[0:7])—Output

The eight column address strobe (CAS[0:7]) signals are outputs on the MPC8240. CAS0 connects to the most-signiﬁcant byte select. CAS7 connects to the least-signiﬁcant byte select. When the MPC8240 is operating in 32-bit mode (see MCCR1[DBUS_SIZ[0:1]), the CAS

[0:3] signals are used. Following are the state meaning and timing comments for the

CAS

n output signals.

State Meaning Asserted—Indicates that the DRAM (or EDO) column address is

valid and selects one of the columns in the row. Negated—For DRAMs, it indicates CAS

n precharge, and that the current DRAM data transfer has completed. —or— For EDO DRAMs, it indicates CAS data transfer completes in the ﬁrst clock cycle of CAS

Timing Comments Assertion—The MPC8240 asserts CAS

after the assertion of RAS MCCR3[RCD

] parameter). See Section 6.3.5, “FPM or EDO

n (depending on the setting of the

n precharge, and that the current

n precharge.

n two to eight clock cycles

DRAM Interface Timing,” for more information.

2.2.2.3 SDRAM Command Select (CS[0:7])—Output

The eight SDRAM command select (CS[0:7]) signals are output on the MPC8240. Following are the state meaning and timing comments for the CS

State Meaning Asserted—Selects an SDRAM bank to perform a memory operation.

Negated—Indicates no SDRAM action during the current cycle.

Timing Comments Assertion—The MPC8240 asserts the CS

cycle. For SDRAM, CS

n is valid on the rising edge of the

SDRAM_CLK[0:3] clock signals.

n output signals.

n signal to begin a memory

2.2.2.4 SDRAM Data Input/Output Mask (DQM[0:7])—Output

The eight SDRAM data input/output mask (DQM[0:7]) signals are outputs on the MPC8240. Following are the state meaning and timing comments for the DQMn output signals. DQM0 connects to the most signiﬁcant byte select, and DQM7 connects to the least signiﬁcant byte select. Note that parity memory can be connected to any DQMn signal.

State Meaning Asserted—Prevents writing to SDRAM. Note that the DQMn

signals are active-high for SDRAM. DQMn is part of the SDRAM command encoding. See Section 6.2, “SDRAM Interface Operation,” for more information.

Negated—Allows a read or write operation to SDRAM.

Timing Comments Assertion—For SDRAM, DQMn is valid on the rising edge of the

SDRAM_CLK[0:3] clock signals during read or write cycles.

Chapter 2. Signal Descriptions and Clocking 2-17

Detailed Signal Descriptions

2.2.2.5 Write Enable (WE)—Output

The write enable (WE) signal is an output on the MPC8240. For SDRAM, WE is part of the SDRAM command encoding. See Section 6.2, “SDRAM Interface Operation,” for more information. Following are the state meaning and timing comments for the WE

output

signal for DRAM, ECO and Flash writes. State Meaning Asserted—Enables writing to DRAM, EDO, or Flash.

Negated—No DRAM, EDO, or Flash write operation is pending.

Timing Comments Assertion—For DRAM, the MPC8240 asserts WE

the column address and prior to CAS asserts WE

concurrent with SDCAS for write operations.

n. For SDRAM, the MPC8240

concurrent with

2.2.2.6 SDRAM Address (SDMA[11:0])—Output

The SDMA[11:0] signals carry 12 of the address bits for the memory interface. For (S)DRAMs, they correspond to the row and column address bits.

State Meaning Asserted/Negated—Contain different portions of the address

depending on the size of memory in use, the type of memory in use (DRAM, SDRAM, ROM or Flash) and the phase of the transaction. See Section 6.2.2, “SDRAM Address Multiplexing”, for a complete description of the mapping of these signals in all cases.

Timing Comments Assertion—For DRAM, the row address is considered valid on the

assertion of RAS of CAS

n. For SDRAM, the row address is v alid on the rising edge of SDRAM_CLK[0:3] clock signals when CS column address is valid on the rising edge of SDRAM_CLK[0:3] when DQMn is asserted. For ROM and Flash, the address is valid with the assertion of RCS0

n, and the column address is valid on the assertion

n is asserted and the

2.2.2.7 SDRAM Address 12 (SDMA12)—Output

The SDMA12 signal is similar to SDMA[11:0] in that it corresponds to different row or column address bits, depending on the memory in use.

State Meaning Asserted/Negated—See Section 6.2.2, “SDRAM Address

Multiplexing,” for a complete description of the mapping of this signal in all cases.

Timing Comments Assertion/Negation—The same as SDMA[11:0].

2.2.2.8 SDRAM Internal Bank Select 0–1 (SDBA0, SDBA1)—Output

The SDBA[0:1] signals are similar to SDMA[11:0] in that they correspond to dif ferent ro w or column address bits, depending on the memory in use. However, they are only used for the SDRAM interface. Note that SDBA1 is multiplexed with the SDMA12 signal.

2-18 MPC8240 Integrated Processor User’s Manual

Detailed Signal Descriptions

State Meaning Asserted/Negated—Selects the SDRAM internal bank to be

activated during the row address phase and selects the SDRAM internal bank for the read or write operation during the column address phase of the memory access. See Section 6.2.2, “SDRAM Address Multiplexing, ” for a complete description of the mapping of these signals in all cases.

Timing Comments Assertion/Negation—The row address is valid on the rising edge of

SDRAM_CLK[0:3] clock signals when CS

n is asserted and the column address is valid on the rising edge of SDRAM_CLK[0:3] when DQMn is asserted.

2.2.2.9 Memory Data Bus (MDH[0:31], MDL[0:31])

The memory data bus (MDH[0:31], MDL[0:31]) consists of 64 signals that are both input and output signals on the MPC8240. The data bus is comprised of two halves—data bus high (MDH[0:31]) and data bus low (MDL[0:31]).

The MPC8240 can also be conﬁgured to operate with a 32-bit data bus on the memory interface by driving the reset conﬁguration signal MDL0 low during reset. When the MPC8240 is conﬁgured with a 32-bit data bus, the bus operates in the same way as when conﬁgured with a 64-bit data bus, with the exception that only MDH[0:31] is used, and MDL[0:31] can be left ﬂoating. For more information on other data bus sizes available for the ROM/Flash/Port X interfaces, see Chapter 6, “MPC8240 Memory Interface.”

Table 2-4 speciﬁes the byte lane assignments (and data parity signal correspondence) for the transfer of an aligned double word in both 64- and 32-bit modes.

Table 2-4. Memory Data Bus Byte Lane Assignments

Data Bus Signals

64-Bit Mode 32-Bit Mode

MDH[0:7] 0 (MSB) 0 (MSB), 4 MDH[8:15] 1 1, 5 MDH[16:23] 2 2, 6 MDH[24:31] 3 3, 7 (LSB) MDL[0:7] 4 x MDL[8:15] 5 x MDL[16:23] 6 x MDL[24:31] 7 (LSB) x

Chapter 2. Signal Descriptions and Clocking 2-19

Byte Lane

Detailed Signal Descriptions

2.2.2.9.1 Memory Data Bus (MDH[0:31], MDL[0:31])—Output

Following are the state meaning and timing comments for the memory data bus as output signals.

State Meaning Asserted/Negated—Represents the value of data being driven by the

MPC8240.

Timing Comments Assertion/Negation—For DRAM accesses, the data bus signals are

valid when CAS

[0:7] and WE are asserted. For SDRAM, the data bus signals are valid on the next rising edge of SDRAM_CLK[0:3] after DQM[0:7] is asserted for a write command. For ROM/Flash memory and Port X, the data bus signals are valid on the assertion of RCS0

2.2.2.9.2 Memory Data Bus (MDH[0:31], MDL[0:31])—Input

Following are the state meaning and timing comments for the data bus as input signals. Note that MDL0 is a reset conﬁguration input signal.

State Meaning Asserted/Negated—Represents the value of data being driven by the

memory subsystem on a read.

Timing Comments Assertion/Negation—For a memory read transaction, the data bus

signals are valid at a time dependent on the memory interface conﬁguration parameters. Refer to Chapter 4, “Conﬁguration Registers, ” and Chapter 6, “MPC8240 Memory Interface,” for more information.

2.2.2.10 Data Parity/ECC (PAR[0:7])

The eight data parity/ECC (PAR[0:7]) signals are both input and output signals on the MPC8240.

2.2.2.10.1 Data Parity (PAR[0:7])—Output

Following are the state meaning and timing comments for PAR[0:7] as output signals. State Meaning Asserted/Negated—Represents the byte parity or ECC bits being

written to memory (PAR0 is the most-signiﬁcant parity bit and corresponds to byte lane 0 which is selected by CAS0 The data parity signals are asserted or negated as appropriate to provide odd parity (including the parity bit) or ECC.

Timing Comments Assertion/Negation—PAR[0:7] are valid concurrent with

MDH[0:31] and MDL[0:31].

2-20 MPC8240 Integrated Processor User’s Manual

or DQM0).

Detailed Signal Descriptions

2.2.2.10.2 Data Parity (PAR[0:7])—Input

Following are the state meaning and timing comments for PAR[0:7] as input signals. State Meaning Asserted/Negated—Represents the byte parity or ECC bits being

read from memory (PAR0 is the most-signiﬁcant parity bit and corresponds to byte lane 0 which is selected by CAS0

or DQM0).

Timing Comments Assertion/Negation—PAR[0:7] are valid concurrent with

MDH[0:31] and MDL[0:31].

2.2.2.11 ROM Address 19:12 (AR[19:12])—Output

The ROM address 19–12 (AR[19:12]) signals are output signals only for the R OM address function. Note that these signals are both input and output signals for the memory parity function (PAR[0:7]). Following are the state meaning and timing comments for AR[19:12] as output signals.

State Meaning Asserted/Negated—Represents bits 19–12 of the ROM/Flash

address. The other ROM address bits are provided by AR[10:0] as shown in Section 6.4.1, “ROM/Flash Address Multiplexing.”

Timing Comments Assertion/Negation—The ROM address is valid on assertion of

RCS0

or RCS1.

2.2.2.12 SDRAM Clock Enable (CKE)—Output

The SDRAM clock enable (CKE) signal is an output on the MPC8240 (and is also used as a reset conﬁguration input signal). CKE is part of the SDRAM command encoding. See Section 6.2, “SDRAM Interface Operation,” for more information. Following are the state meaning and timing comments for the CKE output signal.

State Meaning Asserted—Enables the internal clock circuit of the SDRAM memory

device. Negated—Disables the internal clock circuit of the SDRAM

memory device.

Timing Comments Assertion—CKE is valid on the rising edge of the

SDRAM_CLK[0:3] clock signals. See Section 6.2, “SDRAM Interface Operation,” for more information.

2.2.2.13 SDRAM Row Address Strobe (SDRAS)—Output

The SDRAM row address strobe (SDRAS) signal is an output on the MPC8240. Follo wing are the state meaning and timing comments for the SDRAS

State Meaning Asserted/Negated—SDRAS

is part of the SDRAM command encoding and is used for SDRAM bank selection during read or write operations. See Section 6.2, “SDRAM Interface Operation,” for more information.

Chapter 2. Signal Descriptions and Clocking 2-21

output signal.

Detailed Signal Descriptions

Timing Comments Assertion—SDRAS is valid on the rising edge of the SDRAM clock

when a CS

n signal is asserted.

2.2.2.14 SDRAM Column Address Strobe (SDCAS)—Output

The SDRAM column address strobe (SDCAS) signal is an output on the MPC8240. Following are the state meaning and timing comments for the SDCAS

State Meaning Asserted—SDCAS

is part of the SDRAM command encoding and is

output signal.

used for SDRAM column selection during read or write operations. See Section 6.2, “SDRAM Interface Operation,” for more information.

Negated—SDCAS

is part of SDRAM command encoding used for

SDRAM column selection during read or write operations.

Timing Comments Assertion—For SDRAM, SDCAS

SDRAM clock when a CS

n signal is asserted.

is valid on the rising edge of the

2.2.2.15 ROM Bank 0 Select (RCS0)—Output

The ROM bank0 select (RCS0) signal is an output on the MPC8240 (and a reset conﬁguration input signal). Following are the state meaning and timing comments for the RCS0

output signal.

State Meaning Asserted—Selects ROM bank 0 for a read access or Flash bank 0 for

a read or write access. Negated—Deselects bank 0, indicating no pending memory access

to ROM/Flash.

Timing Comments Assertion—The MPC8240 asserts RCS0

access cycle. Negation—Controlled by the ROMFAL and ROMNAL parameters

of the MCCR1 register.

at the start of a ROM/Flash

2.2.2.16 ROM Bank 1 Select (RCS1)—Output

The ROM bank 1 select (RCS1) signal is an output on the MPC8240. Following are the state meaning and timing comments for the RCS1

State Meaning Asserted—Selects ROM bank 1 for a read access or Flash bank 1 for

a read or write access. Negated—Deselects bank 1, indicating no pending memory access

to ROM/Flash.

Timing Comments Assertion—The MPC8240 asserts RCS1

access cycle. Negation—Controlled by the ROMFAL and ROMNAL parameters

of the MCCR1 register.

2-22 MPC8240 Integrated Processor User’s Manual

output signal.

at the start of a ROM/Flash

Detailed Signal Descriptions

2.2.2.17 Flash Output Enable (FOE)—Output

The Flash output enable (FOE) signal is an output on the MPC8240 (and a reset conﬁguration input signal). Following are the state meaning and timing comments for the FOE

output signal.

State Meaning Asserted—Enables Flash output for the current read access.

Negated—Indicates that there is currently no read access to Flash. Note that the FOE

operation(s) to Flash.

Timing Comments Assertion—The MPC8240 asserts FOE

cycle. Negation—Controlled by the ROMFAL and ROMNAL parameters

of the MCCR1 register.

signal provides no indication of any write

at the start of the Flash read

2.2.2.18 Address Strobe (AS)—Output

The AS output signal is used as a user-deﬁned timing signal for the Port X interface. The assertion and pulse width are fully programmable with the ASFALL and ASRISE parameters in the MCCR2 register. AS

State Meaning Asserted—Programmable number of clocks (ASFALL) from the

assertion of RCS0 Negated—Programmable number of clocks (ASRISE) from the

assertion of AS.

is also a reset conﬁguration input signal.

or RCS1.

2.2.3 EPIC Control Signals

There are ﬁve EPIC interrupt control signals that have dual functions. The signals serve as ﬁve distinct incoming interrupt requests (IRQ[0:4]) when the EPIC unit is in discrete

interrupt mode (deﬁned by GCR[M] = 1 and EICR[SIE] = 0). When the EPIC unit is in the serial interrupt mode (GCR[M] = 1 and EICR[SIE] = 1) or pass-through mode (GCR[M] =

0), each signal takes on an alternate function. The protocol for the various modes of the EPIC unit are described in Chapter 11, “Embedded Programmable Interrupt Controller (EPIC) Unit.”

2.2.3.1 Discrete Interrupt 0:4 (IRQ[0:4])—Input

Following is the state meaning for the IRQ[0:4] signals (discrete interrupt mode). The polarity and sense of each of these signals is programmable. All of these inputs can be driven completely asynchronously. In pass-through mode, interrupts from external source IRQ0 are passed directly to the processor.

Chapter 2. Signal Descriptions and Clocking 2-23

Detailed Signal Descriptions

State Meaning Asserted/Negated—When the interrupt signal is asserted (according

to the programmed polarity), the priority is checked by the EPIC unit, and the interrupt is conditionally passed to the processor as described in Chapter 11, “Embedded Programmable Interrupt Controller (EPIC) Unit.”

2.2.3.2 Serial Interrupt Mode Signals

The serial interrupt mode provides for up to 16 interrupts to be serially clocked in through the S_INT signal. The relative timing for these signals is described in Section 11.6.2, “Serial Interrupt Timing Protocol.”

2.2.3.2.1 Serial Interrupt Stream (S_INT)—Input

This signal represents the incoming interrupt stream in serial interrupt mode. State Meaning Asserted/Negated—Represents the interrupts for up to 16 external

interrupt sources with individually programmable sense and polarity . These interrupts are clocked in to the MPC8240 by the S_CLK signal.

2.2.3.2.2 Serial Interrupt Clock (S_CLK)—Output

This output serves as the serial clock that the external interrupt source must use for driving the 16 interrupts onto the S_INT signal.

State Meaning Asserted/Negated—The frequency of this clock signal is

programmed in the serial interrupt conﬁguration register.

2.2.3.2.3 Serial Interrupt Reset (S_RST)—Output

Following is the state meaning of the S_RST signal. State Meaning Asserted/Negated—S_RST is asserted only once for two S_CLK

cycles when the EPIC is programmed to the serial interrupt mode.

2.2.3.2.4 Serial Interrupt Frame (S_FRAME

Following is the state meaning of the S_FRAME State Meaning Asserted/Negated—Synchronizes the serial interrupt sampling to

interrupt source 00.

)—Output

signal.

2.2.3.3 Local Interrupt (L_INT)—Output

Following is the state meaning of the L_INT signal. State Meaning Asserted/Negated—When the EPIC is programmed in pass-through

mode, this output reﬂects the raw interrupts generated by the on-chip

MU, I

C, and DMA controllers.

2-24 MPC8240 Integrated Processor User’s Manual

Detailed Signal Descriptions

2.2.4 I2C Interface Control Signals

These two signals serve as a communication interconnect with other devices. All devices connected to these two signals must have open-drain or open-collector outputs. The logic AND function is performed on both of these signals with external pull-up resistors. Refer to the MPC8240 Hardware Speciﬁcation for the electrical characteristics of these signals.

Chapter 10, “I timings of the I

2.2.4.1 Serial Data (SDA)

C Interface, ” has a complete description of the I2C protocol and the relative

C signals.

This signal is an input when the MPC8240 is in a receiving mode and an output when it is transmitting (as an I

C master or a slave).

2.2.4.1.1 Serial Data (SDA)—Output

Following is the state meaning of the SD A output signal when the MPC8240 is transmitting (as an I

C master or a slave).

State Meaning Asserted/Negated—Used to drive the data.

2.2.4.1.2 Serial Data (SDA)—Input

Following is the state meaning of the SDA input signal when the MPC8240 is receiving data.

State Meaning Asserted/Negated—Used to receive data from other devices. The b us

is assumed to be busy when SDA is detected low.

2.2.4.2 Serial Clock (SCL)

This signal is an input when the MPC8240 is programmed as an I2C slave and an output when programmed as an I

2.2.4.2.1 Serial Clock (SCL)—Output

Following is the state meaning of the SCL output signal when the MPC8240 is an I master.

State Meaning Asserted/Negated—Driven along with SDA as the clock for the data.

2.2.4.2.2 Serial Clock (SCL)—Input

C master.

Following is the state meaning of the SCL output signal when the MPC8240 is an I2C slave.

State Meaning Asserted/Negated—The I

C unit uses this signal to synchronize incoming data on SDA. The bus is assumed to be busy when this signal is detected low.

2.2.5 System Control and Power Management Signals

The following sections describe the system control and power management signals of the MPC8240.

Chapter 2. Signal Descriptions and Clocking 2-25

Detailed Signal Descriptions

2.2.5.1 Hard Reset

The two hard reset signals on the MPC8240 (HRST_CPU and HRST_CTRL) must be asserted and negated together to guarantee normal operation. Together, HRST_CPU HRST_CTRL and set all registers to their default values. Although HRST_CPU

cause the MPC8240 to abort all current internal and external transactions,

and HRST_CTRL must be asserted together, they may be asserted completely asynchronously with respect to all other signals. See Section 13.2.1, “System Reset,” for a complete description of the reset functionality.

and

2.2.5.1.1 Hard Reset (Processor) (HRST_CPU

The following describes the state meaning and timing for the HRST_CPU

)—Input

input signal.

State Meaning Asserted/Negated—See Section 2.1.2, “Output Signal States during

Reset,” and Section 2.4, “Conﬁguration Signals Sampled at Reset,” for more information on the interpretation of the other MPC8240 signals during reset.

Timing Comments Assertion/Negation—See the MPC8240Hardware Speciﬁcation for

speciﬁc timing information of these signals and the reset conﬁguration signals.

2.2.5.1.2 Hard Reset (Peripheral Logic) (HRST_CTRL

The following describes the state meaning and timing for the HRST_CTRL

)—Input

input signal.

State Meaning Asserted/Negated—See Section 2.1.2, “Output Signal States during

Reset”, and Section 2.4, “Conﬁguration Signals Sampled at Reset,” for more information on the interpretation of the other MPC8240 signals during reset.

Timing Comments Assertion/Negation—See the MPC8240 Hardware Speciﬁcation for

speciﬁc timing information of these signals and the reset conﬁguration signals.

2.2.5.2 Soft Reset (SRESET)—Input

The assertion of the soft reset input signal causes the same actions as the assertion of the internal sr attempting to reach a recoverable state, the processor does not encounter a machine check condition. A soft reset exception is third in priority, following a hard reset and machine check.

State Meaning Asserted/Negated—When SRESET

eset signal by the EPIC unit. A soft reset is recoverable, provided that in

is asserted, the processor core attempts to reach a recoverable state by allowing the ne xt instruction to either complete or cause an exception, blocking the completion of subsequent instructions, and allowing the completed store queue to drain. Unlike a hard reset, no registers or latches are initialized; however, the instruction cache is disabled (HID0[ICE] = 0].

2-26 MPC8240 Integrated Processor User’s Manual

Detailed Signal Descriptions

Timing Comments Assertion—May occur at any time, asynchronous to any clock.

Negation—Must be asserted for at least 2 sys_logic_clk cycles. After SRESET

is negated, the processor vectors to the system reset vector .

2.2.5.3 Machine Check (MCP)—Output

The MCP signal is driven by the MPC8240 when a machine check error is generated by any of the conditions described in Chapter 13, “Error Handling,” for generating the internal mcp signal. The assertion of MCP depends upon whether the error handling registers of the MPC8240 are set to report the speciﬁc error. Additionally, the programmable parameter PICR1[MCP_EN] is used to enable or disable the assertion of MCP all error conditions. MCP

is also used as a reset conﬁguration input signal.

State Meaning Asserted—Reﬂects the state of the internal mcp

a reportable error condition, as deﬁned in Chapter 13, “Error Handling, ” has occurred. The current transaction may or may not be aborted depending upon the software conﬁguration. Assertion of

mcp

causes the processor core to conditionally take a machine check exception or enter the checkstop state based on the setting of the MSR[ME] bit in the processor core.

Negated—There is no mcp

Timing Comments Assertion—mcp

so the same timing applies to MCP Negation—The MPC8240 holds mcp

may be asserted to the processor core in any cycle,

being reported to the processor core.

asserted until the processor core has taken the exception. The MPC8240 decodes a machine check acknowledge cycle by detecting processor reads from the two possible machine check exception addresses at 0x0000_0200–0x0000_0207 and 0xFFF0_0200–0xFFF0_0207 and then negates mcp

. This timing also applies to MCP.

High impedance—If the PMCR2[SHARED_MCP] bit is set, the MCP

signal is placed in high impedance when there is no error to

report.

by the MPC8240 for

signal. Indicates that

2.2.5.4 Nonmaskable Interrupt (NMI)—Input

The nonmaskable interrupt (NMI) signal is an input on the MPC8240. Following are the state meaning and timing comments for the NMI input signal. See Chapter 13, “Error Handling,” for more information.

State Meaning Asserted—Indicates that the MPC8240 should signal a machine

check interrupt (mcp Negated—No NMI reported.

Chapter 2. Signal Descriptions and Clocking 2-27

) to the processor core.

Detailed Signal Descriptions

Timing Comments Assertion—NMI may occur at any time, asynchronously.

Negation—Should not occur until after the interrupt is taken. (interrupt source assumed to be cleared by software in the interrupt handler routine).

2.2.5.5 System Management Interrupt (SMI)—Input

Following are the state meaning and timing comments for SMI. State Meaning Asserted—The SMI

input signal is level-sensitive, and causes exception processing for a system management interrupt when SMI is asserted and MSR[EE] is set.

Negated—Indicates that normal operation should proceed.

Timing Comments Assertion—May occur at any time and may be asserted

asynchronously to the input clocks. Negation—Should not occur until the interrupt is taken.

2.2.5.6 Checkstop In (CHKSTOP_IN)—Input

Following are the state meaning and timing comments for the CHKSTOP_IN signal. State Meaning Asserted—Indicates that the MPC8240 processor core must

terminate operation by internally gating off all clocks, and releasing all processor-related outputs to the high-impedance state.

Negated—Indicates that normal operation should proceed.

Timing Comments Assertion—May occur at any time and may be asserted

asynchronously to the input clocks. Negation—Must remain asserted until the system has been reset with

a hard reset.

2.2.5.7 Time Base Enable (TBEN)—Input

Following are the state meaning and timing comments for TBEN. State Meaning Asserted—Indicates that the time base and decrementer should

continue clocking. This input is essentially a count enable control for the time base counter and the decrementer.

Negated—Indicates that the time base and decrementer should stop clocking.

Timing Comments Assertion/Negation—May occur on any cycle.

2.2.5.8 Quiesce Acknowledge (QACK)—Output

The quiesce acknowledge (QACK) signal is an output on the MPC8240.It is also a reset conﬁguration input signal. See Chapter 14, “Power Management,” for more information

2-28 MPC8240 Integrated Processor User’s Manual

Detailed Signal Descriptions

about the power management signals. Following are the state meaning and timing comments for the QA

CK output signal.

State Meaning Asserted—Indicates that the processor core and peripheral logic are

in either nap or sleep mode. Negated—Indicates that the processor core and peripheral logic are

not in nap or sleep mode.

2.2.5.9 Watchpoint Trigger Signals

There is one watchpoint trigger input and one watchpoint trigger output signal that together provide a programmable output signal and control of the watchpoint facility. See Chapter 16, “Programmable I/O and Watchpoint,” for more information about the watchpoint facility.

2.2.5.9.1

The watchpoint trigger in (TRIG_IN) signal is an input on the MPC8240. Following are the state meaning and timing comments for the TRIG_IN signal. Note that TRIG_IN is an active-high (rising-edge triggered) signal.

State Meaning Asserted—May cause the MPC8240 to exit the HOLD state, or

Timing Comments Assertion/Negation—The MPC8240 interprets TRIG_IN as asserted

Watchpoint Trigger In (TRIG_IN)—Input

causes the value of the WP_R UN bit in the WP_CONTROL register to toggle (turning the watchpoint facility on or off). See Chapter 16, “Programmable I/O and Watchpoint,” for more information.

Negated—No action taken.

on detection of the rising edge of TRIG_IN. Only required to be asserted for a single clock cycle.

2.2.5.9.2 Watchpoint Trigger Out (TRIG_OUT)—Output

The watchpoint trigger out (TRIG_OUT) signal is an output on the MPC8240. Following are the state meaning and timing comments for the TRIG_OUT signal. Note that the active sense of TRIG_OUT is controlled by the setting of WP_CONTROL[WP_TRIG].

State Meaning Asserted—Indicates that a ﬁnal watchpoint match has occurred, as

deﬁned in the WP_MODE ﬁeld of the WP_CONTROL register. Negated—No ﬁnal watchpoint match condition.

Timing Comments Assertion/Negation—Asserted until TRIG_IN is asserted, unless the

WP_TRIG_HOLD parameter in the WP_CONTROL register is cleared. Then TRIG_OUT is asserted for a single clock cycle.

2.2.5.10 Debug Signals

The following sections describe the debug signals used by the MPC8240 in various debug modes. See Chapter 15, “Debug Features,” for more details and timing information on the debug signals.

Chapter 2. Signal Descriptions and Clocking 2-29

Detailed Signal Descriptions

2.2.5.10.1 Memory Address Attributes (MAA[0:2])—Output

The memory attribute signals are associated with the memory interface and provide information about the source of the memory operation being performed by the MPC8240. They are also reset conﬁguration input signals.

State Meaning Asserted/Negated—These signals are encoded to provide more

detailed information about a memory transaction. See Section 15.2.1, “Memory Address Attribute Signals (MAA[0:2]),” for a table showing these encodings.

Timing Comments Assertion/Negation—Section 15.2.2, “Memory Address Attribute

Signal Timing,” refers to timing diagrams showing the relative timing of these signals and the rest of the memory interface.

2.2.5.10.2 PCI Address Attributes (PMAA[0:2])—Output

The memory attribute signals are associated with the PCI interface and provide information about the source of the PCI operation being performed by the MPC8240. They are also reset conﬁguration input signals.

State Meaning Asserted/Negated—These signals are encoded to provide more

detailed information about a PCI transaction. See Section 15.2.3, “PCI Address Attribute Signals,” for a table showing these encodings.

Timing Comments Assertion/Negation—Section 15.2.4, “PCI Address Attribute Signal

Timing,” contains timing diagrams showing the relative timing of these signals and the rest of the PCI interface.

2.2.5.10.3 Debug Address (DA[0:15])—Output

When enabled, the debug address provides software disassemblers a simple way to reconstruct the 30-bit physical address for a memory bus transaction to DRAM and SDRAM, ROM, Flash, or PortX. Note that most of these signals are multiplex ed with other signals (that may be inputs in their alternate function).

State Meaning Asserted/Negated—Section 15.3, “Memory Debug Address,”

describes these signals in detail, and how they are mapped to different address bits, depending on the type of memory in use.

Timing Comments Assertion/Negation— For DRAM or SDRAM, these 16 debug

address signals are sampled with the column address and chip-selects. For ROM, Flash, and PortX de vices, the deb ug address pins are sampled at the same time as the ROM address and can be used to recreate the 24-bit physical address in conjunction with ROM address.

2-30 MPC8240 Integrated Processor User’s Manual

2.2.5.10.4 Memory Interface Valid (MIV)—Output

Detailed Signal Descriptions

The MIV

signal is intended to help reduce the number of bus cycles that logic analyzers must store in memory during a debug trace by signalling when address and data signals should be sampled.

State Meaning Asserted—The memory interface valid signal, MIV

, is asserted whenever FPM, EDO, SDRAM, Flash, or R OM addresses or data are present on the external memory bus.

Timing Comments Assertion/Negation—Section 15.4.1, “MIV Signal

Timing,”describes the relative timing of MIV

in detail.

2.2.6 Test and Conﬁguration Signals

The MPC8240 has several signals that are sampled during reset to determine the conﬁguration of the ROM, Flash, and dynamic memory, and the phase-locked loop clock mode.

To facilitate system testing, the MPC8240 provides a JTAG test access port (TAP) that complies with the IEEE 1149.1 boundary-scan speciﬁcation. This section also describes the JTAG test access port signals.

2.2.6.1 PLL Conﬁguration (PLL_CFG[0:4])—Input

PLL_CFG[0:4] determine the clock frequency relationships of the PCI clock, the processor core frequency, and the sys_logic_clk signal (that determines the frequency of the memory interface clock). The multiplier factor determined by these signals on reset is stored in HID1[PLLRATIO]. However, system software cannot read the PLLRATIO value and associate it with a unique PLL_CFG[0:4] value. See Section 5.3.1.2.2, “Hardware Implementation-Dependent Register 1 (HID1),” for more information on HID1.

State Meaning Asserted—See the MPC8240 Hardware Speciﬁcation for the

supported settings.

Timing Comments Assertion—These signals are sampled at the negation of

HRST_CPU signals. See Section 2.4, “Conﬁguration Signals Sampled at Reset.”

and HRST_CTRL as part of the reset conﬁguration

2.2.6.2 JTAG Test Clock (TCK)—Input

The JTAG test clock (TCK) signal is an input on the MPC8240. Following is the state meaning for the TCK input signal.

State Meaning Asserted/Negated—This input should be driven by a free-running

clock signal with a 30–70% duty cycle. Input signals to the test access port are clocked in on the rising edge of TCK. Changes to the test access port output signals occur on the falling edge of TCK. The test logic allows TCK to be stopped.

Note that this input contains an internal pull-up resistor to ensure that an unterminated input appears as a high signal level to the test logic.

Chapter 2. Signal Descriptions and Clocking 2-31

Detailed Signal Descriptions

2.2.6.3 JTAG Test Data Input (TDI)—Input

Following is the state meaning for the TDI input signal. State Meaning Asserted/Negated—The value presented on this signal on the rising

edge of TCK is clocked into the selected JTAG test instruction or data register.

Note that this input contains an internal pull-up resistor to ensure that an unterminated input appears as a high signal level to the test logic.

2.2.6.4 JTAG Test Data Output (TDO)—Output

Following is the state meaning for the TDO output signal. State Meaning Asserted/Negated—The contents of the selected internal instruction

or data register are shifted out onto this signal on the falling edge of TCK. The TDO signal remains in a high-impedance state except when scanning of data is in progress.

2.2.6.5 JTAG Test Mode Select (TMS)—Input

The test mode select (TMS) signal is an input on the MPC8240. Following is the state meaning for the TMS input signal.

State Meaning Asserted/Negated—This signal is decoded by the internal JTA G T AP

controller to distinguish the primary operation of the test support circuitry.

Note that this input contains an internal pull-up resistor to ensure that an unterminated input appears as a high signal level to the test logic.

2.2.6.6 JTAG Test Reset (TRST)—Input

The test reset (TRST) signal is an input on the MPC8240. Following is the state meaning for the TRST

input signal.

State Meaning Asserted—This input causes asynchronous initialization of the

internal JT A G test access port controller. Note that the signal must be asserted during power-up reset in order to initialize properly the JTAG test access port.

Negated—Indicates normal operation. Note that this input contains an internal pull-up resistor to ensure that

an unterminated input appears as a high signal level to the test logic.

2.2.7 Clock Signals

The MPC8240 coordinates clocking across the memory bus and the PCI bus. This section provides a brief description of the MPC8240 clock signals. See Section 2.3, “Clocking,” for more detailed information on the use of the MPC8240 clock signals.

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Motorola MPC8240 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1.1 MPC8240 Integrated Processor Overview

1.1.1 MPC8240 Integrated Processor Features

1.1.2 MPC8240 Integrated Processor Applications

1.2 Processor Core Overview

1.3 Peripheral Logic Bus

1.4 Peripheral Logic Overview

1.4.1 Peripheral Logic Features

1.4.2 Peripheral Logic Functional Units

1.4.3 Memory System Interface

1.4.4 Peripheral Component Interconnect (PCI) Interface

1.4.4.1 PCI Bus Arbitration Unit

1.4.4.2 Address Maps and Translation

1.4.4.3 Byte Ordering

1.4.4.4 PCI Agent Capability

1.4.5 DMA Controller

1.4.6 Message Unit (MU)

1.4.6.1 Doorbell Registers

1.4.6.2 Inbound and Outbound Message Registers

1.4.6.3 Intelligent Input/Output Controller (I2O)

1.4.7 Inter-Integrated Circuit (I2C) Controller

1.4.8 Embedded Programmable Interrupt Controller (EPIC)

1.4.9 Integrated PCI Bus and SDRAM Clock Generation

1.5 Power Management

1.5.1 Programmable Processor Power Management Modes

1.5.2 Programmable Peripheral Logic Power Management Modes

1.6 Programmable I/O Signals with Watchpoint

1.7 Debug Features

1.7.1 Memory Attribute and PCI Attribute Signals

1.7.2 Memory Debug Address

1.7.3 Memory Interface Valid (MIV)

1.7.4 Error Injection/Capture on Data Path

1.7.5 IEEE 1149.1 (JTAG)/Test Interface

2.1 Signal Overview

2.1.1 Signal Cross Reference

2.1.2 Output Signal States during Reset

2.2 Detailed Signal Descriptions

2.2.1 PCI Interface Signals

2.2.1.1 PCI Bus Request (REQ[4:0])—Input

2.2.1.2 PCI Bus Grant (GNT[4:0])—Output

2.2.1.3 PCI Address/Data Bus (AD[31:0])

2.2.1.3.1 Address/Data (AD[31:0])—Output

2.2.1.3.2 Address/Data (AD[31:0])—Input

2.2.1.4 Parity (PAR)

2.2.1.4.1 Parity (PAR)—Output

2.2.1.4.2 Parity (PAR)—Input

2.2.1.5 Command/Byte Enable (C/BE[3:0])

2.2.1.5.2 Command/Byte Enable (C/BE[3:0])—Input

2.2.1.6 Device Select (DEVSEL)

2.2.1.6.2 Device Select (DEVSEL)—Input

2.2.1.7 Frame (FRAME)

2.2.1.8 Initiator Ready (IRDY)

2.2.1.9 Lock (LOCK)—Input

2.2.1.10 Target Ready (TRDY)

2.2.1.10.2 Targ et Ready (TRDY)—Input

2.2.1.11 Parity Error (PERR)

2.2.1.12 System Error (SERR)

2.2.1.12.1 System Error (SERR)—Output

2.2.1.13 Stop (STOP)

2.2.1.14 Interrupt Request (INTA)—Output

2.2.1.15 ID Select (IDSEL)—Input

2.2.2 Memory Interface Signals

2.2.2.1 Row Address Strobe (RAS[0:7])—Output

2.2.2.2 Column Address Strobe (CAS[0:7])—Output

2.2.2.3 SDRAM Command Select (CS[0:7])—Output

2.2.2.4 SDRAM Data Input/Output Mask (DQM[0:7])—Output

2.2.2.5 Write Enable (WE)—Output

2.2.2.6 SDRAM Address (SDMA[11:0])—Output

2.2.2.7 SDRAM Address 12 (SDMA12)—Output

2.2.2.8 SDRAM Internal Bank Select 0–1 (SDBA0, SDBA1)—Output

2.2.2.9 Memory Data Bus (MDH[0:31], MDL[0:31])

2.2.2.9.1 Memory Data Bus (MDH[0:31], MDL[0:31])—Output

2.2.2.9.2 Memory Data Bus (MDH[0:31], MDL[0:31])—Input

2.2.2.10 Data Parity/ECC (PAR[0:7])

2.2.2.10.1 Data Parity (PAR[0:7])—Output

2.2.2.10.2 Data Parity (PAR[0:7])—Input

2.2.2.11 ROM Address 19:12 (AR[19:12])—Output