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MPC821FADS
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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different
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such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manuf acture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employ er.
©
1998 Motorola, Inc. All Rights Reserved.
For More Information On This Product,
Go to: www.freescale.com
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PowerPC
™
is a registered trademark of IBM Corporation and is used by Motorola under license from IBM.
All other trademarks are the property of their respective owners.
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®
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is a registered tradmeark of Philips Corporation.
For More Information On This Product,
Go to: www.freescale.com
SECTION 1
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INTRODUCTION
,
This document is the MPC821FADS daughterboard operation guide. The daughterboard
encompasses the MPC821 device along with some necessary logic that must be in close
proximity to the MPC821 and peripherals. These peripherals are dedicated to the MPC821,
but are not necessarily required for any other member of the MPC8xx Family. The
daughterboard has two sets of matching connectors—one set on the print side (on the
bottom of the board) and one on the component side (on the top of the board). Those on the
print side connect to a matching set found on the MPC8xxFADS, while those on the
component side are to serve hardware expansion via a dedicated adaptor. Also a set of logic
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analyzer connectors is featured matching the new high-density HP16500 logic analyzer
adaptors to provide fast connection to a logic analyzer while saving board space and
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reducing EMI.
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1.1 TERMINOLOGY
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• ADI—Application Development Interface
• ADS—Application Development System
• BCSR—Board Control and Status Register
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• BGA—Ball Grid Array
• DB—Daughterboard
• GPCM—General-Purpose Chip-Select Machine
• GPL—General-Purpose Line (associated with the UPM)
• I/R—Infra-Red
• UPM—User-Programmable Machine
• ZIF—Zero Input Force
1.2 RELATED DOCUMENTATION
• MPC821 User’s Manual
• SDS Monitor User’s Manual
• MPC8bug User’s Manual
• ADI Board Specification
• MPC8xxFADS User’s Manual
MOTOROLA
MPC821FADS-DB USER’S MANUAL
1-1
Introduction
1.3 SPECIFICATIONS
The MPC821FADS daughterboard specifications are shown in Table 1-1.
Table 1-1. MPC821FADS Daughterboard Specifications
CHARACTERISTICS SPECIFICATIONS
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Microprocessor MPC821 @ 50MHz
Operating temperature
Storage temperature
Relative humidity 5% to 90% (noncondensing)
Dimensions:
Length
Width
Thickness
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1.4 FEATURES
• MPC821 Operation at a Maximum 50MHz
• Selectable KAPWR Source—3.3V or Externally Supplied
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• Selectable VDDL Source—3.3V or 2V
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• Selectable Clock Source—32768Hz Crystal Resonator or 4MHz Clock Generator That
Can be Easily Changed to Any 3.3V-Powered Oscillator with a 3–5MHz Frequency
Range
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0OC – 30OC
-25
5.87" (145mm)
4.37" (125mm)
0.063" (1.6mm)
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• On-Board Expansion Connectors, Including All MPC821 Pins and MPC8xxFADS
Control and Status Signals.
• Onboard High-Density Logic Analyzer Connectors That Support Fast Connection to
HP16500 Logic Analyzer
• MPC821 Modem Tool Support
1-2
MPC821FADS-DB USER’S MANUAL
MOTOROLA
EXPANSION
CONNECTORS
EXPANSION
CONNECTORS
MPC821
DAUGHTER
BOARD
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Figure 1-1. MPC821FADS Daughterboard Block Diagram
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CLOCKS
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EXPANSION
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CONNECTORS
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Introduction
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MOTOROLA
MPC821FADS-DB USER’S MANUAL
1-3
SECTION 2
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INSTALLATION
,
This section contains information about preparing, configuring, and installing the
MPC821FADS daughterboard. When you receive your daughterboard it should already be
connected to the MPC8xxFADS motherboard. You should unpack the shipping carton and
verify the contents against the packing list. If the contents were damaged during shipping,
call your local Motorola sales office, explain the problem, and you should receive another
package. If the contents are undamaged, save the packing slip and start configuring the
board for your design.
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Caution:
2.1 CONFIGURING THE BOARD
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Before you configure the MPC821FADS daughterboard, you may have to change the
jumpers settings before you can install the board into your system. Since they are factory
set and tested, they may not be set correctly for your particular configuration. Figure 2-1
illustrates the location of these jumpers, LEDs, and connectors on the board. The
MPC821FADS daughterboard settings contain the following parameters that you can
change for your specific configuration:
A
Avoid touching the integrated circuitry of the board with your hands since static
discharge can damage circuits.
B
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• Clock generator
• Power-on reset source
• MPC821 keep-alive power source
• MPC821 internal logic supply source
MOTOROLA
MPC821FADS-DB USER’S MANUAL
2-1
Installation
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Figure 2-1. MPC821FADS Daughterboard Parts Locator (Top Side)
2-2
MPC821FADS-DB USER’S MANUAL
MOTOROLA
Installation
2.1.1 Replacing the Clock Generator
When replacing the clock generator (U1), all you need to know is that there are two supply
levels. A 5V supply is available at Pin 14 and a 3.3V supply is available at Pin 11. To replace
it, just pop it out of the socket. Figure 2-2 illustrates that a 5V oscillator (with 3.3V output
only) can be used with a 14-pin form-factor, while 3.3V oscillators can be used with an 8-pin
form-factor.
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14
5V1
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Inserting a 14-pin form-factor 3.3V clock generator into U1 could cause permanent damage
to your device. Since the MPC821 clock input is not 5V-tolerant, any clock generator
inserted into U1 must have a 3.3V-compatible output. If you insert a 5V output clock
generator into U1, you could cause permanent damage to the MPC821 microprocessor.
Figure 2-2. U1 Power Sources
GND
7
U1
8
3.3V
MOTOROLA
MPC821FADS-DB USER’S MANUAL
2-3
Installation
2.1.2 Selecting the Power-On Reset Source
The functionality of the power-on reset logic changes with each revision of the MPC821. For
your purposes, this means that you may need to select a different source to generate a
power-on reset. To select your power-on reset source, you need to set J1 on the
MPC821FADS daughterboard. When the J1 jumper is between positions 1 and 2, a
power-on reset is generated by the keep-alive power rail (KAPWR). For example, when
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KAPWR goes below 2.005V, a power-on reset is generated. When the J1 jumper is between
positions 2 and 3, a power-on reset is generated from the main 3.3V power rail. In other
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words, when the 3.3V power rail gets below 2.805V, a power-on reset is generated.
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MAIN POWER RAIL
KEEP-ALIVE POWER RAIL
Figure 2-3. Power-On Reset Source
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2.1.3 Selecting the Keep-Alive Power Source
The J2 jumper is used to select the keep-alive power source. When the J2 jumper is
between positions 1 and 2, the keep-alive power is fed from the main 3.3V bus. When you
need to connect an external power source (such as a battery) to the keep-alive power rail,
it should be connected between positions 2 (the positive pole) and 3 (GND).
A
2-4
J2
3.3V
KAPWR
GND
1
KAPWR FROM 3.3V KAPWR FROM EXTERNAL
Figure 2-4. Keep-Alive Power Source
MPC821FADS-DB USER’S MANUAL
3.3V
KAPWR
GND
J2
1
POWER SUPPLY
+
–
EXTERNAL
POWER SUPPLY
MOTOROLA
Installation
2.1.4 Selecting the VDDL Source
The J3 jumper is used to select the VDDL, which supplies the MPC821’s internal logic.
When the J3 jumper is between positions 1 and 2, VDDL is supplied with 3.3V of power.
When the J3 jumper is between positions 2 and 3, VDDL is supplied with 2.2V of power. The
J3 jumper is factory set between positions 1 and 2.
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3.3V VDDL 2V VDDL
Figure 2-5. VDDL Source
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MOTOROLA
MPC821FADS-DB USER’S MANUAL
2-5
SECTION 3
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OPERATION
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This section contains the necessary information you need to operate the MPC821FADS
daughterboard.
3.1 INDICATORS
The MPC821FADS daughterboard does not have any switches, but it has five indicators.
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3.1.1 Ground Bridges
There are four ground (GND) bridges on the MPC821FADS daughterboard. They can be
used to assist you with easy ground access points for general measurements and a logic
analyzer connection.
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Warning:
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3.1.2 3.3V Indicator
The yellow 3.3V light (LD1) indicates that the 3.3V power bus is receiving power from the
MPC8xxFADS motherboard.
3.1.3 Memory Map
The memory map is the same on all daughterboards. See
MPC8xxFADS User’s Manual
D
The onboard GND bridges physically resemble the J4 jumper and you should
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take care not to mistake it for a GND jumper. Doing so could cause permanent
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damage to your MPC821FADS daughterboard or MPC8xxFADS
motherboard. When you are connecting to a GND bridge, use only insulated
GND clips to keep from damaging the board.
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Section 3.3 Memory Map
of the
3.1.4 Programming the MPC821 Registers
To program the MPC821 registers, see
Registers
MOTOROLA
of the
MPC8xxFADS User’s Manual.
Section 3.1.7 Programming the MPC821
MPC821FADS-DB USER’S MANUAL
3-1
SECTION 4
FUNCTIONALITY
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This section describes the main functions of the MPC821FADS daughterboard.
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• Reset
• Interrupts
• Clock generator
• LCD panel support
• Board control and status registers
4.1 RESET
There are three sources of reset for the MPC821 microprocessor:
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• Power-on reset
• Hard reset
• Soft reset
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4.1.1 Power-On Reset
On the MPC821FADS daughterboard, a power-on reset can be generated from a keep-alive
power bus or a main power bus. The J1 jumper is used to select one of these sources. When
you select the keep-alive power source, a dedicated voltage detector made by Seiko
(S-8051HN-CD-X), which has a detection voltage range of 1.795–2.005V, generates the
power-on reset. During a keep-alive power-on, or when there is a voltage drop of that input
into the above range, a power-on reset is generated (the PORESET
asserted for approximately 4 seconds).
When you select the main power source, a dedicated voltage detector made by Seiko
(S-8052ANY-NH-X), with a detection voltage range of 2.595–2.805V, generates the
power-on reset. During a main 3.3V bus power-on, or when there is a voltage drop of that
input into the above range, a power-on reset is generated (the PORESET
MPC821 is asserted for approximately 4 seconds). The main power-on reset also generates
a power-on reset to all logic on the motherboard.
The power-on reset configuration is read by the MPC821 when PORESET
MPC821. See
User’s Manual
Section 4.1.6.1 Power-On Reset Configuration
for more information.
input of the MPC821 is
input of the
is asserted to the
of the
MPC8xxFADS
MOTOROLA
MPC821FADS-DB USER’S MANUAL
4-1
Functionality
4.1.2 Hard Reset
A hard reset is generated from four possible sources:
• A main power-on reset
• A manual hard reset generated on the motherboard
• A debug port hard reset
• An internal source of the MPC821
When the open-drain HRESET
the data bus by the motherboard logic. See
MPC8xxFADS User’s Manual
the
signal is asserted, hard reset configuration data is driven on
for details.
4.1.3 Soft Reset
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A soft reset is generated from three possible sources:
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Section 4.1.6.2 Soft Reset Configuration
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• The debug port controller on the motherboard
• A manual soft reset generated on the motherboard
• An internal source of the MPC821
The motherboard logic makes a soft reset configuration available to the MPC821 when a
soft reset is generated to the MPC821. See
MPC8xxFADS User’s Manual
the
4.2 INTERRUPTS
The only external interrupt that is applied to the MPC821 via its interrupt controller is the
abort (NMI) interrupt, which is generated by a push-button and logic that resides on the
motherboard.
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4.3 CLOCK GENERATOR
Although most of the clock generator logic is found on the daughterboard, it is explained in
detail in the motherboard manual since it is common to all daughterboards. See
Clock Generator
of the
MPC8xxFADS User’s Manual
for more information.
Section 4.3
4.4 LCD PANEL SUPPORT
A dedicated LCD connector is provided with your board to allow connection to an LCD panel.
This connector contains the MPC821 Port D pins. The LCD connector is a superset of the
LCD connector on the MPC821FADS board, which makes it easy to move tools between
the two boards and to connect the additional color bits.
To make connecting even easier, there are 5V supply pins available on the LCD connector.
For a description of these signals, refer to Table 5-8 in
4-2
MPC821FADS-DB USER’S MANUAL
Section 5 Signal Descriptions
MOTOROLA
.
Functionality
4.5 BOARD CONTROL AND STATUS REGISTERS
Most board control and status register (BCSR) control signals and some of the status signals
are available on the motherboard connectors and on the expansion connectors. The BCSRs
control most of the functions available on the MPC821FADS daughterboard and the
MPC8xxFADS motherboard.
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MPC821FADS-DB USER’S MANUAL
4-3
SECTION 5
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SIGNAL DESCRIPTIONS
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This section contains signal information for supporting, maintaining, as well as connecting
to, the MPC821FADS daughterboard.
5.1 INTERCONNECT SIGNALS
The MPC821FADS daughterboard uses the following connectors to interconnect with
external devices.
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• P1, P2, P3, P4, P5, P6, and P8—Logic analyzer connectors
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• PM1, PM2, PM3, and PM4—Motherboard connectors
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• PX1, PX2, PX3, and PX4—Expansion connectors
• P7—LCD panel connector
• MPC8xxFADS’s P8—Serial port expansion connector
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This connector is located on the motherboard. It is documented here since its contents depends on the
daughterboard.
MOTOROLA
MPC821FADS-DB USER’S MANUAL
5-1
Signal Descriptions
5.1.1 P1, P2, P3, P4, P5, P6, and P8—Logic Analyzer Connectors
The logic analyzer connectors are 38-pin, receptacle MICTOR connectors manufactured by
AMP. Each connector connects to a dedicated adaptor for the HP16500 Series logic
analyzers, which interconnect to two 16-bit pods. Since all the signals on these connectors
are also on the motherboard connectors and expansion connectors, they are also described
in the
MPC8xxFADS User’s Manual
Table 5-1. P1 Interconnect Signals
PIN MOTHER
BOARD
SIGNAL
1—— 2——
3 GND GND 4 — —
5TS
7TSTS 8TATA
9 F_CS F_CS 10 VFLS0 VFLS0
11 BCSRCS BCSRCS 12 VFLS1 VFLS1
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13 DRMCS1
15 DRMCS2 DRMCS2 16 AT1 AT1
17 SDRMCS
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DRMCS1 14 AT0 AT0
SDRMCS 18 AT2 AT2
CS6 22 VF0 VF0
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23 CS7 CS7 24 VF1 VF1
25 — — 26 VF2 VF2
27 R_W
29 REG_A REG_A 30 RESETA RESETA
31 TSIZE1 TSIZE1 32 POE_A
33 BURST BURST 34 MODCK1 MODCK1
35 TEA TEA 36 MODCK2 MODCK2
37 SPKROUT SPKROUT
NOTE: — = Not Connected.
R_W 28 WAIT_B WAIT_B
(KR/IRQ4
)
38 EXTCLK EXTCLK
POE_A
5-2
MPC821FADS-DB USER’S MANUAL
MOTOROLA
Table 5-2. P2 Interconnect Signals
Signal Descriptions
PIN MOTHER
BOARD
SIGNAL
1—— 2——
3 GND GND 4 — —
5 — — 6 BS0A
7 ALE_A ALE_A 8 BS0A BS0A
9 CE1A CE1A 10 BS1A BS1A
11 CE2A CE2A 12 BS2A BS2A
DAUGHTER
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SIGNAL
PIN MOTHER
BOARD
SIGNAL
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13 BWAITA BWAITA 14 BS3A BS3A
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15 BB BB 16 WE0 WE0
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17 BR BR 18 WE1 WE1
19 BWP BWP 20 WE2 WE2
21 BCD2 BCD2 22 WE3 WE3
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23 BCD1 BCD1 24 DRM_W DRM_W
25 BG BG 26 EDOOE EDOOE
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27 BI BI 28 GPL2 GPL2
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31 BADDR28 BADDR28 32 GPL4A GPL4A
33 BADDR29 BADDR29 34 GPL4B GPL4B
35 BADDR30 BADDR30 36 GPL5A GPL5A
37 AS AS 38 GPL5B GPL5B
NOTE: — = Not Connected.
MOTOROLA
MPC821FADS-DB USER’S MANUAL
5-3
Signal Descriptions
Table 5-3. P3 Interconnect Signals
PIN MOTHER
BOARD
SIGNAL
1—— 2——
3 GND GND 4 — —
5 TEA
7 A0 A0 8 A16 A16
9 A1 A1 10 A17 A17
11 A2 A2 12 A18 A18
DAUGHTER
BOARD
SIGNAL
TEA 6——
PIN MOTHER
BOARD
SIGNAL
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13 A3 A3 14 A19 A19
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15 A4 A4 16 A20 A20
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17 A5 A5 18 A21 A21
19 A6 A6 20 A22 A22
21 A7 A7 22 A23 A23
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23 A8 A8 24 A24 A24
25 A9 A9 26 A25 A25
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27 A10 A10 28 A26 A26
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31 A12 A12 32 A28 A28
33 A13 A13 34 A29 A29
35 A14 A14 36 A30 A30
37 A15 A15 38 A31 A31
NOTE: — = Not Connected.
5-4
MPC821FADS-DB USER’S MANUAL
MOTOROLA
Table 5-4. P4 Interconnect Signals
Signal Descriptions
PIN MOTHER
BOARD
SIGNAL
1—— 2——
3 GND GND 4 — —
5 — — 6 LD1 PD8
7 PA0 PA0 8 LD8 PD15
9 PA1 PA1 10 LD7 PD14
11 PA2 PA2 12 LD6 PD13
DAUGHTER
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SIGNAL
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SIGNAL
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13 PA3 PA3 14 LD5 PD12
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15 PA4 PA4 16 LD4 PD11
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17 PA5 PA5 18 LD3 PD10
19 PA6 PA6 20 LD2 PD9
21 PA7 PA7 22 LD1 PD8
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23 PA8 PA8 24 LD0 PD7
25 PA9 PA9 26 LOE PD6
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.
31 IRDTXD IRDTXD 32 SHIFT_C PD3
33 IRDRXD IRDRXD 34 SPARE1 SPARE1
35 ETHTX ETHTX 36 SPARE2 SPARE2
37 ETHRXS ETHRXS 38 SPARE3 SPARE3
NOTE: — = Not Connected.
MOTOROLA
MPC821FADS-DB USER’S MANUAL
5-5
Signal Descriptions
Table 5-5. P5 Interconnect Signals
PIN MOTHER
BOARD
SIGNAL
1—— 2——
3 GND GND 4 — —
5 IRQ7
7 UUFEN UUFEN 8 DSDI DSDI
9 USBVCC0 — 10 DSCK DSCK
11 VDOEXTCK — 12 DSDO DSDO
DAUGHTER
BOARD
SIGNAL
IRQ7 6——
PIN MOTHER
BOARD
SIGNAL
U
D
N
O
C
I
DAUGHTER
BOARD
SIGNAL
R
O
T
C
,
M
13 USBSPD — 14 TMS TMS
A
E SE
L
15 VDORST
17 BVS1 BVS1 18 NMI NMI
19 BVS2 BVS2 20 IRQ1 IRQ1
B
Y
F
21 BBVD1 BBVD1 22 IRQ2 IRQ2
23 BBVD2 BBVD2 24 IRQ3 IRQ3
25 RSTCNF RSTCNF 26 FRZ FRZ
V
I
H
27 TEXP TEXP 28 BINPAK BINPAK
C
R
29 HRESET HRESET 30 DP0 DP0
A
E
D
— 16 TRST TRST
C
S
E
E
R
I
N
C
.
31 SRESET SRESET 32 DP1 DP1
33 PORST
35 R_PORI R_PORI 36 DP3 DP3
37 IRQ7
NOTE: — = Not Connected.
PORST 34 DP2 DP2
IRQ7 38 — V3.3
5-6
MPC821FADS-DB USER’S MANUAL
MOTOROLA
Table 5-6. P6 Interconnect Signals
Signal Descriptions
PIN MOTHER
BOARD
SIGNAL
1—— 2——
3 GND GND 4 — —
5 — — 6 SYSCLK SYSCLK
7 PB14 PB14 8 SYSCLK SYSCLK
9 PB15 PB15 10 PB30 PB30
11 PB16 PB16 12 PB31 PB31
DAUGHTER
BOARD
SIGNAL
PIN MOTHER
BOARD
SIGNAL
U
D
N
O
C
I
DAUGHTER
BOARD
SIGNAL
,
R
O
T
C
M
13 PB17 PB17 14 PC4 PC4
A
E SE
L
15 PB18 PB18 16 PC5 PC5
17 E_TENA E_TENA 18 PC6 PC6
19 RSRXD2 RSRXD2 20 PC7 PC7
21 RSTXD2 RSTXD2 22 PC8 PC8
E
D
B
23 RSDTR2
25 RSDTR1
V
I
H
27 RSRXD1 RSRXD1 28 E_CLSN E_CLSN
C
R
29 RSTXD1 RSTXD1 30 PC12 PC12
A
Y
R
F
C
S
E
E
RSDTR2 24 PC9 PC9
RSDTR1 26 E_RENA E_RENA
I
N
C
.
31 PB26 PB26 32 PC13. PC13.
33 PB27 PB27 34 PC14 PC14
35 PB28 PB28 36 SPARE4 SPARE4
37 PB29 PB29 38 — —
NOTE: — = Not Connected.
MOTOROLA
MPC821FADS-DB USER’S MANUAL
5-7
Signal Descriptions
Table 5-7. P8 Interconnect Signals
PIN MOTHER
BOARD
SIGNAL
1—— 2——
3 GND GND 4 — —
5—— 6——
7 D0 D0 8 D16 D16
9 D1 D1 10 D17 D17
11 D2 D2 12 D18 D18
DAUGHTER
BOARD
SIGNAL
PIN MOTHER
BOARD
SIGNAL
U
D
N
O
C
I
DAUGHTER
BOARD
SIGNAL
R
O
T
C
,
M
13 D3 D3 14 D19 D19
A
E SE
L
15 D4 D4 16 D20 D20
E
E
S
C
17 D5 D5 18 D21 D21
19 D6 D6 20 D22 D22
21 D7 D7 22 D23 D23
E
D
B
23 D8 D8 24 D24 D24
25 D9 D9 26 D25 D25
V
I
H
27 D10 D10 28 D26 D26
C
R
29 D11 D11 30 D27 D27
A
Y
R
F
I
N
C
.
31 D12 D12 32 D28 D28
33 D13 D13 34 D29 D29
35 D14 D14 36 D30 D30
37 D15 D15 38 D31 D31
NOTE: — = Not Connected.
5-8
MPC821FADS-DB USER’S MANUAL
MOTOROLA
Signal Descriptions
5.1.2 P7—LCD Panel Connector
The LCD panel connector is a 40-pin (2x20) header connector that is compatible with the
LCD panel connector on the MPC821ADS board. To allow MPC821 users to migrate
conveniently, the signals are assigned so that panels connected to the MPC821ADS board
can be connected directly.
I
N
C
.
Table 5-8. P7 Interconnect Signals
O
R
,
PIN SIGNAL INPUT/OUTPUT DESCRIPTION
U
C
T
1 SHIFT_C I/O LCD Shift Clock
2
E
E
S
—
C
I
M
panels LCD_AC
E SE
L
A
C
mark.
3
4
5 LOE I/O LCD Output Enable for TFT displays or passive
6 GND —
7 HSYNC I/O Horizontal Sync signal. Displays line beginning mark.
8 GND —
9 VSYNC I/O Vertical Sync signal. Displays new frame beginning
10
11
12
13 LD0 I/O LCD Data line 0
A
R
C
GND
Y
B
D
E
V
I
H
GND —
R
F
N
O
signal.
D
14 GND —
15 LD1 I/O LCD Data line 1
16 GND —
17 LD2 I/O LCD Data line 2
18 GND —
19 LD3 I/O LCD Data line 3
20 GND —
21 LD4 I/O LCD Data line 4
22 GND —
23 LD5 I/O LCD Data line 5
24 GND —
25 LD6 I/O LCD Data line 6
26 GND —
27 LD7 I/O LCD Data line 7
28 GND —
MOTOROLA
MPC821FADS-DB USER’S MANUAL
5-9
Signal Descriptions
Table 5-8. P7 Interconnect Signals (Continued)
PIN SIGNAL INPUT/OUTPUT DESCRIPTION
29 LD8 I/O LCD Data line 8
30 GND —
31
32
33
34
35 — I/O
36 VCC O 5V supply
37 — I/O
38 VCC O 5V supply
39 — I/O
40 VCC O 5V supply
NOTE: I = Input and O = Output.
V
I
H
C
R
A
— — Pin is cut to allow 30-pin connector insertion.
O
T
C
U
D
N
O
C
I
R
,
I
N
M
E SE
L
A
C
S
E
E
R
F
Y
B
D
E
C
.
5-10
MPC821FADS-DB USER’S MANUAL
MOTOROLA
Signal Descriptions
5.1.3 PM1 to PM4—Motherboard Connectors
These connectors, which connect to their mates on the motherboard, are 140-pin
interboard, male connectors manufactured by Molex. These connectors are arranged in a
square shape so that there is a short route to the PCB. As shown in Figure 5-1, the
connectors are set asymmetrically to prevent incorrect daughterboard insertion.
.
C
N
PM1
1
U
O
N
D
1
C
I
C
1
T
O
I
,
R
13.68mm
M
PM2 PM3
Y
B
D
E
V
I
H
C
R
A
Figure 5-1. Motherboard Connectors Mechanical Assembly (Top Side)
17.49mm
1
46.3mm
C
S
E
E
R
F
PM4
93.98mm
A
E SE
L
71.12mm
11.14mm
30.19mm
MOTOROLA
MPC821FADS-DB USER’S MANUAL
5-11
Signal Descriptions
Table 5-9. PM1 Interconnect Signals
PIN MOTHERBOARD
SIGNAL
1BB
2 VCC VCC —
3 DRM_W
4 VCC VCC — 5V Bus
5 TEA
6 VCC VCC —
7BR
8 VCC VCC —
9 BURST
10 VCC VCC —
11 GPL4A
12 VCC VCC —
13 TA
A
R
C
H
E
V
I
DAUGHTERBOARD
SIGNAL
DRM_W I,L DRAM Write signal. GPL0 line used as R/W
BURST I/O, L Burst signal. Pulled up, but otherwise unused
R
F
Y
B
D
GPL4A X,L General-Purpose Line 4 of UPMA. Not used on
INPUT/
OUTPUT
BB I/O, L Bus Busy signal. Pulled up on this board.
signal for the DRAM SIMM or as A10 line for
the SDRAM.
TEA I/O, L, OD Transfer Error Acknowledge signal. Pulled up,
but not driven on the board.
C
I
M
BR I/O,L Bus Request signal. Pulled up on this board,
C
S
E
E
TA I/O, L Transfer Acknowledge signal. Indicates the
A
E SE
L
but otherwise unused.
on this board.
this board.
end of a bus cycle,. Used with MPC8xxFADS
logic.
O
N
DESCRIPTION
C
U
D
T
O
R
,
I
N
C
.
14 VCC VCC —
15 TS
16 VCC VCC —
17 GPL5B
18 VCC VCC —
19 BG
20 VCC VCC —
21 GPL4B
22 VCC VCC —
23 R_W
24 VCC VCC —
TS I/O, L Transfer Start signal. Pulled up, but otherwise
GPL5B O, L General-Purpose Line 5 of UPMB. Not used on
BG I/O, L Bus Grant signal. Pulled up, but otherwise
GPL4B O, L General-Purpose Line 4 of UPMB. Not used on
R_W I/O, L Read/Write signal. Pulled up on this board and
unused on this board.
this board.
unused on this board.
this board.
used by MPC8xxFADS logic.
5-12
MPC821FADS-DB USER’S MANUAL
MOTOROLA
Table 5-9. PM1 Interconnect Signals (Continued)
Signal Descriptions
PIN MOTHERBOARD
SIGNAL
25 BCSRCS
26 VCC VCC O 5V Bus
27 GPL5A
28 VCC VCC O 5V Bus
29 BI
30 — — — Not Connected. Reserved.
31 CS7
32 GND GND — MPC8xxFADS ground plane.
33 CS5
34 GND GND —
35 CE1A
E
V
C
H
I
36 GND GND —
37 F_CS
A
R
DAUGHTERBOARD
SIGNAL
BCSRCS I/O, L Board Control and Status Register Chip-Select
GPL5A X,L General-Purpose Line 5 of UPMA. Not used on
R
F
Y
CE1A I, L Card Enable 1 signal for PCMCIA Slot A.
F_CS I/O, L Flash Chip-Select signal. CS0 on the MPC821.
D
B
INPUT/
OUTPUT
signal. CS1
chip-select for the BCSRs. Pulled up. When the
BCSR is removed from the local map, this
signal can be used off-board via the
daughterboard’s expansion connectors.
this board.
BI I/O,L Burst Inhibit signal. Pulled up, but otherwise
N
O
unused on this board.
C
I
DESCRIPTION
on the MPC821. Used as the
R
O
T
C
U
D
M
CS7 — Chip-Select Line 7. Unused on this board.
C
S
CS5 — Chip-Select line 5. Unused on this board.
E
E
A
E SE
L
Enables the even address bytes. Used by the
on-board PCMCIA port.
Used as chip-select for the Flash SIMM. Pulled
up. When the flash is disabled via the BCSR,
this signal can be used off-board via the
daughterboard’s expansion connectors.
,
I
N
C
.
38 GND GND —
39 CS6
40 GND GND —
41 CE2A
42 GND GND —
43 DRMCS2
44 GND GND —
45 DRMCS1
46 GND GND —
CS6 — Chip-Select line 6. Unused on this board.
CE2A I, L Card Enable 2 signal for PCMCIA Slot A.
DRMCS2 I/O, L DRAM Chip-Select 2 signal. CS3 on the
DRMCS1 I/O, L DRAM Chip-Select 1 signal. CS2 on the
Enables the odd address bytes. Used by onboard PCMCIA port.
MPC821. Used as chip-select line for the
second bank of the DRAM SIMM. Pulled up.
When the DRAM is disabled via the BCSR or
when a single-bank DRAM SIMM is being
used, this signal can be used off-board via the
daughterboard’s expansion connectors.
MPC821. Used as chip-select line for the first
bank of the DRAM SIMM. Pulled up. When the
DRAM is disabled via the BCSR, this signal
can be used off-board via the daughterboard’s
expansion connectors.
MOTOROLA
MPC821FADS-DB USER’S MANUAL
5-13
Signal Descriptions
Table 5-9. PM1 Interconnect Signals (Continued)
PIN MOTHERBOARD
SIGNAL
47 SDRMCS
48 GND GND —
49 GPL3
50 GND GND —
51 GPL2
52 GND GND —
53 WE3
54 GND GND —
55 WE2
56 GND GND —
57 WE1
C
R
A
58 GND GND —
H
E
V
I
DAUGHTERBOARD
SIGNAL
SDRMCS I/O, L SDRAM Chip-Select signal. CS4 on the
GPL3 I/O, L General-Purpose line 3 for UPMA or UPMB.
GPL2 I, L General-Purpose Line 2 for UPMA or UPMB.
R
F
Y
B
D
INPUT/
OUTPUT
WE3 I, L GPCM Write Enable 3 or PCMCIA WE signal.
E SE
L
A
C
S
E
E
WE2 I, L GPCM Write Enable 2 or PCMCIA OE signal.
WE1 I, L GPCM Write Enable 1 or PCMCIA I/O Write
DESCRIPTION
MPC821. Used as chip-select for the
synchronous DRAM. Pulled up. When the
SDRAM is disabled via the BCSR, this signal
can be used off-board via the daughterboard.
,
T
O
R
Used as WR
Used with the SDRAM as a CAS
O
C
I
signal for the SDRAM.
C
U
D
N
I
N
.
C
signal.
M
Selects the LSB within a word for the Flash
SIMM or qualifies writes for a PC card.
Selects the offset two bytes within a word for
the flash SIMM or open data buffers for read
from PC card.
signal. Used to qualify write cycles to the flash
memory and as I/O write for the PCMCIA
channel.
59 BS2A
60 GND GND —
61 WE0
62 GND GND —
63 SPARE1 SPARE1 I,O, L Spare line 1. Pulled up, but otherwise unused
64 GND GND —
65 EDOOE
66 GND GND —
67 BS0A
68 GND GND —
BS2A I, L Byte Select 2 signal for UPMA. Selects offset
WE0 I, L GPCM Write Enable 0 or PCMCIA I/O Read
EDOOE I,L EDO Output Enable signal. It is the
BS0A I, L Byte Select 0 signal from UPMA. Selects offset
two bytes within a word. Used for DRAM
access.
signal. Used to qualify write cycles to the flash
memory and as I/O reads from the PC card.
on this board.
general-purpose line 1 for UPMA and UPMB.
Used for output enable with EDO DRAM
SIMMs that have this input (most of them do
not). Used also as RAS
zero bytes within a word. Used as one of the
lines for DRAM access.
CAS
signal for the SDRAM.
5-14
MPC821FADS-DB USER’S MANUAL
MOTOROLA
Table 5-9. PM1 Interconnect Signals (Continued)
Signal Descriptions
PIN MOTHERBOARD
SIGNAL
69 BS3A
70 GND GND —
71 A31 A31 I, TS Address line 31
72 GND GND —
73 BS1A
74 GND GND —
75 TSIZ1 TSIZ1 X, TS Transfer Size 1 signal. Used in conjunction with
76 GND GND —
77 REG_A
78 GND GND —
79 A30 A30 I, TS Address line 30
80 GND GND —
81 A21 A21 I, TS Address line 21
82 GND GND —
A
R
C
H
E
V
I
DAUGHTERBOARD
SIGNAL
BS3A I, L Byte Select 3 signal from UPMA. Selects offset
BS1A I, L Byte Select 1 signal from UPMA. Selects offset
REG_A I, TS, L Register Select Port A signal. TSIZ0/REG on
R
F
Y
B
D
E
E
S
C
A
INPUT/
OUTPUT
E SE
L
DESCRIPTION
three bytes within a word. Used as one of the
lines for DRAM access.
CAS
.
C
N
I
,
R
O
T
D
U
C
one byte within a word. Used as one of the
lines for DRAM access.
CAS
N
O
C
I
M
TSIZ0 to indicate the number of bytes
remaining in an operand transfer. Not used on
this board.
the MPC821. Used with the PCMCIA port to
select attribute memory or I/O space.
83 A20 A20 I, TS Address line 20
84 GND GND —
85 A7 A7 I, TS Address line 7
86 GND GND —
87 A15 A15 I, TS Address line 15
88 GND GND —
89 A14 A14 I, TS Address line 14
90 GND GND —
91 A13 A13 I, TS Address line 13
92 GND GND —
93 A6 A6 I, TS Address line 6
94 GND GND —
95 A12 A12 I, TS Address line 12
96 GND GND —
97 A11 A11 I, TS Address line 11
98 GND GND —
MOTOROLA
MPC821FADS-DB USER’S MANUAL
5-15
Signal Descriptions
Table 5-9. PM1 Interconnect Signals (Continued)
PIN MOTHERBOARD
SIGNAL
99 A19 A19 I, TS Address line 19
100 GND GND —
101 A9 A9 I, TS Address line 9
102 GND GND —
103 A18 A18 I, TS Address line 18
104 GND GND —
105 A10 A10 I, TS Address line 10
106 GND GND —
107 A17 A17 I, TS Address line 17
108 GND GND —
109 A16 A16 I, TS Address line 16
110 GND GND —
111 A8 A8 I, TS Address line 8
112 GND GND —
113 A29 A29 I, TS Address line 29
114 GND GND —
115 A27 A27 I, TS Address line 27
116 GND GND —
A
R
C
H
E
V
I
DAUGHTERBOARD
SIGNAL
R
F
Y
B
D
E
E
S
C
A
INPUT/
OUTPUT
E SE
L
M
U
D
N
O
C
I
DESCRIPTION
I
,
R
O
T
C
N
C
.
117 A28 A28 I, TS Address line 28
118 GND GND —
119 A26 A26 I, TS Address line 26
120 GND GND —
121 A25 A25 I, TS Address line 25
122 GND GND —
123 A24 A24 I, TS Address line 24
124 GND GND —
125 A22 A22 I, TS Address line 22
126 GND GND —
127 A3 A3 I, TS Address line 3. Not used on this board.
128 GND GND —
129 A23 A23 I, TS Address line 23
130 GND GND —
131 A4 A4 I, TS Address line 4. Not used on this board.
132 GND GND —
5-16
MPC821FADS-DB USER’S MANUAL
MOTOROLA
Table 5-9. PM1 Interconnect Signals (Continued)
Signal Descriptions
PIN MOTHERBOARD
SIGNAL
133 A2 A2 I, TS Address line 2. Not used on this board.
134 GND GND —
135 A5 A5 I, TS Address line 5. Not used on this board.
136 GND GND —
137 A1 A1 I, TS Address line 1. Not used on this board.
138 GND GND —
139 A0 A0 I, TS Address line 0. Not used on this board.
140 GND GND —
NOTE: I = Input, O = Output, L = Low, X = Don’t Care, OD = Open-Drain, and TS = Three-State.
PIN MOTHERBOARD
SIGNAL
1
2
3
4
5
6
V12 V12 O
C
R
A
E
V
I
H
———
DAUGHTERBOARD
SIGNAL
INPUT/
OUTPUT
O
C
I
M
E SE
L
S
C
A
INPUT/
OUTPUT
10V output from voltage doubler. Used to
switch TMOS gates on the motherboard and
daughterboard. Should not be used for any
other purpose.
Table 5-10. PM2 Interconnect Signals
R
SIGNAL
F
E
E
DAUGHTERBOARD
Y
B
D
N
DESCRIPTION
C
U
D
DESCRIPTION
T
O
R
,
I
N
C
.
7 DSDI DSDI I/O Debug Port Serial Data Input or JTAG Port
8
9
10 DSCK DSCK I/O Debug Port Serial Clock input or JTAG Port
11 DSDO DSDO I Debug Port Serial Data Output or JTAG Port
12
13
GND GND —
GND GND —
Serial Data Input. Used on the MPC8xxFADS
as a debug port serial data driven by the debug
port controller. If the ADI bundle is not
connected to the MPC8xxFADS, this signal
can be driven by the external debug / JTAG
port controller.
Serial Clock input. Used on the MPC8xxFADS
as a debug port serial clock driven by the
debug port controller. If the ADI bundle is not
connected to the MPC8xxFADS, this signal
can be driven by the external debug / JTAG
port controller.
Data Output. Used on the MPC8xxFADS as
debug port serial data. If the ADI bundle is not
connected to the MPC8xxFADS, this signal
can be used by the external debug / JTAG port
controller.
MOTOROLA
MPC821FADS-DB USER’S MANUAL
5-17
Signal Descriptions
Table 5-10. PM2 Interconnect Signals (Continued)
PIN MOTHERBOARD
SIGNAL
14 AT2 AT2 I/O Configured as AT2, but may be configured to
15 GND GND —
16 VF2 VF2 I/O Visible Instruction Queue Flushes Status 2.
17 GND GND —
18 VF0 VF0 I/O Visible Instruction Queue Flushes Status 0
19
20
21
22 IRQ3
23 GND GND —
24 FRZ FRZ I, X Freeze signal. Used by the debug port
25 GND GND —
26 IRQ2
GND GND —
E
V
I
H
C
R
A
DAUGHTERBOARD
SIGNAL
IRQ3 I/O, L Interrupt Request line 3. Pulled up, but
R
F
Y
B
D
IRQ2 I/O, L Interrupt Request line 2. Pulled up, but
E
E
S
C
A
INPUT/
OUTPUT
E SE
L
DESCRIPTION
another function, since it is not used on the
MPC8xxFADS.
.
C
N
R
,
I
signal. IP_B3/IWP2/VF2 on the MPC821.
O
T
C
N
D
U
signal. IP_B4/LWP0/VF0 on the MPC821.
O
C
I
M
otherwise unused on this board.
controller as a debug state indication. May be
configured to another function if the VFLS[0:1]
signal functions as VFLS and J1 is moved to
position 1 or 2.
otherwise unused on this board.
27
28
29
30 AT3 AT3 I/O Address Type 3 signal. IP_B7/PTR
31 GND GND —
32 SPARE4
33 GND GND —
34 VFLS0 VFLS0 I/O Visible History Flushes Status 0 signal. IP_B0/
35 GND GND —
36 SPKROUT SPKROUT I, X Speaker Output signal. KR
37 GND GND —
GND GND —
SPARE4 I/O Spare line 4. Pulled up, but otherwise unused
MPC821.
on this board.
IWP0/VFLS0 on the MPC821. This signal can
be configured for another function. In
conjunction with VFLS1, this signal indicates
the number of instructions flushed from the
core’s history buffer. It also indicates whether
the MPC821 is in debug mode.
on the MPC821. This signal can be configured
for another function. It is mainly used for a
PCMCIA notification alert.
/IRQ4/SPKROUT
/AT3 on the
5-18
MPC821FADS-DB USER’S MANUAL
MOTOROLA
Table 5-10. PM2 Interconnect Signals (Continued)
Signal Descriptions
PIN MOTHERBOARD
SIGNAL
38 VFLS1 VFLS1 I/O Visible History Flushes Status 1 signal. IP_B1/
39
40
41
42 VF1 VF1 — Visible Instruction Queue Flushes Status 1
43 GND GND —
44 AT1 AT1 — Address Type 1 signal. ALE_B/DSCK/AT1 on
45 GND GND —
46 AT0 AT0 I Address Type 0 signal. IP_B6/DSDI/AT0 on
47 GND GND —
48 POE_A
GND GND —
E
V
I
H
C
R
A
DAUGHTERBOARD
SIGNAL
R
F
Y
B
D
POE_A I, L PCMCIA Buffers Output Enable signal. The
E
E
S
C
A
INPUT/
OUTPUT
E SE
L
DESCRIPTION
IWP1/VFLS1 on the MPC821. In conjunction
with VFLS0, this signal indicates the number of
instructions flushed from the core’s history
buffer. It also indicates whether the MPC821 is
in debug mode. If you are not using the debug
port, this signal can be configured for another
function.
T
C
U
D
N
O
C
I
signal. IP_B5/LWP1/VF1 on the MPC821. This
M
signal can be configured to another function if
you are not using it on the MPC8xxFADS.
the MPC821. Not used on this board. May be
configured for another function.
the MPC821.
OP1 signal of the PCMCIA interface. Enables
address buffers towards the PC card.
O
R
,
I
N
C
.
49
50
51
52 BADDR30 BADDR30 I/O,X Burst Address line 30. Dedicated for external
53 GND GND —
54 ALE_A ALE_A I, H Address Latch Enable signal for PCMCIA Slot
55 GND GND —
56 BADDR29 BADDR29 I/O,X Burst Address line 29. Dedicated for external
57 GND GND —
58 AS
59 GND GND —
GND GND —
AS I/O, L Address Strobe signal. When asserted by the
master support. Used to generate a burst
address during external master burst cycles.
Pulled up, but otherwise unused on this board.
A. Latches the address in external latches at
the beginning of an access to a PC card.
master support. Used to generate a burst
address during external master burst cycles.
Pulled up, but otherwise unused on this board.
external master, the MPC821 recognizes that
an asynchronous cycle is in progress. Pulled
up, but otherwise unused on this board.
MOTOROLA
MPC821FADS-DB USER’S MANUAL
5-19
Signal Descriptions
Table 5-10. PM2 Interconnect Signals (Continued)
PIN MOTHERBOARD
SIGNAL
60 MODCK1 MODCK1 I/O Mode Clock 1 signal. OP2/MODCK1/STS
61 GND GND —
62 RESETA RESETA I,H Reset signal for PCMCIA port A.
63
64
65
66 BADDR28 BADDR28 I/O,X Burst Address line 28. Dedicated for external
67 GND GND —
68 TEXP TEXP X,X Timer Expired signal. Not used on this board.
69 GND GND —
70 WAIT_B
71 GND GND —
72 MODCK2 MODCK2 I/O Mode Clock 2 signal. OP3/MODCK2/DSDO on
73
74
GND GND —
E
V
I
H
C
R
A
GND GND —
DAUGHTERBOARD
SIGNAL
WAIT_B I/O, L Wait signal for PCMCIA Slot B. Pulled up, but
R
F
Y
B
D
E
E
S
C
A
INPUT/
OUTPUT
E SE
L
DESCRIPTION
the MPC821. Used at power-on reset.
.
C
N
I
,
R
O
T
C
U
D
N
O
master support. Used to generate a burst
C
address during external master burst cycles.
I
Pulled up, but otherwise unused on this board.
M
otherwise unused on this board.
the MPC821. Used at power-on reset as
MODCK2 and configured afterwards as OP3.
This signal can be configured for another
function.
on
75
76 — — — Not connected.
77
78
79
80 SRESET
81 GND GND —
82 PORST
83 GND GND —
84 HRESET
85 GND GND —
GND GND —
SRESET I/O, L, OD Soft Reset signal. This signal is driven by
PORST X, L Power-On Reset signal. Not used on the
HRESET I/O, L, OD Hard Reset signal. This signal is driven by
onboard logic and may be driven by offboard
logic with open-drain gate only.
MPC8xxFADS, but generated on the
daughterboard.
onboard logic and may be driven by offboard
logic with open-drain gate only.
5-20
MPC821FADS-DB USER’S MANUAL
MOTOROLA
Table 5-10. PM2 Interconnect Signals (Continued)
Signal Descriptions
PIN MOTHERBOARD
SIGNAL
86 RSTCNF
87 GND GND —
88 R_PORI
89
90
91
92 BWAITA
93 GND GND —
94 BWP BWP O, H Buffered Write-Protect signal for PCMCIA slot
95 GND GND —
96 BVS1 BVS1 O,X Buffered Voltage Sense 1 signal for PCMCIA
97 GND GND —
GND GND —
E
V
I
H
C
R
A
DAUGHTERBOARD
SIGNAL
RSTCNF O, L Hard Reset Configuration signal. It is driven
R_PORI O, L Main battery power-on reset signal. Generated
BWAITA O, L Buffered Wait signal for PCMCIA slot A. Used
R
F
Y
B
D
E
E
S
C
A
INPUT/
OUTPUT
E SE
L
DESCRIPTION
during hard reset to the daughterboard to tell
the MPC821 that it should sample hard reset
configuration from the data bus.
.
C
N
I
O
R
,
when the main 3.3V bus goes through
power-up or power-down. Drives onboard logic
as well hard reset or power-on reset to the
MPC821.
D
N
O
C
I
U
C
T
M
to prolong cycles to slow PC cards.
A. IP_A2/IOIS16A
PC card write-protect indication or as 16-bit I/O
capability indication for PCMCIA slot A.
slot A. IP_A0 on the MPC821. Used in
conjunction with BVS2 to determine the
operation voltage of a PCMCIA card.
on the MPC821. Used as
98 BRDY BRDY O, H Buffered Ready signal for PCMCIA slot A.
99
100
101
102 DP3 DP3 I/O, X Data Parity line 3. DP3/IRQ6
103 GND GND —
104 BVS2 BVS2 O, X Buffered Voltage Sense 2 signal for PCMCIA
105 GND GND —
106 BCD1
107 GND GND —
GND GND —
BCD1 O, L Buffered Card Detect 1 signal for PCMCIA slot
IP_A7 on the MPC821. Used as PCMCIA port
A card ready indication.
This signal can generate and receive parity
data for the D[24:31] bits that are connected to
the DRAM SIMM. It may also be configured as
signal for the MPC821.
IRQ6
slot A. IP_A1 on the MPC821. Used in
conjunction with BVS1 to determine the
operation voltage of a PCMCIA card.
A. IP_A4 on the MPC821. Used as a card
detect indication in conjunction with BCD2
on the MPC821.
.
MOTOROLA
MPC821FADS-DB USER’S MANUAL
5-21
Signal Descriptions
Table 5-10. PM2 Interconnect Signals (Continued)
PIN MOTHERBOARD
SIGNAL
108 MODIN MODIN O, X Mode Clock In signal. This signal selects the
109 GND GND —
110 BBVD1 BBVD1 O, X Buffered Battery Voltage Detect 1 signal for
111 GND GND —
112 BCD2
113 GND GND —
114 BBVD2 BBVD2 O, X Buffered Battery Voltage Detect 2 signal
115
116
117 — — — Not connected.
118 DP0 DP0 I/O Data Parity line 0. DP0/IRQ3
GND GND —
E
V
I
H
C
R
A
DAUGHTERBOARD
SIGNAL
BCD2 O, L Buffered Card Detect 2 signal for PCMCIA slot
R
F
Y
B
D
E
E
S
C
A
INPUT/
OUTPUT
E SE
L
DESCRIPTION
4MHz clock generator or the 32768Hz crystal
as clock sources for the MPC821. Its is driven
by the DS2/4 signal.
.
C
N
I
O
,
R
on the MPC821.
PCMCIA slot A. IP_A6 on the MPC821. Used
in conjunction with BBVD2 to determine the
battery status of a PC card.
D
N
O
A. IP_A3 on the MPC823. Used as a card
C
I
detect indication in conjunction with BCD1
M
PCMCIA slot A. IP_A5 on the MPC821. Used
in conjunction with BBVD1 to determine the
battery status of a PC card.
This signal can generate and receive parity
data for the D[0:7] signals that are connected to
the DRAM SIMM. It may not be configured as
.
IRQ3
U
C
T
.
119 V3.3 V3.3 —
120 DP2 DP2 I/O Data Parity line 2. DP2/IRQ5
121 V3.3 V3.3 —
122 DP1 DP1 I/O Data Parity line1. DP1/IRQ4
123 V3.3 V3.3 —
124 — — — Not connected.
125 V3.3 V3.3 —
126 IRQ1
127 V3.3 V3.3 —
128 SPARE3
129 V3.3 V3.3 —
IRQ1 I/O, L Interrupt Request line 1.Pulled up, but
SPARE3 I/O, X Spare line 3. Pulled up, but otherwise unused
This signal can generate and receive parity
data for the D[16:23] signals that are
connected to the DRAM SIMM. It may not be
configured as IRQ5
This signal can generate and receive parity
data for the D[8:15] signals that are connected
to the DRAM SIMM. It may not be configured
as IRQ4
otherwise unused on this board.
on this board.
.
.
on the MPC821.
on the MPC821.
5-22
MPC821FADS-DB USER’S MANUAL
MOTOROLA
Table 5-10. PM2 Interconnect Signals (Continued)
Signal Descriptions
PIN MOTHERBOARD
SIGNAL
130 IRQ7
131 V3.3 V3.3
132 — — — Not connected.
133 V3.3 V3.3 —
134 NMI
135 V3.3 V3.3 —
136 — — — Not connected.
137 V3.3 V3.3 —
138 — — — Not connected.
139 V3.3 V3.3 —
140 — — — Not connected.
NOTE: I = Input, O = Output, L = Low, X = Don’t Care, OD = Open-Drain, and TS = Three-State.
E
V
I
H
C
R
A
DAUGHTERBOARD
SIGNAL
MIITXCLK I/O, L Interrupt Request line 7. This signal is the
NMI I/O, L Non-Maskable Interrupt signal. IRQ0 on the
R
F
Y
B
D
E
E
S
C
A
INPUT/
OUTPUT
E SE
L
—
DESCRIPTION
lowest priority interrupt request line. Pulled up,
but otherwise unused on this board.
R
O
T
D
U
C
MPC821. This signal is driven by onboard logic
by an open-drain gate. Pulled up. It may be
driven offboard only by an open-drain gate.
N
O
C
I
M
Table 5-11. PM3 Interconnect Signals
,
I
N
C
.
PIN MOTHERBOARD
SIGNAL
1 ETHRX ETHRX O, X Ethernet Port Receive Data signal. When the
2
3
4 UUFEN
5 ETHTX ETHTX I, X Ethernet Port Transmit Data signal. Also
6
7
8 PC9 PC9 X, X Port C Bit 9. Also appears at P8, but is
9 IRDRXD IRDRXD O, X Infra-Red Port Receive Data signal. When the
10 GND GND —
11 IRDTXD IRDTXD I, X Infra-Red Port Transmit Data signal. Also
GND GND —
GND GND —
DAUGHTERBOARD
SIGNAL
UUFEN O, L Not used on this board.
INPUT/
OUTPUT
Ethernet port is disabled via the BCSR1, it is
three-stated. This signal also appears at P8.
appears at P8.
otherwise unused on the this board.
I/R port is disabled via the BCSR1, this signal
is three-stated. This signal also appears at P8.
appears at P8.
DESCRIPTION
MOTOROLA
MPC821FADS-DB USER’S MANUAL
5-23
Signal Descriptions
Table 5-11. PM3 Interconnect Signals (Continued)
PIN MOTHERBOARD
SIGNAL
12
13
14 PC8 PC8 I/O, X Port C Bit 8. Also appears at P8, but is
15 PA11 PA11 I/O, X Port A Bit 11. Also appears at P8, but is
16 GND GND —
17 PA10 PA10 I/O, X Port A Bit 10. Also appears at P8, but is
18
19
20 PC7 PC7 I/O, X Port C Bit 7. Also appears at P8, but is
21 PA9 PA9 I/O, X Port A Bit 9. Also appears at P8, but is
22 GND GND —
23 PA8 PA8 I/O, X Port A Bit 8. Also appears at P8, but is
24
25
26 PC13 PC13 I/O, X Port C Bit 13. Also appears at P8, but is
GND GND —
GND GND —
E
V
I
GND GND —
H
C
R
A
DAUGHTERBOARD
SIGNAL
R
F
Y
B
D
E
E
S
C
A
INPUT/
OUTPUT
E SE
L
otherwise unused.
otherwise unused.
otherwise unused.
N
O
C
I
M
otherwise unused.
otherwise unused.
otherwise unused.
otherwise unused.
DESCRIPTION
C
U
D
T
O
R
,
I
N
C
.
27 ETHTCK ETHTCK O, X Ethernet Port Transmit Clock signal. When the
28 GND GND —
29 ETHRCK ETHRCK O, X Ethernet Port Receive Clock signal. When the
30
31
32 USBSPD
33 PB31 PB31 I/O, X Port B Bit 31. Also appears at P8, but is
34 BINPAK
35 PB30 PB30 I/O, X Port B Bit 30. Also appears at P8, but is
36 GND GND —
37 PB29 PB29 I/O, X Port B Bit 29. Also appears at P8, but is
GND GND —
— O, X Unused on this board.
BINPAK I/O PCMCIA Port Input Port Acknowledge signal.
Ethernet port is disabled via the BCSR1, this
signal is three-stated. Also appears at P8.
Ethernet port is disabled via the BCSR1 , this
signal is three-stated. Also appears at P8.
otherwise unused.
PC15/DREQ1
When the PCMCIA port is disabled via the
BCSR1, this signal can be used off-board for
another function.
otherwise unused.
otherwise unused.
/RTS1/L1ST1 on the MPC821.
5-24
MPC821FADS-DB USER’S MANUAL
MOTOROLA
Table 5-11. PM3 Interconnect Signals (Continued)
Signal Descriptions
PIN MOTHERBOARD
SIGNAL
38 RSTXD1 RSTXD1 I, X RS-232 Port 1 Transmit Data signal. When the
39 RSRXD1 RSRXD1 O, X RS-232 Port 1 Receive Data signal. When the
40 RSDTR1
41 GND GND —
42 RSTXD2 RSTXD2 I, X RS-232 Port 2 Transmit Data signal. When the
43 RSRXD2 RSRXD2 O, X RS-232 Port 2 Receive Data signal. When the
44 RSDTR2
E
V
C
H
I
45 PC14 PC14 I/O, X Port C Bit 14. Also appears at P8, but is
R
46 GND GND —
A
DAUGHTERBOARD
SIGNAL
RSDTR1 O, L RS-232 Port 1 DTR signal. When the RS-232
R
F
RSDTR2 O, L RS-232 Port 2 DTR signal. When the RS-232
Y
B
D
E
E
S
C
A
INPUT/
OUTPUT
E SE
L
DESCRIPTION
RS-232 port 1 is disabled via the BCSR1, this
signal can be used for another function. Also
appears at P8.
.
,
I
N
C
RS-232 port 1 is disabled via the BCSR1, this
signal is three-stated and may be used for
another function. Also appears at P8.
port 1 is disabled via the BCSR1, this signal is
three-stated and may be used for another
function. Also appears at P8.
N
O
C
I
D
U
C
T
O
R
M
RS-232 port 2 is disabled via the BCSR1, this
signal can be used for another function. Also
appears at P8.
RS-232 port 2 is disabled via the BCSR1, this
signal is three-stated and can be used for
another function. Also appears at P8.
port 2 is disabled via the BCSR1, this signal is
three-stated and can be used for another
function. Also appears at P8.
otherwise unused.
47 — — — Not connected.
48
49
50 PB27 PB27 I/O, X Port B Bit 27. Also appears at P8, but is
51 PB28 PB28 I/O, X Port B Bit 28. Also appears at P8, but is
52 GND GND —
53 PC12 PC12 I/O, X Port C Bit 12. Also appears at P8, but is
54 PB26 PB26 I/O, X Port B Bit 26. Also appears at P8, but is
55
56
57 PA5 PA5 I/O, X Port A Bit 5. Also appears at P8, but is
58
59
60 PA4 PA4 I/O, X Port A Bit 4. Also appears at P8, but is
GND GND —
otherwise unused.
otherwise unused.
otherwise unused.
otherwise unused.
GND GND —
otherwise unused.
GND GND —
otherwise unused.
MOTOROLA
MPC821FADS-DB USER’S MANUAL
5-25
Signal Descriptions
Table 5-11. PM3 Interconnect Signals (Continued)
PIN MOTHERBOARD
SIGNAL
61 E_CLSN E_CLSN I/O, H Ethernet Port Collision signal. It is connected to
62 E_RENA E_RENA I/O, H Ethernet Receive Enable signal. It is
63 SPARE2 — I/O, X Spare line 2. Pulled up, but otherwise unused
64 VDOEN
DAUGHTERBOARD
SIGNAL
— O, L Unused on this board.
INPUT/
OUTPUT
DESCRIPTION
the serial communication controller’s CTS
signal. When the Ethernet port is disabled via
the BCSR1, this signale can be used off-board
for another function.
C
N
R
,
I
connected to the serial communication
controller’s CD
network activity. When the Ethernet port is
disabled via the BCSR1, this signal can be
used off-board for another function.
N
on the this board.
O
C
I
signal. It is active when there is
O
T
C
U
D
.
M
65
66
67 SYSCLK SYSCLK I, X System Clock signal. CLKOUT on the
68
69
70
71 PA3 PA3 I/O, X Port A Bit 3. Also appears at P8, but is
72
73
GND GND —
S
E
E
R
F
B
Y
GND GND —
D
E
V
I
H
C
R
A
GND GND —
C
A
E SE
L
MPC821.
otherwise unused.
74 PA2 PA2 I/O, X Port A Bit 2. Also appears at P8, but is
75 PB17 PB17 I/O, X Port B Bit 17. Also appears at P8, but is
76 PB18 PB18 I/O, X Port B Bit 18. Also appears at P8, but is
77 E_TENA E_TENA I/O, H Ethernet Port Transmit Enable signal. It is
78 GND GND —
79
80
81
82 ETHEN
83 — — — Not connected.
84 IRD_EN
———
ETHEN O, L Ethernet Port Enable signal. It is connected to
IRD_EN O, L Infra-Red Enable signal. It is connected to the
otherwise unused.
otherwise unused.
otherwise unused.
connected to the serial communication
controller’s RTS
active, transmit is enabled via the MC68160
EEST. When the Ethernet port is disabled via
the BCSR1, this signal can be used off-board
for another function.
Not connected.
the BCSR1.
BCSR1.
signal. When this signal is
5-26
MPC821FADS-DB USER’S MANUAL
MOTOROLA
Table 5-11. PM3 Interconnect Signals (Continued)
Signal Descriptions
PIN MOTHERBOARD
SIGNAL
85 PA1 PA1 I/O, X Port A Bit 1. Also appears at P8, but is
86
87
88 — — — Not connected.
89 PA0 PA0 I/O, X Port A Bit 0. Also appears at P8, but is
90 GND GND —
91
92 TMS TMS I/O, X JTAG Port Test Mode Select signal. It is used
93 PB16 PB16 I/O, X Port B Bit 16. Also appears at P8, but is
94 TRST
95 PB15 PB15 I/O, X Port B Bit 15. Also appears at P8, but is
96 RS_EN1
97 PB14 PB14 I/O, X Port B Bit 14. Also appears at P8, but is
GND GND —
E
V
I
H
C
R
A
DAUGHTERBOARD
SIGNAL
TRST O, L JTAG Port Reset signal. Pulled down with a
R
F
Y
B
D
RS_EN1 O, L RS-232 Port 1 Enable signal. It is connected to
E
E
S
C
A
INPUT/
OUTPUT
E SE
L
DESCRIPTION
otherwise unused.
.
C
N
I
,
R
O
U
C
T
otherwise unused.
D
N
O
C
I
M
to select testing through the JTAG port. Pulled
up, but is otherwise unused on this board.
otherwise unused.
zero ohm resistor so that the JTAG logic is
constantly reset. Otherwise, it is unused on this
board.
otherwise unused.
the BCSR1.
otherwise unused.
98 PC4 PC4 I/O, X Port C Bit 4. Also appears at P8, but is
99 PC5 PC5 I/O, X Port C Bit 5. Also appears at P8, but is
100 PC6 PC6 I/O, X Port C Bit 6. Also appears at P8, but is
101 GND GND —
102 RS_EN2
103 SHIFT_C SHIFT_C I/O, X Shift Clock signal. PD3/SHIFT/CLK on the
104
105
106 HSYNC HSYNC I/O, X Horizontal Sync signal. PD4/LOAD/HSYNC on
107 VSYNC VSYNC I/O, X Vertical Sync signal. PD5/FRAME/VSYNC on
GND GND —
RS_EN2 O, L RS-232 Port 2 Enable signal. It is connected to
otherwise unused.
otherwise unused.
otherwise unused.
the BCSR1.
MPC821. Not used on the MPC8xxFADS
motherboard. Also appears at P8 and a
dedicated LCD connector.
the MPC821. Not used on the MPC8xxFADS
motherboard. Also appears at P8 and a
dedicated LCD connector.
the MPC821. Not used on the MPC8xxFADS
motherboard. Also appears at P8 and a
dedicated LCD connector.
MOTOROLA
MPC821FADS-DB USER’S MANUAL
5-27
Signal Descriptions
Table 5-11. PM3 Interconnect Signals (Continued)
PIN MOTHERBOARD
SIGNAL
108
109
110 LOE LOE I/O, X LCD Output Enable signal. PD6/LCD_AC/LOE
111 VDORST
112 VDOEXTCK — O, H Unused on this board.
113 LD0 LD0 I/O, X LCD Data line 0. PD7/LD0 on th e MPC821.
114 LD1 LD1 — LCD Data line 1. PD8/LD1 on the MPC821. Not
115 LD2 LD2 I/O, X LCD Data line 2. PD9/LD2 on the MPC821. Not
116 LD3 LD3 I/O, X LCD Data line 3 PD10/LD3 on the MPC821.
117 LD4 LD4 I/O, X LCD Data line 4. PD11/LD4 on the MPC821.
118 LD5 LD5 I/O LCD Data line 5. PD12/LD5 on the MPC821.
GND GND —
E
V
I
H
C
R
A
DAUGHTERBOARD
SIGNAL
R
F
Y
B
D
INPUT/
OUTPUT
on the MPC821. Not used on the
MPC8xxFADS motherboard. Also appears at
P8 and a dedicated LCD connector.
— O, L Unused on this board.
N
Not used on the MPC8xxFADS motherboard.
O
Also appears at P8 and a dedicated LCD
C
I
connector.
M
used on the MPC8xxFADS motherboard. Also
appears at P8 and a dedicated LCD connector.
used on the MPC8xxFADS motherboard. Also
appears at P8 and a dedicated LCD connector.
Not used on the MPC8xxFADS motherboard.
Also appears at P8 and a dedicated LCD
connector.
Not used on the MPC8xxFADS motherboard.
Also appears at P8 and a dedicated LCD
connector.
Not used on the MPC8xxFADS motherboard.
Also appears at P8 and a dedicated LCD
connector.
E
E
S
C
A
E SE
L
DESCRIPTION
C
U
D
T
O
R
,
I
N
C
.
119 LD6 LD6 I/O, X LCD Data line 6. PD13/LD6 on the MPC821.
120 LD7 LD7 I/O, X LCD Data line 7. PD14/LD7 on the MPC821.
121 LD8 LD8 I/O, X LCD Data line 8. PD15/LD8 on the MPC821.
122
123
124 ETHLOOP ETHLOOP O, H Ethernet Transceiver Diagnostic Loop-Back
125 TPFLDL
126 TPSQEL
127 MDM_AUD
GND GND —
TPFLDL O, L Twisted-Pair Full Duplex signal. Allows for
TPSQEL O, L Twisted-Pair Signal Quality Error Test Enable
MDM_AUD O, L Modem Audio signal. Unused on this board.
Not used on the MPC8xxFADS motherboard.
Also appears at P8 and a dedicated LCD
connector.
Not used on the MPC8xxFADS motherboard.
Also appears also at P8 and a dedicated LCD
connector.
Not used on the MPC8xxFADS motherboard.
Also appears at P8 and a dedicated LCD
connector.
signal. Generated by the BCSR4.
full-duplex operation over a Ethernet Twisted-
Pair channel.
signal.
5-28
MPC821FADS-DB USER’S MANUAL
MOTOROLA
Table 5-11. PM3 Interconnect Signals (Continued)
Signal Descriptions
PIN MOTHERBOARD
SIGNAL
128 MODEMEN
129 — — — Not connected.
130 GND GND —
131
132
133
134
135
136
137
138
139
140
NOTE: I = Input, O = Output, L = Low, H = High, and X = Don’t Care.
———
VCC VCC —
E
V
I
H
C
R
A
DAUGHTERBOARD
SIGNAL
MODEMEN O, L Modem Enable signal. Unused on this board.
INPUT/
OUTPUT
Not connected.
O
C
I
M
E SE
L
A
C
S
E
E
R
F
Y
B
D
Table 5-12. PM4 Interconnect Signals
N
D
DESCRIPTION
O
T
C
U
R
,
I
N
C
.
PIN MOTHERBOARD
SIGNAL
1 GND GND —
2 D31 D31 I/O, X Data line 31
3 GND GND —
4 D30 D30 I/O, X Data line 30
5 GND GND —
6 D29 D29 I/O, X Data line 29
7 GND GND —
8 D28 D28 I/O, X Data line 28
9
10
11
12 D27 D27 I/O, X Data line 27
13 GND GND —
14 D26 D26 I/O, X Data line 26
GND GND —
DAUGHTERBOARD
SIGNAL
INPUT/
OUTPUT
DESCRIPTION
MOTOROLA
MPC821FADS-DB USER’S MANUAL
5-29
Signal Descriptions
Table 5-12. PM4 Interconnect Signals (Continued)
PIN MOTHERBOARD
SIGNAL
15 GND GND —
16 D25 D25 I/O, X Data line 25
17 GND GND —
18 D24 D24 I/O, X Data line 24
19
20
21
22 D23 D23 I/O, X Data line 23
23 GND GND —
24 D22 D22 I/O, X Data line 22
25 GND GND —
26 D21 D21 I/O, X Data line 21
27 GND GND —
28 D20 D20 I/O, X Data line 20
29
30
31
32 D19 D19 I/O, X Data line 19
GND GND —
E
V
I
GND GND —
H
C
R
A
DAUGHTERBOARD
SIGNAL
R
F
Y
B
D
E
E
S
C
A
OUTPUT
E SE
L
INPUT/
M
D
N
O
C
I
DESCRIPTION
O
T
C
U
R
,
I
N
C
.
33 GND GND —
34 D18 D18 I/O, X Data line 18
35 GND GND —
36 D17 D17 I/O, X Data line 17
37 GND GND —
38 D16 D16 I/O, X Data line 16
39
40
41
42 D15 D15 I/O, X Data line 15
43 GND GND —
44 D14 D14 I/O, X Data line 14
45 GND GND —
46 D13 D13 I/O, X Data line 13
47 GND GND —
48 D12 D12 I/O, X Data line 12
GND GND —
5-30
MPC821FADS-DB USER’S MANUAL
MOTOROLA
Table 5-12. PM4 Interconnect Signals (Continued)
Signal Descriptions
PIN MOTHERBOARD
SIGNAL
49
50
51
52 D11 D11 I/O, X Data line 11
53 GND GND —
54 D10 D10 I/O, X Data line 10
55 GND GND —
56 D9 D9 I/O, X Data line 9
57 GND GND —
58 D8 D8 I/O, X Data line 8
59
60
61
62 D7 D7 I/O, X Data line 7
63 GND GND —
64 D6 D6 I/O, X Data line 6
65 GND GND —
66 D5 D5 I/O, X Data line 5
GND GND —
GND GND —
E
V
I
H
C
R
A
DAUGHTERBOARD
SIGNAL
R
F
Y
B
D
E
E
S
C
A
OUTPUT
E SE
L
INPUT/
M
D
N
O
C
I
DESCRIPTION
O
T
C
U
R
,
I
N
C
.
67 GND GND —
68 D4 D4 I/O, X Data line 4
69
70
71
72 D3 D3 I/O, X Data line 3
73 GND GND —
74 D2 D2 I/O, X Data line 2
75 GND GND —
76 D1 D1 I/O, X Data line 1
77 GND GND —
78 D0 D0 I/O, X Data line 0
79
80
81 DRMH_W
GND GND —
GND GND —
DRMH_W O, L DRAM Half Word signal. Sets the DRAM to
16-bit data bus width.
MOTOROLA
MPC821FADS-DB USER’S MANUAL
5-31
Signal Descriptions
Table 5-12. PM4 Interconnect Signals (Continued)
PIN MOTHERBOARD
SIGNAL
82 DRAMEN
83 FCFGEN
84 F_EN
85 SDRAMEN SDRAMEN O, H SDRAM Enable signal. Enables the
86 BCSREN
87 USBVCC0 — O, X Unused on this board.
88 PCCEN
89 EXTOLI0 EXTOLI0 I/O, X External Tool Identification 0 signal.
90 SGLAMP
91 EXTOLI2 EXTOLI2 I/O, X External Tool Identification 2 signal.
E
V
C
H
I
92 USBVCC1 — O, X Unused on this board.
93 DBREV0 DBREV0 I, X Daughterboard Revision Code 0 signal. The
94 EXTOLI1 EXTOLI1 I/O, X External Tool Identification 1 signal.
A
R
DAUGHTERBOARD
SIGNAL
DRAMEN O, L DRAM Enable signal. Enables DRAM to the
FCFGEN O, L Flash Configuration Enable signal. Allows
F_EN O, L Flash Enable signal. Enables the Flash
BCSREN O, L BCSR Enable signal. Enables the BCSR to
PCCEN O, L PC Card Enable signal. Enables the PC card
R
F
Y
B
D
INPUT/
OUTPUT
MPC8xxFADS memory map.
hard reset configuration to be obtained from
the Flash memory if this option is supported
by the MPC821.
memory to the MPC8xxFADS memory map.
synchronous DRAM to the MPC8xxFADS
memory map.
N
O
C
I
the MPC8xxFADS memory map.
M
E SE
L
A
C
S
E
E
— O, L Unused on this board.
to be accessed by the MPC8xxFADS.
Connected to the BCSR2.
Connected to the BCSR2.
MSB of the daughterboard revision code.
Connected to the BCSR2.
D
U
C
DESCRIPTION
O
T
R
,
I
N
C
.
95 DBREV2 DBREV2 I, X Daughterboard Revision Code 2 signal. The
96 EXTOLI3 EXTOLI3 I/O, X External Tool Identification 3 signal.
97 BCSR3R1 BCSR3R1 I/O, X Board Control and Status Register 3
98 DBREV1 DBREV1 I/O, X Daughterboard Revision Code 1 signal.
99 DBID1 DBID1 I/O, X Daughterboard ID Code 1 signal. It is part of
100 BCSR3R0 BCSR3R0 I/O, X Board Control and Status Register 3
101 DBID3 DBID3 I/O, X Daughterboard ID Code 3 signal. It is part of
102 DBID0 DBID0 I/O, X Daughterboard ID Code 0 signal. It is part of
103 DBID5 DBID5 I/O, X Daughterboard ID Code 5 signal. Part of the
LSB of the daughterboard revision code.
Connected to the BCSR2.
Reserved 1 signal. It is the reserved signal 1
in BCSR3.
the field that designates the type of
daughterboard connected.
Reserved 0 signal. Reserved signal 0 in
BCSR3.
the field that designates the type of
daughterboard connected.
the field which designates the type of
daughterboard connected.
field that designates the type of
daughterboard connected.
5-32
MPC821FADS-DB USER’S MANUAL
MOTOROLA
Table 5-12. PM4 Interconnect Signals (Continued)
Signal Descriptions
PIN MOTHERBOARD
SIGNAL
104 DBID2 DBID2 I/O, X Daughterboard ID Code 2 signal. It is part of
105 BCSR3R13 BCSR3R13 I/O, X Reserved signal 13 in BCSR3.
106 DBID4 DBID4 I/O, X Daughterboard ID Code 4 signal. It is part of
107 CHINS
DAUGHTERBOARD
SIGNAL
CHINS I/O, L Chip In Socket signal. When this signal is
INPUT/
OUTPUT
DESCRIPTION
the field that designates the type of
daughterboard connected.
the field that designates the type of
daughterboard connected.
T
D
U
C
active (low), MPC8xxFADS logic notices that
the evaluated MPC821 resides in its socket. If
inactive, either the MPC821 is out of socket or
N
a daughterboard is not connected, in which
O
case the MPC8xxFADS becomes a
C
I
debugging station.
O
R
,
I
N
C
.
M
108
109
110
111
112
113
114
115
116
117
GND GND —
E
E
S
———
R
F
D
B
Y
GND GND —
E
V
I
———
H
C
R
A
GND GND —
C
A
E SE
L
Not connected.
Not connected.
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
———
GND GND —
———
GND GND —
———
GND GND —
———
GND GND —
Not connected.
Not connected.
Not connected.
Not connected.
MOTOROLA MPC821FADS-DB USER’S MANUAL 5-33
Signal Descriptions
Table 5-12. PM4 Interconnect Signals (Continued)
PIN MOTHERBOARD
SIGNAL
134
135
136
137
138
139
140 GND GND —
NOTE: I = Input, O = Output, L = Low, and X = Don’t Care.
———
GND GND —
———
DAUGHTERBOARD
SIGNAL
INPUT/
OUTPUT
Not connected.
Not connected.
D
N
O
C
I
DESCRIPTION
O
T
C
U
R
,
I
N
C
.
M
A
E SE
L
1
13.28mm
5.1.4 PX1 to PX4—Hardware Expansion Connectors
E
PX1
E
S
C
These connectors are receptacle interboard connectors manufactured by Molex. They are
identical to those on the MPC8xxFADS motherboard and their mechanical assembly is
1
Y
R
F
similar as well.
R
A
C
1
H
B
D
E
V
I
PX2 PX3
17.09mm
Figure 5-2. Expansion Connectors Mechanical Assembly
In principle, the expansion connectors are identical in signal assignment to the motherboard
connectors. However, there is a difference between PM3 and PX3, which is a result of the
5-34 MPC821FADS-DB USER’S MANUAL MOTOROLA
1
47.1mm
PX4
93.98mm
71.12mm
10.74mm
29.79mm
Signal Descriptions
difference between the various members of the MPC8xx Family. Therefore, in the following
tables only the differences are documented for each connector pair (PM1 and PX1, etc).
Table 5-13. PX1–PM1 Interconnect Signal Differences
PIN SIGNAL ATTRIBUTE DESCRIPTION
— — — No Difference.
,
R
O
T
C
U
O
N
D
Figure 5-3. PX2–PM2 Interconnect Signal Differences
M
C
I
PIN SIGNAL ATTRIBUTE DESCRIPTION
76 EXTCLK O, X External Clock. 4MHz clock generator output, the input clock to the
NOTE: O = Output and X = Don’t Care.
R
F
Y
B
Figure 5-4. PX3–PM3 Interconnect Signal Differences
PIN SIGNAL ATTRIBUTE DESCRIPTION
— — — No Difference.
A
R
C
H
D
E
V
I
E
E
S
MPC.
A
C
E SE
L
I
N
C
.
Figure 5-5. PX4–PM4 Interconnect Signal Differences
PIN SIGNAL ATTRIBUTE DESCRIPTION
— — — No Difference.
MOTOROLA MPC821FADS-DB USER’S MANUAL 5-35
Signal Descriptions
5.1.5 MPC8xxFADS’s P8—Serial Port Expansion Connector
P8 is a 96-pin, 900, DIN 41612 connector that allows you to conveniently expand the
MPC821 serial ports. Although this connector resides on the motherboard, it is documented
here since its signal assignment is unique for each MPC821. The contents of Table 5-14
may conflict with the MPC8xxFADS schematic. If there is such a conflict, use this table to
resolve it.
.
C
R
,
I
N
Table 5-14. P13 Interconnect Signals
C
T
O
PIN SIGNAL INPUT/
OUTPUT
A1 ETHRX I/O Ethernet Port Receive Data signal. See PM3(1).
A2 ETHTX I/O Ethernet Port Transmit Data signal. See PM3(5,11,42).
A3 IRDRXD I/O IrDA Port Receive Data signal. See PM3(9).
M
DESCRIPTION
N
O
C
I
D
U
A4 IRDTXD I/O IrDA Port Transmit Data signal. See PM3(5,11,42).
A5 LD4 I/O LCD Data line 4 signal. See PM3(117).
A6 LD3 I/O LCD Data line 3 signal. See PM3(116).
Y
R
F
A7 LD2 I/O LCD Data line 2 signal. See PM3(115).
A8 LD1 I/O LCD Data line 1 signal. See PM3(114).
A9 ETHTCK I/O Ethernet Port Transmit Clock signal. See PM3(27).
A10 ETHRCK I/O Ethernet Port Receive Clock signal. See PM3(29).
A11 — — Not connected.
A12 PA4 I/O Port A Bit 4. BRGCLK2/TOUT2
A13 — — Not connected.
A14 L1RCLKB I/O Receive Clock for TDM B. See PM3(74).
A15
A16
A17 VCC —
A18 PA9 I/O Port A Bit 9. See PM3(15,21).
A19 L1RXDB I/O Receive Data signal for TDM B. See PM3(17).
A
R
V
I
H
C
——
E
D
B
S
E
E
PM3(60).
Not connected.
C
A
E SE
L
/CLK4/PA[4] on the MPC821. See
A20 PA9 I/O Port A Bit 9. See PM3(21).
A21 L1RXDA I/O Receive Data signal for TDM A. See PM3(23).
A22 GND —
A23 GND —
A24 IRQ7
A25 FRZ I/O Freeze signal. See PM2(24).
A26 ETHEN O Ethernet Enable signal. See PM3(82).
A27 — — Not connected.
5-36 MPC821FADS-DB USER’S MANUAL MOTOROLA
I, L Interrupt Request line 7. See PM2(130).
Table 5-14. P13 Interconnect Signals (Continued)
Signal Descriptions
PIN SIGNAL INPUT/
OUTPUT
A28 IRQ2 I, L Interrupt Request line 2. RSV/IRQ2 on the MPC821. See PM2(26).
A29 IRQ1 I, L Interrupt Request line 1. See PM2(126).
A30 NMI
A31 RS_EN1 O,L Reset Enable 1 signal. See PM3(96).
A32 GND —
B1 PB31 I/O Port B Bit 31. See PM3(33).
B2 PB30 I/O Port B Bit 30. See PM3(35).
B3 PB29 I/O Port B Bit 29. See PM3(37).
B4 PB28 I/O Port B Bit 28. See PM3(51).
B5 I2CDAT I/O
B6 I2CCLK I/O
B7 RSTXD1 I/O RS-232 Transmit 1 signal. See PM3(38).
B8 RSRXD1 I/O RS-232 Receive 1 signal. See PM3(39).
E
D
B
B9 RSDTR1
B10 RSDTR2
B11 RSTXD2 I/O RS-232 Transmit Data 2 signal. See PM3(5,11,42).
B12 RSRXD2 I/O RS-232 Reveive Data 2 signal. See PM3(43).
A
R
C
H
V
I
I, L Non-Maskable Interrupt signal. See PM2(134).
M
2
I
C Data signal. See PM3(50).
E SE
L
A
2
C
I
C Clock signal. See PM3(54).
S
E
E
R
F
Y
I/O RS-232 Data Terminal Ready 1 signal. See PM3(40).
I/O RS-232 Data Terminal Ready 2 signal. See PM3(44).
DESCRIPTION
N
O
C
I
D
U
C
T
O
R
,
I
N
C
.
B13 E_TENA I/O Ethernet Transmit Enable signal. See PM3(77).
B14 PB19 I/O Port B Bit 19. See PM3(76).
B15 PB17 I/O Port B Bit 17. See PM3(75).
B16 PB16 I/O Port B Bit 16. See PM3(93).
B17 — — Not connected.
B18 — — Not connected.
B19 GND —
B20 BINPAK
B21 PC14 I/O Port C Bit 14. See PM3(45).
B22 PC13 I/O Port C Bit 13. See PM3(26).
B23 PC12 I/O Port C Bit 12. See PM3(53).
B24 E_CLSN I/O Ethernet Collision signal. See PM3(61).
B25 E_RENA I/O Ethernet Receive Enable signal. See PM3(62).
B26 USBRXP I/O Universal Serial Bus Receive Positive signal. PC11 on the MPC821.
B27 USBRXN I/O Universal Serial Bus Receive Negative signal. PC10 on the
I/O Buffered INPAK signal. See PM3(34).
See PM3(8).
MPC821. See PM3(14).
MOTOROLA MPC821FADS-DB USER’S MANUAL 5-37
Signal Descriptions
Table 5-14. P13 Interconnect Signals (Continued)
PIN SIGNAL INPUT/
OUTPUT
B28 USBTXP I/O Universal Serial Bus Transmit Positive signal. PC7 on the MPC821.
B29 L1RSYNCB I/O Receive Sync signal for TDM B. See PM3(100).
B30 PC5 I/O Port C Bit 5. See PM3(99).
B31 L1RSYNCA I/O Receive Sync signal for TDM A. See PM3(98).
B32 GND —
C1
C2
C3
VCC —
See PM3(20).
DESCRIPTION
N
O
C
I
D
U
C
T
O
R
,
I
N
C
.
M
C4
C5
C6 RS_EN2
C7
C8
C9
C10
C11
C12
A
R
V
I
GND —
H
C
E
D
B
E
E
S
C
O, L RS-232 Enable 2 signal. See PM3(102).
R
F
Y
A
E SE
L
C13
C14
C15 LD8 I/O LCD Data line 8. See PM3(121).
C16 LD7 I/O LCD Data line 7. See PM3(120).
C17 LD6 I/O LCD Data line 6. See PM3(119).
C18 LD5 I/O LCD Data line 5. See PM3(118).
C19 LD0 I/O LCD Data line 0 signal. See PM3(113).
C20 LOE I/O LCD Output Enable signal. See PM3(110).
C21 VCC —
C22 HRESET
C23 SRESET I/O, L Soft Reset signal. See PM2(80).
C24 — — Not connected.
C25 VCC —
C26 SHIFT_C I/O Shift Clock signal. See PM3(103)
C27
C28
C29 GND —
VPPIN I/O
I/O, L Hard Reset signal. See PM2(84).
Voltage Protection Input signal. The +12V input for PCMCIA flash
programming. Parallel to P7 of the MPC8xxFADS.
5-38 MPC821FADS-DB USER’S MANUAL MOTOROLA
Table 5-14. P13 Interconnect Signals (Continued)
Signal Descriptions
PIN SIGNAL INPUT/
OUTPUT
C30 HSYNC I/O Horizontal Sync signal. See PM3(106).
C31 GND —
C32 VSYNC I/O Vertical Sync signal. See PM3(107).
NOTE: I = Input, O = Output, and L = Low.
5.2 MPC821ADS DAUGHTERBOARD PART LIST
The MPC821FADS daughterboard’s bill of material is listed in Table 5-15 according to the
reference designation.
DESCRIPTION
N
O
C
I
D
U
C
T
O
R
,
I
N
C
.
M
Table 5-15. MPC821FADS Daughterboard Part List
REFERENCE
DESIGNATION
Board — — 084 00114 1
C5 C6 C7 C8 C9 C10
C11 C12 C14 C15 C16
C17 C19 C20 C22 C23
C24 C25 C28 C29 C43
R
C
H
C4 C31 C33 Capacitor 10µF, 20V, 10%,
C13 Capacitor 100µF, 10V, 10%,
A
D
E
V
I
DESCRIPTION MANUFACTURER PART NUMBER # OF
R
F
Y
Capacitor 0.1µF,16V, 10%,
B
0603, Ceramic
Size C, Tantalum
Size D, Tantalum
E
E
S
C
A
E SE
L
PARTS
SMD 021 00118 21
SMD 023 00027 3
SMD 023 00038 1
C30 C35 Capacitor 1µF, 25V, 10%,
C18 C21 Capacitor 10pF, 50V 10%, COG,
C26 Capacitor 5000pF, 50V, 10%,
C27 Capacitor 0.68µF, 20V, 10%,
D1 Diode SMD LL4004G SMD 048 LL4004G 1
H1 H2 H3 Gnd Bridge, Gold-Plated TH 022 00011 3
J1 J2 J3 Jumper Header, 3-Pole with
J1 J2 J3 — TH 009 00124 3
J4 J5 Jumper, Soldered TH 022 00011 2
L1 Inductor 8.2mHy TH 024 00020 1
LD1 Green LED SMD 048 01005 1
P1 P2 P3 P4 P5 P6 P8 Connector 38-Pin, Receptacle MICTOR SMD 009 00393 7
P7 Connector Header, 40-Pin, Dual
Size A, Tantalum
1206, Ceramic
1206, Ceramic
Size A, Tantalum
Fabricated Jumper
In-line,TSM-115-04-S-DV
SMD 023 00028 2
SMD 021 00097 2
SMD 021 00080 1
SMD 023 00041 1
TH 028 00162 3
SMD 028 00165 1
MOTOROLA MPC821FADS-DB USER’S MANUAL 5-39
Signal Descriptions
Table 5-15. MPC821FADS Daughterboard Part List (Continued)
REFERENCE
DESIGNATION
PM1 PM2 PM3 PM4 Connector Inter-Board, 7mm Height,
PX1 PX2 PX3 PX4 Connector Inter-Board 140-Pin,
R15 R17 R18 R21 22Ω SMD 006 00301 4
R45 Resistor 100Ω, 1%, 1206, 1/8W SMD 006 00240 1
R8 R9 R10 Resistor 75Ω, 5%, 1206, 1/8W SMD 006 00260 3
R11 Resistor 47KΩ, 1%, 1206, 1/8W SMD 006 00261 1
R12 Resistor 200KΩ, 5%, 1206, 1/8W SMD 006 00298 1
R13 Resistor 20MΩ, 5%, 1206, 1/8W SMD 006 00314 1
R14 R16 R19 R20
R29 R31 R32 R33 R34
R35 R48 R49
R28 R30 0 (*) not use SMD 006 00252 2
R36 Resistor 124KΩ, 5%, SMD 1206, 1/8W SMD 006 00299 1
R53 Resistor 243Ω, 1%, 1206, 1/8W SMD 006 006 00215 1
R54 Resistor 143Ω, 5%, 1206, 1/8W SMD 006 00300 1
RN1 RN2 RN3 Resistor Network 75 Ω, 5%,
RN4 Resistor Network 4.7K, 5%,
A
R
C
H
D
E
V
I
DESCRIPTION MANUFACTURER PART NUMBER # OF
PARTS
140-Pin, Plug
Receptacle
SMD 028 00392 4
SMD 009 00172 4
C
N
I
,
R
O
T
C
U
D
N
O
C
I
.
M
Resistor 0Ω, 1206, 1/8W SMD 006 00252 12
C
S
E
E
R
F
Y
B
Eight Resistors, 16-Pin
Eight Resistors, 14-Pin
A
E SE
L
SMD 051 00060 3
SMD 051 00036 1
T1S MMDF3N03HD
U1 4 MHz Clock Generator. 3.3V,
U1 Socket 14-Pin PC Socket TH 009 00135 1
U2 MPC821, 19 x 19, 357-Pin BGA TH 009 00284 1
U2 Socket 361-Pin 19 x 19 BGA ZIF Socket TH 009 00284 1
U6 74LCX08D Quad Low Voltage
U7 S-8051HN-CD-X
U8 LM317MDT
Y2 Crystal Resonator 32.768kHz, Frequency
Transistor TMOS, Dual, 3A
CMOS Levels
CMOS AND Gate
Voltage Level Detector,
1.795V to 2.005V Range,
Open-Drain Output
Variable Output Voltage Regulator
Tolerance ± 30ppm,
Drive Level 10µW Max.,
Shunt Capacitance 2pF Max.,
Load Capacitance 12.5pF Max.,
Equivalent Series Resistance 35KΩ Max.
SMD 051 MMDF3N03HD 1
TH 048 00072 1
SMD 051 74LCX08D 1
SMD 051 S-8051 1
SMD 051 LM317MD 1
SMD 048 00034 1
5-40 MPC821FADS-DB USER’S MANUAL MOTOROLA
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