MOTOROLA MPC564EVB User Guide
Freescale Semiconductor, Inc.
MPC564EVB User’s Manual
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MPC564EVBUM
Rev. 1.2, 3/2003
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Revision History
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Version
Number
1.1 11/2002 Initial Version
1.2 3/2003 Fixed typos. Added appendix describing dBUG ethernet configu-
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Date
Description of Changes
ration. Added appendix for emulating the MPC53X parts. Added
66MHz references.
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DigitalDNA and Mfax are trademarks of Motorola, Inc.
IBM PC and IBM AT are registered trademark of IBM Corp.
All other trademark names mentioned in this manual are the registered trade mark of respective owners
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No part of this manual and the dBUG software provided in Flash ROM’s/EPROM’s may be reproduced, stored in a retrieval system, or
transmitted in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise. Use of the program or any
part thereof, for any purpose other than single end user by the purchaser is prohibited.
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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must
be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent
rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in
which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or
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employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola
and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:
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or 1–800–441–2447
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© Motorola Inc., 2002. All rights reserved.
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Cautionary Notes
Axiom Manufacturing (http://www.axman.com) reserves the right to make changes without
further notice to any products to improve reliability, function or design. Axiom does not
assume any liability arising out of the application or use of any product or circuit described
herein; neither does it convey any license under patent rights or the rights of others. Axiom
products are not designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which failure of the Axiom product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Axiom
manufacturing products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Axiom Manufacturing and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Axiom
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Manufacturing was negligent regarding the design or manufacture of the part or system.
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EMC Information on MPC564EVB
1. This product as shipped from the factory with associated power supplies and cables,
has been tested and meets with requirements of EN5022 and EN 50082-1: 1998 as a
CLASS A product.
2. This product is designed and intended for use as a development platform for hardware or software in an educational or professional laboratory.
3. In a domestic environment this product may cause radio interference in which case
the user may be required to take adequate measures.
4. Anti-static precautions must be adhered to when using this product.
5. Attaching additional cables or wiring to this product or modifying the products operation from the factory default as shipped may effect its performance and also cause
interference with other apparatus in the immediate vicinity. If such interference is
detected, suitable mitigating measures should be taken.
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WARNING
This board generates, uses, and can radiate radio frequency energy and, if not installed
properly, may cause interference to radio communications. As temporarily permitted by
regulation, it has not been tested for compliance with the limits for class a computing devices
pursuant to Subpart J of Part 15 of FCC rules, which are designed to provide reasonable
protection against such interference. Operation of this product in a residential area is likely
to cause interference, in which case the user, at his/her own expense, will be required to
correct the interference.
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Contents
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Paragraph
Number Title
Chapter 1
MPC564 EVB Board
1.1 Processor.............................................................................................................. 1-3
1.2 System Memory................................................................................................... 1-4
1.2.1 External Flash.................................................................................................. 1-4
1.2.2 SRAM.............................................................................................................. 1-5
1.2.3 Internal SRAM................................................................................................. 1-5
1.2.4 Internal Flash ...................................................................................................1-5
1.2.5 MPC564EVB Memory Map............................................................................ 1-5
1.2.5.1 Memory Device / Bank Selection and Configuration.................................. 1-6
1.2.5.2 Memory Bank Chip Select Configuration................................................... 1-7
1.2.5.3 Reset Vector Mapping..................................................................................1-7
1.3 Support Logic ...................................................................................................... 1-8
1.3.1 Reset Logic...................................................................................................... 1-8
1.3.2 Clock Circuitry ................................................................................................1-8
1.3.3 Watchdog Timer...............................................................................................1-8
1.3.4 Exception Sources............................................................................................ 1-9
1.3.5 TA Generation.................................................................................................. 1-9
1.3.6 User’s Program................................................................................................ 1-9
1.3.7 Power Oak K/I/S Hardware Options ............................................................. 1-10
1.4 Communication Ports ........................................................................................ 1-11
1.4.1 COM1 and COM2 ......................................................................................... 1-11
1.4.2 CAN PORTs and Options ..............................................................................1-12
1.4.3 10/100T Ethernet Port.................................................................................... 1-14
1.4.4 BDM and NEXUS Development Ports .........................................................1-15
1.4.4.1 BDM Port Options..................................................................................... 1-15
1.4.4.2 Nexus Connector ....................................................................................... 1-16
1.5 Connectors and User Components..................................................................... 1-19
1.5.1 Keypad...........................................................................................................1-19
1.5.2 LCD Port........................................................................................................ 1-19
1.5.3 User Components........................................................................................... 1-21
1.5.4 MPC564EVB Hardware Options................................................................... 1-21
1.5.5 Signals Available on Board............................................................................ 1-22
1.5.5.1 IRQ PORT ................................................................................................. 1-22
1.5.5.2 BUS_PORT................................................................................................ 1-22
1.5.5.3 TPU_PORTs .............................................................................................. 1-23
1.5.5.4 CONTROL_PORT .................................................................................... 1-24
1.5.5.5 MIOS_PORT .............................................................................................1-25
1.5.5.6 QADC_PORTs........................................................................................... 1-26
1.5.5.7 QSM_PORT............................................................................................... 1-27
1.5.5.8 MICTOR 1 – 3 PORTs...............................................................................1-27
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Contents
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Paragraph
Number Title
1.6 Reference Documents........................................................................................ 1-28
1.7 Software Development ...................................................................................... 1-28
Chapter 2 Initialization and Setup
2.1 System Configuration .......................................................................................... 2-1
2.2 Installation And Setup ......................................................................................... 2-3
2.2.1 Unpacking........................................................................................................ 2-3
2.2.2 Preparing the Board for Use ............................................................................2-3
2.2.3 Providing Power to the Board.......................................................................... 2-3
2.2.4 Selecting Terminal Baud Rate .........................................................................2-5
2.2.5 The Terminal Character Format.......................................................................2-5
2.2.6 Connecting the Terminal.................................................................................. 2-5
2.2.7 Using a Personal Computer as a Terminal....................................................... 2-5
2.3 MPC564EVB Jumper and Switch Setup............................................................. 2-6
2.3.1 Reset Configuration Word and Configuration Switch (CONFIG_SW) ..........2-8
2.3.2 Memory Configuration (MAP_SW).............................................................. 2-10
2.4 System Power-up and Initial Operation............................................................. 2-10
Chapter 3
Using the Monitor/Debug Firmware
3.1 What Is dBUG?.................................................................................................... 3-1
3.2 Operational Procedure .........................................................................................3-2
3.2.1 System Power-up............................................................................................. 3-2
3.2.2 System Initialization........................................................................................ 3-4
3.2.2.1 Hard RESET Button.................................................................................... 3-5
3.2.2.2 Non-Maskable Interrupt Button................................................................... 3-5
3.2.2.3 Software Reset Command. ..........................................................................3-5
3.3 Command Line Usage ......................................................................................... 3-6
3.4 Commands ........................................................................................................... 3-6
3.5 System Call Functions....................................................................................... 3-39
3.5.1 OUT_CHAR.................................................................................................. 3-39
3.5.2 IN_CHAR...................................................................................................... 3-39
3.5.3 IN_STAT........................................................................................................ 3-40
3.5.4 ISR_REGISTER............................................................................................ 3-40
3.5.5 ISR_REMOVE ..............................................................................................3-40
3.5.6 EXIT_TO_dBUG........................................................................................... 3-41
Page
Number
Appendix A
MPC533/534 Emulation
ii MPC564EVB User’s Manual MOTOROLA
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Contents
Paragraph
Number Title
Appendix B
Configuring dBUG for Network Downloads
B.1 Required Network Parameters.............................................................................B-1
B.2 Configuring dBUG Network Parameters.............................................................B-1
B.3 Troubleshooting Network Problems....................................................................B-2
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MOTOROLA MPC564EVB User’s Manual iii
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Contents
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iv MPC564EVB User’s Manual MOTOROLA
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Chapter 1
MPC564 EVB Board
The MPC564EVB is an MPC564-based evaluation board that can be used for the development and
test of microcontroller systems1 (see Figure 1-1). The MPC564 is a member of the Motorola
MPC500 RISC microcontroller family. It is a 32-bit processor with a 32-bit internal address bus
and 32 lines of data.
The evaluation board is a development and test platform for software and hardware for the
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MPC5641. The system provides for development of target applications for the similar MPC561,
MPC562, or MPC563 microcontrollers also. It can be used by software and hardware developers
to test programs, tools, or circuits without having to develop a complete microcontroller system
themselves. All special features of the MPC5641 are supported.
The heart of the evaluation board is the MPC564. The MPC564EVB has 512Kbyte (128K x 32)
external SRAM for development or application memory, 2Mbyte (512K x 32) external Flash
memory, and numerous hardware expansion possibilities. The MPC564EVB board also provides
an Ethernet interface (10/100BaseT), T ouCAN, and RS232 interface in addition to the built-in I/O
functions of the MPC564
cessor. To support development and test, the evaluation board can be connected to debuggers and
emulators produced by different manufacturers.
The MPC564EVB provides for low cost software testing with the use of a ROM resident debug
monitor, dBUG, programmed into the external Flash device. Operation allows the user to load
code in the on-board RAM, execute applications, set breakpoints, and display or modify registers
or memory. After software is operational, the user may program the MPC564 Internal Flash
EEPROM or the on-board FLASH memory for dedicated operation of new software application.
No additional hardware or software is required for basic operation. For high level debug, extensive third-party tools are available for the MPC500 series. The Nexus and BDM debug ports are
available to connect the tool sets.
1
device for programming and evaluating the attributes of the micropro-
Specifications
1
Clock: 66 MHz Maximum
Operating temperature: 0°C to +70°C
Power requirement: 6 – 26V DC @ 300 ma Typical
Power output: 5.8V @ 1.5A output with 5V, 3.3V, and 2.6V regulated supplies
Board Size: 7.00 x 7.60 inches, 8 layers
1
The MPC564EVB can be used to emulate the MPC533 and MPC534. See Appendix A and MPC564CZP66
Electrical Spec for limitations.
, 4Mhz reference
Chapter 1. MPC564 EVB Board 1-1
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•Memory Devices:
512K Byte (128K x 32) Sync. SRAM, optional additional 512K Byte
2M Byte (512K x 32) Sync. FLASH
512K Byte FLASH internal to MPC564 device
32K Byte SRAM internal to MPC564 device
•POWER OAK (PC33394 P2.6) regulated power supply for 5V, 3.3V and 2.6V supplies.
•MAP Switch – provides easy assignment of chip selects and memory mapping.
•CONFIG Switch – Basic necessary Reset Word Configuration options.
•COM1 - SCIA1 with RS232 type DB9-S Connection
•COM2 - SCIA2 with RS232 type DB9-S Connection, TX / RX polarity option.
•CAN Ports
•10/100T Ethernet Port – LAN91C111 based MAC+PHY, memory mapped.
•DEVELOPMENT Ports – Nexus 50 pin and dual voltage BDM Port.
•LCD Port - LCD Module Interface Connector w/ Contrast Adjust, Buffered and Memory
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Mapped
•KEYPAD Port
•BUS Port – 32 data and 24 address lines on 60 pin header.
•CONTROL Port - Bus Controls with 40 pin header.
•QSM Port – Serial I/O port with 16 pin socket header.
•MIOS Port - MDA, PWM, and MGPIO ports with 34 pin socket header.
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– 3 CAN transceiver interfaced ports, 1 x 4 headers.
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- 16 Key passive interface, applies QADC_B channels for operation.
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•TPU Ports1 - 2 Timing Processor I/O ports with 20 pin socket headers.
•QADC Ports1 - 2 Analog I/O ports, one 20 pin and one 24 pin socket header.
•IRQ Port – Interrupt or MPC564 port I/O with 10 pin socket header.
•POWER Port – Primary and standby power supply access port, no header.
•I/O Connecto rs in .1 g rid, pin headers for bus and control provide easy ribbon cable connection
for external connections. Socket headers provide easy wire connection to breadboard prototype
area with 22ga solid wire.
•Large Prototyping Area with +5V and ground connection grids.
•Mictor Logic Probe connectors for the Address and Data bus (Not installed default)
•Breadboard Prototyping area (2.5 x 1.5 inch) for easy installation of test connections.
•System Indicators – Reset Indicator, Supply voltage indications for 5V, 3.3V, and 2.6V supplies
•Reset Switches – POReset, Hard, Soft reset buttons.
•User Components – 4 user LEDs (one with debounce), 4 user Switches, 1 user Potentiometer
with socket header for I/O connection.
1
The MPC533/4 has limited or no functionality for this module. See Appendix A
1-2 MPC564EVB User’s Manual
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Processor
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Figure 1-1. M PC 564EVB top view
1.1 Processor
The microprocessor used on the MPC564EVB is the highly integrated Motorola PowerPC
MPC564 32-bit microcontroller . The MPC564 i mplements a PPC ISA core with 512KByte UC3F
flash, two UART channels, two Timing Processor Units (TPUs)1, 32 KBytes of SRAM, a QSPI
(Queued Serial Peripheral Interface) module, three TouCAN modules
submodules in the MIOS, enhanced QADC64E, PPM module
8KByte DPTRAM1. This processor communicates with external devices over a 32-bit wide data
bus, D[0:31]. The MPC564 can address a 32 bit address range. Only 24 bits are available on the
bus however . There are inte rnally generated chip sele cts to allow the full 3 2 bit address range to be
selected. There are regions that can be decoded to allow superviser, user , instruction, and data each
to have the 32-bit address range. All the processor’s signals are available through the expansion
connector (BUS_PORT). Refer to the schematic for their pin assignments.
The MPC564 processor has the capability to support both an IEEE-ISTO 5001-1999 NEXUS port
and a BDM debug port. These ports are multiplexed and can be used with third party tools to allow
the user to download code to the board. The board is configured to boot up in the normal/BDM
mode of operation. The BDM signals are available at the port labeled BDM_PORT. The NEXUS
connector is near the reset switches on the board. It is the 2002 50 pin standard I/O connections and
connector. The BDM and NEXUS ports can not be used at the same time.
1
, a Nexus debug interface port, and
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, 12 PWMs and 6 counter
1
The MPC533/4 has limited or no functionality for this module. See Appendix A.
MPC564EVB User’s Manual 1-3
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System Memory
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Figure 1-2 shows the MPC564 block diagram.
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JTAG
Burst
Buffer
Controller 2
DECRAM
(2Kbytes)
MPC500
Core
+
FPU
32K CALRAM
28 Kbytes
4-Kbyte Overlay
QADC64E
TPU3
QADC64E
8-Kbyte
DPTRAM
Figure 1-2. MPC564
1.2 System Memory
L-BUS
TPU3
512 Kbytes
Nexus
QSMCM
Flash*
U-BUS
L2U
PPM
Tou
CAN
1
Tou
CAN
Block Diagram
UIMB
Tou
CAN
USIU
MIOS14
IMB3
E-BUS
1.2.1 External Flash
One on-board Flash ROM (U4) is used in the system. The Am29BDD160G device contains
16Mbits of non-volatile storage (1 M x 16-bit/512 K x 32-bit) giving a total of 2MBytes of Flash
memory. This device requires a 32 bit wide port and must be written in 32 bit word size data. It
may be read in bytes, half words, or words. W ait states are required to access in asynchronous mode
and the same wait state delay is required during the first cycle of a burst type access. Refer to the
specific device data sheet for configuring the flash memory. User should note that the debug
monitor firmware is installed in this flash device. Development tools or user application programs
1
See Appendix A for block diagram of MPC533/4
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may erase or corrupt the debug monitor. If the debug monitor becomes corrupted and it’s operation
is desired, the firmware must be programmed into the flash by applying a development port tool
such as BDM or Nexus. User should use caution to avoid this situation. The upper 1 MByte is used
to store the MPC564EVB dBUG debugger/monitor firmware (0x0090_0000 to 0x009F_FFFF).
System Memory
1.2.2 SRAM
The MPC564EVB has one 512 KByte device on the board (U2). It’s starting address is
0xFFF0_0000.
The synchronous SRAM Memory Bank is composed of one (optional 2) 128K x 32 memory
devices. These memory devices are connected in linear order from U2 to U3 if more than one is
available, so that the low order address of the memory bank will access U2 and the high order
addresses of the memory bank will access U3. This memory bank must be configured as a 32 bit
wide port but is byte, half word, and word accessible for read or write operations.
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Also see Section 1.2.5, “MPC564EVB Memory Map”.
1.2.3 Internal SRAM
The MPC564 processor has 32-KBtyes of internal memory which may be used as data or
instruction memory . This memory is mapped to 0x003F_8000 and configured as data space but is
not used by the dBUG monitor except during system initialization. After system initialization is
complete, the internal memory is availabl e to the user . The memory is relocatabl e to any 32-KByte
boundary.
1.2.4 Internal Flash
The MPC564 has a U-bus CDR3 flash EEPROM module (UC3F). The primary function of the
UC3F flash EEPROM module is to serve as electrically programmable and erasable non-volitle
memory (NVM) to store program instructions and/or data. The MPC564 flash EEPROM array has
512 Kbytes of NVM that is divided into eight 64-Kbyte array blocks. If the flash array is disabled
in the IMMR register (FLEN=0), then neither the UC3F array or the UC3F control registers are
accessible. This feature allows the MPC564 to emulate the MPC561/562.
Please refer to the MPC564 User’s Manual for more details.
NOTE:
The internal flash can not be programmed at 66MHz. Please see the
MPC564CZP66 Electrical Spec for other limitations at 66MHz.
1.2.5 MPC564EVB Memory Map
Interface signals to support interface to external memory and peripheral devices are generated by
the memory controller. It supports four regions on four chip-select pins. The general purpose
chip-selects are available on lines CS[0] through CS[3]. CS[0] also functions as the global (boot)
chip-select for booting out of external flash.
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System Memory
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Since the MPC564 chip selects are fully programmable, the memory banks can be located at any
location in the MPC5xx memory space.
Following is the default memory map for this board as configured by the Debug Monitor located
in the external flash bank. The internal memory space of the MPC564 is detailed further in the
MPC561/3 Users Manual. Chip Selects 0-3 can be changed by user software to map the external
memory in different locations but the chip select configuration such as wait states and transfer
acknowledge for each memory type should be maintained.
Possible Chip Select usage:
Synchronous SRAM Memory Bank CS0 or CS1 default CS1, MAP SW. 1,2
Synchronous FLASH Memory Bank CS0 or CS2 default CS0, MAP SW. 3,4
10/100T / LCD Port CS3 default CS3, MAP SW. 6,7
MPC564 Internal Flash N/A MAP_SW. 8, may effect mem-
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ory map of chip selects
The MPC564EVB Default Memory Map shows the MPC564EVB memory map.
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Table 1-1. The MPC564EVB Default Memory Map
Address Range Signal and Device
0x0000_0000 - 0x0007_FFFF 512KByte UC3F Flash
0x0008_0000 - 0x002F_7FFF Reserved for Flash
0x002F_8000 - 0x002F_87FF BBC DECRAM 2 KBytes
0x002F_8800 - 0x002F_9FFF Reserved for BBC
0x002F_A000 - 0x002F_BFFF BBC Control
0x002F_C000 - 0x002F_FFFF USIU & Flash Control
0x0030_0000 - 0x0030_7FFF UIMB I/F & IMB Modules 32KBytes
0x0030_8000 - 0x0037_FFFF Reserved for IMB
0x0038_0000 - 0x0038_007F CALRAM/READI Control
0x0038_0080 - 0x0038_3FFF Reserved (L-bus Control)
0x0038_4000 - 0x003F_7FFF Reserved (L-bus Memory)
0x003F_8000 - 0x003F_FFFF CALRAM (internal SRAM)
0x0080_0000 - 0x00A0_0000 External Flash 2MByte (0x0090_0000 -
0x00A0_0000 reserved for dBUG)
0x0100_0000 - 0x0108_0000 Ethernet
0xFFF0_0000 - 0xFFF8_0000 External SRAM 512KByte
1.2.5.1 Memory Device / Bank S electio n and C onfigur ation.
The MPC564EVB board has two internal memory banks, two external memory banks and a
Peripheral memory bank that provide:
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x 32KByte Internal SRAM
MPC564 512K byte Internal FLASH Memory (U1)
x
x 128K x 32bit (512KByte) Synchronous Static RAM (U2), 1M Byte with U3 option.
x 512K x 32bit (2MByte) Synchronous Flash EEPROM (U4)
x Peripherals 10/100T Ethernet and LCD Port
System Memory
Each external RAM or Flash memory bank can be configured individually to operate from the
MPC564 chip selects. Caution should be used not to place more than one memory bank on the CS0
chip select and to properly configure the chip select to control the memory devices provided in the
memory bank correctly. Failur e to observe precautions may r ender the external memory bus
inoperable.
The MAP Switch (MAP_SW) connects MPC564 chip selects to the different external memory
banks. If memory access problems occur, the settings of these options and the associated chip
select configurations should be reviewed with some detail. Information to configure the chip
selects and memory is detailed in the following section.
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1.2.5.2 Memory Bank Chi p Selec t Confi guration
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Application software that executes on Reset must configure each memory bank chip select
properly for correct operation. Chip Select Memory Options shows the default memory settings
programmed by the dBUG ROM monitor and may be applied for most user applications:
Table 1-2. Chip Select Memory Options
Memory Bank Reg. Default Value Notes
CS1 = SRAM BR1 0xFFF0_0003 Base Address = 0xFFF0_0 000 , Port wi d th = 32 bit *Default
CS1 = SRAM, asynchr o-
nous access mode
CS0 = FLASH BR0 0x0080_0003 Base address 0x0080_0000, Port width = 32 bit *Default
CS0 = FLASH, asynchro-
nous access mode
CS3 = Peripheral BR3 0x0100_0807 Base address = 0x0100_0000, Po rt w id t h = 16 bit *Default
OR1 0xFFF0_0000 Memory Range = 0xFFF0_0 000 > 0xFFF7_ FFFF, wait state
= 0. Note U2 = 512K bytes and will mirror 4x with this setting. Usable range = 0xFFF0_8000 – 0xFFF7_FFFF.
OR0 0xFFE0_0030 Memory range = 0x0080_0000 > 0x009F_FFFF, wait state
= 3, asynchronous operation 40Mhz clock, 95ns device.
Note U4 = 2M bytes and will mirror 2x with this setting.
Usable range = 0x00 80_ 0000 > 0x008F_FFFF (dBUG m on itor is in upper half starting at 0x00 90_ 0000)
External TA* generation provided.
CS3 = Peripheral, asynchronous
OR3 0xFFFF_80F0 Memory Range 0x0100_0000 > 0100_7FFF, wait state =
External Terminate (T A*) *Default Note Peripher al mem ory
map.
1.2.5.3 Reset Vector Mapping
After reset, the processor attempts to execute at physical address 0x0000_0100 if the hard reset
configuration word IP bit is cleared to 0 or physical address 0xFFF0_0100 if the hard reset
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Support Logic
configuration word IP bit is set to 1. This requires the board to have a non-volatile memory device
in this range with the correct information stored in it. The MPC564 processor chip-select zero
(CS0
) responds to any accesses after reset until the OR0 is written. Since CS0 (the global chip
select) is connected to the Flash ROM (U6), the Flash ROM initially appears at address
0xFFF0_0000. The initialization routine then programs the chip-select logic, locates the Flash
ROM to start at 0x0080_0000 and configures the rest of the internal and external peripherals.
Please refer to the MPC561/563 user’s manual (Global (Boot) Chip-Select Operation) for more
information.
1.3 Support Logic
1.3.1 Reset Logic
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The reset logic provides system initialization. Reset occurs during power-on or via assertion of the
signal RESET which causes the MPC564 to reset. HRESET is triggered by the reset switch (SW1)
which resets the entire processor/system.
dBUG configures the MPC564 microprocessor internal resources during initialization. The
contents of the exception table are copied to address 0xFFF0_0000 in the SDRAM. The Software
W atchdog Timer is disabled, the Bus Monitor is enabled, and the internal timers are placed in a stop
condition. A memory map for the entire board can be seen in Table 1-1., “The MPC564EVB
Default Memory Map”.
RW0 – 30: External Reset Configuration Word (RCW) Options
R W0, RW2, RW4 – 18, RW23 – 30 provide the user access to external Reset Configuration Word
(RCW) bits not normally required for default MPC564EVB operation. The RW0 – 30 designations
reflect the data bus D0 – D30 bit effected when the RCW word is enabled externally. All RW0 –
30 option bits are defaulted to the logic low value during external RCW word operation. The user
may apply a wire jumper between the 2 pad positions of each RW0 – 30 option to provide a logic
high level on the respective bit position during external RCW operation. Refer to the MPC564 user
manual Reset chapter for the respective RCW bit definitions.
1.3.2 Clock Circuitry
The MPC564EVB board uses a 4MHz crystal (Y1 on the schematics) to provide the clock to the
on-chip oscillator of the MPC564. In addition to the 4MHz crystal, there is also a 25MHz oscillator
(Y3) which feeds the Ethernet chip (U20).
1.3.3 Watchdog Timer
The duration of the Watchdog is selected by the SWT[1:0] bits in the System Protection and
Control Register (SYPCR), SWT[1:0] = 0b11 gives a maximum timeout period of 228/System
frequency. The dBUG monitor initializes these bits with the value 0b11, which provides the
maximum time-out period, but dBUG does NOT enable the watchdog timer via the SYPCR
register SWE bit.
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Support Logic
1.3.4 Exception Sources
The MPC500 family of processors can receive exceptions as a result of external signals, errors,
interrupts, or unusual conditions arising in the execution of instructions. When the processor
receives an exception, information about the state of the processor is saved and, after switching to
supervisor mode, the processor begins handling the exception based on instructions in the
Exception Vector Table in memory. Exceptions are handled in program order based on PowerPC
architecture requirements. When an exception occurs that was caused by an instruction, any
unexecuted instructions that appear earlier in the instruction stream are required to complete before
the exception is taken. Exceptions no associated with a specific instruction (asynchronous
exceptions) are recognized when they occur. Exception handlers should save the information in
SRR0 and SRR1 soon after the exception is taken to prevent this information from being lost due
to another exception being taken.
The processor goes to an exception routine via the exception table. This table is stored in the Flash
EEPROM. The address of the table location is set by the IP bit (switch 5 of MAP_SWITCH). The
dBUG ROM monitor writes a copy of the exception table into the RAM starting at 0xFFF0_0000.
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To set an exception vector, the user places the address of the exception handler in the appropriate
vector in the vector table located at 0xFFF0_0000.
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The MPC564’s interrupt controller supports up to 8 external interrups (0 - 7), eight levels for all
internal USIU interrupt sources and 32 levels for internal peripheral modules. It has an enhanced
mode of operation, which simplifies the MPC564 interrupt structure and speeds up interrupt
processing.
NOTE:
No interrupt sources should have the same level and priority as
another. P rogramming two interrupt sources with the same level and
priority can result in undefined operation.
The MPC564EVB hardware uses IRQ
Interrupt) function using the ABOR T switch (SWITCH1 when BRK_EN jumper is inserted). This
switch is used to force a non-maskable interrupt if the user's program execution should be aborted
without issuing a RESET.
Refer to MPC564 User’s Manual for more information about the interrupt controller.
[0]/SGPIOC[0] to support the ABORT (Non Maskable
1.3.5 TA Generation
The TA signal is driven by the slave device from which the current transaction was addressed. It
indicates that the slave has rece ived the data on the write cycle or returned data on the read cycle.
If the transaction is a burst, TA should be asserted for each one of the transaction beats. The
MPC564 drives T A when the slave device is controlled by the on-chip memory controller or when
an external master initiated a transaction to an internal slave module. TA is used to indicate the
completion of the bus cycle. It also allows devices with different access times to communicate with
the processor properly (i.e. asynchronously) like the Ethernet controller. The internal TA generator
is used for all external memories. External TA is only used for Ethernet/LCD.
1.3.6 User’s Program
Switch 5 on the MAP_SW bank of switches allows users to test code from boot/PORESET without
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having to overwrite the ROM Monitor. The user’s code will boot from internal flash
(0x0000_0000) needs to contain the start of the Exception Vector Table).
When the switch is ON (IP is set), the behavior of the system is normal, dBUG boots and then runs
from 0x0090_0000.
Procedure:
1. Compile and link as though the code was to be placed at the base of the internal flash, but
setup so that it will download to the SRAM starting at address 0xFFF0_8000. The user
should refer to their compiler documentation for this, since it will depend upon the compiler
used.
2. Set IP bit (Switch 5 ON).
3. Download to SRAM (If using serial or ethernet, start the ROM Monitor first. If using BDM
via a wiggler cable, download first, then start ROM Monitor by pointing the program
counter (PC) to 0x0090_0100 and run.)
4. In the ROM Monitor, execute the 'upuser' command.
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5. Turn off IP bit (Switch 5 OFF). User code should now be running from reset/POR.
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1.3.7 Power Oak K/I/S Hardware Options
Several hardware options surround the Power Oak supply to allow the user access to many of the
features. The options are sorted by leading character to indicate functionality. ‘K’ designated
options refer to VKAM and MPC564 back-up supply options. ‘I’ designated options refer to
Interrupt operation options. ‘S’ designated options refer to MPC564 Reset or I/O signal connection
options. Following is the summary table (also refer to MPC564EVB schematic):
Table 1-3. K/I/S Option Table
Option
Designator
K0 VKAM KAPWR K1 Closed
K1 2.6V KAPWR K0 Open
K2 VKAM IRAMSTBY K3 Closed
K3 2.6V IRAMSTBY K2 Open
K4 VKAM VDDSYN K5 Open
K5 +2.6V VDDSYN K4 Closed
I0 WAKEUP IRQ4 Open
Power Oak Signal
MPC564 signal
Associated
1
Option
Default Connection
I1 WAKEUP IRQ0 I2 Open
I2 PRERESET IRQ0 I1 Open
S0 PORESETB PORESET Closed
S1 HRESETB HRESET Closed
S2 SLEEP RSTCONF_TEXP Open
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Option
Designator
S3 REGON MGPIO15 Open
S4 CANTXD B_CANTX0 A_CANTX0 Open
S5 CANRXD B_CANRX0 A_CANRX0 Open
S6 CS
S7 DO QSPI_MISO Closed
S8 DI QSPI_MOSI Closed
S9 VREF3 BOEPEE S10 Open
S10 VREF3 EPEE S9 Open
1
The MPC533/4 has limited or no functionality for this module. See Appendix A
Power Oak Signal
MPC564 signal
QSPI_PCS1 Closed
Associated
1
Option
Default Connection
1.4 Communication Ports
The MPC564EVB provides external interfaces for 2 SCI serial ports, 3 CAN ports and a 10/100T
ethernet port.
1.4.1 COM1 and COM2
The MPC564 processor has one queued serial multi-channel module (QSMCM) which provides
two serial communications interfaces (SCI/UAR T). These submodules communicate with the CPU
via a common slave bus interface unit (SBIU). The signals of COM1 and COM2 pass through
external Driver/Receivers to make the channels RS-232 compatible. An RS-232 serial cable with
DB9 connectors is included with the board. The signals of both channels are available on the
QSM_PORT connector. SCI0 (COM-1) is the “TERMINAL” channel used by dBUG for
communication with an external terminal/PC. The “TERMINAL” baud rate defaults to 19200.
Notes:
1. COM ports provide connection pads 1 – 9 behind the DB9 cable connectors so the user
may modify operation of the serial connection. Each connection pad is numbered for the
associated serial connector pin. Each connection pad can be isolated from the others if
grouped above, by cutting the associated trace to the pad on the bottom side of the board.
See the MPC564EVB schematic.
2. COM-2 has the JP1 DCE/DTE option, see below.
3. RS232 translators available to COM3 and COM4 that are not required by user application
may be applied to other COM ports by isolating the MPC564 SCI signals to the RS232
transceiver and applying the associated RS232 level input or output to another COM port.
User should refer to the schematic diagrams of the board to make sure correct signals and
connections are isolated and reconnected for the new application.
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Communication Ports
JP1 – COM2 DCE/DTE Option:
1
••
••
COM-2 is optioned as a DCE type RS232 connection by default (same as COM-1). This allows
direct connection to a standard 9 pin PC COM serial port.
1
••
••
COM-2 DTE option. This requires a NULL modem adapter to connect to a standard 9 pin PC
COM serial port.
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AT1/2, AR1/2 - Serial Port Configuration
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The AT1, AT2, AR1 and AR2 cut-away options provide a means of isolating the individual SCI
RXD and TXD signals from the RS232 interface translator device (U10) and COM port operation.
This allows the SCI channels to be used for other purposes, possibly on the QSM port connector.
Following is a table of the SCI signals and AT/R_ positions used for enabling RS232 and COM
port operation. Note: 2mm header maybe installed after cutaways are cut to allow jumper option.
Table 1-4. Serial Port Configuration
AT_ Position SCI Channel
Signal
AT1 SCI_A_ TXD1 COM-1 Output
AR1 SCI_A_ RXD1 COM-1 Input
AT2 SCI_A_ TXD2 COM-2 Output
AR2 SCI_A_ RXD2 COM-2 Input
1.4.2 CAN PORTs and Options
The MPC564EVB board provides 3 CAN transceivers with I/O ports: CAN_A, CAN_B, and
CAN_C. CAN_A is supported by the PC33394 Power Oak CAN transceiver. The CAN_B and
CAN_C ports are supported by Philips PCA82C250 1M Baud CAN transceivers. The MPC564
CAN_A port is directly interfaced to the Power Oak transceiver and can not be isolated easily . The
MPC564 CAN_B and C ports are interfaced to the MPC564 TOUCAN channels B and C by option
jumpers B_RX, C_TX, and C_RX.
RS232 COM Port
Connection
1
COM_PORT Signal
Direction to RS232
interface translator
CAN_A
1
The MPC533/4 has limited or no functionality for this module. See Appendix A
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The CAN_A channel transceiver is provided by the Power Oak (PC33394). This transceiver has
software selectable options via the QSPI 0 channel which may communicate with the Power Oak
device. See the PC33394 data sheet for details. A 4.7K ohm pull-up is provided on the CAN_A
TX signal. Options S4 and S5 are provided near the Power Oak device to provide both MPC564
CAN_A and CAN_B channels for messaging on the Power Oak transceiver. If S4 and S5 are
connected, the B_RX option from the CAN_B port must be open.
B_RX Option Jumper
This option jumper enables the receive connection from the CAN_B port transceiver to the
MPC564 CAN B RX channel. The option allows the isolation of the CAN_B port transceiver RX
signal so that the user may use a different connection or transceiver for the MPC564 CAN B port.
C_RX and C_TX Option Jumpers
These options enable the CAN_C port transceiver RX and TX signals to be placed on the MPC564
MGPIO port CAN C signals. The CAN C operation on the MPC564 MGPIO port must be enabled
in software, see example source code. The MPC564 MGPIO Port bits 11 and 12 are effected along
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with the MPC564EVB MIOS Port pins 30 and 31 respectfully.
B_EN and C_EN Option Pads, CN1 and CN2 Option Cut-Aways
Communication Ports
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These options provide access to the output enable and slew rate control of the respective CAN
transceiver. By default the transceivers are set to provide minimum slew rate (fast edge) and to be
constantly enabled for output. The configuration of the transceivers maybe modified for slew rate
or output control or both. Signaling CAN bus slew rate can be modified by increasing the value of
R66 and R67 for CAN_B and CAN_C respectfully. Opening the CN1 and CN2 away options for
CAN_B and CAN_C respectfully allows a MPC564 I/O port to be applied to the B_EN and C_EN
option pads to provide output control. A high level on the B_EN or C_EN would disable the
respective CAN transceiver output. See the PCA82C250 data sheet on the support CD for
additional information.
CAN_A, CAN_B, and CAN_C Port Connectors
These ports provide the CAN transceiver input and output connection to the CAN bus. No bias or
termination for the CAN bus is provided on the MPC564EVB board. If required the user must
install these components in the proto area or elsewhere on the CAN bus. Following are the pin
connections for the ports:
Pin 1 = CAN-Hi level signal
Pin 2 = CAN-Lo level signal
Pin 3 = Ground or common (this is required for proper return path on CAN bus)
Pin 4 = +5V supply for remote use or bias of CAN bus.
CAN_A, CAN_B, and CAN_C Port Termination Options
The RA1-3, RB1-3, and RC1-3 option locations provide the respective CAN A, B, or C port with
the ability to add bias and/or termination resistance. RA1, RB1, and RC1 locations provide low
bias (to ground) on the respective CAN Port CAN Hi signal. RA3, RB3, and R C3 locations provide
high bias (to +5V) on the respective CAN Port CAN Low signal. RA2, RB2, and RC2 locations
provide termination between the respective CAN Port CAN Hi and CAN Low signals.
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1.4.3 10/100T Ethernet Port
The MPC564EVB has an Ethernet controller (SMSC LAN91C11 1 U20) operating at 10M bits/sec
or 100Mbits/sec (see the device data sheet on the support CD forr operation details). The dBUG
ROM monitor is programmed to allow a user to download files over a network to memory in
different formats. The compiler-formats currently supported are S-Record, COFF, ELF, or Image
(raw binary). Refer to Appendix B, “Configuring dBUG for Network Downloads”, for details on
how to configure the board for network download.
The Ethernet registers are located at chip select CS3 base address in the address range 0x0000 0x000F . The access is 16 bits wide or half word transfers only. The LAN91C111 device applies a
register bank selection technique to provide a minimum memory space size. Users should review
the device data sheet in detail for operation notes. The debug monitor applies the Ethernet for file
downloads only, no high level stacks are applied in the sample source code.
RJ45 jack J3 of the Ethernet port provides a direct to HUB type connection. The Ethernet cable
provided with the MPC564EVB kit is a crossover type for direct connection of the EVB to a PC
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host network card. If connection to a HUB is desired, a standard Ethernet cable should be applied.
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Table 1-5. Ethernet Jack J3
PIN SIGNAL
1TX+
2TX3RX+
4 Term 1 75 ohm
5 Term 1 75 ohm
6RX7 Term 2 75 ohm
8 Term 2 75 ohm
100_IRQ Option Jumper
The 100_IRQ Option jumper provides Ethernet Interrupt capability to the MPC564 processor.
With the option installed and the LAN91C111 device properly configured, the MPC564 IRQ1
interrupt can be applied to service the port.
LINK and STAT Indicators
The LAN91C11 1 Ethernet controller provides two indication drivers under software control. The
LINK indicator is driven by the LAN91C111 LEDA output and the STA T indicator is driven by the
LEDB output.
MII Connector
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The MII connector location is for testing and the connection of an external Ethernet PHY device.
This connector is not installed or supported by the EVB application.
Communication Ports
1.4.4 BDM and NEXUS Development Ports
Both NEXUS (MPC564 Readi Module) and standard BDM (background debug module)
development ports are provided on the MPC564EVB for application of integrated software debug
tool suites. In order to use the BDM, simply connect the 10-pin debug connector on the board,
BDM_PORT, to the P&E BDM wiggler cable provided in the kit. No special setting is needed.
Refer to the MPC564 User’s Manual BDM Section for additiona instructions. The NEXUS
interface provides the IEEE-ISTO 5001 50 pin standard I/O connections and connector and the
BDM port provides the standard 10 pin interface (refer to MPC564EVB schematic sheet 3 for
details). User should observe that both ports can not be applied at the same time. Note that the
NEXUS interface applies some of the MPC564 standard I/O signals from the MIOS module as
alternate development port I/O signals. Following are the I/O effected:
MGPIO 0, 1, 2, 3, 5, 6
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MPWM 0, 1, 17, 19
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IRQ0
NOTE:
BDM functionality and use is supported via third party developer
software tools. Details may be found on CD-ROM included in this
kit
1.4.4.1 BDM Port Options
The BDM Port provides several options for flexibility of operation.
JP3 - BDM Port Interface Level
JP3 provides the option of 2.6V or 3.3V interface levels on the BDM port. This allows the use of
legacy MPC555 BDM tools on the MPC564. The option is set for 3.3V interface from the factory .
The following JP3 reference is with the MPC564EVB setting with the COM ports facing left.
JP3
i
3.3V 2.6V
The signals which are neccessary for debug are available at connector (BDM_PORT). Figure 1-3
shows the (BDM_PORT) Connector pin assignment.
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VFLS0
GND
GND
HRESET
Power
2.6 or 3.3 V
1
3
5
7
9
2
4
6
8
10
SRESET
DSCK
VFLS1
DSDI
DSO
Figure 1-3. The BDM_PORT Connector pin assignment
V1, V2, V3, and V4
The V1 – V4 options provide a way to use the alternate VFLS0 and VFLS1 BDM signals from the
MPC564. By default, the primary VFLS0 and VFLS1 signals are applied by V1 and V2 default
connections. To modify the BDM port to apply the alternate VFLS0 and VFLS1 signals, options
V1 and V2 should be cut and options V3 and V4 connected.
1.4.4.2 Nexus Connector
The 2001-Nexus standard defines several different standards for different speed accesses to a
microcontroller in a target system. These standards have been revised since that release. The new
connectors come in both a robust and a non-robust configuration. In addition, each connector has
2 definitions depending upon whether the connection is an Auxiliary only (Auxiliary In and
Auxiliary Out) connection or a JTAG IEEE 1149.1 port with an Auxiliary Output port.
NOTE
The MPC56x parts do not support the JTAG IEEE 1149.1 configuration.
Table 1-6. MPC56x Nexus 50-Pin Definition (Full-Port Mode)
MPC56x
Signal
Nexus Auxiliary
Signal
I/O
Pin
Number
Pin
Number
Nexus Auxiliary
I/O
Signal
MPC56x
Signal
— UBATT OUT 1 2 OUT UBATT —
VSTBY2.6 VSTBY OUT 3 4 IN or
OUT
— TOOL_IO1 IN or
OUT
HRESET
EVTI /EVTI IN
RSTI
MSEI
1-16 MPC564EVB User’s Manual
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1
/RSTI IN
/MSEI IN
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56IN or
OUT
2
7 8 OUT VREF VDD2.6
2
910— GND GND
2
11 12 GND GND
2
13 14 — GND GND
TOOL_IO0 —
TOOL_IO2 —
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Table 1-6. MPC56x Nexus 50-Pin Definition (Full-Port Mode) (Continued)
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MPC56x
Signal
MDI[0] MDI0 IN
MCKI MCKI IN
MDO[0] MDO0 OUT 19 20 — GND GND
MCKO MCKO OUT 21 22 — GND GND
LWP[1] /EVTO OUT 23 24 — GND GND
MSEO
MDO[1] MDO1 OUT 27 28 — GND GND
MDO[2] MDO2 OUT 29 30 — GND GND
MDO[3] MDO3 OUT 31 32 — GND GND
MDI[1] MDI1 IN
— /MSEO1 OUT 35 36 — GND GND
MDO[4] MDO4 OUT 37 38 — GND GND
MDO[5] MDO5 OUT 39 40 — GND GND
MDO[6] MDO6 OUT 41 42 — GND GND
MDO[7] MDO7 OUT 43 44 — GND GND
— MDI2 IN
— MDI3 IN
EPEE & B0EPEE
1
The Nexus specification labels active low signals with a forward slash (/) before the signal name.
2
The Nexus standard recommends that inputs should have 10K :pull-up resistors to VREF (2.6 volts).
Exception: The RSTI input should have a 10K :pull-down resistor. This is in line with the proposed new
standard.
3
This signal is needed only if control of EPEE or B0EPEE is required by the Nexus tool.
Nexus Auxiliary
Signal
/MSEO0 OUT 25 26 IN or
3
VENDOR_IO1 IN or
I/O
OUT
Pin
Number
2
15 16 — GND GND
2
17 18 — GND GND
2
33 34 — GND GND
2
45 46 — GND GND
2
47 48 — GND GND
49 50 — GND GND
Pin
Number
Nexus Auxiliary
I/O
OUT
MPC56x
Signal
VENDOR_IO0 LWP[0]
Signal
On the MPC56x devices, some of the Nexus signals are shared with other pin functions. MPC56x
Signal Sharing shows the Nexus signal versus the MPC561/562/563/564 pins.
.
Table 1-7. MPC56x Signal Sharing
MPC561/562/563/564
Nexus Signal
Signal Ball
/RESET HRESET W23
/RSTI JCOMP/RSTI
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Table 1-7. MPC56x Signal Sharing (Continued)
MPC561/562/563/564
Nexus Signal
Signal Ball
MCKI TCK/DSCK/MCKI L2
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/MSEI VF[2]/MPIO32B[2]/
MSEI
MDI0 TDI/DSDI/MDI0 M1
MDI1 MPWM0/MDI1 F26
Aux In Port
Aux Out Port
Port
MDI2 —
MDI3 —
/EVTI TMS/EVTI
MCKO VF[1]/MPIO32B[1]/
MCKO
/MSEO VFLS[0]/MPIOB32[3]/
MSEO
MDO0 TDO/DSDO/MDO[0] M4
MDO1 VF[0]/MPIO32B[0]/
MDO[1]
MDO2 MPWM[1]/MDO[2] G23
MDO3 MPWM[17]/MDO[3] H23
MDO4 IRQ[0]/SGPIO[0]/
MDO[4]
MDO5 MPIO32B[5]/MDO[5] H26
MDO6 MPIO32B[6]/
MPWM[4]/MDO[6]
MDO7 MPWM[19]/MDO[7] H25
/EVTO BG/VF[0]/LWP[1] R3
PORT0 —
VENDOR_IO0 SGPIOC[7]/IRQOUT/
LWP[0]
VENDOR_IO1 EPEE & B0EPEE
M24
1
1
1
1
2
—
—
M2
L24
M25
L23
P3
J23
—
R1
T23 & T24
Vendor Defined
TOOL_IO0 ——
TOOL_IO1 ——
TOOL_IO2 ——
Tool Defined
VREF VDD2.6 VDD
VALTREF VSTBY VSTBY2.6
1
Pin MPWM[18]/MDO[6] (H24) could also be used, but is not
enabled at reset and must be enabled via software. This is not
recommended.
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2
This signal is needed only if control of EPEE or B0EPEE is
required by the Nexus tool.
3
This should be a 2.6-volt supply and not the ISRAMSTBY current
source.
Connectors and User Components
1.5 Connectors and User Components
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1.5.1 Keypad
1
The Keypad port provides MPC564 I/O connections for a passive 16 key 4x4 matrix keypad
(Axiom HC-KP). The port is applied as 4 column drivers and 4 row inputs. The MPC564
QADC_B Ports PQA[4:7] are column outputs and PQB[4:7] are row inputs. The row inputs have
10K ohm pull-down resistance applied to idle the row inputs low. A simple keypad scan will
enable each column output high one at a time and test the input rows for a high input. Column and
row position can then determine the value of the key pressed. Sample software for driving the
Keypad Port is provided on the MPC5xx support CD.
Table 1-8. Keypad
PIN
1 QADC_B PQA4 out
2 QADC_B PQA5 out
3 QADC_B PQA6 out
4 QADC_B PQA7 out
5 QADC_B PQB4 in
6 QADC_B PQB5 in
7 QADC_B PQB6 in
8 QADC_B PQB7 in
MPC564 I/O SIGNAL
1.5.2 LCD Port
The LCD Port provides a versatile connector to attach 80 or 160 character display modules and
some graphics display modules with embedded controllers. Most LCD modules operate very
slowly compared to the MPC564 bus operation speeds so the LCD port provides a 16 bit wide
register port for access. The registered port allows writing the LCD module control signals and full
Read and Write capability for LCD module command and data bytes without the CPU waiting for
LCD access time. LCD Port access are performed as a 3 or 4 bus cycle transaction as follows:
1
The MPC533/4 has limited or no functionality for this module. See Appendix A
MPC564EVB User’s Manual 1-19
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Connectors and User Components
Access cycle 1: Write LCD control bits RS, R/W, LCD data byte. LCD1 and 2 select bits = 0.
Access cycle 2: Write LCD control bits LCD1 select, LCD2 select active as required. RS, R/W,
LCD data byte values do not change but must be written again.
Access cycle 3 = READ: Read LCD Port if a Read access type, determined by R/W = 1 in first
access cycles.
Access cycle 3 = WRITE: Write LCD control bits LCD1 select, LCD2 select idle. RS, R/W , LCD
data byte do not change but must be written again. This terminates a Write access sequence.
Access cycle 4 = READ end: W rite LCD control bits LCD1 select, LCD2 select idle, RS, R/W bits
do not change but must be written again. This terminates a Read access sequence.
Table 1-9. LCD PORT REGISTER Definition (MPC500 core register aligned)
BIT # FUNCTION
nc...
I
cale Semiconductor,
Frees
D0 LCD1 select, 80 character or first 80 characters of 160 character module select. 1 = Active
D1 LCD2 select, second 80 characters of 160 character module select. 1 = Active
D2 – D5 N/A, not applied
D6 LCD RS or Register Select. 0 = Command, 1 = Display Data access
D7 LCD Read / Write select. 0 = Write, 1 = Read access
D8 > D15 LCD Data Byte D7 > D0, Write output to LCD if D7 = 0, Read input if D7 = 1.
See LCD Module data sheet for command codes
Example source code for the LCD and Keypad drivers are provided on the Axiom MPC5xx support
CD. The LCD Port is assigned on chip select CS3 if enabled with MAP Switch position 6. Memory
map offset for the LCD Port = CS3 base + 0x0010.
LCD Display CONTRAST
The CONTRAST adjustment allows a contrast Vee voltage to be presented to the LCD_PORT of
–5V to +5V DC.
JP2 - LCD_PORT Power Polarity Select
JP2 determines the display power pin polarity on the LCD_PORT. Depending on the type and
location of the IDC connector on your display module, the power connections may need to be
reversed. Care should be used to verify proper connection and signal matching at the IDC Cable
Connector and LCD_PORT.
See the schematic to match this jumper setting to your LCD device connector. Contact
support@axman.com for assistance applying a LCD module.
Typical JP2 positions for 80 character or smaller LCD. Rotate 90 degrees for 160
character type modules.
1
1-20 MPC564EVB User’s Manual
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