MPC2002•MPC2003
1
MOTOROLA FAST SRAM
256KB and 512KB BurstRAM
Secondary Cache Module for
PowerPC – Based Systems
The MPC2002SG and MPC2003SG are designed to provide a burstable, high
performance, 256K/512K L2 cache for the PowerPC 60x processors. The modules are configured as 32K x 72 and 64K x 72 bits in a 136 pin dual readout single
inline memory module (DIMM). The module uses four of Motorola’s
MCM67M518 or MCM67M618 BiCMOS BurstRAMs.
Bursts can be initiated with either transfer start processor (TSP
) or transfer
start controller (TSC
). Subsequent burst addresses are generated internal to the
BurstRAM by the burst address advance (BAA
) pin.
Write cycles are internally self timed and are initiated by the rising edge of the
clock (K) input. Eight write enables are provided for byte write control.
The cache family is designed to interface with the PowerPC 60x bus and requires external tag.
PD0 – PD2 are reserved for density and speed identification.
• PowerPC–style Burst Counter on Board
• Dual Readout SIMM for Circuit Density
• Single 5 V ± 5% Power Supply
• All Inputs and Outputs are TTL Compatible
• Three State Outputs
• Byte Parity
• Byte Write Capability
• Fast Module Clock Rates: 66 MHz, 60 MHz, 50MHz
• Decoupling Capacitors for each Fast Static RAM
• High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes
• I/Os are 3.3 V Compatible
BurstRAM is a trademark of Motorola.
PowerPC and PowerPC 601 are trademarks of International Business Machines Corp.
Order this document
by MPC2002/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MPC2002
MPC2003
(Formerly MCM72MS32/64)
136–LEAD DIMM
CASE 1104–01
TOP VIEW
68
35
34
1
5/95
Motorola, Inc. 1995
查询MPC2002供应商
PIN ASSIGNMENT
136–LEAD DIMM
CASE 1104–01
TOP VIEW
PD0
PD1
DQ0
DQ1
V
CC
DQ4
DQ6
DQP0
DQ8
DQ10
V
SS
K0
V
SS
DQ14
V
CC
DQ16
DQ17
DQ19
DQ21
V
CC
DQP2
DQ24
DQ26
DQ28
V
SS
DQ31
DQP3
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
V
SS
PD2
V
CC
DQ2
DQ3
DQ5
DQ7
V
SS
DQ9
DQ11
DQ12
V
SS
DQ13
DQ15
DQP1
V
SS
DQ18
DQ20
DQ22
DQ23
V
SS
DQ25
DQ27
DQ29
DQ30
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
W6
DQ32
DQ33
V
SS
DQ36
DQ38
DQ39
DQ40
V
CC
DQ43
DQ45
DQ46
DQP5
V
SS
K1
V
SS
DQ52
DQ53
DQ55
DQP6
V
CC
DQ58
DQ60
DQ62
DQP7
A0
A2
A4
A6
A8
A10
A12
A14
V
SS
W7
E1
DQ34
DQ35
DQ37
V
CC
DQP4
DQ41
DQ42
DQ44
V
SS
DQ47
DQ48
DQ49
V
SS
DQ50
DQ51
DQ54
DQ56
V
SS
DQ57
DQ59
DQ61
DQ63
V
CC
A1
A3
A5
A7
NC
A9
A11
A13
A15*
W0
W2
TSP
BAA
E0
W1
W3
G0
TSC
W4
G1
W5
V
CC
V
SS
V
SS
V
SS
PIN NAMES
A0 – A15 Address Inputs. . . . . . . . . . . . . . . . . . . . . .
K0, K1 Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
W0
– W7 Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . .
E0
, E1 Module Enable. . . . . . . . . . . . . . . . . . . . . . . .
G0
, G1 Module Output Enable. . . . . . . . . . . . . . . . .
DQ0 – DQ63 Cache Data Input/Output. . . . . . . . . .
DQP0 – DQP7 Data Parity Input/Output. . . . . . . . .
TSC
Transfer Start Controller. . . . . . . . . . . . . . . . . .
TSP
Transfer Start Processor. . . . . . . . . . . . . . . . .
BAA
Burst Address Advance. . . . . . . . . . . . . . . . . .
PD0 – PD2 Presence Detect. . . . . . . . . . . . . . . . . .
V
CC
+ 5 V Power Supply. . . . . . . . . . . . . . . . . . . . . .
V
SS
Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
* This pin on the MPC2002 is a No Connect (NC)
MPC2002•MPC2003
2
MOTOROLA FAST SRAM
PD2 PD1 PD0
Cache
Size
Module
V
SS
NC NC 512KB MPC2003SG66/60
V
SS
NC V
SS
512KB MPC2003SG50
V
SS
V
SS
NC 256KB MPC2002SG66/60
V
SS
V
SS
V
SS
256KB MPC2002SG50
MPC2002•MPC2003
3
MOTOROLA FAST SRAM
MPC2003 (64K x 72) MODULE BLOCK DIAGRAM
LW
MCM67M618
A0 – A15
BAA
K
G
E
DQ0 – DQ7
A0 – A15
E0
16
K1
E1
G1
DQ8
UW
TSP
TSC
DQ9 – DQ16
DQ17
BAA
TSP
TSC
K0
G0
DQ0 – DQ7
DQP0
DQ8 – DQ15
DQP1
W0
W1
8
8
LW
MCM67M618
A0 – A15
BAA
K
G
E
DQ0 – DQ7
DQ8
UW
TSP
TSC
DQ9 – DQ16
DQ17
DQ16 – DQ23
DQP2
DQ24 – DQ31
DQP3
W2
W3
8
8
LW
MCM67M618
A0 – A15
BAA
K
G
E
DQ0 – DQ7
DQ8
UW
TSP
TSC
DQ9 – DQ16
DQ17
DQ32 – DQ39
DQP4
DQ40 – DQ47
DQP5
W4
W5
8
8
LW
MCM67M618
A0 – A15
BAA
K
G
E
DQ0 – DQ7
DQ8
UW
TSP
TSC
DQ9 – DQ16
DQ17
DQ48 – DQ55
DQP6
DQ56 – DQ63
DQP7
W6
W7
8
8
MPC2002•MPC2003
4
MOTOROLA FAST SRAM
MPC2002 (32K x 72) MODULE BLOCK DIAGRAM
LW
MCM67M518
A0 – A14
BAA
K
G
E
DQ0 – DQ7
A0 – A14
E0
15
K1
E1
G1
DQ8
UW
TSP
TSC
DQ9 – DQ16
DQ17
BAA
TSP
TSC
K0
G0
DQ0 – DQ7
DQP0
DQ8 – DQ15
DQP1
W0
W1
8
8
LW
MCM67M518
A0 – A14
BAA
K
G
E
DQ0 – DQ7
DQ8
UW
TSP
TSC
DQ9 – DQ16
DQ17
DQ16 – DQ23
DQP2
DQ24 – DQ31
DQP3
W2
W3
8
8
LW
MCM67M518
A0 – A14
BAA
K
G
E
DQ0 – DQ7
DQ8
UW
TSP
TSC
DQ9 – DQ16
DQ17
DQ32 – DQ39
DQP4
DQ40 – DQ47
DQP5
W4
W5
8
8
LW
MCM67M518
A0 – A14
BAA
K
G
E
DQ0 – DQ7
DQ8
UW
TSP
TSC
DQ9 – DQ16
DQ17
DQ48 – DQ55
DQP6
DQ56 – DQ63
DQP7
W6
W7
8
8
A15 NC
MPC2002•MPC2003
5
MOTOROLA FAST SRAM
BLOCK DIAGRAM (See Note)
EXTERNAL
ADDRESS
16
9
9
18
16
A15 – A2
DQ0 – DQ8
INTERNAL
ADDRESS
64K x 18
MEMORY
ARRAY
ADDRESS
REGISTERS
WRITE
REGISTER
ENABLE
REGISTER
DATA–IN
REGISTERS
OUTPUT
BUFFER
BAA
K
TSP
TSC
A15 – A0
UW
E
G
9
DQ9 – DQ17
99
9
LW
A0
′
A1
′
A1
LOAD
D1
BINARY
COUNTER
D0
Q1
Q0
BURST LOGIC
A0
NOTE: All registers are positive–edge triggered. The TSC or TSP signals control the duration of the burst and the start of the next
burst. When TSP
is sampled low, any ongoing burst is interrupted and a read (independent of W and TSC) is performed
using the new external address. Alternatively, a TSP
–initiated two cycle WRITE can be performed by asserting TSP and
a valid address on the first cycle, then negating both TSP
and TSC and asserting L W and/or UW with valid data on the second cycle (see Single Write Cycle in WRITE CYCLES timing diagram).
When TSC
is sampled low (and TSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on
W
) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded. After
the first cycle of the burst, BAA
controls subsequent burst cycles. When BAA is sampled low, the internal address is ad-
vanced prior to the operation. When BAA
is sampled high, the internal address is not advanced, thus inserting a wait state
into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See BURST
SEQUENCE GRAPH. Write refers to either or both byte write enables (LW
, UW).
BURST SEQUENCE GRAPH
(See Note)
1,0
1,1
0,0
0,1
A1
′
, A0′ =
NOTE: The external two values for A1 and A0
provide the starting point for the burst
sequence g raph. T he burst logic advances A1 and A0 as shown above.
MPC2002•MPC2003
6
MOTOROLA FAST SRAM
SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)
E
TSP TSC BAA LW or UW K Address Operation
H L X X X L–H N/A Deselected
H X L X X L–H N/A Deselected
L L X X X L–H External Address Read Cycle, Begin Burst
L H L X L L–H External Address Write Cycle, Begin Burst
L H L X H L–H External Address Read Cycle, Begin Burst
X H H L L L–H Next Address Write Cycle, Continue Burst
X H H L H L–H Next Address Read Cycle, Continue Burst
X H H H L L–H Current Address Write Cycle, Suspend Burst
X H H H H L–H Current Address Read Cycle, Suspend Burst
NOTES:
1. X means Don’t Care.
2. All inputs except G
must meet setup and hold times for the low–to–high transition of clock (K).
3. Wait states are inserted by suspending burst.
ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
Operation
G I/O Status
Read L Data Out (DQ0 – DQ8)
Write X High–Z — Data In
Deselected X High–Z
NOTES:
1. X means Don’t Care.
2. For a write operation following a read operation, G
must be high before the input data
required setup time and held high through the input data hold time.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V
SS
= 0 V)
Rating
Symbol Value Unit
Power Supply Voltage V
CC
– 0.5 to + 7.0 V
Voltage Relative to VSS for Any
Pin Except V
CC
Vin, V
out
– 0.5 to VCC + 0.5 V
Output Current (per I/O) I
out
± 30 mA
Power Dissipation P
D
6.0 W
Temperature Under Bias T
bias
– 10 to + 85 °C
Operating Temperature T
A
0 to +70 °C
Storage Temperature T
stg
– 55 to + 125 °C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will ensure
the output devices are in High–Z at power up.
This device contains circuitry to protect the
inputs against damage due to high static volt
MPC2002•MPC2003
7
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
(Voltages referenced to VSS = 0 V)
Parameter
Symbol Min Max Unit
Supply Voltage (Operating Voltage Range) V
CC
4.75 5.25 V
Input High Voltage V
IH
2.2 VCC + 0.3
**
V
Input Low Voltage V
IL
– 0.5* 0.8 V
*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20.0 ns) for I ≤ 20.0 mA.
**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20.0 ns) for I ≤ 20.0 mA.
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter Symbol Min Max Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC) I
lkg(I)
— ± 1.0 µA
Output Leakage Current (G = VIH) I
lkg(O)
— ± 1.0 µA
AC Supply Current (G = VIH, E = VIL, I
out
= 0 mA, All Inputs = VIL or VIH,
VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ t
KHKH
min)
I
CCA66
I
CCA60
I
CCA50
— 1160
1100
1000
mA
AC Standby Current (E = VIH, I
out
= 0 mA, All Inputs = VIL and V
IH,
VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ t
KHKH
min)
I
SB1
— 300 mA
Output Low Voltage (IOL = + 8.0 mA) V
OL
— 0.4 V
Output High Voltage (IOH = – 4.0 mA) V
OH
2.4 3.3 V
NOTE: Good decoupling of the local power supply should always be used. DC characteristics are guaranteed for all possible PowerPC bus cycles.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T
A
= 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol Typ Max Unit
Input Capacitance (A0 – A15, TSP, TSC, BAA) C
in
25 32 pF
Input/Output Capacitance (DQ0 – DQ63, DQP0 – DQP7) C
I/O
8 10 pF
Input Capacitance (Kx, Gx, Ex, Wx) C
in
12 15 pF
MPC2002•MPC2003
8
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 5% TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .
Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time 3 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Timing Reference Level 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .
Output Load See Figure 1A Unless Otherwise Noted. . . . . . . . . . . .
READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3) (W refers to either or both byte write enables)
MPC2002SG66/
MPC2003SG66
MPC2002SG60/
MPC2003SG60
MPC2002SG50/
MPC2003SG50
Parameter Symbol Min Max Min Max Min Max Unit Notes
Cycle Time t
KHKH
15 — 16.6 — 20 — ns
Clock Access Time t
KHQV
— 9 — 11 — 14 ns 4
Output Enable to Output Valid t
GLQV
— 5 — 5 — 6 ns
Clock High to Output Active t
KHQX1
6 — 6 — 6 — ns
Clock High to Output Change t
KHQX2
3 — 3 — 3 — ns
Output Enable to Output
Active
t
GLQX
0 — 0 — 0 — ns
Output Disable to Q High–Z t
GHQZ
2 6 2 6 2 6 ns 5
Clock High to Q High–Z t
KHQZ
— 6 — 6 — 6 ns 5
Clock High Pulse Width t
KHKL
5 — 5 — 6 — ns
Clock Low Pulse Width t
KLKH
5 — 5 — 6 — ns
Setup Times: Address
Address Status
Data In
Write
Address Advance
Chip Select
t
AVKH
t
TSVKH
t
DVKH
t
WVKH
t
BAVKH
t
EVKH
2.5 — 2.5 — 2.5 — ns 6
Hold Times: Address
Address Status
Data In
Write
Address Advance
Chip Select
t
KHAX
t
KHTSX
t
KHDX
t
KHWX
t
KHBAX
t
KHEX
0.5 — 0.5 — 0.5 — ns 6
NOTES:
1. A read cycle is defined by UW
and LW high or TSP low for the setup and hold times. A write cycle is defined by LW or UW low and TSP high
for the setup and hold times.
2. All read and write cycle timings are referenced from K or G
.
3. G
is a don’t care when UW or LW is sampled low.
4. Maximum access times are guaranteed for all possible PowerPC 60x external bus cycles.
5. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B. This parameter is sampled and not 100% tested. At any
given voltage and temperature, t
KHQZ
max is less than t
KHQX1
min for a given device and from device to device.
6. This is a synchronous device. All addresses must meet the specified setup and hold times for
ALL
rising edges of clock (K) whenever TSP
or TSC are low and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for
ALL
rising edges of
K when the chip is selected.Chip enable must be valid at each rising edge of clock for the device (when TSP
or TSC is low) to remain enabled.
AC TEST LOADS
Figure 1A Figure 1B
5 pF
+ 5 V
OUTPUT
480
Ω
255
Ω
OUTPUT
Z0 = 50
Ω
RL = 50
Ω
VL = 1.5 V
MPC2002•MPC2003
9
MOTOROLA FAST SRAM
Q(A2 + 2)Q(A2 + 1)Q(A2)Q(A2 + 3)Q(A2 + 2)Q(A2 + 1)Q(A2)Q(A1)
BURST READ
(BAA SUSPENDS BURST)
(BURST WRAPS AROUND
TO ITS INITIAL STATE)
SINGLE READ
TSC
t
KHQZ
t
KHQV
t
KHQX2
t
GHQZ
t
GLQX
t
GLQV
t
KHQV
t
KHBAX
t
BAVKH
t
KHEX
t
EVKH
t
KHWX
t
WVKH
t
KHTSX
t
TSVKH
t
KHAX
t
AVKH
t
KLKH
t
KHKL
t
TSVKH
t
KHKH
t
KHTSX
DATA OUT
G
E
K
TSP
ADDRESS
LW, UW
NOTE: Q(A2) represents the first output data from the base address A2; Q(A2 + 1) represents the next output data in the burst sequence with A2 as the base address.
A1 A2
BAA
READ CYCLES
MPC2002•MPC2003
10
MOTOROLA FAST SRAM
W IS IGNORED FOR FIRST CYCLE WHEN TSP INITIATES BURST
NEW BURST WRITEBURST WRITE
BAA SUSPENDS BURST
t
KHDX
t
DVKH
t
KHBAX
t
BAVKH
t
KHWX
t
WVKH
TSC STARTS NEW BURST
A3
t
KHSX
t
TSVKH
t
KHKH
t
KHKL
t
KLKH
t
KHTSX
t
TSVKH
t
KHAX
t
AVKH
t
KHEX
t
EVKH
SINGLE WRITEBURST READ
t
GHQZ
K
TSP
TSC
A
BAA
G
D
Q
WRITE CYCLES
A1 A2
E
LW, UW
Q(An – 1)
Q(An)
D(A3 + 2)D(A3 + 1)D(A3)D(A2 + 3)D(A2 + 2)D(A2 + 1)D(A2) D(A2 + 1)D(A1)
(WITH A SUSPENDED CYCLE)
MPC2002•MPC2003
11
MOTOROLA FAST SRAM
COMBINATION READ/WRITE CYCLE (E
low, TSC high)
K
TSP
ADDRESS
LW
, UW
BAA
G
DATA IN
DATA OUT
READ WRITE BURST READ
t
KHKH
t
TSVKH
t
KHTSX
t
KHKL
t
KLKH
A1 A2 A3
t
AVKH
t
KHAX
t
WVKH
t
KHWX
t
BAVKH
t
KHBAX
t
KHQV
t
KHQX1
t
GHQZ
t
DVKH
t
KHDX
t
GLQX
t
KHQX2
D(A2)
Q(A1)
Q(A3) Q(A3 + 1) Q(A3 + 2)
t
GLQV
MPC2002•MPC2003
12
MOTOROLA FAST SRAM
APPLICATION EXAMPLE
512K Byte Burstable, Secondary Cache
Using MPC2003SG66 with a 66 MHz MPC601 PowerPC
DATA
ADDRESS
(PowerPC
)
BCLK
TS
CONTROL
CACHE
CONTROL
LOGIC
BAA
TSP
K0
TSC
Wx
G0
DATA BUS
ADDRESS BUS
MCM67M618FN9
MPC601
CLOCK
ADDR ADDR DATA
K
Figure 2
MPC2003SG66
K1
G1
ORDERING INFORMATION
(Order by Full Part Number)
Motorola Memory Prefix
Part Number Package (SG = Gold Pad SIMM)
Speed (66 = 66 MHz, 60 = 60 MHz,
50 = 50 MHz)
MCM
MPC2002
MPC2003
XX XX
Full Part Numbers — MPC2002SG66 MPC2002SG60 MPC2002SG50
MPC2003SG66 MPC2003SG60 MPC2003SG50
MPC2002•MPC2003
13
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
136–LEAD DIMM
CASE 1104–01
X0.006 (0.15) T Y
L
0.012 (0.30)
M
COMPONENT AREA
VIEW AA
FRONT VIEW
136X K
2X Q
DIMAMIN MAX MIN MAX
MILLIMETERS
4.045 4.055 102.74 103.00
INCHES
B 0.995 1.005 25.27 25.53
C ––– 0.413 ––– 10.50
D 0.040 0.042 1.02 1.07
F 0.125 BSC
0.064
–––
3.18 BSC
G
––– 0.010 0.25H
J 0.046 0.054 1.17 1.37
K 0.100 ––– 2.54 –––
LM1.650 BSC 41.91 BSC
N 0.400 BSC 10.16 BSC
P 0.125 ––– 3.18 –––
Q 0.123 0.127 3.12 3.22
R 0.245 0.255 6.22 6.48
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. CARD THICKNESS APPLIES ACROSS TABS AND
INCLUDES PLATING AND/OR METALLIZATION.
4. DIMENSIONS C AND S DEFINE A DOUBLE–SIDED
MODULE.
5. DIMENSION V DEFINES OPTIONAL
SINGLE–SIDED MODULE.
6. STRAIGHTNESS CALLOUT APPLIES TO TAB
AREA ONLY.
T
–––
3.784 BSC
W
0.050 BSC 1.27 BSC
U
V
Y
0.060 0.064 1.52 1.63
0.075 0.085 1.91 2.16
0.060 1.52 1.63
0.157 ––– 4.00 –––
––– 0.236 ––– 6.00
1.57 –––0.062
96.11 BSC
COMPONENT AREA
BACK VIEW
U
F
X0.006 (0.15) T Y
S
A
M
2X
N2X
2X
L
R
Y
B
-Y-
-X-
VIEW AA
1
34
35
68
69
102
103
136
SIDE VIEW
-T-
2X W
2X W
R
M
136X H
136X D
M
X0.004 (0.10) T Y
SL
G132X
C
NOTE 4
S
NOTE 4
V
NOTE 5
P
J
R T
NOTE 6
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters can and do vary in different
applications. All operating parameters, including “T ypicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MPC2002•MPC2003
14
MOTOROLA FAST SRAM
Literature Distribution Centers:
USA/Europe: Motorola Literature Distribution; P .O. Box 20912; Phoenix, Arizona 85036.
JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan.
ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
MPC2002/D
*MPC2002/D*
◊
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