Motorola MMFT3055V Datasheet
1
Motorola TMOS Power MOSFET Transistor Device Data
N–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resistance area product about one–half that of standard MOSFET s. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
New Features of TMOS V
• On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low R
DS(on)
Technology
• Faster Switching than E–FET Predecessors
Features Common to TMOS V and TMOS E–FETS
• Avalanche Energy Specified
• I
DSS
and V
DS(on)
Specified at Elevated Temperature
• Static Parameters are the Same for both TMOS V and TMOS E–FET
• Available in 12 mm Tape & Reel
Use MMFT3055VT1 to order the 7 inch/1000 unit reel
Use MMFT3055VT3 to order the 13 inch/4000 unit reel
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain–to–Source Voltage V
DSS
60 Vdc
Drain–to–Gate Voltage (RGS = 1.0 MΩ) V
DGR
60 Vdc
Gate–to–Source Voltage – Continuous
Gate–to–Source Voltage – Non–repetitive (tp ≤ 10 ms)
V
GS
V
GSM
± 20
± 25
Vdc
Vpk
Drain Current – Continuous
Drain Current – Continuous @ 100°C
Drain Current – Single Pulse (tp ≤ 10 µs)
I
D
I
D
I
DM
1.7
1.4
6.0
Adc
Apk
Total PD @ TA = 25°C mounted on 1” sq. Drain pad on FR–4 bd material
Total PD @ TA = 25°C mounted on 0.70” sq. Drain pad on FR–4 bd material
Total PD @ TA = 25°C mounted on min. Drain pad on FR–4 bd material
Derate above 25°C
P
D
2.0
1.7
0.9
6.3
Watts
mW/°C
Operating and Storage Temperature Range TJ, T
stg
–55 to 175 °C
Single Pulse Drain–to–Source Avalanche Energy – Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 3.4 Apk, L = 10 mH, RG = 25 Ω )
E
AS
58
mJ
Thermal Resistance
– Junction to Ambient on 1” sq. Drain pad on FR–4 bd material
– Junction to Ambient on 0.70” sq. Drain pad on FR–4 bd material
– Junction to Ambient on min. Drain pad on FR–4 bd material
R
θJA
R
θJA
R
θJA
70
88
159
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T
L
260 °C
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E–FET and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Order this document
by MMFT3055V/D
SEMICONDUCTOR TECHNICAL DATA
TM
TMOS POWER FET
1.7 AMPERES
60 VOLTS
R
DS(on)
= 0.130 OHM
D
S
G
CASE 318E–04, Style 3
TO–261AA
1
2
3
4
Motorola, Inc. 1996
MMFT3055V
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
V
(BR)DSS
60
—
—
63
—
—
Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
I
DSS
—
—
—
—
10
100
µAdc
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) I
GSS
— — 100 nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
V
GS(th)
2.0
—
2.8
5.6
4.0
—
Vdc
mV/°C
Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 0.85 Adc) R
DS(on)
— 0.115 0.13 Ohm
Drain–to–Source On–Voltage
(VGS = 10 Vdc, ID = 1.7 Adc)
(VGS = 10 Vdc, ID = 0.85 Adc, TJ = 150°C)
V
DS(on)
—
—
—
—
0.27
0.25
Vdc
Forward Transconductance (VDS = 8.0 Vdc, ID = 1.7 Adc) g
FS
1.0 2.7 — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
— 360 500 pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
C
oss
— 110 150
Transfer Capacitance
f = 1.0 MHz)
C
rss
— 25 50
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
t
d(on)
— 8.0 20 ns
Rise Time
t
r
— 9.0 20
Turn–Off Delay Time
VGS = 10 Vdc,
RG = 9.1 Ω)
t
d(off)
— 32 60
Fall Time
G
= 9.1 Ω)
t
f
— 18 40
Q
T
— 13 20 nC
DS
= 48 Vdc, ID = 1.7 Adc,
Q
1
— 2.0 —
(VDS = 48 Vdc, ID = 1.7 Adc,
VGS = 10 Vdc)
Q
2
— 5.0 —
Q
3
— 4.0 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1)
(IS = 1.7 Adc, VGS = 0 Vdc)
(IS = 1.7 Adc, VGS = 0 Vdc, TJ = 150°C)
V
SD
—
—
0.85
0.7
1.6
—
Vdc
t
rr
— 40 —
S
= 1.7 Adc, VGS = 0 Vdc,
t
a
— 34 —
(IS = 1.7 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
t
b
— 6.0 —
Reverse Recovery Stored Charge Q
RR
— 0.089 — µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
L
D
— 4.5 —
nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
S
— 7.5 —
nH
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
Gate Charge
Reverse Recovery Time
(VDD = 30 Vdc, ID = 1.7 Adc,
(V
(I
ns
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