MOTOROLA MMDF3N03HD Datasheet

MMDF3N03HD

Preferred Device

Power MOSFET
3 Amps, 30 Volts

N–Channel SO–8, Dual

These miniature surface mount MOSFET s feature ultra low R

DS(on)

and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
drain–to–source diode has a very low reverse recovery time.
MiniMOS devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dc–dc converters, and power management in portable
and battery powered products such as computers, printers, cellular and
cordless phones. They can also be used for low voltage motor controls
in mass storage products such as disk drives and tape drives. The
avalanche energy is specified to eliminate the guesswork in designs
where inductive loads are switched and offer additional safety margin
against unexpected voltage transients.

• Ultra Low R

Provides Higher Efficiency and Extends Battery

DS(on)

Life

• Logic Level Gate Drive – Can Be Driven by Logic ICs

• Miniature SO–8 Surface Mount Package – Saves Board Space

• Diode Is Characterized for Use In Bridge Circuits

• Diode Exhibits High Speed, With Soft Recovery

• I

Specified at Elevated Temperature

DSS

• Avalanche Energy Specified

• Mounting Information for SO–8 Package Provided

MAXIMUM RATINGS (T

Rating

Drain–to–Source Voltage V
Drain–to–Gate Voltage (RGS = 1.0 MΩ) V
Gate–to–Source Voltage – Continuous V
Drain Current – Continuous @ TA = 25°C

Drain Current – Continuous @ TA = 100°C
Drain Current – Single Pulse (tp ≤ 10 µs)

Total Power Dissipation @ TA = 25°C

(Note 1.)

Operating and Storage Temperature Range TJ, T

Single Pulse Drain–to–Source Avalanche

Energy – Starting TJ = 25°C
(VDD = 30 Vdc, VGS = 5.0 Vdc, Peak
IL = 9.0 Apk, L = 8.0 mH, RG = 25 Ω)

Thermal Resistance – Junction to Ambient

(Note 1.)

Maximum Lead Temperature for Soldering

Purposes, 1/8″ from case for 10 seconds

1. When mounted on 2″ square FR–4 board (1″ square 2 oz. Cu 0.06″ thick
single sided) with one die operating, 10s max.

= 25°C unless otherwise noted)

J

Symbol Value Unit

DSS

DGR

GS

I

D

I

D

I

DM
P

D

stg

E

AS

R

θJA

T

L

30 Vdc
30 Vdc

± 20 Vdc

4.1

3.0
40

2.0 Watts

– 55 to

150
324 mJ

62.5 °C/W

260 °C

Adc

Apk

°C

http://onsemi.com

3 AMPERES

30 VOLTS

R

DS(on)

G

8

1

L = Location Code
Y = Year
WW = Work Week

PIN ASSIGNMENT

Source–1

Gate–1

Source–2

Gate–2

ORDERING INFORMATION

Device Package Shipping

MMDF3N03HDR2 SO–8 2500 Tape & Reel

Preferred devices are recommended choices for future use
and best overall value.

= 70 m

N–Channel

D

SO–8, Dual

CASE 751

STYLE 11

1
2
3
4

Top View

S

8
7
6
5

MARKING
DIAGRAM

D3N03
LYWW

Drain–1
Drain–1

Drain–2
Drain–2

 Semiconductor Components Industries, LLC, 2000

November, 2000 – Rev. 7

1 Publication Order Number:

MMDF3N03HD/D

MMDF3N03HD

)

f = 1.0 MHz)

R

G

9.1 Ω)

R

G

9.1 Ω)

(V

DS

Vdc, I

D

Adc

)

dIS/dt = 100 A/µs)

ELECTRICAL CHARACTERISTICS (T

Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain–to–Source Breakdown Voltage

(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)

Zero Gate Voltage Drain Current

(VDS = 30 Vdc, VGS = 0 Vdc)
(VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125°C)

Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) I

ON CHARACTERISTICS (Note 2.)

Gate Threshold Voltage

(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)

Static Drain–to–Source On–Resistance

(VGS = 10 Vdc, ID = 3.0 Adc)
(VGS = 4.5 Vdc, ID = 1.5 Adc)

Forward Transconductance

(VDS = 3.0 Vdc, ID = 1.5 Adc)

DYNAMIC CHARACTERISTICS

Input Capacitance
Output Capacitance
Transfer Capacitance

SWITCHING CHARACTERISTICS (Note 3.)

Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Turn–On Delay Time t
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage (Note 2.)

Reverse Recovery Time

See Figure 12

Reverse Recovery Storage Charge Q

2. Pulse Test: Pulse Width ≤300 µs, Duty Cycle ≤ 2%.

3. Switching characteristics are independent of operating junction temperature.

= 25°C unless otherwise noted)

A

(VDS = 24 Vdc, VGS = 0 Vdc,

(VDD = 15 Vdc, ID = 3.0 Adc,

(VDD = 15 Vdc, ID = 3.0 Adc,

(VDS = 10 Vdc, ID = 3.0 Adc,

f = 1.0 MHz

VGS = 4.5 Vdc,

RG = 9.1 Ω)

VGS = 10 Vdc,

RG = 9.1 Ω)

10

VGS = 10 Vdc)

(IS = 3.0 Adc, VGS = 0 Vdc)
(IS = 3.0 Adc, VGS = 0 Vdc,

TJ = 125°C)

(IS = 3.0 Adc, VGS = 0 Vdc,

/dt = 100 A/µs

dI

3.0

,

V

(BR)DSS

I

DSS

GSS

V

GS(th)

R

DS(on)

g

FS

C

iss

C

oss

C

rss

t

d(on)

t

r

t

d(off)

t

f

d(on)

t

r

t

d(off)

t

f

Q
Q
Q
Q

V

SD

t

rr

t

a

t

b

RR

30

–

–
–

– – 100 nAdc

1.0 1.7 3.0

–
–

2.0 3.6 –

– 450 630 pF
– 160 225
– 35 70

– 12 24 ns
– 65 130
– 16 32
– 19 38
– 8 16 ns
– 15 30
– 30 60
– 23 46

T
1
2
3

– 11.5 16 nC
– 1.5 –
– 3.5 –
– 2.8 –

–
–

– 24 –
– 17 –
– 7 –
– 0.025 – µC

–

34.5

–
–

0.06

0.065

0.82

0.7

–
–

1.0
10

0.07

0.075

1.2

–

Vdc

mV/°C

µAdc

Vdc

mV/°C

Ohms

Mhos

Vdc

ns

http://onsemi.com

2

MMDF3N03HD

TYPICAL ELECTRICAL CHARACTERISTICS

6

VGS = 10 V

4.5 V

5

4.3 V

4.1 V

4

3

2

, DRAIN CURRENT (AMPS)

D

I

1

0

0.2 0.6

0 0.4 0.8 1.2 1.6 2

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

3.9 V

3.7 V

3.5 V

3.3 V

3.1 V

2.9 V

2.7 V

2.5 V

T

= 25°C

J

Figure 1. On–Region Characteristics

0.6

ID = 1.5 A
T

0.5

0.4

0.3

= 25°C

J

6

V

≥ 10 V

DS

5

4

100°C

3

T

= -55°C

J

25°C

2

, DRAIN CURRENT (AMPS)

D

I

1

0

1.81.41

2 2.5 3 3.5 4

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

0.08

T

= 25°C

J

0.07

VGS = 4.5

0.2

0.1

, DRAIN-TO-SOURCE RESISTANCE (OHMS)

0

DS(on)

2345 867

R

VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 3. On–Resistance versus

Gate–to–Source Voltage

2.0
VGS = 10 V
ID = 1.5 A

1.5

1.0

0.5

, DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)

0

-50 0 50 100 150

DS(on)

R

T

, JUNCTION TEMPERATURE (°C)

J

Figure 5. On–Resistance Variation

with Temperature

910

1257525-25

0.06

10 V

, DRAIN-TO-SOURCE RESISTANCE (OHMS)

0.05

DS(on)

0 0.5 1 2.5 3

ID, DRAIN CURRENT (AMPS)

1.5 2

Figure 4. On–Resistance versus Drain Current

and Gate Voltage

100

VGS = 0 V

T

= 125°C

J

10

, LEAKAGE (nA) R

DSS

I

1

0 5 10 15 30

VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

100°C

20 25

Figure 6. Drain–to–Source Leakage Current

versus V oltage

http://onsemi.com

3

MMDF3N03HD

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (∆t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain–gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I

) can be made from a

G(AV)

rudimentary analysis of the drive circuit so that
t = Q/I

G(AV)

During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, V

. Therefore, rise and fall

SGP

times may be approximated by the following:
tr = Q2 x RG/(VGG – V

tf = Q2 x RG/V

GSP

GSP

)

where
VGG = the gate drive voltage, which varies from zero to V

GG

RG = the gate drive resistance
and Q2 and V

are read from the gate charge curve.

GSP

During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

t

= RG C

d(on)

t

= RG C

d(off)

The capacitance (C

In [VGG/(VGG – V

iss

In (VGG/V

iss

) is read from the capacitance curve at

iss

GSP

)

GSP

)]

a voltage corresponding to the off–state condition when
calculating t
on–state when calculating t

and is read at a voltage corresponding to the

d(on)

d(off)

.

At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.

System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, trr, due
to the storage of minority carrier charge, QRR, as shown in
the typical reverse recovery wave form of Figure 11. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short trr and low QRR specifications to
minimize these losses.

The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by

high di/dts. The diode’s negative di/dt during ta is directly
controlled by the device clearing the stored charge.
However, the positive di/dt during tb is an uncontrollable
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of tb/ta serves as a good indicator of recovery
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.

Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter trr), have less stored charge and a softer
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.

http://onsemi.com

4