Motorola MCM69F819ZP8R, MCM69F819ZP11R, MCM69F819ZP7.5, MCM69F819ZP8.5, MCM69F819TQ8.5R Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

256K x 18 Bit Flow–Through
BurstRAM Synchronous
Fast Static RAM

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by MCM69F819/D

MCM69F819

The MCM69F819 is a 4M bit synchronous fast static RAM designed to provide
a burstable, high performance, secondary cache for the PowerPC and other
high performance microprocessors. It is organized as 256K words of 18 bits
each. This device integrates input registers, a 2–bit address counter, and high
speed SRAM onto a single monolithic circuit for reduced parts count in cache
data RAM applications. Synchronous design allows precise cycle control with the
use of an external clock (K).

Addresses (SA), data inputs (DQx), and all control signals except output
enable (G
edge–triggered noninverting registers.

addresses can be generated internally by the MCM69F819 (burst sequence
operates in linear or interleaved mode dependent upon the state of LBO
controlled by the burst address advance (ADV) input pin.

clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.

nous write enable (SW) are provided to allow writes to either individual bytes or
to all bytes. The two bytes are designated as “a” and “b”. SBa
SBb
asserted with SW. All bytes are written if either SGW is asserted or if all SBx and
SW

from the memory array .
operate on a 2.5 V or 3.3 V power supply . All inputs and outputs are JEDEC stan-

dard JESD8–5 compatible.

• MCM69F819–7.5: 7.5 ns Access/ 8.5 ns Cycle (117 MHz)

• 3.3 V + 10%, – 5% Core Power Supply , 2.5 V or 3.3 V I/O Supply

• ADSP

• Selectable Burst Sequencing Order (Linear/Interleaved)

• Single–Cycle Deselect Timing

• Internally Self–Timed Write Cycle

• Byte Write and Global Write Control

• PB1 Version 2.0 Compatible

• JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages

) and linear burst order (LBO) are clock (K) controlled through positive–

Bursts can be initiated with either ADSP

Write cycles are internally self–timed and are initiated by the rising edge of the

Synchronous byte write (SBx

controls DQb. Individual bytes are written if the selected byte writes SBx are

are asserted.

For read cycles, a flow–through SRAM allows output data to simply flow freely

The MCM69F819 operates from a 3.3 V core power supply and all outputs

MCM69F819–8: 8 ns Access/10 ns Cycle (100 MHz)
MCM69F819–8.5: 8.5 ns Access/11 ns Cycle 90 MHz)
MCM69F819–11: 11 ns Access/20 ns Cycle (50 MHz)

, ADSC, and ADV Burst Control Pins

), synchronous global write (SGW), and synchro-

or ADSC input pins. Subsequent burst

) and

controls DQa and

ZP PACKAGE

PBGA

CASE 999–02

TQ PACKAGE

TQFP

CASE 983A–01

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

REV 7
1/22/98

 Motorola, Inc. 1998

MOTOROLA FAST SRAM

MCM69F819

1

LBO

ADV

K
ADSC
ADSP

SA
SA1
SA0

FUNCTIONAL BLOCK DIAGRAM

K2

ADDRESS

REGISTER

18

BURST

COUNTER

CLR

2

16

2

18

256K x 18

ARRAY

SGW

SW

SBa

SBb

SE1
SE2

SE3

G

WRITE

REGISTER

a

WRITE

REGISTER

b

K2

ENABLE

REGISTER

2

DATA–IN

REGISTER

K

18

18

DQa – DQb

MCM69F819
2

MOTOROLA FAST SRAM

PIN ASSIGNMENTS

6543217
A
B
C

D
E

F
G

H
J

K
L
M

N
P

R
T

U

SA SA SA SA

V

DDQ

NC SE2 SA ADSC

SA SA SA SA

NC

DQb NC VSSNC DQa

DQbNC

V

NC V

DDQ

DQb

NC VSSSGW

V

V

V

DD

DDQ
NC DQb V

NCDQb

DQb V

DDQ

NCDQb

NC DQb VSSSA0

SA SA

NC

SA SA SA SA

NC

DDQ

SS
SS

SBbDQbNC

NCV

SS

V

SS
SS
SS

LBO

NCNC

ADSP

SA

SE3

V

DD

V

SS

V

NCSE1V

SS

DQa

V

G

SS

NCADV

V

SS

V

DQa

SS

V

NCV

DD
KV

NC
SW

DD

NC

NC

V
V
V

SS

SS
SS
SS

NCV

NC

NC

DQaSBa

NC

DQaSA1V

NC

NC

DD

V

V

V

V

V

DDQ

NC
NC
NC

DQa

DDQ

DQa

NC

DDQ

DQa

NC
DDQ

NC

DQa

NC
NC

DDQ

V

V

DDQ

V

V

DDQ

NC
NC
NC

DDQ

V

SS
NC

NC
DQb
DQb

V

SS
DQb

DQb

NC

V

DD

NC

V

SS
DQb

DQb

DDQ

V

SS

DQb
DQb
DQb

NC

V

SS

NC

NC

NC

1
2
3
4
5
6
7
8

9

10
11
12
13
14
15
16
17
18
19
20

21
22
23
24
25
26
27
28
29
30

31 3233

SASASE1

DD

SE2

NC

SBa

SBb

NC

94 93979695 89889291 90 86858710099 98 81828384

3738343536 42433940 41 454644

SE3

K

VSSV

SW

SGW

G

ADSP

ADSC

ADV

SA

SA

SA

80
79

NC

78

NC
V

77

DDQ

76

V

SS

NC

75

DQa

74
73

DQa

72

DQa

71

V

SS

70

V

DDQ

69

DQa

68

DQa
V

67

SS

NC

66

V

65

DD

NC

64

DQa

63

DQa

62

V

61

DDQ

V

60

SS

DQa

59
58

DQa
NC

57

NC

56

V

55

SS

V

54

DDQ

NC

53
52

NC
NC

51

50494847

TOP VIEW 119 BUMP PBGA

SASASA

LBO

SA

SA1

TOP VIEW 100 PIN TQFP

SA0

NC

NC

V

SS

DD

V

NC

NC

SA

SASASA

SA

SA

SA

Not to Scale

MOTOROLA FAST SRAM

MCM69F819

3

PBGA PIN DESCRIPTIONS

Pin Locations Symbol

4B ADSC Input Synchronous Address Status Controller: Active low, interrupts any

4A ADSP Input Synchronous Address Status Processor: Active low, interrupts any

4G ADV Input Synchronous Address Advance: Increments address count in

(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P

(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P

4F G Input Asynchronous Output Enable Input:

4K K Input Clock: This signal registers the address, data in, and all control signals

3R LBO Input Linear Burst Order Input: This pin must remain in steady state (this

2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C,

5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T

4N, 4P SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two

5L, 3G
(a) (b)

4E SE1 Input Synchronous Chip Enable: Active low to enable chip.

2B SE2 Input Synchronous Chip Enable: Active high for depth expansion.
6B SE3 Input Synchronous Chip Enable: Active low for depth expansion.
4H SGW Input Synchronous Global Write: This signal writes all bytes regardless of the

4M SW Input Synchronous Write: This signal writes only those bytes that have been

4C, 2J, 4J, 6J, 4R V

1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U V

3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H,
3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P

1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E,

2F, 1G, 6G, 2H, 7H, 3J, 5J, 1K, 6K,
2L, 4L, 7L, 6M, 2N, 7N, 1P, 6P, 1R,

5R, 7R, 1T, 4T, 7T, 2U, 3U, 4U, 5U, 6U

Type Description

ongoing burst and latches a new external address. Used to initiate a

READ, WRITE, or chip deselect.

ongoing burst and latches a new external address. Used to initiate a

new READ, WRITE, or chip deselect (exception — chip deselect does

not occur when ADSP

accordance with counter type selected (linear/interleaved).

DQx I/O Synchronous Data I/O: “x” refers to the byte being read or written

SA Input Synchronous Address Inputs: These inputs are registered and must

SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte

DD

DDQ

V

SS

NC — No Connection: There is no connection to the chip.

Supply Core Power Supply.
Supply I/O Power Supply.
Supply Ground.

(byte a, b).

Low — enables output buffers (DQx pins).

High — DQx pins are high impedance.

except G

signal not registered or latched). It must be tied high or low.

Low — linear burst counter (68K/PowerPC).

High — interleaved burst counter (486/i960/Pentium).

meet setup and hold times.

LSBs of the address bus for proper burst operation. These inputs are

registered and must meet setup and hold times.

a, b). SGW

Negated high — blocks ADSP

asserted.

status of the SBx

being used, tie this pin high.

selected using the byte write SBx

are being used, tie this pin low.

and LBO.

overrides SBx.

is asserted and SE1 is high).

or deselects chip when ADSC is

and SW signals. If only byte write signals SBx are

pins. If only byte write signals SBx

MCM69F819
4

MOTOROLA FAST SRAM

TQFP PIN DESCRIPTIONS

Pin Locations Symbol

85 ADSC Input Synchronous Address Status Controller: Active low, interrupts any

84 ADSP Input Synchronous Address Status Processor: Active low, interrupts any

83 ADV Input Synchronous Address Advance: Increments address count in

(a) 58, 59, 62, 63, 68, 69, 72, 73, 74

(b) 8, 9, 12, 13, 18, 19, 22, 23, 24

86 G Input Asynchronous Output Enable Input:

89 K Input Clock: This signal registers the address, data in, and all control signals

31 LBO Input Linear Burst Order Input: This pin must remain in steady state (this

32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50,

80, 81, 82, 99, 100

36, 37 SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two

93, 94

(a) (b)

88 SGW Input Synchronous Global Write: This signal writes all bytes regardless of the

98 SE1 Input Synchronous Chip Enable: Active low to enable chip.

97 SE2 Input Synchronous Chip Enable: Active high for depth expansion.
92 SE3 Input Synchronous Chip Enable: Active low for depth expansion.
87 SW Input Synchronous Write: This signal writes only those bytes that have been

15, 41, 65, 91 V

4, 11, 20, 27, 54, 61, 70, 77 V

5, 10, 17, 21, 26, 40,

55, 60, 67, 71, 76, 90

1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, 38,

39, 42, 43, 51, 52, 53, 56, 57, 64, 66, 75,

78, 79, 95, 96

Type Description

ongoing burst and latches a new external address. Used to initiate a

READ, WRITE, or chip deselect.

ongoing burst and latches a new external address. Used to initiate a

new READ, WRITE, or chip deselect (exception — chip deselect does

not occur when ADSP

accordance with counter type selected (linear/interleaved).

DQx I/O Synchronous Data I/O: “x” refers to the byte being read or written

SA Input Synchronous Address Inputs: These inputs are registered and must

SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte

DD

DDQ

V

SS

NC — No Connection: There is no connection to the chip.

Supply Core Power Supply.
Supply I/O Power Supply.
Supply Ground.

(byte a, b).

Low — enables output buffers (DQx pins).

High — DQx pins are high impedance.

except G

signal not registered or latched). It must be tied high or low.

Low — linear burst counter (68K/PowerPC).

High — interleaved burst counter (486/i960/Pentium).

meet setup and hold times.

LSBs of the address bus for proper burst operation. These inputs are

registered and must meet setup and hold times.

a, b). SGW

status of the SBx

being used, tie this pin high.

Negated high — blocks ADSP

asserted.

selected using the byte write SBx

are being used, tie this pin low.

and LBO.

overrides SBx.

is asserted and SE1 is high).

and SW signals. If only byte write signals SBx are

or deselects chip when ADSC is

pins. If only byte write signals SBx

MOTOROLA FAST SRAM

MCM69F819

5

TRUTH TABLE (See Notes 1 Through 5)

Address

Next Cycle

Deselect None 1 X X X 0 X X High–Z X
Deselect None 0 X 1 0 X X X High–Z X
Deselect None 0 0 X 0 X X X High–Z X
Deselect None X X 1 1 0 X X High–Z X
Deselect None X 0 X 1 0 X X High–Z X
Begin Read External 0 1 0 0 X X 0 High–Z X
Begin Read External 0 1 0 1 0 X 0 High–Z READ
Continue Read Next X X X 1 1 0 1 High–Z READ
Continue Read Next X X X 1 1 0 0 DQ READ
Continue Read Next 1 X X X 1 0 1 High–Z READ
Continue Read Next 1 X X X 1 0 0 DQ READ
Suspend Read Current X X X 1 1 1 1 High–Z READ
Suspend Read Current X X X 1 1 1 0 DQ READ
Suspend Read Current 1 X X X 1 1 1 High–Z READ
Suspend Read Current 1 X X X 1 1 0 DQ READ
Begin Write External 0 1 0 1 0 X X High–Z WRITE
Continue Write Next X X X 1 1 0 X High–Z WRITE
Continue Write Next 1 X X X 1 0 X High–Z WRITE
Suspend Write Current X X X 1 1 1 X High–Z WRITE
Suspend Write Current 1 X X X 1 1 X High–Z WRITE

NOTES:

1. X = Don’t Care. 1 = logic high. 0 = logic low.

2. Write is defined as either 1) any SBx

3. G

is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (t

4. On write cycles that follow read cycles, G
also remain negated at the completion of the write cycle to ensure proper write data hold times.

5. This read assumes the RAM was previously deselected.

Used

SE1 SE2 SE3 ADSP ADSC ADV G

and SW low or 2) SGW is low.

must be negated prior to the start of the write cycle to ensure proper write data setup times. G must

3

DQx Write 2,

) following G going low.

GLQX

4

5

5

LINEAR BURST ADDRESS TABLE (LBO = V

1st Address (External)

X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X10 X . . . X11 X . . . X00
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X00 X . . . X01 X . . . X10

2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal)

INTERLEAVED BURST ADDRESS TABLE (LBO = V

1st Address (External) 2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal)

X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X00 X . . . X11 X . . . X10
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X10 X . . . X01 X . . . X00

SS

)

)

DD

WRITE TRUTH TABLE

Cycle Type SGW SW SBa SBb

Read H H X X
Read H L H H
Write Byte a H L L H
Write Byte b H L H L
Write All Bytes H L L L
Write All Bytes L X X X

MCM69F819
6

MOTOROLA FAST SRAM