Motorola MCM67H618AFN9, MCM67H618AFN10, MCM67H618AFN12 Datasheet
MCM67H618A
1
MOTOROLA FAST SRAM
Product Preview
64K x 18 Bit BurstRAM
Synchronous Fast Static RAM
With Burst Counter and Self–Timed Write
The MCM67H618A is a 1,179,648 bit synchronous fast static random access
memory designed to provide a burstable, high–performance, secondary cache
for the i486 and Pentium microprocessors. It is organized as 65,536 words
of 18 bits, fabricated with Motorola’s high–performance silicon–gate BiCMOS
technology. The device integrates input registers, a 2–bit counter, high speed
SRAM, and high drive capability outputs onto a single monolithic circuit for
reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock
(K). BiCMOS circuitry reduces the overall power consumption of the integrated
functions for greater reliability.
Addresses (A0 – A15), data inputs (D0 – D17), and all control signals except
output enable (G
) are clock (K) controlled through positive–edge–triggered
noninverting registers.
Bursts can be initiated with either address status processor (ADSP
) or address
status cache controller (ADSC
) input pins. Subsequent burst addresses can be
generated internally by the MCM67H618A (burst sequence imitates that of the
i486 and Pentium) and controlled by the burst address advance (ADV
) input pin.
The following pages provide more detailed information on burst controls.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased flexibility for incoming signals.
Dual write enables (LW
and UW) are provided to allow individually writeable
bytes. LW
controls DQ0 – DQ8 (the lower bits), while UW controls DQ9 – DQ17
(the upper bits).
This device is ideally suited for systems that require wide data bus widths and
cache memory. See Figure 2 for applications information.
• Single 5 V
± 5% Power Supply
• Fast Access Times: 9/10/12 ns Max
• Byte Writeable via Dual Write Enables
• Internal Input Registers (Address, Data, Control)
• Internally Self–Timed Write Cycle
• ADSP
, ADSC, and ADV Burst Control Pins
• Asynchronous Output Enable Controlled Three–State Outputs
• Common Data Inputs and Data Outputs
• 3.3 V I/O Compatible
• High Board Density 52–Lead PLCC Package
• ADSP
Disabled with Chip Enable (E) – Supports Address Pipelining
BurstRAM is a trademark of Motorola, Inc.
i486 and Pentium are trademarks of Intel Corp.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
PIN ASSIGNMENT
10
9
8
DQ9
V
CC
DQ8
12
11
15
14
13
17
16
20
19
18
37
38
34
35
36
42
43
39
40
41
45
46
44
21 22 23 24 25 26 27 28 29 30 31 32 33
7 6 5 4 3 2 1 52 51 50 49 4847
DQ6
DQ7
V
SS
DQ4
DQ5
DQ2
DQ3
V
SS
V
CC
DQ0
DQ1
V
CC
V
SS
V
SS
V
CC
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
A6A7E
UW
K
A8A9A10
LW
G
A15
A4A3A2
A1
A13
A14
A12
A11
V
SS
A5
A0
V
CC
ADV
ADSC
ADSP
Order this document
by MCM67H618A/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MCM67H618A
FN PACKAGE
PLASTIC
CASE 778–02
PIN NAMES
A0 – A15 Address Inputs. . . . . . . . . . . . . . . .
K Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADV Burst Address Advance. . . . . . . . . . . .
LW
Lower Byte Write Enable. . . . . . . . . . . .
UW
Upper Byte Write Enable. . . . . . . . . . . .
ADSC
Controller Address Status. . . . . . . . .
ADSP
Processor Address Status. . . . . . . . .
E
Chip Enable. . . . . . . . . . . . . . . . . . . . . . . . .
G
Output Enable. . . . . . . . . . . . . . . . . . . . . .
DQ0 – DQ17 Data Input/Output. . . . . . . . . .
V
CC
+ 5 V Power Supply. . . . . . . . . . . . . . . .
V
SS
Ground. . . . . . . . . . . . . . . . . . . . . . . . . .
REV 1
5/95
Motorola, Inc. 1994
All power supply and ground pins must be
connected for proper operation of the device.
MCM67H618A
2
MOTOROLA FAST SRAM
BLOCK DIAGRAM (See Note)
BINARY
COUNTER
DQ0 – DQ8
CLR
Q0
Q1
A0
A1
K
ADSC
A0 – A15
E
G
ADDRESS
REGISTER
WRITE
REGISTER
ENABLE
REGISTER
DATA–IN
REGISTERS
OUTPUT
BUFFER
64K x 18
MEMORY
ARRAY
ADV
BURST LOGIC
INTERNAL
ADDRESS
A0
′
A1
′
16
9
18
16
2
A2 – A15
A1 – A0
DQ9 – DQ17
9
9 9
9
9
UW
LW
ADSP
NOTE: All registers are positive–edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the
next burst. When ADSP
and E are sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC)
is performed using the new external address. Alternatively, an ADSP
–initiated two cycle WRITE can be performed by as-
serting ADSP
, E, and a valid address on the first cycle, then negating both ADSP and ADSC and asserting LW and/or UW
with valid data on the second cycle (see Single Write Cycle in WRITE CYCLES timing diagram). Note that when E and
ADSC
are high, ADSP is ignored – the external address is not registered in this case.
When ADSC
is sampled low (and ADSP is sampled high), any ongoing burst is interrupted and a read or write (dependent
on W
) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded.
After the first cycle of the burst, ADV
controls subsequent burst cycles. When ADV is sampled low, the internal address
is advanced prior to the operation. When ADV
is sampled high, the internal address is not advanced, thus inserting a wait
state into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See
BURST SEQUENCE TABLE. Write refers to either or both byte write enables (LW
, UW).
BURST SEQUENCE TABLE (See Note)
External Address A15 – A2 A1 A0
1st Burst Address A15 – A2 A1 A0
2nd Burst Address A15 – A2 A1 A0
3rd Burst Address A15 – A2 A1 A0
NOTE: The burst wraps around to its initial state upon completion.
MCM67H618A
3
MOTOROLA FAST SRAM
SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)
E
ADSP ADSC ADV UW or LW K Address Used Operation
H X L X X L–H N/A Deselected
L L X X X L–H External Address Read Cycle, Begin Burst
L H L X L L–H External Address Write Cycle, Begin Burst
L H L X H L–H External Address Read Cycle, Begin Burst
X H H L L L–H Next Address Write Cycle, Continue Burst
X H H L H L–H Next Address Read Cycle, Continue Burst
X H H H L L–H Current Address Write Cycle, Suspend Burst
X H H H H L–H Current Address Read Cycle, Suspend Burst
H X H L L L–H Next Address Write Cycle, Continue Burst
H X H L H L–H Next Address Read Cycle, Continue Burst
H X H H L L–H Current Address Write Cycle, Suspend Burst
H X H H H L–H Current Address Read Cycle, Suspend Burst
NOTES:
1. X means Don’t Care.
2. All inputs except G
must meet setup and hold times for the low–to–high transition of clock (K).
3. Wait states are inserted by suspending burst.
ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
Operation
G I/O Status
Read L Data Out
Read H High–Z
Write X High–Z — Data In
Deselected X High–Z
NOTES:
1. X means Don’t Care.
2. For a write operation following a read operation, G
must be high before the input data
required setup time and held high through the input data hold time.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V
SS
= 0 V)
Rating
Symbol Value Unit
Power Supply Voltage V
CC
– 0.5 to + 7.0 V
Voltage Relative to VSS for Any
Pin Except V
CC
Vin, V
out
– 0.5 to VCC + 0.5 V
Output Current (per I/O) I
out
± 30 mA
Power Dissipation P
D
1.6 W
Temperature Under Bias T
bias
– 10 to + 85 °C
Operating Temperature T
A
0 to +70 °C
Storage Temperature T
stg
– 55 to + 125 °C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will ensure
the output devices are in High–Z at power up.
This device contains circuitry to protect the
inputs against damage due to high static volt
MCM67H618A
4
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
(Voltages referenced to VSS = 0 V)
Parameter
Symbol Min Max Unit
Supply Voltage (Operating Voltage Range) V
CC
4.75 5.25 V
Input High Voltage V
IH
2.2 VCC + 0.3** V
Input Low Voltage V
IL
– 0.5* 0.8 V
*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20.0 ns) for I ≤ 20.0 mA.
**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20.0 ns) for I ≤ 20.0 mA.
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter Symbol Min Max Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC) I
lkg(I)
— ± 1.0 µA
Output Leakage Current (G = VIH) I
lkg(O)
— ± 1.0 µA
AC Supply Current (G = VIH, E = VIL, I
out
= 0 mA, All Inputs = VIL or VIH, VIL = 0.0 V and
VIH ≥ 3.0 V, Cycle Time ≥ t
KHKH
min)
I
CCA9
I
CCA10
I
CCA12
—
—
—
275
265
250
mA
AC Standby Current (E = VIH, I
out
= 0 mA, All Inputs = VIL and V
IH, VIL
= 0.0 V and
VIH ≥ 3.0 V, Cycle Time ≥ t
KHKH
min)
I
SB1
— 95 mA
Output Low Voltage (IOL = + 8.0 mA) V
OL
— 0.4 V
Output High Voltage (IOH = – 4.0 mA) V
OH
2.4 3.3 V
NOTE: Good decoupling of the local power supply should always be used. DC characteristics are guaranteed for all possible i486 and Pentium
bus cycles.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T
A
= 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol Typ Max Unit
Input Capacitance (All Pins Except DQ0 – DQ17) C
in
4 5 pF
Input/Output Capacitance (DQ0 – DQ17) C
I/O
6 8 pF
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