Motorola MCM67A518FN12., MCM67A518FN15, MCM67A518FN10. Datasheet

MCM67A518

1

MOTOROLA FAST SRAM

32K x 18 Bit Asynchronous/
Latched Address Fast Static RAM

The MCM67A518 is a 589,824 bit latched address static random access
memory organized as 32,768 words of 18 bits, fabricated with Motorola’s high–
performance silicon–gate BiCMOS technology . The device integrates a 32K x 18
SRAM core with advanced peripheral circuitry consisting of address and data in­put latches, active low chip enable, separate upper and lower byte write strobes,
and a fast output enable. This device has increased output drive capability sup­ported by multiple power pins.

Address, data in, and chip enable latches are provided. When latch enables
(AL for address and chip enables and DL for data in) are high, the address, data
in, and chip enable latches are in the transparent state. If latch enables are tied
high, the device can be used as an asynchronous SRAM. When latch enables
are low, the address, data in, and chip enable latches are in the latched state. This
input latch simplifies read and write cycles by guaranteeing address and data–in
hold time in a simple fashion.

Dual write enables (LW

and UW) are provided to allow individually writeable

bytes. LW

controls DQ0 – DQ8 (the lower bits) while UW controls DQ9 – DQ17

(the upper bits).

Additional power supply pins have been utilized and placed on the package for
maximum performance.

The MCM67A518 will be available in a 52–pin plastic leaded chip carrier
(PLCC).

This device is ideally suited for systems which require wide data bus widths,
cache memory, and tag RAMs.

• Single 5 V

± 10% Power Supply

• Fast Access Times: 10/12/15 ns Max

• Byte Writeable via Dual Write Enables

• Separate Data Input Latch for Simplified Write Cycles

• Address and Chip Enable Input Latches

• Common Data Inputs and Data Outputs

• Output Enable Controlled Three–State Outputs

• 3.3 V I/O Compatible

• High Board Density 52–Lead PLCC Package

PIN ASSIGNMENT

V

CC

DQ10

DQ9

V

SS

DQ11
DQ12
DQ13
DQ14

V

SS

V

CC

DQ15
DQ16

DQ17

DQ7
DQ6

V

CC

V

SS

DQ5
DQ4

DQ3
DQ2

V

SS

V

CC

DQ1
DQ0

8

9
10
11
12
13

14
15

16
17
18

19
20

46
45

44
43
42
41
40
39
38
37
36
35
34

4748495051521234567

33323130292827262524232221

SS

V

DQ8

CC

V

A4A3A2

A1

A5

A0

NC

A13

A14

A12

A11

V

SS

V

CC

AL

A8A9A10

G

A6A7E

UW

LW

DL

All power supply and ground pins must be
connected for proper operation of the device.

PIN NAMES

A0 – A14 Address Inputs. . . . . . . . . . . . . . . .

AL Address Latch. . . . . . . . . . . . . . . . . . . . . .

DL Data Latch. . . . . . . . . . . . . . . . . . . . . . . . .

LW

Lower Byte Write Enable. . . . . . . . . . . .

UW

Higher Byte Write Enable. . . . . . . . . . . .

E

Chip Enable. . . . . . . . . . . . . . . . . . . . . . . . .

G

Output Enable. . . . . . . . . . . . . . . . . . . . . .

DQ0 – DQ17 Data Input/Output. . . . . . . . . . .

V

CC

+ 5 V Power Supply. . . . . . . . . . . . . . . .

V

SS

Ground. . . . . . . . . . . . . . . . . . . . . . . . . . .

NC No Connection. . . . . . . . . . . . . . . . . . . . .

Order this document

by MCM67A518/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MCM67A518

FN PACKAGE

PLASTIC

CASE 778–02

REV 2
5/95

 Motorola, Inc. 1994

MCM67A518
2

MOTOROLA FAST SRAM

BLOCK DIAGRAM

A0 – A14

DQ0 – DQ17

MEMORY ARRAY

32K x 18

E

WRITE AMP

OUTPUT
BUFFER

CONTROL

15

18

AL

LW

UW G

15

18

18

LATCH

DL

18

9 9

LATCH

LATCH

TRUTH TABLE

E LW UW AL* DL* G Mode

Supply

Current

I/O

Status

H X X X X X Deselected Cycle I

SB

High–Z

L X X L X X Read or Write Using Latched Addresses I

CC

—

L X X H X X Read or Write Using Unlatched Addresses I

CC

—

L H H X X L Read Cycle I

CC

Data Out

L H H X X H Read Cycle I

CC

High–Z

L L L X L X Write Both Bytes Using Latched Data In I

CC

High–Z

L L L X H X Write Both Bytes Using Unlatched Data In I

CC

High–Z

L L H X X X Write Cycle, Lower Byte I

CC

High–Z

L H L X X X Write Cycle, Lower Byte I

CC

High–Z

*E and Addresses satisfy the specified setup and hold times for the falling edge of AL. Data–in satisfies the specified setup and hold times for falling
edge of DL.
NOTE: This truth table shows the application of each function. Combinations of these functions are valid.

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V

SS

= 0)

Rating

Symbol Value Unit

Power Supply Voltage V

CC

– 0.5 to 7.0 V

Voltage Relative to VSS for Any
Pin Except V

CC

Vin, V

out

– 0.5 to VCC + 0.5 V

Output Current (per I/O) I

out

± 30

mA

Power Dissipation P

D

1.6 W

Temperature Under Bias T

bias

– 10 to + 85 °C

Operating Temperature T

A

0 to + 70 °C

Storage Temperature T

stg

– 55 to + 125 °C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to RECOMMENDED OPER­ATING CONDITIONS. Exposure to higher t han recommended voltages for
extended periods of time could affect device reliability.

advised
that normal precautions be taken to avoid
application of any voltage higher than maxi­mum rated voltages to this high–impedance
circuit.

This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.

This device contains circuitry that will ensure
the output devices are in High–Z at power up.

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is

MCM67A518

3

MOTOROLA FAST SRAM

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

(Voltages referenced to VSS = 0 V)

Parameter

Symbol Min Max Unit

Supply Voltage (Operating Voltage Range) V

CC

4.5 5.5 V

Input High Voltage V

IH

2.2

VCC + 0.3**

V

Input Low Voltage V

IL

– 0.5*

0.8 V

** VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.

** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.

DC CHARACTERISTICS

Parameter Symbol Min Max Unit

Input Leakage Current (All Inputs, Vin = 0 to VCC) I

lkg(I)

— ± 1.0 µA

Output Leakage Current (G = VIH) I

lkg(O)

— ± 1.0 µA

AC Supply Current (G = VIH, I

out

= 0 mA, All Inputs = VIL or VIH, VIL = 0.0 V and

VIH ≥ 3.0, Cycle Time ≥ t

AVAV

min)

I

CCA10

I

CCA12

I

CCA15

— 290

275
260

mA

AC Standby Current (E = VIH, I

out

= 0 mA, All Inputs = VIL and V

IH, VIL

= 0.0 V and

VIH ≥ 3.0 V, f = f

max

)

I

SB1

— 75 mA

CMOS Standby Current (E ≥ VCC – 0.2, All Inputs ≥ VCC – 0.2 V or ≤ 0.2 V,

f = f

max

)

I

SB2

— 30 mA

Output Low Voltage (IOL = + 8.0 mA) V

OL

— 0.4 V

Output High Voltage (IOH = – 4.0 mA) V

OH

2.4 3.3 V

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

A

= 25°C, Periodically Sampled Rather Than 100% Tested)

Characteristic

Symbol Typ Max Unit

Input Capacitance (All Pins Except DQ0 – DQ17) C

in

4 5 pF

Input/Output Capacitance (DQ0 – DQ17) C

I/O

6 8 pF

MCM67A518
4

MOTOROLA FAST SRAM

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 3 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Timing Reference Level 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .

Output Load Figure 1 Unless Otherwise Noted. . . . . . . . . . . . . . . . . .

ASYNCHRONOUS READ CYCLE TIMING (See Notes 1 and 2)

MCM67A518–10 MCM67A518–12 MCM67A518–15

Parameter Symbol Min Max Min Max Min Max Unit Notes

Read Cycle Times t

AVAV

10 — 12 — 15 — ns 3

Access Times:

Address Valid to Output Valid

E Low to Output Valid

Output Enable Low to Output Valid

t

AVQV

t

ELQV

t

GLQV

—
—
—

10
10

5

—
—
—

12
12

6

—
—
—

15
15

7

ns 4

Output Hold from Address Change t

AXQX

4 — 4 — 4 — ns

Output Buffer Control:

E

Low to Output Active

G

Low to Output Active

E

High to Output High–Z

G

High to Output High–Z

t

ELQX

t

GLQX

t

EHQZ

t

GHQZ

3
1
2
2

—
—

5
5

3
1
2
2

—
—

6
6

2
1
2
2

—
—

9
7

ns 5

Power Up Time t

ELICCA

0 — 0 — 0 — ns

NOTES:

1. AL and DL are equal to VIH for all asynchronous cycles.

2. Both Write Enable signals (LW

, UW) are equal to VIH for all read cycles.

3. All read cycle timing is referenced from the last valid address to the first transitioning address.

4. Addresses valid prior to or coincident with E

going low.

5. Transition is measured ± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested.
At any given voltage and temperature, t

EHQZ

is less than t

ELQX

and t

GHQZ

is less than t

GLQX

for a given device.

AC TEST LOADS

Figure 1A Figure 1B

5 pF

+ 5 V

OUTPUT

480

Ω

255

Ω

OUTPUT

Z0 = 50

Ω

RL = 50

Ω

VL = 1.5 V