Motorola MCM6708AJ12, MCM6708AJ12R2, MCM6708AJ8, MCM6708AJ8R2, MCM6708AJ10R2 Datasheet
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MCM6708A
2–1
MOTOROLA FAST SRAM
64K x 4 Bit Static RAM
The MCM6708A is a 262,144 bit static random access memory organized as
65,536 words of 4 bits, fabricated using high–performance silicon–gate BiCMOS
technology. Static design eliminates the need for external clocks or timing
strobes.
The MCM6708A is available in a 300 mil, 24 lead plastic surface–mount SOJ
package.
• Single 5 V ± 10% Power Supply
• Fully Static — No Clock or Timing Strobes Necessary
• All Inputs and Outputs are TTL Compatible
• Three State Outputs
• Fast Access Times:
MCM6708A–8 = 8 ns
MCM6708A–10 = 10 ns
MCM6708A–12 = 12 ns
BLOCK DIAGRAM
INPUT
DATA
CONTROL
MEMORY MATRIX
256 ROWS x 256 x 4
COLUMNS
COLUMN I/O
COLUMN DECODER
A A A A A A A A
A
A
A
A
A
A
A
A
DQ0
DQ3
E
W
ROW
DECODER
•
•
•
•
•
•
•
•
•
Order this document
by MCM6708A/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
PIN ASSIGNMENT
MCM6708A
J PACKAGE
300 MIL SOJ
CASE 810A–02
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
E
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
V
CC
A15
A14
A13
A12
A11
A10
DQ0
DQ1
DQ2
DQ3
W
24
23
22
21
20
19
18
17
16
15
14
13
A0 – A15 Address Inputs. . . . . . . . . . .
W
Write Enable. . . . . . . . . . . . . . . . . . .
E
Chip Enable. . . . . . . . . . . . . . . . . . . . .
DQ0 – DQ3 Data Input/Output. . . . . . .
V
CC
+ 5 V Power Supply. . . . . . . . . . .
V
SS
Ground. . . . . . . . . . . . . . . . . . . . . .
NC No Connection. . . . . . . . . . . . . . . .
PIN NAMES
REV 5
5/95
Motorola, Inc. 1995
MCM6708A
2–2
MOTOROLA FAST SRAM
TRUTH TABLE (X = Don’t Care)
E
G W Mode Output Cycle
H X X Not Selected High–Z —
L H H Read High–Z —
L L H Read D
out
Read Cycle
L X L Write D
in
Write Cycle
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating
Symbol Value Unit
Power Supply Voltage V
CC
– 0.5 to + 7.0 V
Voltage Relative to VSS for Any Pin
Except V
CC
Vin, V
out
– 0.5 to VCC + 0.5 V
Output Current (per I/O) I
out
± 30 mA
Power Dissipation P
D
2.0 W
Temperature Under Bias T
bias
– 10 to + 85 °C
Operating Temperature T
A
0 to + 70 °C
Storage Temperature — Plastic T
stg
– 55 to + 125 °C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Typ Max Unit
Supply Voltage (Operating Voltage Range) V
CC
4.5 5.0 5.5 V
Input High Voltage V
IH
2.2 — VCC + 0.3* V
Input Low Voltage V
IL
– 0.5** — 0.8 V
*VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.
**VIL (min) = – 0.5 V dc @ 30.0 mA; VIL (min) = – 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.
DC CHARACTERISTICS
Parameter Symbol Min Max Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC) I
lkg(I)
— ± 1.0 µA
Output Leakage Current (E = VIH, V
out
= 0 to VCC) I
lkg(O)
— ± 1.0 µA
Output High Voltage (IOH = – 4.0 mA) V
OH
2.4 — V
Output Low Voltage (IOL = 8.0 mA) V
OL
— 0.4 V
POWER SUPPLY CURRENTS
Parameter Symbol MCM6708A–8 MCM6708A–10 MCM6708A–12 Unit Notes
AC Active Supply Current (I
out
= 0 mA, VCC = max,
f = f
max
)
I
CCA
185 175 165 mA 1, 2, 3
AC Standby Current (E = VIH, VCC = max, f = f
max
) I
SB1
120 110 105 mA 1, 2, 3
CMOS Standby Current (VCC = max, f = 0 MHz,
E
≥ VCC – 0.2 V, Vin ≤ VSS, or ≥ VCC – 0.2 V)
I
SB2
50 50 50 mA
NOTES:
1. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V).
2. All addresses transition simultaneously low (LSB) and then high (MSB).
3. Data states are all zero.
against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid application of any voltage higher than maximum
rated voltages to this high–impedance circuit.
This BiCMOS memory circuit has been designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear feet
per minute is maintained.
This device contains circuitry to protect the
inputs
MCM6708A
2–3
MOTOROLA FAST SRAM
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T
A
= 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol Max Unit
Address Input Capacitance C
in
5 pF
Control Pin Input Capacitance (E, G, W) C
in
5 pF
Input/Output Capacitance C
I/O
6 pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .
Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time 2 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .
Output Load See Figure 1A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ CYCLES 1 AND 2 (See Notes 1 and 2)
MCM6708A–8 MCM6708A–10 MCM6708A–12
Parameter Symbol Min Max Min Max Min Max Unit Notes
Read Cycle Time t
AVAV
8 — 10 — 12 — ns 3
Address Access Time t
AVQV
— 8 — 10 — 12 ns
Chip Enable Access Time t
ELQV
— 8 — 10 — 12 ns
Output Hold from Address Change t
AXQX
3 — 3 — 3 — ns
Chip Enable Low to Output Active t
ELQX
1 — 1 — 1 — ns 4, 5, 6
Chip Enable High to Output High–Z t
EHQZ
0 4.5 0 5 0 6 ns 4, 5, 6
NOTES:
1. W
is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All read cycle timings are referenced from the last valid address to the first transitioning address.
4. At any given voltage and temperature, t
EHQZ
max is less than t
ELQX
min for a given device and from device to device.
5. Transition is measured 200 mV from steady–state voltage with load of Figure 1B.
6. This parameter is sampled and not 100% tested.
AC TEST LOADS
OUTPUT
Z0 = 50
Ω
RL = 50
Ω
VL = 1.5 V
Figure 1A Figure 1B
5 pF
+5 V
OUTPUT
255
Ω
480
Ω
The table of timing values shows either a
minimum or a maximum limit for each parameter. Input requirements are specified from
the external system point of view. Thus, address setup time is shown as a minimum
since the system must supply at least that
much time (even though most devices do not
require it). On the other hand, responses from
the memory are specified from the device
point of view. Thus, the access time is shown
as a maximum since the device never provides data later than that time.
TIMING LIMITS
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