Motorola MCM6706RJ7, MCM6706RJ7R2, MCM6706RJ8, MCM6706RJ8R2, MCM6706RJ6R2 Datasheet

MCM6706R

1

MOTOROLA FAST SRAM

32K x 8 Bit Static Random Access
Memory

The MCM6706R is a 262,144 bit static random access memory organized as
32,768 words of 8 bits, fabricated using high performance silicon–gate BiCMOS
technology. Static design eliminates the need for external clocks or timing
strobes.

Output enable (G

) is a special control feature that provides increased system

flexibility and eliminates bus contention problems.

The MCM6706R meets JEDEC standards and is available in a revolutionary
pinout 300 mil, 32–lead surface–mount SOJ package.

• Single 5.0 V ± 10% Power Supply

• Fully Static — No Clock or Timing Strobes Necessary

• All Inputs and Outputs Are TTL Compatible

• Three State Outputs

• Fast Access Times: MCM6706R–6 = 6 ns

MCM6706R–7 = 7 ns
MCM6706R–8 = 8 ns

• Center Power and I/O Pins for Reduced Noise

BLOCK DIAGRAM

ROW

DECODER

MEMORY

MATRIX

512 ROWS x 64 x 8

COLUMNS

INPUT

DATA

CONTROL

COLUMN I/O

COLUMN DECODER

A
A
A
A
A
A
A
A

DQ0

A A A

E

W

V

CC

V

SS

A

A A A

DQ7

G

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by MCM6706R/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

PIN ASSIGNMENT

MCM6706R

J PACKAGE
300 MIL SOJ

CASE 857–02

32
31
30
29
28
27
26
25
24
23
22
21

2
3

1

5
6

4

7

9
10

8

12
13

11

14

20

15
16

19
18
17

A1
A2
A3

E

A7

W
A4
A5
A6

V

CC

A11

A9
A8

A10

DQ5

DQ6

A12
G

A13

A14

V

SS

V

CC

V

SS

DQ1

DQ3

A0 NC

NC

DQ0

DQ2

DQ4

DQ7

A0 – A14 Address. . . . . . . . . . . . . . . . . .

W

Write Enable. . . . . . . . . . . . . . . . . . . .

E

Chip Enable. . . . . . . . . . . . . . . . . . . . . .

G

Output Enable. . . . . . . . . . . . . . . . . . .

DQ0 – DQ7 Data Input/Output. . . . . . . .

V

CC

+ 5 V Power Supply. . . . . . . . . . . .

V

SS

Ground. . . . . . . . . . . . . . . . . . . . . . .

NC No Connection. . . . . . . . . . . . . . . . .

PIN NAMES

REV 1
5/95

 Motorola, Inc. 1995

MCM6706R
2

MOTOROLA FAST SRAM

TRUTH TABLE

E G W Mode I/O Pin Cycle

H X X Not Selected High–Z —
L H H Read High–Z —
L L H Read D

out

Read Cycle

L X L Write D

in

Write Cycle

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating

Symbol Value Unit

Power Supply Voltage V

CC

– 0.5 to + 7.0 V

Voltage Relative to VSS for Any Pin

Except V

CC

Vin, V

out

– 0.5 to VCC + 0.5 V

Output Current I

out

± 30 mA

Power Dissipation P

D

2.0 W

Temperature Under Bias T

bias

– 10 to + 85 °C

Operating Temperature T

A

0 to + 70 °C

Storage Temperature — Plastic T

stg

– 55 to + 125 °C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to RECOMMENDED OPER­ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit

Supply Voltage (Operating Voltage Range) V

CC

4.5 5.0 5.5 V

Input High Voltage V

IH

2.2 —

VCC + 0.3*

V

Input Low Voltage V

IL

– 0.5**

— 0.8 V

*VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.

**VIL (min) = – 0.5 V dc @ 30.0 mA; VIL (min) = – 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.

DC CHARACTERISTICS

Parameter Symbol Min Max Unit

Input Leakage Current (All Inputs, Vin = 0 to VCC) I

lkg(I)

— ± 1.0 µA

Output Leakage Current (E = VIH or G = VIH, V

out

= 0 to VCC) I

lkg(O)

— ± 1.0 µA

Output High Voltage (IOH = – 4.0 mA) V

OH

2.4 — V

Output Low Voltage (IOL = + 8.0 mA) V

OL

— 0.4 V

POWER SUPPLY CURRENTS

Parameter Symbol 6706R–6 6706R–7 6706R–8 Unit Notes

AC Active Supply Current (I

out

= 0 mA, VCC = max, f = f

max

) I

CCA

205 200 195 mA 1, 2, 3

AC Standby Current (E = VIH, VCC = max, f = f

max

) I

SB1

95 90 85 mA 1, 2. 3

CMOS Standby Current (VCC = max, f = 0 MHz, E ≥ VCC – 0.2 V,

Vin ≤ VSS, or ≥ VCC – 0.2 V)

I

SB2

20 20 20 mA

NOTES:

1. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V).

2. All addresses transition simultaneously low (LSB) and then high (MSB).

3. Data states are all zero.

­ages or electric fields; however, it is advised
that normal precautions be taken to avoid appli­cation of any voltage higher than maximum
rated voltages to this high–impedance circuit.

This BiCMOS memory circuit has been de­signed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear feet
per minute is maintained.

This device contains circuitry to protect the

inputs against damage due to high static volt

MCM6706R

3

MOTOROLA FAST SRAM

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

A

= 25°C, Periodically Sampled Rather Than 100% Tested)

Parameter

Symbol Max Unit

Address Input Capacitance C

in

5 pF

Control Pin Input Capacitance (E, G, W) C

in

6 pF

I/O Capacitance C

out

6 pF

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 2 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .

Output Load See Figure 1A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

READ CYCLE (See Notes 1 and 2)

MCM6706R–6 MCM6706R–7 MCM6706R–8

Parameter Symbol Min Max Min Max Min Max Unit Notes

Read Cycle Time t

AVAV

6 — 7 — 8 — ns 3

Address Access Time t

AVQV

— 6 — 7 — 8 ns

Chip Enable Access Time t

ELQV

— 6 — 7 — 8 ns

Output Enable Access Time t

GLQV

— 4 — 4 — 4 ns

Output Hold from Address Change t

AXQX

3 — 3 — 3 — ns

Chip Enable Low to Output Active t

ELQX

3 — 3 — 3 — ns 4 ,5, 6

Chip Enable High to Output High–Z t

EHQZ

0 3 0 3.5 0 4 ns 4, 5, 6

Output Enable Low to Output Active t

GLQX

0 — 0 — 0 — ns 4, 5, 6

Output Enable High to Output High–Z t

GHQZ

0 3 0 3.5 0 4 ns 4, 5, 6

NOTES:

1. W

is high for read cycle.

2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.

3. All read cycle timing is referenced from the last valid address to the first transitioning address.

4. At any given voltage and temperature, t

EHQZ

max < t

ELQX

min, and t

GHQZ

max < t

GLQX

min, both for a given device and from

device to device.

5. Transition is measured 200 mV from steady–state voltage with load of Figure 1B.

6. This parameter is sampled and not 100% tested.

7. Device is continuously selected (E

= VIL, G = VIL).

8. Addresses valid prior to or coincident with E

going low.

AC TEST LOADS

OUTPUT

Z0 = 50

Ω

RL = 50

Ω

VL = 1.5 V

Figure 1A Figure 1B

5 pF

+5 V

OUTPUT

255

Ω

480

Ω

The table of timing values shows either a
minimum or a maximum limit for each param­eter. Input requirements are specified from
the external system point of view. Thus, ad­dress setup time is shown as a minimum
since the system must supply at least that
much time (even though most devices do not
require it). On the other hand, responses from
the memory are specified from the device
point of view. Thus, the access time is shown
as a maximum since the device never pro­vides data later than that time.

TIMING LIMITS