MCM6706R
1
MOTOROLA FAST SRAM
32K x 8 Bit Static Random Access
Memory
The MCM6706R is a 262,144 bit static random access memory organized as
32,768 words of 8 bits, fabricated using high performance silicon–gate BiCMOS
technology. Static design eliminates the need for external clocks or timing
strobes.
Output enable (G
) is a special control feature that provides increased system
flexibility and eliminates bus contention problems.
The MCM6706R meets JEDEC standards and is available in a revolutionary
pinout 300 mil, 32–lead surface–mount SOJ package.
• Single 5.0 V ± 10% Power Supply
• Fully Static — No Clock or Timing Strobes Necessary
• All Inputs and Outputs Are TTL Compatible
• Three State Outputs
• Fast Access Times: MCM6706R–6 = 6 ns
MCM6706R–7 = 7 ns
MCM6706R–8 = 8 ns
• Center Power and I/O Pins for Reduced Noise
BLOCK DIAGRAM
ROW
DECODER
MEMORY
MATRIX
512 ROWS x 64 x 8
COLUMNS
INPUT
DATA
CONTROL
COLUMN I/O
COLUMN DECODER
A
A
A
A
A
A
A
A
DQ0
A A A
E
W
V
CC
V
SS
A
A A A
DQ7
G
Order this document
by MCM6706R/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
PIN ASSIGNMENT
MCM6706R
J PACKAGE
300 MIL SOJ
CASE 857–02
32
31
30
29
28
27
26
25
24
23
22
21
2
3
1
5
6
4
7
9
10
8
12
13
11
14
20
15
16
19
18
17
A1
A2
A3
E
A7
W
A4
A5
A6
V
CC
A11
A9
A8
A10
DQ5
DQ6
A12
G
A13
A14
V
SS
V
CC
V
SS
DQ1
DQ3
A0 NC
NC
DQ0
DQ2
DQ4
DQ7
A0 – A14 Address. . . . . . . . . . . . . . . . . .
W
Write Enable. . . . . . . . . . . . . . . . . . . .
E
Chip Enable. . . . . . . . . . . . . . . . . . . . . .
G
Output Enable. . . . . . . . . . . . . . . . . . .
DQ0 – DQ7 Data Input/Output. . . . . . . .
V
CC
+ 5 V Power Supply. . . . . . . . . . . .
V
SS
Ground. . . . . . . . . . . . . . . . . . . . . . .
NC No Connection. . . . . . . . . . . . . . . . .
PIN NAMES
REV 1
5/95
Motorola, Inc. 1995
查询MCM6706J6供应商
MCM6706R
2
MOTOROLA FAST SRAM
TRUTH TABLE
E G W Mode I/O Pin Cycle
H X X Not Selected High–Z —
L H H Read High–Z —
L L H Read D
out
Read Cycle
L X L Write D
in
Write Cycle
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating
Symbol Value Unit
Power Supply Voltage V
CC
– 0.5 to + 7.0 V
Voltage Relative to VSS for Any Pin
Except V
CC
Vin, V
out
– 0.5 to VCC + 0.5 V
Output Current I
out
± 30 mA
Power Dissipation P
D
2.0 W
Temperature Under Bias T
bias
– 10 to + 85 °C
Operating Temperature T
A
0 to + 70 °C
Storage Temperature — Plastic T
stg
– 55 to + 125 °C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Typ Max Unit
Supply Voltage (Operating Voltage Range) V
CC
4.5 5.0 5.5 V
Input High Voltage V
IH
2.2 —
VCC + 0.3*
V
Input Low Voltage V
IL
– 0.5**
— 0.8 V
*VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.
**VIL (min) = – 0.5 V dc @ 30.0 mA; VIL (min) = – 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.
DC CHARACTERISTICS
Parameter Symbol Min Max Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC) I
lkg(I)
— ± 1.0 µA
Output Leakage Current (E = VIH or G = VIH, V
out
= 0 to VCC) I
lkg(O)
— ± 1.0 µA
Output High Voltage (IOH = – 4.0 mA) V
OH
2.4 — V
Output Low Voltage (IOL = + 8.0 mA) V
OL
— 0.4 V
POWER SUPPLY CURRENTS
Parameter Symbol 6706R–6 6706R–7 6706R–8 Unit Notes
AC Active Supply Current (I
out
= 0 mA, VCC = max, f = f
max
) I
CCA
205 200 195 mA 1, 2, 3
AC Standby Current (E = VIH, VCC = max, f = f
max
) I
SB1
95 90 85 mA 1, 2. 3
CMOS Standby Current (VCC = max, f = 0 MHz, E ≥ VCC – 0.2 V,
Vin ≤ VSS, or ≥ VCC – 0.2 V)
I
SB2
20 20 20 mA
NOTES:
1. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V).
2. All addresses transition simultaneously low (LSB) and then high (MSB).
3. Data states are all zero.
ages or electric fields; however, it is advised
that normal precautions be taken to avoid application of any voltage higher than maximum
rated voltages to this high–impedance circuit.
This BiCMOS memory circuit has been designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear feet
per minute is maintained.
This device contains circuitry to protect the
inputs against damage due to high static volt
MCM6706R
3
MOTOROLA FAST SRAM
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T
A
= 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol Max Unit
Address Input Capacitance C
in
5 pF
Control Pin Input Capacitance (E, G, W) C
in
6 pF
I/O Capacitance C
out
6 pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .
Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time 2 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .
Output Load See Figure 1A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ CYCLE (See Notes 1 and 2)
MCM6706R–6 MCM6706R–7 MCM6706R–8
Parameter Symbol Min Max Min Max Min Max Unit Notes
Read Cycle Time t
AVAV
6 — 7 — 8 — ns 3
Address Access Time t
AVQV
— 6 — 7 — 8 ns
Chip Enable Access Time t
ELQV
— 6 — 7 — 8 ns
Output Enable Access Time t
GLQV
— 4 — 4 — 4 ns
Output Hold from Address Change t
AXQX
3 — 3 — 3 — ns
Chip Enable Low to Output Active t
ELQX
3 — 3 — 3 — ns 4 ,5, 6
Chip Enable High to Output High–Z t
EHQZ
0 3 0 3.5 0 4 ns 4, 5, 6
Output Enable Low to Output Active t
GLQX
0 — 0 — 0 — ns 4, 5, 6
Output Enable High to Output High–Z t
GHQZ
0 3 0 3.5 0 4 ns 4, 5, 6
NOTES:
1. W
is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All read cycle timing is referenced from the last valid address to the first transitioning address.
4. At any given voltage and temperature, t
EHQZ
max < t
ELQX
min, and t
GHQZ
max < t
GLQX
min, both for a given device and from
device to device.
5. Transition is measured 200 mV from steady–state voltage with load of Figure 1B.
6. This parameter is sampled and not 100% tested.
7. Device is continuously selected (E
= VIL, G = VIL).
8. Addresses valid prior to or coincident with E
going low.
AC TEST LOADS
OUTPUT
Z0 = 50
Ω
RL = 50
Ω
VL = 1.5 V
Figure 1A Figure 1B
5 pF
+5 V
OUTPUT
255
Ω
480
Ω
The table of timing values shows either a
minimum or a maximum limit for each parameter. Input requirements are specified from
the external system point of view. Thus, address setup time is shown as a minimum
since the system must supply at least that
much time (even though most devices do not
require it). On the other hand, responses from
the memory are specified from the device
point of view. Thus, the access time is shown
as a maximum since the device never provides data later than that time.
TIMING LIMITS
MCM6706R
4
MOTOROLA FAST SRAM
READ CYCLE 1 (See Note 7)
Q (DATA OUT)
A (ADDRESS)
PREVIOUS DATA VALID
t
AVAV
t
AXQX
t
AVQV
DATA VALID
READ CYCLE 2 (See Note 8)
E (CHIP ENABLE)
Q (DATA OUT)
A (ADDRESS)
G
(OUTPUT ENABLE)
t
AVQV
t
AVAV
t
ELQV
t
EHQZ
t
GHQZ
DATA VALID
t
GLQX
t
GLQV
t
ELQX
MCM6706R
5
MOTOROLA FAST SRAM
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
MCM6706R–6 MCM6706R–7 MCM6706R–8
Parameter Symbol Min Max Min Max Min Max Unit Notes
Write Cycle Time t
AVAV
6 — 7 — 8 — ns 3
Address Setup Time t
AVWL
0 — 0 — 0 — ns
Address Valid to End of Write t
AVWH
6 — 7 — 8 — ns
Write Pulse Width t
WLWH
,
t
WLEH
6 — 7 — 8 — ns
Data Valid to End of Write t
DVWH
3 — 3.5 — 4 — ns
Data Hold Time t
WHDX
0 — 0 — 0 — ns
Write Low to Data High–Z t
WLQZ
0 3.5 0 3.5 0 4 ns 4, 5, 6
Write High to Output Active t
WHQX
3 — 3 — 3 — ns 4, 5, 6
Write Recovery Time t
WHAX
0 — 0 — 0 — ns
NOTES:
1. A write occurs during the overlap of E
low and W low.
2. Product sensitivites to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady–state voltage with load of Figure 1B.
5. Parameter is sampled and not 100% tested.
6. At any given voltage and temperature, t
WLQZ
max is < t
WHQX
min both for a given device and from device to device.
WRITE CYCLE 1
Q (DATA OUT)
D (DATA IN)
W
(WRITE ENABLE)
E
(CHIP ENABLE)
A (ADDRESS)
DATA VALID
HIGH–Z
t
AVAV
t
WHDX
t
WHQX
HIGH–Z
t
WHAX
t
AVWH
t
WLQZ
t
AVWL
t
DVWH
t
WLWH
t
WLEH
MCM6706R
6
MOTOROLA FAST SRAM
WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
MCM6706R–6 MCM6706R–7 MCM6706R–8
Parameter Symbol Min Max Min Max Min Max Unit Notes
Write Cycle Time t
AVAV
6 — 7 — 8 — ns 3
Address Setup Time t
AVEL
0 — 0 — 0 — ns
Address Valid to End of Write t
AVEH
6 — 7 — 8 — ns
Chip Enable to End of Write t
ELWH
,
t
ELEH
5 — 6 — 7 — ns 4,5
Data Valid to End of Write t
DVEH
3 — 3.5 — 4 — ns
Data Hold Time t
EHDX
0 — 0 — 0 — ns
Write Recovery Time t
EHAX
0 — 0 — 0 — ns
NOTES:
1. A write occurs during the overlap of E
low and W low.
2. Product sensitivites to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All write cycle timing is referenced from the last valid address to the first transitioning address.
4. If E
goes low coincident with or after W goes low, the output will remain in a high impedance condition.
5. If E
goes high coincident with or before W goes high, the output will remain in a high impedance condition.
WRITE CYCLE 2
(WRITE ENABLE)
Q (DATA OUT)
D (DATA IN)
E
(CHIP ENABLE)
A (ADDRESS)
HIGH–Z
t
AVAV
DATA VALID
t
EHDX
t
DVEH
t
EHAX
t
ELWH
t
AVEH
t
AVEL
t
ELEH
ORDERING INFORMATION
(Order by Full Part Number)
Motorola Memory Prefix
Part Number
Package (J = 300 mil SOJ)
Full Part Numbers — MCM6706J6 MCM6706RJ7 MCM6706RJ8
MCM6706RJ6R2 MCM6706RJ7R2 MCM6706RJ8R2
Shipping Method (R2 = Tape and Reel, Blank = Rails)
Speed (6 = 6 ns, 7 = 7 ns, 8 = 8 ns)
MCM 6706R X XX XX
W
MCM6706R
7
MOTOROLA FAST SRAM
32–LEAD
300 MIL SOJ
CASE 857–02
PACKAGE DIMENSIONS
G
L
K
-A-
-X-
1
16
1732
M
F
D
P
-B-
E
C
R S
NOTE 3
NOTE 4
NOTE 5
NOTE 5
RADIUS
32 PL
32 PL
DETAIL Z
0.10 (0.004)
SEATING
PLANE
-T-
S S
0.25 (0.010) B
S S
0.17(0.007) B
S S
0.17(0.007) A
S S
0.17(0.007) A
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
A
B
C
D
E
F
G
K
L
N
P
R
S
20.83
7.50
3.26
0.41
2.24
0.67
0.89
0.76
8.38
6.60
0.77
21.08
7.74
3.75
0.50
2.48
0.81
1.14
1.14
8.64
6.86
1.01
0.820
0.295
0.128
0.016
0.088
0.026
0.035
0.030
0.330
0.260
0.030
0.830
0.305
0.148
0.020
0.098
0.032
0.045
0.045
0.340
0.270
0.040
1.27 BSC
0.64 BSC
0.050 BSC
0.025 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DATUM PLANE -X- LOCATED AT TOP OF MOLD
PARTING LINE AND COINCIDENT WITH TOP OF
LEAD, WHERE LEAD EXITS BODY.
4. TO BE DETERMINED AT PLANE -X-.
5. TO BE DETERMINED AT PLANE -T-.
6. DIMENSION A & B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
7. 857-01 IS OBSOLETE, NEW STANDARD 857-02.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters can and do vary in different
applications. All operating parameters, including “T ypicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MCM6706R
8
MOTOROLA FAST SRAM
Literature Distribution Centers:
USA/EUROPE: Motorola Literature Distribution; P .O. Box 20912; Phoenix, Arizona 85036.
JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan.
ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
MCM6706R/D
*MCM6706R/D*
◊
CODELINE TO BE PLACED HERE
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