Motorola MCM6706BRJ7, MCM6706BRJ7R, MCM6706BRJ8, MCM6706BRJ8R, MCM6706BRJ6 Datasheet
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MCM6706BR
1
MOTOROLA FAST SRAM
Product Preview
32K x 8 Bit Static Random
Access Memory
The MCM6706BR is a 262,144 bit static random access memory organized as
32,768 words of 8 bits. Static design eliminates the need for external clocks or
timing strobes.
Output enable (G
) is a special control feature that provides increased system
flexibility and eliminates bus contention problems.
The MCM6706BR meets JEDEC standards and is available in a revolutionary
pinout 300 mil, 32–lead surface–mount SOJ package.
• Single 5.0 V ± 10% Power Supply
• Fully Static — No Clock or Timing Strobes Necessary
• All Inputs and Outputs Are TTL Compatible
• Three State Outputs
• Fast Access Times: MCM6706BR–6 = 6 ns
MCM6706BR–7 = 7 ns
MCM6706BR–8 = 8 ns
• Center Power and I/O Pins for Reduced Noise
BLOCK DIAGRAM
ROW
DECODER
MEMORY
MATRIX
512 ROWS x 64 x 8
COLUMNS
INPUT
DATA
CONTROL
COLUMN I/O
COLUMN DECODER
A
A
A
A
A
A
A
A
D0
AA A
E
W
V
CC
V
SS
A
A A A
DQ
G
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
Order this document
by MCM6706BR/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
PIN ASSIGNMENT
MCM6706BR
J PACKAGE
300 MIL SOJ
CASE 857–02
32
31
30
29
28
27
26
25
24
23
22
21
2
3
1
5
6
4
7
9
10
8
12
13
11
14
20
15
16
19
18
17
A
A
A
E
A
W
A
A
A
V
CC
A
A
A
A
DQ
DQ
A
G
A
A
V
SS
V
CC
V
SS
DQ
DQ
ANC
NC
DQ
DQ
DQ
DQ
A Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
W
Write Enable. . . . . . . . . . . . . . . . . . . . . . . . .
E
Chip Enable. . . . . . . . . . . . . . . . . . . . . . . . . .
G
Output Enable. . . . . . . . . . . . . . . . . . . . . . .
DQ Data Input/Output. . . . . . . . . . . . . . . . . . .
V
CC
+ 5 V Power Supply. . . . . . . . . . . . . . . .
V
SS
Ground. . . . . . . . . . . . . . . . . . . . . . . . . . .
NC No Connection. . . . . . . . . . . . . . . . . . . . . .
PIN NAMES
REV 1
10/9/96
Motorola, Inc. 1996
MCM6706BR
2
MOTOROLA FAST SRAM
TRUTH TABLE
E G W Mode I/O Pin Cycle
H X X Not Selected High–Z —
L H H Read High–Z —
L L H Read D
out
Read Cycle
L X L Write D
in
Write Cycle
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating
Symbol Value Unit
Power Supply Voltage V
CC
– 0.5 to + 7.0 V
Voltage Relative to VSS for Any Pin
Except V
CC
Vin, V
out
– 0.5 to VCC + 0.5 V
Output Current I
out
± 30 mA
Power Dissipation P
D
2.0 W
Temperature Under Bias T
bias
– 10 to + 85 °C
Operating Temperature T
A
0 to + 70 °C
Storage Temperature — Plastic T
stg
– 55 to + 125 °C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC OPERA TING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Typ Max Unit
Supply Voltage (Operating Voltage Range) V
CC
4.5 5.0 5.5 V
Input High Voltage V
IH
2.2 —
VCC + 0.3*
V
Input Low Voltage V
IL
– 0.5**
— 0.8 V
*VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.
** VIL (min) = – 0.5 V dc @ 30.0 mA; VIL (min) = – 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.
DC CHARACTERISTICS
Parameter Symbol Min Max Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC) I
lkg(I)
— ± 1.0 µA
Output Leakage Current (E = VIH or G = VIH, V
out
= 0 to VCC) I
lkg(O)
— ± 1.0 µA
Output High Voltage (IOH = – 4.0 mA) V
OH
2.4 — V
Output Low Voltage (IOL = + 8.0 mA) V
OL
— 0.4 V
POWER SUPPLY CURRENTS
Parameter Symbol –6 –7 –8 Unit Notes
AC Active Supply Current (I
out
= 0 mA, VCC = max, f = f
max
) I
CCA
215 205 195 mA 1, 2, 3
AC Standby Current (E = VIH, VCC = max, f = f
max
) I
SB1
95 85 75 mA 1, 2, 3
CMOS Standby Current (VCC = max, f = 0 MHz,
E
≥ VCC – 0.2 V , Vin ≤ VSS, or ≥ VCC – 0.2 V)
I
SB2
20 20 20 mA
NOTES:
1. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V , VIH = 3.0 V).
2. All addresses transition simultaneously low (LSB) and then high (MSB).
3. Data states are all zero.
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid application of any voltage higher than maximum
rated voltages to this high–impedance circuit.
This BiCMOS memory circuit has been designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear feet
per minute is maintained.
MCM6706BR
3
MOTOROLA FAST SRAM
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T
A
= 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol Max Unit
Address Input Capacitance C
in
5 pF
Control Pin Input Capacitance (E, G, W) C
in
6 pF
I/O Capacitance C
out
6 pF
AC OPERA TING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .
Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time 2 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .
Output Load See Figure 1a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ CYCLE (See Notes 1 and 2)
6706BR–6 6706BR–7 6706BR–8
Parameter Symbol Min Max Min Max Min Max Unit Notes
Read Cycle Time t
AVAV
6 — 7 — 8 — ns 3
Address Access Time t
AVQV
— 6 — 7 — 8 ns
Chip Enable Access Time t
ELQV
— 6 — 7 — 8 ns
Output Enable Access Time t
GLQV
— 4 — 4 — 4 ns
Output Hold from Address Change t
AXQX
3 — 3 — 3 — ns
Chip Enable Low to Output Active t
ELQX
3 — 3 — 3 — ns 4 ,5, 6
Chip Enable High to Output High–Z t
EHQZ
— 3 — 3.5 — 3.5 ns 4, 5, 6
Output Enable Low to Output Active t
GLQX
0 — 0 — 0 — ns 4, 5, 6
Output Enable High to Output High–Z t
GHQZ
— 3 — 3.5 — 3.5 ns 4, 5, 6
NOTES:
1. W
is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All read cycle timing is referenced from the last valid address to the first transitioning address.
4. At any given voltage and temperature, t
EHQZ
max < t
ELQX
min, and t
GHQZ
max < t
GLQX
min, both for a given device and from
device to device.
5. Transition is measured 200 mV from steady–state voltage with load of Figure 1b.
6. This parameter is sampled and not 100% tested.
7. Device is continuously selected (E
= VIL, G = VIL).
8. Addresses valid prior to or coincident with E
going low.
OUTPUT
Z0 = 50
Ω
RL = 50
Ω
VL = 1.5 V
(a) (b)
5 pF
+5 V
OUTPUT
255
Ω
480
Ω
The table of timing values shows either a
minimum or a maximum limit for each parameter. Input requirements are specified from
the external system point of view. Thus, address setup time is shown as a minimum
since the system must supply at least that
much time. On the other hand, responses
from the memory are specified from the device point of view. Thus, the access time is
shown as a maximum since the device never
provides data later than that time.
TIMING LIMITS
Figure 1. AC Test Loads
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