Motorola MCM62486BFN11, MCM62486BFN12, MCM62486BFN14 Datasheet

MCM62486B

1

MOTOROLA FAST SRAM

32K x 9 Bit BurstRAM
Synchronous Static RAM

With Burst Counter and Self–Timed Write

The MCM62486B is a 294,912 bit synchronous static random access
memory designed to provide a burstable, high–performance, secondary cache
for the i486 and Pentium microprocessors. It is organized as 32,768 words of
9 bits, fabricated with Motorola’s high–performance silicon–gate CMOS
technology. The device integrates input registers, a 2–bit counter, high speed
SRAM, and high drive capability outputs onto a single monolithic circuit for re­duced parts count implementation of cache data RAM applications. Synchro­nous design allows precise cycle control with the use of an external clock (K).
CMOS circuitry reduces the overall power consumption of the integrated func­tions for greater reliability.

Addresses (A0 – A14), data inputs (D0 – D8), and all control signals except

output enable (G

) are clock (K) controlled through positive–edge–triggered

noninverting registers.

Bursts can be initiated with either address status processor (ADSP

) or address

status cache controller (ADSC

) input pins. Subsequent burst addresses can be
generated internally by the MCM62486B (burst sequence imitates that of the
i486 and Pentium) and controlled by the burst address advance (ADV

) input pin.

The following pages provide more detailed information on burst controls.

Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased flexibility for incoming signals.

The MCM62486B will be available in a 44–pin plastic leaded chip carrier
(PLCC). Multiple power and ground pins have been utilized to minimize effects
induced by output noise. Separate power and ground pins have been employed
for DQ0 – DQ8 to allow user–controlled output levels of 5 volts or 3.3 volts.

• Single 5 V ±

10% Power Supply (± 5% for MCM62486BFN11)

• Choice of 5 V or 3.3 V ± 10% Power Supplies for Output Level

Compatibility

• Fast Access Times:11/12/14/19 ns Max and Cycle Times:15/20/25 ns Min

• Internal Input Registers (Address, Data, Control)

• Internally Self–Timed Write Cycle

• ADSP

, ADSC, and ADV Burst Control Pins

• Asynchronous Output Enable Controlled Three–State Outputs

• Common Data Inputs and Data Outputs

• High Output Drive Capability: 85 pF per I/O

• High Board Density PLCC Package

• Fully TTL–Compatible

• Active High and Low Chip Select Inputs for Easy Depth Expansion

BurstRAM is a trademark of Motorola, Inc.
i486 and Pentium are trademarks of Intel Corp.

Order this document

by MCM62486B/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MCM62486B

PIN NAMES

PIN ASSIGNMENT

A11
A12
A13
A14

DQ7
DQ6

DQ5
DQ4

A2
A3
A4
A5
A6

DQ0
DQ1

DQ2

V

SS

V

SSQ

V

CCQ

V

SS

V

SSQ

V

CCQ

A1

A0

K

VCCA7A8A9

A10

DQ3VSSQ

V

CC

V

SS

W

G

S0

S1

DQ8VSSQ

ADV

ADSP

A0 – A14 Address Inputs. . . . . . . . . . . . . . . .

K Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

W Write Enable. . . . . . . . . . . . . . . . . . . . . . . .

G

Output Enable. . . . . . . . . . . . . . . . . . . . . .

S0, S1

Chip Selects. . . . . . . . . . . . . . . . . . . .

ADV

Burst Address Advance. . . . . . . . . . . .

ADSP

, ADSC Address Status. . . . . . . . . . . .

DQ0 – DQ8 Data Input/Output. . . . . . . . . . .

V

CC

+ 5 V Power Supply. . . . . . . . . . . . . . . .

V

CCQ

Output Buffer Power Supply. . . . . . .

V

SS

Ground. . . . . . . . . . . . . . . . . . . . . . . . . .

V

SSQ

Output Buffer Ground. . . . . . . . . . . .

All power supply and ground pins must be con­nected for proper operation of the device. VCC ≥
V

CCQ

at all times including power up.

6 5 4 3 2 1 44 43 42 41 40

10

9

8

12

11

15

14

13

17

16

7

32

33

29

30

31

35

36

34

37

38

39

18 19 20 21 22 23 24 25 26 27 28

V

SS

ADSC

REV 2
5/95

 Motorola, Inc. 1994

FN PACKAGE

44–LEAD PLCC

CASE 777–01

MCM62486B
2

MOTOROLA FAST SRAM

BLOCK DIAGRAM (See Note)

DQ0 – DQ8

S0

K

A0 – A14

W

S1

G

BINARY

COUNTER

CLR

Q0

Q1

A0

A1

ADDRESS

REGISTER

WRITE

REGISTER

ENABLE

REGISTER

DATA–IN

REGISTERS

OUTPUT
BUFFER

32K x 9

MEMORY

ARRAY

ADV

BURST LOGIC

INTERNAL

ADDRESS

A0

′

A1

′

15

9

9

15

2

A2 – A14

A1 – A0

ADSC
ADSP

9

NOTE: All registers are positive–edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the

next burst. When ADSP

is sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC) is per-

formed using the new external address. When ADSC

is sampled low (and ADSP is sampled high), any ongoing burst is

interrupted and a read or write (dependent on W

) is performed using the new external address. Chip selects (S0, S1) are

sampled only when a new base address is loaded. After the first cycle of the burst, ADV

controls subsequent burst cycles.

When ADV

is sampled low, the internal address is advanced prior to the operation. When ADV is sampled high, the internal
address is not advanced, thus inserting a wait state into the burst sequence accesses. Upon completion of a burst, the
address will wrap around to its initial state. See BURST SEQUENCE TABLE.

BURST SEQUENCE TABLE

(See Note)

External Address A14 – A2

A1 A0
1st Burst Address A14 – A2 A1 A0
2nd Burst Address A14 – A2 A1 A0
3rd Burst Address A14 – A2 A1 A0

NOTE: The burst wraps around to its initial state upon completion.

MCM62486B

3

MOTOROLA FAST SRAM

SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, 3, and 4)

S

ADSP ADSC ADV W K Address Used Operation

F L X X X L–H N/A Deselected
F X L X X L–H N/A Deselected
T L X X X L–H External Address Read Cycle, Begin Burst
T H L X L L–H External Address Write Cycle, Begin Burst
T H L X H L–H External Address Read Cycle, Begin Burst
X H H L L L–H Next Address Write Cycle, Continue Burst
X H H L H L–H Next Address Read Cycle, Continue Burst
X H H H L L–H Current Address Write Cycle, Suspend Burst
X H H H H L–H Current Address Read Cycle, Suspend Burst

NOTES:

1. X means Don’t Care.

2. All inputs except G

must meet setup and hold times for the low–to–high transition of clock (K).

3. S represents S0 and S1

. T implies S1 = L and S0 = H; F implies S1 = H or S0 = L.

4. Wait states are inserted by suspending burst.

ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)

Operation

G I/O Status

Read L Data Out (DQ0 – DQ8)
Read H High–Z

Write X High–Z — Data In (DQ0 – DQ8)

Deselected X High–Z

NOTES:

1. X means Don’t Care.

2. For a write operation following a read operation, G

must be high before the input data

required setup time and held high through the input data hold time.

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V

SS

= 0)

Rating

Symbol Value Unit

Power Supply Voltage V

CC

– 0.5 to 7.0 V

Output Power Supply Voltage V

CCQ

– 0.5 to V

CC

V

Voltage Relative to V

SS

Vin, V

out

– 0.5 to VCC + 0.5 V

Output Current (per I/O) I

out

± 20 mA

Power Dissipation P

D

1.0 W

Temperature Under Bias T

bias

– 10 to + 85 °C

Operating Temperature T

A

0 to + 70 °C

Storage Temperature T

stg

– 55 to + 125 °C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to RECOMMENDED OPER­ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is ad­vised that normal precautions be taken to avoid
application of any voltage higher than maxi­mum rated voltages to this high–impedance
circuit.

This CMOS memory circuit has been de­signed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.

MCM62486B
4

MOTOROLA FAST SRAM

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC, V

CCQ

= 5.0 V ± 5%, TA = 0 to + 70°C, for device MCM62486B–11)

(VCC = 5.0 V ± 10%, V

CCQ

= 5.0 V or 3.3 V ± 10%, TA = 0 to + 70°C, for all other devices)

RECOMMENDED OPERATING CONDITIONS

(Voltages referenced to VSS = 0 V)

Parameter

Symbol Min Max Unit

Supply Voltage (Operating Voltage Range) V

CC

4.5 5.5 V

Output Buffer Supply Voltage

(5.0 V TTL Compatible)
(3.3 V 50 Ω Compatible)

V

CCQ

4.5

3.0

5.5

3.6

V

Input High Voltage V

IH

2.2 VCC + 0.3 V

Input Low Voltage V

IL

– 0.5*

0.8 V

*VIL (min) = – 3.0 V ac (pulse width ≤ 20 ns)

DC CHARACTERISTICS

Parameter Symbol Min Max Unit

Input Leakage Current (All Inputs, Vin = 0 to VCC) I

lkg(I)

— ± 1.0 µA

Output Leakage Current (G, S1 = VIH, S0 = VIL, V

out

= 0 to V

CCQ

) I

lkg(O)

— ± 1.0 µA

AC Supply Current (G, S1 = VIL, S0 = VIH, All Inputs = VIL = 0.0 V and VIH ≥ 3.0 V,

I

out

= 0 mA, Cycle Time ≥ t

KHKH

min)

I

CCA

— 160 mA

Standby Current (S1 = VIH, S0 = VIL, All Inputs = VIL and VIH, Cycle Time ≥ t

KHKH

min) I

SB1

— 50 mA

Output Low Voltage (IOL = + 8.0 mA) V

OL

— 0.4 V

Output High Voltage (IOH = – 4.0 mA) V

OH

2.4 — V

NOTE: Good decoupling of the local power supply should always be used. DC characteristics are guaranteed for all possible i486 and Pentium

bus cycles.

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

A

= 25°C, Periodically Sampled Rather Than 100% Tested)

Characteristic

Symbol Typ Max Unit

Input Capacitance (All Pins Except DQ0 – DQ8) C

in

2 3 pF

Input/Output Capacitance (DQ0 – DQ8) C

I/O

7 8 pF