Motorola MCM6227BJ25R2, MCM6227BJ35, MCM6227BJ35R2, MCM6227BWJ15, MCM6227BJ17 Datasheet
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1M x 1 Bit Static Random
Order this document
by MCM6227B/D
MCM6227B
Access Memory
The MCM6227B is a 1,048,576 bit static random–access memory organized
as 1,048,576 words of 1 bit. Static design eliminates the need for external clocks
or timing strobes while CMOS circuitry reduces power consumption and provides
for greater reliability .
The MCM6227B is each equipped with a chip enable (E
vides reduced system power requirements without degrading access time performance.
The MCM6227B is available in 300 mil and 400 mil, 28–lead surface–mount
SOJ packages.
• Single 5 V ± 10% Power Supply
• Fast Access Times: 15/17/20/25/35 ns
• Equal Address and Chip Enable Access Times
• Input and Output are TTL Compatible
• Three–State Output
• Low Power Operation: 1 15/110/105/100/95 mA Maximum, Active AC
BLOCK DIAGRAM
A
A
A
A
A
A
A
ROW
DECODER
MEMORY MATRIX
512 ROWS x
2048 x 1 COLUMNS
) pin. This feature pro-
CASE 810B–03
WJ PACKAGE
PIN ASSIGNMENT
1
A
A
2
3
A
A
4
5
A
6
A
NC
7
8
A
A
9
A
10
11
A
12
Q
13
W
V
14
SS
J PACKAGE
300 MIL SOJ
400 MIL SOJ
CASE 810–03
V
28
CC
A
27
A
26
A
25
A
24
A
23
A
22
NC*
21
A
20
19
A
18
A
17
A
16
D
15
E
A
A
D
E
W
REV 3
10/31/96
Motorola, Inc. 1994
MOTOROLA FAST SRAM
INPUT
DATA
CONTROL
COLUMN I/O
COLUMN DECODER
AAAAAA
A
AAA
A
PIN NAMES
A Address Inputs. . . . . . . . . . . . . . . . . . . .
W
Q
E
D Data Input. . . . . . . . . . . . . . . . . . . . . . . .
Q Data Output. . . . . . . . . . . . . . . . . . . . .
NC No Connection. . . . . . . . . . . . . . . . . .
V
CC
V
SS
*If not used for no connect, then do not ex-
ceed voltages of – 0.5 to VCC + 0.5 V.
This pin is used for manufacturing diagnostics.
Write Enable. . . . . . . . . . . . . . . . . . . . .
Chip Enable. . . . . . . . . . . . . . . . . . . . . .
+ 5 V Power Supply. . . . . . . . . . . . .
Ground. . . . . . . . . . . . . . . . . . . . . . .
MCM6227B
1
TRUTH TABLE
E W Mode I/O Pin Cycle Current
H X Not Selected High–Z — I
L H Read D
L L Write High–Z Write I
H = High, L = Low, X = Don’t Care
out
Read I
SB1
, I
CCA
CCA
SB2
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating
Power Supply Voltage Relative to V
Voltage Relative to VSS for Any Pin
Except V
Output Current I
Power Dissipation P
Temperature Under Bias T
Operating Temperature T
Storage Temperature T
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
CC
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
SS
Symbol V alue Unit
V
CC
Vin, V
out
bias
stg
out
D
A
– 0.5 to 7.0 V
– 0.5 to VCC + 0.5 V
± 20
1.1 W
– 10 to + 85 °C
0 to + 70 °C
– 55 to + 150 °C
mA
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to these high–impedance
circuits.
This CMOS memory circuit has been designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear feet
per minute is maintained.
DC OPERA TING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Max Unit
Supply Voltage (Operating Voltage Range) V
Input High Voltage V
Input Low Voltage V
*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns).
**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width ≤ 20 ns).
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter Symbol Min Max Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC) I
Output Leakage Current (E = VIH, V
AC Active Supply Current (I
AC Standby Current (VCC = max, E = VIH, f ≤ f
CMOS Standby Current (E ≥ VCC – 0.2 V, Vin ≤ VSS + 0.2 V
or ≥ VCC – 0.2 V, VCC = max, f = 0 MHz)
Output Low Voltage (IOL = + 8.0 mA) V
Output High Voltage (IOH = – 4.0 mA) V
out
= 0 to VCC) I
out
= 0 mA, VCC = max)
max
)
MCM6227B–15: t
MCM6227B–17: t
MCM6227B–20: t
MCM6227B–25: t
MCM6227B–35: t
MCM6227B–15: t
MCM6227B–17: t
MCM6227B–20: t
MCM6227B–25: t
MCM6227B–35: t
AVAV
AVAV
AVAV
AVAV
AVAV
AVAV
AVAV
AVAV
AVAV
AVAV
= 15 ns
= 17 ns
= 20 ns
= 25 ns
= 35 ns
= 15 ns
= 17 ns
= 20 ns
= 25 ns
= 35 ns
CC
IH
IL
lkg(I)
lkg(O)
I
CCA
I
SB1
I
SB2
OL
OH
4.5 5.5 V
2.2 VCC +0.3** V
– 0.5* 0.8 V
— ± 1 µA
— ± 1 µA
—
—
—
—
—
—
—
—
—
—
— 5 mA
— 0.4 V
2.4 — V
115
110
105
100
95
40
35
30
25
20
mA
mA
MCM6227B
2
MOTOROLA FAST SRAM
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T
Input Capacitance All Inputs Except Clocks and D, Q
Input and Output Capacitance D, Q Cin, C
= 25°C, Periodically Sampled Rather Than 100% Tested)
A
Characteristic
E
and W
Symbol Typ Max Unit
C
in
out
4
5
5 8 pF
6
8
AC OPERA TING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time 2 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .
READ CYCLE TIMING (See Notes 1 and 2)
6227B–15 6227B–17 6227B–20 6227B–25 6227B–35
Parameter Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes
Read Cycle Time t
Address Access Time t
Enable Access Time t
Output Hold from
Address Change
Enable Low to Output
Active
Enable High to Output
High–Z
NOTES:
1. W
is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles.
3. All timings are referenced from the last valid address to the first transitioning address.
4. Addresses valid prior to or coincident with E
5. At any given voltage and temperature, t
6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b.
7. This parameter is sampled and not 100% tested.
8. Device is continuously selected (E
AVAV
AVQV
ELQV
t
AXQX
t
ELQX
t
EHQZ
15 — 17 — 20 — 25 — 35 — ns 2, 3
— 15 — 17 — 20 — 25 — 35 ns
— 15 — 17 — 20 — 25 — 35 ns 4
5 — 5 — 5 — 5 — 5 — ns
5 — 5 — 5 — 5 — 5 — ns 5, 6, 7
— 6 — 7 — 7 — 8 — 8 ns 5, 6, 7
going low.
max is less than t
EHQZ
≤ VIL).
Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .
Output Load See Figure 1a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
min, both for a given device and from device to device.
ELQX
pF
OUTPUT
Z0 = 50
Ω
(a) (b)
MOTOROLA FAST SRAM
RL = 50
VL = 1.5 V
Ω
OUTPUT
255
Ω
Figure 1. AC Test Loads
+ 5 V
480
5 pF
TIMING LIMITS
The table of timing values shows either a
minimum or a maximum limit for each param-
Ω
eter. Input requirements are specified from
the external system point of view. Thus, address setup time is shown as a minimum
since the system must supply at least that
much time. On the other hand, responses
from the memory are specified from the device point of view. Thus, the access time is
shown as a maximum since the device never
provides data later than that time.
MCM6227B
3
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